rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

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Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_91( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_92( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_225( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Periphery.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.experimental.{noPrefix, IntParam} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} import freechips.rocketchip.jtag.JTAGIO import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget} import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg} import freechips.rocketchip.util.BooleanToAugmentedBoolean /** Protocols used for communicating with external debugging tools / sealed trait DebugExportProtocol case object DMI extends DebugExportProtocol case object JTAG extends DebugExportProtocol case object CJTAG extends DebugExportProtocol case object APB extends DebugExportProtocol /* Options for possible debug interfaces / case class DebugAttachParams( protocols: Set[DebugExportProtocol] = Set(DMI), externalDisable: Boolean = false, masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = CBUS ) { def dmi = protocols.contains(DMI) def jtag = protocols.contains(JTAG) def cjtag = protocols.contains(CJTAG) def apb = protocols.contains(APB) } case object ExportDebug extends Field(DebugAttachParams()) class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) { val clock = Clock() val reset = Reset() } class DebugIO(implicit val p: Parameters) extends Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO())) val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO) val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32)))) //------------------------------ val ndreset = Output(Bool()) val dmactive = Output(Bool()) val dmactiveAck = Input(Bool()) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool())) } class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO { } class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle { val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool()))) val hartIsInReset = Input(Vec(nComponents, Bool())) } /* Either adds a JTAG DTM to system, and exports a JTAG interface, * or exports the Debug Module Interface (DMI), or exports and hooks up APB, * based on a global parameter. / trait HasPeripheryDebug { this: BaseSubsystem => private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere) lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB")))))) val debugTLDomainOpt = p(DebugModuleKey).map { _ => val domain = ClockSinkNode(Seq(ClockSinkParameters())) domain := tlbus.fixedClockNode domain } lazy val debugOpt = p(DebugModuleKey).map { params => val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes)) tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ } tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) => slave := master } tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") { _ := TLWidthWidget(1) := sb2tl.node } } tlDM } val debugNode = debugOpt.map(_.intnode) val psd = InModuleBody { val psd = IO(new PSDIO) psd } val resetctrl = InModuleBody { debugOpt.map { debug => debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size)) debug.module.io.hartIsInReset := resetctrl.hartIsInReset resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }} resetctrl } } // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603 val debug = InModuleBody { noPrefix(debugOpt.map { debugmod => val debug = IO(new DebugIO) require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined), "You cannot have both DMI and JTAG interface in HasPeripheryDebug") require(!(debug.clockeddmi.isDefined && debug.apb.isDefined), "You cannot have both DMI and APB interface in HasPeripheryDebug") require(!(debug.systemjtag.isDefined && debug.apb.isDefined), "You cannot have both APB and JTAG interface in HasPeripheryDebug") debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg } (debug.apb zip apbDebugNodeOpt zip debugmod.module.io.apb_clock zip debugmod.module.io.apb_reset).foreach { case (((io, apb), c ), r) => apb.out(0)._1 <> io c:= io.clock r:= io.reset } debugmod.module.io.debug_reset := debug.reset debugmod.module.io.debug_clock := debug.clock debug.ndreset := debugmod.module.io.ctrl.ndreset debug.dmactive := debugmod.module.io.ctrl.dmactive debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}} // TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down" debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B } debug })} val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) } def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = { val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS \| x }) // force TMS high when debug is disabled dtm.io.jtag_clock := sj.jtag.TCK dtm.io.jtag_reset := sj.reset dtm.io.jtag_mfr_id := sj.mfr_id dtm.io.jtag_part_number := sj.part_number dtm.io.jtag_version := sj.version dtm.rf_reset := sj.reset debugOpt.map { outerdebug => outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK outerdebug.module.io.dmi.get.dmiReset := sj.reset } dtm } } /* BlackBox to export DMI interface / class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clk = Input(Clock()) val reset = Input(Bool()) val debug = new DMIIO val exit = Output(UInt(32.W)) }) def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = { io.clk := tbclk io.reset := tbreset dutio.dmi <> io.debug dutio.dmiClock := tbclk dutio.dmiReset := tbreset tbsuccess := io.exit === 1.U assert(io.exit < 2.U, " FAILED * (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimDTM.v") addResource("/csrc/SimDTM.cc") } /** BlackBox to export JTAG interface / class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val jtag = new JTAGIO(hasTRSTn = true) val enable = Input(Bool()) val init_done = Input(Bool()) val exit = Output(UInt(32.W)) }) def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = { dutio.TCK := io.jtag.TCK dutio.TMS := io.jtag.TMS dutio.TDI := io.jtag.TDI io.jtag.TDO := dutio.TDO io.clock := tbclock io.reset := tbreset io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.") io.init_done := init_done // Success is determined by the gdbserver // which is controlling this simulation. tbsuccess := io.exit === 1.U assert(io.exit < 2.U, " FAILED * (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimJTAG.v") addResource("/csrc/SimJTAG.cc") addResource("/csrc/remote_bitbang.h") addResource("/csrc/remote_bitbang.cc") } object Debug { def connectDebug( debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO], psdio: PSDIO, c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode())) (implicit p: Parameters): Unit = { connectDebugClockAndReset(debugOpt, c) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }} debugOpt.map { debug => debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } debug.systemjtag.foreach { sj => val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out) sj.reset := r.asAsyncReset sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) sj.version := p(JtagDTMKey).idcodeVersion.U(4.W) } debug.apb.foreach { apb => require(false, "No support for connectDebug for an APB debug connection.") } psdio.psd.foreach { _ <> psd } debug.disableDebug.foreach { x => x := false.B } } } def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { debugOpt.foreach { debug => val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) \| debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) \| debug.apb.map(_.reset.asBool).getOrElse(false.B) connectDebugClockHelper(debug, dmi_reset, c, sync) } } def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { val debug_reset = Wire(Bool()) withClockAndReset(c, dmi_reset) { val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset debug_reset := debug_reset_syncd } // Need to clock DM during debug_reset because of synchronous reset, so keep // the clock alive for one cycle after debug_reset asserts to action this behavior. // The unit should also be clocked when dmactive is high. withClockAndReset(c, debug_reset.asAsyncReset) { val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive val clock_en = RegNext(next=dmactiveAck, init=true.B) val gated_clock = if (!p(DebugModuleKey).get.clockGate) c else ClockGate(c, clock_en, "debug_clock_gate") debug.clock := gated_clock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset) debug.dmactiveAck := dmactiveAck } } def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = { psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } ) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }} debugOpt.map { debug => debug.clock := true.B.asClock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset) debug.systemjtag.foreach { sj => sj.jtag.TCK := true.B.asClock sj.jtag.TMS := true.B sj.jtag.TDI := true.B sj.jtag.TRSTn.foreach { r => r := true.B } sj.reset := true.B.asAsyncReset sj.mfr_id := 0.U sj.part_number := 0.U sj.version := 0.U } debug.clockeddmi.foreach { d => d.dmi.req.valid := false.B d.dmi.req.bits.addr := 0.U d.dmi.req.bits.data := 0.U d.dmi.req.bits.op := 0.U d.dmi.resp.ready := true.B d.dmiClock := false.B.asClock d.dmiReset := true.B.asAsyncReset } debug.apb.foreach { apb => apb.clock := false.B.asClock apb.reset := true.B.asAsyncReset apb.pready := false.B apb.pslverr := false.B apb.prdata := 0.U apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser)) apb.psel := false.B apb.penable := false.B } debug.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } debug.disableDebug.foreach { x => x := false.B } debug.dmactiveAck := false.B debug.ndreset }.getOrElse(false.B) } } File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating \|\| enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode := clockNamePrefixer := aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * / case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) \|\| (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /* UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit / class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get \|\| !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy \|\| txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get \|\| errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) \|\| (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /* Parameterization of the memory-side bus created for each memory channel / case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /* Wrapper for creating TL nodes from a bus connected to the back of each mem channel / class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :=* TLFIFOFixer(TLFIFOFixer.all) := _.node) .getOrElse(xbar.node := TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() := xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File CanHaveClockTap.scala: package chipyard.clocking import chisel3._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ case object ClockTapKey extends Field[Boolean](true) trait CanHaveClockTap { this: BaseSubsystem => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO") val clockTapNode = Option.when(p(ClockTapKey)) { val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) clockTap := ClockGroup() := allClockGroupsNode clockTap } val clockTapIO = clockTapNode.map { node => InModuleBody { val clock_tap = IO(Output(Clock())) clock_tap := node.in.head._1.clock clock_tap }} } File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node := _.node).getOrElse(fixer.node) (out_xbar.node := fixer_node := TLBuffer(pa.buffer) := (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) := TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) := in_xbar.node) } .getOrElse { TLXbar() := fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File BankedCoherenceParams.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.BuiltInDevices import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.interrupts.IntOutwardNode import freechips.rocketchip.tilelink.{ TLBroadcast, HasTLBusParams, BroadcastFilter, TLBusWrapper, TLBusWrapperInstantiationLike, TLJbar, TLEdge, TLOutwardNode, TLTempNode, TLInwardNode, BankBinder, TLBroadcastParams, TLBroadcastControlParams, TLBuffer, TLFragmenter, TLNameNode } import freechips.rocketchip.util.Location import CoherenceManagerWrapper._ /** Global cache coherence granularity, which applies to all caches, for now. / case object CacheBlockBytes extends Field[Int](64) /* LLC Broadcast Hub configuration / case object BroadcastKey extends Field(BroadcastParams()) case class BroadcastParams( nTrackers: Int = 4, bufferless: Boolean = false, controlAddress: Option[BigInt] = None, filterFactory: TLBroadcast.ProbeFilterFactory = BroadcastFilter.factory) /* Coherence manager configuration / case object SubsystemBankedCoherenceKey extends Field(BankedCoherenceParams()) case class ClusterBankedCoherenceKey(clusterId: Int) extends Field(BankedCoherenceParams(nBanks=0)) case class BankedCoherenceParams( nBanks: Int = 1, coherenceManager: CoherenceManagerInstantiationFn = broadcastManager ) { require (isPow2(nBanks) \|\| nBanks == 0) } case class CoherenceManagerWrapperParams( blockBytes: Int, beatBytes: Int, nBanks: Int, name: String, dtsFrequency: Option[BigInt] = None) (val coherenceManager: CoherenceManagerInstantiationFn) extends HasTLBusParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = { val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context)) cmWrapper.suggestName(loc.name + "_wrapper") cmWrapper.halt.foreach { context.anyLocationMap += loc.halt(_) } context.tlBusWrapperLocationMap += (loc -> cmWrapper) cmWrapper } } class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) { val (tempIn, tempOut, halt) = params.coherenceManager(context) private val coherent_jbar = LazyModule(new TLJbar) def busView: TLEdge = coherent_jbar.node.edges.out.head val inwardNode = tempIn := coherent_jbar.node val builtInDevices = BuiltInDevices.none val prefixNode = None private def banked(node: TLOutwardNode): TLOutwardNode = if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) := node } val outwardNode = banked(tempOut) } object CoherenceManagerWrapper { type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode]) def broadcastManagerFn( name: String, location: HierarchicalLocation, controlPortsSlaveWhere: TLBusWrapperLocation ): CoherenceManagerInstantiationFn = { context => implicit val p = context.p val cbus = context.locateTLBusWrapper(controlPortsSlaveWhere) val BroadcastParams(nTrackers, bufferless, controlAddress, filterFactory) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(TLBroadcastParams( lineBytes = p(CacheBlockBytes), numTrackers = nTrackers, bufferless = bufferless, control = controlAddress.map(x => TLBroadcastControlParams(AddressSet(x, 0xfff), cbus.beatBytes)), filterFactory = filterFactory))) bh.suggestName(name) bh.controlNode.foreach { _ := cbus.coupleTo(s"${name}_ctrl") { TLBuffer(1) := TLFragmenter(cbus) := _ } } bh.intNode.foreach { context.ibus.fromSync := _ } (bh.node, bh.node, None) } val broadcastManager = broadcastManagerFn("broadcast", InSystem, CBUS) val incoherentManager: CoherenceManagerInstantiationFn = { _ => val node = TLNameNode("no_coherence_manager") (node, node, None) } } File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /* Entry point for Config-uring the presence of Tiles / case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /* List of HierarchicalLocations which might contain a Tile / case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /* For determining static tile id / case object NumTiles extends Field[Int](0) /* Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. / case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /* Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. / case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /* Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. / case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /* These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. / trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /* tileHartIdNode is used to collect publishers and subscribers of hartids. / val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. / val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix \| totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /* tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. / val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. / val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /* tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. / val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) := tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. / val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) := tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. / trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /* Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. / trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /* Narrow waist through which all tiles are intended to pass while being instantiated. / def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /* A default set of connections that need to occur for most tile types / def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /* Connect the port where the tile is the master to a TileLink interconnect. / def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus := crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. / def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) := crossingParams.slave.injectNode(context) := TLWidthWidget(controlBus.beatBytes) := bus } } } /** Connect the various interrupts sent to and and raised by the tile. / def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /* Notifications of tile status are connected to be broadcast without needing to be clock-crossed. / def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode := domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. / def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /* Connect power/reset/clock resources. / def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing \| _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /* Function to handle all trace crossings when tile is instantiated inside domains / def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) := traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File BusWrapper.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding} // TODO This class should be moved to package subsystem to resolve // the dependency awkwardness of the following imports import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices} import freechips.rocketchip.prci.{ ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode, FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain, ClockGroupEphemeralNode, asyncMux, ClockCrossingType, NoCrossing } import freechips.rocketchip.subsystem.{ HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations, CanInstantiateWithinContextThatHasTileLinkLocations } import freechips.rocketchip.util.Location /** Specifies widths of various attachement points in the SoC / trait HasTLBusParams { def beatBytes: Int def blockBytes: Int def beatBits: Int = beatBytes 8 def blockBits: Int = blockBytes * 8 def blockBeats: Int = blockBytes / beatBytes def blockOffset: Int = log2Up(blockBytes) def dtsFrequency: Option[BigInt] def fixedClockOpt = dtsFrequency.map(f => ClockParameters(freqMHz = f.toDouble / 1000000.0)) require (isPow2(beatBytes)) require (isPow2(blockBytes)) } abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters) extends ClockDomain with HasTLBusParams with CanHaveBuiltInDevices { private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups") private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true }) val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here val clockNode = clockGroup.node val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt))) clockGroup.node := clockGroupAggregator.node fixedClockNode := clockGroup.node // first member of group is always domain's own clock clockSinkNode := fixedClockNode InModuleBody { // make sure the above connections work properly because mismatched-by-name signals will just be ignored. (clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) => require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}") } } def clockBundle = clockSinkNode.in.head._1 def beatBytes = params.beatBytes def blockBytes = params.blockBytes def dtsFrequency = params.dtsFrequency val dtsClk = fixedClockNode.fixedClockResources(s"${busName}_clock").flatten.headOption /* If you violate this requirement, you will have a rough time. * The codebase is riddled with the assumption that this is true. / require(blockBytes >= beatBytes) def inwardNode: TLInwardNode def outwardNode: TLOutwardNode def busView: TLEdge def prefixNode: Option[BundleBridgeNode[UInt]] def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers) def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing")) def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing")) def generateSynchronousDomain(domainName: String): ClockSinkDomain = { val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName))) domain.clockNode := fixedClockNode domain } def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("") protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W))) def to[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_to_${name}", s"TLInterconnectCoupler_${busName}_to_${name}") { body } } } def from[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_from_${name}", s"TLInterconnectCoupler_${busName}_from_${name}") { body } } } def coupleTo[T](name: String)(gen: TLOutwardNode => T): T = to(name) { gen(TLNameNode("tl") :=* outwardNode) } def coupleFrom[T](name: String)(gen: TLInwardNode => T): T = from(name) { gen(inwardNode := TLNameNode("tl")) } def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleTo(s"bus_named_${bus.busName}") { bus.crossInHelper(xType) := TLWidthWidget(beatBytes) := _ } } def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleFrom(s"bus_named_${bus.busName}") { _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType) } } } trait TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper } trait TLBusWrapperConnectionLike { val xType: ClockCrossingType def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit } object TLBusWrapperConnection { /** Backwards compatibility factory for master driving clock and slave setting cardinality / def crossTo( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(true), nodeBinding: NodeBinding = BIND_STAR, flipRendering: Boolean = false) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) } /* Backwards compatibility factory for slave driving clock and master setting cardinality / def crossFrom( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(false), nodeBinding: NodeBinding = BIND_QUERY, flipRendering: Boolean = true) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) } /* Factory for making generic connections between TLBusWrappers / def apply (xType: ClockCrossingType = NoCrossing, driveClockFromMaster: Option[Boolean] = None, nodeBinding: NodeBinding = BIND_ONCE, flipRendering: Boolean = false)( slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, inject: Parameters => TLNode = { _ => TLTempNode() }) = { new TLBusWrapperConnection( xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView, masterNodeView, inject) } } /* TLBusWrapperConnection is a parameterization of a connection between two TLBusWrappers. * It has the following serializable parameters: * - xType: What type of TL clock crossing adapter to insert between the buses. * The appropriate half of the crossing adapter ends up inside each bus. * - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode, * otherwise have either the master or the slave bus bind the other one's clockGroupNode, * assuming the inserted crossing type is not asynchronous. * - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection. * - flipRendering: fine-grained control of the graphML rendering of the connection. * If has the following non-serializable parameters: * - slaveNodeView: programmatic control of the specific attachment point within the slave bus. * - masterNodeView: programmatic control of the specific attachment point within the master bus. * - injectNode: programmatic injection of additional nodes into the middle of the connection. * The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s. / class TLBusWrapperConnection (val xType: ClockCrossingType, val driveClockFromMaster: Option[Boolean], val nodeBinding: NodeBinding, val flipRendering: Boolean) (slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, inject: Parameters => TLNode) extends TLBusWrapperConnectionLike { def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = { val masterTLBus = context.locateTLBusWrapper(master) val slaveTLBus = context.locateTLBusWrapper(slave) def bindClocks(implicit p: Parameters) = driveClockFromMaster match { case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode) case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode) case None => } def bindTLNodes(implicit p: Parameters) = nodeBinding match { case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_QUERY => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p) case BIND_STAR => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_FLEX => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) } if (flipRendering) { FlipRendering { implicit p => bindClocks(implicitly[Parameters]) slaveTLBus.from(s"bus_named_${masterTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } else { bindClocks(implicitly[Parameters]) masterTLBus.to (s"bus_named_${slaveTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } } class TLBusWrapperTopology( val instantiations: Seq[(Location[TLBusWrapper], TLBusWrapperInstantiationLike)], val connections: Seq[(Location[TLBusWrapper], Location[TLBusWrapper], TLBusWrapperConnectionLike)] ) extends CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations { def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } } } def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } } } } trait HasTLXbarPhy { this: TLBusWrapper => private val xbar = LazyModule(new TLXbar(nameSuffix = Some(busName))).suggestName(busName + "_xbar") override def shouldBeInlined = xbar.node.circuitIdentity def inwardNode: TLInwardNode = xbar.node def outwardNode: TLOutwardNode = xbar.node def busView: TLEdge = xbar.node.edges.in.head } case class AddressAdjusterWrapperParams( blockBytes: Int, beatBytes: Int, replication: Option[ReplicatedRegion], forceLocal: Seq[AddressSet] = Nil, localBaseAddressDefault: Option[BigInt] = None, policy: TLFIFOFixer.Policy = TLFIFOFixer.allVolatile, ordered: Boolean = true ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = { val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name)) aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> aaWrapper) aaWrapper } } class AddressAdjusterWrapper(params: AddressAdjusterWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val address_adjuster = params.replication.map { r => LazyModule(new AddressAdjuster(r, params.forceLocal, params.localBaseAddressDefault, params.ordered)) } private val viewNode = TLIdentityNode() val inwardNode: TLInwardNode = address_adjuster.map(_.node := TLFIFOFixer(params.policy) := viewNode).getOrElse(viewNode) def outwardNode: TLOutwardNode = address_adjuster.map(_.node).getOrElse(viewNode) def busView: TLEdge = viewNode.edges.in.head val prefixNode = address_adjuster.map { a => a.prefix := addressPrefixNexusNode addressPrefixNexusNode } val builtInDevices = BuiltInDevices.none override def shouldBeInlined = !params.replication.isDefined } case class TLJBarWrapperParams( blockBytes: Int, beatBytes: Int ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = { val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name)) jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> jbarWrapper) jbarWrapper } } class TLJBarWrapper(params: TLJBarWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val jbar = LazyModule(new TLJbar) val inwardNode: TLInwardNode = jbar.node val outwardNode: TLOutwardNode = jbar.node def busView: TLEdge = jbar.node.edges.in.head val prefixNode = None val builtInDevices = BuiltInDevices.none override def shouldBeInlined = jbar.node.circuitIdentity } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Scratchpad.scala: package testchipip.soc import chisel3._ import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.resources.{DiplomacyUtils} import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters} import scala.collection.immutable.{ListMap} case class BankedScratchpadParams( base: BigInt, size: BigInt, busWhere: TLBusWrapperLocation = SBUS, banks: Int = 4, subBanks: Int = 2, name: String = "banked-scratchpad", disableMonitors: Boolean = false, buffer: BufferParams = BufferParams.none, outerBuffer: BufferParams = BufferParams.none, dtsEnabled: Boolean = false ) case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil) class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { val mask = (subBanks - 1) p(CacheBlockBytes) val xbar = TLXbar() (0 until subBanks).map { sb => val ram = LazyModule(new TLRAM( address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask), beatBytes = beatBytes, devOverride = Some(devOverride)) { override lazy val desiredName = s"TLRAM_ScratchpadBank" }) ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar } override lazy val desiredName = "ScratchpadBank" } trait CanHaveBankedScratchpad { this: BaseSubsystem => p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) => val bus = locateTLBusWrapper(params.busWhere) require (params.subBanks >= 1) val name = params.name val banks = params.banks val bankStripe = p(CacheBlockBytes)params.subBanks val mask = (params.banks-1)bankStripe val device = new MemoryDevice { override def describe(resources: ResourceBindings): Description = { Description(describeName("memory", resources), ListMap( "reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList, "device_type" -> Seq(ResourceString("memory")), "status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled")) )) } } def genBanks()(implicit p: Parameters) = (0 until banks).map { b => val bank = LazyModule(new ScratchpadBank( params.subBanks, AddressSet(params.base + bankStripe * b, params.size - 1 - mask), bus.beatBytes, device, params.buffer)) bank.clockNode := bus.fixedClockNode bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ } } if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks() } } File ClockGroupCombiner.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ object ClockGroupCombiner { def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = { LazyModule(new ClockGroupCombiner()).node } } case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil) // All clock groups with a name containing any substring in names will be combined into a single clock group class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])) extends Config((site, here, up) => { case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) => (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n))) } }) /* This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey * The ClockGroupCombinersKey contains a list of tuples of: * - The name of the combined group * - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node * This node will fail if * - Multiple grouping functions match a single clock group * - A grouping function matches zero clock groups * - A grouping function matches clock groups with different requested frequncies / class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule { val combiners = p(ClockGroupCombinerKey) val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m } val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u => var i = 0 val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) => val (g, r) = rest.partition(c(_)) val name = combiners(i)._1 i = i + 1 require(g.size >= 1) val names = g.map(_.name.getOrElse("unamed")) val takes = g.map(_.take).flatten require(takes.distinct.size <= 1, s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}") require(takes.size > 0, s"Clock group '$name' has no inheritable frequencies") (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r) } ClockGroupSinkParameters( name = u.name, members = grouped ++ rest ) } val node = ClockGroupAdapterNode(sourceFn, sinkFn) lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, oe), (i, ie)) => { val inMap = (i.member.data zip ie.sink.members).map { case (id, im) => im.name.get -> id }.toMap (o.member.data zip oe.sink.members).map { case (od, om) => val matches = combiners.filter(c => c._2(om)) require(matches.size <= 1) if (matches.size == 0) { od := inMap(om.name.get) } else { od := inMap(matches(0)._1) } } } } } } File SinkNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, IO} import org.chipsalliance.diplomacy.ValName /* A node which represents a node in the graph which has only inward edges, no outward edges. * * A [[SinkNode]] cannot appear cannot appear right of a `:=`, `:=`, `:=`, or `:=` * * There are no "Mixed" [[SinkNode]]s because each one only has an inward side. / class SinkNode[D, U, EO, EI, B <: Data]( imp: NodeImp[D, U, EO, EI, B] )(pi: Seq[U] )( implicit valName: ValName) extends MixedNode(imp, imp) { override def description = "sink" protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { def resolveStarInfo: String = s"""$context \|$bindingInfo \|number of known := bindings to inward nodes: $iKnown \|number of known := bindings to outward nodes: $oKnown \|number of binding queries from inward nodes: $iStars \|number of binding queries from outward nodes: $oStars \|${pi.size} inward parameters: [${pi.map(_.toString).mkString(",")}] \|""".stripMargin require( iStars <= 1, s"""Diplomacy has detected a problem with your graph: \|The following node appears left of a := $iStars times; at most once is allowed. \|$resolveStarInfo \|""".stripMargin ) require( oStars == 0, s"""Diplomacy has detected a problem with your graph: \|The following node cannot appear right of a :=* \|$resolveStarInfo \|""".stripMargin ) require( oKnown == 0, s"""Diplomacy has detected a problem with your graph: \|The following node cannot appear right of a := \|$resolveStarInfo \|""".stripMargin ) if (iStars == 0) require( pi.size == iKnown, s"""Diplomacy has detected a problem with your graph: \|The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. \|Either the number of inward := bindings should be exactly equal to the number of sink, or connect this node on the left-hand side of a := \|$resolveStarInfo \|""".stripMargin ) else require( pi.size >= iKnown, s"""Diplomacy has detected a problem with your graph: \|The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. \|To resolve :=, size of inward parameters can not be less than bindings. \|$resolveStarInfo \|""".stripMargin ) (pi.size - iKnown, 0) } protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq() protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi def makeIOs( )( implicit valName: ValName ): HeterogeneousBag[B] = { val bundles = this.in.map(_._1) val ios = IO(new HeterogeneousBag(bundles)) ios.suggestName(valName.value) bundles.zip(ios).foreach { case (bundle, io) => io <> bundle } ios } } File DigitalTop.scala: package chipyard import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // BOOM and/or Rocket Top Level Systems // ------------------------------------ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l) with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop File FrontBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams} import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy} import freechips.rocketchip.util.{Location} case class FrontBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = { val fbus = LazyModule(new FrontBus(this, loc.name)) fbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> fbus) fbus } } class FrontBus(params: FrontBusParams, name: String = "front_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) with HasTLXbarPhy { val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) val prefixNode = None } File PeripheryTLSerial.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.util.{ClockedIO} import testchipip.soc.{OBUS} // Parameters for a read-only-memory that appears over serial-TL case class ManagerROMParams( address: BigInt = 0x20000, size: Int = 0x10000, contentFileName: Option[String] = None) // If unset, generates a JALR to DRAM_BASE // Parameters for a read/write memory that appears over serial-TL case class ManagerRAMParams( address: BigInt, size: BigInt) // Parameters for a coherent cacheable read/write memory that appears over serial-TL case class ManagerCOHParams( address: BigInt, size: BigInt) // Parameters for a set of memory regions that appear over serial-TL case class SerialTLManagerParams( memParams: Seq[ManagerRAMParams] = Nil, romParams: Seq[ManagerROMParams] = Nil, cohParams: Seq[ManagerCOHParams] = Nil, isMemoryDevice: Boolean = false, sinkIdBits: Int = 8, totalIdBits: Int = 8, cacheIdBits: Int = 2, slaveWhere: TLBusWrapperLocation = OBUS ) // Parameters for a TL client which may probe this system over serial-TL case class SerialTLClientParams( totalIdBits: Int = 8, cacheIdBits: Int = 2, masterWhere: TLBusWrapperLocation = FBUS, supportsProbe: Boolean = false ) // The SerialTL can be configured to be bidirectional if serialTLManagerParams is set case class SerialTLParams( client: Option[SerialTLClientParams] = None, manager: Option[SerialTLManagerParams] = None, phyParams: SerialPhyParams = ExternalSyncSerialPhyParams(), bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS) case object SerialTLKey extends Field[Seq[SerialTLParams]](Nil) trait CanHavePeripheryTLSerial { this: BaseSubsystem => private val portName = "serial-tl" val tlChannels = 5 val (serdessers, serial_tls, serial_tl_debugs) = p(SerialTLKey).zipWithIndex.map { case (params, sid) => val name = s"serial_tl_$sid" lazy val manager_bus = params.manager.map(m => locateTLBusWrapper(m.slaveWhere)) lazy val client_bus = params.client.map(c => locateTLBusWrapper(c.masterWhere)) val clientPortParams = params.client.map { c => TLMasterPortParameters.v1( clients = Seq.tabulate(1 << c.cacheIdBits){ i => TLMasterParameters.v1( name = s"serial_tl_${sid}_${i}", sourceId = IdRange(i << (c.totalIdBits - c.cacheIdBits), (i + 1) << (c.totalIdBits - c.cacheIdBits)), supportsProbe = if (c.supportsProbe) TransferSizes(client_bus.get.blockBytes, client_bus.get.blockBytes) else TransferSizes.none )} )} val managerPortParams = params.manager.map { m => val memParams = m.memParams val romParams = m.romParams val cohParams = m.cohParams val memDevice = if (m.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil) val romDevice = new SimpleDevice("lbwif-readonly", Nil) val blockBytes = manager_bus.get.blockBytes TLSlavePortParameters.v1( managers = memParams.map { memParams => TLSlaveParameters.v1( address = AddressSet.misaligned(memParams.address, memParams.size), resources = memDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )} ++ romParams.map { romParams => TLSlaveParameters.v1( address = List(AddressSet(romParams.address, romParams.size-1)), resources = romDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), fifoId = Some(0) )} ++ cohParams.map { cohParams => TLSlaveParameters.v1( address = AddressSet.misaligned(cohParams.address, cohParams.size), regionType = RegionType.TRACKED, // cacheable executable = true, supportsAcquireT = TransferSizes(1, blockBytes), supportsAcquireB = TransferSizes(1, blockBytes), supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )}, beatBytes = manager_bus.get.beatBytes, endSinkId = if (cohParams.isEmpty) 0 else (1 << m.sinkIdBits), minLatency = 1 ) } val serial_tl_domain = LazyModule(new ClockSinkDomain(name=Some(s"SerialTL$sid"))) serial_tl_domain.clockNode := manager_bus.getOrElse(client_bus.get).fixedClockNode if (manager_bus.isDefined) require(manager_bus.get.dtsFrequency.isDefined, s"Manager bus ${manager_bus.get.busName} must provide a frequency") if (client_bus.isDefined) require(client_bus.get.dtsFrequency.isDefined, s"Client bus ${client_bus.get.busName} must provide a frequency") if (manager_bus.isDefined && client_bus.isDefined) { val managerFreq = manager_bus.get.dtsFrequency.get val clientFreq = client_bus.get.dtsFrequency.get require(managerFreq == clientFreq, s"Mismatching manager freq $managerFreq != client freq $clientFreq") } val serdesser = serial_tl_domain { LazyModule(new TLSerdesser( flitWidth = params.phyParams.flitWidth, clientPortParams = clientPortParams, managerPortParams = managerPortParams, bundleParams = params.bundleParams, nameSuffix = Some(name) )) } serdesser.managerNode.foreach { managerNode => val maxClients = 1 << params.manager.get.cacheIdBits val maxIdsPerClient = 1 << (params.manager.get.totalIdBits - params.manager.get.cacheIdBits) manager_bus.get.coupleTo(s"port_named_${name}_out") { (managerNode := TLProbeBlocker(p(CacheBlockBytes)) := TLSourceAdjuster(maxClients, maxIdsPerClient) := TLSourceCombiner(maxIdsPerClient) := TLWidthWidget(manager_bus.get.beatBytes) := _) } } serdesser.clientNode.foreach { clientNode => client_bus.get.coupleFrom(s"port_named_${name}_in") { _ := TLBuffer() := clientNode } } // If we provide a clock, generate a clock domain for the outgoing clock val serial_tl_clock_freqMHz = params.phyParams match { case params: InternalSyncSerialPhyParams => Some(params.freqMHz) case params: ExternalSyncSerialPhyParams => None case params: SourceSyncSerialPhyParams => Some(params.freqMHz) } val serial_tl_clock_node = serial_tl_clock_freqMHz.map { f => serial_tl_domain { ClockSinkNode(Seq(ClockSinkParameters(take=Some(ClockParameters(f))))) } } serial_tl_clock_node.foreach(_ := ClockGroup()(p, ValName(s"${name}_clock")) := allClockGroupsNode) val inner_io = serial_tl_domain { InModuleBody { val inner_io = IO(params.phyParams.genIO).suggestName(name) inner_io match { case io: InternalSyncPhitIO => { // Outer clock comes from the clock node. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = serial_tl_clock_node.get.in.head._1.clock io.clock_out := outer_clock val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(io.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: ExternalSyncPhitIO => { // Outer clock comes from the IO. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = io.clock_in val outer_reset = ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(params.phyParams.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: SourceSyncPhitIO => { // 3 clock domains - // - serdesser's "Inner clock": synchronizes signals going to the digital logic // - outgoing clock: synchronizes signals going out // - incoming clock: synchronizes signals coming in val outgoing_clock = serial_tl_clock_node.get.in.head._1.clock val outgoing_reset = ResetCatchAndSync(outgoing_clock, serdesser.module.reset.asBool) val incoming_clock = io.clock_in val incoming_reset = ResetCatchAndSync(incoming_clock, io.reset_in.asBool) io.clock_out := outgoing_clock io.reset_out := outgoing_reset.asAsyncReset val phy = Module(new CreditedSerialPhy(tlChannels, params.phyParams)) phy.io.incoming_clock := incoming_clock phy.io.incoming_reset := incoming_reset phy.io.outgoing_clock := outgoing_clock phy.io.outgoing_reset := outgoing_reset phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.inner_ser <> serdesser.module.io.ser phy.io.outer_ser <> io.viewAsSupertype(new ValidPhitIO(params.phyParams.phitWidth)) } } inner_io }} val outer_io = InModuleBody { val outer_io = IO(params.phyParams.genIO).suggestName(name) outer_io <> inner_io outer_io } val inner_debug_io = serial_tl_domain { InModuleBody { val inner_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") inner_debug_io := serdesser.module.io.debug inner_debug_io }} val outer_debug_io = InModuleBody { val outer_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") outer_debug_io := inner_debug_io outer_debug_io } (serdesser, outer_io, outer_debug_io) }.unzip3 } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File SystemBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{ BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams } import freechips.rocketchip.tilelink.{ TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode, TLFIFOFixer, TLTempNode } import freechips.rocketchip.util.Location case class SystemBusParams( beatBytes: Int, blockBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = { val sbus = LazyModule(new SystemBus(this, loc.name)) sbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> sbus) sbus } } class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name))) val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode()) val outwardNode: TLOutwardNode = system_bus_xbar.node def busView: TLEdge = system_bus_xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File InterruptBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.{Device, DeviceInterrupts, Description, ResourceBindings} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain} import freechips.rocketchip.interrupts.IntClockDomainCrossing /** Collects interrupts from internal and external devices and feeds them into the PLIC / class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain { override def shouldBeInlined = true val int_bus = LazyModule(new IntXbar) // Interrupt crossbar private val int_in_xing = this.crossIn(int_bus.intnode) private val int_out_xing = this.crossOut(int_bus.intnode) def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) := IntNameNode(name) def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) := int_out_xing(xing) def fromAsync: IntInwardNode = from(None)(AsynchronousCrossing(8,3)) def fromRational: IntInwardNode = from(None)(RationalCrossing()) def fromSync: IntInwardNode = int_bus.intnode def toPLIC: IntOutwardNode = int_bus.intnode } /* Specifies the number of external interrupts / case object NExtTopInterrupts extends Field[Int](0) /* This trait adds externally driven interrupts to the system. * However, it should not be used directly; instead one of the below * synchronization wiring child traits should be used. / abstract trait HasExtInterrupts { this: BaseSubsystem => private val device = new Device with DeviceInterrupts { def describe(resources: ResourceBindings): Description = { Description("soc/external-interrupts", describeInterrupts(resources)) } } val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) } /* This trait should be used if the External Interrupts have NOT * already been synchronized to the Periphery (PLIC) Clock. / trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromAsync := extInterrupts } } } /* This trait can be used if the External Interrupts have already been synchronized * to the Periphery (PLIC) Clock. / trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromSync := extInterrupts } } } /* Common io name and methods for propagating or tying off the port bundle / trait HasExtInterruptsBundle { val interrupts: UInt def tieOffInterrupts(dummy: Int = 1): Unit = { interrupts := 0.U } } /* This trait performs the translation from a UInt IO into Diplomatic Interrupts. * The wiring must be done in the concrete LazyModuleImp. */ trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle { val outer: HasExtInterrupts val interrupts = IO(Input(UInt(outer.nExtInterrupts.W))) outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) } } File BundleBridgeSink.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, IO, Output} import chisel3.reflect.DataMirror import chisel3.reflect.DataMirror.internal.chiselTypeClone import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.SinkNode case class BundleBridgeSink[T <: Data]( genOpt: Option[() => T] = None )( implicit valName: ValName) extends SinkNode(new BundleBridgeImp[T])(Seq(BundleBridgeParams(genOpt))) { def bundle: T = in(0)._1 private def inferOutput = getElements(bundle).forall { elt => DataMirror.directionOf(elt) == ActualDirection.Unspecified } def makeIO( )( implicit valName: ValName ): T = { val io: T = IO( if (inferOutput) Output(chiselTypeOf(bundle)) else chiselTypeClone(bundle) ) io.suggestName(valName.value) io <> bundle io } def makeIO(name: String): T = makeIO()(ValName(name)) } object BundleBridgeSink { def apply[T <: Data]( )( implicit valName: ValName ): BundleBridgeSink[T] = { BundleBridgeSink(None) } }	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [4:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [15:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1653 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1668 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1753 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_133( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_18( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_223( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter_173( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_6_ready, // @[SwitchAllocator.scala:18:14] input io_in_6_valid, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_7_ready, // @[SwitchAllocator.scala:18:14] input io_in_7_valid, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [7:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [7:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [7:0] unassigned = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, 2'h0} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}, :39:21, :41:24] reg [7:0] mask; // @[SwitchAllocator.scala:27:21] wire [7:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [15:0] sel = _sel_T_1[0] ? 16'h1 : _sel_T_1[1] ? 16'h2 : _sel_T_1[2] ? 16'h4 : _sel_T_1[3] ? 16'h8 : _sel_T_1[4] ? 16'h10 : _sel_T_1[5] ? 16'h20 : _sel_T_1[6] ? 16'h40 : _sel_T_1[7] ? 16'h80 : unassigned[0] ? 16'h100 : unassigned[1] ? 16'h200 : unassigned[2] ? 16'h400 : unassigned[3] ? 16'h800 : unassigned[4] ? 16'h1000 : unassigned[5] ? 16'h2000 : unassigned[6] ? 16'h4000 : {unassigned[7], 15'h0}; // @[OneHot.scala:85:71] wire [5:0] _GEN = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid}; // @[SwitchAllocator.scala:41:24] wire [7:0] chosen = (\|(_GEN & lock_0[7:2])) ? lock_0 : sel[7:0] \| sel[15:8]; // @[Mux.scala:50:70] wire [5:0] _io_out_0_valid_T = _GEN & chosen[7:2]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN_0 = io_out_0_ready & (\|_io_out_0_valid_T); // @[Decoupled.scala:51:35] wire [6:0] _GEN_1 = chosen[6:0] \| chosen[7:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_2 = _GEN_1[5:0] \| chosen[7:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_3 = _GEN_2[4:0] \| chosen[7:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_4 = _GEN_3[3:0] \| chosen[7:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_5 = _GEN_4[2:0] \| chosen[7:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_6 = _GEN_5[1:0] \| chosen[7:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 8'h0; // @[SwitchAllocator.scala:24:38] mask <= 8'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_0) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_7_bits_tail, ~io_in_6_bits_tail, ~io_in_5_bits_tail, ~io_in_4_bits_tail, ~io_in_3_bits_tail, ~io_in_2_bits_tail, 2'h3}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_0 ? {chosen[7], _GEN_1[6], _GEN_2[5], _GEN_3[4], _GEN_4[3], _GEN_5[2], _GEN_6[1], _GEN_6[0] \| chosen[7]} : (&mask) ? 8'h0 : {mask[6:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8*beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start }	module TLAtomicAutomata_ccbus0( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset // @[AtomicAutomata.scala:36:9] ); endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File TileResetSetter.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ // Currently only works if all tiles are already driven by independent clock groups // TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should // always put all tiles on independent clock groups class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("tile-reset-setter", Nil) val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) val clockNode = ClockGroupIdentityNode() lazy val module = new LazyModuleImp(this) { val nTiles = p(TilesLocated(InSubsystem)).size require (nTiles <= 4096 / 4) val tile_async_resets = Wire(Vec(nTiles, Reset())) val r_tile_resets = (0 until nTiles).map({ i => tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842 withReset (tile_async_resets(i)) { Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0))) } }) if (nTiles > 0) tlNode.regmap((0 until nTiles).map({ i => i 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) }): _) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream // to synchronize the resets // Also, this or enforces that the tiles come out of reset after the reset of the system oD.reset := (rOut.asBool \|\| iD.reset.asBool).asAsyncReset rIn := iD.reset } } } } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_64 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_tl_in_d_ready), .io_in_a_valid (auto_tl_in_a_valid), .io_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .io_in_a_bits_param (auto_tl_in_a_bits_param), .io_in_a_bits_size (auto_tl_in_a_bits_size), .io_in_a_bits_source (auto_tl_in_a_bits_source), .io_in_a_bits_address (auto_tl_in_a_bits_address), .io_in_a_bits_mask (auto_tl_in_a_bits_mask), .io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .io_in_d_ready (auto_tl_in_d_ready), .io_in_d_valid (auto_tl_in_a_valid), .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_tl_in_a_bits_size), .io_in_d_bits_source (auto_tl_in_a_bits_source) ); // @[Nodes.scala:27:25] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLBuffer_a32d64s5k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_13 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_user_amba_prot_privileged (auto_in_a_bits_user_amba_prot_privileged), .io_enq_bits_user_amba_prot_secure (auto_in_a_bits_user_amba_prot_secure), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_user_amba_prot_bufferable (auto_out_a_bits_user_amba_prot_bufferable), .io_deq_bits_user_amba_prot_modifiable (auto_out_a_bits_user_amba_prot_modifiable), .io_deq_bits_user_amba_prot_readalloc (auto_out_a_bits_user_amba_prot_readalloc), .io_deq_bits_user_amba_prot_writealloc (auto_out_a_bits_user_amba_prot_writealloc), .io_deq_bits_user_amba_prot_privileged (auto_out_a_bits_user_amba_prot_privileged), .io_deq_bits_user_amba_prot_secure (auto_out_a_bits_user_amba_prot_secure), .io_deq_bits_user_amba_prot_fetch (auto_out_a_bits_user_amba_prot_fetch), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_EntryData_35( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid \|\| valids.reduce(_\|\|_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }	module Pipeline_9( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_0_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_1_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_2_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_3_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_4_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_5_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_6_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_7_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_8_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_9_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_10_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_11_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_12_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_13_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_14_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_15_0, // @[Pipeline.scala:7:14] input io_in_bits_resp_fromDMA, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_scale_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_igelu_qb, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_igelu_qc, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_iexp_qln2, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_iexp_qln2_inv, // @[Pipeline.scala:7:14] input [2:0] io_in_bits_resp_act, // @[Pipeline.scala:7:14] input [1:0] io_in_bits_resp_acc_bank_id, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_0_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_1_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_2_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_3_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_4_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_5_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_6_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_7_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_8_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_9_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_10_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_11_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_12_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_13_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_14_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_15_0, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_0_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_1_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_2_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_3_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_4_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_5_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_6_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_7_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_8_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_9_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_10_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_11_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_12_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_13_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_14_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_15_0, // @[Pipeline.scala:7:14] output io_out_bits_resp_fromDMA, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_resp_acc_bank_id, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_0_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_1_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_2_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_3_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_4_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_5_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_6_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_7_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_8_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_9_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_10_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_11_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_12_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_13_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_14_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_15_0 // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_0_0_0 = io_in_bits_resp_data_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_1_0_0 = io_in_bits_resp_data_1_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_2_0_0 = io_in_bits_resp_data_2_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_3_0_0 = io_in_bits_resp_data_3_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_4_0_0 = io_in_bits_resp_data_4_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_5_0_0 = io_in_bits_resp_data_5_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_6_0_0 = io_in_bits_resp_data_6_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_7_0_0 = io_in_bits_resp_data_7_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_8_0_0 = io_in_bits_resp_data_8_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_9_0_0 = io_in_bits_resp_data_9_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_10_0_0 = io_in_bits_resp_data_10_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_11_0_0 = io_in_bits_resp_data_11_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_12_0_0 = io_in_bits_resp_data_12_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_13_0_0 = io_in_bits_resp_data_13_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_14_0_0 = io_in_bits_resp_data_14_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_15_0_0 = io_in_bits_resp_data_15_0; // @[Pipeline.scala:6:7] wire io_in_bits_resp_fromDMA_0 = io_in_bits_resp_fromDMA; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_scale_bits_0 = io_in_bits_resp_scale_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_igelu_qb_0 = io_in_bits_resp_igelu_qb; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_igelu_qc_0 = io_in_bits_resp_igelu_qc; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_iexp_qln2_0 = io_in_bits_resp_iexp_qln2; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_iexp_qln2_inv_0 = io_in_bits_resp_iexp_qln2_inv; // @[Pipeline.scala:6:7] wire [2:0] io_in_bits_resp_act_0 = io_in_bits_resp_act; // @[Pipeline.scala:6:7] wire [1:0] io_in_bits_resp_acc_bank_id_0 = io_in_bits_resp_acc_bank_id; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_0_0_0 = io_in_bits_full_data_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_1_0_0 = io_in_bits_full_data_1_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_2_0_0 = io_in_bits_full_data_2_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_3_0_0 = io_in_bits_full_data_3_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_4_0_0 = io_in_bits_full_data_4_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_5_0_0 = io_in_bits_full_data_5_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_6_0_0 = io_in_bits_full_data_6_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_7_0_0 = io_in_bits_full_data_7_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_8_0_0 = io_in_bits_full_data_8_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_9_0_0 = io_in_bits_full_data_9_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_10_0_0 = io_in_bits_full_data_10_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_11_0_0 = io_in_bits_full_data_11_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_12_0_0 = io_in_bits_full_data_12_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_13_0_0 = io_in_bits_full_data_13_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_14_0_0 = io_in_bits_full_data_14_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_15_0_0 = io_in_bits_full_data_15_0; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_4 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_5 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_6 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_7 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_7; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_0_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_1_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_2_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_3_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_4_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_5_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_6_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_7_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_8_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_9_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_10_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_11_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_12_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_13_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_14_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_15_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_scale_bits; // @[Pipeline.scala:6:7] wire io_out_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_igelu_qb; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_igelu_qc; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_iexp_qln2; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_iexp_qln2_inv; // @[Pipeline.scala:6:7] wire [2:0] io_out_bits_resp_act; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_0_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_1_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_2_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_3_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_4_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_5_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_6_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_7_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_8_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_9_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_10_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_11_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_12_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_13_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_14_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_15_0_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [31:0] stages_0_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_0_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_0_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_0_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_1_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_1_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_1_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_2_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_2_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_2_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_3_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_3_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_3_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_4_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_4_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_4_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_5_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_5_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_5_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_6_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_6_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_6_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_7_resp_data_0_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_0_0_0 = stages_7_resp_data_0_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_1_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_1_0_0 = stages_7_resp_data_1_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_2_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_2_0_0 = stages_7_resp_data_2_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_3_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_3_0_0 = stages_7_resp_data_3_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_4_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_4_0_0 = stages_7_resp_data_4_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_5_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_5_0_0 = stages_7_resp_data_5_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_6_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_6_0_0 = stages_7_resp_data_6_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_7_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_7_0_0 = stages_7_resp_data_7_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_8_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_8_0_0 = stages_7_resp_data_8_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_9_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_9_0_0 = stages_7_resp_data_9_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_10_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_10_0_0 = stages_7_resp_data_10_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_11_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_11_0_0 = stages_7_resp_data_11_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_12_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_12_0_0 = stages_7_resp_data_12_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_13_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_13_0_0 = stages_7_resp_data_13_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_14_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_14_0_0 = stages_7_resp_data_14_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_15_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_15_0_0 = stages_7_resp_data_15_0; // @[Pipeline.scala:6:7, :21:21] reg stages_7_resp_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_resp_fromDMA_0 = stages_7_resp_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_scale_bits; // @[Pipeline.scala:21:21] assign io_out_bits_resp_scale_bits = stages_7_resp_scale_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_igelu_qb; // @[Pipeline.scala:21:21] assign io_out_bits_resp_igelu_qb = stages_7_resp_igelu_qb; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_igelu_qc; // @[Pipeline.scala:21:21] assign io_out_bits_resp_igelu_qc = stages_7_resp_igelu_qc; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_iexp_qln2; // @[Pipeline.scala:21:21] assign io_out_bits_resp_iexp_qln2 = stages_7_resp_iexp_qln2; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] assign io_out_bits_resp_iexp_qln2_inv = stages_7_resp_iexp_qln2_inv; // @[Pipeline.scala:6:7, :21:21] reg [2:0] stages_7_resp_act; // @[Pipeline.scala:21:21] assign io_out_bits_resp_act = stages_7_resp_act; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_7_resp_acc_bank_id; // @[Pipeline.scala:21:21] assign io_out_bits_resp_acc_bank_id_0 = stages_7_resp_acc_bank_id; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_0_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_0_0_0 = stages_7_full_data_0_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_1_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_1_0_0 = stages_7_full_data_1_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_2_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_2_0_0 = stages_7_full_data_2_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_3_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_3_0_0 = stages_7_full_data_3_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_4_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_4_0_0 = stages_7_full_data_4_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_5_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_5_0_0 = stages_7_full_data_5_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_6_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_6_0_0 = stages_7_full_data_6_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_7_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_7_0_0 = stages_7_full_data_7_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_8_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_8_0_0 = stages_7_full_data_8_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_9_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_9_0_0 = stages_7_full_data_9_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_10_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_10_0_0 = stages_7_full_data_10_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_11_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_11_0_0 = stages_7_full_data_11_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_12_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_12_0_0 = stages_7_full_data_12_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_13_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_13_0_0 = stages_7_full_data_13_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_14_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_14_0_0 = stages_7_full_data_14_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_15_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_15_0_0 = stages_7_full_data_15_0; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] reg valids_4; // @[Pipeline.scala:22:25] reg valids_5; // @[Pipeline.scala:22:25] reg valids_6; // @[Pipeline.scala:22:25] reg valids_7; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_7; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T; // @[Pipeline.scala:30:16] wire _stalling_4_T; // @[Pipeline.scala:30:16] wire _stalling_5_T; // @[Pipeline.scala:30:16] wire _stalling_6_T; // @[Pipeline.scala:30:16] wire _stalling_7_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire stalling_4; // @[Pipeline.scala:23:27] wire stalling_5; // @[Pipeline.scala:23:27] wire stalling_6; // @[Pipeline.scala:23:27] wire stalling_7; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 \| valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T \| valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 \| valids_3; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_3 = _io_busy_T_2 \| valids_4; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_4 = _io_busy_T_3 \| valids_5; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_5 = _io_busy_T_4 \| valids_6; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_6 = _io_busy_T_5 \| valids_7; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_7 = io_in_valid_0 \| _io_busy_T_6; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_7; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_7_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_7_T_1 = valids_7 & _stalling_7_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_7 = _stalling_7_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_3_T = valids_3 & stalling_4; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_3 = _stalling_3_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_4_T = valids_4 & stalling_5; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_4 = _stalling_4_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_5_T = valids_5 & stalling_6; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_5 = _stalling_5_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_6_T = valids_6 & stalling_7; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_6 = _stalling_6_T; // @[Pipeline.scala:23:27, :30:16] wire _T_8 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_8) begin // @[Decoupled.scala:51:35] stages_0_resp_data_0_0 <= io_in_bits_resp_data_0_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_1_0 <= io_in_bits_resp_data_1_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_2_0 <= io_in_bits_resp_data_2_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_3_0 <= io_in_bits_resp_data_3_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_4_0 <= io_in_bits_resp_data_4_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_5_0 <= io_in_bits_resp_data_5_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_6_0 <= io_in_bits_resp_data_6_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_7_0 <= io_in_bits_resp_data_7_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_8_0 <= io_in_bits_resp_data_8_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_9_0 <= io_in_bits_resp_data_9_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_10_0 <= io_in_bits_resp_data_10_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_11_0 <= io_in_bits_resp_data_11_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_12_0 <= io_in_bits_resp_data_12_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_13_0 <= io_in_bits_resp_data_13_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_14_0 <= io_in_bits_resp_data_14_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_15_0 <= io_in_bits_resp_data_15_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_fromDMA <= io_in_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_scale_bits <= io_in_bits_resp_scale_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_igelu_qb <= io_in_bits_resp_igelu_qb_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_igelu_qc <= io_in_bits_resp_igelu_qc_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_iexp_qln2 <= io_in_bits_resp_iexp_qln2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_iexp_qln2_inv <= io_in_bits_resp_iexp_qln2_inv_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_act <= io_in_bits_resp_act_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_acc_bank_id <= io_in_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_0_0 <= io_in_bits_full_data_0_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_1_0 <= io_in_bits_full_data_1_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_2_0 <= io_in_bits_full_data_2_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_3_0 <= io_in_bits_full_data_3_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_4_0 <= io_in_bits_full_data_4_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_5_0 <= io_in_bits_full_data_5_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_6_0 <= io_in_bits_full_data_6_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_7_0 <= io_in_bits_full_data_7_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_8_0 <= io_in_bits_full_data_8_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_9_0 <= io_in_bits_full_data_9_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_10_0 <= io_in_bits_full_data_10_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_11_0 <= io_in_bits_full_data_11_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_12_0 <= io_in_bits_full_data_12_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_13_0 <= io_in_bits_full_data_13_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_14_0 <= io_in_bits_full_data_14_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_15_0 <= io_in_bits_full_data_15_0_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_resp_data_0_0 <= stages_0_resp_data_0_0; // @[Pipeline.scala:21:21] stages_1_resp_data_1_0 <= stages_0_resp_data_1_0; // @[Pipeline.scala:21:21] stages_1_resp_data_2_0 <= stages_0_resp_data_2_0; // @[Pipeline.scala:21:21] stages_1_resp_data_3_0 <= stages_0_resp_data_3_0; // @[Pipeline.scala:21:21] stages_1_resp_data_4_0 <= stages_0_resp_data_4_0; // @[Pipeline.scala:21:21] stages_1_resp_data_5_0 <= stages_0_resp_data_5_0; // @[Pipeline.scala:21:21] stages_1_resp_data_6_0 <= stages_0_resp_data_6_0; // @[Pipeline.scala:21:21] stages_1_resp_data_7_0 <= stages_0_resp_data_7_0; // @[Pipeline.scala:21:21] stages_1_resp_data_8_0 <= stages_0_resp_data_8_0; // @[Pipeline.scala:21:21] stages_1_resp_data_9_0 <= stages_0_resp_data_9_0; // @[Pipeline.scala:21:21] stages_1_resp_data_10_0 <= stages_0_resp_data_10_0; // @[Pipeline.scala:21:21] stages_1_resp_data_11_0 <= stages_0_resp_data_11_0; // @[Pipeline.scala:21:21] stages_1_resp_data_12_0 <= stages_0_resp_data_12_0; // @[Pipeline.scala:21:21] stages_1_resp_data_13_0 <= stages_0_resp_data_13_0; // @[Pipeline.scala:21:21] stages_1_resp_data_14_0 <= stages_0_resp_data_14_0; // @[Pipeline.scala:21:21] stages_1_resp_data_15_0 <= stages_0_resp_data_15_0; // @[Pipeline.scala:21:21] stages_1_resp_fromDMA <= stages_0_resp_fromDMA; // @[Pipeline.scala:21:21] stages_1_resp_scale_bits <= stages_0_resp_scale_bits; // @[Pipeline.scala:21:21] stages_1_resp_igelu_qb <= stages_0_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_1_resp_igelu_qc <= stages_0_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_1_resp_iexp_qln2 <= stages_0_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_1_resp_iexp_qln2_inv <= stages_0_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_1_resp_act <= stages_0_resp_act; // @[Pipeline.scala:21:21] stages_1_resp_acc_bank_id <= stages_0_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_1_full_data_0_0 <= stages_0_full_data_0_0; // @[Pipeline.scala:21:21] stages_1_full_data_1_0 <= stages_0_full_data_1_0; // @[Pipeline.scala:21:21] stages_1_full_data_2_0 <= stages_0_full_data_2_0; // @[Pipeline.scala:21:21] stages_1_full_data_3_0 <= stages_0_full_data_3_0; // @[Pipeline.scala:21:21] stages_1_full_data_4_0 <= stages_0_full_data_4_0; // @[Pipeline.scala:21:21] stages_1_full_data_5_0 <= stages_0_full_data_5_0; // @[Pipeline.scala:21:21] stages_1_full_data_6_0 <= stages_0_full_data_6_0; // @[Pipeline.scala:21:21] stages_1_full_data_7_0 <= stages_0_full_data_7_0; // @[Pipeline.scala:21:21] stages_1_full_data_8_0 <= stages_0_full_data_8_0; // @[Pipeline.scala:21:21] stages_1_full_data_9_0 <= stages_0_full_data_9_0; // @[Pipeline.scala:21:21] stages_1_full_data_10_0 <= stages_0_full_data_10_0; // @[Pipeline.scala:21:21] stages_1_full_data_11_0 <= stages_0_full_data_11_0; // @[Pipeline.scala:21:21] stages_1_full_data_12_0 <= stages_0_full_data_12_0; // @[Pipeline.scala:21:21] stages_1_full_data_13_0 <= stages_0_full_data_13_0; // @[Pipeline.scala:21:21] stages_1_full_data_14_0 <= stages_0_full_data_14_0; // @[Pipeline.scala:21:21] stages_1_full_data_15_0 <= stages_0_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_resp_data_0_0 <= stages_1_resp_data_0_0; // @[Pipeline.scala:21:21] stages_2_resp_data_1_0 <= stages_1_resp_data_1_0; // @[Pipeline.scala:21:21] stages_2_resp_data_2_0 <= stages_1_resp_data_2_0; // @[Pipeline.scala:21:21] stages_2_resp_data_3_0 <= stages_1_resp_data_3_0; // @[Pipeline.scala:21:21] stages_2_resp_data_4_0 <= stages_1_resp_data_4_0; // @[Pipeline.scala:21:21] stages_2_resp_data_5_0 <= stages_1_resp_data_5_0; // @[Pipeline.scala:21:21] stages_2_resp_data_6_0 <= stages_1_resp_data_6_0; // @[Pipeline.scala:21:21] stages_2_resp_data_7_0 <= stages_1_resp_data_7_0; // @[Pipeline.scala:21:21] stages_2_resp_data_8_0 <= stages_1_resp_data_8_0; // @[Pipeline.scala:21:21] stages_2_resp_data_9_0 <= stages_1_resp_data_9_0; // @[Pipeline.scala:21:21] stages_2_resp_data_10_0 <= stages_1_resp_data_10_0; // @[Pipeline.scala:21:21] stages_2_resp_data_11_0 <= stages_1_resp_data_11_0; // @[Pipeline.scala:21:21] stages_2_resp_data_12_0 <= stages_1_resp_data_12_0; // @[Pipeline.scala:21:21] stages_2_resp_data_13_0 <= stages_1_resp_data_13_0; // @[Pipeline.scala:21:21] stages_2_resp_data_14_0 <= stages_1_resp_data_14_0; // @[Pipeline.scala:21:21] stages_2_resp_data_15_0 <= stages_1_resp_data_15_0; // @[Pipeline.scala:21:21] stages_2_resp_fromDMA <= stages_1_resp_fromDMA; // @[Pipeline.scala:21:21] stages_2_resp_scale_bits <= stages_1_resp_scale_bits; // @[Pipeline.scala:21:21] stages_2_resp_igelu_qb <= stages_1_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_2_resp_igelu_qc <= stages_1_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_2_resp_iexp_qln2 <= stages_1_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_2_resp_iexp_qln2_inv <= stages_1_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_2_resp_act <= stages_1_resp_act; // @[Pipeline.scala:21:21] stages_2_resp_acc_bank_id <= stages_1_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_2_full_data_0_0 <= stages_1_full_data_0_0; // @[Pipeline.scala:21:21] stages_2_full_data_1_0 <= stages_1_full_data_1_0; // @[Pipeline.scala:21:21] stages_2_full_data_2_0 <= stages_1_full_data_2_0; // @[Pipeline.scala:21:21] stages_2_full_data_3_0 <= stages_1_full_data_3_0; // @[Pipeline.scala:21:21] stages_2_full_data_4_0 <= stages_1_full_data_4_0; // @[Pipeline.scala:21:21] stages_2_full_data_5_0 <= stages_1_full_data_5_0; // @[Pipeline.scala:21:21] stages_2_full_data_6_0 <= stages_1_full_data_6_0; // @[Pipeline.scala:21:21] stages_2_full_data_7_0 <= stages_1_full_data_7_0; // @[Pipeline.scala:21:21] stages_2_full_data_8_0 <= stages_1_full_data_8_0; // @[Pipeline.scala:21:21] stages_2_full_data_9_0 <= stages_1_full_data_9_0; // @[Pipeline.scala:21:21] stages_2_full_data_10_0 <= stages_1_full_data_10_0; // @[Pipeline.scala:21:21] stages_2_full_data_11_0 <= stages_1_full_data_11_0; // @[Pipeline.scala:21:21] stages_2_full_data_12_0 <= stages_1_full_data_12_0; // @[Pipeline.scala:21:21] stages_2_full_data_13_0 <= stages_1_full_data_13_0; // @[Pipeline.scala:21:21] stages_2_full_data_14_0 <= stages_1_full_data_14_0; // @[Pipeline.scala:21:21] stages_2_full_data_15_0 <= stages_1_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_resp_data_0_0 <= stages_2_resp_data_0_0; // @[Pipeline.scala:21:21] stages_3_resp_data_1_0 <= stages_2_resp_data_1_0; // @[Pipeline.scala:21:21] stages_3_resp_data_2_0 <= stages_2_resp_data_2_0; // @[Pipeline.scala:21:21] stages_3_resp_data_3_0 <= stages_2_resp_data_3_0; // @[Pipeline.scala:21:21] stages_3_resp_data_4_0 <= stages_2_resp_data_4_0; // @[Pipeline.scala:21:21] stages_3_resp_data_5_0 <= stages_2_resp_data_5_0; // @[Pipeline.scala:21:21] stages_3_resp_data_6_0 <= stages_2_resp_data_6_0; // @[Pipeline.scala:21:21] stages_3_resp_data_7_0 <= stages_2_resp_data_7_0; // @[Pipeline.scala:21:21] stages_3_resp_data_8_0 <= stages_2_resp_data_8_0; // @[Pipeline.scala:21:21] stages_3_resp_data_9_0 <= stages_2_resp_data_9_0; // @[Pipeline.scala:21:21] stages_3_resp_data_10_0 <= stages_2_resp_data_10_0; // @[Pipeline.scala:21:21] stages_3_resp_data_11_0 <= stages_2_resp_data_11_0; // @[Pipeline.scala:21:21] stages_3_resp_data_12_0 <= stages_2_resp_data_12_0; // @[Pipeline.scala:21:21] stages_3_resp_data_13_0 <= stages_2_resp_data_13_0; // @[Pipeline.scala:21:21] stages_3_resp_data_14_0 <= stages_2_resp_data_14_0; // @[Pipeline.scala:21:21] stages_3_resp_data_15_0 <= stages_2_resp_data_15_0; // @[Pipeline.scala:21:21] stages_3_resp_fromDMA <= stages_2_resp_fromDMA; // @[Pipeline.scala:21:21] stages_3_resp_scale_bits <= stages_2_resp_scale_bits; // @[Pipeline.scala:21:21] stages_3_resp_igelu_qb <= stages_2_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_3_resp_igelu_qc <= stages_2_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_3_resp_iexp_qln2 <= stages_2_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_3_resp_iexp_qln2_inv <= stages_2_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_3_resp_act <= stages_2_resp_act; // @[Pipeline.scala:21:21] stages_3_resp_acc_bank_id <= stages_2_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_3_full_data_0_0 <= stages_2_full_data_0_0; // @[Pipeline.scala:21:21] stages_3_full_data_1_0 <= stages_2_full_data_1_0; // @[Pipeline.scala:21:21] stages_3_full_data_2_0 <= stages_2_full_data_2_0; // @[Pipeline.scala:21:21] stages_3_full_data_3_0 <= stages_2_full_data_3_0; // @[Pipeline.scala:21:21] stages_3_full_data_4_0 <= stages_2_full_data_4_0; // @[Pipeline.scala:21:21] stages_3_full_data_5_0 <= stages_2_full_data_5_0; // @[Pipeline.scala:21:21] stages_3_full_data_6_0 <= stages_2_full_data_6_0; // @[Pipeline.scala:21:21] stages_3_full_data_7_0 <= stages_2_full_data_7_0; // @[Pipeline.scala:21:21] stages_3_full_data_8_0 <= stages_2_full_data_8_0; // @[Pipeline.scala:21:21] stages_3_full_data_9_0 <= stages_2_full_data_9_0; // @[Pipeline.scala:21:21] stages_3_full_data_10_0 <= stages_2_full_data_10_0; // @[Pipeline.scala:21:21] stages_3_full_data_11_0 <= stages_2_full_data_11_0; // @[Pipeline.scala:21:21] stages_3_full_data_12_0 <= stages_2_full_data_12_0; // @[Pipeline.scala:21:21] stages_3_full_data_13_0 <= stages_2_full_data_13_0; // @[Pipeline.scala:21:21] stages_3_full_data_14_0 <= stages_2_full_data_14_0; // @[Pipeline.scala:21:21] stages_3_full_data_15_0 <= stages_2_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_4) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_4_resp_data_0_0 <= stages_3_resp_data_0_0; // @[Pipeline.scala:21:21] stages_4_resp_data_1_0 <= stages_3_resp_data_1_0; // @[Pipeline.scala:21:21] stages_4_resp_data_2_0 <= stages_3_resp_data_2_0; // @[Pipeline.scala:21:21] stages_4_resp_data_3_0 <= stages_3_resp_data_3_0; // @[Pipeline.scala:21:21] stages_4_resp_data_4_0 <= stages_3_resp_data_4_0; // @[Pipeline.scala:21:21] stages_4_resp_data_5_0 <= stages_3_resp_data_5_0; // @[Pipeline.scala:21:21] stages_4_resp_data_6_0 <= stages_3_resp_data_6_0; // @[Pipeline.scala:21:21] stages_4_resp_data_7_0 <= stages_3_resp_data_7_0; // @[Pipeline.scala:21:21] stages_4_resp_data_8_0 <= stages_3_resp_data_8_0; // @[Pipeline.scala:21:21] stages_4_resp_data_9_0 <= stages_3_resp_data_9_0; // @[Pipeline.scala:21:21] stages_4_resp_data_10_0 <= stages_3_resp_data_10_0; // @[Pipeline.scala:21:21] stages_4_resp_data_11_0 <= stages_3_resp_data_11_0; // @[Pipeline.scala:21:21] stages_4_resp_data_12_0 <= stages_3_resp_data_12_0; // @[Pipeline.scala:21:21] stages_4_resp_data_13_0 <= stages_3_resp_data_13_0; // @[Pipeline.scala:21:21] stages_4_resp_data_14_0 <= stages_3_resp_data_14_0; // @[Pipeline.scala:21:21] stages_4_resp_data_15_0 <= stages_3_resp_data_15_0; // @[Pipeline.scala:21:21] stages_4_resp_fromDMA <= stages_3_resp_fromDMA; // @[Pipeline.scala:21:21] stages_4_resp_scale_bits <= stages_3_resp_scale_bits; // @[Pipeline.scala:21:21] stages_4_resp_igelu_qb <= stages_3_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_4_resp_igelu_qc <= stages_3_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_4_resp_iexp_qln2 <= stages_3_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_4_resp_iexp_qln2_inv <= stages_3_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_4_resp_act <= stages_3_resp_act; // @[Pipeline.scala:21:21] stages_4_resp_acc_bank_id <= stages_3_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_4_full_data_0_0 <= stages_3_full_data_0_0; // @[Pipeline.scala:21:21] stages_4_full_data_1_0 <= stages_3_full_data_1_0; // @[Pipeline.scala:21:21] stages_4_full_data_2_0 <= stages_3_full_data_2_0; // @[Pipeline.scala:21:21] stages_4_full_data_3_0 <= stages_3_full_data_3_0; // @[Pipeline.scala:21:21] stages_4_full_data_4_0 <= stages_3_full_data_4_0; // @[Pipeline.scala:21:21] stages_4_full_data_5_0 <= stages_3_full_data_5_0; // @[Pipeline.scala:21:21] stages_4_full_data_6_0 <= stages_3_full_data_6_0; // @[Pipeline.scala:21:21] stages_4_full_data_7_0 <= stages_3_full_data_7_0; // @[Pipeline.scala:21:21] stages_4_full_data_8_0 <= stages_3_full_data_8_0; // @[Pipeline.scala:21:21] stages_4_full_data_9_0 <= stages_3_full_data_9_0; // @[Pipeline.scala:21:21] stages_4_full_data_10_0 <= stages_3_full_data_10_0; // @[Pipeline.scala:21:21] stages_4_full_data_11_0 <= stages_3_full_data_11_0; // @[Pipeline.scala:21:21] stages_4_full_data_12_0 <= stages_3_full_data_12_0; // @[Pipeline.scala:21:21] stages_4_full_data_13_0 <= stages_3_full_data_13_0; // @[Pipeline.scala:21:21] stages_4_full_data_14_0 <= stages_3_full_data_14_0; // @[Pipeline.scala:21:21] stages_4_full_data_15_0 <= stages_3_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_5) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_5_resp_data_0_0 <= stages_4_resp_data_0_0; // @[Pipeline.scala:21:21] stages_5_resp_data_1_0 <= stages_4_resp_data_1_0; // @[Pipeline.scala:21:21] stages_5_resp_data_2_0 <= stages_4_resp_data_2_0; // @[Pipeline.scala:21:21] stages_5_resp_data_3_0 <= stages_4_resp_data_3_0; // @[Pipeline.scala:21:21] stages_5_resp_data_4_0 <= stages_4_resp_data_4_0; // @[Pipeline.scala:21:21] stages_5_resp_data_5_0 <= stages_4_resp_data_5_0; // @[Pipeline.scala:21:21] stages_5_resp_data_6_0 <= stages_4_resp_data_6_0; // @[Pipeline.scala:21:21] stages_5_resp_data_7_0 <= stages_4_resp_data_7_0; // @[Pipeline.scala:21:21] stages_5_resp_data_8_0 <= stages_4_resp_data_8_0; // @[Pipeline.scala:21:21] stages_5_resp_data_9_0 <= stages_4_resp_data_9_0; // @[Pipeline.scala:21:21] stages_5_resp_data_10_0 <= stages_4_resp_data_10_0; // @[Pipeline.scala:21:21] stages_5_resp_data_11_0 <= stages_4_resp_data_11_0; // @[Pipeline.scala:21:21] stages_5_resp_data_12_0 <= stages_4_resp_data_12_0; // @[Pipeline.scala:21:21] stages_5_resp_data_13_0 <= stages_4_resp_data_13_0; // @[Pipeline.scala:21:21] stages_5_resp_data_14_0 <= stages_4_resp_data_14_0; // @[Pipeline.scala:21:21] stages_5_resp_data_15_0 <= stages_4_resp_data_15_0; // @[Pipeline.scala:21:21] stages_5_resp_fromDMA <= stages_4_resp_fromDMA; // @[Pipeline.scala:21:21] stages_5_resp_scale_bits <= stages_4_resp_scale_bits; // @[Pipeline.scala:21:21] stages_5_resp_igelu_qb <= stages_4_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_5_resp_igelu_qc <= stages_4_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_5_resp_iexp_qln2 <= stages_4_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_5_resp_iexp_qln2_inv <= stages_4_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_5_resp_act <= stages_4_resp_act; // @[Pipeline.scala:21:21] stages_5_resp_acc_bank_id <= stages_4_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_5_full_data_0_0 <= stages_4_full_data_0_0; // @[Pipeline.scala:21:21] stages_5_full_data_1_0 <= stages_4_full_data_1_0; // @[Pipeline.scala:21:21] stages_5_full_data_2_0 <= stages_4_full_data_2_0; // @[Pipeline.scala:21:21] stages_5_full_data_3_0 <= stages_4_full_data_3_0; // @[Pipeline.scala:21:21] stages_5_full_data_4_0 <= stages_4_full_data_4_0; // @[Pipeline.scala:21:21] stages_5_full_data_5_0 <= stages_4_full_data_5_0; // @[Pipeline.scala:21:21] stages_5_full_data_6_0 <= stages_4_full_data_6_0; // @[Pipeline.scala:21:21] stages_5_full_data_7_0 <= stages_4_full_data_7_0; // @[Pipeline.scala:21:21] stages_5_full_data_8_0 <= stages_4_full_data_8_0; // @[Pipeline.scala:21:21] stages_5_full_data_9_0 <= stages_4_full_data_9_0; // @[Pipeline.scala:21:21] stages_5_full_data_10_0 <= stages_4_full_data_10_0; // @[Pipeline.scala:21:21] stages_5_full_data_11_0 <= stages_4_full_data_11_0; // @[Pipeline.scala:21:21] stages_5_full_data_12_0 <= stages_4_full_data_12_0; // @[Pipeline.scala:21:21] stages_5_full_data_13_0 <= stages_4_full_data_13_0; // @[Pipeline.scala:21:21] stages_5_full_data_14_0 <= stages_4_full_data_14_0; // @[Pipeline.scala:21:21] stages_5_full_data_15_0 <= stages_4_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_6) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_6_resp_data_0_0 <= stages_5_resp_data_0_0; // @[Pipeline.scala:21:21] stages_6_resp_data_1_0 <= stages_5_resp_data_1_0; // @[Pipeline.scala:21:21] stages_6_resp_data_2_0 <= stages_5_resp_data_2_0; // @[Pipeline.scala:21:21] stages_6_resp_data_3_0 <= stages_5_resp_data_3_0; // @[Pipeline.scala:21:21] stages_6_resp_data_4_0 <= stages_5_resp_data_4_0; // @[Pipeline.scala:21:21] stages_6_resp_data_5_0 <= stages_5_resp_data_5_0; // @[Pipeline.scala:21:21] stages_6_resp_data_6_0 <= stages_5_resp_data_6_0; // @[Pipeline.scala:21:21] stages_6_resp_data_7_0 <= stages_5_resp_data_7_0; // @[Pipeline.scala:21:21] stages_6_resp_data_8_0 <= stages_5_resp_data_8_0; // @[Pipeline.scala:21:21] stages_6_resp_data_9_0 <= stages_5_resp_data_9_0; // @[Pipeline.scala:21:21] stages_6_resp_data_10_0 <= stages_5_resp_data_10_0; // @[Pipeline.scala:21:21] stages_6_resp_data_11_0 <= stages_5_resp_data_11_0; // @[Pipeline.scala:21:21] stages_6_resp_data_12_0 <= stages_5_resp_data_12_0; // @[Pipeline.scala:21:21] stages_6_resp_data_13_0 <= stages_5_resp_data_13_0; // @[Pipeline.scala:21:21] stages_6_resp_data_14_0 <= stages_5_resp_data_14_0; // @[Pipeline.scala:21:21] stages_6_resp_data_15_0 <= stages_5_resp_data_15_0; // @[Pipeline.scala:21:21] stages_6_resp_fromDMA <= stages_5_resp_fromDMA; // @[Pipeline.scala:21:21] stages_6_resp_scale_bits <= stages_5_resp_scale_bits; // @[Pipeline.scala:21:21] stages_6_resp_igelu_qb <= stages_5_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_6_resp_igelu_qc <= stages_5_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_6_resp_iexp_qln2 <= stages_5_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_6_resp_iexp_qln2_inv <= stages_5_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_6_resp_act <= stages_5_resp_act; // @[Pipeline.scala:21:21] stages_6_resp_acc_bank_id <= stages_5_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_6_full_data_0_0 <= stages_5_full_data_0_0; // @[Pipeline.scala:21:21] stages_6_full_data_1_0 <= stages_5_full_data_1_0; // @[Pipeline.scala:21:21] stages_6_full_data_2_0 <= stages_5_full_data_2_0; // @[Pipeline.scala:21:21] stages_6_full_data_3_0 <= stages_5_full_data_3_0; // @[Pipeline.scala:21:21] stages_6_full_data_4_0 <= stages_5_full_data_4_0; // @[Pipeline.scala:21:21] stages_6_full_data_5_0 <= stages_5_full_data_5_0; // @[Pipeline.scala:21:21] stages_6_full_data_6_0 <= stages_5_full_data_6_0; // @[Pipeline.scala:21:21] stages_6_full_data_7_0 <= stages_5_full_data_7_0; // @[Pipeline.scala:21:21] stages_6_full_data_8_0 <= stages_5_full_data_8_0; // @[Pipeline.scala:21:21] stages_6_full_data_9_0 <= stages_5_full_data_9_0; // @[Pipeline.scala:21:21] stages_6_full_data_10_0 <= stages_5_full_data_10_0; // @[Pipeline.scala:21:21] stages_6_full_data_11_0 <= stages_5_full_data_11_0; // @[Pipeline.scala:21:21] stages_6_full_data_12_0 <= stages_5_full_data_12_0; // @[Pipeline.scala:21:21] stages_6_full_data_13_0 <= stages_5_full_data_13_0; // @[Pipeline.scala:21:21] stages_6_full_data_14_0 <= stages_5_full_data_14_0; // @[Pipeline.scala:21:21] stages_6_full_data_15_0 <= stages_5_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_7) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_7_resp_data_0_0 <= stages_6_resp_data_0_0; // @[Pipeline.scala:21:21] stages_7_resp_data_1_0 <= stages_6_resp_data_1_0; // @[Pipeline.scala:21:21] stages_7_resp_data_2_0 <= stages_6_resp_data_2_0; // @[Pipeline.scala:21:21] stages_7_resp_data_3_0 <= stages_6_resp_data_3_0; // @[Pipeline.scala:21:21] stages_7_resp_data_4_0 <= stages_6_resp_data_4_0; // @[Pipeline.scala:21:21] stages_7_resp_data_5_0 <= stages_6_resp_data_5_0; // @[Pipeline.scala:21:21] stages_7_resp_data_6_0 <= stages_6_resp_data_6_0; // @[Pipeline.scala:21:21] stages_7_resp_data_7_0 <= stages_6_resp_data_7_0; // @[Pipeline.scala:21:21] stages_7_resp_data_8_0 <= stages_6_resp_data_8_0; // @[Pipeline.scala:21:21] stages_7_resp_data_9_0 <= stages_6_resp_data_9_0; // @[Pipeline.scala:21:21] stages_7_resp_data_10_0 <= stages_6_resp_data_10_0; // @[Pipeline.scala:21:21] stages_7_resp_data_11_0 <= stages_6_resp_data_11_0; // @[Pipeline.scala:21:21] stages_7_resp_data_12_0 <= stages_6_resp_data_12_0; // @[Pipeline.scala:21:21] stages_7_resp_data_13_0 <= stages_6_resp_data_13_0; // @[Pipeline.scala:21:21] stages_7_resp_data_14_0 <= stages_6_resp_data_14_0; // @[Pipeline.scala:21:21] stages_7_resp_data_15_0 <= stages_6_resp_data_15_0; // @[Pipeline.scala:21:21] stages_7_resp_fromDMA <= stages_6_resp_fromDMA; // @[Pipeline.scala:21:21] stages_7_resp_scale_bits <= stages_6_resp_scale_bits; // @[Pipeline.scala:21:21] stages_7_resp_igelu_qb <= stages_6_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_7_resp_igelu_qc <= stages_6_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_7_resp_iexp_qln2 <= stages_6_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_7_resp_iexp_qln2_inv <= stages_6_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_7_resp_act <= stages_6_resp_act; // @[Pipeline.scala:21:21] stages_7_resp_acc_bank_id <= stages_6_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_7_full_data_0_0 <= stages_6_full_data_0_0; // @[Pipeline.scala:21:21] stages_7_full_data_1_0 <= stages_6_full_data_1_0; // @[Pipeline.scala:21:21] stages_7_full_data_2_0 <= stages_6_full_data_2_0; // @[Pipeline.scala:21:21] stages_7_full_data_3_0 <= stages_6_full_data_3_0; // @[Pipeline.scala:21:21] stages_7_full_data_4_0 <= stages_6_full_data_4_0; // @[Pipeline.scala:21:21] stages_7_full_data_5_0 <= stages_6_full_data_5_0; // @[Pipeline.scala:21:21] stages_7_full_data_6_0 <= stages_6_full_data_6_0; // @[Pipeline.scala:21:21] stages_7_full_data_7_0 <= stages_6_full_data_7_0; // @[Pipeline.scala:21:21] stages_7_full_data_8_0 <= stages_6_full_data_8_0; // @[Pipeline.scala:21:21] stages_7_full_data_9_0 <= stages_6_full_data_9_0; // @[Pipeline.scala:21:21] stages_7_full_data_10_0 <= stages_6_full_data_10_0; // @[Pipeline.scala:21:21] stages_7_full_data_11_0 <= stages_6_full_data_11_0; // @[Pipeline.scala:21:21] stages_7_full_data_12_0 <= stages_6_full_data_12_0; // @[Pipeline.scala:21:21] stages_7_full_data_13_0 <= stages_6_full_data_13_0; // @[Pipeline.scala:21:21] stages_7_full_data_14_0 <= stages_6_full_data_14_0; // @[Pipeline.scala:21:21] stages_7_full_data_15_0 <= stages_6_full_data_15_0; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] valids_4 <= 1'h0; // @[Pipeline.scala:22:25] valids_5 <= 1'h0; // @[Pipeline.scala:22:25] valids_6 <= 1'h0; // @[Pipeline.scala:22:25] valids_7 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_8 \| stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 \| stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 \| stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 \| stalling_4 & valids_3; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_4 <= valids_3 \| stalling_5 & valids_4; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_5 <= valids_4 \| stalling_6 & valids_5; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_6 <= valids_5 \| stalling_7 & valids_6; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_7 <= valids_6 \| ~io_out_ready_0 & valids_7; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_0_0 = io_out_bits_resp_data_0_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_1_0 = io_out_bits_resp_data_1_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_2_0 = io_out_bits_resp_data_2_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_3_0 = io_out_bits_resp_data_3_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_4_0 = io_out_bits_resp_data_4_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_5_0 = io_out_bits_resp_data_5_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_6_0 = io_out_bits_resp_data_6_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_7_0 = io_out_bits_resp_data_7_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_8_0 = io_out_bits_resp_data_8_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_9_0 = io_out_bits_resp_data_9_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_10_0 = io_out_bits_resp_data_10_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_11_0 = io_out_bits_resp_data_11_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_12_0 = io_out_bits_resp_data_12_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_13_0 = io_out_bits_resp_data_13_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_14_0 = io_out_bits_resp_data_14_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_15_0 = io_out_bits_resp_data_15_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_fromDMA = io_out_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_acc_bank_id = io_out_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_0_0 = io_out_bits_full_data_0_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_1_0 = io_out_bits_full_data_1_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_2_0 = io_out_bits_full_data_2_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_3_0 = io_out_bits_full_data_3_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_4_0 = io_out_bits_full_data_4_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_5_0 = io_out_bits_full_data_5_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_6_0 = io_out_bits_full_data_6_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_7_0 = io_out_bits_full_data_7_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_8_0 = io_out_bits_full_data_8_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_9_0 = io_out_bits_full_data_9_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_10_0 = io_out_bits_full_data_10_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_11_0 = io_out_bits_full_data_11_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_12_0 = io_out_bits_full_data_12_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_13_0 = io_out_bits_full_data_13_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_14_0 = io_out_bits_full_data_14_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_15_0 = io_out_bits_full_data_15_0_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module ClockCrossingReg_w32_17( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFNToRaw_postMul_e8_s24_3( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Protocol.scala: package rerocc.bus import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import rerocc.client.{ReRoCCClientParams} import rerocc.manager.{ReRoCCManagerParams} object ReRoCCProtocol { val width = 3 val mAcquire = 0.U(width.W) // beat0: data = inst // beat1: data = mstatus[63:0] // beat2: data = mstatus[127:64] val mInst = 1.U(width.W) // beat0: data = mstatus[63:0] // beat1: data = mstatus[127:0] val mUStatus = 2.U(width.W) // beat0: data = ptbr val mUPtbr = 3.U(width.W) val mRelease = 4.U(width.W) val mUnbusy = 5.U(width.W) // data // data = acquired val sAcqResp = 0.U(width.W) // data = 0 val sInstAck = 1.U(width.W) // beat0: data = data // beat1: data = rd val sWrite = 2.U(width.W) val sRelResp = 3.U(width.W) val sUnbusyAck = 4.U(width.W) val MAX_BEATS = 3 } class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle { val opcode = UInt(ReRoCCProtocol.width.W) val client_id = UInt(params.clientIdBits.W) val manager_id = UInt(params.managerIdBits.W) val data = UInt(64.W) } object ReRoCCMsgFirstLast { def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = { val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val first = beat === 0.U val last = Wire(Bool()) val inst = m.bits.data.asTypeOf(new RoCCInstruction) when (m.fire && first) { max_beat := 0.U if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mInst) { max_beat := inst.xs1 +& inst.xs2 } .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) { max_beat := 1.U } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { max_beat := 1.U } } } last := true.B if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mUStatus) { last := beat === max_beat && !first } .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) { last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat) } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { last := beat === max_beat && !first } } when (m.fire) { beat := beat + 1.U } when (m.fire && last) { max_beat := 0.U beat := 0.U } (first, last, beat) } } class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle { val req = Decoupled(new ReRoCCMsgBundle(params)) val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params))) } case class EmptyParams() object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] { def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = { ReRoCCEdgeParams(pu, pd) } def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle) def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black /) } case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams)))) case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams)))) class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, _), (out, _)) => out.req <> b(in.req) in.resp <> b(out.resp) } } } object ReRoCCBuffer { def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = { val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p)) rerocc_buffer.node } } case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)() File Arbiter.scala: package rerocc.bus import chisel3._ import chisel3.util._ import freechips.rocketchip.util.{HellaLockingArbiter} class ReRoCCMsgArbiter(bundle: ReRoCCBundleParams, arbN: Int, isReq: Boolean) extends HellaLockingArbiter(new ReRoCCMsgBundle(bundle), arbN, false) { when (io.out.fire) { when (!locked) { lockIdx := choice locked := true.B } when (ReRoCCMsgFirstLast(io.out, isReq)._2) { locked := false.B } } } File Arbiters.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters /* A generalized locking RR arbiter that addresses the limitations of the * version in the Chisel standard library / abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(arbN, Decoupled(typ.cloneType))) val out = Decoupled(typ.cloneType) }) def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { val n = norm.size VecInit.tabulate(n) { i => Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U)) } } val lockIdx = RegInit(0.U(log2Up(arbN).W)) val locked = RegInit(false.B) val choice = if (rr) { PriorityMux( rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U), rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U)) } else { PriorityEncoder(io.in.map(_.valid)) } val chosen = Mux(locked, lockIdx, choice) for (i <- 0 until arbN) { io.in(i).ready := io.out.ready && chosen === i.U } io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits } /* This locking arbiter determines when it is safe to unlock * by peeking at the data / class HellaPeekingArbiter[T <: Data]( typ: T, arbN: Int, canUnlock: T => Bool, needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B } // the unlock statement takes precedent when (canUnlock(io.out.bits)) { locked := false.B } } } /* This arbiter determines when it is safe to unlock by counting transactions / class HellaCountingArbiter[T <: Data]( typ: T, arbN: Int, count: Int, val needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) // if count is 1, you should use a non-locking arbiter require(count > 1, "CountingArbiter cannot have count <= 1") val lock_ctr = Counter(count) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B lock_ctr.inc() } when (locked) { when (lock_ctr.inc()) { locked := false.B } } } } /* This arbiter preserves the order of responses */ class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val in_req = Flipped(Vec(n, Decoupled(reqTyp))) val in_resp = Vec(n, Decoupled(respTyp)) val out_req = Decoupled(reqTyp) val out_resp = Flipped(Decoupled(respTyp)) }) if (n > 1) { val route_q = Module(new Queue(UInt(log2Up(n).W), 2)) val req_arb = Module(new RRArbiter(reqTyp, n)) req_arb.io.in <> io.in_req val req_helper = DecoupledHelper( req_arb.io.out.valid, route_q.io.enq.ready, io.out_req.ready) io.out_req.bits := req_arb.io.out.bits io.out_req.valid := req_helper.fire(io.out_req.ready) route_q.io.enq.bits := req_arb.io.chosen route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready) req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid) val resp_sel = route_q.io.deq.bits val resp_ready = io.in_resp(resp_sel).ready val resp_helper = DecoupledHelper( resp_ready, route_q.io.deq.valid, io.out_resp.valid) val resp_valid = resp_helper.fire(resp_ready) for (i <- 0 until n) { io.in_resp(i).bits := io.out_resp.bits io.in_resp(i).valid := resp_valid && resp_sel === i.U } route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid) io.out_resp.ready := resp_helper.fire(io.out_resp.valid) } else { io.out_req <> io.in_req.head io.in_resp.head <> io.out_resp } }	module ReRoCCMsgArbiter_6( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_opcode, // @[Arbiters.scala:14:14] input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14] output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_manager_id, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_opcode_0 = io_in_0_bits_opcode; // @[Arbiter.scala:7:7] wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7] wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7] wire _io_in_0_ready_T = 1'h1; // @[Arbiters.scala:40:46] wire chosen = 1'h0; // @[Arbiters.scala:37:19] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_out_valid_WIRE = 1'h0; wire _io_out_bits_WIRE = 1'h0; wire io_out_valid_0 = io_in_0_valid_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_opcode_0 = io_in_0_bits_opcode_0; // @[Arbiter.scala:7:7] wire [3:0] io_out_bits_client_id_0 = io_in_0_bits_client_id_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_manager_id_0 = io_in_0_bits_manager_id_0; // @[Arbiter.scala:7:7] wire [63:0] io_out_bits_data_0 = io_in_0_bits_data_0; // @[Arbiter.scala:7:7] assign _io_in_0_ready_T_1 = io_out_ready_0; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[Arbiter.scala:7:7] reg locked; // @[Arbiters.scala:27:23] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] reg [1:0] beat; // @[Protocol.scala:54:23] reg [1:0] max_beat; // @[Protocol.scala:55:27] wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22] wire last; // @[Protocol.scala:57:20] wire [6:0] _inst_T_7; // @[Protocol.scala:58:36] wire [4:0] _inst_T_6; // @[Protocol.scala:58:36] wire [4:0] _inst_T_5; // @[Protocol.scala:58:36] wire _inst_T_4; // @[Protocol.scala:58:36] wire _inst_T_3; // @[Protocol.scala:58:36] wire _inst_T_2; // @[Protocol.scala:58:36] wire [4:0] _inst_T_1; // @[Protocol.scala:58:36] wire [6:0] _inst_T; // @[Protocol.scala:58:36] wire [6:0] inst_funct; // @[Protocol.scala:58:36] wire [4:0] inst_rs2; // @[Protocol.scala:58:36] wire [4:0] inst_rs1; // @[Protocol.scala:58:36] wire inst_xd; // @[Protocol.scala:58:36] wire inst_xs1; // @[Protocol.scala:58:36] wire inst_xs2; // @[Protocol.scala:58:36] wire [4:0] inst_rd; // @[Protocol.scala:58:36] wire [6:0] inst_opcode; // @[Protocol.scala:58:36] wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36] assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36] assign inst_opcode = _inst_T; // @[Protocol.scala:58:36] assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36] assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36] assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36] assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36] assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36] assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36] assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36] assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36] assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36] assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36] assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36] assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36] assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36] assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36] wire [1:0] _max_beat_T = {1'h0, inst_xs1} + {1'h0, inst_xs2}; // @[Protocol.scala:58:36, :63:32] wire _GEN = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :77:22] wire _last_T; // @[Protocol.scala:77:22] assign _last_T = _GEN; // @[Protocol.scala:77:22] wire _last_T_6; // @[Protocol.scala:79:57] assign _last_T_6 = _GEN; // @[Protocol.scala:77:22, :79:57] wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :77:38] wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:77:{22,35,38}] wire _last_T_3 = ~inst_xs1; // @[Protocol.scala:58:36, :79:28] wire _last_T_4 = ~inst_xs2; // @[Protocol.scala:58:36, :79:41] wire _last_T_5 = _last_T_3 & _last_T_4; // @[Protocol.scala:79:{28,38,41}] wire _last_T_7 = first ? _last_T_5 : _last_T_6; // @[Protocol.scala:56:22, :79:{20,38,57}] assign last = io_out_bits_opcode_0 == 3'h2 ? _last_T_2 : io_out_bits_opcode_0 != 3'h1 \| _last_T_7; // @[Protocol.scala:57:20, :74:10, :76:{27,56}, :77:{14,35}, :78:{34,60}, :79:{14,20}, :87:34] wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Protocol.scala:54:23, :87:34] wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34] wire _T_9 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Arbiter.scala:7:7] if (reset) begin // @[Arbiter.scala:7:7] locked <= 1'h0; // @[Arbiters.scala:27:23] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Arbiter.scala:7:7] if (_T_9) // @[Decoupled.scala:51:35] locked <= ~last; // @[Arbiters.scala:27:23] if (_T_9 & last) begin // @[Decoupled.scala:51:35] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Protocol.scala:88:18] if (_T_9) // @[Decoupled.scala:51:35] beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34] if (_T_9 & first) // @[Decoupled.scala:51:35] max_beat <= io_out_bits_opcode_0 == 3'h1 ? _max_beat_T : {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Protocol.scala:55:27, :60:16, :62:{29,55}, :63:{20,32}, :64:{36,65}, :65:20, :87:34] end end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7] assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7] assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7] assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_89( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_71( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth2 - 1)) }) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) \|\| (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf \|\| io.b.isInf val notNaN_isZeroOut = io.a.isZero \|\| io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth2 - 1, 0) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ io.invalidExc := isSigNaNRawFloat(io.a) \|\| isSigNaNRawFloat(io.b) \|\| notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN \|\| io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulFullRawFN_7( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_63( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ object consts { /------------------------------------------------------------------------ \| For rounding to integer values, rounding mode 'odd' rounds to minimum \| magnitude instead, same as 'minMag'. ------------------------------------------------------------------------/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /------------------------------------------------------------------------ ------------------------------------------------------------------------/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /------------------------------------------------------------------------ ------------------------------------------------------------------------/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /------------------------------------------------------------------------ ------------------------------------------------------------------------/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }	module RecFNToRecFN_261( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23] .io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23] .io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RecFNToRecFN.scala:72:19] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_24( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen_0 = io_in_uop_bits_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen_0 = io_in_uop_bits_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File L2MemHelperLatencyInjection.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import chisel3.reflect.DataMirror import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig, TLBPTWIO, TLB, MStatus, PRV} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.rocket.{RAS} import freechips.rocketchip.tilelink._ class L2MemHelperLatencyInjection(printInfo: String = "", numOutstandingReqs: Int = 32, queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModule { val numOutstandingRequestsAllowed = numOutstandingReqs val tlTagBits = log2Ceil(numOutstandingRequestsAllowed) lazy val module = new L2MemHelperLatencyInjectionModule(this, printInfo, queueRequests, queueResponses, printWriteBytes) val masterNode = TLClientNode(Seq(TLClientPortParameters( Seq(TLClientParameters(name = printInfo, sourceId = IdRange(0, numOutstandingRequestsAllowed))) ))) } class L2MemHelperLatencyInjectionModule(outer: L2MemHelperLatencyInjection, printInfo: String = "", queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModuleImp(outer) with HasCoreParameters with MemoryOpConstants { val io = IO(new Bundle { val userif = Flipped(new L2MemHelperBundle) val latency_inject_cycles = Input(UInt(64.W)) val sfence = Input(Bool()) val ptw = new TLBPTWIO val status = Flipped(Valid(new MStatus)) }) val (dmem, edge) = outer.masterNode.out.head val request_input = Wire(Decoupled(new L2ReqInternal)) if (!queueRequests) { request_input <> io.userif.req } else { val requestQueue = Module(new Queue(new L2ReqInternal, 4)) request_input <> requestQueue.io.deq requestQueue.io.enq <> io.userif.req } val response_output = Wire(Decoupled(new L2RespInternal)) if (!queueResponses) { io.userif.resp <> response_output } else { val responseQueue = Module(new Queue(new L2RespInternal, 4)) responseQueue.io.enq <> response_output io.userif.resp <> responseQueue.io.deq } val status = Reg(new MStatus) when (io.status.valid) { CompressAccelLogger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, PRV.M.U) status := io.status.bits } val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), p(CompressAccelTLB).get)(edge, p)) tlb.io.req.valid := request_input.valid tlb.io.req.bits.vaddr := request_input.bits.addr tlb.io.req.bits.size := request_input.bits.size tlb.io.req.bits.cmd := request_input.bits.cmd tlb.io.req.bits.passthrough := false.B val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss tlb.io.req.bits.prv := DontCare tlb.io.req.bits.v := DontCare tlb.io.sfence.bits.hv := DontCare tlb.io.sfence.bits.hg := DontCare io.ptw <> tlb.io.ptw tlb.io.ptw.status := status tlb.io.sfence.valid := io.sfence tlb.io.sfence.bits.rs1 := false.B tlb.io.sfence.bits.rs2 := false.B tlb.io.sfence.bits.addr := 0.U tlb.io.sfence.bits.asid := 0.U tlb.io.kill := false.B val outstanding_req_addr = Module(new Queue(new L2InternalTracking, outer.numOutstandingRequestsAllowed * 4)) val tags_for_issue_Q = Module(new Queue(UInt(outer.tlTagBits.W), outer.numOutstandingRequestsAllowed * 2)) tags_for_issue_Q.io.enq.valid := false.B tags_for_issue_Q.io.enq.bits := DontCare val tags_init_reg = RegInit(0.U((outer.tlTagBits+1).W)) when (tags_init_reg =/= (outer.numOutstandingRequestsAllowed).U) { tags_for_issue_Q.io.enq.bits := tags_init_reg tags_for_issue_Q.io.enq.valid := true.B when (tags_for_issue_Q.io.enq.ready) { CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) tags_init_reg := tags_init_reg + 1.U } } val addr_mask_check = (1.U(64.W) << request_input.bits.size) - 1.U val assertcheck = RegNext((!request_input.valid) \|\| ((request_input.bits.addr & addr_mask_check) === 0.U)) when (!assertcheck) { CompressAccelLogger.logInfo(printInfo + " L2IF: access addr must be aligned to write width\n") } assert(assertcheck, printInfo + " L2IF: access addr must be aligned to write width\n") val global_memop_accepted = RegInit(0.U(64.W)) when (io.userif.req.fire) { global_memop_accepted := global_memop_accepted + 1.U } val global_memop_sent = RegInit(0.U(64.W)) val global_memop_ackd = RegInit(0.U(64.W)) val global_memop_resp_to_user = RegInit(0.U(64.W)) io.userif.no_memops_inflight := global_memop_accepted === global_memop_ackd val free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) < (1 << outer.tlTagBits).U val assert_free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) <= (1 << outer.tlTagBits).U when (!assert_free_outstanding_op_slots) { CompressAccelLogger.logInfo(printInfo + " L2IF: Too many outstanding requests for tag count.\n") } assert(assert_free_outstanding_op_slots, printInfo + " L2IF: Too many outstanding requests for tag count.\n") when (request_input.fire) { global_memop_sent := global_memop_sent + 1.U } val sendtag = tags_for_issue_Q.io.deq.bits val cur_cycle = RegInit(0.U(64.W)) cur_cycle := cur_cycle + 1.U val release_cycle_q_depth = 2 * outer.numOutstandingRequestsAllowed val request_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth)) // val req_release_cycle_q = Module(new Queue(UInt(64.W), release_cycle_q_depth, flow=true)) // val req_q = Module(new Queue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth, flow=true)) // req_release_cycle_q.io.enq.bits := cur_cycle + io.latency_inject_cycles request_latency_injection_q.io.latency_cycles := io.latency_inject_cycles request_latency_injection_q.io.enq.bits := DontCare when (request_input.bits.cmd === M_XRD) { val (legal, bundle) = edge.Get(fromSource=sendtag, toAddress=tlb.io.resp.paddr, lgSize=request_input.bits.size) request_latency_injection_q.io.enq.bits := bundle // dmem.a.bits := bundle } .elsewhen (request_input.bits.cmd === M_XWR) { val (legal, bundle) = edge.Put(fromSource=sendtag, toAddress=tlb.io.resp.paddr, lgSize=request_input.bits.size, data=request_input.bits.data << ((request_input.bits.addr(4, 0) << 3))) request_latency_injection_q.io.enq.bits := bundle // dmem.a.bits := bundle } .elsewhen (request_input.valid) { CompressAccelLogger.logInfo(printInfo + " ERR") assert(false.B, "ERR") } val tl_resp_queues = Seq.fill(outer.numOutstandingRequestsAllowed)( Module(new Queue(new L2RespInternal, 4, flow=true)).io) // val current_request_tag_has_response_space = tl_resp_queues(tags_for_issue_Q.io.deq.bits).enq.ready val current_request_tag_has_response_space = tl_resp_queues.zipWithIndex.map({ case (q, idx) => q.enq.ready && (idx.U === tags_for_issue_Q.io.deq.bits) }).reduce(_ \|\| _) val fire_req = DecoupledHelper( request_input.valid, request_latency_injection_q.io.enq.ready, tlb_ready, outstanding_req_addr.io.enq.ready, free_outstanding_op_slots, tags_for_issue_Q.io.deq.valid, current_request_tag_has_response_space ) outstanding_req_addr.io.enq.bits.addrindex := request_input.bits.addr & 0x1F.U outstanding_req_addr.io.enq.bits.tag := sendtag request_latency_injection_q.io.enq.valid := fire_req.fire(request_latency_injection_q.io.enq.ready) request_input.ready := fire_req.fire(request_input.valid) outstanding_req_addr.io.enq.valid := fire_req.fire(outstanding_req_addr.io.enq.ready) tags_for_issue_Q.io.deq.ready := fire_req.fire(tags_for_issue_Q.io.deq.valid) dmem.a <> request_latency_injection_q.io.deq when (dmem.a.fire) { when (request_input.bits.cmd === M_XRD) { CompressAccelLogger.logInfo(printInfo + " L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, sendtag) } } when (fire_req.fire) { when (request_input.bits.cmd === M_XWR) { CompressAccelLogger.logCritical(printInfo + " L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, sendtag) if (printWriteBytes) { for (i <- 0 until 32) { when (i.U < (1.U << request_input.bits.size)) { CompressAccelLogger.logInfo("WRITE_BYTE ADDR: 0x%x BYTE: 0x%x " + printInfo + "\n", request_input.bits.addr + i.U, (request_input.bits.data >> (i8).U)(7, 0)) } } } } } val response_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleD](dmem.d.bits), release_cycle_q_depth)) response_latency_injection_q.io.latency_cycles := io.latency_inject_cycles response_latency_injection_q.io.enq <> dmem.d // val selectQready = tl_resp_queues(response_latency_injection_q.io.deq.bits.source).enq.ready val selectQready = tl_resp_queues.zipWithIndex.map({ case(q, idx) => q.enq.ready && (idx.U === response_latency_injection_q.io.deq.bits.source) }).reduce(_ \|\| _) val fire_actual_mem_resp = DecoupledHelper( selectQready, response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready ) when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready)) { tags_for_issue_Q.io.enq.valid := true.B tags_for_issue_Q.io.enq.bits := response_latency_injection_q.io.deq.bits.source } when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready) && tags_for_issue_Q.io.enq.valid) { CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) } response_latency_injection_q.io.deq.ready := fire_actual_mem_resp.fire(response_latency_injection_q.io.deq.valid) for (i <- 0 until outer.numOutstandingRequestsAllowed) { tl_resp_queues(i).enq.valid := fire_actual_mem_resp.fire(selectQready) && (response_latency_injection_q.io.deq.bits.source === i.U) tl_resp_queues(i).enq.bits.data := response_latency_injection_q.io.deq.bits.data } // val currentQueue = tl_resp_queues(outstanding_req_addr.io.deq.bits.tag) // val queueValid = currentQueue.deq.valid val queueValid = tl_resp_queues.zipWithIndex.map({ case(q, idx) => q.deq.valid && (idx.U === outstanding_req_addr.io.deq.bits.tag) }).reduce(_ \|\| _) val fire_user_resp = DecoupledHelper( queueValid, response_output.ready, outstanding_req_addr.io.deq.valid ) // val resultdata = currentQueue.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3) val resultdata = tl_resp_queues.zipWithIndex.map({ case(q, idx) => val is_current_q = (idx.U === outstanding_req_addr.io.deq.bits.tag) val data = Wire(q.deq.bits.data.cloneType) when (is_current_q) { data := q.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3) } .otherwise { data := 0.U } data }).reduce(_ \| _) response_output.bits.data := resultdata response_output.valid := fire_user_resp.fire(response_output.ready) outstanding_req_addr.io.deq.ready := fire_user_resp.fire(outstanding_req_addr.io.deq.valid) for (i <- 0 until outer.numOutstandingRequestsAllowed) { tl_resp_queues(i).deq.ready := fire_user_resp.fire(queueValid) && (outstanding_req_addr.io.deq.bits.tag === i.U) } when (dmem.d.fire) { when (edge.hasData(dmem.d.bits)) { CompressAccelLogger.logInfo(printInfo + " L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", dmem.d.bits.data, global_memop_ackd, dmem.d.bits.source) } .otherwise { CompressAccelLogger.logInfo(printInfo + " L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, dmem.d.bits.source) } } when (response_output.fire) { CompressAccelLogger.logInfo(printInfo + " L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) } when (response_latency_injection_q.io.deq.fire) { global_memop_ackd := global_memop_ackd + 1.U } when (response_output.fire) { global_memop_resp_to_user := global_memop_resp_to_user + 1.U } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } def logCritical(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } } def logWaveStyle(format: String, args: Bits)(implicit p: Parameters) { } } object CompressAccelParams { } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File annotations.scala: // See LICENSE for license details. package midas.targetutils import chisel3.{ dontTouch, fromBooleanToLiteral, when, Bits, Bool, Clock, Data, MemBase, Module, Printable, RegNext, Reset, UInt, Wire, WireDefault, } import chisel3.printf.Printf import chisel3.experimental.{annotate, requireIsHardware, BaseModule, ChiselAnnotation} import firrtl.RenameMap import firrtl.annotations.{ Annotation, ComponentName, HasSerializationHints, InstanceTarget, ModuleTarget, ReferenceTarget, SingleTargetAnnotation, } /* These are consumed by [[midas.passes.AutoILATransform]] to directly instantiate an ILA at the top of simulator's * design hierarchy (the PlatformShim level). / case class FpgaDebugAnnotation(target: Data) extends ChiselAnnotation { def toFirrtl = FirrtlFpgaDebugAnnotation(target.toNamed) } case class FirrtlFpgaDebugAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] { def duplicate(n: ComponentName) = this.copy(target = n) } object FpgaDebug { def apply(targets: Data): Unit = { targets.foreach { requireIsHardware(_, "Target passed to FpgaDebug:") } targets.map({ t => annotate(FpgaDebugAnnotation(t)) }) } } private[midas] class ReferenceTargetRenamer(renames: RenameMap) { // TODO: determine order for multiple renames, or just check of == 1 rename? def exactRename(rt: ReferenceTarget): ReferenceTarget = { val renameMatches = renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) assert( renameMatches.length <= 1, s"${rt} should be renamed exactly once (or not at all). Suggested renames: ${renameMatches}", ) renameMatches.headOption.getOrElse(rt) } def apply(rt: ReferenceTarget): Seq[ReferenceTarget] = { renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) } } private[midas] case class SynthPrintfAnnotation( target: ReferenceTarget ) extends firrtl.annotations.SingleTargetAnnotation[ReferenceTarget] { def duplicate(newTarget: ReferenceTarget) = this.copy(newTarget) } object SynthesizePrintf { /** Annotates a chisel printf as a candidate for synthesis. The printf is only synthesized if Printf synthesis is * enabled in Golden Gate. * * See: https://docs.fires.im/en/stable/search.html?q=Printf+Synthesis&check_keywords=yes&area=default * * @param printf * The printf statement to be synthesized. * * @return * The original input, so that this annotator may be applied inline if desired. / def apply(printf: Printf): Printf = { annotate(new ChiselAnnotation { def toFirrtl = SynthPrintfAnnotation(printf.toTarget) }) printf } private def generateAnnotations(format: String, args: Seq[Bits], name: Option[String]): Printable = { Module.currentModule.getOrElse(throw new RuntimeException("Cannot annotate a printf outside of a Module")) // To preserve the behavior of the printf parameter annotator, generate a // secondary printf and annotate that, instead of the user's printf, which // will be given an empty string. This will be removed with the apply methods in 1.15. val printf = SynthesizePrintf(chisel3.printf(Printable.pack(format, args: _))) name.foreach { n => printf.suggestName(n) } Printable.pack("") } /** Annotates* a printf by intercepting the parameters to a chisel printf, and returning a printable. As a side * effect, this function generates a ChiselSynthPrintfAnnotation with the format string and references to each of the * args. * * Note: this isn't actually annotating the statement but instead the arguments. This is a vestige from earlier versions of chisel / firrtl in which print statements were unnamed, and thus not referenceable from annotations. * * @param format * The format string for the printf * @param args * Hardware references to populate the format string. / @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(format: String, args: Bits): Printable = generateAnnotations(format, args, None) /** Like the other apply method, but provides an optional name which can be used by synthesized hardware / bridge. * Generally, users deploy the nameless form. * * @param name * A descriptive name for this printf instance. * @param format * The format string for the printf * @param args * Hardware references to populate the format string. / @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(name: String, format: String, args: Bits): Printable = generateAnnotations(format, args, Some(name)) } /** A mixed-in ancestor trait for all FAME annotations, useful for type-casing. / trait FAMEAnnotation { this: Annotation => } /* This labels an instance so that it is extracted as a separate FAME model. / case class FAMEModelAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlFAMEModelAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlFAMEModelAnnotation(parent.instOf(target.instanceName, target.name)) } } case class FirrtlFAMEModelAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /* This specifies that the module should be automatically multi-threaded (Chisel annotator). / case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlEnableModelMultiThreadingAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlEnableModelMultiThreadingAnnotation(parent.instOf(target.instanceName, target.name)) } } /* This specifies that the module should be automatically multi-threaded (FIRRTL annotation). / case class FirrtlEnableModelMultiThreadingAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /* This labels a target Mem so that it is extracted and replaced with a separate model. / case class MemModelAnnotation[T <: Data](target: MemBase[T]) extends ChiselAnnotation { def toFirrtl = FirrtlMemModelAnnotation(target.toNamed.toTarget) } case class FirrtlMemModelAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] { def duplicate(rt: ReferenceTarget) = this.copy(target = rt) } case class ExcludeInstanceAssertsAnnotation(target: (String, String)) extends firrtl.annotations.NoTargetAnnotation { def duplicate(n: (String, String)) = this.copy(target = n) } // TODO: Actually use a real target and not strings. object ExcludeInstanceAsserts { def apply(target: (String, String)): ChiselAnnotation = new ChiselAnnotation { def toFirrtl = ExcludeInstanceAssertsAnnotation(target) } } sealed trait PerfCounterOpType object PerfCounterOps { /* Takes the annotated UInt and adds it to an accumulation register generated in the bridge / case object Accumulate extends PerfCounterOpType /* Takes the annotated UInt and exposes it directly to the driver NB: Fields longer than 64b are not supported, and * must be divided into smaller segments that are sepearate annotated / case object Identity extends PerfCounterOpType } /* AutoCounter annotations. Do not emit the FIRRTL annotations unless you are writing a target transformation, use the * Chisel-side [[PerfCounter]] object instead. / case class AutoCounterFirrtlAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: ReferenceTarget, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, coverGenerated: Boolean = false, ) extends firrtl.annotations.Annotation with HasSerializationHints { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = renamer.exactRename(reset) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } // The AutoCounter tranform will reject this annotation if it's not enclosed def shouldBeIncluded(modList: Seq[String]): Boolean = !coverGenerated \|\| modList.contains(target.module) def enclosingModule(): String = target.module def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, enclosingModule()) def typeHints: Seq[Class[_]] = Seq(opType.getClass) } case class AutoCounterCoverModuleFirrtlAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation { def duplicate(n: ModuleTarget) = this.copy(target = n) } case class AutoCounterCoverModuleAnnotation(target: ModuleTarget) extends ChiselAnnotation { def toFirrtl = AutoCounterCoverModuleFirrtlAnnotation(target) } object PerfCounter { private def emitAnnotation( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType, ): Unit = { requireIsHardware(target, "Target passed to PerfCounter:") requireIsHardware(clock, "Clock passed to PerfCounter:") requireIsHardware(reset, "Reset passed to PerfCounter:") annotate(new ChiselAnnotation { def toFirrtl = AutoCounterFirrtlAnnotation(target.toTarget, clock.toTarget, reset.toTarget, label, description, opType) }) } /* Labels a signal as an event for which an host-side counter (an "AutoCounter") should be generated). Events can be * multi-bit to encode multiple occurances in a cycle (e.g., the number of instructions retired in a superscalar * processor). NB: Golden Gate will not generate the coutner unless AutoCounter is enabled in your the platform * config. See the docs.fires.im for end-to-end usage information. * * @param target * The number of occurances of the event (in the current cycle) * * @param clock * The clock to which this event is sychronized. * * @param reset * If the event is asserted while under the provide reset, it is not counted. TODO: This should be made optional. * * @param label * A verilog-friendly identifier for the event signal * * @param description * A human-friendly description of the event. * * @param opType * Defines how the bridge should be aggregated into a performance counter. / def apply( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, ): Unit = emitAnnotation(target, clock, reset, label, description, opType) /* A simplified variation of the full apply method above that uses the implicit clock and reset. / def apply(target: UInt, label: String, description: String): Unit = emitAnnotation(target, Module.clock, Module.reset, label, description, PerfCounterOps.Accumulate) /* Passes the annotated UInt through to the driver without accumulation. Use cases: * - Custom accumulation / counting logic not supported by the driver * - Providing runtime metadata along side standard accumulation registers * * Note: Under reset, the passthrough value is set to 0. This keeps event handling uniform in the transform. / def identity(target: UInt, label: String, description: String): Unit = { require( target.getWidth <= 64, s"""\|PerfCounter.identity can only accept fields <= 64b wide. Provided target for label: \| $label \|was ${target.getWidth}b.""".stripMargin, ) emitAnnotation(target, Module.clock, Module.reset, label, description, opType = PerfCounterOps.Identity) } } case class PlusArgFirrtlAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } object PlusArg { private def emitAnnotation( target: BaseModule ): Unit = { annotate(new ChiselAnnotation { def toFirrtl = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) PlusArgFirrtlAnnotation(parent.instOf(target.instanceName, target.name)) } }) } /* Labels a Rocket Chip 'plusarg_reader' module to synthesize. Must be of the type found in * https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/PlusArg.scala * * @param target * The 'plusarg_reader' module to synthesize / def apply(target: BaseModule): Unit = { emitAnnotation(target) } } // Need serialization utils to be upstreamed to FIRRTL before i can use these. //sealed trait TriggerSourceType //case object Credit extends TriggerSourceType //case object Debit extends TriggerSourceType case class TriggerSourceAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: Option[ReferenceTarget], sourceType: Boolean, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = reset.map(renamer.exactRename) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } case class TriggerSinkAnnotation( target: ReferenceTarget, clock: ReferenceTarget, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) Seq(this.copy(target = renamedTarget, clock = renamedClock)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) } object TriggerSource { private def annotateTrigger(tpe: Boolean)(target: Bool, reset: Option[Bool]): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val clock = WireDefault(Module.clock) reset.map(dontTouch.apply) requireIsHardware(target, "Target passed to TriggerSource:") reset.foreach { requireIsHardware(_, "Reset passed to TriggerSource:") } annotate(new ChiselAnnotation { def toFirrtl = TriggerSourceAnnotation(target.toNamed.toTarget, clock.toNamed.toTarget, reset.map(_.toTarget), tpe) }) } def annotateCredit = annotateTrigger(true) _ def annotateDebit = annotateTrigger(false) _ /* Methods to annotate a Boolean as a trigger credit or debit. Credits and debits issued while the module's implicit * reset is asserted are not counted. / def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.asBool)) def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.asBool)) def apply(creditSig: Bool, debitSig: Bool): Unit = { credit(creditSig) debit(debitSig) } /* Variations of the above methods that count credits and debits provided while the implicit reset is asserted. / def creditEvenUnderReset(credit: Bool): Unit = annotateCredit(credit, None) def debitEvenUnderReset(debit: Bool): Unit = annotateDebit(debit, None) def evenUnderReset(creditSig: Bool, debitSig: Bool): Unit = { creditEvenUnderReset(creditSig) debitEvenUnderReset(debitSig) } /* Level sensitive trigger sources. Implemented using [[credit]] and [[debit]]. Note: This generated hardware in your * target design. * * @param src * Enables the trigger when asserted. If no other credits have been issued since (e.g., a second level-sensitive * enable was asserted), the trigger is disabled when src is desasserted. / def levelSensitiveEnable(src: Bool): Unit = { val srcLast = RegNext(src) credit(src && !srcLast) debit(!src && srcLast) } } object TriggerSink { /* Marks a bool as receiving the global trigger signal. * * @param target * A Bool node that will be driven with the trigger * * @param noSourceDefault * The value that the trigger signal should take on if no trigger soruces are found in the target. This is a * temporary parameter required while this apply method generates a wire. Otherwise this can be punted to the * target's RTL. / def apply(target: Bool, noSourceDefault: => Bool = true.B): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val targetWire = WireDefault(noSourceDefault) val clock = Module.clock target := targetWire // Both the provided node and the generated one need to be dontTouched to stop // constProp from optimizing the down stream logic(?) dontTouch(target) annotate(new ChiselAnnotation { def toFirrtl = TriggerSinkAnnotation(targetWire.toTarget, clock.toTarget) }) } /* Syntatic sugar for a when context that is predicated by a trigger sink. Example usage: * {{{ * TriggerSink.whenEnabled { * printf(<...>) * } * }}} * * @param noSourceDefault * See [[TriggerSink.apply]]. / def whenEnabled(noSourceDefault: => Bool = true.B)(elaborator: => Unit): Unit = { val sinkEnable = Wire(Bool()) apply(sinkEnable, noSourceDefault) when(sinkEnable) { elaborator } } } case class RoCCBusyFirrtlAnnotation( target: ReferenceTarget, ready: ReferenceTarget, valid: ReferenceTarget, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedReady = renamer.exactRename(ready) val renamedValid = renamer.exactRename(valid) val renamedTarget = renamer.exactRename(target) Seq(this.copy(target = renamedTarget, ready = renamedReady, valid = renamedValid)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } object MakeRoCCBusyLatencyInsensitive { def apply( target: Bool, ready: Bool, valid: Bool, ): Unit = { requireIsHardware(target, "Target passed to ..:") requireIsHardware(ready, "Ready passed to ..:") requireIsHardware(valid, "Valid passed to ..:") annotate(new ChiselAnnotation { def toFirrtl = RoCCBusyFirrtlAnnotation(target.toNamed.toTarget, ready.toNamed.toTarget, valid.toNamed.toTarget) }) } } case class FirrtlPartWrapperParentAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } case class FirrtlPortToNeighborRouterIdxAnno( target: ReferenceTarget, extractNeighborIdx: Int, removeNeighborIdx: Int, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } case class FirrtlCombLogicInsideModuleAnno( target: ReferenceTarget ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module L2MemHelperLatencyInjection_2( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [70:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [70:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_userif_req_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire request_input_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_74 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_75 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_76 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] a_mask_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] _a_mask_sizeOH_T_2 = 5'h0; // @[OneHot.scala:65:27] wire [4:0] _a_mask_sizeOH_T_5 = 5'h0; // @[OneHot.scala:65:27] wire [2:0] io_userif_req_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] request_input_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:44:27] wire [2:0] a_mask_sizeOH_shiftAmount = 3'h5; // @[OneHot.scala:64:49] wire [2:0] a_mask_sizeOH_shiftAmount_1 = 3'h5; // @[OneHot.scala:64:49] wire [255:0] io_userif_req_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] request_input_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] bundle_mask = 32'hFFFFFFFF; // @[Edges.scala:460:17] wire [31:0] _a_mask_T = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [31:0] bundle_1_mask = 32'hFFFFFFFF; // @[Edges.scala:480:17] wire [31:0] _a_mask_T_1 = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [4:0] a_mask_sizeOH = 5'h1; // @[Misc.scala:202:81] wire [4:0] a_mask_sizeOH_1 = 5'h1; // @[Misc.scala:202:81] wire [7:0] _a_mask_sizeOH_T_1 = 8'h20; // @[OneHot.scala:65:12] wire [7:0] _a_mask_sizeOH_T_4 = 8'h20; // @[OneHot.scala:65:12] wire [4:0] _a_mask_sizeOH_T = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = 5'h5; // @[OneHot.scala:64:31] wire [4:0] _a_mask_sizeOH_T_3 = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = 5'h5; // @[OneHot.scala:64:31] wire [3:0] bundle_size = 4'h5; // @[Edges.scala:460:17] wire [3:0] bundle_1_size = 4'h5; // @[Edges.scala:480:17] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire [70:0] addr_mask_check = 71'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [71:0] _addr_mask_check_T_1 = 72'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [70:0] _addr_mask_check_T = 71'h20; // @[L2MemHelperLatencyInjection.scala:108:36] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [70:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = request_input_bits_addr & 71'h1F; // @[L2MemHelperLatencyInjection.scala:44:27, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T \| _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 \| _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 \| _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 \| _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 \| _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 \| _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 \| _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 \| _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_60; // @[Parameters.scala:684:54, :685:42] wire legal = _legal_T_62 \| _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_eq_16; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_eq_17; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_eq_18; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_eq_19; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_eq_20; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_eq_21; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_eq_22; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_eq_23; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_eq_24; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_eq_25; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_eq_26; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_eq_27; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_eq_28; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_eq_29; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_eq_30; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [510:0] _T_31 = 511'h0 << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 \| _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 \| _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 \| _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 \| _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 \| _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 \| _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 \| _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_123; // @[Parameters.scala:684:54, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 \| _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_eq_32; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_eq_33; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_eq_34; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_eq_35; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_eq_36; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_eq_37; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_eq_38; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_eq_39; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_eq_40; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_eq_41; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_eq_42; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_eq_43; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_eq_44; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_eq_45; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_eq_46; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_eq_47; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_eq_48; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_eq_49; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_eq_50; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_eq_51; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_eq_52; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_eq_53; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_eq_54; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_eq_55; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_eq_56; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_eq_57; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_eq_58; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_eq_59; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_eq_60; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_eq_61; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_eq_62; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_eq_63; // @[Misc.scala:214:27, :215:38] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 \| _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 \| _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 \| _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 \| _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 \| _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 \| _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 \| _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 \| _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 \| _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 \| _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 \| _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 \| _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 \| _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 \| _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 \| _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 \| _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 \| _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 \| _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 \| _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 \| _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 \| _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 \| _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 \| _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 \| _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 \| _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 \| _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 \| _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 \| _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 \| _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 \| _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 \| _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [70:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {66'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 \| _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 \| _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 \| _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 \| _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 \| _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 \| _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 \| _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 \| _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 \| _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 \| _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 \| _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 \| _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 \| _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 \| _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 \| _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 \| _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 \| _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 \| _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 \| _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 \| _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 \| _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 \| _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 \| _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 \| _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 \| _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 \| _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 \| _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 \| _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 \| _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 \| _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 \| _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_57 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_57 \| _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_57 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_156 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_160 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_163 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_166 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_169 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_172 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_175 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_178 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_181 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_184 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_187 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_190 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_193 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_196 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_199 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_202 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_205 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_208 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_211 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_214 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_217 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_220 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_223 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_226 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_229 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_232 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_235 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_238 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_241 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_244 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_247 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_250 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 \| _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 \| _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 \| _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 \| _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 \| _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 \| _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 \| _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 \| _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 \| _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 \| _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 \| _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 \| _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 \| _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 \| _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 \| _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 \| _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 \| _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 \| _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 \| _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 \| _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 \| _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 \| _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 \| _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 \| _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 \| _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 \| _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 \| _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 \| _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 \| _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 \| _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 \| _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_8 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data \| resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T \| resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 \| resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 \| resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 \| resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 \| resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 \| resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 \| resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 \| resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 \| resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 \| resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 \| resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 \| resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 \| resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 \| resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 \| resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 \| resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 \| resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 \| resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 \| resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 \| resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 \| resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 \| resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 \| resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 \| resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 \| resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 \| resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 \| resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 \| resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 \| resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 \| resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_252 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] wire _T_270 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidthcoreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool \|\| io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid \|\| io.cpu.sfence.valid \|\| io.cpu.flush_icache \|\| io.cpu.bht_update.valid \|\| io.cpu.btb_update.valid) \|\| io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) \|\| (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid \|\| !s2_valid)) \|\| (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid \|\| s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst \|\| s2_tlb_resp.pf.inst \|\| s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc \| (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) \|\| RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative \|\| s2_valid && !s2_speculative \|\| predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytesfetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid \|\| s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect \|\| tlb.io.resp.miss \|\| s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill \|\| s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) \|\| (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay \|\| icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) \|\| (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc \| (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits(idx+1)-1, coreInstBitsidx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR \|\| rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ \|\| bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J \|\| rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL \|\| rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken \|\| force_taken val taken = prevRVI && (rviJump \|\| rviJALR \|\| rviBranch && predict_taken) \|\| valid && (rvcJump \|\| rvcJALR \|\| rvcJR \|\| rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn \|\| valid && rvcReturn) val predictJump = prevRVI && rviJump \|\| valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch \|\| valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall \|\| rviReturn) \|\| valid && (rvcCall \|\| rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch \|\| predictJump)) { val pc = s2_base_pc \| (idxcoreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch \|\| valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken \|\| predictJump \|\| predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits \| 0x3.U } } prevTaken \|\| taken } else { scanInsns(idx + 1, valid, bits, prevTaken \|\| taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc \| (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken \|\| taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid \|\| fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B \|\| io.cpu.might_request \|\| // chicken bit icache.io.keep_clock_enabled \|\| // I$ miss or ITIM access s1_valid \|\| s2_valid \|\| // some fetch in flight !tlb.io.req.ready \|\| // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc \| (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /* Mix-ins for constructing tiles that have an ICache-based pipeline frontend / trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Frontend( // @[Frontend.scala:82:7] input clock, // @[Frontend.scala:82:7] input reset, // @[Frontend.scala:82:7] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_cpu_might_request, // @[Frontend.scala:85:14] input io_cpu_req_valid, // @[Frontend.scala:85:14] input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14] input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14] input io_cpu_sfence_valid, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14] input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14] input io_cpu_resp_ready, // @[Frontend.scala:85:14] output io_cpu_resp_valid, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14] output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14] output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14] output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14] output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14] input io_cpu_btb_update_valid, // @[Frontend.scala:85:14] input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14] input io_cpu_bht_update_valid, // @[Frontend.scala:85:14] input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14] input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14] input io_cpu_flush_icache, // @[Frontend.scala:85:14] input io_cpu_progress, // @[Frontend.scala:85:14] input io_ptw_req_ready, // @[Frontend.scala:85:14] output io_ptw_req_valid, // @[Frontend.scala:85:14] output io_ptw_req_bits_valid, // @[Frontend.scala:85:14] output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14] output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14] input io_ptw_resp_valid, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14] input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14] input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14] input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14] input io_ptw_status_debug, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_0_value // @[Frontend.scala:85:14] ); wire s2_redirect; // @[Frontend.scala:145:32, :336:26, :337:20, :341:{31,45}] wire [38:0] predicted_npc; // @[Frontend.scala:270:25, :330:19, :331:21] wire updateBTB; // @[Frontend.scala:270:25, :298:125, :299:21] wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40] wire [1:0] after_idx; // @[Frontend.scala:270:25, :272:19] wire taken_taken; // @[Frontend.scala:255:71] wire [38:0] _io_cpu_npc_T; // @[Frontend.scala:186:28] wire fq_io_enq_valid; // @[Frontend.scala:184:{40,52}] wire _btb_io_resp_valid; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21] wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21] wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21] wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21] wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21] wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21] wire _tlb_io_resp_miss; // @[Frontend.scala:105:19] wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19] wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19] wire _tlb_io_ptw_req_valid; // @[Frontend.scala:105:19] wire _fq_io_enq_ready; // @[Frontend.scala:91:64] wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64] wire _icache_io_resp_valid; // @[Frontend.scala:70:26] wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26] wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26] reg s1_valid; // @[Frontend.scala:107:21] reg s2_valid; // @[Frontend.scala:108:25] wire s0_valid = io_cpu_req_valid \| ~(_fq_io_mask[2]) \| ~(_fq_io_mask[3]) & (~s1_valid \| ~s2_valid) \| ~(_fq_io_mask[4]) & ~s1_valid & ~s2_valid; // @[Frontend.scala:91:64, :107:21, :108:25, :110:{5,16,40}, :111:{6,17,41,45,55,58,70}, :112:{6,17,41,55}, :113:35] reg [39:0] s1_pc; // @[Frontend.scala:115:18] reg s1_speculative; // @[Frontend.scala:116:27] reg [39:0] s2_pc; // @[Frontend.scala:117:22] reg s2_btb_resp_valid; // @[Frontend.scala:118:44] reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29] reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29] reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29] reg taken_predict_taken; // @[Frontend.scala:119:29] wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40] reg s2_tlb_resp_miss; // @[Frontend.scala:121:24] reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24] wire _s2_xcpt_T = s2_tlb_resp_ae_inst \| s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37] reg s2_speculative; // @[Frontend.scala:123:31] reg s2_partial_insn_valid; // @[Frontend.scala:124:38] reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28] reg wrong_path; // @[Frontend.scala:126:27] wire [39:0] _ntpc_T = {s1_pc[39:2], 2'h0} + 40'h4; // @[Frontend.scala:115:18, :129:25] wire _taken_T_57 = _fq_io_enq_ready & fq_io_enq_valid; // @[Decoupled.scala:51:35] reg s2_replay_REG; // @[Frontend.scala:134:56] wire s2_replay = s2_valid & ~_taken_T_57 \| s2_replay_REG; // @[Decoupled.scala:51:35] reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40] wire s2_kill_speculative_tlb_refill = s2_speculative & recent_progress_counter == 2'h0; // @[Frontend.scala:123:31, :155:40, :156:49, :160:{55,58}] wire icache_io_s2_kill = s2_speculative & ~(s2_tlb_resp_cacheable & ~(io_ptw_customCSRs_csrs_0_value[3])) \| _s2_xcpt_T; // @[CustomCSRs.scala:46:69] reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29] wire _fq_io_enq_bits_replay_T_5 = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112] assign fq_io_enq_valid = fq_io_enq_valid_REG & s2_valid & (_icache_io_resp_valid \| _fq_io_enq_bits_replay_T_5 \| ~s2_tlb_resp_miss & icache_io_s2_kill); // @[Frontend.scala:70:26, :108:25, :121:24, :180:71, :184:{29,40,52,77,112,133,137,155}] assign _io_cpu_npc_T = io_cpu_req_valid ? io_cpu_req_bits_pc[39:1] : s2_replay ? s2_pc[39:1] : predicted_npc; // @[Frontend.scala:85:14, :117:22, :134:46, :135:16, :186:28, :270:25, :330:19, :331:21] wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << s2_pc[1]; // @[package.scala:163:13] wire predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:198:21, :213:29] wire [38:0] _GEN = {s2_pc[38:2], 2'h0}; // @[Frontend.scala:117:22, :323:36, :324:33] wire taken_prevRVI = s2_partial_insn_valid & (&(s2_partial_insn[1:0])); // @[Frontend.scala:124:38, :125:28, :233:{39,45}, :234:31] wire taken_valid = _fq_io_enq_bits_mask_T_1[0] & ~taken_prevRVI; // @[Frontend.scala:189:50, :234:31, :235:{38,44,47}] wire taken_rviBranch = s2_partial_insn[6:0] == 7'h63; // @[Frontend.scala:125:28, :239:{30,36}] wire taken_rviJump = s2_partial_insn[6:0] == 7'h6F; // @[Frontend.scala:125:28, :239:30, :240:34] wire taken_rviJALR = s2_partial_insn[6:0] == 7'h67; // @[Frontend.scala:125:28, :239:30, :241:34] wire taken_rviReturn = taken_rviJALR & ~(s2_partial_insn[7]) & {_icache_io_resp_bits_data[3:2], _icache_io_resp_bits_data[0], s2_partial_insn[15]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :125:28, :241:34, :242:{31,34,42,46,66,77}] wire _taken_taken_T = taken_rviJALR \| taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30] wire taken_rviCall = _taken_taken_T & s2_partial_insn[7]; // @[Frontend.scala:125:28, :242:42, :243:{30,42}] wire [4:0] _GEN_0 = {_icache_io_resp_bits_data[15:13], _icache_io_resp_bits_data[1:0]}; // @[Frontend.scala:70:26, :244:28] wire taken_rvcBranch = _GEN_0 == 5'h19 \| _GEN_0 == 5'h1D; // @[Frontend.scala:244:{28,52,60}] wire taken_rvcJump = {_icache_io_resp_bits_data[15:13], _icache_io_resp_bits_data[1:0]} == 5'h15; // @[Frontend.scala:70:26, :236:37, :244:28, :246:26] wire taken_rvcJR = {_icache_io_resp_bits_data[15:12], _icache_io_resp_bits_data[1:0]} == 6'h22 & ~(\|(_icache_io_resp_bits_data[6:2])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,46,53,59}] wire taken_rvcReturn = taken_rvcJR & {_icache_io_resp_bits_data[11:10], _icache_io_resp_bits_data[8:7]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :236:37, :248:46, :249:{29,49,57}] wire taken_rvcJALR = {_icache_io_resp_bits_data[15:12], _icache_io_resp_bits_data[1:0]} == 6'h26 & ~(\|(_icache_io_resp_bits_data[6:2])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,53,59}, :250:{26,49,62}] assign taken_taken = taken_prevRVI & (_taken_taken_T \| taken_rviBranch & taken_predict_taken) \| taken_valid & (taken_rvcJump \| taken_rvcJALR \| taken_rvcJR \| taken_rvcBranch & taken_predict_taken); // @[Frontend.scala:119:29, :234:31, :235:44, :239:36, :243:30, :244:52, :246:26, :248:46, :250:49, :255:{17,40,53,71}, :256:{15,27,38,47,60}] wire taken_predictReturn = _btb_io_ras_head_valid & (taken_prevRVI & taken_rviReturn \| taken_valid & taken_rvcReturn); // @[Frontend.scala:198:21, :234:31, :235:44, :242:{31,46}, :249:29, :257:{49,61,74,83}] wire taken_predictJump = taken_prevRVI & taken_rviJump \| taken_valid & taken_rvcJump; // @[Frontend.scala:234:31, :235:44, :240:34, :246:26, :258:{33,44,53}] wire _taken_T_19 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_T_20 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75] wire taken_predictBranch = taken_predict_taken & (_taken_T_19 \| _taken_T_20); // @[Frontend.scala:119:29, :259:{41,53,66,75}] wire _taken_T_29 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22] wire _taken_T_5 = _taken_T_29 & ~s2_btb_resp_bits_bridx & taken_valid & (&(_icache_io_resp_bits_data[1:0])); // @[Frontend.scala:70:26, :119:29, :233:{39,45}, :235:44, :236:37, :261:{22,43,69,79,88}] wire [32:0] _taken_npc_T_2 = taken_prevRVI ? {{13{_icache_io_resp_bits_data[15]}}, s2_partial_insn[3] ? {_icache_io_resp_bits_data[3:0], s2_partial_insn[15:12], _icache_io_resp_bits_data[4], _icache_io_resp_bits_data[14:5]} : {{8{_icache_io_resp_bits_data[15]}}, s2_partial_insn[7], _icache_io_resp_bits_data[14:9], s2_partial_insn[11:8]}, 1'h0} - 33'h2 : {{22{_icache_io_resp_bits_data[12]}}, _icache_io_resp_bits_data[14] ? {{3{_icache_io_resp_bits_data[12]}}, _icache_io_resp_bits_data[6:5], _icache_io_resp_bits_data[2], _icache_io_resp_bits_data[11:10], _icache_io_resp_bits_data[4:3]} : {_icache_io_resp_bits_data[8], _icache_io_resp_bits_data[10:9], _icache_io_resp_bits_data[6], _icache_io_resp_bits_data[7], _icache_io_resp_bits_data[2], _icache_io_resp_bits_data[11], _icache_io_resp_bits_data[5:3]}, 1'h0}; // @[RocketCore.scala:1341:44, :1343:65, :1345:39, :1347:62, :1349:57, :1355:8] wire [39:0] _taken_npc_T_3 = {s2_pc[39:2], 2'h0} + {{7{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:117:22, :289:{39,44}] wire taken_prevRVI_1 = taken_valid & (&(_icache_io_resp_bits_data[1:0])); // @[Frontend.scala:70:26, :233:{39,45}, :234:31, :235:44, :236:37] wire taken_valid_1 = _fq_io_enq_bits_mask_T_1[1] & ~taken_prevRVI_1; // @[Frontend.scala:189:50, :234:31, :235:{38,44,47}] wire taken_rviBranch_1 = _icache_io_resp_bits_data[6:0] == 7'h63; // @[Frontend.scala:70:26, :239:{30,36}] wire taken_rviJump_1 = _icache_io_resp_bits_data[6:0] == 7'h6F; // @[Frontend.scala:70:26, :239:30, :240:34] wire taken_rviJALR_1 = _icache_io_resp_bits_data[6:0] == 7'h67; // @[Frontend.scala:70:26, :239:30, :241:34] wire taken_rviReturn_1 = taken_rviJALR_1 & ~(_icache_io_resp_bits_data[7]) & {_icache_io_resp_bits_data[19:18], _icache_io_resp_bits_data[16:15]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :241:34, :242:{31,34,42,46,66,77}] wire _taken_taken_T_9 = taken_rviJALR_1 \| taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30] wire taken_rviCall_1 = _taken_taken_T_9 & _icache_io_resp_bits_data[7]; // @[Frontend.scala:70:26, :242:42, :243:{30,42}] wire [4:0] _GEN_1 = {_icache_io_resp_bits_data[31:29], _icache_io_resp_bits_data[17:16]}; // @[Frontend.scala:70:26, :244:28] wire taken_rvcBranch_1 = _GEN_1 == 5'h19 \| _GEN_1 == 5'h1D; // @[Frontend.scala:244:{28,52,60}] wire taken_rvcJump_1 = {_icache_io_resp_bits_data[31:29], _icache_io_resp_bits_data[17:16]} == 5'h15; // @[Frontend.scala:70:26, :236:37, :244:28, :246:26] wire taken_rvcJR_1 = {_icache_io_resp_bits_data[31:28], _icache_io_resp_bits_data[17:16]} == 6'h22 & ~(\|(_icache_io_resp_bits_data[22:18])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,46,53,59}] wire taken_rvcReturn_1 = taken_rvcJR_1 & {_icache_io_resp_bits_data[27:26], _icache_io_resp_bits_data[24:23]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :236:37, :248:46, :249:{29,49,57}] wire taken_rvcJALR_1 = {_icache_io_resp_bits_data[31:28], _icache_io_resp_bits_data[17:16]} == 6'h26 & ~(\|(_icache_io_resp_bits_data[22:18])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,53,59}, :250:{26,49,62}] wire taken_taken_1 = taken_prevRVI_1 & (_taken_taken_T_9 \| taken_rviBranch_1 & taken_predict_taken) \| taken_valid_1 & (taken_rvcJump_1 \| taken_rvcJALR_1 \| taken_rvcJR_1 \| taken_rvcBranch_1 & taken_predict_taken); // @[Frontend.scala:119:29, :234:31, :235:44, :239:36, :243:30, :244:52, :246:26, :248:46, :250:49, :255:{17,40,53,71}, :256:{15,27,38,47,60}] wire taken_predictReturn_1 = _btb_io_ras_head_valid & (taken_prevRVI_1 & taken_rviReturn_1 \| taken_valid_1 & taken_rvcReturn_1); // @[Frontend.scala:198:21, :234:31, :235:44, :242:{31,46}, :249:29, :257:{49,61,74,83}] wire taken_predictJump_1 = taken_prevRVI_1 & taken_rviJump_1 \| taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:234:31, :235:44, :240:34, :246:26, :258:{33,44,53}] wire _taken_T_48 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_T_49 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75] wire taken_predictBranch_1 = taken_predict_taken & (_taken_T_48 \| _taken_T_49); // @[Frontend.scala:119:29, :259:{41,53,66,75}] wire _taken_T_34 = _taken_T_29 & s2_btb_resp_bits_bridx & taken_valid_1 & (&(_icache_io_resp_bits_data[17:16])); // @[Frontend.scala:70:26, :119:29, :233:{39,45}, :235:44, :236:37, :261:{22,43,79,88}] assign after_idx = taken_taken ? 2'h1 : 2'h2; // @[Frontend.scala:255:71, :270:25, :272:19] assign btb_io_ras_update_bits_cfiType = taken_taken ? ((taken_prevRVI ? taken_rviReturn : taken_rvcReturn) ? 2'h3 : (taken_prevRVI ? taken_rviCall : taken_rvcJALR) ? 2'h2 : {1'h0, ~(taken_prevRVI ? taken_rviBranch : taken_rvcBranch)}) : (taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1) ? 2'h3 : (taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcJALR_1) ? 2'h2 : {1'h0, ~(taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1)}; // @[Frontend.scala:234:31, :239:36, :242:{31,46}, :243:42, :244:52, :249:29, :250:49, :255:71, :270:25, :274:{40,46,50}, :275:{46,50}, :276:{46,50}] wire [30:0] _GEN_2 = taken_prevRVI_1 ? {{12{_icache_io_resp_bits_data[31]}}, _icache_io_resp_bits_data[3] ? {_icache_io_resp_bits_data[19:12], _icache_io_resp_bits_data[20], _icache_io_resp_bits_data[30:21]} : {{8{_icache_io_resp_bits_data[31]}}, _icache_io_resp_bits_data[7], _icache_io_resp_bits_data[30:25], _icache_io_resp_bits_data[11:8]}} : {{21{_icache_io_resp_bits_data[28]}}, _icache_io_resp_bits_data[30] ? {{3{_icache_io_resp_bits_data[28]}}, _icache_io_resp_bits_data[22:21], _icache_io_resp_bits_data[18], _icache_io_resp_bits_data[27:26], _icache_io_resp_bits_data[20:19]} : {_icache_io_resp_bits_data[24], _icache_io_resp_bits_data[26:25], _icache_io_resp_bits_data[22], _icache_io_resp_bits_data[23], _icache_io_resp_bits_data[18], _icache_io_resp_bits_data[27], _icache_io_resp_bits_data[21:19]}}; // @[RocketCore.scala:1341:44, :1343:65, :1345:39, :1347:62, :1349:57, :1355:8] wire [39:0] _taken_npc_T_10 = (taken_prevRVI_1 ? {s2_pc[39:2], 2'h2} - 40'h2 : {s2_pc[39:2], 2'h2}) + {{8{_GEN_2[30]}}, _GEN_2, 1'h0}; // @[Frontend.scala:117:22, :234:31, :287:33, :290:{23,36,66,71}] assign updateBTB = ~taken_taken & ~s2_btb_resp_valid & (taken_predictBranch_1 \| taken_predictJump_1 \| taken_predictReturn_1) \| ~s2_btb_resp_valid & (taken_predictBranch \| taken_predictJump \| taken_predictReturn); // @[Frontend.scala:118:44, :255:71, :257:49, :258:44, :259:41, :270:{13,25}, :298:{15,34,91,106,125}, :299:21] wire taken = taken_taken \| taken_taken_1; // @[Frontend.scala:255:71, :311:19] assign predicted_npc = ~taken_taken & ~s2_btb_taken & s2_valid & taken_predictReturn_1 \| ~s2_btb_taken & s2_valid & taken_predictReturn ? {1'h0, _btb_io_ras_head_bits[38:1]} : ~taken_taken & ~s2_btb_taken & s2_valid & (taken_predictBranch_1 \| taken_predictJump_1) ? _taken_npc_T_10[39:1] : ~s2_btb_taken & s2_valid & (taken_predictBranch \| taken_predictJump) ? _taken_npc_T_3[39:1] : predicted_taken ? {_btb_io_resp_bits_target[38], _btb_io_resp_bits_target[38:1]} : _ntpc_T[39:1]; // @[package.scala:132:{15,38}] wire _GEN_3 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34] assign s2_redirect = ~s2_btb_taken & taken & _taken_T_57 \| io_cpu_req_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_191( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_347 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File LatencyInjectionQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import freechips.rocketchip.util.DecoupledHelper class LatencyInjectionQueue[T <: Data](data: T, depth: Int) extends Module { val io = IO(new Bundle { val latency_cycles = Input(UInt(64.W)) val enq = Flipped(Decoupled(data)) val deq = Decoupled(data) }) val cur_cycle = RegInit(0.U(64.W)) cur_cycle := cur_cycle + 1.U val queue = Module(new Queue(data, depth)) val release_ready_cycle_q = Module(new Queue(UInt(64.W), depth)) release_ready_cycle_q.io.enq.bits := cur_cycle + io.latency_cycles queue.io.enq.bits := io.enq.bits io.deq.bits := queue.io.deq.bits val enq_fire = DecoupledHelper( queue.io.enq.ready, release_ready_cycle_q.io.enq.ready, io.enq.valid ) queue.io.enq.valid := enq_fire.fire(queue.io.enq.ready) release_ready_cycle_q.io.enq.valid := enq_fire.fire(release_ready_cycle_q.io.enq.ready) io.enq.ready := enq_fire.fire(io.enq.valid) val deq_fire = DecoupledHelper( queue.io.deq.valid, release_ready_cycle_q.io.deq.valid, release_ready_cycle_q.io.deq.bits <= cur_cycle, io.deq.ready ) queue.io.deq.ready := deq_fire.fire(queue.io.deq.valid) release_ready_cycle_q.io.deq.ready := deq_fire.fire(release_ready_cycle_q.io.deq.valid) io.deq.valid := deq_fire.fire(io.deq.ready) }	module LatencyInjectionQueue_35( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14] input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14] input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14] input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue64_TLBundleD_a32d256s5k3z4u_13 queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode), .io_deq_bits_param (io_deq_bits_param), .io_deq_bits_size (io_deq_bits_size), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_sink (io_deq_bits_sink), .io_deq_bits_denied (io_deq_bits_denied), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt) ); // @[LatencyInjectionQueue.scala:18:21] Queue64_UInt64_27 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_3( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File functional-unit.scala: //*************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v4.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import freechips.rocketchip.rocket.ALU._ import boom.v4.common._ import boom.v4.ifu._ import boom.v4.util._ / * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit / class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val ftq_info = Vec(2, new FTQInfo) // Need this-pc and next-pc for JALR val pred_data = Bool() val imm_data = UInt(xLen.W) // only used for integer ALU and AGen units } class BrInfoBundle(implicit p: Parameters) extends BoomBundle { val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) } /* * Branch resolution information given from the branch unit / class BrResolutionInfo(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt(21.W) } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /* * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? / abstract class FunctionalUnit( val dataWidth: Int, val isAluUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val kill = Input(Bool()) val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new ExeUnitResp(dataWidth))) //val fflags = new ValidIO(new FFlagsResp) val brupdate = Input(new BrUpdateInfo()) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(Valid(new BrResolutionInfo)) else null }) io.resp.bits.fflags.valid := false.B io.resp.bits.fflags.bits := DontCare io.resp.bits.predicated := false.B } /* * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit / class ALUUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isAluUnit = true, dataWidth = dataWidth) with boom.v4.ifu.HasBoomFrontendParameters with freechips.rocketchip.rocket.constants.ScalarOpConstants { io.req.ready := true.B val uop = io.req.bits.uop // immediate generation val imm_xprlen = io.req.bits.imm_data //ImmGen(uop.imm_packed, uop.imm_sel) // operand 1 select // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.req.bits.ftq_info(0).pc, icBlockBytes) val uop_pc = (block_pc \| uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) val op1_shamt = Mux(uop.fcn_op === FN_ADD, io.req.bits.uop.pimm(2,1), 0.U) val op1_shl = Mux(uop.fcn_dw === DW_32, // shaddw io.req.bits.rs1_data(31,0), io.req.bits.rs1_data) << op1_shamt val op1_data = MuxLookup(uop.op1_sel, 0.U)(Seq( OP1_RS1 -> io.req.bits.rs1_data, OP1_PC -> Sext(uop_pc, xLen), OP1_RS1SHL -> op1_shl )) // operand 2 select val op2_oh = UIntToOH(Mux(uop.op2_sel(0), // rs1 io.req.bits.rs2_data, imm_xprlen)(log2Ceil(xLen)-1,0)) val op2_data = MuxLookup(uop.op2_sel, 0.U)(Seq( OP2_IMM -> Sext(imm_xprlen, xLen), OP2_IMMC -> io.req.bits.uop.prs1(4,0), OP2_RS2 -> io.req.bits.rs2_data, OP2_NEXT -> Mux(uop.is_rvc, 2.U, 4.U), OP2_RS2OH -> op2_oh, OP2_IMMOH -> op2_oh )) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.fcn_op alu.io.dw := Mux(uop.op1_sel === OP1_RS1SHL, DW_64, uop.fcn_dw) val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu \| rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.br_type, PC_PLUS4)( Seq( B_N -> PC_PLUS4, B_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), B_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), B_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), B_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), B_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), B_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), B_J -> PC_BRJMP, B_JR -> PC_JALR )) val is_taken = io.req.valid && (uop.br_type =/= BR_N) && (pc_sel =/= PC_PLUS4) // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S \|\| a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && uop.is_jal val is_jalr = io.req.valid && uop.is_jalr val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt val cfi_idx = ((uop.pc_lob ^ Mux(io.req.bits.ftq_info(0).entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (is_br \|\| is_jalr) { when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } when (pc_sel === PC_JALR) { mispredict := (!io.req.bits.ftq_info(1).valid \|\| (io.req.bits.ftq_info(1).pc =/= jalr_target) \|\| !io.req.bits.ftq_info(0).entry.cfi_idx.valid \|\| (io.req.bits.ftq_info(0).entry.cfi_idx.bits =/= cfi_idx)) } } val brinfo = Wire(Valid(new BrResolutionInfo)) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br \|\| is_jalr brinfo.bits.mispredict := mispredict brinfo.bits.uop := uop brinfo.bits.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.bits.taken := is_taken brinfo.bits.pc_sel := pc_sel brinfo.bits.jalr_target := DontCare brinfo.bits.jalr_target := jalr_target brinfo.bits.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.is_mov, io.req.bits.rs2_data, alu.io.out)) io.resp.valid := io.req.valid io.resp.bits.uop := io.req.bits.uop io.resp.bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) io.resp.bits.predicated := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data assert(io.resp.ready) } /* * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. / class FPUUnit(implicit p: Parameters) extends FunctionalUnit( //numBypassStages = 0, dataWidth = 65, needsFcsr = true) { io.req.ready := true.B val numStages = p(tile.TileKey).core.fpu.get.dfmaLatency val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), numStages)) pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.valid := pipe.io.resp(numStages-1).valid io.resp.bits.uop := pipe.io.resp(numStages-1).bits.uop io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits := fpu.io.resp.bits.fflags.bits } /* * Int to FP conversion functional unit * * @param latency the amount of stages to delay by / class IntToFPUnit(latency: Int)(implicit p: Parameters) extends FunctionalUnit( //numBypassStages = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val io_req = io.req.bits io.req.ready := true.B val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), latency)) pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate val fp_ctrl = io_req.uop.fp_ctrl val fp_rm = Mux(io_req.uop.fp_rm === 7.U, io.fcsr_rm, io_req.uop.fp_rm) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) <> fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := io_req.uop.fp_typ req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits io.resp.valid := pipe.io.resp(latency-1).valid io.resp.bits.uop := pipe.io.resp(latency-1).bits.uop io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits := ifpu.io.out.bits.exc } /* * Divide functional unit. * * @param dataWidth data to be passed into the functional unit / class DivUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit(dataWidth = dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) val req = Reg(Valid(new MicroOp())) when (io.req.fire) { req.valid := !IsKilledByBranch(io.brupdate, io.kill, io.req.bits) req.bits := UpdateBrMask(io.brupdate, io.req.bits.uop) } .otherwise { req.valid := !IsKilledByBranch(io.brupdate, io.kill, req.bits) && req.valid req.bits := UpdateBrMask(io.brupdate, req.bits) } when (reset.asBool) { req.valid := false.B } // request div.io.req.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.kill, io.req.bits) div.io.req.bits.dw := io.req.bits.uop.fcn_dw div.io.req.bits.fn := io.req.bits.uop.fcn_op div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready && !req.valid // handle pipeline kills and branch misspeculations div.io.kill := (req.valid && IsKilledByBranch(io.brupdate, io.kill, req.bits)) // response io.resp.valid := div.io.resp.valid && req.valid div.io.resp.ready := io.resp.ready io.resp.valid := div.io.resp.valid && req.valid io.resp.bits.data := div.io.resp.bits.data io.resp.bits.uop := req.bits when (io.resp.fire) { req.valid := false.B } } /* * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit / class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit(dataWidth = dataWidth) { io.req.ready := true.B val imul = Module(new PipelinedMultiplier(xLen, numStages)) val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.fcn_op imul.io.req.bits.dw := io.req.bits.uop.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate // response io.resp.valid := pipe.io.resp(numStages-1).valid io.resp.bits.uop := pipe.io.resp(numStages-1).bits.uop io.resp.bits.data := imul.io.resp.bits.data io.resp.bits.predicated := false.B } File micro-op.scala: //***************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.common import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ import org.chipsalliance.cde.config.Parameters abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = Vec(IQ_SZ, Bool()) // which issue unit do we use? val fu_code = Vec(FC_SZ, Bool()) // which functional unit do we use? val iw_issued = Bool() // Was this uop issued last cycle? If so, it can vacate this cycle val iw_issued_partial_agen = Bool() val iw_issued_partial_dgen = Bool() val iw_p1_speculative_child = UInt(aluWidth.W) val iw_p2_speculative_child = UInt(aluWidth.W) // Get the operand off the bypass network, avoid a register read port allocation val iw_p1_bypass_hint = Bool() val iw_p2_bypass_hint = Bool() val iw_p3_bypass_hint = Bool() val dis_col_sel = UInt(coreWidth.W) // If using column-issue ALUs with 1-wide dispatch, which column to issue to? val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) val br_type = UInt(4.W) val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val is_fence = Bool() val is_fencei = Bool() val is_sfence = Bool() val is_amo = Bool() val is_eret = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_rocc = Bool() val is_mov = Bool() // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_rename = Bool() val imm_sel = UInt(IS_N.getWidth.W) val pimm = UInt(immPregSz.W) val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val fp_ctrl = new freechips.rocketchip.tile.FPUCtrlSigs val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) // Predication def is_br = br_type.isOneOf(B_NE, B_EQ, B_GE, B_GEU, B_LT, B_LTU) def is_jal = br_type === B_J def is_jalr = br_type === B_JR def is_sfb_br = br_type =/= B_N && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = br_type === B_N && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() val fcn_dw = Bool() val fcn_op = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_rm = UInt(3.W) val fp_typ = UInt(2.W) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) \|\| is_jalr def starts_bsy = !(is_fence \|\| is_fencei) // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def starts_unsafe = uses_ldq \|\| (uses_stq && !is_fence) \|\| is_br \|\| is_jalr }	module ALUUnit( // @[functional-unit.scala:133:7] input clock, // @[functional-unit.scala:133:7] input reset, // @[functional-unit.scala:133:7] input io_kill, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [11:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [11:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14] ); wire [63:0] _alu_io_out; // @[functional-unit.scala:173:19] wire io_kill_0 = io_kill; // @[functional-unit.scala:133:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [11:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:133:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:133:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:133:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:133:7] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[functional-unit.scala:234:90] wire [39:0] _block_pc_T = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [39:0] _block_pc_T_1 = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[util.scala:245:5] wire [39:0] block_pc = 40'h0; // @[util.scala:245:5] wire [3:0] io_req_bits_ftq_info_0_entry_br_mask = 4'h0; // @[functional-unit.scala:105:14, :133:7, :234:35] wire [3:0] io_req_bits_ftq_info_1_entry_br_mask = 4'h0; // @[functional-unit.scala:105:14, :133:7, :234:35] wire [3:0] _cfi_idx_T_2 = 4'h0; // @[functional-unit.scala:105:14, :133:7, :234:35] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 2'h0; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 2'h0; // @[functional-unit.scala:133:7] wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:188:48] wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:133:7] wire _cfi_idx_T = 1'h0; // @[functional-unit.scala:234:77] wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:285:51] wire _io_resp_bits_predicated_T_3 = 1'h0; // @[functional-unit.scala:291:60] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:133:7] wire io_resp_ready = 1'h1; // @[functional-unit.scala:133:7] wire _mispredict_T_1 = 1'h1; // @[functional-unit.scala:245:22] wire _mispredict_T_3 = 1'h1; // @[functional-unit.scala:245:53] wire _mispredict_T_4 = 1'h1; // @[functional-unit.scala:247:22] wire _mispredict_T_5 = 1'h1; // @[functional-unit.scala:246:67] wire _mispredict_T_7 = 1'h1; // @[functional-unit.scala:247:67] wire io_resp_valid_0 = io_req_valid_0; // @[functional-unit.scala:133:7] wire [31:0] io_resp_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [31:0] io_resp_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7, :252:20] wire [39:0] io_resp_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] wire [39:0] brinfo_bits_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [11:0] io_resp_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] wire [11:0] brinfo_bits_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_type_0 = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_type = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfence = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_eret_0 = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_eret = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rocc = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_mov_0 = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_mov = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] wire [5:0] _cfi_idx_T_3 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :234:30] wire [5:0] brinfo_bits_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_imm_rename = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_imm_sel = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_pimm_0 = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_pimm = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7, :252:20] wire [19:0] io_resp_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] wire [19:0] brinfo_bits_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_op1_sel = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_op2_sel = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] io_resp_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] wire [63:0] brinfo_bits_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_fcn_op = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_fp_rm = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_typ = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] jalr_target_base = io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :229:47] wire [63:0] _io_resp_bits_data_T_4; // @[functional-unit.scala:290:27] wire brinfo_valid; // @[functional-unit.scala:252:20] wire brinfo_bits_mispredict; // @[functional-unit.scala:252:20] wire brinfo_bits_taken; // @[functional-unit.scala:252:20] wire [2:0] brinfo_bits_cfi_type; // @[functional-unit.scala:252:20] wire [1:0] brinfo_bits_pc_sel; // @[functional-unit.scala:252:20] wire [39:0] brinfo_bits_jalr_target; // @[functional-unit.scala:252:20] wire [20:0] brinfo_bits_target_offset; // @[functional-unit.scala:252:20] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [11:0] io_brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_mispredict; // @[functional-unit.scala:133:7] wire io_brinfo_bits_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brinfo_bits_target_offset; // @[functional-unit.scala:133:7] wire io_brinfo_valid; // @[functional-unit.scala:133:7] wire [39:0] _uop_pc_T = {34'h0, io_req_bits_uop_pc_lob_0}; // @[functional-unit.scala:133:7, :150:26] wire [1:0] _uop_pc_T_1 = {io_req_bits_uop_edge_inst_0, 1'h0}; // @[functional-unit.scala:133:7, :150:45] wire [40:0] _uop_pc_T_2 = {1'h0, _uop_pc_T} - {39'h0, _uop_pc_T_1}; // @[functional-unit.scala:150:{26,40,45}] wire [39:0] uop_pc = _uop_pc_T_2[39:0]; // @[functional-unit.scala:150:40] wire _op1_shamt_T = io_req_bits_uop_fcn_op_0 == 5'h0; // @[functional-unit.scala:133:7, :151:34] wire [1:0] _op1_shamt_T_1 = io_req_bits_uop_pimm_0[2:1]; // @[functional-unit.scala:133:7, :151:66] wire [1:0] op1_shamt = _op1_shamt_T ? _op1_shamt_T_1 : 2'h0; // @[functional-unit.scala:151:{22,34,66}] wire _op1_shl_T = ~io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :152:32] wire [31:0] _op1_shl_T_1 = io_req_bits_rs1_data_0[31:0]; // @[functional-unit.scala:133:7, :153:25] wire [63:0] _op1_shl_T_2 = _op1_shl_T ? {32'h0, _op1_shl_T_1} : io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :152:{20,32}, :153:25] wire [66:0] op1_shl = {3'h0, _op1_shl_T_2} << op1_shamt; // @[functional-unit.scala:151:22, :152:20, :153:55] wire _op1_data_T = uop_pc[39]; // @[util.scala:269:46] wire [23:0] _op1_data_T_1 = {24{_op1_data_T}}; // @[util.scala:269:{25,46}] wire [63:0] _op1_data_T_2 = {_op1_data_T_1, uop_pc}; // @[util.scala:269:{20,25}] wire _op1_data_T_3 = io_req_bits_uop_op1_sel_0 == 2'h0; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_4 = _op1_data_T_3 ? io_req_bits_rs1_data_0 : 64'h0; // @[functional-unit.scala:133:7, :155:45] wire _op1_data_T_5 = io_req_bits_uop_op1_sel_0 == 2'h2; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_6 = _op1_data_T_5 ? _op1_data_T_2 : _op1_data_T_4; // @[util.scala:269:20] wire _op1_data_T_7 = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45] wire [66:0] op1_data = _op1_data_T_7 ? op1_shl : {3'h0, _op1_data_T_6}; // @[functional-unit.scala:153:55, :155:45] wire _op2_oh_T = io_req_bits_uop_op2_sel_0[0]; // @[functional-unit.scala:133:7, :162:40] wire [63:0] _op2_oh_T_1 = _op2_oh_T ? io_req_bits_rs2_data_0 : io_req_bits_imm_data_0; // @[functional-unit.scala:133:7, :162:{28,40}] wire [5:0] _op2_oh_T_2 = _op2_oh_T_1[5:0]; // @[functional-unit.scala:162:28, :163:38] wire [63:0] op2_oh = 64'h1 << _op2_oh_T_2; // @[OneHot.scala:58:35] wire [4:0] _op2_data_T = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:133:7, :166:37] wire [2:0] _op2_data_T_1 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:133:7, :168:20] wire _op2_data_T_2 = io_req_bits_uop_op2_sel_0 == 3'h1; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_3 = _op2_data_T_2 ? io_req_bits_imm_data_0 : 64'h0; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_4 = io_req_bits_uop_op2_sel_0 == 3'h4; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_5 = _op2_data_T_4 ? {59'h0, _op2_data_T} : _op2_data_T_3; // @[functional-unit.scala:164:45, :166:37] wire _op2_data_T_6 = io_req_bits_uop_op2_sel_0 == 3'h0; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_7 = _op2_data_T_6 ? io_req_bits_rs2_data_0 : _op2_data_T_5; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_8 = io_req_bits_uop_op2_sel_0 == 3'h3; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_9 = _op2_data_T_8 ? {61'h0, _op2_data_T_1} : _op2_data_T_7; // @[functional-unit.scala:164:45, :168:20] wire _op2_data_T_10 = io_req_bits_uop_op2_sel_0 == 3'h5; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_11 = _op2_data_T_10 ? op2_oh : _op2_data_T_9; // @[OneHot.scala:58:35] wire _op2_data_T_12 = io_req_bits_uop_op2_sel_0 == 3'h6; // @[functional-unit.scala:133:7, :164:45] wire [63:0] op2_data = _op2_data_T_12 ? op2_oh : _op2_data_T_11; // @[OneHot.scala:58:35] wire _alu_io_dw_T = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45, :178:33] wire _alu_io_dw_T_1 = _alu_io_dw_T \| io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :178:{20,33}] wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :183:21] wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :184:28] wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22] wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22, :186:20] wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36] wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36, :186:35] wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:185:{22,31,36}] wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:185:{17,31}] wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:184:28, :185:{17,46}] wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:186:{31,35}] wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:186:{20,29,31}] wire br_lt = _br_lt_T_4 \| _br_lt_T_8; // @[functional-unit.scala:185:{46,55}, :186:29] wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:183:21, :190:38] wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:190:{37,38}] wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:183:21, :191:37] wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:185:55, :192:38] wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:192:{37,38}] wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:184:28, :193:38] wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:193:{37,38}] wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:185:55, :194:37] wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:184:28, :195:37] wire _pc_sel_T_9 = ~(\|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _GEN = io_req_bits_uop_br_type_0 == 4'h1; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_11; // @[functional-unit.scala:188:48] assign _pc_sel_T_11 = _GEN; // @[functional-unit.scala:188:48] wire _is_br_T; // @[package.scala:16:47] assign _is_br_T = _GEN; // @[package.scala:16:47] wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:188:48, :190:37] wire _GEN_0 = io_req_bits_uop_br_type_0 == 4'h2; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_13; // @[functional-unit.scala:188:48] assign _pc_sel_T_13 = _GEN_0; // @[functional-unit.scala:188:48] wire _is_br_T_1; // @[package.scala:16:47] assign _is_br_T_1 = _GEN_0; // @[package.scala:16:47] wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:188:48, :191:37] wire _GEN_1 = io_req_bits_uop_br_type_0 == 4'h3; // @[functional-unit.scala:133:7, :188:48, :201:33] wire _pc_sel_T_15; // @[functional-unit.scala:188:48] assign _pc_sel_T_15 = _GEN_1; // @[functional-unit.scala:188:48] wire _is_br_T_2; // @[package.scala:16:47] assign _is_br_T_2 = _GEN_1; // @[package.scala:16:47] wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:188:48, :192:37] wire _GEN_2 = io_req_bits_uop_br_type_0 == 4'h4; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_17; // @[functional-unit.scala:188:48] assign _pc_sel_T_17 = _GEN_2; // @[functional-unit.scala:188:48] wire _is_br_T_3; // @[package.scala:16:47] assign _is_br_T_3 = _GEN_2; // @[package.scala:16:47] wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:188:48, :193:37] wire _GEN_3 = io_req_bits_uop_br_type_0 == 4'h5; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_19; // @[functional-unit.scala:188:48] assign _pc_sel_T_19 = _GEN_3; // @[functional-unit.scala:188:48] wire _is_br_T_4; // @[package.scala:16:47] assign _is_br_T_4 = _GEN_3; // @[package.scala:16:47] wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:188:48, :194:37] wire _GEN_4 = io_req_bits_uop_br_type_0 == 4'h6; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_21; // @[functional-unit.scala:188:48] assign _pc_sel_T_21 = _GEN_4; // @[functional-unit.scala:188:48] wire _is_br_T_5; // @[package.scala:16:47] assign _is_br_T_5 = _GEN_4; // @[package.scala:16:47] wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:188:48, :195:37] wire _GEN_5 = io_req_bits_uop_br_type_0 == 4'h7; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_23; // @[functional-unit.scala:188:48] assign _pc_sel_T_23 = _GEN_5; // @[functional-unit.scala:188:48] wire _is_jal_T; // @[micro-op.scala:118:34] assign _is_jal_T = _GEN_5; // @[functional-unit.scala:188:48] wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:188:48] wire _GEN_6 = io_req_bits_uop_br_type_0 == 4'h8; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_25; // @[functional-unit.scala:188:48] assign _pc_sel_T_25 = _GEN_6; // @[functional-unit.scala:188:48] wire _is_jalr_T; // @[micro-op.scala:119:34] assign _is_jalr_T = _GEN_6; // @[functional-unit.scala:188:48] wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:188:48] assign brinfo_bits_pc_sel = pc_sel; // @[functional-unit.scala:188:48, :252:20] wire _is_taken_T = io_req_bits_uop_br_type_0 != 4'h3; // @[functional-unit.scala:133:7, :201:33] wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:133:7, :200:31, :201:33] wire _is_taken_T_2 = \|pc_sel; // @[functional-unit.scala:188:48, :202:28] wire is_taken = _is_taken_T_1 & _is_taken_T_2; // @[functional-unit.scala:200:31, :201:43, :202:28] assign brinfo_bits_taken = is_taken; // @[functional-unit.scala:201:43, :252:20] wire [20:0] _target_offset_T = io_req_bits_imm_data_0[20:0]; // @[functional-unit.scala:133:7, :208:33] wire [20:0] target_offset = _target_offset_T; // @[functional-unit.scala:208:{33,40}] assign brinfo_bits_target_offset = target_offset; // @[functional-unit.scala:208:40, :252:20] wire mispredict; // @[functional-unit.scala:223:28] assign brinfo_bits_mispredict = mispredict; // @[functional-unit.scala:223:28, :252:20] wire _is_br_T_6 = _is_br_T \| _is_br_T_1; // @[package.scala:16:47, :81:59] wire _is_br_T_7 = _is_br_T_6 \| _is_br_T_2; // @[package.scala:16:47, :81:59] wire _is_br_T_8 = _is_br_T_7 \| _is_br_T_3; // @[package.scala:16:47, :81:59] wire _is_br_T_9 = _is_br_T_8 \| _is_br_T_4; // @[package.scala:16:47, :81:59] wire _is_br_T_10 = _is_br_T_9 \| _is_br_T_5; // @[package.scala:16:47, :81:59] wire _is_br_T_11 = io_req_valid_0 & _is_br_T_10; // @[package.scala:81:59] wire _is_br_T_12 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :225:53] wire is_br = _is_br_T_11 & _is_br_T_12; // @[functional-unit.scala:225:{37,50,53}] wire is_jal = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:133:7, :226:37] wire is_jalr = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:133:7, :227:37] wire [63:0] _jalr_target_xlen_T_3; // @[functional-unit.scala:231:58] wire [63:0] jalr_target_xlen; // @[functional-unit.scala:230:30] wire [63:0] _jalr_target_a_T = jalr_target_xlen; // @[functional-unit.scala:215:16, :230:30] wire [64:0] _jalr_target_xlen_T = {jalr_target_base[63], jalr_target_base} + {{44{target_offset[20]}}, target_offset}; // @[functional-unit.scala:208:40, :229:47, :231:41] wire [63:0] _jalr_target_xlen_T_1 = _jalr_target_xlen_T[63:0]; // @[functional-unit.scala:231:41] wire [63:0] _jalr_target_xlen_T_2 = _jalr_target_xlen_T_1; // @[functional-unit.scala:231:41] assign _jalr_target_xlen_T_3 = _jalr_target_xlen_T_2; // @[functional-unit.scala:231:{41,58}] assign jalr_target_xlen = _jalr_target_xlen_T_3; // @[functional-unit.scala:230:30, :231:58] wire [24:0] jalr_target_a = _jalr_target_a_T[63:39]; // @[functional-unit.scala:215:{16,23}] wire _jalr_target_msb_T = jalr_target_a == 25'h0; // @[functional-unit.scala:215:23, :216:21] wire _jalr_target_msb_T_1 = &jalr_target_a; // @[functional-unit.scala:215:23, :216:34] wire _jalr_target_msb_T_2 = _jalr_target_msb_T \| _jalr_target_msb_T_1; // @[functional-unit.scala:216:{21,29,34}] wire _jalr_target_msb_T_3 = jalr_target_xlen[39]; // @[functional-unit.scala:216:46, :230:30] wire _jalr_target_msb_T_4 = jalr_target_xlen[38]; // @[functional-unit.scala:216:62, :230:30] wire _jalr_target_msb_T_5 = ~_jalr_target_msb_T_4; // @[functional-unit.scala:216:{59,62}] wire jalr_target_msb = _jalr_target_msb_T_2 ? _jalr_target_msb_T_3 : _jalr_target_msb_T_5; // @[functional-unit.scala:216:{18,29,46,59}] wire [38:0] _jalr_target_T = jalr_target_xlen[38:0]; // @[functional-unit.scala:217:16, :230:30] wire [39:0] _jalr_target_T_1 = {jalr_target_msb, _jalr_target_T}; // @[functional-unit.scala:216:18, :217:{8,16}] wire [39:0] _jalr_target_T_2 = _jalr_target_T_1; // @[functional-unit.scala:217:8, :232:79] wire [39:0] _jalr_target_T_3 = _jalr_target_T_2 & 40'hFFFFFFFFFE; // @[functional-unit.scala:232:{79,86}] wire [39:0] _jalr_target_T_4 = _jalr_target_T_3; // @[functional-unit.scala:232:86] wire [39:0] jalr_target = _jalr_target_T_4; // @[functional-unit.scala:232:{86,94}] assign brinfo_bits_jalr_target = jalr_target; // @[functional-unit.scala:232:94, :252:20] wire [1:0] cfi_idx = _cfi_idx_T_3[2:1]; // @[functional-unit.scala:234:{30,120}] wire _brinfo_valid_T = is_br \| is_jalr; // @[functional-unit.scala:225:50, :227:37, :237:15, :255:34] wire _mispredict_T = ~io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :242:21] wire _mispredict_T_2 = \|jalr_target; // @[functional-unit.scala:232:94, :246:50] wire _mispredict_T_6 = \|cfi_idx; // @[functional-unit.scala:234:120, :248:66] assign mispredict = _brinfo_valid_T & (pc_sel == 2'h2 \| (pc_sel == 2'h1 ? _mispredict_T : ~(\|pc_sel) & io_req_bits_uop_taken_0)); // @[functional-unit.scala:133:7, :188:48, :202:28, :223:28, :237:27, :238:{18,32}, :239:18, :241:{18,32}, :242:{18,21}, :244:{18,31}, :245:18, :255:34] assign io_brinfo_valid = brinfo_valid; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_inst = brinfo_bits_uop_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_inst = brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rvc = brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_pc = brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_0 = brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_1 = brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_2 = brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_3 = brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_0 = brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_1 = brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_2 = brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_3 = brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_4 = brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_5 = brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_6 = brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_7 = brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_8 = brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_9 = brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued = brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_agen = brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_dgen = brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_speculative_child = brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_speculative_child = brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_bypass_hint = brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_bypass_hint = brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p3_bypass_hint = brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dis_col_sel = brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_mask = brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_tag = brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_type = brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfb = brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fence = brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fencei = brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfence = brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_amo = brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_eret = brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sys_pc2epc = brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rocc = brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_mov = brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ftq_idx = brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_edge_inst = brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pc_lob = brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_taken = brinfo_bits_uop_taken; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_rename = brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_sel = brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pimm = brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_packed = brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op1_sel = brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op2_sel = brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ldst = brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wen = brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren1 = brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren2 = brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren3 = brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap12 = brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap23 = brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagIn = brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagOut = brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fromint = brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_toint = brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fastpipe = brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fma = brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_div = brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_sqrt = brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wflags = brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_vec = brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rob_idx = brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldq_idx = brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stq_idx = brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rxq_idx = brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pdst = brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1 = brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2 = brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3 = brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred = brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1_busy = brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2_busy = brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3_busy = brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred_busy = brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stale_pdst = brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exception = brinfo_bits_uop_exception; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exc_cause = brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_cmd = brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_size = brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_signed = brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_ldq = brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_stq = brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_unique = brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_flush_on_commit = brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_csr_cmd = brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst_is_rs1 = brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst = brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1 = brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2 = brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs3 = brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dst_rtype = brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1_rtype = brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2_rtype = brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_frs3_en = brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_dw = brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_op = brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_val = brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_rm = brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_typ = brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_pf_if = brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ae_if = brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ma_if = brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_debug_if = brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_xcpt_if = brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_fsrc = brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_tsrc = brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_mispredict = brinfo_bits_mispredict; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_taken = brinfo_bits_taken; // @[functional-unit.scala:133:7, :252:20] wire [2:0] _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:258:36] assign io_brinfo_bits_cfi_type = brinfo_bits_cfi_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_pc_sel = brinfo_bits_pc_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_jalr_target = brinfo_bits_jalr_target; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_target_offset = brinfo_bits_target_offset; // @[functional-unit.scala:133:7, :252:20] assign brinfo_valid = _brinfo_valid_T; // @[functional-unit.scala:252:20, :255:34] wire [2:0] _brinfo_bits_cfi_type_T = {2'h0, is_br}; // @[functional-unit.scala:225:50, :259:36] assign _brinfo_bits_cfi_type_T_1 = is_jalr ? 3'h3 : _brinfo_bits_cfi_type_T; // @[functional-unit.scala:227:37, :258:36, :259:36] assign brinfo_bits_cfi_type = _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:252:20, :258:36] wire _alu_out_T = ~(\|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _alu_out_T_1 = _alu_out_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _alu_out_T_2 = _alu_out_T_1; // @[micro-op.scala:121:{42,52}] wire [63:0] _alu_out_T_4 = io_req_bits_uop_ldst_is_rs1_0 ? io_req_bits_rs1_data_0 : io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :286:10] wire [63:0] _alu_out_T_5 = io_req_bits_uop_is_mov_0 ? io_req_bits_rs2_data_0 : _alu_io_out; // @[functional-unit.scala:133:7, :173:19, :287:10] wire [63:0] alu_out = _alu_out_T_5; // @[functional-unit.scala:285:20, :287:10] wire _io_resp_bits_data_T = \|io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_data_T_2 = _io_resp_bits_data_T_1; // @[micro-op.scala:120:{42,52}] wire _io_resp_bits_data_T_3 = pc_sel == 2'h1; // @[functional-unit.scala:188:48, :290:62] assign _io_resp_bits_data_T_4 = _io_resp_bits_data_T_2 ? {63'h0, _io_resp_bits_data_T_3} : alu_out; // @[OneHot.scala:58:35] assign io_resp_bits_data_0 = _io_resp_bits_data_T_4; // @[functional-unit.scala:133:7, :290:27] wire _io_resp_bits_predicated_T = ~(\|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_predicated_T_1 = _io_resp_bits_predicated_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_predicated_T_2 = _io_resp_bits_predicated_T_1; // @[micro-op.scala:121:{42,52}] ALU alu ( // @[functional-unit.scala:173:19] .clock (clock), .reset (reset), .io_dw (_alu_io_dw_T_1), // @[functional-unit.scala:178:20] .io_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:133:7] .io_in2 (op2_data), // @[functional-unit.scala:164:45] .io_in1 (op1_data[63:0]), // @[functional-unit.scala:155:45, :175:14] .io_out (_alu_io_out) ); // @[functional-unit.scala:173:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:133:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_15( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_22 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller / class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) / Negotiated sizes / def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) / Construct the enable registers, chunked into 8-bit segments to reduce verilog size / val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_\|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c \|\| g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ \|\| _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed \|\| completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed \|\| completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U \| right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /* Trait that will connect a PLIC to a subsystem / trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode := ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }	module PLICFanIn_2( // @[Plic.scala:338:7] input clock, // @[Plic.scala:338:7] input reset, // @[Plic.scala:338:7] input io_prio_0, // @[Plic.scala:339:14] input io_ip, // @[Plic.scala:339:14] output io_dev, // @[Plic.scala:339:14] output io_max // @[Plic.scala:339:14] ); wire io_prio_0_0 = io_prio_0; // @[Plic.scala:338:7] wire io_ip_0 = io_ip; // @[Plic.scala:338:7] wire [1:0] effectivePriority_0 = 2'h2; // @[Plic.scala:355:32] wire _effectivePriority_T = io_ip_0; // @[Plic.scala:338:7, :355:55] wire maxDev; // @[Misc.scala:35:36] wire io_dev_0; // @[Plic.scala:338:7] wire io_max_0; // @[Plic.scala:338:7] wire [1:0] effectivePriority_1 = {_effectivePriority_T, io_prio_0_0}; // @[Plic.scala:338:7, :355:{55,100}] wire [1:0] maxPri = effectivePriority_1 != 2'h3 ? 2'h2 : effectivePriority_1; // @[Misc.scala:35:9] assign maxDev = &effectivePriority_1; // @[Misc.scala:35:36] assign io_dev_0 = maxDev; // @[Misc.scala:35:36] assign io_max_0 = maxPri[0]; // @[Misc.scala:35:9] assign io_dev = io_dev_0; // @[Plic.scala:338:7] assign io_max = io_max_0; // @[Plic.scala:338:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_40( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_354 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_356 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_357 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File OutputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class OutputCreditAlloc extends Bundle { val alloc = Bool() val tail = Bool() } class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams { val occupied = Bool() def available = !occupied val flow = new FlowRoutingBundle } class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams { val alloc = Bool() val flow = new FlowRoutingBundle } class AbstractOutputUnitIO( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Bundle with HasRouterInputParams { val nodeId = cParam.srcId val nVirtualChannels = cParam.nVirtualChannels val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val credit_available = Output(Vec(nVirtualChannels, Bool())) val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus)) val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc)) val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc)) } abstract class AbstractOutputUnit( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams { val nodeId = cParam.srcId def io: AbstractOutputUnitIO } class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = new Channel(cParam.asInstanceOf[ChannelParams]) } val io = IO(new OutputUnitIO) class OutputState(val bufferSize: Int) extends Bundle { val occupied = Bool() val c = UInt(log2Up(1+bufferSize).W) val flow = new FlowRoutingBundle } val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) })) (states zip io.channel_status).map { case (s,a) => a.occupied := s.occupied a.flow := s.flow } io.out.flit := io.in states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) { when (io.out.vc_free(i)) { assert(s.occupied) s.occupied := false.B } } } (states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) { when (a.alloc) { s.occupied := true.B s.flow := a.flow } } } (io.credit_available zip states).zipWithIndex.map { case ((c,s),i) => c := s.c =/= 0.U //\|\| (io.out.credit_return.valid && io.out.credit_return.bits === i.U) } states.zipWithIndex.map { case (s,i) => val free = io.out.credit_return(i) val alloc = io.credit_alloc(i).alloc if (cParam.virtualChannelParams(i).traversable) { s.c := s.c +& free - alloc } } when (reset.asBool) { states.foreach(_.occupied := false.B) states.foreach(s => s.c := s.bufferSize.U) } }	module OutputUnit( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [5:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [5:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_8, // @[OutputUnit.scala:58:14] output io_credit_available_9, // @[OutputUnit.scala:58:14] output io_credit_available_12, // @[OutputUnit.scala:58:14] output io_credit_available_13, // @[OutputUnit.scala:58:14] output io_credit_available_16, // @[OutputUnit.scala:58:14] output io_credit_available_17, // @[OutputUnit.scala:58:14] output io_credit_available_20, // @[OutputUnit.scala:58:14] output io_credit_available_21, // @[OutputUnit.scala:58:14] output io_channel_status_8_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_9_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_12_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_13_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_16_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_17_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_20_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_21_occupied, // @[OutputUnit.scala:58:14] input io_allocs_8_alloc, // @[OutputUnit.scala:58:14] input io_allocs_9_alloc, // @[OutputUnit.scala:58:14] input io_allocs_12_alloc, // @[OutputUnit.scala:58:14] input io_allocs_13_alloc, // @[OutputUnit.scala:58:14] input io_allocs_16_alloc, // @[OutputUnit.scala:58:14] input io_allocs_17_alloc, // @[OutputUnit.scala:58:14] input io_allocs_20_alloc, // @[OutputUnit.scala:58:14] input io_allocs_21_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_8_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_9_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_12_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_13_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_16_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_17_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_20_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_21_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [5:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [5:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [21:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [21:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_21_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_21_c; // @[OutputUnit.scala:66:19] reg states_20_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_20_c; // @[OutputUnit.scala:66:19] reg states_17_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_17_c; // @[OutputUnit.scala:66:19] reg states_16_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_16_c; // @[OutputUnit.scala:66:19] reg states_13_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_13_c; // @[OutputUnit.scala:66:19] reg states_12_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_12_c; // @[OutputUnit.scala:66:19] reg states_9_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_9_c; // @[OutputUnit.scala:66:19] reg states_8_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_8_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = \|(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 \| _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 \| _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 \| _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 \| _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 \| _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 \| _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 \| _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 \| _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 \| _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 \| _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 \| _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 \| _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 \| _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 \| _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 \| _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 \| _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 \| _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 \| _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 \| _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 \| _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} \| _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2461 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2461; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2461; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2535 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2535; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2535; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2535; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2535; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2532 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2532; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2532; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2387 = _T_2461 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2387 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2387 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2387 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2387 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2387 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2433 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2433 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2535 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2402 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2402 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2402 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2474 = _T_2532 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2474 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2474 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2474 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2474 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2474 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2505 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2505 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2487 = _T_2535 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2487 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2487 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2487 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2541 = _T_2535 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2541 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2550 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2550 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Tail.scala: //**************************************************************************** // Copyright (c) 2021-2022, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE for license details. //------------------------------------------------------------------------------ / * - Tail.scala is the top of the system * - Input for FFT: `val signalIn` in class TailIO * - signalIn is a vector of K complex numbers (specified by TailParams) * - Connection: signalIn -> Deserialize -> FFT -> Unscramble -> OUTPUT / package fftgenerator import chisel3._ import chisel3.util._ import dsptools.numbers._ import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS} import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink.{TLRegisterNode, TLFragmenter} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import craft._ import dsptools._ import dsptools.numbers.implicits._ import dspjunctions._ import dspblocks._ import scala.math._ import scala.math.sqrt import scala.collection.mutable.ListBuffer import fixedpoint._ import fixedpoint.{fromIntToBinaryPoint} trait TailParams[T <: Data] extends DeserializeParams[T] with FFTConfig[T] with UnscrambleParams[T] { // Number of lanes in FFT. Should be same as N. val lanes: Int // n-point FFT val n: Int val S: Int } case class FixedTailParams( IOWidth: Int = 16, binaryPoint: Int = 8, lanes: Int = 2, n: Int = 2, S: Int = 256, pipelineDepth: Int = 0, // not configurable since this is an mmio device and not on-pipeline baseAddress: Int = 0x2000, ) extends TailParams[FixedPoint] { val proto = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoIn = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoOut = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val genIn = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val genOut = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoInDes = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoOutDes = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val inA = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val inB = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val outC = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) } class TailIO[T <: Data](params: TailParams[T]) extends Bundle { val signalIn = Flipped(Decoupled(params.protoIn.cloneType)) // (decoupled: adds ready-valid (vector of k complex numbers)) // Outputs // -- Signal Output val signalOut = Decoupled((Vec(params.lanes, params.protoOut.cloneType))) } object TailIO { def apply[T <: Data](params: TailParams[T]): TailIO[T] = new TailIO(params) } class Tail[T <: Data : RealBits : BinaryRepresentation : Real](val params: TailParams[T]) extends Module { val io = IO(TailIO(params)) // Instantiate the modules val DeserializeModule = Module(new Deserialize(params)).io val FFTModule = Module(new FFT(params)).io val UnscrambleModule = Module(new Unscramble(params)).io DeserializeModule.in.bits := io.signalIn.bits DeserializeModule.in.valid := io.signalIn.valid // signalIn.valid = new point being passed in io.signalIn.ready := DeserializeModule.in.ready // Connect Deserialize to FFT for (j <- 0 until params.lanes) FFTModule.in.bits(j) := DeserializeModule.out.bits(j) FFTModule.in.valid := DeserializeModule.out.valid FFTModule.in.sync := DeserializeModule.out.sync / Connect FFT to Unscramble * FFT outputs values with bits reversed (Ex: input of 001 becomes output of 100) * Unscramble fixes the bit order / for (j <- 0 until params.lanes) UnscrambleModule.in.bits(j) := FFTModule.out.bits(j) UnscrambleModule.in.valid := FFTModule.out.valid UnscrambleModule.in.sync := FFTModule.out.sync for (j <- 0 until params.lanes) io.signalOut.bits(j) := UnscrambleModule.out.bits(j) io.signalOut.valid := UnscrambleModule.out.valid UnscrambleModule.out.ready := io.signalOut.ready } class LazyTail(val config: FixedTailParams)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("fft-generator", Seq("cpu")) // add an entry to the DeviceTree in the BootROM so that it can be read by a Linux driver (9.2 chipyard docs) val node = TLRegisterNode( address = Seq(AddressSet(config.baseAddress, 0xff)), // (base address + size) of regmap device = device, beatBytes = 8, // specifies interface width in bytes -- since we're connected to a 64bit bus, want an 8byte width (default is 4) concurrency = 1 // size of the internal queue for TileLink requests, must be >0 for decoupled requests and responses (9.4 chipyard docs) ) lazy val module = new LazyModuleImp(this) { val tail = Module(new Tail(config)) val inputWire = Wire(Decoupled(UInt((config.IOWidth 2).W))) inputWire.ready := tail.io.signalIn.ready tail.io.signalIn.bits := inputWire.bits.asTypeOf(config.protoIn) tail.io.signalIn.valid := inputWire.valid val outputRegs = tail.io.signalOut.bits.map(b => RegEnable(b.asUInt, 0.U, tail.io.signalOut.valid)) var regMap = new ListBuffer[(Int, Seq[freechips.rocketchip.regmapper.RegField])]() regMap += (0x00 -> Seq(RegField.w(config.IOWidth * 2, inputWire))) for (i <- 0 until config.n) { regMap += (0x00 + (i+1) * 8 -> Seq(RegField.r(config.IOWidth * 2, outputRegs(i)))) } tail.io.signalOut.ready := true.B node.regmap((regMap.toList):_) } } trait CanHavePeripheryFFT extends BaseSubsystem { if (!p(FFTEnableKey).isEmpty) { // instantiate tail chain val pbus = locateTLBusWrapper(PBUS) val domain = pbus.generateSynchronousDomain.suggestName("fft_domain") val tailChain = domain { LazyModule(new LazyTail(p(FFTEnableKey).get)) } // connect memory interfaces to pbus pbus.coupleTo("tailWrite") { domain { tailChain.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ } } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module ClockSinkDomain_1( // @[ClockDomain.scala:14:9] output auto_fragmenter_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_fragmenter_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_fragmenter_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_fragmenter_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_fragmenter_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [10:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [13:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _tailChain_auto_in_a_ready; // @[Tail.scala:148:40] wire _tailChain_auto_in_d_valid; // @[Tail.scala:148:40] wire [2:0] _tailChain_auto_in_d_bits_opcode; // @[Tail.scala:148:40] wire [1:0] _tailChain_auto_in_d_bits_size; // @[Tail.scala:148:40] wire [10:0] _tailChain_auto_in_d_bits_source; // @[Tail.scala:148:40] wire [63:0] _tailChain_auto_in_d_bits_data; // @[Tail.scala:148:40] LazyTail tailChain ( // @[Tail.scala:148:40] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_a_ready (_tailChain_auto_in_a_ready), .auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_in_d_valid (_tailChain_auto_in_d_valid), .auto_in_d_bits_opcode (_tailChain_auto_in_d_bits_opcode), .auto_in_d_bits_size (_tailChain_auto_in_d_bits_size), .auto_in_d_bits_source (_tailChain_auto_in_d_bits_source), .auto_in_d_bits_data (_tailChain_auto_in_d_bits_data) ); // @[Tail.scala:148:40] TLFragmenter_1 fragmenter ( // @[Fragmenter.scala:345:34] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_anon_in_a_ready (auto_fragmenter_anon_in_a_ready), .auto_anon_in_a_valid (auto_fragmenter_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_fragmenter_anon_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_fragmenter_anon_in_a_bits_param), .auto_anon_in_a_bits_size (auto_fragmenter_anon_in_a_bits_size), .auto_anon_in_a_bits_source (auto_fragmenter_anon_in_a_bits_source), .auto_anon_in_a_bits_address (auto_fragmenter_anon_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_fragmenter_anon_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_fragmenter_anon_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_fragmenter_anon_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_fragmenter_anon_in_d_ready), .auto_anon_in_d_valid (auto_fragmenter_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_fragmenter_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_fragmenter_anon_in_d_bits_size), .auto_anon_in_d_bits_source (auto_fragmenter_anon_in_d_bits_source), .auto_anon_in_d_bits_data (auto_fragmenter_anon_in_d_bits_data), .auto_anon_out_a_ready (_tailChain_auto_in_a_ready), // @[Tail.scala:148:40] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_tailChain_auto_in_d_valid), // @[Tail.scala:148:40] .auto_anon_out_d_bits_opcode (_tailChain_auto_in_d_bits_opcode), // @[Tail.scala:148:40] .auto_anon_out_d_bits_size (_tailChain_auto_in_d_bits_size), // @[Tail.scala:148:40] .auto_anon_out_d_bits_source (_tailChain_auto_in_d_bits_source), // @[Tail.scala:148:40] .auto_anon_out_d_bits_data (_tailChain_auto_in_d_bits_data) // @[Tail.scala:148:40] ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_31( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [514:0] _c_sizes_set_T_1 = 515'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [159:0] c_opcodes_set = 160'h0; // @[Monitor.scala:740:34] wire [159:0] c_sizes_set = 160'h0; // @[Monitor.scala:741:34] wire [39:0] c_set = 40'h0; // @[Monitor.scala:738:34] wire [39:0] c_set_wo_ready = 40'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 6'h28; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [5:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 6'h28; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [39:0] inflight; // @[Monitor.scala:614:27] reg [159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [159:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [39:0] a_set; // @[Monitor.scala:626:34] wire [39:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [159:0] _a_opcode_lookup_T_6 = {156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [159:0] _a_size_lookup_T_6 = {156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_2 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[159:0] : 160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[159:0] : 160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [39:0] d_clr; // @[Monitor.scala:664:34] wire [39:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[159:0] : 160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[159:0] : 160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [39:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [39:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [39:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [39:0] inflight_1; // @[Monitor.scala:726:35] wire [39:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [159:0] _c_opcode_lookup_T_6 = {156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [159:0] _c_size_lookup_T_6 = {156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [39:0] d_clr_1; // @[Monitor.scala:774:34] wire [39:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[39:0] : 40'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[39:0] : 40'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[159:0] : 160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[159:0] : 160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [39:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [39:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s5k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_11 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module MulAddRecFNToRaw_preMul_e8_s24_72( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SingleVCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} // Allocates 1 VC per cycle abstract class SingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends VCAllocator(vP)(p) { // get single input val mask = RegInit(0.U(allInParams.size.W)) val in_arb_reqs = Wire(Vec(allInParams.size, MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))) val in_arb_vals = Wire(Vec(allInParams.size, Bool())) val in_arb_filter = PriorityEncoderOH(Cat(in_arb_vals.asUInt, in_arb_vals.asUInt & ~mask)) val in_arb_sel = (in_arb_filter(allInParams.size-1,0) \| (in_arb_filter >> allInParams.size)) when (in_arb_vals.orR) { mask := Mux1H(in_arb_sel, (0 until allInParams.size).map { w => ~(0.U((w+1).W)) }) } for (i <- 0 until allInParams.size) { (0 until allOutParams.size).map { m => (0 until allOutParams(m).nVirtualChannels).map { n => in_arb_reqs(i)(m)(n) := io.req(i).bits.vc_sel(m)(n) && !io.channel_status(m)(n).occupied } } in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).toSeq.orR } // Input arbitration io.req.foreach(_.ready := false.B) val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow).toSeq) val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc).toSeq) val in_vc_sel = Mux1H(in_arb_sel, in_arb_reqs) in_alloc := Mux(in_arb_vals.orR, inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).toSeq.orR), 0.U.asTypeOf(in_alloc)) // send allocation to inputunits for (i <- 0 until allInParams.size) { io.req(i).ready := in_arb_sel(i) for (m <- 0 until allOutParams.size) { (0 until allOutParams(m).nVirtualChannels).map { n => io.resp(i).vc_sel(m)(n) := in_alloc(m)(n) } } assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U) } // send allocation to output units for (i <- 0 until allOutParams.size) { (0 until allOutParams(i).nVirtualChannels).map { j => io.out_allocs(i)(j).alloc := in_alloc(i)(j) io.out_allocs(i)(j).flow := in_flow } } } File VCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.{DecodeLogic} import constellation.channel._ import constellation.noc.{HasNoCParams} import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo, ChannelRoutingInfo} class VCAllocReq( val inParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams with HasNoCParams { val flow = new FlowRoutingBundle val in_vc = UInt(log2Ceil(inParam.nVirtualChannels).W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class VCAllocResp(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } case class VCAllocatorParams( routerParams: RouterParams, inParams: Seq[ChannelParams], outParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], egressParams: Seq[EgressChannelParams]) abstract class VCAllocator(val vP: VCAllocatorParams)(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val routerParams = vP.routerParams val inParams = vP.inParams val outParams = vP.outParams val ingressParams = vP.ingressParams val egressParams = vP.egressParams val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new VCAllocReq(u, outParams, egressParams))) }) val resp = MixedVec(allInParams.map { u => Output(new VCAllocResp(outParams, egressParams)) }) val channel_status = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Input(new OutputChannelStatus)) }) val out_allocs = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputChannelAlloc)) }) }) val nOutChannels = allOutParams.map(_.nVirtualChannels).sum def inputAllocPolicy( flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool): MixedVec[Vec[Bool]] def outputAllocPolicy( out: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool): Vec[Bool] } File ISLIP.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} trait ISLIP { this: VCAllocator => def islip(in: UInt, fire: Bool): UInt = { val w = in.getWidth if (w > 1) { val mask = RegInit(0.U(w.W)) val full = Cat(in, in & ~mask) val oh = PriorityEncoderOH(full) val sel = (oh(w-1,0) \| (oh >> w)) when (fire) { mask := MuxCase(0.U, (0 until w).map { i => sel(i) -> ~(0.U((i+1).W)) }) } sel } else { in } } def inputAllocPolicy(flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool) = { islip(vc_sel.asUInt, fire).asTypeOf(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool())})) } def outputAllocPolicy(channel: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool) = { islip(VecInit(reqs).asUInt, fire).asTypeOf(Vec(allInParams.size, Bool())) } } class ISLIPMultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends MultiVCAllocator(vP)(p) with ISLIP class RotatingSingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends SingleVCAllocator(vP)(p) with ISLIP	module RotatingSingleVCAllocator_1( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_4_ready, // @[VCAllocator.scala:49:14] input io_req_4_valid, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_2_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_4; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [4:0] mask; // @[SingleVCAllocator.scala:16:21] wire [4:0] _in_arb_filter_T_3 = {in_arb_vals_4, in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [9:0] in_arb_filter = _in_arb_filter_T_3[0] ? 10'h1 : _in_arb_filter_T_3[1] ? 10'h2 : _in_arb_filter_T_3[2] ? 10'h4 : _in_arb_filter_T_3[3] ? 10'h8 : _in_arb_filter_T_3[4] ? 10'h10 : in_arb_vals_0 ? 10'h20 : in_arb_vals_1 ? 10'h40 : in_arb_vals_2 ? 10'h80 : in_arb_vals_3 ? 10'h100 : {in_arb_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] in_arb_sel = in_arb_filter[4:0] \| in_arb_filter[9:5]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 \| in_arb_vals_1 \| in_arb_vals_2 \| in_arb_vals_3 \| in_arb_vals_4; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_1 = io_req_0_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_2 = io_req_0_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 \| in_arb_reqs_0_0_1 \| in_arb_reqs_0_0_2 \| in_arb_reqs_0_1_0 \| in_arb_reqs_0_1_1 \| in_arb_reqs_0_1_2 \| in_arb_reqs_0_2_0 \| in_arb_reqs_0_2_1 \| in_arb_reqs_0_2_2 \| in_arb_reqs_0_3_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_1 = io_req_1_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_2 = io_req_1_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_1 = io_req_1_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_2 = io_req_1_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 \| in_arb_reqs_1_0_1 \| in_arb_reqs_1_0_2 \| in_arb_reqs_1_1_0 \| in_arb_reqs_1_1_1 \| in_arb_reqs_1_1_2 \| in_arb_reqs_1_2_0 \| in_arb_reqs_1_2_1 \| in_arb_reqs_1_2_2 \| in_arb_reqs_1_3_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_1 = io_req_2_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_2 = io_req_2_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 \| in_arb_reqs_2_0_1 \| in_arb_reqs_2_0_2 \| in_arb_reqs_2_1_0 \| in_arb_reqs_2_1_1 \| in_arb_reqs_2_1_2 \| in_arb_reqs_2_2_0 \| in_arb_reqs_2_2_1 \| in_arb_reqs_2_2_2 \| in_arb_reqs_2_3_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_1 = io_req_3_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_2 = io_req_3_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_1 = io_req_3_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_2 = io_req_3_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_3_0 = io_req_3_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 \| in_arb_reqs_3_0_1 \| in_arb_reqs_3_0_2 \| in_arb_reqs_3_1_0 \| in_arb_reqs_3_1_1 \| in_arb_reqs_3_1_2 \| in_arb_reqs_3_2_0 \| in_arb_reqs_3_2_1 \| in_arb_reqs_3_2_2 \| in_arb_reqs_3_3_0); // @[package.scala:81:59] wire in_arb_reqs_4_0_0 = io_req_4_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_0_1 = io_req_4_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_0_2 = io_req_4_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_0 = io_req_4_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_1 = io_req_4_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_2 = io_req_4_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_0 = io_req_4_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_1 = io_req_4_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_2 = io_req_4_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_3_0 = io_req_4_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_4 = io_req_4_valid & (in_arb_reqs_4_0_0 \| in_arb_reqs_4_0_1 \| in_arb_reqs_4_0_2 \| in_arb_reqs_4_1_0 \| in_arb_reqs_4_1_1 \| in_arb_reqs_4_1_2 \| in_arb_reqs_4_2_0 \| in_arb_reqs_4_2_1 \| in_arb_reqs_4_2_2 \| in_arb_reqs_4_3_0); // @[package.scala:81:59] wire _in_vc_sel_T_13 = in_arb_sel[0] & in_arb_reqs_0_0_0 \| in_arb_sel[1] & in_arb_reqs_1_0_0 \| in_arb_sel[2] & in_arb_reqs_2_0_0 \| in_arb_sel[3] & in_arb_reqs_3_0_0 \| in_arb_sel[4] & in_arb_reqs_4_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_22 = in_arb_sel[0] & in_arb_reqs_0_0_1 \| in_arb_sel[1] & in_arb_reqs_1_0_1 \| in_arb_sel[2] & in_arb_reqs_2_0_1 \| in_arb_sel[3] & in_arb_reqs_3_0_1 \| in_arb_sel[4] & in_arb_reqs_4_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_0_2 \| in_arb_sel[1] & in_arb_reqs_1_0_2 \| in_arb_sel[2] & in_arb_reqs_2_0_2 \| in_arb_sel[3] & in_arb_reqs_3_0_2 \| in_arb_sel[4] & in_arb_reqs_4_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_40 = in_arb_sel[0] & in_arb_reqs_0_1_0 \| in_arb_sel[1] & in_arb_reqs_1_1_0 \| in_arb_sel[2] & in_arb_reqs_2_1_0 \| in_arb_sel[3] & in_arb_reqs_3_1_0 \| in_arb_sel[4] & in_arb_reqs_4_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_49 = in_arb_sel[0] & in_arb_reqs_0_1_1 \| in_arb_sel[1] & in_arb_reqs_1_1_1 \| in_arb_sel[2] & in_arb_reqs_2_1_1 \| in_arb_sel[3] & in_arb_reqs_3_1_1 \| in_arb_sel[4] & in_arb_reqs_4_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_58 = in_arb_sel[0] & in_arb_reqs_0_1_2 \| in_arb_sel[1] & in_arb_reqs_1_1_2 \| in_arb_sel[2] & in_arb_reqs_2_1_2 \| in_arb_sel[3] & in_arb_reqs_3_1_2 \| in_arb_sel[4] & in_arb_reqs_4_1_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_67 = in_arb_sel[0] & in_arb_reqs_0_2_0 \| in_arb_sel[1] & in_arb_reqs_1_2_0 \| in_arb_sel[2] & in_arb_reqs_2_2_0 \| in_arb_sel[3] & in_arb_reqs_3_2_0 \| in_arb_sel[4] & in_arb_reqs_4_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_76 = in_arb_sel[0] & in_arb_reqs_0_2_1 \| in_arb_sel[1] & in_arb_reqs_1_2_1 \| in_arb_sel[2] & in_arb_reqs_2_2_1 \| in_arb_sel[3] & in_arb_reqs_3_2_1 \| in_arb_sel[4] & in_arb_reqs_4_2_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_85 = in_arb_sel[0] & in_arb_reqs_0_2_2 \| in_arb_sel[1] & in_arb_reqs_1_2_2 \| in_arb_sel[2] & in_arb_reqs_2_2_2 \| in_arb_sel[3] & in_arb_reqs_3_2_2 \| in_arb_sel[4] & in_arb_reqs_4_2_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_94 = in_arb_sel[0] & in_arb_reqs_0_3_0 \| in_arb_sel[1] & in_arb_reqs_1_3_0 \| in_arb_sel[2] & in_arb_reqs_2_3_0 \| in_arb_sel[3] & in_arb_reqs_3_3_0 \| in_arb_sel[4] & in_arb_reqs_4_3_0; // @[Mux.scala:30:73, :32:36] reg [9:0] mask_1; // @[ISLIP.scala:17:25] wire [9:0] _full_T_1 = {_in_vc_sel_T_94, _in_vc_sel_T_85, _in_vc_sel_T_76, _in_vc_sel_T_67, _in_vc_sel_T_58, _in_vc_sel_T_49, _in_vc_sel_T_40, _in_vc_sel_T_31, _in_vc_sel_T_22, _in_vc_sel_T_13} & ~mask_1; // @[Mux.scala:30:73] wire [19:0] oh = _full_T_1[0] ? 20'h1 : _full_T_1[1] ? 20'h2 : _full_T_1[2] ? 20'h4 : _full_T_1[3] ? 20'h8 : _full_T_1[4] ? 20'h10 : _full_T_1[5] ? 20'h20 : _full_T_1[6] ? 20'h40 : _full_T_1[7] ? 20'h80 : _full_T_1[8] ? 20'h100 : _full_T_1[9] ? 20'h200 : _in_vc_sel_T_13 ? 20'h400 : _in_vc_sel_T_22 ? 20'h800 : _in_vc_sel_T_31 ? 20'h1000 : _in_vc_sel_T_40 ? 20'h2000 : _in_vc_sel_T_49 ? 20'h4000 : _in_vc_sel_T_58 ? 20'h8000 : _in_vc_sel_T_67 ? 20'h10000 : _in_vc_sel_T_76 ? 20'h20000 : _in_vc_sel_T_85 ? 20'h40000 : {_in_vc_sel_T_94, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] sel = oh[9:0] \| oh[19:10]; // @[Mux.scala:50:70] wire in_alloc_3_0 = _GEN & sel[9]; // @[package.scala:81:59] wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_2_1 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_2_2 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_1_2 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w4_d3_i0_38( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_343 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_346 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_218( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_26 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_27 = _source_ok_T_26 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_67 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire _source_ok_T_66 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) \| t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) \| t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) \| t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) \| t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) \| t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }	module RouteComputer( // @[RouteComputer.scala:29:7] input [3:0] io_req_6_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_6_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2 // @[RouteComputer.scala:40:14] ); wire [3:0] _GEN = ~io_req_6_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_6_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_6_vc_sel_1_0 = \|{&{_GEN_0[0], _GEN[0], _GEN[1], io_req_6_bits_flow_egress_node[2]}, &{_GEN_0[0], _GEN[0], _GEN[1], io_req_6_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_6_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_6_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_6_vc_sel_0_0 = \|{&{_GEN_0[0], io_req_6_bits_flow_egress_node[0], _GEN[2], _GEN[3]}, &{_GEN_0[0], _GEN_0[1], io_req_6_bits_flow_egress_node[1]}, &{_GEN_0[0], io_req_6_bits_flow_egress_node[0], io_req_6_bits_flow_egress_node[2], io_req_6_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_6_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_6_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_2 = \|{&{io_req_4_bits_flow_egress_node[2], ~(io_req_4_bits_flow_egress_node[3])}, io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_2 = \|{&{io_req_2_bits_flow_egress_node[2], ~(io_req_2_bits_flow_egress_node[3])}, io_req_2_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLInterconnectCoupler_cbus_to_debug( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire [9:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [13:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [9:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [9:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [11:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [13:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [9:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] TLFragmenter_Debug fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7] ); // @[Fragmenter.scala:345:34] assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_274( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_61 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid \|\| full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }	module Repeater_TLBundleD_a32d256s5k5z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_sink, // @[Repeater.scala:13:14] input io_enq_bits_denied, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_sink, // @[Repeater.scala:13:14] output io_deq_bits_denied, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[Repeater.scala:10:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [1:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_sink; // @[Repeater.scala:26:21] wire _io_deq_bits_T_denied; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [1:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_sink_0; // @[Repeater.scala:10:7] wire io_deq_bits_denied_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [1:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [4:0] saved_sink; // @[Repeater.scala:21:18] reg saved_denied; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_sink = full ? saved_sink : io_enq_bits_sink_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_denied = full ? saved_denied : io_enq_bits_denied_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_sink_0 = _io_deq_bits_T_sink; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_denied_0 = _io_deq_bits_T_denied; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_sink <= io_enq_bits_sink_0; // @[Repeater.scala:10:7, :21:18] saved_denied <= io_enq_bits_denied_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_sink = io_deq_bits_sink_0; // @[Repeater.scala:10:7] assign io_deq_bits_denied = io_deq_bits_denied_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn \|\| noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }	module TLNoC_2_router_7ClockSinkDomain( // @[ClockDomain.scala:14:9] output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_54 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_2_flit_ready (auto_routers_egress_nodes_out_2_flit_ready), .auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid), .auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head), .auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLBuffer_a28d64s4k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_57 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21] .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21] .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_10( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_63( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_76 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a29d64s9k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_19 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s9k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s9k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [1:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [1:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [1:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [6:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [80:0] inflight; // @[Monitor.scala:614:27] reg [323:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [323:0] inflight_sizes; // @[Monitor.scala:618:33] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_1 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_4 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [80:0] inflight_1; // @[Monitor.scala:726:35] reg [323:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [127:0] _GEN_6 = {121'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [11:0] inflight_2; // @[Monitor.scala:828:27] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [11:0] d_set = _GEN_8 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_87( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_100 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. / object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /* Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. / case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /* the base address of DM / def atzero = (baseAddress == 0) /* The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm / def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /TODO , val configStringAddr: Int/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /* Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above / case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ************************************** // Module Interfaces // // ************************************* / Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} / class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* resume request / val resumereq = Bool() /* hart select / val hartsel = UInt(10.W) /* reset acknowledge / val ackhavereset = Bool() /* hart array enable / val hasel = Bool() /* hart array mask / val hamask = Vec(nComponents, Bool()) /* halt-on-reset mask / val hrmask = Vec(nComponents, Bool()) } /* structure for top-level Debug Module signals which aren't the bus interfaces. / class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* debug availability status for all harts / val debugUnavail = Input(Vec(nComponents, Bool())) /* reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM / val ndreset = Output(Bool()) /* reset signal for the DM itself / val dmactive = Output(Bool()) /* dmactive acknowlege / val dmactiveAck = Input(Bool()) } // ************************************** // Debug Module // // ************************************* / Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. / // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /* structure for top-level Debug Module signals which aren't the bus interfaces. / val ctrl = (new DebugCtrlBundle(nComponents)) /* control signals for Inner, generated in Outer / val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /* debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* authentication support / val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /* whether the hart is selected / def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive \|\| ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((iihaWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (iihaWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive \|\| ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((iihaWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(iihaWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(iihaWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) \| io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) \|\| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn \| resumereqWrEn \| ackhaveresetWrEn \| setresethaltreqWrEn \| clrresethaltreqWrEn \| haselWrEn \| (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid \| innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) \| innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) \| innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode := IntSyncCrossingSource(alreadyRegistered = true) := dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /* conrol signals for Inner, generated in Outer / val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /* debug interruption generated in Inner / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Authentication signal from core / val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive \| ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /* dmiNode address set / val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) \| (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /* dm reset signal passed in from Outer / val dmactive = Input(Bool()) /* conrol signals for Inner * * it's generated by Outer and comes in / val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /* debug unavail signal passed in from Outer/ val debugUnavail = Input(Vec(nComponents, Bool())) /* debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Output(Vec(nComponents, Bool())) /* interface for trigger / val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug Authentication signals from core / val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) \|\| (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /* all harts halted status / val haltedBitRegs = Reg(UInt(nComponents.W)) /* all harts resume request status / val resumeReqRegs = Reg(UInt(nComponents.W)) /* all harts have reset status / val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /* all harts resume ack status / val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive \|\| ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive \|\| ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive \|\| ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync \| // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ \| _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ \| _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools \| ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive \|\| ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) \| hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs \| hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive \|\| ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive \|\| ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ \| _) hgTrigsAllAcked(hg) := (trigOutAck \| hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools \| hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive \|\| ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) \| hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt \| hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r \| w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r \| w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ \|\| _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ \|\| _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ \|\| _) \|\| autoexecProg.reduce(_ \|\| _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive \|\| ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive \|\| ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs \| hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs \| hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i8, (i+1)8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) \|\| (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) \|\| (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) \|\| (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) \|\| (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) \|\| (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result \|\| (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer \|\| accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand \|\| regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive \|\| ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive \|\| !hartExceptionWrEn \|\| ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /* reset signal for DM / val dmactive = Input(Bool()) /* conrol signals for Inner * * generated in Outer / val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /* debug available status / val debugUnavail = Input(Vec(getNComponents(), Bool())) /* debug interruption/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(getNComponents(), Bool())) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /* Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. / class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug control signals generated in Outer / val ctrl = new DebugCtrlBundle(nComponents) /* Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) /* hart reset request generated by hartreset-logic in Outer / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File SBA.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value } object SBErrorCode extends scala.Enumeration { type SBErrorCode = Value val NoError = Value(0) val Timeout = Value(1) val BadAddr = Value(2) val AlgnError = Value(3) val BadAccess = Value(4) val OtherError = Value(7) } object SystemBusAccessModule { def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = { import SBErrorCode._ val cfg = p(DebugModuleKey).get val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn") val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn") val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn") // --- SBCS Status Register --- val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg") val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields())) SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) SBCSFieldsRegReset.sbaccess := 2.U SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData") val SBCSWrDataVal = WireInit(0.U(32.W)) val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields())) val sberrorWrEn = WireInit(false.B) val sbreadondataWrEn = WireInit(false.B) val sbautoincrementWrEn= WireInit(false.B) val sbaccessWrEn = WireInit(false.B) val sbreadonaddrWrEn = WireInit(false.B) val sbbusyerrorWrEn = WireInit(false.B) val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq( RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))), RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))), WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn, RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn, RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn, RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))), WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn, RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))), WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn, RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))), RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn, RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(6), RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))), )) // --- System Bus Address Registers --- // ADDR0 Register is required // Instantiate ADDR1-3 registers as needed depending on system bus address width val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33) val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65) val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97) val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3) val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W))) SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")} val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val autoIncrementedAddr = WireInit(0.U(128.W)) autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess) autoIncrementedAddr.suggestName("autoIncrementedAddr") val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) => if(hasAddr(i)) { when (~dmactive \|\| ~dmAuthenticated) { a := 0.U(32.W) }.otherwise { a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i), Mux((sb2tl.module.io.rdDone \|\| sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32i+31,32i), a)) } RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i), Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true))))) } else { a := DontCare Seq.empty[RegField] } } sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0), Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)), Cat(SBADDRESSFieldsReg.reverse)) anyAddressWrEn := SBADDRESSWrEn.reduce(_ \|\| _) // --- System Bus Data Registers --- // DATA0 Register is required // DATA1-3 Registers may not be needed depending on implementation val hasSBData1 = (cfg.maxSupportedSBAccess > 32) val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128) val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3) val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W)))) SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }} val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) } val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) } val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) } val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) => if(hasData(i)) { // For data registers, load enable per-byte for (j <- 0 to 3) { when (~dmactive \|\| ~dmAuthenticated) { d(j) := 0.U(8.W) }.otherwise { d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8j+7,8j), Mux(sb2tl.module.io.rdLoad(4i+j), sb2tl.module.io.dataOut, d(j))) } } SBDATARdData(i) := Cat(d.reverse) RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i), Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true))))) } else { for (j <- 0 to 3) { d(j) := DontCare } Seq.empty[RegField] } } sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse)) anyDataRdEn := SBDATARdEn.reduce(_ \|\| _) anyDataWrEn := SBDATAWrEn.reduce(_ \|\| _) val tryWrEn = SBDATAWrEn(0) val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) \|\| (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata) val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) \|\| (SBCSFieldsReg.sbaccess > 4.U) val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0)) val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) \|\| (SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U) sbAccessError.suggestName("sbAccessError") sbAlignmentError.suggestName("sbAlignmentError") sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) when (~dmactive \|\| ~dmAuthenticated) { SBCSFieldsReg := SBCSFieldsRegReset }.otherwise { SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy Mux((anyDataRdEn \|\| anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr) SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata) SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 } // sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it val sbErrorReg = Reg(Vec(4, UInt(1.W))) when(~dmactive \|\| ~dmAuthenticated) { for (i <- 0 until 3) sbErrorReg(i) := 0.U }.otherwise { for (i <- 0 until 3) sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) \|\| (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed Mux((tryWrEn \|\| tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error Mux((tryWrEn \|\| tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error Mux((sb2tl.module.io.rdDone \|\| sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL } SBCSRdData := SBCSFieldsReg SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B SBCSRdData.sbbusy := sbBusy SBCSRdData.sberror := sbErrorReg.asUInt when (~dmAuthenticated) { // Read value must be 0 if not authenticated SBCSRdData := 0.U.asTypeOf(new SBCSFields()) } property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set") property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access") property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set") property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set") property.cover((sb2tl.module.io.wrEn \|\| sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value") (sbcsfields, sbaddrfields, sbdatafields) } } class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val rdEn = Input(Bool()) val wrEn = Input(Bool()) val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths val dataIn = Input(UInt(128.W)) val sizeIn = Input(UInt(3.W)) val rdLegal = Output(Bool()) val wrLegal = Output(Bool()) val rdDone = Output(Bool()) val wrDone = Output(Bool()) val respError = Output(Bool()) val dataOut = Output(UInt(8.W)) val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool())) val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W)) }) val rf_reset = IO(Input(Reset())) import SystemBusAccessState._ val (tl, edge) = node.out(0) val sbState = RegInit(0.U) // --- Drive payloads on bus to TileLink --- val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request d.ready := (sbState === SBReadResponse.id.U) \|\| (sbState === SBWriteResponse.id.U) val muxedData = WireInit(0.U(8.W)) val requestValid = tl.a.valid val requestReady = tl.a.ready val responseValid = d.valid val responseReady = d.ready val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W)) val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W))) vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8i+7,8i) } muxedData := vecData(counter(log2Ceil(vecData.size)-1,0)) // Need an additional check to determine if address is safe for Get/Put val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn) val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData) io.rdLegal := rdLegal_addr io.wrLegal := wrLegal_addr io.sbStateOut := sbState when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits } .otherwise { tl.a.bits := pfbits } tl.a.bits.user.lift(AMBAProt).foreach { x => x.bufferable := false.B x.modifiable := false.B x.readalloc := false.B x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B } val respError = d.bits.denied \|\| d.bits.corrupt io.respError := respError val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady val txLast = counter === ((1.U << io.sizeIn) - 1.U) counter := Mux((wrTxValid \|\| rdTxValid) && txLast, 0.U, Mux((wrTxValid \|\| rdTxValid) , counter+1.U, counter)) for (i <- 0 until (cfg.maxSupportedSBAccess/8)) { io.rdLoad(i) := rdTxValid && (counter === i.U) } // --- State Machine to interface with TileLink --- when (sbState === Idle.id.U){ sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U, Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState)) }.elsewhen (sbState === SBReadRequest.id.U){ sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState) }.elsewhen (sbState === SBWriteRequest.id.U){ sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState) }.elsewhen (sbState === SBReadResponse.id.U){ sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState) }.elsewhen (sbState === SBWriteResponse.id.U){ sbState := Mux(responseValid && responseReady, Idle.id.U, sbState) } io.rdDone := rdTxValid && txLast io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady io.dataOut := d.bits.data tl.a.valid := (sbState === SBReadRequest.id.U) \|\| (sbState === SBWriteRequest.id.U) // Tie off unused channels tl.b.ready := false.B tl.c.valid := false.B tl.e.valid := false.B assert (sbState === Idle.id.U \|\| sbState === SBReadRequest.id.U \|\| sbState === SBWriteRequest.id.U \|\| sbState === SBReadResponse.id.U \|\| sbState === SBWriteResponse.id.U, "SBA state machine in undefined state") property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle") property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req") property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req") property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp") property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp") property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal") property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal") } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLDebugModuleInner( // @[Debug.scala:790:9] input clock, // @[Debug.scala:790:9] input reset, // @[Debug.scala:790:9] input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_dmactive, // @[Debug.scala:803:16] input io_innerCtrl_valid, // @[Debug.scala:803:16] input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16] input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16] input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16] input io_innerCtrl_bits_hasel, // @[Debug.scala:803:16] input io_innerCtrl_bits_hamask_0, // @[Debug.scala:803:16] input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16] output io_hgDebugInt_0, // @[Debug.scala:803:16] input io_hartIsInReset_0, // @[Debug.scala:803:16] input io_tl_clock, // @[Debug.scala:803:16] input io_tl_reset // @[Debug.scala:803:16] ); wire out_front_1_valid; // @[RegisterRouter.scala:87:24] wire out_front_1_ready; // @[RegisterRouter.scala:87:24] wire out_1_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_1_bits_index; // @[RegisterRouter.scala:73:18] wire in_1_bits_read; // @[RegisterRouter.scala:73:18] wire [7:0] _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:71] wire [2:0] _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:71] wire [15:0] _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:71] wire [7:0] _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:74] wire [2:0] _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:74] wire [15:0] _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:74] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [6:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire SBDATAWrEn_0; // @[SBA.scala:150:35] wire [31:0] SBDATARdData_1; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_0; // @[SBA.scala:145:35] wire SBADDRESSWrEn_0; // @[SBA.scala:108:38] wire [7:0] _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:65] wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41] wire [31:0] _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52] wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52] wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52] wire auto_sb2tlOpt_out_a_ready_0 = auto_sb2tlOpt_out_a_ready; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_valid_0 = auto_sb2tlOpt_out_d_valid; // @[Debug.scala:790:9] wire [2:0] auto_sb2tlOpt_out_d_bits_opcode_0 = auto_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] auto_sb2tlOpt_out_d_bits_param_0 = auto_sb2tlOpt_out_d_bits_param; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_d_bits_size_0 = auto_sb2tlOpt_out_d_bits_size; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_sink_0 = auto_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_denied_0 = auto_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_d_bits_data_0 = auto_sb2tlOpt_out_d_bits_data; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_corrupt_0 = auto_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[Debug.scala:790:9] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[Debug.scala:790:9] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[Debug.scala:790:9] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[Debug.scala:790:9] wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_param_0 = auto_dmi_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_a_bits_size_0 = auto_dmi_in_a_bits_size; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_source_0 = auto_dmi_in_a_bits_source; // @[Debug.scala:790:9] wire [8:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:790:9] wire [3:0] auto_dmi_in_a_bits_mask_0 = auto_dmi_in_a_bits_mask; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_corrupt_0 = auto_dmi_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:790:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:790:9] wire io_innerCtrl_valid_0 = io_innerCtrl_valid; // @[Debug.scala:790:9] wire io_innerCtrl_bits_resumereq_0 = io_innerCtrl_bits_resumereq; // @[Debug.scala:790:9] wire [9:0] io_innerCtrl_bits_hartsel_0 = io_innerCtrl_bits_hartsel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_ackhavereset_0 = io_innerCtrl_bits_ackhavereset; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hasel_0 = io_innerCtrl_bits_hasel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hamask_0_0 = io_innerCtrl_bits_hamask_0; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hrmask_0_0 = io_innerCtrl_bits_hrmask_0; // @[Debug.scala:790:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:790:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:790:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_addr = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_ready = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_valid = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_addr = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_ready = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_valid = 1'h0; // @[MixedNode.scala:551:17] wire _dmiProgramBufferRdEn_WIRE_0 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_1 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_2 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_3 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_4 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_5 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_6 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_7 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_8 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_9 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_10 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_11 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_12 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_13 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_14 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_15 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_16 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_17 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_18 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_19 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_20 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_21 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_22 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_23 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_24 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_25 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_26 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_27 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_28 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_29 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_30 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_31 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_32 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_33 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_34 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_35 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_36 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_37 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_38 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_39 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_40 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_41 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_42 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_43 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_44 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_45 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_46 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_47 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_48 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_49 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_50 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_51 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_52 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_53 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_54 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_55 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_56 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_57 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_58 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_59 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_60 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_61 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_62 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_63 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_32 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_33 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_34 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_35 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_36 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_37 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_38 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_39 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_40 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_41 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_42 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_43 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_44 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_45 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_46 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_47 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_48 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_49 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_50 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_51 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_52 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_53 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_54 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_55 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_56 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_57 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_58 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_59 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_60 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_61 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_62 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_63 = 1'h0; // @[Debug.scala:889:53] wire _dmiAbstractDataRdEn_WIRE_0 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_1 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_2 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_3 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_4 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_5 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_6 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_7 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_8 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_9 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_10 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_11 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_12 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_13 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_14 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_15 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_16 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_17 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_18 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_19 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_20 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_21 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_22 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_23 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_24 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_25 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_26 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_27 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_28 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_29 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_30 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_31 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:893:52] wire _hamaskFull_WIRE_0 = 1'h0; // @[Debug.scala:903:38] wire _hamaskWrSel_WIRE_0 = 1'h0; // @[Debug.scala:933:39] wire _hrReset_WIRE_0 = 1'h0; // @[Debug.scala:945:38] wire hrReset_0 = 1'h0; // @[Debug.scala:945:30] wire _hrDebugIntReg_WIRE_0 = 1'h0; // @[Debug.scala:961:42] wire _DMSTATUSRdData_WIRE_impebreak = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allnonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anynonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authenticated = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authbusy = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_hasresethaltreq = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_confstrptrvalid = 1'h0; // @[Debug.scala:978:47] wire DMSTATUSRdData_impebreak = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyunavail = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_authbusy = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_confstrptrvalid = 1'h0; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anynonexistent_T = 1'h0; // @[Debug.scala:988:57] wire _DMSTATUSRdData_allnonexistent_T = 1'h0; // @[Debug.scala:991:57] wire _DMSTATUSRdData_anyunavail_T = 1'h0; // @[package.scala:74:72] wire _DMCS2RdData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1025:47] wire _DMCS2RdData_WIRE_hgselect = 1'h0; // @[Debug.scala:1025:47] wire DMCS2RdData_hgwrite = 1'h0; // @[Debug.scala:1025:34] wire DMCS2RdData_hgselect = 1'h0; // @[Debug.scala:1025:34] wire _DMCS2WrData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1026:47] wire _DMCS2WrData_WIRE_hgselect = 1'h0; // @[Debug.scala:1026:47] wire DMCS2WrData_hgwrite = 1'h0; // @[Debug.scala:1026:34] wire DMCS2WrData_hgselect = 1'h0; // @[Debug.scala:1026:34] wire hgselectWrEn = 1'h0; // @[Debug.scala:1027:34] wire hgwriteWrEn = 1'h0; // @[Debug.scala:1028:34] wire haltgroupWrEn = 1'h0; // @[Debug.scala:1029:34] wire exttriggerWrEn = 1'h0; // @[Debug.scala:1030:34] wire _hgDebugInt_WIRE_0 = 1'h0; // @[Debug.scala:1031:42] wire hgDebugInt_0 = 1'h0; // @[Debug.scala:1031:34] wire _selectedHaltedStatus_T = 1'h0; // @[Debug.scala:1172:53] wire _selectedHaltedStatus_T_1 = 1'h0; // @[Debug.scala:1172:59] wire _selectedHaltedStatus_T_2 = 1'h0; // @[Debug.scala:1172:114] wire _selectedHaltedStatus_WIRE = 1'h0; wire _ABSTRACTCSReset_WIRE_busy = 1'h0; // @[Debug.scala:1179:48] wire _ABSTRACTCSReset_WIRE_reserved2 = 1'h0; // @[Debug.scala:1179:48] wire ABSTRACTCSReset_busy = 1'h0; // @[Debug.scala:1179:35] wire ABSTRACTCSReset_reserved2 = 1'h0; // @[Debug.scala:1179:35] wire _ABSTRACTCSWrData_WIRE_busy = 1'h0; // @[Debug.scala:1184:52] wire _ABSTRACTCSWrData_WIRE_reserved2 = 1'h0; // @[Debug.scala:1184:52] wire ABSTRACTCSWrData_busy = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSWrData_reserved2 = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSRdData_reserved2 = 1'h0; // @[Debug.scala:1185:39] wire ABSTRACTCSRdEn = 1'h0; // @[Debug.scala:1187:34] wire ABSTRACTAUTORdEn = 1'h0; // @[Debug.scala:1239:36] wire _dmiAbstractDataAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1257:53] wire _dmiProgramBufferAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_32 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_33 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_34 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_35 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_36 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_37 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_38 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_39 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_40 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_41 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_42 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_43 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_44 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_45 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_46 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_47 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_48 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_49 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_50 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_51 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_52 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_53 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_54 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_55 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_56 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_57 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_58 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_59 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_60 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_61 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_62 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_63 = 1'h0; // @[Debug.scala:1260:54] wire _autoexecData_WIRE_0 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_1 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_2 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_3 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_4 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_5 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_6 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_7 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecProg_WIRE_0 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_1 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_2 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_3 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_4 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_5 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_6 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_7 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_8 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_9 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_10 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_11 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_12 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_13 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_14 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_15 = 1'h0; // @[Debug.scala:1268:41] wire authRdEnMaybe = 1'h0; // @[Debug.scala:1356:33] wire authWrEnMaybe = 1'h0; // @[Debug.scala:1357:33] wire _SBCSFieldsRegReset_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbbusy = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadondata = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:49:51] wire SBCSFieldsRegReset_sbbusyerror = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadonaddr = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbautoincrement = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadondata = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess128 = 1'h0; // @[SBA.scala:49:38] wire _SBCSRdData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbbusy = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:60:51] wire SBCSRdData_sbaccess128 = 1'h0; // @[SBA.scala:60:38] wire _SBCSWrData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbbusy = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_1 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_2 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_3 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_4 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_7 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_10 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_11 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_12 = 1'h0; // @[SBA.scala:63:61] wire SBCSWrData_sbbusy = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess128 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess64 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess32 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess16 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess8 = 1'h0; // @[SBA.scala:63:38] wire _SBADDRESSRdEn_WIRE_0 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_1 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_2 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_3 = 1'h0; // @[SBA.scala:107:46] wire SBADDRESSRdEn_1 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_2 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_3 = 1'h0; // @[SBA.scala:107:38] wire _SBADDRESSWrEn_WIRE_0 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_1 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_2 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_3 = 1'h0; // @[SBA.scala:108:46] wire SBADDRESSWrEn_1 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_2 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_3 = 1'h0; // @[SBA.scala:108:38] wire _SBDATARdEn_WIRE_0 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_1 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_2 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_3 = 1'h0; // @[SBA.scala:149:43] wire SBDATARdEn_2 = 1'h0; // @[SBA.scala:149:35] wire SBDATARdEn_3 = 1'h0; // @[SBA.scala:149:35] wire _SBDATAWrEn_WIRE_0 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_1 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_2 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_3 = 1'h0; // @[SBA.scala:150:43] wire SBDATAWrEn_2 = 1'h0; // @[SBA.scala:150:35] wire SBDATAWrEn_3 = 1'h0; // @[SBA.scala:150:35] wire _sbAccessError_T_1 = 1'h0; // @[SBA.scala:182:88] wire _sbAccessError_T_2 = 1'h0; // @[SBA.scala:182:58] wire _sbAccessError_T_4 = 1'h0; // @[SBA.scala:183:88] wire _sbAccessError_T_5 = 1'h0; // @[SBA.scala:183:58] wire _sbAccessError_T_6 = 1'h0; // @[SBA.scala:182:97] wire _sbAccessError_T_8 = 1'h0; // @[SBA.scala:184:88] wire _sbAccessError_T_9 = 1'h0; // @[SBA.scala:184:58] wire _sbAccessError_T_10 = 1'h0; // @[SBA.scala:183:97] wire _sbAccessError_T_12 = 1'h0; // @[SBA.scala:185:88] wire _sbAccessError_T_13 = 1'h0; // @[SBA.scala:185:58] wire _sbAccessError_T_14 = 1'h0; // @[SBA.scala:184:97] wire _SBCSRdData_WIRE_1_sbbusyerror = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbbusy = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadonaddr = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbautoincrement = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadondata = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess128 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess64 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess32 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess16 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess8 = 1'h0; // @[SBA.scala:243:33] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire _jalAbstract_WIRE_imm3 = 1'h0; // @[Debug.scala:1497:66] wire _jalAbstract_WIRE_imm1 = 1'h0; // @[Debug.scala:1497:66] wire jalAbstract_imm3 = 1'h0; // @[Debug.scala:1497:32] wire jalAbstract_imm1 = 1'h0; // @[Debug.scala:1497:32] wire _immBits_T = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_1 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_2 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_6 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_7 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_8 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_9 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_10 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_11 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_12 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_13 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_14 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_15 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_16 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_17 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_18 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_19 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_20 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_WIRE_0 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_1 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_2 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_6 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_7 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_8 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_9 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_10 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_11 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_12 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_13 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_14 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_15 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_16 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_17 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_18 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_19 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_20 = 1'h0; // @[Debug.scala:1575:39] wire immBits_0 = 1'h0; // @[Debug.scala:1575:31] wire immBits_1 = 1'h0; // @[Debug.scala:1575:31] wire immBits_2 = 1'h0; // @[Debug.scala:1575:31] wire immBits_6 = 1'h0; // @[Debug.scala:1575:31] wire immBits_7 = 1'h0; // @[Debug.scala:1575:31] wire immBits_8 = 1'h0; // @[Debug.scala:1575:31] wire immBits_9 = 1'h0; // @[Debug.scala:1575:31] wire immBits_10 = 1'h0; // @[Debug.scala:1575:31] wire immBits_11 = 1'h0; // @[Debug.scala:1575:31] wire immBits_12 = 1'h0; // @[Debug.scala:1575:31] wire immBits_13 = 1'h0; // @[Debug.scala:1575:31] wire immBits_14 = 1'h0; // @[Debug.scala:1575:31] wire immBits_15 = 1'h0; // @[Debug.scala:1575:31] wire immBits_16 = 1'h0; // @[Debug.scala:1575:31] wire immBits_17 = 1'h0; // @[Debug.scala:1575:31] wire immBits_18 = 1'h0; // @[Debug.scala:1575:31] wire immBits_19 = 1'h0; // @[Debug.scala:1575:31] wire immBits_20 = 1'h0; // @[Debug.scala:1575:31] wire _flags_WIRE_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_2_0_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_0_go = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_go = 1'h0; // @[Debug.scala:1517:33] wire flags_1_resume = 1'h0; // @[Debug.scala:1517:25] wire flags_1_go = 1'h0; // @[Debug.scala:1517:25] wire componentSel = 1'h0; // @[Debug.scala:1523:34] wire _out_rifireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_5 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] autoIncrementedAddr_hi = 64'h0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_hi = 64'h0; // @[SBA.scala:132:14] wire [63:0] sb2tlOpt_io_addrIn_hi_1 = 64'h0; // @[SBA.scala:133:10] wire [63:0] sb2tlOpt_io_dataIn_hi = 64'h0; // @[SBA.scala:175:59] wire [63:0] sb2tlOpt_io_dataIn_hi_1 = 64'h0; // @[SBA.scala:175:85] wire [63:0] _out_out_bits_data_WIRE_3_11 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_12 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_13 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_14 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_15 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_16 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_17 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_18 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_19 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_20 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_21 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_22 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_23 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_24 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_25 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_26 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_27 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_28 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_29 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_30 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_31 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_32 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_33 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_34 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_35 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_36 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_37 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_38 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_39 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_40 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_41 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_42 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_43 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_44 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_45 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_46 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_47 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_48 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_49 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_50 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_51 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_52 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_53 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_54 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_55 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_56 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_57 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_58 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_59 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_60 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_61 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_62 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_63 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_64 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_65 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_66 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_67 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_68 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_69 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_70 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_71 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_72 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_73 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_74 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_75 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_76 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_77 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_78 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_79 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_80 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_81 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_82 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_83 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_84 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_85 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_86 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_87 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_88 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_89 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_90 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_91 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_92 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_93 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_94 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_95 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_97 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_98 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_99 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_100 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_101 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_102 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_116 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_117 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_118 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_119 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_120 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_121 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_122 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_123 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_124 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_125 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_126 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_127 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] auto_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:790:9] wire [2:0] _ABSTRACTCSReset_WIRE_reserved0 = 3'h0; // @[Debug.scala:1179:48] wire [2:0] _ABSTRACTCSReset_WIRE_cmderr = 3'h0; // @[Debug.scala:1179:48] wire [2:0] ABSTRACTCSReset_reserved0 = 3'h0; // @[Debug.scala:1179:35] wire [2:0] ABSTRACTCSReset_cmderr = 3'h0; // @[Debug.scala:1179:35] wire [2:0] _ABSTRACTCSWrData_WIRE_reserved0 = 3'h0; // @[Debug.scala:1184:52] wire [2:0] _ABSTRACTCSWrData_WIRE_cmderr = 3'h0; // @[Debug.scala:1184:52] wire [2:0] ABSTRACTCSWrData_reserved0 = 3'h0; // @[Debug.scala:1184:39] wire [2:0] ABSTRACTCSRdData_reserved0 = 3'h0; // @[Debug.scala:1185:39] wire [2:0] _SBCSFieldsRegReset_WIRE_sbversion = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sbaccess = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sberror = 3'h0; // @[SBA.scala:49:51] wire [2:0] SBCSFieldsRegReset_sberror = 3'h0; // @[SBA.scala:49:38] wire [2:0] _SBCSRdData_WIRE_sbversion = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sbaccess = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sberror = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSWrData_WIRE_sbversion = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sbaccess = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sberror = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_6 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_9 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_14 = 3'h0; // @[SBA.scala:63:61] wire [2:0] SBCSWrData_sbversion = 3'h0; // @[SBA.scala:63:38] wire [2:0] _SBCSRdData_WIRE_1_sbversion = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sbaccess = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sberror = 3'h0; // @[SBA.scala:243:33] wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [2:0] jalAbstract_imm0_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] nop_funct3 = 3'h0; // @[Debug.scala:1623:19] wire [2:0] _nop_WIRE_funct3 = 3'h0; // @[Debug.scala:1624:46] wire [2:0] isa_funct3 = 3'h0; // @[Debug.scala:1629:19] wire [2:0] _isa_WIRE_funct3 = 3'h0; // @[Debug.scala:1630:47] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire auto_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:790:9] wire io_innerCtrl_ready = 1'h1; // @[Debug.scala:790:9] wire hamaskFull_0 = 1'h1; // @[Debug.scala:903:30] wire DMSTATUSRdData_authenticated = 1'h1; // @[Debug.scala:978:34] wire DMSTATUSRdData_hasresethaltreq = 1'h1; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anyhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T = 1'h1; // @[package.scala:79:37] wire SBCSFieldsRegReset_sbaccess64 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess32 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess16 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess8 = 1'h1; // @[SBA.scala:49:38] wire SBCSRdData_sbaccess64 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess32 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess16 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess8 = 1'h1; // @[SBA.scala:60:38] wire _sbAccessError_T_16 = 1'h1; // @[SBA.scala:186:88] wire _out_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_T_439 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _immBits_T_3 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_4 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_5 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_WIRE_3 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_4 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_5 = 1'h1; // @[Debug.scala:1575:39] wire immBits_3 = 1'h1; // @[Debug.scala:1575:31] wire immBits_4 = 1'h1; // @[Debug.scala:1575:31] wire immBits_5 = 1'h1; // @[Debug.scala:1575:31] wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire [31:0] SBCSWrDataVal = 32'h0; // @[SBA.scala:62:38] wire [31:0] _SBCSWrData_WIRE_1 = 32'h0; // @[SBA.scala:63:61] wire [31:0] _SBADDRESSWrData_WIRE_0 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_1 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_2 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_3 = 32'h0; // @[SBA.scala:106:46] wire [31:0] SBADDRESSWrData_1 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_2 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_3 = 32'h0; // @[SBA.scala:106:38] wire [31:0] _SBDATARdData_WIRE_0 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_1 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_2 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_3 = 32'h0; // @[SBA.scala:145:43] wire [31:0] SBDATARdData_2 = 32'h0; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_3 = 32'h0; // @[SBA.scala:145:35] wire [31:0] _SBDATAWrData_WIRE_0 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_1 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_2 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_3 = 32'h0; // @[SBA.scala:147:43] wire [31:0] SBDATAWrData_2 = 32'h0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_3 = 32'h0; // @[SBA.scala:147:35] wire [31:0] sb2tlOpt_io_dataIn_hi_lo = 32'h0; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_hi_hi = 32'h0; // @[SBA.scala:175:85] wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_2 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_12 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_13 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_14 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_15 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_16 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_18 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_20 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_21 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_25 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_26 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_27 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_28 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_29 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_30 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_31 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_48 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_49 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_50 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_51 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_52 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_53 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_54 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_55 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_58 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_59 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_62 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_63 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_420 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_578 = 32'h0; // @[RegisterRouter.scala:87:24] wire [5:0] _SBCSFieldsRegReset_WIRE_reserved0 = 6'h0; // @[SBA.scala:49:51] wire [5:0] SBCSFieldsRegReset_reserved0 = 6'h0; // @[SBA.scala:49:38] wire [5:0] _SBCSRdData_WIRE_reserved0 = 6'h0; // @[SBA.scala:60:51] wire [5:0] SBCSRdData_reserved0 = 6'h0; // @[SBA.scala:60:38] wire [5:0] _SBCSWrData_WIRE_reserved0 = 6'h0; // @[SBA.scala:63:61] wire [5:0] _SBCSWrData_T_13 = 6'h0; // @[SBA.scala:63:61] wire [5:0] SBCSWrData_reserved0 = 6'h0; // @[SBA.scala:63:38] wire [5:0] _SBCSRdData_WIRE_1_reserved0 = 6'h0; // @[SBA.scala:243:33] wire [5:0] _flags_WIRE_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_1_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_2_0_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] _flags_WIRE_2_1_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] flags_0_reserved = 6'h0; // @[Debug.scala:1517:25] wire [5:0] flags_1_reserved = 6'h0; // @[Debug.scala:1517:25] wire [3:0] _DMSTATUSRdData_WIRE_version = 4'h0; // @[Debug.scala:978:47] wire [3:0] _DMCS2RdData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1025:47] wire [3:0] DMCS2RdData_exttrigger = 4'h0; // @[Debug.scala:1025:34] wire [3:0] _DMCS2WrData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1026:47] wire [3:0] DMCS2WrData_exttrigger = 4'h0; // @[Debug.scala:1026:34] wire [3:0] _ABSTRACTCSReset_WIRE_reserved3 = 4'h0; // @[Debug.scala:1179:48] wire [3:0] _ABSTRACTCSReset_WIRE_datacount = 4'h0; // @[Debug.scala:1179:48] wire [3:0] ABSTRACTCSReset_reserved3 = 4'h0; // @[Debug.scala:1179:35] wire [3:0] _ABSTRACTCSWrData_WIRE_reserved3 = 4'h0; // @[Debug.scala:1184:52] wire [3:0] _ABSTRACTCSWrData_WIRE_datacount = 4'h0; // @[Debug.scala:1184:52] wire [3:0] ABSTRACTCSWrData_reserved3 = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSWrData_datacount = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSRdData_reserved3 = 4'h0; // @[Debug.scala:1185:39] wire [3:0] _ABSTRACTAUTOReset_WIRE_reserved0 = 4'h0; // @[Debug.scala:1234:54] wire [3:0] ABSTRACTAUTOReset_reserved0 = 4'h0; // @[Debug.scala:1234:41] wire [3:0] _ABSTRACTAUTOWrData_WIRE_reserved0 = 4'h0; // @[Debug.scala:1236:54] wire [3:0] ABSTRACTAUTOWrData_reserved0 = 4'h0; // @[Debug.scala:1236:41] wire [3:0] ABSTRACTAUTORdData_reserved0 = 4'h0; // @[Debug.scala:1237:41] wire [3:0] jalAbstract_imm2_lo = 4'h0; // @[package.scala:45:27] wire [3:0] jalAbstract_imm2_hi = 4'h0; // @[package.scala:45:27] wire [7:0] _out_T_1223 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1224 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_86 = 8'h8; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_85 = 5'h8; // @[RegisterRouter.scala:87:24] wire [3:0] ABSTRACTCSReset_datacount = 4'h8; // @[Debug.scala:1179:35] wire [3:0] ABSTRACTCSRdData_datacount = 4'h8; // @[Debug.scala:1185:39] wire [3:0] _out_T_1214 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1215 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_85 = 4'h8; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReset_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:54] wire [15:0] ABSTRACTAUTOReset_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:41] wire [15:0] _ABSTRACTAUTOWrData_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1236:54] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_hi = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_hi = 16'h0; // @[SBA.scala:175:85] wire [95:0] _sb2tlOpt_io_addrIn_T = 96'h0; // @[SBA.scala:132:14] wire [2:0] SBCSFieldsRegReset_sbversion = 3'h1; // @[SBA.scala:49:38] wire [2:0] SBCSRdData_sbversion = 3'h1; // @[SBA.scala:60:38] wire [10:0] _ABSTRACTCSReset_WIRE_reserved1 = 11'h0; // @[Debug.scala:1179:48] wire [10:0] ABSTRACTCSReset_reserved1 = 11'h0; // @[Debug.scala:1179:35] wire [10:0] _ABSTRACTCSWrData_WIRE_reserved1 = 11'h0; // @[Debug.scala:1184:52] wire [10:0] ABSTRACTCSWrData_reserved1 = 11'h0; // @[Debug.scala:1184:39] wire [10:0] ABSTRACTCSRdData_reserved1 = 11'h0; // @[Debug.scala:1185:39] wire [4:0] ABSTRACTCSReset_progbufsize = 5'h10; // @[Debug.scala:1179:35] wire [4:0] ABSTRACTCSRdData_progbufsize = 5'h10; // @[Debug.scala:1185:39] wire [7:0] _COMMANDReset_WIRE_cmdtype = 8'h0; // @[Debug.scala:1276:45] wire [7:0] COMMANDReset_cmdtype = 8'h0; // @[Debug.scala:1276:32] wire [7:0] _jalAbstract_WIRE_imm2 = 8'h0; // @[Debug.scala:1497:66] wire [7:0] jalAbstract_imm2 = 8'h0; // @[Debug.scala:1497:32] wire [7:0] _jalAbstract_imm2_T = 8'h0; // @[package.scala:45:27] wire [6:0] SBCSFieldsRegReset_sbasize = 7'h20; // @[SBA.scala:49:38] wire [6:0] SBCSRdData_sbasize = 7'h20; // @[SBA.scala:60:38] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] _DMSTATUSRdData_WIRE_reserved1 = 2'h0; // @[Debug.scala:978:47] wire [1:0] DMSTATUSRdData_reserved1 = 2'h0; // @[Debug.scala:978:34] wire [1:0] _haltedBitRegs_T_4 = 2'h0; // @[Debug.scala:1330:43] wire [1:0] _haltedBitRegs_T_6 = 2'h0; // @[Debug.scala:1330:69] wire [1:0] _resumeReqRegs_T_3 = 2'h0; // @[Debug.scala:1338:43] wire [1:0] _resumeReqRegs_T_5 = 2'h0; // @[Debug.scala:1338:69] wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [1:0] jalAbstract_imm0_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_3_96 = 64'h380006F; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_10 = 64'h100073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_349 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4404 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4405 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_9 = 64'h100026237B200073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_592 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6965 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6966 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_8 = 64'h7B20247310802423; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_866 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9839 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9840 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_7 = 64'hF140247330000067; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_1055 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11815 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11816 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_6 = 64'h100022237B202473; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_258 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3452 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3453 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_5 = 64'h4086300147413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_391 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4836 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4837 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_4 = 64'hFE0408E300347413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_641 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7469 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7470 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_3 = 64'h4004440310802023; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_950 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10719 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10720 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_2 = 64'hF14024737B241073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_202 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2860 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2861 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_1 = 64'hFF0000F0440006F; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_511 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6103 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6104 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_0 = 64'h380006F00C0006F; // @[MuxLiteral.scala:49:48] wire [55:0] out_prepend_1054 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11806 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11807 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1055 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1053 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11797 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11798 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1054 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1052 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11788 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11789 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1053 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1051 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11779 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11780 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1052 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1050 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11770 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11771 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1051 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1049 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11761 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11762 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1050 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4341 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4342 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_343 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6328 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6329 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_533 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10656 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10657 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_944 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11752 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11753 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1049 = 8'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_949 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10710 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10711 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_950 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_948 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10701 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10702 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_949 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_947 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10692 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10693 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_948 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_946 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10683 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10684 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_947 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_945 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10674 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10675 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_946 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_944 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10665 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10666 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_945 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_865 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9830 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9831 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_866 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_864 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9821 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9822 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_865 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_863 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9812 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9813 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_864 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_862 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9803 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9804 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_863 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_861 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9794 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9795 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_862 = 24'h67; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_860 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9785 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9786 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_861 = 16'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9776 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9777 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_860 = 8'h67; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_640 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7460 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7461 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_641 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_639 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7451 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7452 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_640 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_638 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7442 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7443 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_639 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_637 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7433 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7434 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_638 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_636 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7424 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7425 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_637 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_635 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7415 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7416 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_636 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6902 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6903 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_586 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7406 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7407 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_635 = 8'h23; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_591 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6956 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6957 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_592 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_590 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6947 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6948 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_591 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_589 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6938 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6939 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_590 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_588 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6929 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6930 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_589 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_587 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6920 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6921 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_588 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_586 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6911 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6912 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_587 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5142 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5143 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6821 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6822 = 42'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_420 = 33'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_578 = 33'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _jalAbstract_WIRE_imm0 = 10'h0; // @[Debug.scala:1497:66] wire [9:0] _jalAbstract_imm1_T = 10'h0; // @[package.scala:45:27] wire [9:0] _out_T_5133 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_5134 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6812 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6813 = 10'h0; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_535 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6355 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6356 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_534 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6346 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6347 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_535 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_343 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4350 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4351 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_344 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_533 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6337 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6338 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_534 = 16'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_510 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6094 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6095 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_511 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_509 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6085 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6086 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_510 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_508 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6076 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6077 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_509 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_507 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6067 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6068 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_508 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_506 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6058 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6059 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_507 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_196 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2806 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2807 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_197 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_505 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6049 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6050 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_506 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2797 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2798 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_196 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6040 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6041 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_505 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5943 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5944 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_390 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4827 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4828 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_391 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_389 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4818 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4819 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_390 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_388 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4809 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4810 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_389 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_387 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4800 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4801 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_388 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_386 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4791 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4792 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_387 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_252 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3398 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3399 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_253 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_385 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4782 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4783 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_386 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3389 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3390 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_252 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4773 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4774 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_385 = 8'h13; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_348 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4395 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4396 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_349 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_347 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4386 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4387 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_348 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_346 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4377 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4378 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_347 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_345 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4368 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4369 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_346 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_344 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4359 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4360 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_345 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_257 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3443 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3444 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_258 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_256 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3434 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3435 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_257 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_255 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3425 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3426 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_256 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_254 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3416 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3417 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_255 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_253 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3407 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3408 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_254 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_201 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2851 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2852 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_202 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_200 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2842 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2843 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_201 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_199 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2833 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2834 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_200 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_198 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2824 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2825 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_199 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_197 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2815 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2816 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_198 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch_1 = 9'h100; // @[RegisterRouter.scala:87:24] wire [11:0] hi = 12'h38; // @[Debug.scala:1697:55] wire [10:0] hi_hi = 11'h1C; // @[Debug.scala:1697:55] wire [19:0] lo = 20'h6F; // @[Debug.scala:1697:55] wire [12:0] lo_hi = 13'h0; // @[Debug.scala:1697:55] wire [31:0] _abstractGeneratedMem_0_T_3 = 32'h13; // @[Debug.scala:1642:15] wire [31:0] _abstractGeneratedMem_1_T = 32'h13; // @[Debug.scala:1645:15] wire [19:0] abstractGeneratedMem_0_hi_2 = 20'h0; // @[Debug.scala:1642:15] wire [19:0] abstractGeneratedMem_1_hi = 20'h0; // @[Debug.scala:1645:15] wire [16:0] abstractGeneratedMem_0_hi_hi_2 = 17'h0; // @[Debug.scala:1642:15] wire [16:0] abstractGeneratedMem_1_hi_hi = 17'h0; // @[Debug.scala:1645:15] wire [11:0] abstractGeneratedMem_0_lo_2 = 12'h13; // @[Debug.scala:1642:15] wire [11:0] abstractGeneratedMem_1_lo = 12'h13; // @[Debug.scala:1645:15] wire [6:0] abstractGeneratedMem_0_inst_1_opcode = 7'h23; // @[Debug.scala:1601:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_opcode = 7'h23; // @[Debug.scala:1604:55] wire [4:0] _DMCS2RdData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1025:47] wire [4:0] DMCS2RdData_haltgroup = 5'h0; // @[Debug.scala:1025:34] wire [4:0] _DMCS2WrData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1026:47] wire [4:0] DMCS2WrData_haltgroup = 5'h0; // @[Debug.scala:1026:34] wire [4:0] _ABSTRACTCSReset_WIRE_progbufsize = 5'h0; // @[Debug.scala:1179:48] wire [4:0] _ABSTRACTCSWrData_WIRE_progbufsize = 5'h0; // @[Debug.scala:1184:52] wire [4:0] ABSTRACTCSWrData_progbufsize = 5'h0; // @[Debug.scala:1184:39] wire [4:0] _jalAbstract_WIRE_rd = 5'h0; // @[Debug.scala:1497:66] wire [4:0] jalAbstract_rd = 5'h0; // @[Debug.scala:1497:32] wire [4:0] jalAbstract_imm0_hi = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_lo = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_hi = 5'h0; // @[package.scala:45:27] wire [4:0] nop_rs1 = 5'h0; // @[Debug.scala:1623:19] wire [4:0] nop_rd = 5'h0; // @[Debug.scala:1623:19] wire [4:0] _nop_WIRE_rs1 = 5'h0; // @[Debug.scala:1624:46] wire [4:0] _nop_WIRE_rd = 5'h0; // @[Debug.scala:1624:46] wire [4:0] isa_rs1 = 5'h0; // @[Debug.scala:1629:19] wire [4:0] isa_rd = 5'h0; // @[Debug.scala:1629:19] wire [4:0] _isa_WIRE_rs1 = 5'h0; // @[Debug.scala:1630:47] wire [4:0] _isa_WIRE_rd = 5'h0; // @[Debug.scala:1630:47] wire [4:0] abstractGeneratedMem_0_inst_rs1 = 5'h0; // @[Debug.scala:1589:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rs1 = 5'h0; // @[Debug.scala:1592:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rd = 5'h0; // @[Debug.scala:1592:55] wire [4:0] abstractGeneratedMem_0_inst_1_rs1 = 5'h0; // @[Debug.scala:1601:22] wire [4:0] abstractGeneratedMem_0_inst_1_immlo = 5'h0; // @[Debug.scala:1601:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs2 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs1 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immlo = 5'h0; // @[Debug.scala:1604:55] wire [2:0] SBCSFieldsRegReset_sbaccess = 3'h2; // @[SBA.scala:49:38] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_funct3 = 3'h2; // @[Debug.scala:1592:55] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_funct3 = 3'h2; // @[Debug.scala:1604:55] wire [6:0] _SBCSFieldsRegReset_WIRE_sbasize = 7'h0; // @[SBA.scala:49:51] wire [6:0] _SBCSRdData_WIRE_sbasize = 7'h0; // @[SBA.scala:60:51] wire [6:0] _SBCSWrData_WIRE_sbasize = 7'h0; // @[SBA.scala:63:61] wire [6:0] _SBCSWrData_T_5 = 7'h0; // @[SBA.scala:63:61] wire [6:0] SBCSWrData_sbasize = 7'h0; // @[SBA.scala:63:38] wire [6:0] _SBCSRdData_WIRE_1_sbasize = 7'h0; // @[SBA.scala:243:33] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immhi = 7'h0; // @[Debug.scala:1604:55] wire [6:0] abstractGeneratedMem_0_inst_1_immhi = 7'h1C; // @[Debug.scala:1601:22] wire [16:0] abstractGeneratedMem_0_hi_hi = 17'h7000; // @[Debug.scala:1597:12] wire [6:0] abstractGeneratedMem_0_inst_opcode = 7'h3; // @[Debug.scala:1589:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_opcode = 7'h3; // @[Debug.scala:1592:55] wire [11:0] _ABSTRACTAUTOReset_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1234:54] wire [11:0] ABSTRACTAUTOReset_autoexecdata = 12'h0; // @[Debug.scala:1234:41] wire [11:0] _ABSTRACTAUTOWrData_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1236:54] wire [11:0] nop_imm = 12'h0; // @[Debug.scala:1623:19] wire [11:0] _nop_WIRE_imm = 12'h0; // @[Debug.scala:1624:46] wire [11:0] isa_imm = 12'h0; // @[Debug.scala:1629:19] wire [11:0] _isa_WIRE_imm = 12'h0; // @[Debug.scala:1630:47] wire [11:0] _abstractGeneratedMem_0_inst_opcode_WIRE_imm = 12'h0; // @[Debug.scala:1592:55] wire [11:0] abstractGeneratedMem_0_inst_imm = 12'h380; // @[Debug.scala:1589:22] wire [6:0] isa_opcode = 7'h1B; // @[Debug.scala:1629:19] wire [6:0] _isa_WIRE_opcode = 7'h1B; // @[Debug.scala:1630:47] wire [6:0] nop_opcode = 7'h13; // @[Debug.scala:1623:19] wire [6:0] _nop_WIRE_opcode = 7'h13; // @[Debug.scala:1624:46] wire [9:0] jalAbstract_imm0 = 10'h1C; // @[Debug.scala:1497:32] wire [9:0] _jalAbstract_imm0_T = 10'h1C; // @[package.scala:45:27] wire [4:0] jalAbstract_imm0_lo = 5'h1C; // @[package.scala:45:27] wire [2:0] out_prepend_25 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_456 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_457 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_prepend_T_26 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] jalAbstract_imm0_lo_hi = 3'h7; // @[package.scala:45:27] wire [1:0] out_prepend_24 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_447 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_448 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_25 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] jalAbstract_imm0_lo_hi_hi = 2'h3; // @[package.scala:45:27] wire [20:0] immWire = 21'h38; // @[Debug.scala:1574:31] wire [6:0] _jalAbstract_WIRE_opcode = 7'h6F; // @[Debug.scala:1497:66] wire [6:0] jalAbstract_opcode = 7'h6F; // @[Debug.scala:1497:32] wire [7:0] out_prepend_64 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_991 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_992 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_65 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [6:0] out_prepend_63 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_982 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_983 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_prepend_T_64 = 7'h22; // @[RegisterRouter.scala:87:24] wire [5:0] out_prepend_62 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_973 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_974 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_prepend_T_63 = 6'h22; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_61 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_964 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_965 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_62 = 5'h2; // @[RegisterRouter.scala:87:24] wire [3:0] DMSTATUSRdData_version = 4'h2; // @[Debug.scala:978:34] wire [3:0] _out_T_955 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_956 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_61 = 4'h2; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_28 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_483 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_484 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_29 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_27 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_474 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_475 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_28 = 5'hF; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend_26 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_465 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_466 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_27 = 4'hF; // @[RegisterRouter.scala:87:24] wire [6:0] out_maskMatch = 7'h40; // @[RegisterRouter.scala:87:24] wire [1:0] _haltedBitRegs_T_3 = 2'h2; // @[Debug.scala:1330:45] wire [1:0] _resumeReqRegs_T_2 = 2'h2; // @[Debug.scala:1338:45] wire [1:0] hartHaltedIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] hartResumingIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _haltedBitRegs_T = 2'h1; // @[Debug.scala:1327:43] wire [23:0] _COMMANDReset_WIRE_control = 24'h0; // @[Debug.scala:1276:45] wire [23:0] COMMANDReset_control = 24'h0; // @[Debug.scala:1276:32] wire [20:0] _DMCS2RdData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1025:47] wire [20:0] DMCS2RdData_reserved0 = 21'h0; // @[Debug.scala:1025:34] wire [20:0] _DMCS2WrData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1026:47] wire [20:0] DMCS2WrData_reserved0 = 21'h0; // @[Debug.scala:1026:34] wire [8:0] _DMSTATUSRdData_WIRE_reserved0 = 9'h0; // @[Debug.scala:978:47] wire [8:0] DMSTATUSRdData_reserved0 = 9'h0; // @[Debug.scala:978:34] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[Debug.scala:790:9] wire [11:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[Debug.scala:790:9] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[Debug.scala:790:9] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_param = auto_dmi_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_a_bits_size = auto_dmi_in_a_bits_size_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_source = auto_dmi_in_a_bits_source_0; // @[Debug.scala:790:9] wire [8:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:790:9] wire [3:0] dmiNodeIn_a_bits_mask = auto_dmi_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_corrupt = auto_dmi_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] dmiNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire _resumereq_T = io_innerCtrl_valid_0; // @[Decoupled.scala:51:35] wire hrDebugInt_0; // @[Debug.scala:946:26] wire [2:0] auto_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:790:9] wire [31:0] auto_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_valid_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_ready_0; // @[Debug.scala:790:9] wire auto_tl_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_d_bits_size_0; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_d_bits_source_0; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_tl_in_d_valid_0; // @[Debug.scala:790:9] wire auto_dmi_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_size_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_source_0; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_valid_0; // @[Debug.scala:790:9] wire io_hgDebugInt_0_0; // @[Debug.scala:790:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:790:9] wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = dmiNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire in_bits_extra_tlrr_extra_source = dmiNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [3:0] in_bits_mask = dmiNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_size_0 = dmiNodeIn_d_bits_size; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_source_0 = dmiNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:790:9] wire in_1_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[Debug.scala:790:9] wire in_1_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_1_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_1_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_1_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_1_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_1_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_1_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [63:0] out_1_bits_data; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_bits_data_0 = tlNodeIn_d_bits_data; // @[Debug.scala:790:9] reg haltedBitRegs; // @[Debug.scala:861:31] wire _DMSTATUSRdData_anyhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :995:77] wire _DMSTATUSRdData_anyrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :996:77] wire _DMSTATUSRdData_allhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1001:79] wire _DMSTATUSRdData_allrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1002:79] wire _haltedStatus_0_T = haltedBitRegs; // @[Debug.scala:861:31, :1163:43] wire _hartHalted_T = haltedBitRegs; // @[Debug.scala:861:31, :1734:37] reg resumeReqRegs; // @[Debug.scala:863:31] wire _flags_resume_T = resumeReqRegs; // @[Debug.scala:863:31, :1524:80] reg haveResetBitRegs; // @[Debug.scala:865:31] wire _DMSTATUSRdData_anyhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :997:58] wire _DMSTATUSRdData_allhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :1003:60] wire resumeAcks; // @[Debug.scala:869:32] wire _DMSTATUSRdData_anyresumeack_T = resumeAcks; // @[Debug.scala:869:32, :998:52] wire _DMSTATUSRdData_allresumeack_T = resumeAcks; // @[Debug.scala:869:32, :1004:54] wire out_f_woready_681; // @[RegisterRouter.scala:87:24] wire hartHaltedWrEn; // @[Debug.scala:875:36] wire [9:0] _out_T_6805; // @[RegisterRouter.scala:87:24] wire [9:0] hartHaltedId; // @[Debug.scala:876:36] wire out_f_woready_682; // @[RegisterRouter.scala:87:24] wire hartGoingWrEn; // @[Debug.scala:877:36] wire [9:0] _out_T_6814; // @[RegisterRouter.scala:87:24] wire [9:0] hartGoingId; // @[Debug.scala:878:36] wire out_f_woready_498; // @[RegisterRouter.scala:87:24] wire hartResumingWrEn; // @[Debug.scala:879:36] wire [9:0] _out_T_5126; // @[RegisterRouter.scala:87:24] wire [9:0] hartResumingId; // @[Debug.scala:880:36] wire out_f_woready_499; // @[RegisterRouter.scala:87:24] wire hartExceptionWrEn; // @[Debug.scala:881:36] wire [9:0] _out_T_5135; // @[RegisterRouter.scala:87:24] wire [9:0] hartExceptionId; // @[Debug.scala:882:36] wire out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_roready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_0; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_1; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_2; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_3; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_4; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_5; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_6; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_7; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_8; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_9; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_10; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_11; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_12; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_13; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_14; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_15; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_16; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_17; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_18; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_19; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_20; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_21; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_22; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_23; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_24; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_25; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_26; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_27; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_28; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_29; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_30; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_31; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_32; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_33; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_34; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_35; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_36; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_37; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_38; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_39; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_40; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_41; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_42; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_43; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_44; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_45; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_46; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_47; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_48; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_49; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_50; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_51; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_52; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_53; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_54; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_55; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_56; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_57; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_58; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_59; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_60; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_61; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_62; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_63; // @[Debug.scala:887:40] wire _dmiProgramBufferAccessLegal_T; // @[Debug.scala:1746:50] wire dmiProgramBufferAccessLegal; // @[Debug.scala:888:47] wire out_f_woready_101; // @[RegisterRouter.scala:87:24] wire out_f_woready_102; // @[RegisterRouter.scala:87:24] wire out_f_woready_103; // @[RegisterRouter.scala:87:24] wire out_f_woready_104; // @[RegisterRouter.scala:87:24] wire out_f_woready_73; // @[RegisterRouter.scala:87:24] wire out_f_woready_74; // @[RegisterRouter.scala:87:24] wire out_f_woready_75; // @[RegisterRouter.scala:87:24] wire out_f_woready_76; // @[RegisterRouter.scala:87:24] wire out_f_woready_105; // @[RegisterRouter.scala:87:24] wire out_f_woready_106; // @[RegisterRouter.scala:87:24] wire out_f_woready_107; // @[RegisterRouter.scala:87:24] wire out_f_woready_108; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_141; // @[RegisterRouter.scala:87:24] wire out_f_woready_142; // @[RegisterRouter.scala:87:24] wire out_f_woready_143; // @[RegisterRouter.scala:87:24] wire out_f_woready_144; // @[RegisterRouter.scala:87:24] wire out_f_woready_55; // @[RegisterRouter.scala:87:24] wire out_f_woready_56; // @[RegisterRouter.scala:87:24] wire out_f_woready_57; // @[RegisterRouter.scala:87:24] wire out_f_woready_58; // @[RegisterRouter.scala:87:24] wire out_f_woready_69; // @[RegisterRouter.scala:87:24] wire out_f_woready_70; // @[RegisterRouter.scala:87:24] wire out_f_woready_71; // @[RegisterRouter.scala:87:24] wire out_f_woready_72; // @[RegisterRouter.scala:87:24] wire out_f_woready_124; // @[RegisterRouter.scala:87:24] wire out_f_woready_125; // @[RegisterRouter.scala:87:24] wire out_f_woready_126; // @[RegisterRouter.scala:87:24] wire out_f_woready_127; // @[RegisterRouter.scala:87:24] wire out_f_woready_136; // @[RegisterRouter.scala:87:24] wire out_f_woready_137; // @[RegisterRouter.scala:87:24] wire out_f_woready_138; // @[RegisterRouter.scala:87:24] wire out_f_woready_139; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_48; // @[RegisterRouter.scala:87:24] wire out_f_woready_49; // @[RegisterRouter.scala:87:24] wire out_f_woready_50; // @[RegisterRouter.scala:87:24] wire out_f_woready_51; // @[RegisterRouter.scala:87:24] wire out_f_woready_132; // @[RegisterRouter.scala:87:24] wire out_f_woready_133; // @[RegisterRouter.scala:87:24] wire out_f_woready_134; // @[RegisterRouter.scala:87:24] wire out_f_woready_135; // @[RegisterRouter.scala:87:24] wire out_f_woready_116; // @[RegisterRouter.scala:87:24] wire out_f_woready_117; // @[RegisterRouter.scala:87:24] wire out_f_woready_118; // @[RegisterRouter.scala:87:24] wire out_f_woready_119; // @[RegisterRouter.scala:87:24] wire out_f_woready_77; // @[RegisterRouter.scala:87:24] wire out_f_woready_78; // @[RegisterRouter.scala:87:24] wire out_f_woready_79; // @[RegisterRouter.scala:87:24] wire out_f_woready_80; // @[RegisterRouter.scala:87:24] wire out_f_woready_59; // @[RegisterRouter.scala:87:24] wire out_f_woready_60; // @[RegisterRouter.scala:87:24] wire out_f_woready_61; // @[RegisterRouter.scala:87:24] wire out_f_woready_62; // @[RegisterRouter.scala:87:24] wire out_f_woready_25; // @[RegisterRouter.scala:87:24] wire out_f_woready_26; // @[RegisterRouter.scala:87:24] wire out_f_woready_27; // @[RegisterRouter.scala:87:24] wire out_f_woready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_0; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_1; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_2; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_3; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_4; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_5; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_6; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_7; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_8; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_9; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_10; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_11; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_12; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_13; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_14; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_15; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_16; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_17; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_18; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_19; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_20; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_21; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_22; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_23; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_24; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_25; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_26; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_27; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_28; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_29; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_30; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_31; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_32; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_33; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_34; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_35; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_36; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_37; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_38; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_39; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_40; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_41; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_42; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_43; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_44; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_45; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_46; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_47; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_48; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_49; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_50; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_51; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_52; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_53; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_54; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_55; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_56; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_57; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_58; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_59; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_60; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_61; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_62; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_63; // @[Debug.scala:889:45] wire out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_roready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_0; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_1; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_2; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_3; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_4; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_5; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_6; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_7; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_8; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_9; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_10; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_11; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_12; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_13; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_14; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_15; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_16; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_17; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_18; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_19; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_20; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_21; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_22; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_23; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_24; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_25; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_26; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_27; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_28; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_29; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_30; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_31; // @[Debug.scala:891:39] wire _dmiAbstractDataAccessLegal_T; // @[Debug.scala:1745:50] wire dmiAbstractDataAccessLegal; // @[Debug.scala:892:46] wire out_f_woready_21; // @[RegisterRouter.scala:87:24] wire out_f_woready_22; // @[RegisterRouter.scala:87:24] wire out_f_woready_23; // @[RegisterRouter.scala:87:24] wire out_f_woready_24; // @[RegisterRouter.scala:87:24] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_64; // @[RegisterRouter.scala:87:24] wire out_f_woready_65; // @[RegisterRouter.scala:87:24] wire out_f_woready_66; // @[RegisterRouter.scala:87:24] wire out_f_woready_67; // @[RegisterRouter.scala:87:24] wire out_f_woready_120; // @[RegisterRouter.scala:87:24] wire out_f_woready_121; // @[RegisterRouter.scala:87:24] wire out_f_woready_122; // @[RegisterRouter.scala:87:24] wire out_f_woready_123; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire out_f_woready_18; // @[RegisterRouter.scala:87:24] wire out_f_woready_19; // @[RegisterRouter.scala:87:24] wire out_f_woready_20; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_29; // @[RegisterRouter.scala:87:24] wire out_f_woready_30; // @[RegisterRouter.scala:87:24] wire out_f_woready_31; // @[RegisterRouter.scala:87:24] wire out_f_woready_32; // @[RegisterRouter.scala:87:24] wire out_f_woready_128; // @[RegisterRouter.scala:87:24] wire out_f_woready_129; // @[RegisterRouter.scala:87:24] wire out_f_woready_130; // @[RegisterRouter.scala:87:24] wire out_f_woready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_0; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_1; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_2; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_3; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_4; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_5; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_6; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_7; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_8; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_9; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_10; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_11; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_12; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_13; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_14; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_15; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_16; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_17; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_18; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_19; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_20; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_21; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_22; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_23; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_24; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_25; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_26; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_27; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_28; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_29; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_30; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_31; // @[Debug.scala:893:44] wire _hamaskWrSel_0_T_1; // @[Debug.scala:935:78] wire hamaskWrSel_0; // @[Debug.scala:933:31] wire _hamaskWrSel_0_T = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:790:9, :935:61] assign _hamaskWrSel_0_T_1 = _hamaskWrSel_0_T; // @[Debug.scala:935:{61,78}] assign hamaskWrSel_0 = _hamaskWrSel_0_T_1; // @[Debug.scala:933:31, :935:78] assign io_hgDebugInt_0_0 = hrDebugInt_0; // @[Debug.scala:790:9, :946:26] reg hrmaskReg_0; // @[Debug.scala:947:29] wire _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] wire hartIsInResetSync_0; // @[Debug.scala:948:33] assign hartIsInResetSync_0 = _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] reg hrDebugIntReg_0; // @[Debug.scala:961:34] assign hrDebugInt_0 = hrDebugIntReg_0; // @[Debug.scala:946:26, :961:34] wire _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:991:75] wire DMSTATUSRdData_allhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_allresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_allnonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_allunavail; // @[Debug.scala:978:34] wire DMSTATUSRdData_allrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_allhalted; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhalted; // @[Debug.scala:978:34] wire resumereq = _resumereq_T & io_innerCtrl_bits_resumereq_0; // @[Decoupled.scala:51:35] assign DMSTATUSRdData_anynonexistent = _DMSTATUSRdData_anynonexistent_T; // @[Debug.scala:978:34, :988:57] wire _DMSTATUSRdData_allnonexistent_T_1 = ~hamaskFull_0; // @[Debug.scala:903:30, :991:78] assign _DMSTATUSRdData_allnonexistent_T_2 = _DMSTATUSRdData_allnonexistent_T & _DMSTATUSRdData_allnonexistent_T_1; // @[Debug.scala:991:{57,75,78}] assign DMSTATUSRdData_allnonexistent = _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:978:34, :991:75] wire _DMSTATUSRdData_anyhalted_T_2 = _DMSTATUSRdData_anyhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhalted_T_3 = _DMSTATUSRdData_anyhalted_T_2 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhalted = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhalted_T_3; // @[package.scala:74:72] wire _DMSTATUSRdData_anyrunning_T_2 = ~_DMSTATUSRdData_anyrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T_3 = _DMSTATUSRdData_anyrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_anyrunning_T_4 = _DMSTATUSRdData_anyrunning_T_3 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyrunning = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyrunning_T_4; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhavereset_T_1 = _DMSTATUSRdData_anyhavereset_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhavereset = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhavereset_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyresumeack_T_1 = _DMSTATUSRdData_anyresumeack_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyresumeack = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyresumeack_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allunavail_T = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allunavail_T_1 = _DMSTATUSRdData_allunavail_T; // @[package.scala:75:75, :79:37] wire _GEN = ~DMSTATUSRdData_allnonexistent & ~DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34, :993:{13,45}, :999:{15,47}, :1000:39] assign DMSTATUSRdData_allunavail = _GEN & _DMSTATUSRdData_allunavail_T_1; // @[package.scala:75:75] wire _DMSTATUSRdData_allhalted_T_2 = _DMSTATUSRdData_allhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allhalted_T_3 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T_4 = _DMSTATUSRdData_allhalted_T_2 \| _DMSTATUSRdData_allhalted_T_3; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allhalted = _GEN & _DMSTATUSRdData_allhalted_T_4; // @[package.scala:75:75] wire _DMSTATUSRdData_allrunning_T_2 = ~_DMSTATUSRdData_allrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_3 = _DMSTATUSRdData_allrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_allrunning_T_4 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_5 = _DMSTATUSRdData_allrunning_T_3 \| _DMSTATUSRdData_allrunning_T_4; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allrunning = _GEN & _DMSTATUSRdData_allrunning_T_5; // @[package.scala:75:75] wire _DMSTATUSRdData_allhavereset_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhavereset_T_2 = _DMSTATUSRdData_allhavereset_T \| _DMSTATUSRdData_allhavereset_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allhavereset = _GEN & _DMSTATUSRdData_allhavereset_T_2; // @[package.scala:75:75] wire _DMSTATUSRdData_allresumeack_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allresumeack_T_2 = _DMSTATUSRdData_allresumeack_T \| _DMSTATUSRdData_allresumeack_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allresumeack = _GEN & _DMSTATUSRdData_allresumeack_T_2; // @[package.scala:75:75] wire _haveResetBitRegs_T = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50] wire _haveResetBitRegs_T_1 = haveResetBitRegs & _haveResetBitRegs_T; // @[Debug.scala:865:31, :1017:{47,50}] wire _haveResetBitRegs_T_2 = _haveResetBitRegs_T_1 \| hartIsInResetSync_0; // @[Debug.scala:948:33, :1017:{47,74}] wire _haveResetBitRegs_T_3 = haveResetBitRegs \| hartIsInResetSync_0; // @[Debug.scala:865:31, :948:33, :1019:46] wire [31:0] haltedStatus_0; // @[Debug.scala:1159:30] wire [31:0] selectedHaltedStatus = haltedStatus_0; // @[Debug.scala:1159:30, :1172:35] assign haltedStatus_0 = {31'h0, _haltedStatus_0_T}; // @[Debug.scala:1159:30, :1163:{26,43}] wire haltedSummary = \|haltedStatus_0; // @[Debug.scala:1159:30, :1169:48] wire [31:0] _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] HALTSUM1RdData_haltsum1; // @[Debug.scala:1170:48] wire [31:0] _out_T_1598 = HALTSUM1RdData_haltsum1; // @[RegisterRouter.scala:87:24] assign _HALTSUM1RdData_T = _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] assign _HALTSUM1RdData_WIRE = {31'h0, haltedSummary}; // @[Debug.scala:1169:48, :1170:48] assign HALTSUM1RdData_haltsum1 = _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] _HALTSUM0RdData_WIRE = selectedHaltedStatus; // @[Debug.scala:1172:35, :1173:55] wire [31:0] _HALTSUM0RdData_T; // @[Debug.scala:1173:55] wire [31:0] HALTSUM0RdData_haltsum0; // @[Debug.scala:1173:55] wire [31:0] _out_T_946 = HALTSUM0RdData_haltsum0; // @[RegisterRouter.scala:87:24] assign _HALTSUM0RdData_T = _HALTSUM0RdData_WIRE; // @[Debug.scala:1173:55] assign HALTSUM0RdData_haltsum0 = _HALTSUM0RdData_T; // @[Debug.scala:1173:55] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34] wire [2:0] ABSTRACTCSRdData_cmderr = ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34, :1185:39] wire [2:0] _out_T_1225; // @[RegisterRouter.scala:87:24] wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39] wire abstractCommandBusy; // @[Debug.scala:1220:39] wire ABSTRACTCSRdData_busy; // @[Debug.scala:1185:39] wire out_f_woready_111; // @[RegisterRouter.scala:87:24] wire ABSTRACTCSWrEnMaybe; // @[Debug.scala:1188:39] wire _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1742:44] wire ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39] wire ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala:1188:39, :1190:39, :1191:51] wire _errorBusy_T_16; // @[Debug.scala:1752:74] wire errorBusy; // @[Debug.scala:1195:36] wire errorException; // @[Debug.scala:1196:36] wire errorUnsupported; // @[Debug.scala:1197:36] wire errorHaltResume; // @[Debug.scala:1198:36] wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39, :1214:58] wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala:1183:34, :1214:{56,58}] wire _abstractCommandBusy_T; // @[Debug.scala:1740:42] assign ABSTRACTCSRdData_busy = abstractCommandBusy; // @[Debug.scala:1185:39, :1220:39] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36] wire [15:0] ABSTRACTAUTORdData_autoexecprogbuf = ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36, :1237:41] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36] wire [11:0] ABSTRACTAUTORdData_autoexecdata = ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36, :1237:41] wire [15:0] _out_T_642; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReg_autoexecprogbuf_T = ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41, :1249:79] wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala:1236:41] wire [11:0] _out_T_631 = ABSTRACTAUTORdData_autoexecdata; // @[RegisterRouter.scala:87:24] wire out_f_woready_52; // @[RegisterRouter.scala:87:24] wire autoexecdataWrEnMaybe; // @[Debug.scala:1240:41] wire out_f_woready_54; // @[RegisterRouter.scala:87:24] wire autoexecprogbufWrEnMaybe; // @[Debug.scala:1241:44] wire _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1744:44] wire ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41] wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = {4'h0, ABSTRACTAUTOWrData_autoexecdata[7:0]}; // @[Debug.scala:1236:41, :1252:73] wire dmiAbstractDataAccessVec_0; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45] assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 \| dmiAbstractDataRdEn_0; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 \| dmiAbstractDataRdEn_1; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 \| dmiAbstractDataRdEn_2; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 \| dmiAbstractDataRdEn_3; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 \| dmiAbstractDataRdEn_4; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_5 = dmiAbstractDataWrEnMaybe_5 \| dmiAbstractDataRdEn_5; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_6 = dmiAbstractDataWrEnMaybe_6 \| dmiAbstractDataRdEn_6; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_7 = dmiAbstractDataWrEnMaybe_7 \| dmiAbstractDataRdEn_7; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 \| dmiAbstractDataRdEn_8; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_9 = dmiAbstractDataWrEnMaybe_9 \| dmiAbstractDataRdEn_9; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_10 = dmiAbstractDataWrEnMaybe_10 \| dmiAbstractDataRdEn_10; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_11 = dmiAbstractDataWrEnMaybe_11 \| dmiAbstractDataRdEn_11; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 \| dmiAbstractDataRdEn_12; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_13 = dmiAbstractDataWrEnMaybe_13 \| dmiAbstractDataRdEn_13; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_14 = dmiAbstractDataWrEnMaybe_14 \| dmiAbstractDataRdEn_14; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_15 = dmiAbstractDataWrEnMaybe_15 \| dmiAbstractDataRdEn_15; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 \| dmiAbstractDataRdEn_16; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_17 = dmiAbstractDataWrEnMaybe_17 \| dmiAbstractDataRdEn_17; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_18 = dmiAbstractDataWrEnMaybe_18 \| dmiAbstractDataRdEn_18; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_19 = dmiAbstractDataWrEnMaybe_19 \| dmiAbstractDataRdEn_19; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 \| dmiAbstractDataRdEn_20; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_21 = dmiAbstractDataWrEnMaybe_21 \| dmiAbstractDataRdEn_21; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_22 = dmiAbstractDataWrEnMaybe_22 \| dmiAbstractDataRdEn_22; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_23 = dmiAbstractDataWrEnMaybe_23 \| dmiAbstractDataRdEn_23; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 \| dmiAbstractDataRdEn_24; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_25 = dmiAbstractDataWrEnMaybe_25 \| dmiAbstractDataRdEn_25; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_26 = dmiAbstractDataWrEnMaybe_26 \| dmiAbstractDataRdEn_26; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_27 = dmiAbstractDataWrEnMaybe_27 \| dmiAbstractDataRdEn_27; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 \| dmiAbstractDataRdEn_28; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_29 = dmiAbstractDataWrEnMaybe_29 \| dmiAbstractDataRdEn_29; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_30 = dmiAbstractDataWrEnMaybe_30 \| dmiAbstractDataRdEn_30; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_31 = dmiAbstractDataWrEnMaybe_31 \| dmiAbstractDataRdEn_31; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] wire dmiProgramBufferAccessVec_0; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46] assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 \| dmiProgramBufferRdEn_0; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 \| dmiProgramBufferRdEn_1; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 \| dmiProgramBufferRdEn_2; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 \| dmiProgramBufferRdEn_3; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 \| dmiProgramBufferRdEn_4; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 \| dmiProgramBufferRdEn_5; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 \| dmiProgramBufferRdEn_6; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 \| dmiProgramBufferRdEn_7; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 \| dmiProgramBufferRdEn_8; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 \| dmiProgramBufferRdEn_9; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 \| dmiProgramBufferRdEn_10; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 \| dmiProgramBufferRdEn_11; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 \| dmiProgramBufferRdEn_12; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 \| dmiProgramBufferRdEn_13; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 \| dmiProgramBufferRdEn_14; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 \| dmiProgramBufferRdEn_15; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 \| dmiProgramBufferRdEn_16; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 \| dmiProgramBufferRdEn_17; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 \| dmiProgramBufferRdEn_18; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 \| dmiProgramBufferRdEn_19; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 \| dmiProgramBufferRdEn_20; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 \| dmiProgramBufferRdEn_21; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 \| dmiProgramBufferRdEn_22; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 \| dmiProgramBufferRdEn_23; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 \| dmiProgramBufferRdEn_24; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 \| dmiProgramBufferRdEn_25; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 \| dmiProgramBufferRdEn_26; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 \| dmiProgramBufferRdEn_27; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 \| dmiProgramBufferRdEn_28; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 \| dmiProgramBufferRdEn_29; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 \| dmiProgramBufferRdEn_30; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 \| dmiProgramBufferRdEn_31; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 \| dmiProgramBufferRdEn_32; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 \| dmiProgramBufferRdEn_33; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 \| dmiProgramBufferRdEn_34; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 \| dmiProgramBufferRdEn_35; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 \| dmiProgramBufferRdEn_36; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 \| dmiProgramBufferRdEn_37; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 \| dmiProgramBufferRdEn_38; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 \| dmiProgramBufferRdEn_39; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 \| dmiProgramBufferRdEn_40; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 \| dmiProgramBufferRdEn_41; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 \| dmiProgramBufferRdEn_42; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 \| dmiProgramBufferRdEn_43; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 \| dmiProgramBufferRdEn_44; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 \| dmiProgramBufferRdEn_45; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 \| dmiProgramBufferRdEn_46; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 \| dmiProgramBufferRdEn_47; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 \| dmiProgramBufferRdEn_48; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 \| dmiProgramBufferRdEn_49; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 \| dmiProgramBufferRdEn_50; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 \| dmiProgramBufferRdEn_51; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 \| dmiProgramBufferRdEn_52; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 \| dmiProgramBufferRdEn_53; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 \| dmiProgramBufferRdEn_54; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 \| dmiProgramBufferRdEn_55; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 \| dmiProgramBufferRdEn_56; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 \| dmiProgramBufferRdEn_57; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 \| dmiProgramBufferRdEn_58; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 \| dmiProgramBufferRdEn_59; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 \| dmiProgramBufferRdEn_60; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 \| dmiProgramBufferRdEn_61; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 \| dmiProgramBufferRdEn_62; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 \| dmiProgramBufferRdEn_63; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] wire _dmiAbstractDataAccess_T = dmiAbstractDataAccessVec_0 \| dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_1 = _dmiAbstractDataAccess_T \| dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_2 = _dmiAbstractDataAccess_T_1 \| dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_3 = _dmiAbstractDataAccess_T_2 \| dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_4 = _dmiAbstractDataAccess_T_3 \| dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_5 = _dmiAbstractDataAccess_T_4 \| dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_6 = _dmiAbstractDataAccess_T_5 \| dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_7 = _dmiAbstractDataAccess_T_6 \| dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_8 = _dmiAbstractDataAccess_T_7 \| dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_9 = _dmiAbstractDataAccess_T_8 \| dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_10 = _dmiAbstractDataAccess_T_9 \| dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_11 = _dmiAbstractDataAccess_T_10 \| dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_12 = _dmiAbstractDataAccess_T_11 \| dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_13 = _dmiAbstractDataAccess_T_12 \| dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_14 = _dmiAbstractDataAccess_T_13 \| dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_15 = _dmiAbstractDataAccess_T_14 \| dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_16 = _dmiAbstractDataAccess_T_15 \| dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_17 = _dmiAbstractDataAccess_T_16 \| dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_18 = _dmiAbstractDataAccess_T_17 \| dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_19 = _dmiAbstractDataAccess_T_18 \| dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_20 = _dmiAbstractDataAccess_T_19 \| dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_21 = _dmiAbstractDataAccess_T_20 \| dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_22 = _dmiAbstractDataAccess_T_21 \| dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_23 = _dmiAbstractDataAccess_T_22 \| dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_24 = _dmiAbstractDataAccess_T_23 \| dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_25 = _dmiAbstractDataAccess_T_24 \| dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_26 = _dmiAbstractDataAccess_T_25 \| dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_27 = _dmiAbstractDataAccess_T_26 \| dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_28 = _dmiAbstractDataAccess_T_27 \| dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_29 = _dmiAbstractDataAccess_T_28 \| dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45, :1263:68] wire dmiAbstractDataAccess = _dmiAbstractDataAccess_T_29 \| dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45, :1263:68] wire _dmiProgramBufferAccess_T = dmiProgramBufferAccessVec_0 \| dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_1 = _dmiProgramBufferAccess_T \| dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_2 = _dmiProgramBufferAccess_T_1 \| dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_3 = _dmiProgramBufferAccess_T_2 \| dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_4 = _dmiProgramBufferAccess_T_3 \| dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_5 = _dmiProgramBufferAccess_T_4 \| dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_6 = _dmiProgramBufferAccess_T_5 \| dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_7 = _dmiProgramBufferAccess_T_6 \| dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_8 = _dmiProgramBufferAccess_T_7 \| dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_9 = _dmiProgramBufferAccess_T_8 \| dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_10 = _dmiProgramBufferAccess_T_9 \| dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_11 = _dmiProgramBufferAccess_T_10 \| dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_12 = _dmiProgramBufferAccess_T_11 \| dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_13 = _dmiProgramBufferAccess_T_12 \| dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_14 = _dmiProgramBufferAccess_T_13 \| dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_15 = _dmiProgramBufferAccess_T_14 \| dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_16 = _dmiProgramBufferAccess_T_15 \| dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_17 = _dmiProgramBufferAccess_T_16 \| dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_18 = _dmiProgramBufferAccess_T_17 \| dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_19 = _dmiProgramBufferAccess_T_18 \| dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_20 = _dmiProgramBufferAccess_T_19 \| dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_21 = _dmiProgramBufferAccess_T_20 \| dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_22 = _dmiProgramBufferAccess_T_21 \| dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_23 = _dmiProgramBufferAccess_T_22 \| dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_24 = _dmiProgramBufferAccess_T_23 \| dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_25 = _dmiProgramBufferAccess_T_24 \| dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_26 = _dmiProgramBufferAccess_T_25 \| dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_27 = _dmiProgramBufferAccess_T_26 \| dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_28 = _dmiProgramBufferAccess_T_27 \| dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_29 = _dmiProgramBufferAccess_T_28 \| dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_30 = _dmiProgramBufferAccess_T_29 \| dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_31 = _dmiProgramBufferAccess_T_30 \| dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_32 = _dmiProgramBufferAccess_T_31 \| dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_33 = _dmiProgramBufferAccess_T_32 \| dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_34 = _dmiProgramBufferAccess_T_33 \| dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_35 = _dmiProgramBufferAccess_T_34 \| dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_36 = _dmiProgramBufferAccess_T_35 \| dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_37 = _dmiProgramBufferAccess_T_36 \| dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_38 = _dmiProgramBufferAccess_T_37 \| dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_39 = _dmiProgramBufferAccess_T_38 \| dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_40 = _dmiProgramBufferAccess_T_39 \| dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_41 = _dmiProgramBufferAccess_T_40 \| dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_42 = _dmiProgramBufferAccess_T_41 \| dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_43 = _dmiProgramBufferAccess_T_42 \| dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_44 = _dmiProgramBufferAccess_T_43 \| dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_45 = _dmiProgramBufferAccess_T_44 \| dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_46 = _dmiProgramBufferAccess_T_45 \| dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_47 = _dmiProgramBufferAccess_T_46 \| dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_48 = _dmiProgramBufferAccess_T_47 \| dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_49 = _dmiProgramBufferAccess_T_48 \| dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_50 = _dmiProgramBufferAccess_T_49 \| dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_51 = _dmiProgramBufferAccess_T_50 \| dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_52 = _dmiProgramBufferAccess_T_51 \| dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_53 = _dmiProgramBufferAccess_T_52 \| dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_54 = _dmiProgramBufferAccess_T_53 \| dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_55 = _dmiProgramBufferAccess_T_54 \| dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_56 = _dmiProgramBufferAccess_T_55 \| dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_57 = _dmiProgramBufferAccess_T_56 \| dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_58 = _dmiProgramBufferAccess_T_57 \| dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_58 \| dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_60 = _dmiProgramBufferAccess_T_59 \| dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_61 = _dmiProgramBufferAccess_T_60 \| dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46, :1264:69] wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_61 \| dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46, :1264:69] wire _autoexecData_0_T; // @[Debug.scala:1269:140] wire _autoexecData_1_T; // @[Debug.scala:1269:140] wire _autoexecData_2_T; // @[Debug.scala:1269:140] wire _autoexecData_3_T; // @[Debug.scala:1269:140] wire _autoexecData_4_T; // @[Debug.scala:1269:140] wire _autoexecData_5_T; // @[Debug.scala:1269:140] wire _autoexecData_6_T; // @[Debug.scala:1269:140] wire _autoexecData_7_T; // @[Debug.scala:1269:140] wire autoexecData_0; // @[Debug.scala:1267:33] wire autoexecData_1; // @[Debug.scala:1267:33] wire autoexecData_2; // @[Debug.scala:1267:33] wire autoexecData_3; // @[Debug.scala:1267:33] wire autoexecData_4; // @[Debug.scala:1267:33] wire autoexecData_5; // @[Debug.scala:1267:33] wire autoexecData_6; // @[Debug.scala:1267:33] wire autoexecData_7; // @[Debug.scala:1267:33] wire _autoexecProg_0_T; // @[Debug.scala:1270:144] wire _autoexecProg_1_T; // @[Debug.scala:1270:144] wire _autoexecProg_2_T; // @[Debug.scala:1270:144] wire _autoexecProg_3_T; // @[Debug.scala:1270:144] wire _autoexecProg_4_T; // @[Debug.scala:1270:144] wire _autoexecProg_5_T; // @[Debug.scala:1270:144] wire _autoexecProg_6_T; // @[Debug.scala:1270:144] wire _autoexecProg_7_T; // @[Debug.scala:1270:144] wire _autoexecProg_8_T; // @[Debug.scala:1270:144] wire _autoexecProg_9_T; // @[Debug.scala:1270:144] wire _autoexecProg_10_T; // @[Debug.scala:1270:144] wire _autoexecProg_11_T; // @[Debug.scala:1270:144] wire _autoexecProg_12_T; // @[Debug.scala:1270:144] wire _autoexecProg_13_T; // @[Debug.scala:1270:144] wire _autoexecProg_14_T; // @[Debug.scala:1270:144] wire _autoexecProg_15_T; // @[Debug.scala:1270:144] wire autoexecProg_0; // @[Debug.scala:1268:33] wire autoexecProg_1; // @[Debug.scala:1268:33] wire autoexecProg_2; // @[Debug.scala:1268:33] wire autoexecProg_3; // @[Debug.scala:1268:33] wire autoexecProg_4; // @[Debug.scala:1268:33] wire autoexecProg_5; // @[Debug.scala:1268:33] wire autoexecProg_6; // @[Debug.scala:1268:33] wire autoexecProg_7; // @[Debug.scala:1268:33] wire autoexecProg_8; // @[Debug.scala:1268:33] wire autoexecProg_9; // @[Debug.scala:1268:33] wire autoexecProg_10; // @[Debug.scala:1268:33] wire autoexecProg_11; // @[Debug.scala:1268:33] wire autoexecProg_12; // @[Debug.scala:1268:33] wire autoexecProg_13; // @[Debug.scala:1268:33] wire autoexecProg_14; // @[Debug.scala:1268:33] wire autoexecProg_15; // @[Debug.scala:1268:33] assign _autoexecData_0_T = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_0 = _autoexecData_0_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_1_T = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_1 = _autoexecData_1_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_2_T = dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_2 = _autoexecData_2_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_3_T = dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_3 = _autoexecData_3_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_4_T = dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_4 = _autoexecData_4_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_5_T = dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_5 = _autoexecData_5_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_6_T = dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_6 = _autoexecData_6_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_7_T = dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_7 = _autoexecData_7_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecProg_0_T = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_0 = _autoexecProg_0_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_1_T = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_1 = _autoexecProg_1_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_2_T = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_2 = _autoexecProg_2_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_3_T = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_3 = _autoexecProg_3_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_4_T = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_4 = _autoexecProg_4_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_5_T = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_5 = _autoexecProg_5_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_6_T = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_6 = _autoexecProg_6_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_7_T = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_7 = _autoexecProg_7_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_8_T = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_8 = _autoexecProg_8_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_9_T = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_9 = _autoexecProg_9_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_10_T = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_10 = _autoexecProg_10_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_11_T = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_11 = _autoexecProg_11_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_12_T = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_12 = _autoexecProg_12_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_13_T = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_13 = _autoexecProg_13_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_14_T = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_14 = _autoexecProg_14_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_15_T = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_15 = _autoexecProg_15_T; // @[Debug.scala:1268:33, :1270:144] wire _autoexec_T = autoexecData_0 \| autoexecData_1; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_1 = _autoexec_T \| autoexecData_2; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_2 = _autoexec_T_1 \| autoexecData_3; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_3 = _autoexec_T_2 \| autoexecData_4; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_4 = _autoexec_T_3 \| autoexecData_5; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_5 = _autoexec_T_4 \| autoexecData_6; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_6 = _autoexec_T_5 \| autoexecData_7; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_7 = autoexecProg_0 \| autoexecProg_1; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_8 = _autoexec_T_7 \| autoexecProg_2; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_9 = _autoexec_T_8 \| autoexecProg_3; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_10 = _autoexec_T_9 \| autoexecProg_4; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_11 = _autoexec_T_10 \| autoexecProg_5; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_12 = _autoexec_T_11 \| autoexecProg_6; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_13 = _autoexec_T_12 \| autoexecProg_7; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_14 = _autoexec_T_13 \| autoexecProg_8; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_15 = _autoexec_T_14 \| autoexecProg_9; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_16 = _autoexec_T_15 \| autoexecProg_10; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_17 = _autoexec_T_16 \| autoexecProg_11; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_18 = _autoexec_T_17 \| autoexecProg_12; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_19 = _autoexec_T_18 \| autoexecProg_13; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_20 = _autoexec_T_19 \| autoexecProg_14; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_21 = _autoexec_T_20 \| autoexecProg_15; // @[Debug.scala:1268:33, :1272:73] wire autoexec = _autoexec_T_6 \| _autoexec_T_21; // @[Debug.scala:1272:{42,48,73}] reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25] reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25] wire [31:0] COMMANDWrDataVal; // @[Debug.scala:1279:39] wire [31:0] _COMMANDWrData_WIRE_1 = COMMANDWrDataVal; // @[Debug.scala:1279:39, :1280:65] wire [7:0] _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_T; // @[Debug.scala:1280:65] wire [7:0] COMMANDWrData_cmdtype = _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:{39,65}] wire [23:0] COMMANDWrData_control = _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:{39,65}] assign _COMMANDWrData_T = _COMMANDWrData_WIRE_1[23:0]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_control = _COMMANDWrData_T; // @[Debug.scala:1280:65] assign _COMMANDWrData_T_1 = _COMMANDWrData_WIRE_1[31:24]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_cmdtype = _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire out_f_woready_140; // @[RegisterRouter.scala:87:24] wire COMMANDWrEnMaybe; // @[Debug.scala:1281:39] wire _COMMANDWrEnLegal_T; // @[Debug.scala:1743:44] wire COMMANDWrEnLegal; // @[Debug.scala:1282:39] wire out_f_roready_140; // @[RegisterRouter.scala:87:24] wire COMMANDRdEn; // @[Debug.scala:1283:32] wire COMMANDWrEn = COMMANDWrEnMaybe & COMMANDWrEnLegal; // @[Debug.scala:1281:39, :1282:39, :1285:40] reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36] wire [7:0] _out_T_308 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9474 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36] wire [7:0] _out_T_77 = abstractDataMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36] wire [7:0] _out_T_761 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7912 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36] wire [7:0] _out_T_1325 = abstractDataMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36] wire [7:0] _out_T_264 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10874 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36] wire [7:0] _out_T_132 = abstractDataMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36] wire [7:0] _out_T_396 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2207 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36] wire [7:0] _out_T_1413 = abstractDataMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36] wire [7:0] abstractDataNxt_0; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_1; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_2; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_3; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_4; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_5; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_6; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_7; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_8; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_9; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_10; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_11; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_12; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_13; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_14; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_15; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_16; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_17; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_18; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_19; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_20; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_21; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_22; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_23; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_24; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_25; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_26; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_27; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_28; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_29; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_30; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_31; // @[Debug.scala:1301:41] reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34] wire [7:0] _out_T_1128 = programBufferMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10426 = programBufferMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34] wire [7:0] _out_T_860 = programBufferMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34] wire [7:0] _out_T_1172 = programBufferMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6582 = programBufferMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34] wire [7:0] _out_T_220 = programBufferMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34] wire [7:0] _out_T_1556 = programBufferMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3679 = programBufferMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34] wire [7:0] _out_T_662 = programBufferMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34] wire [7:0] _out_T_816 = programBufferMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11898 = programBufferMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34] wire [7:0] _out_T_1369 = programBufferMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34] wire [7:0] _out_T_1501 = programBufferMem_32; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8594 = programBufferMem_32; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34] wire [7:0] _out_T_176 = programBufferMem_36; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34] wire [7:0] _out_T_587 = programBufferMem_40; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5954 = programBufferMem_40; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34] wire [7:0] _out_T_1457 = programBufferMem_44; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34] wire [7:0] _out_T_1281 = programBufferMem_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2943 = programBufferMem_48; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34] wire [7:0] _out_T_904 = programBufferMem_52; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34] wire [7:0] _out_T_706 = programBufferMem_56; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12562 = programBufferMem_56; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34] wire [7:0] _out_T_352 = programBufferMem_60; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34] wire [7:0] programBufferNxt_0; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_1; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_2; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_3; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_4; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_5; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_6; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_7; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_8; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_9; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_10; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_11; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_12; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_13; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_14; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_15; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_16; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_17; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_18; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_19; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_20; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_21; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_22; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_23; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_24; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_25; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_26; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_27; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_28; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_29; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_30; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_31; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_32; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_33; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_34; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_35; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_36; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_37; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_38; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_39; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_40; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_41; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_42; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_43; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_44; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_45; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_46; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_47; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_48; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_49; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_50; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_51; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_52; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_53; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_54; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_55; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_56; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_57; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_58; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_59; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_60; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_61; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_62; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_63; // @[Debug.scala:1307:39] wire _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42] wire _resumeReqRegs_T_1 = resumeReqRegs & _resumeReqRegs_T; // @[Debug.scala:863:31, :1320:{40,42}] wire [1023:0] hartselIndex = 1024'h1 << io_innerCtrl_bits_hartsel_0; // @[OneHot.scala:58:35] wire _haltedBitRegs_T_1 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1327:66] wire [1:0] _haltedBitRegs_T_2 = {1'h0, _haltedBitRegs_T[0] & _haltedBitRegs_T_1}; // @[Debug.scala:1327:{43,64,66}] wire _haltedBitRegs_T_5 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1330:71] wire _haltedBitRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1333:44] wire _haltedBitRegs_T_8 = haltedBitRegs & _haltedBitRegs_T_7; // @[Debug.scala:861:31, :1333:{42,44}] wire _resumeReqRegs_T_4 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1338:71] wire _resumeReqRegs_T_6 = resumeReqRegs \| hamaskWrSel_0; // @[Debug.scala:863:31, :933:31, :1342:43] wire _resumeReqRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1342:67] wire _resumeReqRegs_T_8 = _resumeReqRegs_T_6 & _resumeReqRegs_T_7; // @[Debug.scala:1342:{43,65,67}] wire _resumeAcks_T = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24] wire _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50, :1349:41] wire _resumeAcks_T_2 = _resumeAcks_T & _resumeAcks_T_1; // @[Debug.scala:1349:{24,39,41}] wire _resumeAcks_T_3 = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24, :1351:23] assign resumeAcks = resumereq ? _resumeAcks_T_2 : _resumeAcks_T_3; // @[Debug.scala:869:32, :983:39, :1347:24, :1349:{20,39}, :1351:{20,23}] wire _anyAddressWrEn_T_2; // @[SBA.scala:134:54] wire anyAddressWrEn; // @[SBA.scala:42:34] wire _anyDataRdEn_T_2; // @[SBA.scala:176:51] wire anyDataRdEn; // @[SBA.scala:43:34] wire _anyDataWrEn_T_2; // @[SBA.scala:177:51] wire anyDataWrEn; // @[SBA.scala:44:34] reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28] wire SBCSRdData_sbbusyerror = SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28] wire SBCSRdData_sbreadonaddr = SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :60:38] reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28] wire [2:0] SBCSRdData_sbaccess = SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28] wire SBCSRdData_sbautoincrement = SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28] wire SBCSRdData_sbreadondata = SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :60:38] wire _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:51:67] wire SBCSFieldsRegReset_sbbusy; // @[SBA.scala:49:38] assign _SBCSFieldsRegReset_sbbusy_T = \|_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67] assign SBCSFieldsRegReset_sbbusy = _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:49:38, :51:67] wire sbBusy; // @[SBA.scala:203:46] wire SBCSRdData_sbbusy; // @[SBA.scala:60:38] wire [2:0] SBCSRdData_sberror; // @[SBA.scala:60:38] wire _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_529; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_496; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_485; // @[RegisterRouter.scala:87:24] wire SBCSWrData_sbbusyerror; // @[SBA.scala:63:38] wire SBCSWrData_sbreadonaddr; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sbaccess; // @[SBA.scala:63:38] wire SBCSWrData_sbautoincrement; // @[SBA.scala:63:38] wire SBCSWrData_sbreadondata; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sberror; // @[SBA.scala:63:38] wire out_f_woready_39; // @[RegisterRouter.scala:87:24] wire sberrorWrEn; // @[SBA.scala:65:38] wire out_f_woready_40; // @[RegisterRouter.scala:87:24] wire sbreadondataWrEn; // @[SBA.scala:66:38] wire out_f_woready_41; // @[RegisterRouter.scala:87:24] wire sbautoincrementWrEn; // @[SBA.scala:67:38] wire out_f_woready_42; // @[RegisterRouter.scala:87:24] wire sbaccessWrEn; // @[SBA.scala:68:38] wire out_f_woready_43; // @[RegisterRouter.scala:87:24] wire sbreadonaddrWrEn; // @[SBA.scala:69:38] wire out_f_woready_45; // @[RegisterRouter.scala:87:24] wire sbbusyerrorWrEn; // @[SBA.scala:70:38] reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33] wire [31:0] _out_T_750 = SBADDRESSFieldsReg_0; // @[RegisterRouter.scala:87:24] wire [31:0] SBADDRESSWrData_0; // @[SBA.scala:106:38] wire out_f_roready_63; // @[RegisterRouter.scala:87:24] wire SBADDRESSRdEn_0; // @[SBA.scala:107:38] wire out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _anyAddressWrEn_T = SBADDRESSWrEn_0; // @[SBA.scala:108:38, :134:54] wire [127:0] _autoIncrementedAddr_T_3; // @[SBA.scala:111:60] wire [127:0] autoIncrementedAddr; // @[SBA.scala:110:39] wire [63:0] _GEN_0 = {32'h0, SBADDRESSFieldsReg_0}; // @[SBA.scala:104:33, :111:31] wire [63:0] autoIncrementedAddr_lo; // @[SBA.scala:111:31] assign autoIncrementedAddr_lo = _GEN_0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_lo; // @[SBA.scala:133:10] assign sb2tlOpt_io_addrIn_lo = _GEN_0; // @[SBA.scala:111:31, :133:10] wire [127:0] _autoIncrementedAddr_T = {64'h0, autoIncrementedAddr_lo}; // @[SBA.scala:111:31] wire [7:0] _autoIncrementedAddr_T_1 = 8'h1 << SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :111:67] wire [128:0] _autoIncrementedAddr_T_2 = {1'h0, _autoIncrementedAddr_T} + {121'h0, _autoIncrementedAddr_T_1}; // @[SBA.scala:111:{31,60,67}] assign _autoIncrementedAddr_T_3 = _autoIncrementedAddr_T_2[127:0]; // @[SBA.scala:111:60] assign autoIncrementedAddr = _autoIncrementedAddr_T_3; // @[SBA.scala:110:39, :111:60] wire _GEN_1 = SBCSRdData_sberror == 3'h0; // @[SBA.scala:60:38, :119:40] wire _SBADDRESSFieldsReg_0_T; // @[SBA.scala:119:40] assign _SBADDRESSFieldsReg_0_T = _GEN_1; // @[SBA.scala:119:40] wire _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:118] assign _sb2tlOpt_io_wrEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :199:118] wire _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:118] assign _sb2tlOpt_io_rdEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :200:118] wire _SBADDRESSFieldsReg_0_T_1 = SBADDRESSWrEn_0 & _SBADDRESSFieldsReg_0_T; // @[SBA.scala:108:38, :119:{37,40}] wire _SBADDRESSFieldsReg_0_T_2 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63] wire _SBADDRESSFieldsReg_0_T_3 = _SBADDRESSFieldsReg_0_T_1 & _SBADDRESSFieldsReg_0_T_2; // @[SBA.scala:119:{37,60,63}] wire _SBADDRESSFieldsReg_0_T_4 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88] wire _SBADDRESSFieldsReg_0_T_5 = _SBADDRESSFieldsReg_0_T_3 & _SBADDRESSFieldsReg_0_T_4; // @[SBA.scala:119:{60,85,88}] wire _GEN_2 = _sb2tlOpt_io_rdDone \| _sb2tlOpt_io_wrDone; // @[SBA.scala:120:44] wire _SBADDRESSFieldsReg_0_T_6; // @[SBA.scala:120:44] assign _SBADDRESSFieldsReg_0_T_6 = _GEN_2; // @[SBA.scala:120:44] wire _sbErrorReg_0_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_0_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_1_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_1_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_2_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_2_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _SBADDRESSFieldsReg_0_T_7 = _SBADDRESSFieldsReg_0_T_6 & SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :120:{44,71}] wire [31:0] _SBADDRESSFieldsReg_0_T_8 = autoIncrementedAddr[31:0]; // @[SBA.scala:110:39, :120:124] wire [31:0] _SBADDRESSFieldsReg_0_T_9 = _SBADDRESSFieldsReg_0_T_7 ? _SBADDRESSFieldsReg_0_T_8 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :120:{19,71,124}] wire [31:0] _SBADDRESSFieldsReg_0_T_10 = _SBADDRESSFieldsReg_0_T_5 ? SBADDRESSWrData_0 : _SBADDRESSFieldsReg_0_T_9; // @[SBA.scala:106:38, :119:{19,85}, :120:19] wire [127:0] _sb2tlOpt_io_addrIn_T_1 = {96'h0, SBADDRESSWrData_0}; // @[SBA.scala:106:38, :132:10] wire [127:0] _sb2tlOpt_io_addrIn_T_2 = {64'h0, sb2tlOpt_io_addrIn_lo}; // @[SBA.scala:133:10] wire [127:0] _sb2tlOpt_io_addrIn_T_3 = SBADDRESSWrEn_0 ? _sb2tlOpt_io_addrIn_T_1 : _sb2tlOpt_io_addrIn_T_2; // @[SBA.scala:108:38, :131:34, :132:10, :133:10] wire _anyAddressWrEn_T_1 = _anyAddressWrEn_T; // @[SBA.scala:134:54] assign _anyAddressWrEn_T_2 = _anyAddressWrEn_T_1; // @[SBA.scala:134:54] assign anyAddressWrEn = _anyAddressWrEn_T_2; // @[SBA.scala:42:34, :134:54] reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30] wire [31:0] _SBDATARdData_0_T; // @[SBA.scala:165:31] wire [31:0] _SBDATARdData_1_T; // @[SBA.scala:165:31] wire [31:0] _out_T_805 = SBDATARdData_0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_121 = SBDATARdData_1; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35] wire out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_roready_4; // @[RegisterRouter.scala:87:24] wire SBDATARdEn_0; // @[SBA.scala:149:35] wire SBDATARdEn_1; // @[SBA.scala:149:35] wire out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _sb2tlOpt_io_wrEn_T = SBDATAWrEn_0; // @[SBA.scala:150:35, :199:49] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire SBDATAWrEn_1; // @[SBA.scala:150:35] wire _SBDATAFieldsReg_0_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_0_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_0_T_3 = _SBDATAFieldsReg_0_0_T_1 & _SBDATAFieldsReg_0_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_0_T_5 = _SBDATAFieldsReg_0_0_T_3 & _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_0_T_6 = SBDATAWrData_0[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_0_T_7 = _sb2tlOpt_io_rdLoad_0 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_0_T_8 = _SBDATAFieldsReg_0_0_T_5 ? _SBDATAFieldsReg_0_0_T_6 : _SBDATAFieldsReg_0_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_1_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_1_T_3 = _SBDATAFieldsReg_0_1_T_1 & _SBDATAFieldsReg_0_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_1_T_5 = _SBDATAFieldsReg_0_1_T_3 & _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_1_T_6 = SBDATAWrData_0[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_1_T_7 = _sb2tlOpt_io_rdLoad_1 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_1_T_8 = _SBDATAFieldsReg_0_1_T_5 ? _SBDATAFieldsReg_0_1_T_6 : _SBDATAFieldsReg_0_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_2_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_2_T_3 = _SBDATAFieldsReg_0_2_T_1 & _SBDATAFieldsReg_0_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_2_T_5 = _SBDATAFieldsReg_0_2_T_3 & _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_2_T_6 = SBDATAWrData_0[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_2_T_7 = _sb2tlOpt_io_rdLoad_2 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_2_T_8 = _SBDATAFieldsReg_0_2_T_5 ? _SBDATAFieldsReg_0_2_T_6 : _SBDATAFieldsReg_0_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_3_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_3_T_3 = _SBDATAFieldsReg_0_3_T_1 & _SBDATAFieldsReg_0_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_3_T_5 = _SBDATAFieldsReg_0_3_T_3 & _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_3_T_6 = SBDATAWrData_0[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_3_T_7 = _sb2tlOpt_io_rdLoad_3 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_3_T_8 = _SBDATAFieldsReg_0_3_T_5 ? _SBDATAFieldsReg_0_3_T_6 : _SBDATAFieldsReg_0_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_3 = {SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_lo; // @[SBA.scala:165:31] assign SBDATARdData_0_lo = _GEN_3; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_lo = _GEN_3; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_4 = {SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_hi; // @[SBA.scala:165:31] assign SBDATARdData_0_hi = _GEN_4; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_hi = _GEN_4; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_0_T = {SBDATARdData_0_hi, SBDATARdData_0_lo}; // @[SBA.scala:165:31] assign SBDATARdData_0 = _SBDATARdData_0_T; // @[SBA.scala:145:35, :165:31] wire _SBDATAFieldsReg_1_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_0_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_0_T_3 = _SBDATAFieldsReg_1_0_T_1 & _SBDATAFieldsReg_1_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_0_T_5 = _SBDATAFieldsReg_1_0_T_3 & _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_0_T_6 = SBDATAWrData_1[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_0_T_7 = _sb2tlOpt_io_rdLoad_4 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_0_T_8 = _SBDATAFieldsReg_1_0_T_5 ? _SBDATAFieldsReg_1_0_T_6 : _SBDATAFieldsReg_1_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_1_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_1_T_3 = _SBDATAFieldsReg_1_1_T_1 & _SBDATAFieldsReg_1_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_1_T_5 = _SBDATAFieldsReg_1_1_T_3 & _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_1_T_6 = SBDATAWrData_1[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_1_T_7 = _sb2tlOpt_io_rdLoad_5 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_1_T_8 = _SBDATAFieldsReg_1_1_T_5 ? _SBDATAFieldsReg_1_1_T_6 : _SBDATAFieldsReg_1_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_2_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_2_T_3 = _SBDATAFieldsReg_1_2_T_1 & _SBDATAFieldsReg_1_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_2_T_5 = _SBDATAFieldsReg_1_2_T_3 & _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_2_T_6 = SBDATAWrData_1[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_2_T_7 = _sb2tlOpt_io_rdLoad_6 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_2_T_8 = _SBDATAFieldsReg_1_2_T_5 ? _SBDATAFieldsReg_1_2_T_6 : _SBDATAFieldsReg_1_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_3_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_3_T_3 = _SBDATAFieldsReg_1_3_T_1 & _SBDATAFieldsReg_1_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_3_T_5 = _SBDATAFieldsReg_1_3_T_3 & _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_3_T_6 = SBDATAWrData_1[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_3_T_7 = _sb2tlOpt_io_rdLoad_7 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_3_T_8 = _SBDATAFieldsReg_1_3_T_5 ? _SBDATAFieldsReg_1_3_T_6 : _SBDATAFieldsReg_1_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_5 = {SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_lo; // @[SBA.scala:165:31] assign SBDATARdData_1_lo = _GEN_5; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_lo = _GEN_5; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_6 = {SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_hi; // @[SBA.scala:165:31] assign SBDATARdData_1_hi = _GEN_6; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_hi = _GEN_6; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_1_T = {SBDATARdData_1_hi, SBDATARdData_1_lo}; // @[SBA.scala:165:31] assign SBDATARdData_1 = _SBDATARdData_1_T; // @[SBA.scala:145:35, :165:31] wire [63:0] sb2tlOpt_io_dataIn_lo = {SBDATAWrData_1, SBDATAWrData_0}; // @[SBA.scala:147:35, :175:59] wire [127:0] _sb2tlOpt_io_dataIn_T = {64'h0, sb2tlOpt_io_dataIn_lo}; // @[SBA.scala:175:59] wire [31:0] sb2tlOpt_io_dataIn_lo_lo = {sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo}; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_lo_hi = {sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo}; // @[SBA.scala:175:85] wire [63:0] sb2tlOpt_io_dataIn_lo_1 = {sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo}; // @[SBA.scala:175:85] wire [127:0] _sb2tlOpt_io_dataIn_T_1 = {64'h0, sb2tlOpt_io_dataIn_lo_1}; // @[SBA.scala:175:85] wire _sb2tlOpt_io_wrEn_T_10; // @[SBA.scala:199:156] wire [127:0] _sb2tlOpt_io_dataIn_T_2 = _sb2tlOpt_io_wrEn_T_10 ? _sb2tlOpt_io_dataIn_T : _sb2tlOpt_io_dataIn_T_1; // @[SBA.scala:175:{34,59,85}, :199:156] wire _anyDataRdEn_T = SBDATARdEn_0 \| SBDATARdEn_1; // @[SBA.scala:149:35, :176:51] wire _anyDataRdEn_T_1 = _anyDataRdEn_T; // @[SBA.scala:176:51] assign _anyDataRdEn_T_2 = _anyDataRdEn_T_1; // @[SBA.scala:176:51] assign anyDataRdEn = _anyDataRdEn_T_2; // @[SBA.scala:43:34, :176:51] wire _anyDataWrEn_T = SBDATAWrEn_0 \| SBDATAWrEn_1; // @[SBA.scala:150:35, :177:51] wire _anyDataWrEn_T_1 = _anyDataWrEn_T; // @[SBA.scala:177:51] assign _anyDataWrEn_T_2 = _anyDataWrEn_T_1; // @[SBA.scala:177:51] assign anyDataWrEn = _anyDataWrEn_T_2; // @[SBA.scala:44:34, :177:51] wire _tryRdEn_T = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :108:38, :180:37] wire _tryRdEn_T_1 = SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :149:35, :180:86] wire tryRdEn = _tryRdEn_T \| _tryRdEn_T_1; // @[SBA.scala:180:{37,68,86}] wire _sb2tlOpt_io_rdEn_T = tryRdEn; // @[SBA.scala:180:68, :200:49] wire _sbAccessError_T = SBCSFieldsReg_sbaccess == 3'h0; // @[SBA.scala:47:28, :182:49] wire _T_204 = SBCSFieldsReg_sbaccess == 3'h1; // @[SBA.scala:47:28, :183:49] wire _sbAccessError_T_3; // @[SBA.scala:183:49] assign _sbAccessError_T_3 = _T_204; // @[SBA.scala:183:49] wire _sbAlignmentError_T; // @[SBA.scala:191:52] assign _sbAlignmentError_T = _T_204; // @[SBA.scala:183:49, :191:52] wire _T_211 = SBCSFieldsReg_sbaccess == 3'h2; // @[SBA.scala:47:28, :184:49] wire _sbAccessError_T_7; // @[SBA.scala:184:49] assign _sbAccessError_T_7 = _T_211; // @[SBA.scala:184:49] wire _sbAlignmentError_T_4; // @[SBA.scala:192:52] assign _sbAlignmentError_T_4 = _T_211; // @[SBA.scala:184:49, :192:52] wire _T_218 = SBCSFieldsReg_sbaccess == 3'h3; // @[SBA.scala:47:28, :185:49] wire _sbAccessError_T_11; // @[SBA.scala:185:49] assign _sbAccessError_T_11 = _T_218; // @[SBA.scala:185:49] wire _sbAlignmentError_T_9; // @[SBA.scala:193:52] assign _sbAlignmentError_T_9 = _T_218; // @[SBA.scala:185:49, :193:52] wire _T_225 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49] wire _sbAccessError_T_15; // @[SBA.scala:186:49] assign _sbAccessError_T_15 = _T_225; // @[SBA.scala:186:49] wire _sbAlignmentError_T_14; // @[SBA.scala:194:52] assign _sbAlignmentError_T_14 = _T_225; // @[SBA.scala:186:49, :194:52] wire _sbAccessError_T_17 = _sbAccessError_T_15; // @[SBA.scala:186:{49,58}] wire _sbAccessError_T_18 = _sbAccessError_T_17; // @[SBA.scala:185:97, :186:58] wire _sbAccessError_T_19 = SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:124] wire sbAccessError = _sbAccessError_T_18 \| _sbAccessError_T_19; // @[SBA.scala:185:97, :186:{97,124}] wire [31:0] _compareAddr_T; // @[SBA.scala:189:23] wire [31:0] compareAddr; // @[SBA.scala:188:27] assign _compareAddr_T = SBADDRESSWrEn_0 ? SBADDRESSWrData_0 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :106:38, :108:38, :189:23] assign compareAddr = _compareAddr_T; // @[SBA.scala:188:27, :189:23] wire _sbAlignmentError_T_1 = compareAddr[0]; // @[SBA.scala:188:27, :191:76] wire _sbAlignmentError_T_2 = _sbAlignmentError_T_1; // @[SBA.scala:191:{76,82}] wire _sbAlignmentError_T_3 = _sbAlignmentError_T & _sbAlignmentError_T_2; // @[SBA.scala:191:{52,61,82}] wire [1:0] _sbAlignmentError_T_5 = compareAddr[1:0]; // @[SBA.scala:188:27, :192:76] wire _sbAlignmentError_T_6 = \|_sbAlignmentError_T_5; // @[SBA.scala:192:{76,82}] wire _sbAlignmentError_T_7 = _sbAlignmentError_T_4 & _sbAlignmentError_T_6; // @[SBA.scala:192:{52,61,82}] wire _sbAlignmentError_T_8 = _sbAlignmentError_T_3 \| _sbAlignmentError_T_7; // @[SBA.scala:191:{61,91}, :192:61] wire [2:0] _sbAlignmentError_T_10 = compareAddr[2:0]; // @[SBA.scala:188:27, :193:76] wire _sbAlignmentError_T_11 = \|_sbAlignmentError_T_10; // @[SBA.scala:193:{76,82}] wire _sbAlignmentError_T_12 = _sbAlignmentError_T_9 & _sbAlignmentError_T_11; // @[SBA.scala:193:{52,61,82}] wire _sbAlignmentError_T_13 = _sbAlignmentError_T_8 \| _sbAlignmentError_T_12; // @[SBA.scala:191:91, :192:91, :193:61] wire [3:0] _sbAlignmentError_T_15 = compareAddr[3:0]; // @[SBA.scala:188:27, :194:76] wire _sbAlignmentError_T_16 = \|_sbAlignmentError_T_15; // @[SBA.scala:194:{76,82}] wire _sbAlignmentError_T_17 = _sbAlignmentError_T_14 & _sbAlignmentError_T_16; // @[SBA.scala:194:{52,61,82}] wire sbAlignmentError = _sbAlignmentError_T_13 \| _sbAlignmentError_T_17; // @[SBA.scala:192:91, :193:91, :194:61] wire _sb2tlOpt_io_wrEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :199:63] wire _sb2tlOpt_io_wrEn_T_2 = _sb2tlOpt_io_wrEn_T & _sb2tlOpt_io_wrEn_T_1; // @[SBA.scala:199:{49,60,63}] wire _sb2tlOpt_io_wrEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :199:88] wire _sb2tlOpt_io_wrEn_T_4 = _sb2tlOpt_io_wrEn_T_2 & _sb2tlOpt_io_wrEn_T_3; // @[SBA.scala:199:{60,85,88}] wire _sb2tlOpt_io_wrEn_T_6 = _sb2tlOpt_io_wrEn_T_4 & _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:{85,115,118}] wire _sb2tlOpt_io_wrEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141] wire _sb2tlOpt_io_wrEn_T_8 = _sb2tlOpt_io_wrEn_T_6 & _sb2tlOpt_io_wrEn_T_7; // @[SBA.scala:199:{115,138,141}] wire _sb2tlOpt_io_wrEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159] assign _sb2tlOpt_io_wrEn_T_10 = _sb2tlOpt_io_wrEn_T_8 & _sb2tlOpt_io_wrEn_T_9; // @[SBA.scala:199:{138,156,159}] wire _sb2tlOpt_io_rdEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :200:63] wire _sb2tlOpt_io_rdEn_T_2 = _sb2tlOpt_io_rdEn_T & _sb2tlOpt_io_rdEn_T_1; // @[SBA.scala:200:{49,60,63}] wire _sb2tlOpt_io_rdEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :200:88] wire _sb2tlOpt_io_rdEn_T_4 = _sb2tlOpt_io_rdEn_T_2 & _sb2tlOpt_io_rdEn_T_3; // @[SBA.scala:200:{60,85,88}] wire _sb2tlOpt_io_rdEn_T_6 = _sb2tlOpt_io_rdEn_T_4 & _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:{85,115,118}] wire _sb2tlOpt_io_rdEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141, :200:141] wire _sb2tlOpt_io_rdEn_T_8 = _sb2tlOpt_io_rdEn_T_6 & _sb2tlOpt_io_rdEn_T_7; // @[SBA.scala:200:{115,138,141}] wire _sb2tlOpt_io_rdEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159, :200:159] wire _sb2tlOpt_io_rdEn_T_10 = _sb2tlOpt_io_rdEn_T_8 & _sb2tlOpt_io_rdEn_T_9; // @[SBA.scala:200:{138,156,159}] assign sbBusy = \|_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67, :203:46] assign SBCSRdData_sbbusy = sbBusy; // @[SBA.scala:60:38, :203:46] wire _SBCSFieldsReg_sbbusyerror_T = sbbusyerrorWrEn & SBCSWrData_sbbusyerror; // @[SBA.scala:63:38, :70:38, :208:60] wire _SBCSFieldsReg_sbbusyerror_T_1 = anyAddressWrEn & sbBusy; // @[SBA.scala:42:34, :203:46, :209:59] wire _SBCSFieldsReg_sbbusyerror_T_2 = anyDataRdEn \| anyDataWrEn; // @[SBA.scala:43:34, :44:34, :210:57] wire _SBCSFieldsReg_sbbusyerror_T_3 = _SBCSFieldsReg_sbbusyerror_T_2 & sbBusy; // @[SBA.scala:203:46, :210:{57,73}] wire _SBCSFieldsReg_sbbusyerror_T_4 = _SBCSFieldsReg_sbbusyerror_T_3 \| SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :210:{43,73}] wire _SBCSFieldsReg_sbbusyerror_T_5 = _SBCSFieldsReg_sbbusyerror_T_1 \| _SBCSFieldsReg_sbbusyerror_T_4; // @[SBA.scala:209:{43,59}, :210:43] wire _SBCSFieldsReg_sbbusyerror_T_6 = ~_SBCSFieldsReg_sbbusyerror_T & _SBCSFieldsReg_sbbusyerror_T_5; // @[SBA.scala:208:{43,60}, :209:43] wire _SBCSFieldsReg_sbreadonaddr_T = sbreadonaddrWrEn ? SBCSWrData_sbreadonaddr : SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :63:38, :69:38, :211:43] wire _SBCSFieldsReg_sbautoincrement_T = sbautoincrementWrEn ? SBCSWrData_sbautoincrement : SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :63:38, :67:38, :212:43] wire _SBCSFieldsReg_sbreadondata_T = sbreadondataWrEn ? SBCSWrData_sbreadondata : SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :63:38, :66:38, :213:43] wire [2:0] _SBCSFieldsReg_sbaccess_T = sbaccessWrEn ? SBCSWrData_sbaccess : SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :63:38, :68:38, :214:43] reg sbErrorReg_0; // @[SBA.scala:219:25] reg sbErrorReg_1; // @[SBA.scala:219:25] reg sbErrorReg_2; // @[SBA.scala:219:25] wire _sbErrorReg_0_T = SBCSWrData_sberror[0]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_0_T_1 = _sbErrorReg_0_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_0_T_2 = sberrorWrEn & _sbErrorReg_0_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_0_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_0_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_0_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_0_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_0_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_0_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_0_T_7 = _sbErrorReg_0_T_4 \| _sbErrorReg_0_T_6; // @[SBA.scala:226:{52,81,106}] wire _GEN_7 = SBDATAWrEn_0 \| tryRdEn; // @[SBA.scala:150:35, :180:68, :227:39] wire _sbErrorReg_0_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_0_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_0_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_0_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_1_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_1_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_1_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_1_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_2_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_2_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_2_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_2_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_0_T_9 = _sbErrorReg_0_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_0_T_11 = _sbErrorReg_0_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_0_T_13 = _sbErrorReg_0_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_0_T_14 = _sbErrorReg_0_T_13 \| sbErrorReg_0; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_0_T_15 = ~_sbErrorReg_0_T_11 & _sbErrorReg_0_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_0_T_16 = _sbErrorReg_0_T_9 \| _sbErrorReg_0_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_0_T_17 = ~_sbErrorReg_0_T_7 & _sbErrorReg_0_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_0_T_18 = ~_sbErrorReg_0_T_2 & _sbErrorReg_0_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_1_T = SBCSWrData_sberror[1]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_1_T_1 = _sbErrorReg_1_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_1_T_2 = sberrorWrEn & _sbErrorReg_1_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_1_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_1_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_1_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_1_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_1_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_1_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_1_T_7 = _sbErrorReg_1_T_4 \| _sbErrorReg_1_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_1_T_9 = _sbErrorReg_1_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_1_T_11 = _sbErrorReg_1_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_1_T_13 = _sbErrorReg_1_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_1_T_14 = _sbErrorReg_1_T_13 \| sbErrorReg_1; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_1_T_15 = ~_sbErrorReg_1_T_11 & _sbErrorReg_1_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_1_T_16 = _sbErrorReg_1_T_9 \| _sbErrorReg_1_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_1_T_17 = _sbErrorReg_1_T_7 \| _sbErrorReg_1_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_1_T_18 = ~_sbErrorReg_1_T_2 & _sbErrorReg_1_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_2_T = SBCSWrData_sberror[2]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_2_T_1 = _sbErrorReg_2_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_2_T_2 = sberrorWrEn & _sbErrorReg_2_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_2_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_2_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_2_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_2_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_2_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_2_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_2_T_7 = _sbErrorReg_2_T_4 \| _sbErrorReg_2_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_2_T_9 = _sbErrorReg_2_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_2_T_11 = _sbErrorReg_2_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_2_T_13 = _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_2_T_14 = _sbErrorReg_2_T_13 \| sbErrorReg_2; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_2_T_15 = _sbErrorReg_2_T_11 \| _sbErrorReg_2_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_2_T_16 = ~_sbErrorReg_2_T_9 & _sbErrorReg_2_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_2_T_17 = ~_sbErrorReg_2_T_7 & _sbErrorReg_2_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_2_T_18 = ~_sbErrorReg_2_T_2 & _sbErrorReg_2_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire [1:0] SBCSRdData_sberror_lo = {sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:42] wire [1:0] SBCSRdData_sberror_hi = {1'h0, sbErrorReg_2}; // @[SBA.scala:219:25, :240:42] wire [3:0] _SBCSRdData_sberror_T = {SBCSRdData_sberror_hi, SBCSRdData_sberror_lo}; // @[SBA.scala:240:42] assign SBCSRdData_sberror = _SBCSRdData_sberror_T[2:0]; // @[SBA.scala:60:38, :240:{28,42}] wire [31:0] _T_237 = {COMMANDReg_cmdtype, COMMANDReg_control}; // @[Debug.scala:1277:25, :1435:40] wire [31:0] _out_T_1545; // @[RegisterRouter.scala:87:24] assign _out_T_1545 = _T_237; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] wire [31:0] _accessRegisterCommandReg_T; // @[Debug.scala:1533:56] assign _accessRegisterCommandReg_T = _T_237; // @[Debug.scala:1435:40, :1533:56] assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [3:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = dmiNodeIn_a_bits_address[8:2]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_112 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_741 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_796 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_939 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1536 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1591 = out_front_bits_data; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [6:0] _GEN_8 = out_front_bits_index & 7'h40; // @[RegisterRouter.scala:87:24] wire [6:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN_8; // @[RegisterRouter.scala:87:24] wire [6:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN_8; // @[RegisterRouter.scala:87:24] wire _GEN_9 = out_findex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_14; // @[RegisterRouter.scala:87:24] assign _out_T_14 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_16; // @[RegisterRouter.scala:87:24] assign _out_T_16 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_18; // @[RegisterRouter.scala:87:24] assign _out_T_18 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_20; // @[RegisterRouter.scala:87:24] assign _out_T_20 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_22; // @[RegisterRouter.scala:87:24] assign _out_T_22 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_24; // @[RegisterRouter.scala:87:24] assign _out_T_24 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_T_26 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_28; // @[RegisterRouter.scala:87:24] assign _out_T_28 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_30; // @[RegisterRouter.scala:87:24] assign _out_T_30 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_32; // @[RegisterRouter.scala:87:24] assign _out_T_32 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_34; // @[RegisterRouter.scala:87:24] assign _out_T_34 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_36; // @[RegisterRouter.scala:87:24] assign _out_T_36 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_38; // @[RegisterRouter.scala:87:24] assign _out_T_38 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_42; // @[RegisterRouter.scala:87:24] assign _out_T_42 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_44; // @[RegisterRouter.scala:87:24] assign _out_T_44 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_46; // @[RegisterRouter.scala:87:24] assign _out_T_46 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_48; // @[RegisterRouter.scala:87:24] assign _out_T_48 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_50; // @[RegisterRouter.scala:87:24] assign _out_T_50 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_52; // @[RegisterRouter.scala:87:24] assign _out_T_52 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_54; // @[RegisterRouter.scala:87:24] assign _out_T_54 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_56; // @[RegisterRouter.scala:87:24] assign _out_T_56 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_58; // @[RegisterRouter.scala:87:24] assign _out_T_58 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_60; // @[RegisterRouter.scala:87:24] assign _out_T_60 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_62; // @[RegisterRouter.scala:87:24] assign _out_T_62 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_64; // @[RegisterRouter.scala:87:24] assign _out_T_64 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_66; // @[RegisterRouter.scala:87:24] assign _out_T_66 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _GEN_10 = out_bindex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_15; // @[RegisterRouter.scala:87:24] assign _out_T_15 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_17; // @[RegisterRouter.scala:87:24] assign _out_T_17 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_19; // @[RegisterRouter.scala:87:24] assign _out_T_19 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_21; // @[RegisterRouter.scala:87:24] assign _out_T_21 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_23; // @[RegisterRouter.scala:87:24] assign _out_T_23 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_25; // @[RegisterRouter.scala:87:24] assign _out_T_25 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_27; // @[RegisterRouter.scala:87:24] assign _out_T_27 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_29; // @[RegisterRouter.scala:87:24] assign _out_T_29 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_31; // @[RegisterRouter.scala:87:24] assign _out_T_31 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_33; // @[RegisterRouter.scala:87:24] assign _out_T_33 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_35; // @[RegisterRouter.scala:87:24] assign _out_T_35 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_37; // @[RegisterRouter.scala:87:24] assign _out_T_37 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_39; // @[RegisterRouter.scala:87:24] assign _out_T_39 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_43; // @[RegisterRouter.scala:87:24] assign _out_T_43 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_45; // @[RegisterRouter.scala:87:24] assign _out_T_45 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_47; // @[RegisterRouter.scala:87:24] assign _out_T_47 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_49; // @[RegisterRouter.scala:87:24] assign _out_T_49 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_51; // @[RegisterRouter.scala:87:24] assign _out_T_51 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_53; // @[RegisterRouter.scala:87:24] assign _out_T_53 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_55; // @[RegisterRouter.scala:87:24] assign _out_T_55 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_57; // @[RegisterRouter.scala:87:24] assign _out_T_57 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_59; // @[RegisterRouter.scala:87:24] assign _out_T_59 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_61; // @[RegisterRouter.scala:87:24] assign _out_T_61 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_63; // @[RegisterRouter.scala:87:24] assign _out_T_63 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_65; // @[RegisterRouter.scala:87:24] assign _out_T_65 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_67; // @[RegisterRouter.scala:87:24] assign _out_T_67 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_5 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_61 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_9 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_41 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_35 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_8 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_47 = _out_T_15; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_10 = _out_T_17; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_56 = _out_T_19; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_42 = _out_T_21; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_24 = _out_T_23; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_37 = _out_T_25; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_46 = _out_T_27; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_57 = _out_T_29; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_6 = _out_T_31; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_60 = _out_T_33; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_38 = _out_T_35; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_33 = _out_T_37; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_45 = _out_T_39; // @[MuxLiteral.scala:49:48] wire _out_T_40 = out_findex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_bindex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_41; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_17 = _out_T_43; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_32 = _out_T_45; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_34 = _out_T_47; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_22 = _out_T_49; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_44 = _out_T_51; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_7 = _out_T_53; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_39 = _out_T_55; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_11 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_43 = _out_T_59; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_40 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_23 = _out_T_63; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_36 = _out_T_65; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_19 = _out_T_67; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_145; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_145; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire out_roready_18; // @[RegisterRouter.scala:87:24] wire out_roready_19; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_21; // @[RegisterRouter.scala:87:24] wire out_roready_22; // @[RegisterRouter.scala:87:24] wire out_roready_23; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire out_roready_25; // @[RegisterRouter.scala:87:24] wire out_roready_26; // @[RegisterRouter.scala:87:24] wire out_roready_27; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_29; // @[RegisterRouter.scala:87:24] wire out_roready_30; // @[RegisterRouter.scala:87:24] wire out_roready_31; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_33; // @[RegisterRouter.scala:87:24] wire out_roready_34; // @[RegisterRouter.scala:87:24] wire out_roready_35; // @[RegisterRouter.scala:87:24] wire out_roready_36; // @[RegisterRouter.scala:87:24] wire out_roready_37; // @[RegisterRouter.scala:87:24] wire out_roready_38; // @[RegisterRouter.scala:87:24] wire out_roready_39; // @[RegisterRouter.scala:87:24] wire out_roready_40; // @[RegisterRouter.scala:87:24] wire out_roready_41; // @[RegisterRouter.scala:87:24] wire out_roready_42; // @[RegisterRouter.scala:87:24] wire out_roready_43; // @[RegisterRouter.scala:87:24] wire out_roready_44; // @[RegisterRouter.scala:87:24] wire out_roready_45; // @[RegisterRouter.scala:87:24] wire out_roready_46; // @[RegisterRouter.scala:87:24] wire out_roready_47; // @[RegisterRouter.scala:87:24] wire out_roready_48; // @[RegisterRouter.scala:87:24] wire out_roready_49; // @[RegisterRouter.scala:87:24] wire out_roready_50; // @[RegisterRouter.scala:87:24] wire out_roready_51; // @[RegisterRouter.scala:87:24] wire out_roready_52; // @[RegisterRouter.scala:87:24] wire out_roready_53; // @[RegisterRouter.scala:87:24] wire out_roready_54; // @[RegisterRouter.scala:87:24] wire out_roready_55; // @[RegisterRouter.scala:87:24] wire out_roready_56; // @[RegisterRouter.scala:87:24] wire out_roready_57; // @[RegisterRouter.scala:87:24] wire out_roready_58; // @[RegisterRouter.scala:87:24] wire out_roready_59; // @[RegisterRouter.scala:87:24] wire out_roready_60; // @[RegisterRouter.scala:87:24] wire out_roready_61; // @[RegisterRouter.scala:87:24] wire out_roready_62; // @[RegisterRouter.scala:87:24] wire out_roready_63; // @[RegisterRouter.scala:87:24] wire out_roready_64; // @[RegisterRouter.scala:87:24] wire out_roready_65; // @[RegisterRouter.scala:87:24] wire out_roready_66; // @[RegisterRouter.scala:87:24] wire out_roready_67; // @[RegisterRouter.scala:87:24] wire out_roready_68; // @[RegisterRouter.scala:87:24] wire out_roready_69; // @[RegisterRouter.scala:87:24] wire out_roready_70; // @[RegisterRouter.scala:87:24] wire out_roready_71; // @[RegisterRouter.scala:87:24] wire out_roready_72; // @[RegisterRouter.scala:87:24] wire out_roready_73; // @[RegisterRouter.scala:87:24] wire out_roready_74; // @[RegisterRouter.scala:87:24] wire out_roready_75; // @[RegisterRouter.scala:87:24] wire out_roready_76; // @[RegisterRouter.scala:87:24] wire out_roready_77; // @[RegisterRouter.scala:87:24] wire out_roready_78; // @[RegisterRouter.scala:87:24] wire out_roready_79; // @[RegisterRouter.scala:87:24] wire out_roready_80; // @[RegisterRouter.scala:87:24] wire out_roready_81; // @[RegisterRouter.scala:87:24] wire out_roready_82; // @[RegisterRouter.scala:87:24] wire out_roready_83; // @[RegisterRouter.scala:87:24] wire out_roready_84; // @[RegisterRouter.scala:87:24] wire out_roready_85; // @[RegisterRouter.scala:87:24] wire out_roready_86; // @[RegisterRouter.scala:87:24] wire out_roready_87; // @[RegisterRouter.scala:87:24] wire out_roready_88; // @[RegisterRouter.scala:87:24] wire out_roready_89; // @[RegisterRouter.scala:87:24] wire out_roready_90; // @[RegisterRouter.scala:87:24] wire out_roready_91; // @[RegisterRouter.scala:87:24] wire out_roready_92; // @[RegisterRouter.scala:87:24] wire out_roready_93; // @[RegisterRouter.scala:87:24] wire out_roready_94; // @[RegisterRouter.scala:87:24] wire out_roready_95; // @[RegisterRouter.scala:87:24] wire out_roready_96; // @[RegisterRouter.scala:87:24] wire out_roready_97; // @[RegisterRouter.scala:87:24] wire out_roready_98; // @[RegisterRouter.scala:87:24] wire out_roready_99; // @[RegisterRouter.scala:87:24] wire out_roready_100; // @[RegisterRouter.scala:87:24] wire out_roready_101; // @[RegisterRouter.scala:87:24] wire out_roready_102; // @[RegisterRouter.scala:87:24] wire out_roready_103; // @[RegisterRouter.scala:87:24] wire out_roready_104; // @[RegisterRouter.scala:87:24] wire out_roready_105; // @[RegisterRouter.scala:87:24] wire out_roready_106; // @[RegisterRouter.scala:87:24] wire out_roready_107; // @[RegisterRouter.scala:87:24] wire out_roready_108; // @[RegisterRouter.scala:87:24] wire out_roready_109; // @[RegisterRouter.scala:87:24] wire out_roready_110; // @[RegisterRouter.scala:87:24] wire out_roready_111; // @[RegisterRouter.scala:87:24] wire out_roready_112; // @[RegisterRouter.scala:87:24] wire out_roready_113; // @[RegisterRouter.scala:87:24] wire out_roready_114; // @[RegisterRouter.scala:87:24] wire out_roready_115; // @[RegisterRouter.scala:87:24] wire out_roready_116; // @[RegisterRouter.scala:87:24] wire out_roready_117; // @[RegisterRouter.scala:87:24] wire out_roready_118; // @[RegisterRouter.scala:87:24] wire out_roready_119; // @[RegisterRouter.scala:87:24] wire out_roready_120; // @[RegisterRouter.scala:87:24] wire out_roready_121; // @[RegisterRouter.scala:87:24] wire out_roready_122; // @[RegisterRouter.scala:87:24] wire out_roready_123; // @[RegisterRouter.scala:87:24] wire out_roready_124; // @[RegisterRouter.scala:87:24] wire out_roready_125; // @[RegisterRouter.scala:87:24] wire out_roready_126; // @[RegisterRouter.scala:87:24] wire out_roready_127; // @[RegisterRouter.scala:87:24] wire out_roready_128; // @[RegisterRouter.scala:87:24] wire out_roready_129; // @[RegisterRouter.scala:87:24] wire out_roready_130; // @[RegisterRouter.scala:87:24] wire out_roready_131; // @[RegisterRouter.scala:87:24] wire out_roready_132; // @[RegisterRouter.scala:87:24] wire out_roready_133; // @[RegisterRouter.scala:87:24] wire out_roready_134; // @[RegisterRouter.scala:87:24] wire out_roready_135; // @[RegisterRouter.scala:87:24] wire out_roready_136; // @[RegisterRouter.scala:87:24] wire out_roready_137; // @[RegisterRouter.scala:87:24] wire out_roready_138; // @[RegisterRouter.scala:87:24] wire out_roready_139; // @[RegisterRouter.scala:87:24] wire out_roready_140; // @[RegisterRouter.scala:87:24] wire out_roready_141; // @[RegisterRouter.scala:87:24] wire out_roready_142; // @[RegisterRouter.scala:87:24] wire out_roready_143; // @[RegisterRouter.scala:87:24] wire out_roready_144; // @[RegisterRouter.scala:87:24] wire out_roready_145; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire out_woready_18; // @[RegisterRouter.scala:87:24] wire out_woready_19; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_21; // @[RegisterRouter.scala:87:24] wire out_woready_22; // @[RegisterRouter.scala:87:24] wire out_woready_23; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire out_woready_25; // @[RegisterRouter.scala:87:24] wire out_woready_26; // @[RegisterRouter.scala:87:24] wire out_woready_27; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_29; // @[RegisterRouter.scala:87:24] wire out_woready_30; // @[RegisterRouter.scala:87:24] wire out_woready_31; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_33; // @[RegisterRouter.scala:87:24] wire out_woready_34; // @[RegisterRouter.scala:87:24] wire out_woready_35; // @[RegisterRouter.scala:87:24] wire out_woready_36; // @[RegisterRouter.scala:87:24] wire out_woready_37; // @[RegisterRouter.scala:87:24] wire out_woready_38; // @[RegisterRouter.scala:87:24] wire out_woready_39; // @[RegisterRouter.scala:87:24] wire out_woready_40; // @[RegisterRouter.scala:87:24] wire out_woready_41; // @[RegisterRouter.scala:87:24] wire out_woready_42; // @[RegisterRouter.scala:87:24] wire out_woready_43; // @[RegisterRouter.scala:87:24] wire out_woready_44; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_46; // @[RegisterRouter.scala:87:24] wire out_woready_47; // @[RegisterRouter.scala:87:24] wire out_woready_48; // @[RegisterRouter.scala:87:24] wire out_woready_49; // @[RegisterRouter.scala:87:24] wire out_woready_50; // @[RegisterRouter.scala:87:24] wire out_woready_51; // @[RegisterRouter.scala:87:24] wire out_woready_52; // @[RegisterRouter.scala:87:24] wire out_woready_53; // @[RegisterRouter.scala:87:24] wire out_woready_54; // @[RegisterRouter.scala:87:24] wire out_woready_55; // @[RegisterRouter.scala:87:24] wire out_woready_56; // @[RegisterRouter.scala:87:24] wire out_woready_57; // @[RegisterRouter.scala:87:24] wire out_woready_58; // @[RegisterRouter.scala:87:24] wire out_woready_59; // @[RegisterRouter.scala:87:24] wire out_woready_60; // @[RegisterRouter.scala:87:24] wire out_woready_61; // @[RegisterRouter.scala:87:24] wire out_woready_62; // @[RegisterRouter.scala:87:24] wire out_woready_63; // @[RegisterRouter.scala:87:24] wire out_woready_64; // @[RegisterRouter.scala:87:24] wire out_woready_65; // @[RegisterRouter.scala:87:24] wire out_woready_66; // @[RegisterRouter.scala:87:24] wire out_woready_67; // @[RegisterRouter.scala:87:24] wire out_woready_68; // @[RegisterRouter.scala:87:24] wire out_woready_69; // @[RegisterRouter.scala:87:24] wire out_woready_70; // @[RegisterRouter.scala:87:24] wire out_woready_71; // @[RegisterRouter.scala:87:24] wire out_woready_72; // @[RegisterRouter.scala:87:24] wire out_woready_73; // @[RegisterRouter.scala:87:24] wire out_woready_74; // @[RegisterRouter.scala:87:24] wire out_woready_75; // @[RegisterRouter.scala:87:24] wire out_woready_76; // @[RegisterRouter.scala:87:24] wire out_woready_77; // @[RegisterRouter.scala:87:24] wire out_woready_78; // @[RegisterRouter.scala:87:24] wire out_woready_79; // @[RegisterRouter.scala:87:24] wire out_woready_80; // @[RegisterRouter.scala:87:24] wire out_woready_81; // @[RegisterRouter.scala:87:24] wire out_woready_82; // @[RegisterRouter.scala:87:24] wire out_woready_83; // @[RegisterRouter.scala:87:24] wire out_woready_84; // @[RegisterRouter.scala:87:24] wire out_woready_85; // @[RegisterRouter.scala:87:24] wire out_woready_86; // @[RegisterRouter.scala:87:24] wire out_woready_87; // @[RegisterRouter.scala:87:24] wire out_woready_88; // @[RegisterRouter.scala:87:24] wire out_woready_89; // @[RegisterRouter.scala:87:24] wire out_woready_90; // @[RegisterRouter.scala:87:24] wire out_woready_91; // @[RegisterRouter.scala:87:24] wire out_woready_92; // @[RegisterRouter.scala:87:24] wire out_woready_93; // @[RegisterRouter.scala:87:24] wire out_woready_94; // @[RegisterRouter.scala:87:24] wire out_woready_95; // @[RegisterRouter.scala:87:24] wire out_woready_96; // @[RegisterRouter.scala:87:24] wire out_woready_97; // @[RegisterRouter.scala:87:24] wire out_woready_98; // @[RegisterRouter.scala:87:24] wire out_woready_99; // @[RegisterRouter.scala:87:24] wire out_woready_100; // @[RegisterRouter.scala:87:24] wire out_woready_101; // @[RegisterRouter.scala:87:24] wire out_woready_102; // @[RegisterRouter.scala:87:24] wire out_woready_103; // @[RegisterRouter.scala:87:24] wire out_woready_104; // @[RegisterRouter.scala:87:24] wire out_woready_105; // @[RegisterRouter.scala:87:24] wire out_woready_106; // @[RegisterRouter.scala:87:24] wire out_woready_107; // @[RegisterRouter.scala:87:24] wire out_woready_108; // @[RegisterRouter.scala:87:24] wire out_woready_109; // @[RegisterRouter.scala:87:24] wire out_woready_110; // @[RegisterRouter.scala:87:24] wire out_woready_111; // @[RegisterRouter.scala:87:24] wire out_woready_112; // @[RegisterRouter.scala:87:24] wire out_woready_113; // @[RegisterRouter.scala:87:24] wire out_woready_114; // @[RegisterRouter.scala:87:24] wire out_woready_115; // @[RegisterRouter.scala:87:24] wire out_woready_116; // @[RegisterRouter.scala:87:24] wire out_woready_117; // @[RegisterRouter.scala:87:24] wire out_woready_118; // @[RegisterRouter.scala:87:24] wire out_woready_119; // @[RegisterRouter.scala:87:24] wire out_woready_120; // @[RegisterRouter.scala:87:24] wire out_woready_121; // @[RegisterRouter.scala:87:24] wire out_woready_122; // @[RegisterRouter.scala:87:24] wire out_woready_123; // @[RegisterRouter.scala:87:24] wire out_woready_124; // @[RegisterRouter.scala:87:24] wire out_woready_125; // @[RegisterRouter.scala:87:24] wire out_woready_126; // @[RegisterRouter.scala:87:24] wire out_woready_127; // @[RegisterRouter.scala:87:24] wire out_woready_128; // @[RegisterRouter.scala:87:24] wire out_woready_129; // @[RegisterRouter.scala:87:24] wire out_woready_130; // @[RegisterRouter.scala:87:24] wire out_woready_131; // @[RegisterRouter.scala:87:24] wire out_woready_132; // @[RegisterRouter.scala:87:24] wire out_woready_133; // @[RegisterRouter.scala:87:24] wire out_woready_134; // @[RegisterRouter.scala:87:24] wire out_woready_135; // @[RegisterRouter.scala:87:24] wire out_woready_136; // @[RegisterRouter.scala:87:24] wire out_woready_137; // @[RegisterRouter.scala:87:24] wire out_woready_138; // @[RegisterRouter.scala:87:24] wire out_woready_139; // @[RegisterRouter.scala:87:24] wire out_woready_140; // @[RegisterRouter.scala:87:24] wire out_woready_141; // @[RegisterRouter.scala:87:24] wire out_woready_142; // @[RegisterRouter.scala:87:24] wire out_woready_143; // @[RegisterRouter.scala:87:24] wire out_woready_144; // @[RegisterRouter.scala:87:24] wire out_woready_145; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_4 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_5 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_6 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_7 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo = {_out_frontMask_T_5, _out_frontMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi = {_out_frontMask_T_7, _out_frontMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_4 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_5 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_6 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_7 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo = {_out_backMask_T_5, _out_backMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi = {_out_backMask_T_7, _out_backMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_69 = out_f_rivalid; // @[RegisterRouter.scala:87:24] assign out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_4 = out_f_roready; // @[RegisterRouter.scala:87:24] wire _out_T_70 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_wivalid; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_4 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_68 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_123 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_167 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_211 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_255 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_299 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_343 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_387 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_578 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_622 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_653 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_697 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_752 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_807 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_851 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_895 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1119 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1163 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1272 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1316 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1360 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1404 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1448 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1492 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1547 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_4 = out_f_woready ? _out_T_68 : abstractDataMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_74 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_78 = _out_T_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_78; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_80 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_5 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire _out_T_81 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_5 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_79 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_134 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_178 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_222 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_266 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_310 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_354 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_398 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_589 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_633 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_664 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_708 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_763 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_818 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_862 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_906 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1130 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1174 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1283 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1327 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1371 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1415 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1459 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1503 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1558 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_5 = out_f_woready_1 ? _out_T_79 : abstractDataMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {abstractDataMem_5, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_88 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_89; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_91 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_6 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire _out_T_92 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_6 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_90 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_145 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_189 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_233 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_277 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_321 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_365 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_409 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_600 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_675 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_719 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_774 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_829 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_873 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_917 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1141 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1185 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1294 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1338 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1382 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1426 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1470 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1514 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1569 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_6 = out_f_woready_2 ? _out_T_90 : abstractDataMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_95 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_96 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {abstractDataMem_6, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_99 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_100 = _out_T_99; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_100; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_102 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_7 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire _out_T_103 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_7 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_101 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_156 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_200 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_244 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_288 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_332 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_376 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_420 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_611 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_686 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_730 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_785 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_840 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_884 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_928 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1152 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1196 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1305 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1349 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1393 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1437 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1481 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1525 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1580 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_7 = out_f_woready_3 ? _out_T_101 : abstractDataMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {abstractDataMem_7, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_5 = _out_T_111; // @[MuxLiteral.scala:49:48] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_1 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_1 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_woready_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_1 = out_f_woready_4 ? _out_T_112 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_117 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_118 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_122 = _out_T_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_61 = _out_T_122; // @[MuxLiteral.scala:49:48] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_124 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_20 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire _out_T_125 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_20 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_woready_5; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_20 = out_f_woready_5 ? _out_T_123 : abstractDataMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_128 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_129 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_133 = _out_T_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_3 = _out_T_133; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_135 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_21 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_136 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_21 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_woready_6; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_21 = out_f_woready_6 ? _out_T_134 : abstractDataMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_139 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_140 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_3 = {abstractDataMem_21, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_143 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_144 = _out_T_143; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_4 = _out_T_144; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_146 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_22 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire _out_T_147 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_22 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_woready_7; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_22 = out_f_woready_7 ? _out_T_145 : abstractDataMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_150 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_4 = {abstractDataMem_22, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_154 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_155 = _out_T_154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_5 = _out_T_155; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_157 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_23 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_23 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_woready_8; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_23 = out_f_woready_8 ? _out_T_156 : abstractDataMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_161 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_5 = {abstractDataMem_23, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_165 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_166 = _out_T_165; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_9 = _out_T_166; // @[MuxLiteral.scala:49:48] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_168 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_36 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_169 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_36 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_woready_9; // @[RegisterRouter.scala:87:24] assign programBufferNxt_36 = out_f_woready_9 ? _out_T_167 : programBufferMem_36; // @[RegisterRouter.scala:87:24] wire _out_T_172 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_173 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_177 = _out_T_176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_6 = _out_T_177; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_179 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_37 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_180 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_37 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign programBufferNxt_37 = out_f_woready_10 ? _out_T_178 : programBufferMem_37; // @[RegisterRouter.scala:87:24] wire _out_T_183 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_184 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_6 = {programBufferMem_37, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_187 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_188 = _out_T_187; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_7 = _out_T_188; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_190 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_38 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire _out_T_191 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_38 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign programBufferNxt_38 = out_f_woready_11 ? _out_T_189 : programBufferMem_38; // @[RegisterRouter.scala:87:24] wire _out_T_194 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_195 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_7 = {programBufferMem_38, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_198 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_199 = _out_T_198; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_8 = _out_T_199; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = \|_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = \|_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_201 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_39 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire _out_T_202 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_203 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_39 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_204 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign programBufferNxt_39 = out_f_woready_12 ? _out_T_200 : programBufferMem_39; // @[RegisterRouter.scala:87:24] wire _out_T_205 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_206 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_207 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_208 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_8 = {programBufferMem_39, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_209 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_210 = _out_T_209; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_41 = _out_T_210; // @[MuxLiteral.scala:49:48] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_212 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_12 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_213 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_214 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_12 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_215 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign programBufferNxt_12 = out_f_woready_13 ? _out_T_211 : programBufferMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_216 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_217 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_218 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_219 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_221 = _out_T_220; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_9 = _out_T_221; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = \|_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = \|_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_223 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_13 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire _out_T_224 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_225 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_13 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_226 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign programBufferNxt_13 = out_f_woready_14 ? _out_T_222 : programBufferMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_227 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_228 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_229 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_230 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_9 = {programBufferMem_13, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_231 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_232 = _out_T_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_10 = _out_T_232; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_234 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_14 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire _out_T_235 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_236 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_14 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_237 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign programBufferNxt_14 = out_f_woready_15 ? _out_T_233 : programBufferMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_238 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_239 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_240 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_241 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_10 = {programBufferMem_14, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_242 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_243 = _out_T_242; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_11 = _out_T_243; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_245 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_15 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire _out_T_246 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_247 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_15 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_248 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign programBufferNxt_15 = out_f_woready_16 ? _out_T_244 : programBufferMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_249 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_250 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_251 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_252 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_11 = {programBufferMem_15, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_253 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_254 = _out_T_253; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_35 = _out_T_254; // @[MuxLiteral.scala:49:48] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_256 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_16 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire _out_T_257 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_258 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_16 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_259 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_16 = out_f_woready_17 ? _out_T_255 : abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_260 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_261 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_262 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_263 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_265 = _out_T_264; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_12 = _out_T_265; // @[RegisterRouter.scala:87:24] wire out_rimask_18 = \|_out_rimask_T_18; // @[RegisterRouter.scala:87:24] wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24] wire out_romask_18 = \|_out_romask_T_18; // @[RegisterRouter.scala:87:24] wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_267 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_17 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire _out_T_268 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_269 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_17 = out_f_woready_18; // @[RegisterRouter.scala:87:24] wire _out_T_270 = out_f_woready_18; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_17 = out_f_woready_18 ? _out_T_266 : abstractDataMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_271 = ~out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_272 = ~out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_273 = ~out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_274 = ~out_womask_18; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_12 = {abstractDataMem_17, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_275 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_276 = _out_T_275; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_13 = _out_T_276; // @[RegisterRouter.scala:87:24] wire out_rimask_19 = \|_out_rimask_T_19; // @[RegisterRouter.scala:87:24] wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24] wire out_romask_19 = \|_out_romask_T_19; // @[RegisterRouter.scala:87:24] wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_278 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_18 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire _out_T_279 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_280 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_18 = out_f_woready_19; // @[RegisterRouter.scala:87:24] wire _out_T_281 = out_f_woready_19; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_18 = out_f_woready_19 ? _out_T_277 : abstractDataMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_282 = ~out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_283 = ~out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_284 = ~out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_285 = ~out_womask_19; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_13 = {abstractDataMem_18, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_286 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_287 = _out_T_286; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_14 = _out_T_287; // @[RegisterRouter.scala:87:24] wire out_rimask_20 = \|_out_rimask_T_20; // @[RegisterRouter.scala:87:24] wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24] wire out_romask_20 = \|_out_romask_T_20; // @[RegisterRouter.scala:87:24] wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_289 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_19 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire _out_T_290 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_291 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_19 = out_f_woready_20; // @[RegisterRouter.scala:87:24] wire _out_T_292 = out_f_woready_20; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_19 = out_f_woready_20 ? _out_T_288 : abstractDataMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_293 = ~out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_294 = ~out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_295 = ~out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_296 = ~out_womask_20; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_14 = {abstractDataMem_19, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_297 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_298 = _out_T_297; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_8 = _out_T_298; // @[MuxLiteral.scala:49:48] wire out_rimask_21 = \|_out_rimask_T_21; // @[RegisterRouter.scala:87:24] wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24] wire out_romask_21 = \|_out_romask_T_21; // @[RegisterRouter.scala:87:24] wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_300 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_0 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire _out_T_301 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_302 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_0 = out_f_woready_21; // @[RegisterRouter.scala:87:24] wire _out_T_303 = out_f_woready_21; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_0 = out_f_woready_21 ? _out_T_299 : abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_304 = ~out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_305 = ~out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_306 = ~out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_307 = ~out_womask_21; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_309 = _out_T_308; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_15 = _out_T_309; // @[RegisterRouter.scala:87:24] wire out_rimask_22 = \|_out_rimask_T_22; // @[RegisterRouter.scala:87:24] wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24] wire out_romask_22 = \|_out_romask_T_22; // @[RegisterRouter.scala:87:24] wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_311 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_1 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire _out_T_312 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_313 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_1 = out_f_woready_22; // @[RegisterRouter.scala:87:24] wire _out_T_314 = out_f_woready_22; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_1 = out_f_woready_22 ? _out_T_310 : abstractDataMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_315 = ~out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_316 = ~out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_317 = ~out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_318 = ~out_womask_22; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_15 = {abstractDataMem_1, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_319 = out_prepend_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_320 = _out_T_319; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_16 = _out_T_320; // @[RegisterRouter.scala:87:24] wire out_rimask_23 = \|_out_rimask_T_23; // @[RegisterRouter.scala:87:24] wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24] wire out_romask_23 = \|_out_romask_T_23; // @[RegisterRouter.scala:87:24] wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_322 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_2 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire _out_T_323 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_324 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_2 = out_f_woready_23; // @[RegisterRouter.scala:87:24] wire _out_T_325 = out_f_woready_23; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_2 = out_f_woready_23 ? _out_T_321 : abstractDataMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_326 = ~out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_327 = ~out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_328 = ~out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_329 = ~out_womask_23; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_16 = {abstractDataMem_2, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_330 = out_prepend_16; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_331 = _out_T_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_17 = _out_T_331; // @[RegisterRouter.scala:87:24] wire out_rimask_24 = \|_out_rimask_T_24; // @[RegisterRouter.scala:87:24] wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24] wire out_romask_24 = \|_out_romask_T_24; // @[RegisterRouter.scala:87:24] wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_333 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_3 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire _out_T_334 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_335 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_3 = out_f_woready_24; // @[RegisterRouter.scala:87:24] wire _out_T_336 = out_f_woready_24; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_3 = out_f_woready_24 ? _out_T_332 : abstractDataMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_337 = ~out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_338 = ~out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_339 = ~out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_340 = ~out_womask_24; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_17 = {abstractDataMem_3, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_341 = out_prepend_17; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_342 = _out_T_341; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_4 = _out_T_342; // @[MuxLiteral.scala:49:48] wire out_rimask_25 = \|_out_rimask_T_25; // @[RegisterRouter.scala:87:24] wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24] wire out_romask_25 = \|_out_romask_T_25; // @[RegisterRouter.scala:87:24] wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_344 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_60 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire _out_T_345 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_346 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_60 = out_f_woready_25; // @[RegisterRouter.scala:87:24] wire _out_T_347 = out_f_woready_25; // @[RegisterRouter.scala:87:24] assign programBufferNxt_60 = out_f_woready_25 ? _out_T_343 : programBufferMem_60; // @[RegisterRouter.scala:87:24] wire _out_T_348 = ~out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_349 = ~out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_350 = ~out_romask_25; // @[RegisterRouter.scala:87:24] wire _out_T_351 = ~out_womask_25; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_353 = _out_T_352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_18 = _out_T_353; // @[RegisterRouter.scala:87:24] wire out_rimask_26 = \|_out_rimask_T_26; // @[RegisterRouter.scala:87:24] wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24] wire out_romask_26 = \|_out_romask_T_26; // @[RegisterRouter.scala:87:24] wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_355 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_61 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire _out_T_356 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_357 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_61 = out_f_woready_26; // @[RegisterRouter.scala:87:24] wire _out_T_358 = out_f_woready_26; // @[RegisterRouter.scala:87:24] assign programBufferNxt_61 = out_f_woready_26 ? _out_T_354 : programBufferMem_61; // @[RegisterRouter.scala:87:24] wire _out_T_359 = ~out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_360 = ~out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_361 = ~out_romask_26; // @[RegisterRouter.scala:87:24] wire _out_T_362 = ~out_womask_26; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_18 = {programBufferMem_61, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_363 = out_prepend_18; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_364 = _out_T_363; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_19 = _out_T_364; // @[RegisterRouter.scala:87:24] wire out_rimask_27 = \|_out_rimask_T_27; // @[RegisterRouter.scala:87:24] wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24] wire out_romask_27 = \|_out_romask_T_27; // @[RegisterRouter.scala:87:24] wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_366 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_62 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire _out_T_367 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_368 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_62 = out_f_woready_27; // @[RegisterRouter.scala:87:24] wire _out_T_369 = out_f_woready_27; // @[RegisterRouter.scala:87:24] assign programBufferNxt_62 = out_f_woready_27 ? _out_T_365 : programBufferMem_62; // @[RegisterRouter.scala:87:24] wire _out_T_370 = ~out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_371 = ~out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_372 = ~out_romask_27; // @[RegisterRouter.scala:87:24] wire _out_T_373 = ~out_womask_27; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_19 = {programBufferMem_62, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_374 = out_prepend_19; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_375 = _out_T_374; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_20 = _out_T_375; // @[RegisterRouter.scala:87:24] wire out_rimask_28 = \|_out_rimask_T_28; // @[RegisterRouter.scala:87:24] wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24] wire out_romask_28 = \|_out_romask_T_28; // @[RegisterRouter.scala:87:24] wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_377 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_63 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire _out_T_378 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_379 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_63 = out_f_woready_28; // @[RegisterRouter.scala:87:24] wire _out_T_380 = out_f_woready_28; // @[RegisterRouter.scala:87:24] assign programBufferNxt_63 = out_f_woready_28 ? _out_T_376 : programBufferMem_63; // @[RegisterRouter.scala:87:24] wire _out_T_381 = ~out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_382 = ~out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_383 = ~out_romask_28; // @[RegisterRouter.scala:87:24] wire _out_T_384 = ~out_womask_28; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_20 = {programBufferMem_63, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_385 = out_prepend_20; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_386 = _out_T_385; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_47 = _out_T_386; // @[MuxLiteral.scala:49:48] wire out_rimask_29 = \|_out_rimask_T_29; // @[RegisterRouter.scala:87:24] wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24] wire out_romask_29 = \|_out_romask_T_29; // @[RegisterRouter.scala:87:24] wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_388 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_24 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire _out_T_389 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_390 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_24 = out_f_woready_29; // @[RegisterRouter.scala:87:24] wire _out_T_391 = out_f_woready_29; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_24 = out_f_woready_29 ? _out_T_387 : abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_392 = ~out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_393 = ~out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_394 = ~out_romask_29; // @[RegisterRouter.scala:87:24] wire _out_T_395 = ~out_womask_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_397 = _out_T_396; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_21 = _out_T_397; // @[RegisterRouter.scala:87:24] wire out_rimask_30 = \|_out_rimask_T_30; // @[RegisterRouter.scala:87:24] wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24] wire out_romask_30 = \|_out_romask_T_30; // @[RegisterRouter.scala:87:24] wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_399 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_25 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire _out_T_400 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_401 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_25 = out_f_woready_30; // @[RegisterRouter.scala:87:24] wire _out_T_402 = out_f_woready_30; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_25 = out_f_woready_30 ? _out_T_398 : abstractDataMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_403 = ~out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_404 = ~out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_405 = ~out_romask_30; // @[RegisterRouter.scala:87:24] wire _out_T_406 = ~out_womask_30; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_21 = {abstractDataMem_25, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_407 = out_prepend_21; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_408 = _out_T_407; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_22 = _out_T_408; // @[RegisterRouter.scala:87:24] wire out_rimask_31 = \|_out_rimask_T_31; // @[RegisterRouter.scala:87:24] wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24] wire out_romask_31 = \|_out_romask_T_31; // @[RegisterRouter.scala:87:24] wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_410 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_26 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire _out_T_411 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_412 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_26 = out_f_woready_31; // @[RegisterRouter.scala:87:24] wire _out_T_413 = out_f_woready_31; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_26 = out_f_woready_31 ? _out_T_409 : abstractDataMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_414 = ~out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_415 = ~out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_416 = ~out_romask_31; // @[RegisterRouter.scala:87:24] wire _out_T_417 = ~out_womask_31; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_22 = {abstractDataMem_26, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_418 = out_prepend_22; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_419 = _out_T_418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_23 = _out_T_419; // @[RegisterRouter.scala:87:24] wire out_rimask_32 = \|_out_rimask_T_32; // @[RegisterRouter.scala:87:24] wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24] wire out_romask_32 = \|_out_romask_T_32; // @[RegisterRouter.scala:87:24] wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_421 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_27 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire _out_T_422 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_423 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_27 = out_f_woready_32; // @[RegisterRouter.scala:87:24] wire _out_T_424 = out_f_woready_32; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_27 = out_f_woready_32 ? _out_T_420 : abstractDataMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_425 = ~out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_426 = ~out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_427 = ~out_romask_32; // @[RegisterRouter.scala:87:24] wire _out_T_428 = ~out_womask_32; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_23 = {abstractDataMem_27, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_429 = out_prepend_23; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_430 = _out_T_429; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_10 = _out_T_430; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_33 = _out_rimask_T_33; // @[RegisterRouter.scala:87:24] wire out_wimask_33 = _out_wimask_T_33; // @[RegisterRouter.scala:87:24] wire _out_romask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_33 = _out_romask_T_33; // @[RegisterRouter.scala:87:24] wire out_womask_33 = _out_womask_T_33; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_432 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_433 = out_f_roready_33; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24] wire out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_T_431 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_434 = ~out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_435 = ~out_wimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_436 = ~out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_437 = ~out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_34 = _out_rimask_T_34; // @[RegisterRouter.scala:87:24] wire out_wimask_34 = _out_wimask_T_34; // @[RegisterRouter.scala:87:24] wire _out_romask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_34 = _out_romask_T_34; // @[RegisterRouter.scala:87:24] wire out_womask_34 = _out_womask_T_34; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_441 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_442 = out_f_roready_34; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24] wire out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_T_440 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_443 = ~out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_444 = ~out_wimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_445 = ~out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_446 = ~out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire out_rimask_35 = _out_rimask_T_35; // @[RegisterRouter.scala:87:24] wire out_wimask_35 = _out_wimask_T_35; // @[RegisterRouter.scala:87:24] wire _out_romask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire out_romask_35 = _out_romask_T_35; // @[RegisterRouter.scala:87:24] wire out_womask_35 = _out_womask_T_35; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_450 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_451 = out_f_roready_35; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24] wire out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_T_449 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24] wire _out_T_452 = ~out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_453 = ~out_wimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_454 = ~out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_455 = ~out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire out_rimask_36 = _out_rimask_T_36; // @[RegisterRouter.scala:87:24] wire out_wimask_36 = _out_wimask_T_36; // @[RegisterRouter.scala:87:24] wire _out_romask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire out_romask_36 = _out_romask_T_36; // @[RegisterRouter.scala:87:24] wire out_womask_36 = _out_womask_T_36; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_459 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_460 = out_f_roready_36; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24] wire out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_T_458 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_T_461 = ~out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_462 = ~out_wimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_463 = ~out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_464 = ~out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire out_rimask_37 = _out_rimask_T_37; // @[RegisterRouter.scala:87:24] wire out_wimask_37 = _out_wimask_T_37; // @[RegisterRouter.scala:87:24] wire _out_romask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire out_romask_37 = _out_romask_T_37; // @[RegisterRouter.scala:87:24] wire out_womask_37 = _out_womask_T_37; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_468 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_469 = out_f_roready_37; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24] wire out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24] wire _out_T_467 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_957 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_470 = ~out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_471 = ~out_wimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_472 = ~out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_473 = ~out_womask_37; // @[RegisterRouter.scala:87:24] wire [6:0] _out_rimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_wimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_rimask_38 = \|_out_rimask_T_38; // @[RegisterRouter.scala:87:24] wire out_wimask_38 = &_out_wimask_T_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_romask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_womask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_romask_38 = \|_out_romask_T_38; // @[RegisterRouter.scala:87:24] wire out_womask_38 = &_out_womask_T_38; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_477 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_478 = out_f_roready_38; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24] wire out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_476 = out_front_bits_data[11:5]; // @[RegisterRouter.scala:87:24] wire _out_T_479 = ~out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_480 = ~out_wimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_481 = ~out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_482 = ~out_womask_38; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_rimask_39 = \|_out_rimask_T_39; // @[RegisterRouter.scala:87:24] wire out_wimask_39 = &_out_wimask_T_39; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_romask_39 = \|_out_romask_T_39; // @[RegisterRouter.scala:87:24] wire out_womask_39 = &_out_womask_T_39; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_486 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_487 = out_f_roready_39; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_488 = out_f_wivalid_39; // @[RegisterRouter.scala:87:24] assign out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24] assign sberrorWrEn = out_f_woready_39; // @[RegisterRouter.scala:87:24] wire _out_T_489 = out_f_woready_39; // @[RegisterRouter.scala:87:24] assign _out_T_485 = out_front_bits_data[14:12]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sberror = _out_T_485; // @[RegisterRouter.scala:87:24] wire _out_T_490 = ~out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_491 = ~out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_492 = ~out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_493 = ~out_womask_39; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_29 = {SBCSRdData_sberror, 12'h40F}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_494 = out_prepend_29; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_495 = _out_T_494; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_30 = _out_T_495; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire out_rimask_40 = _out_rimask_T_40; // @[RegisterRouter.scala:87:24] wire out_wimask_40 = _out_wimask_T_40; // @[RegisterRouter.scala:87:24] wire _out_romask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire out_romask_40 = _out_romask_T_40; // @[RegisterRouter.scala:87:24] wire out_womask_40 = _out_womask_T_40; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_497 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_498 = out_f_roready_40; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_499 = out_f_wivalid_40; // @[RegisterRouter.scala:87:24] assign out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24] assign sbreadondataWrEn = out_f_woready_40; // @[RegisterRouter.scala:87:24] wire _out_T_500 = out_f_woready_40; // @[RegisterRouter.scala:87:24] assign _out_T_496 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] wire _out_T_1056 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadondata = _out_T_496; // @[RegisterRouter.scala:87:24] wire _out_T_501 = ~out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_502 = ~out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_503 = ~out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_504 = ~out_womask_40; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_30 = {SBCSRdData_sbreadondata, _out_prepend_T_30}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_505 = out_prepend_30; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_506 = _out_T_505; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_31 = _out_T_506; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire out_rimask_41 = _out_rimask_T_41; // @[RegisterRouter.scala:87:24] wire out_wimask_41 = _out_wimask_T_41; // @[RegisterRouter.scala:87:24] wire _out_romask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire out_romask_41 = _out_romask_T_41; // @[RegisterRouter.scala:87:24] wire out_womask_41 = _out_womask_T_41; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_508 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_509 = out_f_roready_41; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_510 = out_f_wivalid_41; // @[RegisterRouter.scala:87:24] assign out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24] assign sbautoincrementWrEn = out_f_woready_41; // @[RegisterRouter.scala:87:24] wire _out_T_511 = out_f_woready_41; // @[RegisterRouter.scala:87:24] assign _out_T_507 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] wire _out_T_1065 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbautoincrement = _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_512 = ~out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_513 = ~out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_514 = ~out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_515 = ~out_womask_41; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_31 = {SBCSRdData_sbautoincrement, _out_prepend_T_31}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_516 = out_prepend_31; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_517 = _out_T_516; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_32 = _out_T_517; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_rimask_42 = \|_out_rimask_T_42; // @[RegisterRouter.scala:87:24] wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_romask_42 = \|_out_romask_T_42; // @[RegisterRouter.scala:87:24] wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_519 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_520 = out_f_roready_42; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_521 = out_f_wivalid_42; // @[RegisterRouter.scala:87:24] assign out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24] assign sbaccessWrEn = out_f_woready_42; // @[RegisterRouter.scala:87:24] wire _out_T_522 = out_f_woready_42; // @[RegisterRouter.scala:87:24] assign _out_T_518 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbaccess = _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_523 = ~out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_524 = ~out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_525 = ~out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_526 = ~out_womask_42; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_32 = {SBCSRdData_sbaccess, _out_prepend_T_32}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_527 = out_prepend_32; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_528 = _out_T_527; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_33 = _out_T_528; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire out_rimask_43 = _out_rimask_T_43; // @[RegisterRouter.scala:87:24] wire out_wimask_43 = _out_wimask_T_43; // @[RegisterRouter.scala:87:24] wire _out_romask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire out_romask_43 = _out_romask_T_43; // @[RegisterRouter.scala:87:24] wire out_womask_43 = _out_womask_T_43; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_530 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_531 = out_f_roready_43; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_532 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24] assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24] assign sbreadonaddrWrEn = out_f_woready_43; // @[RegisterRouter.scala:87:24] wire _out_T_533 = out_f_woready_43; // @[RegisterRouter.scala:87:24] assign _out_T_529 = out_front_bits_data[20]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadonaddr = _out_T_529; // @[RegisterRouter.scala:87:24] wire _out_T_534 = ~out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_535 = ~out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_536 = ~out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_537 = ~out_womask_43; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_33 = {SBCSRdData_sbreadonaddr, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_538 = out_prepend_33; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_539 = _out_T_538; // @[RegisterRouter.scala:87:24] wire [20:0] _out_prepend_T_34 = _out_T_539; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire out_rimask_44 = _out_rimask_T_44; // @[RegisterRouter.scala:87:24] wire out_wimask_44 = _out_wimask_T_44; // @[RegisterRouter.scala:87:24] wire _out_romask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire out_romask_44 = _out_romask_T_44; // @[RegisterRouter.scala:87:24] wire out_womask_44 = _out_womask_T_44; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_541 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_542 = out_f_roready_44; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24] wire out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24] wire _out_T_540 = out_front_bits_data[21]; // @[RegisterRouter.scala:87:24] wire _out_T_543 = ~out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_544 = ~out_wimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_545 = ~out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_546 = ~out_womask_44; // @[RegisterRouter.scala:87:24] wire [21:0] out_prepend_34 = {SBCSRdData_sbbusy, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_547 = out_prepend_34; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_548 = _out_T_547; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_35 = _out_T_548; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire out_rimask_45 = _out_rimask_T_45; // @[RegisterRouter.scala:87:24] wire out_wimask_45 = _out_wimask_T_45; // @[RegisterRouter.scala:87:24] wire _out_romask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire out_romask_45 = _out_romask_T_45; // @[RegisterRouter.scala:87:24] wire out_womask_45 = _out_womask_T_45; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_550 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_551 = out_f_roready_45; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_552 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24] assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24] assign sbbusyerrorWrEn = out_f_woready_45; // @[RegisterRouter.scala:87:24] wire _out_T_553 = out_f_woready_45; // @[RegisterRouter.scala:87:24] assign _out_T_549 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] wire _out_T_1110 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbbusyerror = _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_554 = ~out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_555 = ~out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_556 = ~out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_557 = ~out_womask_45; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_35 = {SBCSRdData_sbbusyerror, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_558 = out_prepend_35; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_559 = _out_T_558; // @[RegisterRouter.scala:87:24] wire [22:0] _out_prepend_T_36 = _out_T_559; // @[RegisterRouter.scala:87:24] wire [5:0] _out_rimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_wimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_rimask_46 = \|_out_rimask_T_46; // @[RegisterRouter.scala:87:24] wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_romask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_womask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_romask_46 = \|_out_romask_T_46; // @[RegisterRouter.scala:87:24] wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_561 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_562 = out_f_roready_46; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24] wire out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_560 = out_front_bits_data[28:23]; // @[RegisterRouter.scala:87:24] wire _out_T_563 = ~out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_564 = ~out_wimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_565 = ~out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_566 = ~out_womask_46; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_36 = {1'h0, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_567 = {5'h0, out_prepend_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_568 = _out_T_567; // @[RegisterRouter.scala:87:24] wire [28:0] _out_prepend_T_37 = _out_T_568; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_rimask_47 = \|_out_rimask_T_47; // @[RegisterRouter.scala:87:24] wire out_wimask_47 = &_out_wimask_T_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_romask_47 = \|_out_romask_T_47; // @[RegisterRouter.scala:87:24] wire out_womask_47 = &_out_womask_T_47; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_570 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_571 = out_f_roready_47; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24] wire out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_569 = out_front_bits_data[31:29]; // @[RegisterRouter.scala:87:24] wire _out_T_572 = ~out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_573 = ~out_wimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_574 = ~out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_575 = ~out_womask_47; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_37 = {3'h1, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_576 = out_prepend_37; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_577 = _out_T_576; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_56 = _out_T_577; // @[MuxLiteral.scala:49:48] wire out_rimask_48 = \|_out_rimask_T_48; // @[RegisterRouter.scala:87:24] wire out_wimask_48 = &_out_wimask_T_48; // @[RegisterRouter.scala:87:24] wire out_romask_48 = \|_out_romask_T_48; // @[RegisterRouter.scala:87:24] wire out_womask_48 = &_out_womask_T_48; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_48 = out_rivalid_48 & out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_579 = out_f_rivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_roready_48 = out_roready_48 & out_romask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_40 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire _out_T_580 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_48 = out_wivalid_48 & out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_581 = out_f_wivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_woready_48 = out_woready_48 & out_womask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_40 = out_f_woready_48; // @[RegisterRouter.scala:87:24] wire _out_T_582 = out_f_woready_48; // @[RegisterRouter.scala:87:24] assign programBufferNxt_40 = out_f_woready_48 ? _out_T_578 : programBufferMem_40; // @[RegisterRouter.scala:87:24] wire _out_T_583 = ~out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_584 = ~out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_585 = ~out_romask_48; // @[RegisterRouter.scala:87:24] wire _out_T_586 = ~out_womask_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_588 = _out_T_587; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_38 = _out_T_588; // @[RegisterRouter.scala:87:24] wire out_rimask_49 = \|_out_rimask_T_49; // @[RegisterRouter.scala:87:24] wire out_wimask_49 = &_out_wimask_T_49; // @[RegisterRouter.scala:87:24] wire out_romask_49 = \|_out_romask_T_49; // @[RegisterRouter.scala:87:24] wire out_womask_49 = &_out_womask_T_49; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_49 = out_rivalid_49 & out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_590 = out_f_rivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_roready_49 = out_roready_49 & out_romask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_41 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire _out_T_591 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_49 = out_wivalid_49 & out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_592 = out_f_wivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_woready_49 = out_woready_49 & out_womask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_41 = out_f_woready_49; // @[RegisterRouter.scala:87:24] wire _out_T_593 = out_f_woready_49; // @[RegisterRouter.scala:87:24] assign programBufferNxt_41 = out_f_woready_49 ? _out_T_589 : programBufferMem_41; // @[RegisterRouter.scala:87:24] wire _out_T_594 = ~out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_595 = ~out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_596 = ~out_romask_49; // @[RegisterRouter.scala:87:24] wire _out_T_597 = ~out_womask_49; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_38 = {programBufferMem_41, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_598 = out_prepend_38; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_599 = _out_T_598; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_39 = _out_T_599; // @[RegisterRouter.scala:87:24] wire out_rimask_50 = \|_out_rimask_T_50; // @[RegisterRouter.scala:87:24] wire out_wimask_50 = &_out_wimask_T_50; // @[RegisterRouter.scala:87:24] wire out_romask_50 = \|_out_romask_T_50; // @[RegisterRouter.scala:87:24] wire out_womask_50 = &_out_womask_T_50; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_50 = out_rivalid_50 & out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_601 = out_f_rivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_roready_50 = out_roready_50 & out_romask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_42 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire _out_T_602 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_50 = out_wivalid_50 & out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_603 = out_f_wivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_woready_50 = out_woready_50 & out_womask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_42 = out_f_woready_50; // @[RegisterRouter.scala:87:24] wire _out_T_604 = out_f_woready_50; // @[RegisterRouter.scala:87:24] assign programBufferNxt_42 = out_f_woready_50 ? _out_T_600 : programBufferMem_42; // @[RegisterRouter.scala:87:24] wire _out_T_605 = ~out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_606 = ~out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_607 = ~out_romask_50; // @[RegisterRouter.scala:87:24] wire _out_T_608 = ~out_womask_50; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_39 = {programBufferMem_42, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_609 = out_prepend_39; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_610 = _out_T_609; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_40 = _out_T_610; // @[RegisterRouter.scala:87:24] wire out_rimask_51 = \|_out_rimask_T_51; // @[RegisterRouter.scala:87:24] wire out_wimask_51 = &_out_wimask_T_51; // @[RegisterRouter.scala:87:24] wire out_romask_51 = \|_out_romask_T_51; // @[RegisterRouter.scala:87:24] wire out_womask_51 = &_out_womask_T_51; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_51 = out_rivalid_51 & out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_612 = out_f_rivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_roready_51 = out_roready_51 & out_romask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_43 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire _out_T_613 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_51 = out_wivalid_51 & out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_614 = out_f_wivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_woready_51 = out_woready_51 & out_womask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_43 = out_f_woready_51; // @[RegisterRouter.scala:87:24] wire _out_T_615 = out_f_woready_51; // @[RegisterRouter.scala:87:24] assign programBufferNxt_43 = out_f_woready_51 ? _out_T_611 : programBufferMem_43; // @[RegisterRouter.scala:87:24] wire _out_T_616 = ~out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_617 = ~out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_618 = ~out_romask_51; // @[RegisterRouter.scala:87:24] wire _out_T_619 = ~out_womask_51; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_40 = {programBufferMem_43, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_620 = out_prepend_40; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_621 = _out_T_620; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_42 = _out_T_621; // @[MuxLiteral.scala:49:48] wire out_rimask_52 = \|_out_rimask_T_52; // @[RegisterRouter.scala:87:24] wire out_wimask_52 = &_out_wimask_T_52; // @[RegisterRouter.scala:87:24] wire out_romask_52 = \|_out_romask_T_52; // @[RegisterRouter.scala:87:24] wire out_womask_52 = &_out_womask_T_52; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_52 = out_rivalid_52 & out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_623 = out_f_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_f_roready_52 = out_roready_52 & out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_624 = out_f_roready_52; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_52 = out_wivalid_52 & out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_625 = out_f_wivalid_52; // @[RegisterRouter.scala:87:24] assign out_f_woready_52 = out_woready_52 & out_womask_52; // @[RegisterRouter.scala:87:24] assign autoexecdataWrEnMaybe = out_f_woready_52; // @[RegisterRouter.scala:87:24] wire _out_T_626 = out_f_woready_52; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecdata = {4'h0, _out_T_622}; // @[RegisterRouter.scala:87:24] wire _out_T_627 = ~out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_628 = ~out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_629 = ~out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_630 = ~out_womask_52; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_632 = _out_T_631[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_41 = _out_T_632; // @[RegisterRouter.scala:87:24] wire out_rimask_53 = \|_out_rimask_T_53; // @[RegisterRouter.scala:87:24] wire out_wimask_53 = &_out_wimask_T_53; // @[RegisterRouter.scala:87:24] wire out_romask_53 = \|_out_romask_T_53; // @[RegisterRouter.scala:87:24] wire out_womask_53 = &_out_womask_T_53; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_53 = out_rivalid_53 & out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_634 = out_f_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_f_roready_53 = out_roready_53 & out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_635 = out_f_roready_53; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_53 = out_wivalid_53 & out_wimask_53; // @[RegisterRouter.scala:87:24] wire out_f_woready_53 = out_woready_53 & out_womask_53; // @[RegisterRouter.scala:87:24] wire _out_T_636 = ~out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_637 = ~out_wimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_638 = ~out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_639 = ~out_womask_53; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_41 = {1'h0, _out_prepend_T_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_640 = {7'h0, out_prepend_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_641 = _out_T_640; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_42 = _out_T_641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_54 = \|_out_rimask_T_54; // @[RegisterRouter.scala:87:24] wire out_wimask_54 = &_out_wimask_T_54; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_romask_54 = \|_out_romask_T_54; // @[RegisterRouter.scala:87:24] wire out_womask_54 = &_out_womask_T_54; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_54 = out_rivalid_54 & out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_643 = out_f_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_f_roready_54 = out_roready_54 & out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_644 = out_f_roready_54; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_54 = out_wivalid_54 & out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_645 = out_f_wivalid_54; // @[RegisterRouter.scala:87:24] assign out_f_woready_54 = out_woready_54 & out_womask_54; // @[RegisterRouter.scala:87:24] assign autoexecprogbufWrEnMaybe = out_f_woready_54; // @[RegisterRouter.scala:87:24] wire _out_T_646 = out_f_woready_54; // @[RegisterRouter.scala:87:24] assign _out_T_642 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecprogbuf = _out_T_642; // @[RegisterRouter.scala:87:24] wire _out_T_647 = ~out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_648 = ~out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_649 = ~out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_650 = ~out_womask_54; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_42 = {ABSTRACTAUTORdData_autoexecprogbuf, _out_prepend_T_42}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_651 = out_prepend_42; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_652 = _out_T_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_24 = _out_T_652; // @[MuxLiteral.scala:49:48] wire out_rimask_55 = \|_out_rimask_T_55; // @[RegisterRouter.scala:87:24] wire out_wimask_55 = &_out_wimask_T_55; // @[RegisterRouter.scala:87:24] wire out_romask_55 = \|_out_romask_T_55; // @[RegisterRouter.scala:87:24] wire out_womask_55 = &_out_womask_T_55; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_55 = out_rivalid_55 & out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_654 = out_f_rivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_roready_55 = out_roready_55 & out_romask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_20 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire _out_T_655 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_55 = out_wivalid_55 & out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_656 = out_f_wivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_woready_55 = out_woready_55 & out_womask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_20 = out_f_woready_55; // @[RegisterRouter.scala:87:24] wire _out_T_657 = out_f_woready_55; // @[RegisterRouter.scala:87:24] assign programBufferNxt_20 = out_f_woready_55 ? _out_T_653 : programBufferMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_658 = ~out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_659 = ~out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_660 = ~out_romask_55; // @[RegisterRouter.scala:87:24] wire _out_T_661 = ~out_womask_55; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_663 = _out_T_662; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_43 = _out_T_663; // @[RegisterRouter.scala:87:24] wire out_rimask_56 = \|_out_rimask_T_56; // @[RegisterRouter.scala:87:24] wire out_wimask_56 = &_out_wimask_T_56; // @[RegisterRouter.scala:87:24] wire out_romask_56 = \|_out_romask_T_56; // @[RegisterRouter.scala:87:24] wire out_womask_56 = &_out_womask_T_56; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_56 = out_rivalid_56 & out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_665 = out_f_rivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_roready_56 = out_roready_56 & out_romask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_21 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire _out_T_666 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_56 = out_wivalid_56 & out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_667 = out_f_wivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_woready_56 = out_woready_56 & out_womask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_21 = out_f_woready_56; // @[RegisterRouter.scala:87:24] wire _out_T_668 = out_f_woready_56; // @[RegisterRouter.scala:87:24] assign programBufferNxt_21 = out_f_woready_56 ? _out_T_664 : programBufferMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_669 = ~out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_670 = ~out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_671 = ~out_romask_56; // @[RegisterRouter.scala:87:24] wire _out_T_672 = ~out_womask_56; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_43 = {programBufferMem_21, _out_prepend_T_43}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_673 = out_prepend_43; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_674 = _out_T_673; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_44 = _out_T_674; // @[RegisterRouter.scala:87:24] wire out_rimask_57 = \|_out_rimask_T_57; // @[RegisterRouter.scala:87:24] wire out_wimask_57 = &_out_wimask_T_57; // @[RegisterRouter.scala:87:24] wire out_romask_57 = \|_out_romask_T_57; // @[RegisterRouter.scala:87:24] wire out_womask_57 = &_out_womask_T_57; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_57 = out_rivalid_57 & out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_676 = out_f_rivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_roready_57 = out_roready_57 & out_romask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_22 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire _out_T_677 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_57 = out_wivalid_57 & out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_678 = out_f_wivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_woready_57 = out_woready_57 & out_womask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_22 = out_f_woready_57; // @[RegisterRouter.scala:87:24] wire _out_T_679 = out_f_woready_57; // @[RegisterRouter.scala:87:24] assign programBufferNxt_22 = out_f_woready_57 ? _out_T_675 : programBufferMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_680 = ~out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_681 = ~out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_682 = ~out_romask_57; // @[RegisterRouter.scala:87:24] wire _out_T_683 = ~out_womask_57; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_44 = {programBufferMem_22, _out_prepend_T_44}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_684 = out_prepend_44; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_685 = _out_T_684; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_45 = _out_T_685; // @[RegisterRouter.scala:87:24] wire out_rimask_58 = \|_out_rimask_T_58; // @[RegisterRouter.scala:87:24] wire out_wimask_58 = &_out_wimask_T_58; // @[RegisterRouter.scala:87:24] wire out_romask_58 = \|_out_romask_T_58; // @[RegisterRouter.scala:87:24] wire out_womask_58 = &_out_womask_T_58; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_58 = out_rivalid_58 & out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_687 = out_f_rivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_roready_58 = out_roready_58 & out_romask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_23 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire _out_T_688 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_58 = out_wivalid_58 & out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_689 = out_f_wivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_woready_58 = out_woready_58 & out_womask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_23 = out_f_woready_58; // @[RegisterRouter.scala:87:24] wire _out_T_690 = out_f_woready_58; // @[RegisterRouter.scala:87:24] assign programBufferNxt_23 = out_f_woready_58 ? _out_T_686 : programBufferMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_691 = ~out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_692 = ~out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_693 = ~out_romask_58; // @[RegisterRouter.scala:87:24] wire _out_T_694 = ~out_womask_58; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_45 = {programBufferMem_23, _out_prepend_T_45}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_695 = out_prepend_45; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_696 = _out_T_695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_37 = _out_T_696; // @[MuxLiteral.scala:49:48] wire out_rimask_59 = \|_out_rimask_T_59; // @[RegisterRouter.scala:87:24] wire out_wimask_59 = &_out_wimask_T_59; // @[RegisterRouter.scala:87:24] wire out_romask_59 = \|_out_romask_T_59; // @[RegisterRouter.scala:87:24] wire out_womask_59 = &_out_womask_T_59; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_59 = out_rivalid_59 & out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_698 = out_f_rivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_roready_59 = out_roready_59 & out_romask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_56 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire _out_T_699 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_59 = out_wivalid_59 & out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_700 = out_f_wivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_woready_59 = out_woready_59 & out_womask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_56 = out_f_woready_59; // @[RegisterRouter.scala:87:24] wire _out_T_701 = out_f_woready_59; // @[RegisterRouter.scala:87:24] assign programBufferNxt_56 = out_f_woready_59 ? _out_T_697 : programBufferMem_56; // @[RegisterRouter.scala:87:24] wire _out_T_702 = ~out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_703 = ~out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_704 = ~out_romask_59; // @[RegisterRouter.scala:87:24] wire _out_T_705 = ~out_womask_59; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_707 = _out_T_706; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_46 = _out_T_707; // @[RegisterRouter.scala:87:24] wire out_rimask_60 = \|_out_rimask_T_60; // @[RegisterRouter.scala:87:24] wire out_wimask_60 = &_out_wimask_T_60; // @[RegisterRouter.scala:87:24] wire out_romask_60 = \|_out_romask_T_60; // @[RegisterRouter.scala:87:24] wire out_womask_60 = &_out_womask_T_60; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_60 = out_rivalid_60 & out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_709 = out_f_rivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_roready_60 = out_roready_60 & out_romask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_57 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire _out_T_710 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_60 = out_wivalid_60 & out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_711 = out_f_wivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_woready_60 = out_woready_60 & out_womask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_57 = out_f_woready_60; // @[RegisterRouter.scala:87:24] wire _out_T_712 = out_f_woready_60; // @[RegisterRouter.scala:87:24] assign programBufferNxt_57 = out_f_woready_60 ? _out_T_708 : programBufferMem_57; // @[RegisterRouter.scala:87:24] wire _out_T_713 = ~out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_714 = ~out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_715 = ~out_romask_60; // @[RegisterRouter.scala:87:24] wire _out_T_716 = ~out_womask_60; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_46 = {programBufferMem_57, _out_prepend_T_46}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_717 = out_prepend_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_718 = _out_T_717; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_47 = _out_T_718; // @[RegisterRouter.scala:87:24] wire out_rimask_61 = \|_out_rimask_T_61; // @[RegisterRouter.scala:87:24] wire out_wimask_61 = &_out_wimask_T_61; // @[RegisterRouter.scala:87:24] wire out_romask_61 = \|_out_romask_T_61; // @[RegisterRouter.scala:87:24] wire out_womask_61 = &_out_womask_T_61; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_61 = out_rivalid_61 & out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_720 = out_f_rivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_roready_61 = out_roready_61 & out_romask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_58 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire _out_T_721 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_61 = out_wivalid_61 & out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_722 = out_f_wivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_woready_61 = out_woready_61 & out_womask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_58 = out_f_woready_61; // @[RegisterRouter.scala:87:24] wire _out_T_723 = out_f_woready_61; // @[RegisterRouter.scala:87:24] assign programBufferNxt_58 = out_f_woready_61 ? _out_T_719 : programBufferMem_58; // @[RegisterRouter.scala:87:24] wire _out_T_724 = ~out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_725 = ~out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_726 = ~out_romask_61; // @[RegisterRouter.scala:87:24] wire _out_T_727 = ~out_womask_61; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_47 = {programBufferMem_58, _out_prepend_T_47}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_728 = out_prepend_47; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_729 = _out_T_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_48 = _out_T_729; // @[RegisterRouter.scala:87:24] wire out_rimask_62 = \|_out_rimask_T_62; // @[RegisterRouter.scala:87:24] wire out_wimask_62 = &_out_wimask_T_62; // @[RegisterRouter.scala:87:24] wire out_romask_62 = \|_out_romask_T_62; // @[RegisterRouter.scala:87:24] wire out_womask_62 = &_out_womask_T_62; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_62 = out_rivalid_62 & out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_731 = out_f_rivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_roready_62 = out_roready_62 & out_romask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_59 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire _out_T_732 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_62 = out_wivalid_62 & out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_733 = out_f_wivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_woready_62 = out_woready_62 & out_womask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_59 = out_f_woready_62; // @[RegisterRouter.scala:87:24] wire _out_T_734 = out_f_woready_62; // @[RegisterRouter.scala:87:24] assign programBufferNxt_59 = out_f_woready_62 ? _out_T_730 : programBufferMem_59; // @[RegisterRouter.scala:87:24] wire _out_T_735 = ~out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_736 = ~out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_737 = ~out_romask_62; // @[RegisterRouter.scala:87:24] wire _out_T_738 = ~out_womask_62; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_48 = {programBufferMem_59, _out_prepend_T_48}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_739 = out_prepend_48; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_740 = _out_T_739; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_46 = _out_T_740; // @[MuxLiteral.scala:49:48] wire out_rimask_63 = \|_out_rimask_T_63; // @[RegisterRouter.scala:87:24] wire out_wimask_63 = &_out_wimask_T_63; // @[RegisterRouter.scala:87:24] wire out_romask_63 = \|_out_romask_T_63; // @[RegisterRouter.scala:87:24] wire out_womask_63 = &_out_womask_T_63; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_63 = out_rivalid_63 & out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_742 = out_f_rivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_roready_63 = out_roready_63 & out_romask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSRdEn_0 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire _out_T_743 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_63 = out_wivalid_63 & out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_744 = out_f_wivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_woready_63 = out_woready_63 & out_womask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrEn_0 = out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _out_T_745 = out_f_woready_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrData_0 = out_f_woready_63 ? _out_T_741 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_746 = ~out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_747 = ~out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_748 = ~out_romask_63; // @[RegisterRouter.scala:87:24] wire _out_T_749 = ~out_womask_63; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_751 = _out_T_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_57 = _out_T_751; // @[MuxLiteral.scala:49:48] wire out_rimask_64 = \|_out_rimask_T_64; // @[RegisterRouter.scala:87:24] wire out_wimask_64 = &_out_wimask_T_64; // @[RegisterRouter.scala:87:24] wire out_romask_64 = \|_out_romask_T_64; // @[RegisterRouter.scala:87:24] wire out_womask_64 = &_out_womask_T_64; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_64 = out_rivalid_64 & out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_753 = out_f_rivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_roready_64 = out_roready_64 & out_romask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_8 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire _out_T_754 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_64 = out_wivalid_64 & out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_755 = out_f_wivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_woready_64 = out_woready_64 & out_womask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_8 = out_f_woready_64; // @[RegisterRouter.scala:87:24] wire _out_T_756 = out_f_woready_64; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_8 = out_f_woready_64 ? _out_T_752 : abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_757 = ~out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_758 = ~out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_759 = ~out_romask_64; // @[RegisterRouter.scala:87:24] wire _out_T_760 = ~out_womask_64; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_762 = _out_T_761; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_49 = _out_T_762; // @[RegisterRouter.scala:87:24] wire out_rimask_65 = \|_out_rimask_T_65; // @[RegisterRouter.scala:87:24] wire out_wimask_65 = &_out_wimask_T_65; // @[RegisterRouter.scala:87:24] wire out_romask_65 = \|_out_romask_T_65; // @[RegisterRouter.scala:87:24] wire out_womask_65 = &_out_womask_T_65; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_65 = out_rivalid_65 & out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_764 = out_f_rivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_roready_65 = out_roready_65 & out_romask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_9 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire _out_T_765 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_65 = out_wivalid_65 & out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_766 = out_f_wivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_woready_65 = out_woready_65 & out_womask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_9 = out_f_woready_65; // @[RegisterRouter.scala:87:24] wire _out_T_767 = out_f_woready_65; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_9 = out_f_woready_65 ? _out_T_763 : abstractDataMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_768 = ~out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_769 = ~out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_770 = ~out_romask_65; // @[RegisterRouter.scala:87:24] wire _out_T_771 = ~out_womask_65; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_49 = {abstractDataMem_9, _out_prepend_T_49}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_772 = out_prepend_49; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_773 = _out_T_772; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_50 = _out_T_773; // @[RegisterRouter.scala:87:24] wire out_rimask_66 = \|_out_rimask_T_66; // @[RegisterRouter.scala:87:24] wire out_wimask_66 = &_out_wimask_T_66; // @[RegisterRouter.scala:87:24] wire out_romask_66 = \|_out_romask_T_66; // @[RegisterRouter.scala:87:24] wire out_womask_66 = &_out_womask_T_66; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_66 = out_rivalid_66 & out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_775 = out_f_rivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_roready_66 = out_roready_66 & out_romask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_10 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire _out_T_776 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_66 = out_wivalid_66 & out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_777 = out_f_wivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_woready_66 = out_woready_66 & out_womask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_10 = out_f_woready_66; // @[RegisterRouter.scala:87:24] wire _out_T_778 = out_f_woready_66; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_10 = out_f_woready_66 ? _out_T_774 : abstractDataMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_779 = ~out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_780 = ~out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_781 = ~out_romask_66; // @[RegisterRouter.scala:87:24] wire _out_T_782 = ~out_womask_66; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_50 = {abstractDataMem_10, _out_prepend_T_50}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_783 = out_prepend_50; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_784 = _out_T_783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_51 = _out_T_784; // @[RegisterRouter.scala:87:24] wire out_rimask_67 = \|_out_rimask_T_67; // @[RegisterRouter.scala:87:24] wire out_wimask_67 = &_out_wimask_T_67; // @[RegisterRouter.scala:87:24] wire out_romask_67 = \|_out_romask_T_67; // @[RegisterRouter.scala:87:24] wire out_womask_67 = &_out_womask_T_67; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_67 = out_rivalid_67 & out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_786 = out_f_rivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_roready_67 = out_roready_67 & out_romask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_11 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire _out_T_787 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_67 = out_wivalid_67 & out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_788 = out_f_wivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_woready_67 = out_woready_67 & out_womask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_11 = out_f_woready_67; // @[RegisterRouter.scala:87:24] wire _out_T_789 = out_f_woready_67; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_11 = out_f_woready_67 ? _out_T_785 : abstractDataMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_790 = ~out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_791 = ~out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_792 = ~out_romask_67; // @[RegisterRouter.scala:87:24] wire _out_T_793 = ~out_womask_67; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_51 = {abstractDataMem_11, _out_prepend_T_51}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_794 = out_prepend_51; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_795 = _out_T_794; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_6 = _out_T_795; // @[MuxLiteral.scala:49:48] wire out_rimask_68 = \|_out_rimask_T_68; // @[RegisterRouter.scala:87:24] wire out_wimask_68 = &_out_wimask_T_68; // @[RegisterRouter.scala:87:24] wire out_romask_68 = \|_out_romask_T_68; // @[RegisterRouter.scala:87:24] wire out_womask_68 = &_out_womask_T_68; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_68 = out_rivalid_68 & out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_797 = out_f_rivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_roready_68 = out_roready_68 & out_romask_68; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_0 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire _out_T_798 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_68 = out_wivalid_68 & out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_799 = out_f_wivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_woready_68 = out_woready_68 & out_womask_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_0 = out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _out_T_800 = out_f_woready_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_0 = out_f_woready_68 ? _out_T_796 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_801 = ~out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_802 = ~out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_803 = ~out_romask_68; // @[RegisterRouter.scala:87:24] wire _out_T_804 = ~out_womask_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_806 = _out_T_805; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_60 = _out_T_806; // @[MuxLiteral.scala:49:48] wire out_rimask_69 = \|_out_rimask_T_69; // @[RegisterRouter.scala:87:24] wire out_wimask_69 = &_out_wimask_T_69; // @[RegisterRouter.scala:87:24] wire out_romask_69 = \|_out_romask_T_69; // @[RegisterRouter.scala:87:24] wire out_womask_69 = &_out_womask_T_69; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_69 = out_rivalid_69 & out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_808 = out_f_rivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_roready_69 = out_roready_69 & out_romask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_24 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire _out_T_809 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_69 = out_wivalid_69 & out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_810 = out_f_wivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_woready_69 = out_woready_69 & out_womask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_24 = out_f_woready_69; // @[RegisterRouter.scala:87:24] wire _out_T_811 = out_f_woready_69; // @[RegisterRouter.scala:87:24] assign programBufferNxt_24 = out_f_woready_69 ? _out_T_807 : programBufferMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_812 = ~out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_813 = ~out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_814 = ~out_romask_69; // @[RegisterRouter.scala:87:24] wire _out_T_815 = ~out_womask_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_817 = _out_T_816; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_52 = _out_T_817; // @[RegisterRouter.scala:87:24] wire out_rimask_70 = \|_out_rimask_T_70; // @[RegisterRouter.scala:87:24] wire out_wimask_70 = &_out_wimask_T_70; // @[RegisterRouter.scala:87:24] wire out_romask_70 = \|_out_romask_T_70; // @[RegisterRouter.scala:87:24] wire out_womask_70 = &_out_womask_T_70; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_70 = out_rivalid_70 & out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_819 = out_f_rivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_roready_70 = out_roready_70 & out_romask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_25 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire _out_T_820 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_70 = out_wivalid_70 & out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_821 = out_f_wivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_woready_70 = out_woready_70 & out_womask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_25 = out_f_woready_70; // @[RegisterRouter.scala:87:24] wire _out_T_822 = out_f_woready_70; // @[RegisterRouter.scala:87:24] assign programBufferNxt_25 = out_f_woready_70 ? _out_T_818 : programBufferMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_823 = ~out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_824 = ~out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_825 = ~out_romask_70; // @[RegisterRouter.scala:87:24] wire _out_T_826 = ~out_womask_70; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_52 = {programBufferMem_25, _out_prepend_T_52}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_827 = out_prepend_52; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_828 = _out_T_827; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_53 = _out_T_828; // @[RegisterRouter.scala:87:24] wire out_rimask_71 = \|_out_rimask_T_71; // @[RegisterRouter.scala:87:24] wire out_wimask_71 = &_out_wimask_T_71; // @[RegisterRouter.scala:87:24] wire out_romask_71 = \|_out_romask_T_71; // @[RegisterRouter.scala:87:24] wire out_womask_71 = &_out_womask_T_71; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_71 = out_rivalid_71 & out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_830 = out_f_rivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_roready_71 = out_roready_71 & out_romask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_26 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire _out_T_831 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_71 = out_wivalid_71 & out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_832 = out_f_wivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_woready_71 = out_woready_71 & out_womask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_26 = out_f_woready_71; // @[RegisterRouter.scala:87:24] wire _out_T_833 = out_f_woready_71; // @[RegisterRouter.scala:87:24] assign programBufferNxt_26 = out_f_woready_71 ? _out_T_829 : programBufferMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_834 = ~out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_835 = ~out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_836 = ~out_romask_71; // @[RegisterRouter.scala:87:24] wire _out_T_837 = ~out_womask_71; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_53 = {programBufferMem_26, _out_prepend_T_53}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_838 = out_prepend_53; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_839 = _out_T_838; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_54 = _out_T_839; // @[RegisterRouter.scala:87:24] wire out_rimask_72 = \|_out_rimask_T_72; // @[RegisterRouter.scala:87:24] wire out_wimask_72 = &_out_wimask_T_72; // @[RegisterRouter.scala:87:24] wire out_romask_72 = \|_out_romask_T_72; // @[RegisterRouter.scala:87:24] wire out_womask_72 = &_out_womask_T_72; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_72 = out_rivalid_72 & out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_841 = out_f_rivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_roready_72 = out_roready_72 & out_romask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_27 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire _out_T_842 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_72 = out_wivalid_72 & out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_843 = out_f_wivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_woready_72 = out_woready_72 & out_womask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_27 = out_f_woready_72; // @[RegisterRouter.scala:87:24] wire _out_T_844 = out_f_woready_72; // @[RegisterRouter.scala:87:24] assign programBufferNxt_27 = out_f_woready_72 ? _out_T_840 : programBufferMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_845 = ~out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_846 = ~out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_847 = ~out_romask_72; // @[RegisterRouter.scala:87:24] wire _out_T_848 = ~out_womask_72; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_54 = {programBufferMem_27, _out_prepend_T_54}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_849 = out_prepend_54; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_850 = _out_T_849; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_38 = _out_T_850; // @[MuxLiteral.scala:49:48] wire out_rimask_73 = \|_out_rimask_T_73; // @[RegisterRouter.scala:87:24] wire out_wimask_73 = &_out_wimask_T_73; // @[RegisterRouter.scala:87:24] wire out_romask_73 = \|_out_romask_T_73; // @[RegisterRouter.scala:87:24] wire out_womask_73 = &_out_womask_T_73; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_73 = out_rivalid_73 & out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_852 = out_f_rivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_roready_73 = out_roready_73 & out_romask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_4 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire _out_T_853 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_73 = out_wivalid_73 & out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_854 = out_f_wivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_woready_73 = out_woready_73 & out_womask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_4 = out_f_woready_73; // @[RegisterRouter.scala:87:24] wire _out_T_855 = out_f_woready_73; // @[RegisterRouter.scala:87:24] assign programBufferNxt_4 = out_f_woready_73 ? _out_T_851 : programBufferMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_856 = ~out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_857 = ~out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_858 = ~out_romask_73; // @[RegisterRouter.scala:87:24] wire _out_T_859 = ~out_womask_73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_861 = _out_T_860; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_55 = _out_T_861; // @[RegisterRouter.scala:87:24] wire out_rimask_74 = \|_out_rimask_T_74; // @[RegisterRouter.scala:87:24] wire out_wimask_74 = &_out_wimask_T_74; // @[RegisterRouter.scala:87:24] wire out_romask_74 = \|_out_romask_T_74; // @[RegisterRouter.scala:87:24] wire out_womask_74 = &_out_womask_T_74; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_74 = out_rivalid_74 & out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_863 = out_f_rivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_roready_74 = out_roready_74 & out_romask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_5 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire _out_T_864 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_74 = out_wivalid_74 & out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_865 = out_f_wivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_woready_74 = out_woready_74 & out_womask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_5 = out_f_woready_74; // @[RegisterRouter.scala:87:24] wire _out_T_866 = out_f_woready_74; // @[RegisterRouter.scala:87:24] assign programBufferNxt_5 = out_f_woready_74 ? _out_T_862 : programBufferMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_867 = ~out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_868 = ~out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_869 = ~out_romask_74; // @[RegisterRouter.scala:87:24] wire _out_T_870 = ~out_womask_74; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_55 = {programBufferMem_5, _out_prepend_T_55}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_871 = out_prepend_55; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_872 = _out_T_871; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_56 = _out_T_872; // @[RegisterRouter.scala:87:24] wire out_rimask_75 = \|_out_rimask_T_75; // @[RegisterRouter.scala:87:24] wire out_wimask_75 = &_out_wimask_T_75; // @[RegisterRouter.scala:87:24] wire out_romask_75 = \|_out_romask_T_75; // @[RegisterRouter.scala:87:24] wire out_womask_75 = &_out_womask_T_75; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_75 = out_rivalid_75 & out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_874 = out_f_rivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_roready_75 = out_roready_75 & out_romask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_6 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire _out_T_875 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_75 = out_wivalid_75 & out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_876 = out_f_wivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_woready_75 = out_woready_75 & out_womask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_6 = out_f_woready_75; // @[RegisterRouter.scala:87:24] wire _out_T_877 = out_f_woready_75; // @[RegisterRouter.scala:87:24] assign programBufferNxt_6 = out_f_woready_75 ? _out_T_873 : programBufferMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_878 = ~out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_879 = ~out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_880 = ~out_romask_75; // @[RegisterRouter.scala:87:24] wire _out_T_881 = ~out_womask_75; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_56 = {programBufferMem_6, _out_prepend_T_56}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_882 = out_prepend_56; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_883 = _out_T_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_57 = _out_T_883; // @[RegisterRouter.scala:87:24] wire out_rimask_76 = \|_out_rimask_T_76; // @[RegisterRouter.scala:87:24] wire out_wimask_76 = &_out_wimask_T_76; // @[RegisterRouter.scala:87:24] wire out_romask_76 = \|_out_romask_T_76; // @[RegisterRouter.scala:87:24] wire out_womask_76 = &_out_womask_T_76; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_76 = out_rivalid_76 & out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_885 = out_f_rivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_roready_76 = out_roready_76 & out_romask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_7 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire _out_T_886 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_76 = out_wivalid_76 & out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_887 = out_f_wivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_woready_76 = out_woready_76 & out_womask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_7 = out_f_woready_76; // @[RegisterRouter.scala:87:24] wire _out_T_888 = out_f_woready_76; // @[RegisterRouter.scala:87:24] assign programBufferNxt_7 = out_f_woready_76 ? _out_T_884 : programBufferMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_889 = ~out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_890 = ~out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_891 = ~out_romask_76; // @[RegisterRouter.scala:87:24] wire _out_T_892 = ~out_womask_76; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_57 = {programBufferMem_7, _out_prepend_T_57}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_893 = out_prepend_57; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_894 = _out_T_893; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_33 = _out_T_894; // @[MuxLiteral.scala:49:48] wire out_rimask_77 = \|_out_rimask_T_77; // @[RegisterRouter.scala:87:24] wire out_wimask_77 = &_out_wimask_T_77; // @[RegisterRouter.scala:87:24] wire out_romask_77 = \|_out_romask_T_77; // @[RegisterRouter.scala:87:24] wire out_womask_77 = &_out_womask_T_77; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_77 = out_rivalid_77 & out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_896 = out_f_rivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_roready_77 = out_roready_77 & out_romask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_52 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire _out_T_897 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_77 = out_wivalid_77 & out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_898 = out_f_wivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_woready_77 = out_woready_77 & out_womask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_52 = out_f_woready_77; // @[RegisterRouter.scala:87:24] wire _out_T_899 = out_f_woready_77; // @[RegisterRouter.scala:87:24] assign programBufferNxt_52 = out_f_woready_77 ? _out_T_895 : programBufferMem_52; // @[RegisterRouter.scala:87:24] wire _out_T_900 = ~out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_901 = ~out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_902 = ~out_romask_77; // @[RegisterRouter.scala:87:24] wire _out_T_903 = ~out_womask_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_905 = _out_T_904; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_58 = _out_T_905; // @[RegisterRouter.scala:87:24] wire out_rimask_78 = \|_out_rimask_T_78; // @[RegisterRouter.scala:87:24] wire out_wimask_78 = &_out_wimask_T_78; // @[RegisterRouter.scala:87:24] wire out_romask_78 = \|_out_romask_T_78; // @[RegisterRouter.scala:87:24] wire out_womask_78 = &_out_womask_T_78; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_78 = out_rivalid_78 & out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_907 = out_f_rivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_roready_78 = out_roready_78 & out_romask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_53 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire _out_T_908 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_78 = out_wivalid_78 & out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_909 = out_f_wivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_woready_78 = out_woready_78 & out_womask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_53 = out_f_woready_78; // @[RegisterRouter.scala:87:24] wire _out_T_910 = out_f_woready_78; // @[RegisterRouter.scala:87:24] assign programBufferNxt_53 = out_f_woready_78 ? _out_T_906 : programBufferMem_53; // @[RegisterRouter.scala:87:24] wire _out_T_911 = ~out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_912 = ~out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_913 = ~out_romask_78; // @[RegisterRouter.scala:87:24] wire _out_T_914 = ~out_womask_78; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_58 = {programBufferMem_53, _out_prepend_T_58}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_915 = out_prepend_58; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_916 = _out_T_915; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_59 = _out_T_916; // @[RegisterRouter.scala:87:24] wire out_rimask_79 = \|_out_rimask_T_79; // @[RegisterRouter.scala:87:24] wire out_wimask_79 = &_out_wimask_T_79; // @[RegisterRouter.scala:87:24] wire out_romask_79 = \|_out_romask_T_79; // @[RegisterRouter.scala:87:24] wire out_womask_79 = &_out_womask_T_79; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_79 = out_rivalid_79 & out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_918 = out_f_rivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_roready_79 = out_roready_79 & out_romask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_54 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire _out_T_919 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_79 = out_wivalid_79 & out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_920 = out_f_wivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_woready_79 = out_woready_79 & out_womask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_54 = out_f_woready_79; // @[RegisterRouter.scala:87:24] wire _out_T_921 = out_f_woready_79; // @[RegisterRouter.scala:87:24] assign programBufferNxt_54 = out_f_woready_79 ? _out_T_917 : programBufferMem_54; // @[RegisterRouter.scala:87:24] wire _out_T_922 = ~out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_923 = ~out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_924 = ~out_romask_79; // @[RegisterRouter.scala:87:24] wire _out_T_925 = ~out_womask_79; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_59 = {programBufferMem_54, _out_prepend_T_59}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_926 = out_prepend_59; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_927 = _out_T_926; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_60 = _out_T_927; // @[RegisterRouter.scala:87:24] wire out_rimask_80 = \|_out_rimask_T_80; // @[RegisterRouter.scala:87:24] wire out_wimask_80 = &_out_wimask_T_80; // @[RegisterRouter.scala:87:24] wire out_romask_80 = \|_out_romask_T_80; // @[RegisterRouter.scala:87:24] wire out_womask_80 = &_out_womask_T_80; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_80 = out_rivalid_80 & out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_929 = out_f_rivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_roready_80 = out_roready_80 & out_romask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_55 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire _out_T_930 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_80 = out_wivalid_80 & out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_931 = out_f_wivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_woready_80 = out_woready_80 & out_womask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_55 = out_f_woready_80; // @[RegisterRouter.scala:87:24] wire _out_T_932 = out_f_woready_80; // @[RegisterRouter.scala:87:24] assign programBufferNxt_55 = out_f_woready_80 ? _out_T_928 : programBufferMem_55; // @[RegisterRouter.scala:87:24] wire _out_T_933 = ~out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_934 = ~out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_935 = ~out_romask_80; // @[RegisterRouter.scala:87:24] wire _out_T_936 = ~out_womask_80; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_60 = {programBufferMem_55, _out_prepend_T_60}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_937 = out_prepend_60; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_938 = _out_T_937; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_45 = _out_T_938; // @[MuxLiteral.scala:49:48] wire out_rimask_81 = \|_out_rimask_T_81; // @[RegisterRouter.scala:87:24] wire out_wimask_81 = &_out_wimask_T_81; // @[RegisterRouter.scala:87:24] wire out_romask_81 = \|_out_romask_T_81; // @[RegisterRouter.scala:87:24] wire out_womask_81 = &_out_womask_T_81; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_81 = out_rivalid_81 & out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_940 = out_f_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_f_roready_81 = out_roready_81 & out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_941 = out_f_roready_81; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_81 = out_wivalid_81 & out_wimask_81; // @[RegisterRouter.scala:87:24] wire out_f_woready_81 = out_woready_81 & out_womask_81; // @[RegisterRouter.scala:87:24] wire _out_T_942 = ~out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_943 = ~out_wimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_944 = ~out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_945 = ~out_womask_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_947 = _out_T_946; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_947; // @[MuxLiteral.scala:49:48] wire [3:0] _out_rimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_82 = \|_out_rimask_T_82; // @[RegisterRouter.scala:87:24] wire out_wimask_82 = &_out_wimask_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_romask_82 = \|_out_romask_T_82; // @[RegisterRouter.scala:87:24] wire out_womask_82 = &_out_womask_T_82; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_82 = out_rivalid_82 & out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_949 = out_f_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_f_roready_82 = out_roready_82 & out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_950 = out_f_roready_82; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_82 = out_wivalid_82 & out_wimask_82; // @[RegisterRouter.scala:87:24] wire out_f_woready_82 = out_woready_82 & out_womask_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_948 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1207 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire _out_T_951 = ~out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_952 = ~out_wimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_953 = ~out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_954 = ~out_womask_82; // @[RegisterRouter.scala:87:24] wire out_rimask_83 = _out_rimask_T_83; // @[RegisterRouter.scala:87:24] wire out_wimask_83 = _out_wimask_T_83; // @[RegisterRouter.scala:87:24] wire out_romask_83 = _out_romask_T_83; // @[RegisterRouter.scala:87:24] wire out_womask_83 = _out_womask_T_83; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_83 = out_rivalid_83 & out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_958 = out_f_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_f_roready_83 = out_roready_83 & out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_959 = out_f_roready_83; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_83 = out_wivalid_83 & out_wimask_83; // @[RegisterRouter.scala:87:24] wire out_f_woready_83 = out_woready_83 & out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_T_960 = ~out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_961 = ~out_wimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_962 = ~out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_963 = ~out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire out_rimask_84 = _out_rimask_T_84; // @[RegisterRouter.scala:87:24] wire out_wimask_84 = _out_wimask_T_84; // @[RegisterRouter.scala:87:24] wire _out_romask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire out_romask_84 = _out_romask_T_84; // @[RegisterRouter.scala:87:24] wire out_womask_84 = _out_womask_T_84; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_84 = out_rivalid_84 & out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_967 = out_f_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_f_roready_84 = out_roready_84 & out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_968 = out_f_roready_84; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_84 = out_wivalid_84 & out_wimask_84; // @[RegisterRouter.scala:87:24] wire out_f_woready_84 = out_woready_84 & out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_T_966 = out_front_bits_data[5]; // @[RegisterRouter.scala:87:24] wire _out_T_969 = ~out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_970 = ~out_wimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_971 = ~out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_972 = ~out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire out_rimask_85 = _out_rimask_T_85; // @[RegisterRouter.scala:87:24] wire out_wimask_85 = _out_wimask_T_85; // @[RegisterRouter.scala:87:24] wire _out_romask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire out_romask_85 = _out_romask_T_85; // @[RegisterRouter.scala:87:24] wire out_womask_85 = _out_womask_T_85; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_85 = out_rivalid_85 & out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_976 = out_f_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_f_roready_85 = out_roready_85 & out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_977 = out_f_roready_85; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_85 = out_wivalid_85 & out_wimask_85; // @[RegisterRouter.scala:87:24] wire out_f_woready_85 = out_woready_85 & out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_T_975 = out_front_bits_data[6]; // @[RegisterRouter.scala:87:24] wire _out_T_978 = ~out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_979 = ~out_wimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_980 = ~out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_981 = ~out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire out_rimask_86 = _out_rimask_T_86; // @[RegisterRouter.scala:87:24] wire out_wimask_86 = _out_wimask_T_86; // @[RegisterRouter.scala:87:24] wire _out_romask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire out_romask_86 = _out_romask_T_86; // @[RegisterRouter.scala:87:24] wire out_womask_86 = _out_womask_T_86; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_86 = out_rivalid_86 & out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_985 = out_f_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_f_roready_86 = out_roready_86 & out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_986 = out_f_roready_86; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_86 = out_wivalid_86 & out_wimask_86; // @[RegisterRouter.scala:87:24] wire out_f_woready_86 = out_woready_86 & out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_T_984 = out_front_bits_data[7]; // @[RegisterRouter.scala:87:24] wire _out_T_987 = ~out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_988 = ~out_wimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_989 = ~out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_990 = ~out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire out_rimask_87 = _out_rimask_T_87; // @[RegisterRouter.scala:87:24] wire out_wimask_87 = _out_wimask_T_87; // @[RegisterRouter.scala:87:24] wire _out_romask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire out_romask_87 = _out_romask_T_87; // @[RegisterRouter.scala:87:24] wire out_womask_87 = _out_womask_T_87; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_87 = out_rivalid_87 & out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_994 = out_f_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_f_roready_87 = out_roready_87 & out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_995 = out_f_roready_87; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_87 = out_wivalid_87 & out_wimask_87; // @[RegisterRouter.scala:87:24] wire out_f_woready_87 = out_woready_87 & out_womask_87; // @[RegisterRouter.scala:87:24] wire _out_T_993 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24] wire _out_T_996 = ~out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_997 = ~out_wimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_998 = ~out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_999 = ~out_womask_87; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_65 = {DMSTATUSRdData_anyhalted, 8'hA2}; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1000 = out_prepend_65; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1001 = _out_T_1000; // @[RegisterRouter.scala:87:24] wire [8:0] _out_prepend_T_66 = _out_T_1001; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire out_rimask_88 = _out_rimask_T_88; // @[RegisterRouter.scala:87:24] wire out_wimask_88 = _out_wimask_T_88; // @[RegisterRouter.scala:87:24] wire _out_romask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire out_romask_88 = _out_romask_T_88; // @[RegisterRouter.scala:87:24] wire out_womask_88 = _out_womask_T_88; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_88 = out_rivalid_88 & out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1003 = out_f_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_f_roready_88 = out_roready_88 & out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1004 = out_f_roready_88; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_88 = out_wivalid_88 & out_wimask_88; // @[RegisterRouter.scala:87:24] wire out_f_woready_88 = out_woready_88 & out_womask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1002 = out_front_bits_data[9]; // @[RegisterRouter.scala:87:24] wire _out_T_1005 = ~out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1006 = ~out_wimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1007 = ~out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1008 = ~out_womask_88; // @[RegisterRouter.scala:87:24] wire [9:0] out_prepend_66 = {DMSTATUSRdData_allhalted, _out_prepend_T_66}; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1009 = out_prepend_66; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1010 = _out_T_1009; // @[RegisterRouter.scala:87:24] wire [9:0] _out_prepend_T_67 = _out_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire out_rimask_89 = _out_rimask_T_89; // @[RegisterRouter.scala:87:24] wire out_wimask_89 = _out_wimask_T_89; // @[RegisterRouter.scala:87:24] wire _out_romask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire out_romask_89 = _out_romask_T_89; // @[RegisterRouter.scala:87:24] wire out_womask_89 = _out_womask_T_89; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_89 = out_rivalid_89 & out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1012 = out_f_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_f_roready_89 = out_roready_89 & out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1013 = out_f_roready_89; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_89 = out_wivalid_89 & out_wimask_89; // @[RegisterRouter.scala:87:24] wire out_f_woready_89 = out_woready_89 & out_womask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1011 = out_front_bits_data[10]; // @[RegisterRouter.scala:87:24] wire _out_T_1014 = ~out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1015 = ~out_wimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1016 = ~out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1017 = ~out_womask_89; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_67 = {DMSTATUSRdData_anyrunning, _out_prepend_T_67}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1018 = out_prepend_67; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1019 = _out_T_1018; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_68 = _out_T_1019; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire out_rimask_90 = _out_rimask_T_90; // @[RegisterRouter.scala:87:24] wire out_wimask_90 = _out_wimask_T_90; // @[RegisterRouter.scala:87:24] wire _out_romask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire out_romask_90 = _out_romask_T_90; // @[RegisterRouter.scala:87:24] wire out_womask_90 = _out_womask_T_90; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_90 = out_rivalid_90 & out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1021 = out_f_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_f_roready_90 = out_roready_90 & out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1022 = out_f_roready_90; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_90 = out_wivalid_90 & out_wimask_90; // @[RegisterRouter.scala:87:24] wire out_f_woready_90 = out_woready_90 & out_womask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1020 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1236 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1023 = ~out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1024 = ~out_wimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1025 = ~out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1026 = ~out_womask_90; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_68 = {DMSTATUSRdData_allrunning, _out_prepend_T_68}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1027 = out_prepend_68; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1028 = _out_T_1027; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_69 = _out_T_1028; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire out_rimask_91 = _out_rimask_T_91; // @[RegisterRouter.scala:87:24] wire out_wimask_91 = _out_wimask_T_91; // @[RegisterRouter.scala:87:24] wire _out_romask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire out_romask_91 = _out_romask_T_91; // @[RegisterRouter.scala:87:24] wire out_womask_91 = _out_womask_T_91; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_91 = out_rivalid_91 & out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1030 = out_f_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_f_roready_91 = out_roready_91 & out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1031 = out_f_roready_91; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_91 = out_wivalid_91 & out_wimask_91; // @[RegisterRouter.scala:87:24] wire out_f_woready_91 = out_woready_91 & out_womask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1029 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1245 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1032 = ~out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1033 = ~out_wimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1034 = ~out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1035 = ~out_womask_91; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_69 = {1'h0, _out_prepend_T_69}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1036 = out_prepend_69; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1037 = _out_T_1036; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_70 = _out_T_1037; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire out_rimask_92 = _out_rimask_T_92; // @[RegisterRouter.scala:87:24] wire out_wimask_92 = _out_wimask_T_92; // @[RegisterRouter.scala:87:24] wire _out_romask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire out_romask_92 = _out_romask_T_92; // @[RegisterRouter.scala:87:24] wire out_womask_92 = _out_womask_T_92; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_92 = out_rivalid_92 & out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1039 = out_f_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_f_roready_92 = out_roready_92 & out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1040 = out_f_roready_92; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_92 = out_wivalid_92 & out_wimask_92; // @[RegisterRouter.scala:87:24] wire out_f_woready_92 = out_woready_92 & out_womask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1038 = out_front_bits_data[13]; // @[RegisterRouter.scala:87:24] wire _out_T_1041 = ~out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1042 = ~out_wimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1043 = ~out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1044 = ~out_womask_92; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_70 = {DMSTATUSRdData_allunavail, _out_prepend_T_70}; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1045 = out_prepend_70; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1046 = _out_T_1045; // @[RegisterRouter.scala:87:24] wire [13:0] _out_prepend_T_71 = _out_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire out_rimask_93 = _out_rimask_T_93; // @[RegisterRouter.scala:87:24] wire out_wimask_93 = _out_wimask_T_93; // @[RegisterRouter.scala:87:24] wire _out_romask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire out_romask_93 = _out_romask_T_93; // @[RegisterRouter.scala:87:24] wire out_womask_93 = _out_womask_T_93; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_93 = out_rivalid_93 & out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1048 = out_f_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_f_roready_93 = out_roready_93 & out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1049 = out_f_roready_93; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_93 = out_wivalid_93 & out_wimask_93; // @[RegisterRouter.scala:87:24] wire out_f_woready_93 = out_woready_93 & out_womask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1047 = out_front_bits_data[14]; // @[RegisterRouter.scala:87:24] wire _out_T_1050 = ~out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1051 = ~out_wimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1052 = ~out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1053 = ~out_womask_93; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_71 = {DMSTATUSRdData_anynonexistent, _out_prepend_T_71}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1054 = out_prepend_71; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1055 = _out_T_1054; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_72 = _out_T_1055; // @[RegisterRouter.scala:87:24] wire out_rimask_94 = _out_rimask_T_94; // @[RegisterRouter.scala:87:24] wire out_wimask_94 = _out_wimask_T_94; // @[RegisterRouter.scala:87:24] wire out_romask_94 = _out_romask_T_94; // @[RegisterRouter.scala:87:24] wire out_womask_94 = _out_womask_T_94; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_94 = out_rivalid_94 & out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1057 = out_f_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_f_roready_94 = out_roready_94 & out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1058 = out_f_roready_94; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_94 = out_wivalid_94 & out_wimask_94; // @[RegisterRouter.scala:87:24] wire out_f_woready_94 = out_woready_94 & out_womask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1059 = ~out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1060 = ~out_wimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1061 = ~out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1062 = ~out_womask_94; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_72 = {DMSTATUSRdData_allnonexistent, _out_prepend_T_72}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1063 = out_prepend_72; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1064 = _out_T_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_73 = _out_T_1064; // @[RegisterRouter.scala:87:24] wire out_rimask_95 = _out_rimask_T_95; // @[RegisterRouter.scala:87:24] wire out_wimask_95 = _out_wimask_T_95; // @[RegisterRouter.scala:87:24] wire out_romask_95 = _out_romask_T_95; // @[RegisterRouter.scala:87:24] wire out_womask_95 = _out_womask_T_95; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_95 = out_rivalid_95 & out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1066 = out_f_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_f_roready_95 = out_roready_95 & out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1067 = out_f_roready_95; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_95 = out_wivalid_95 & out_wimask_95; // @[RegisterRouter.scala:87:24] wire out_f_woready_95 = out_woready_95 & out_womask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1068 = ~out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1069 = ~out_wimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1070 = ~out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1071 = ~out_womask_95; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_73 = {DMSTATUSRdData_anyresumeack, _out_prepend_T_73}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1072 = out_prepend_73; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1073 = _out_T_1072; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_74 = _out_T_1073; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire out_rimask_96 = _out_rimask_T_96; // @[RegisterRouter.scala:87:24] wire out_wimask_96 = _out_wimask_T_96; // @[RegisterRouter.scala:87:24] wire _out_romask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire out_romask_96 = _out_romask_T_96; // @[RegisterRouter.scala:87:24] wire out_womask_96 = _out_womask_T_96; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_96 = out_rivalid_96 & out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1075 = out_f_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_f_roready_96 = out_roready_96 & out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1076 = out_f_roready_96; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_96 = out_wivalid_96 & out_wimask_96; // @[RegisterRouter.scala:87:24] wire out_f_woready_96 = out_woready_96 & out_womask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1074 = out_front_bits_data[17]; // @[RegisterRouter.scala:87:24] wire _out_T_1077 = ~out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1078 = ~out_wimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1079 = ~out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1080 = ~out_womask_96; // @[RegisterRouter.scala:87:24] wire [17:0] out_prepend_74 = {DMSTATUSRdData_allresumeack, _out_prepend_T_74}; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1081 = out_prepend_74; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1082 = _out_T_1081; // @[RegisterRouter.scala:87:24] wire [17:0] _out_prepend_T_75 = _out_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire out_rimask_97 = _out_rimask_T_97; // @[RegisterRouter.scala:87:24] wire out_wimask_97 = _out_wimask_T_97; // @[RegisterRouter.scala:87:24] wire _out_romask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire out_romask_97 = _out_romask_T_97; // @[RegisterRouter.scala:87:24] wire out_womask_97 = _out_womask_T_97; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_97 = out_rivalid_97 & out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1084 = out_f_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_f_roready_97 = out_roready_97 & out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1085 = out_f_roready_97; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_97 = out_wivalid_97 & out_wimask_97; // @[RegisterRouter.scala:87:24] wire out_f_woready_97 = out_woready_97 & out_womask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1083 = out_front_bits_data[18]; // @[RegisterRouter.scala:87:24] wire _out_T_1086 = ~out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1087 = ~out_wimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1088 = ~out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1089 = ~out_womask_97; // @[RegisterRouter.scala:87:24] wire [18:0] out_prepend_75 = {DMSTATUSRdData_anyhavereset, _out_prepend_T_75}; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1090 = out_prepend_75; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1091 = _out_T_1090; // @[RegisterRouter.scala:87:24] wire [18:0] _out_prepend_T_76 = _out_T_1091; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire out_rimask_98 = _out_rimask_T_98; // @[RegisterRouter.scala:87:24] wire out_wimask_98 = _out_wimask_T_98; // @[RegisterRouter.scala:87:24] wire _out_romask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire out_romask_98 = _out_romask_T_98; // @[RegisterRouter.scala:87:24] wire out_womask_98 = _out_womask_T_98; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_98 = out_rivalid_98 & out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1093 = out_f_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_f_roready_98 = out_roready_98 & out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1094 = out_f_roready_98; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_98 = out_wivalid_98 & out_wimask_98; // @[RegisterRouter.scala:87:24] wire out_f_woready_98 = out_woready_98 & out_womask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1092 = out_front_bits_data[19]; // @[RegisterRouter.scala:87:24] wire _out_T_1095 = ~out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1096 = ~out_wimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1097 = ~out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1098 = ~out_womask_98; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_76 = {DMSTATUSRdData_allhavereset, _out_prepend_T_76}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1099 = out_prepend_76; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1100 = _out_T_1099; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_77 = _out_T_1100; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_rimask_99 = \|_out_rimask_T_99; // @[RegisterRouter.scala:87:24] wire out_wimask_99 = &_out_wimask_T_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_romask_99 = \|_out_romask_T_99; // @[RegisterRouter.scala:87:24] wire out_womask_99 = &_out_womask_T_99; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_99 = out_rivalid_99 & out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1102 = out_f_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_f_roready_99 = out_roready_99 & out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1103 = out_f_roready_99; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_99 = out_wivalid_99 & out_wimask_99; // @[RegisterRouter.scala:87:24] wire out_f_woready_99 = out_woready_99 & out_womask_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_1101 = out_front_bits_data[21:20]; // @[RegisterRouter.scala:87:24] wire _out_T_1104 = ~out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1105 = ~out_wimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1106 = ~out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1107 = ~out_womask_99; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_77 = {1'h0, _out_prepend_T_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1108 = {1'h0, out_prepend_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1109 = _out_T_1108; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_78 = _out_T_1109; // @[RegisterRouter.scala:87:24] wire out_rimask_100 = _out_rimask_T_100; // @[RegisterRouter.scala:87:24] wire out_wimask_100 = _out_wimask_T_100; // @[RegisterRouter.scala:87:24] wire out_romask_100 = _out_romask_T_100; // @[RegisterRouter.scala:87:24] wire out_womask_100 = _out_womask_T_100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_100 = out_rivalid_100 & out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1111 = out_f_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_f_roready_100 = out_roready_100 & out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1112 = out_f_roready_100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_100 = out_wivalid_100 & out_wimask_100; // @[RegisterRouter.scala:87:24] wire out_f_woready_100 = out_woready_100 & out_womask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1113 = ~out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1114 = ~out_wimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1115 = ~out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1116 = ~out_womask_100; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_78 = {1'h0, _out_prepend_T_78}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1117 = out_prepend_78; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1118 = _out_T_1117; // @[RegisterRouter.scala:87:24] wire out_rimask_101 = \|_out_rimask_T_101; // @[RegisterRouter.scala:87:24] wire out_wimask_101 = &_out_wimask_T_101; // @[RegisterRouter.scala:87:24] wire out_romask_101 = \|_out_romask_T_101; // @[RegisterRouter.scala:87:24] wire out_womask_101 = &_out_womask_T_101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_101 = out_rivalid_101 & out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1120 = out_f_rivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_roready_101 = out_roready_101 & out_romask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_0 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1121 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_101 = out_wivalid_101 & out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1122 = out_f_wivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_woready_101 = out_woready_101 & out_womask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_0 = out_f_woready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1123 = out_f_woready_101; // @[RegisterRouter.scala:87:24] assign programBufferNxt_0 = out_f_woready_101 ? _out_T_1119 : programBufferMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_1124 = ~out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1125 = ~out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1126 = ~out_romask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1127 = ~out_womask_101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1129 = _out_T_1128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_79 = _out_T_1129; // @[RegisterRouter.scala:87:24] wire out_rimask_102 = \|_out_rimask_T_102; // @[RegisterRouter.scala:87:24] wire out_wimask_102 = &_out_wimask_T_102; // @[RegisterRouter.scala:87:24] wire out_romask_102 = \|_out_romask_T_102; // @[RegisterRouter.scala:87:24] wire out_womask_102 = &_out_womask_T_102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_102 = out_rivalid_102 & out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1131 = out_f_rivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_roready_102 = out_roready_102 & out_romask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_1 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1132 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_102 = out_wivalid_102 & out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1133 = out_f_wivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_woready_102 = out_woready_102 & out_womask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_1 = out_f_woready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1134 = out_f_woready_102; // @[RegisterRouter.scala:87:24] assign programBufferNxt_1 = out_f_woready_102 ? _out_T_1130 : programBufferMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_1135 = ~out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1136 = ~out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1137 = ~out_romask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1138 = ~out_womask_102; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_79 = {programBufferMem_1, _out_prepend_T_79}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1139 = out_prepend_79; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1140 = _out_T_1139; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_80 = _out_T_1140; // @[RegisterRouter.scala:87:24] wire out_rimask_103 = \|_out_rimask_T_103; // @[RegisterRouter.scala:87:24] wire out_wimask_103 = &_out_wimask_T_103; // @[RegisterRouter.scala:87:24] wire out_romask_103 = \|_out_romask_T_103; // @[RegisterRouter.scala:87:24] wire out_womask_103 = &_out_womask_T_103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_103 = out_rivalid_103 & out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1142 = out_f_rivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_roready_103 = out_roready_103 & out_romask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_2 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1143 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_103 = out_wivalid_103 & out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1144 = out_f_wivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_woready_103 = out_woready_103 & out_womask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_2 = out_f_woready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1145 = out_f_woready_103; // @[RegisterRouter.scala:87:24] assign programBufferNxt_2 = out_f_woready_103 ? _out_T_1141 : programBufferMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_1146 = ~out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1147 = ~out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1148 = ~out_romask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1149 = ~out_womask_103; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_80 = {programBufferMem_2, _out_prepend_T_80}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1150 = out_prepend_80; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1151 = _out_T_1150; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_81 = _out_T_1151; // @[RegisterRouter.scala:87:24] wire out_rimask_104 = \|_out_rimask_T_104; // @[RegisterRouter.scala:87:24] wire out_wimask_104 = &_out_wimask_T_104; // @[RegisterRouter.scala:87:24] wire out_romask_104 = \|_out_romask_T_104; // @[RegisterRouter.scala:87:24] wire out_womask_104 = &_out_womask_T_104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_104 = out_rivalid_104 & out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1153 = out_f_rivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_roready_104 = out_roready_104 & out_romask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_3 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1154 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_104 = out_wivalid_104 & out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1155 = out_f_wivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_woready_104 = out_woready_104 & out_womask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_3 = out_f_woready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1156 = out_f_woready_104; // @[RegisterRouter.scala:87:24] assign programBufferNxt_3 = out_f_woready_104 ? _out_T_1152 : programBufferMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_1157 = ~out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1158 = ~out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1159 = ~out_romask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1160 = ~out_womask_104; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_81 = {programBufferMem_3, _out_prepend_T_81}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1161 = out_prepend_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1162 = _out_T_1161; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_32 = _out_T_1162; // @[MuxLiteral.scala:49:48] wire out_rimask_105 = \|_out_rimask_T_105; // @[RegisterRouter.scala:87:24] wire out_wimask_105 = &_out_wimask_T_105; // @[RegisterRouter.scala:87:24] wire out_romask_105 = \|_out_romask_T_105; // @[RegisterRouter.scala:87:24] wire out_womask_105 = &_out_womask_T_105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_105 = out_rivalid_105 & out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1164 = out_f_rivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_roready_105 = out_roready_105 & out_romask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_8 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1165 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_105 = out_wivalid_105 & out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1166 = out_f_wivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_woready_105 = out_woready_105 & out_womask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_8 = out_f_woready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1167 = out_f_woready_105; // @[RegisterRouter.scala:87:24] assign programBufferNxt_8 = out_f_woready_105 ? _out_T_1163 : programBufferMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_1168 = ~out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1169 = ~out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1170 = ~out_romask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1171 = ~out_womask_105; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1173 = _out_T_1172; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_82 = _out_T_1173; // @[RegisterRouter.scala:87:24] wire out_rimask_106 = \|_out_rimask_T_106; // @[RegisterRouter.scala:87:24] wire out_wimask_106 = &_out_wimask_T_106; // @[RegisterRouter.scala:87:24] wire out_romask_106 = \|_out_romask_T_106; // @[RegisterRouter.scala:87:24] wire out_womask_106 = &_out_womask_T_106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_106 = out_rivalid_106 & out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1175 = out_f_rivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_roready_106 = out_roready_106 & out_romask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_9 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1176 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_106 = out_wivalid_106 & out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1177 = out_f_wivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_woready_106 = out_woready_106 & out_womask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_9 = out_f_woready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1178 = out_f_woready_106; // @[RegisterRouter.scala:87:24] assign programBufferNxt_9 = out_f_woready_106 ? _out_T_1174 : programBufferMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_1179 = ~out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1180 = ~out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1181 = ~out_romask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1182 = ~out_womask_106; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_82 = {programBufferMem_9, _out_prepend_T_82}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1183 = out_prepend_82; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1184 = _out_T_1183; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_83 = _out_T_1184; // @[RegisterRouter.scala:87:24] wire out_rimask_107 = \|_out_rimask_T_107; // @[RegisterRouter.scala:87:24] wire out_wimask_107 = &_out_wimask_T_107; // @[RegisterRouter.scala:87:24] wire out_romask_107 = \|_out_romask_T_107; // @[RegisterRouter.scala:87:24] wire out_womask_107 = &_out_womask_T_107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_107 = out_rivalid_107 & out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1186 = out_f_rivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_roready_107 = out_roready_107 & out_romask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_10 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1187 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_107 = out_wivalid_107 & out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1188 = out_f_wivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_woready_107 = out_woready_107 & out_womask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_10 = out_f_woready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1189 = out_f_woready_107; // @[RegisterRouter.scala:87:24] assign programBufferNxt_10 = out_f_woready_107 ? _out_T_1185 : programBufferMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_1190 = ~out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1191 = ~out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1192 = ~out_romask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1193 = ~out_womask_107; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_83 = {programBufferMem_10, _out_prepend_T_83}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1194 = out_prepend_83; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1195 = _out_T_1194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_84 = _out_T_1195; // @[RegisterRouter.scala:87:24] wire out_rimask_108 = \|_out_rimask_T_108; // @[RegisterRouter.scala:87:24] wire out_wimask_108 = &_out_wimask_T_108; // @[RegisterRouter.scala:87:24] wire out_romask_108 = \|_out_romask_T_108; // @[RegisterRouter.scala:87:24] wire out_womask_108 = &_out_womask_T_108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_108 = out_rivalid_108 & out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1197 = out_f_rivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_roready_108 = out_roready_108 & out_romask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_11 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1198 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_108 = out_wivalid_108 & out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1199 = out_f_wivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_woready_108 = out_woready_108 & out_womask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_11 = out_f_woready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1200 = out_f_woready_108; // @[RegisterRouter.scala:87:24] assign programBufferNxt_11 = out_f_woready_108 ? _out_T_1196 : programBufferMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_1201 = ~out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1202 = ~out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1203 = ~out_romask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1204 = ~out_womask_108; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_84 = {programBufferMem_11, _out_prepend_T_84}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1205 = out_prepend_84; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1206 = _out_T_1205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_34 = _out_T_1206; // @[MuxLiteral.scala:49:48] wire out_rimask_109 = \|_out_rimask_T_109; // @[RegisterRouter.scala:87:24] wire out_wimask_109 = &_out_wimask_T_109; // @[RegisterRouter.scala:87:24] wire out_romask_109 = \|_out_romask_T_109; // @[RegisterRouter.scala:87:24] wire out_womask_109 = &_out_womask_T_109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_109 = out_rivalid_109 & out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1208 = out_f_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_f_roready_109 = out_roready_109 & out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1209 = out_f_roready_109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_109 = out_wivalid_109 & out_wimask_109; // @[RegisterRouter.scala:87:24] wire out_f_woready_109 = out_woready_109 & out_womask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1210 = ~out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1211 = ~out_wimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1212 = ~out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1213 = ~out_womask_109; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_rimask_110 = \|_out_rimask_T_110; // @[RegisterRouter.scala:87:24] wire out_wimask_110 = &_out_wimask_T_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_romask_110 = \|_out_romask_T_110; // @[RegisterRouter.scala:87:24] wire out_womask_110 = &_out_womask_T_110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_110 = out_rivalid_110 & out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1217 = out_f_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_f_roready_110 = out_roready_110 & out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1218 = out_f_roready_110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_110 = out_wivalid_110 & out_wimask_110; // @[RegisterRouter.scala:87:24] wire out_f_woready_110 = out_woready_110 & out_womask_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1216 = out_front_bits_data[7:4]; // @[RegisterRouter.scala:87:24] wire _out_T_1219 = ~out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1220 = ~out_wimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1221 = ~out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1222 = ~out_womask_110; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_111 = \|_out_rimask_T_111; // @[RegisterRouter.scala:87:24] wire out_wimask_111 = &_out_wimask_T_111; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_romask_111 = \|_out_romask_T_111; // @[RegisterRouter.scala:87:24] wire out_womask_111 = &_out_womask_T_111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_111 = out_rivalid_111 & out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1226 = out_f_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_f_roready_111 = out_roready_111 & out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1227 = out_f_roready_111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_111 = out_wivalid_111 & out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1228 = out_f_wivalid_111; // @[RegisterRouter.scala:87:24] assign out_f_woready_111 = out_woready_111 & out_womask_111; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrEnMaybe = out_f_woready_111; // @[RegisterRouter.scala:87:24] wire _out_T_1229 = out_f_woready_111; // @[RegisterRouter.scala:87:24] assign _out_T_1225 = out_front_bits_data[10:8]; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrData_cmderr = _out_T_1225; // @[RegisterRouter.scala:87:24] wire _out_T_1230 = ~out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1231 = ~out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1232 = ~out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1233 = ~out_womask_111; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_86 = {ABSTRACTCSRdData_cmderr, 8'h8}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1234 = out_prepend_86; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1235 = _out_T_1234; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_87 = _out_T_1235; // @[RegisterRouter.scala:87:24] wire out_rimask_112 = _out_rimask_T_112; // @[RegisterRouter.scala:87:24] wire out_wimask_112 = _out_wimask_T_112; // @[RegisterRouter.scala:87:24] wire out_romask_112 = _out_romask_T_112; // @[RegisterRouter.scala:87:24] wire out_womask_112 = _out_womask_T_112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_112 = out_rivalid_112 & out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1237 = out_f_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_f_roready_112 = out_roready_112 & out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1238 = out_f_roready_112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_112 = out_wivalid_112 & out_wimask_112; // @[RegisterRouter.scala:87:24] wire out_f_woready_112 = out_woready_112 & out_womask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1239 = ~out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1240 = ~out_wimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1241 = ~out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1242 = ~out_womask_112; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_87 = {1'h0, _out_prepend_T_87}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1243 = out_prepend_87; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1244 = _out_T_1243; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_88 = _out_T_1244; // @[RegisterRouter.scala:87:24] wire out_rimask_113 = _out_rimask_T_113; // @[RegisterRouter.scala:87:24] wire out_wimask_113 = _out_wimask_T_113; // @[RegisterRouter.scala:87:24] wire out_romask_113 = _out_romask_T_113; // @[RegisterRouter.scala:87:24] wire out_womask_113 = _out_womask_T_113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_113 = out_rivalid_113 & out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1246 = out_f_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_f_roready_113 = out_roready_113 & out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1247 = out_f_roready_113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_113 = out_wivalid_113 & out_wimask_113; // @[RegisterRouter.scala:87:24] wire out_f_woready_113 = out_woready_113 & out_womask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1248 = ~out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1249 = ~out_wimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1250 = ~out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1251 = ~out_womask_113; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_88 = {ABSTRACTCSRdData_busy, _out_prepend_T_88}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1252 = out_prepend_88; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1253 = _out_T_1252; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_89 = _out_T_1253; // @[RegisterRouter.scala:87:24] wire [10:0] _out_rimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_wimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_rimask_114 = \|_out_rimask_T_114; // @[RegisterRouter.scala:87:24] wire out_wimask_114 = &_out_wimask_T_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_romask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_womask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_romask_114 = \|_out_romask_T_114; // @[RegisterRouter.scala:87:24] wire out_womask_114 = &_out_womask_T_114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_114 = out_rivalid_114 & out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1255 = out_f_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_f_roready_114 = out_roready_114 & out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1256 = out_f_roready_114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_114 = out_wivalid_114 & out_wimask_114; // @[RegisterRouter.scala:87:24] wire out_f_woready_114 = out_woready_114 & out_womask_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1254 = out_front_bits_data[23:13]; // @[RegisterRouter.scala:87:24] wire _out_T_1257 = ~out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1258 = ~out_wimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1259 = ~out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1260 = ~out_womask_114; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_89 = {1'h0, _out_prepend_T_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1261 = {10'h0, out_prepend_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1262 = _out_T_1261; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_90 = _out_T_1262; // @[RegisterRouter.scala:87:24] wire [4:0] _out_rimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_wimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_115 = \|_out_rimask_T_115; // @[RegisterRouter.scala:87:24] wire out_wimask_115 = &_out_wimask_T_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_romask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_womask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_romask_115 = \|_out_romask_T_115; // @[RegisterRouter.scala:87:24] wire out_womask_115 = &_out_womask_T_115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_115 = out_rivalid_115 & out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1264 = out_f_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_f_roready_115 = out_roready_115 & out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1265 = out_f_roready_115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_115 = out_wivalid_115 & out_wimask_115; // @[RegisterRouter.scala:87:24] wire out_f_woready_115 = out_woready_115 & out_womask_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_1263 = out_front_bits_data[28:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1266 = ~out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1267 = ~out_wimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1268 = ~out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1269 = ~out_womask_115; // @[RegisterRouter.scala:87:24] wire [28:0] out_prepend_90 = {5'h10, _out_prepend_T_90}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1270 = out_prepend_90; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1271 = _out_T_1270; // @[RegisterRouter.scala:87:24] wire out_rimask_116 = \|_out_rimask_T_116; // @[RegisterRouter.scala:87:24] wire out_wimask_116 = &_out_wimask_T_116; // @[RegisterRouter.scala:87:24] wire out_romask_116 = \|_out_romask_T_116; // @[RegisterRouter.scala:87:24] wire out_womask_116 = &_out_womask_T_116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_116 = out_rivalid_116 & out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1273 = out_f_rivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_roready_116 = out_roready_116 & out_romask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_48 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1274 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_116 = out_wivalid_116 & out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1275 = out_f_wivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_woready_116 = out_woready_116 & out_womask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_48 = out_f_woready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1276 = out_f_woready_116; // @[RegisterRouter.scala:87:24] assign programBufferNxt_48 = out_f_woready_116 ? _out_T_1272 : programBufferMem_48; // @[RegisterRouter.scala:87:24] wire _out_T_1277 = ~out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1278 = ~out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1279 = ~out_romask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1280 = ~out_womask_116; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1282 = _out_T_1281; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_91 = _out_T_1282; // @[RegisterRouter.scala:87:24] wire out_rimask_117 = \|_out_rimask_T_117; // @[RegisterRouter.scala:87:24] wire out_wimask_117 = &_out_wimask_T_117; // @[RegisterRouter.scala:87:24] wire out_romask_117 = \|_out_romask_T_117; // @[RegisterRouter.scala:87:24] wire out_womask_117 = &_out_womask_T_117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_117 = out_rivalid_117 & out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1284 = out_f_rivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_roready_117 = out_roready_117 & out_romask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_49 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1285 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_117 = out_wivalid_117 & out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1286 = out_f_wivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_woready_117 = out_woready_117 & out_womask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_49 = out_f_woready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1287 = out_f_woready_117; // @[RegisterRouter.scala:87:24] assign programBufferNxt_49 = out_f_woready_117 ? _out_T_1283 : programBufferMem_49; // @[RegisterRouter.scala:87:24] wire _out_T_1288 = ~out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1289 = ~out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1290 = ~out_romask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1291 = ~out_womask_117; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_91 = {programBufferMem_49, _out_prepend_T_91}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1292 = out_prepend_91; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1293 = _out_T_1292; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_92 = _out_T_1293; // @[RegisterRouter.scala:87:24] wire out_rimask_118 = \|_out_rimask_T_118; // @[RegisterRouter.scala:87:24] wire out_wimask_118 = &_out_wimask_T_118; // @[RegisterRouter.scala:87:24] wire out_romask_118 = \|_out_romask_T_118; // @[RegisterRouter.scala:87:24] wire out_womask_118 = &_out_womask_T_118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_118 = out_rivalid_118 & out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1295 = out_f_rivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_50 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1296 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_118 = out_wivalid_118 & out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1297 = out_f_wivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_50 = out_f_woready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1298 = out_f_woready_118; // @[RegisterRouter.scala:87:24] assign programBufferNxt_50 = out_f_woready_118 ? _out_T_1294 : programBufferMem_50; // @[RegisterRouter.scala:87:24] wire _out_T_1299 = ~out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1300 = ~out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1301 = ~out_romask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1302 = ~out_womask_118; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_92 = {programBufferMem_50, _out_prepend_T_92}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1303 = out_prepend_92; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1304 = _out_T_1303; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_93 = _out_T_1304; // @[RegisterRouter.scala:87:24] wire out_rimask_119 = \|_out_rimask_T_119; // @[RegisterRouter.scala:87:24] wire out_wimask_119 = &_out_wimask_T_119; // @[RegisterRouter.scala:87:24] wire out_romask_119 = \|_out_romask_T_119; // @[RegisterRouter.scala:87:24] wire out_womask_119 = &_out_womask_T_119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_119 = out_rivalid_119 & out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1306 = out_f_rivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_roready_119 = out_roready_119 & out_romask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_51 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1307 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_119 = out_wivalid_119 & out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1308 = out_f_wivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_woready_119 = out_woready_119 & out_womask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_51 = out_f_woready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1309 = out_f_woready_119; // @[RegisterRouter.scala:87:24] assign programBufferNxt_51 = out_f_woready_119 ? _out_T_1305 : programBufferMem_51; // @[RegisterRouter.scala:87:24] wire _out_T_1310 = ~out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1311 = ~out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1312 = ~out_romask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1313 = ~out_womask_119; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_93 = {programBufferMem_51, _out_prepend_T_93}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1314 = out_prepend_93; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1315 = _out_T_1314; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_44 = _out_T_1315; // @[MuxLiteral.scala:49:48] wire out_rimask_120 = \|_out_rimask_T_120; // @[RegisterRouter.scala:87:24] wire out_wimask_120 = &_out_wimask_T_120; // @[RegisterRouter.scala:87:24] wire out_romask_120 = \|_out_romask_T_120; // @[RegisterRouter.scala:87:24] wire out_womask_120 = &_out_womask_T_120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_120 = out_rivalid_120 & out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1317 = out_f_rivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_roready_120 = out_roready_120 & out_romask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_12 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1318 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_120 = out_wivalid_120 & out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1319 = out_f_wivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_woready_120 = out_woready_120 & out_womask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_12 = out_f_woready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1320 = out_f_woready_120; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_12 = out_f_woready_120 ? _out_T_1316 : abstractDataMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_1321 = ~out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1322 = ~out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1323 = ~out_romask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1324 = ~out_womask_120; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1326 = _out_T_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_94 = _out_T_1326; // @[RegisterRouter.scala:87:24] wire out_rimask_121 = \|_out_rimask_T_121; // @[RegisterRouter.scala:87:24] wire out_wimask_121 = &_out_wimask_T_121; // @[RegisterRouter.scala:87:24] wire out_romask_121 = \|_out_romask_T_121; // @[RegisterRouter.scala:87:24] wire out_womask_121 = &_out_womask_T_121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_121 = out_rivalid_121 & out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1328 = out_f_rivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_roready_121 = out_roready_121 & out_romask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_13 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1329 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_121 = out_wivalid_121 & out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1330 = out_f_wivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_woready_121 = out_woready_121 & out_womask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_13 = out_f_woready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1331 = out_f_woready_121; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_13 = out_f_woready_121 ? _out_T_1327 : abstractDataMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_1332 = ~out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1333 = ~out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1334 = ~out_romask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1335 = ~out_womask_121; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_94 = {abstractDataMem_13, _out_prepend_T_94}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1336 = out_prepend_94; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1337 = _out_T_1336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_95 = _out_T_1337; // @[RegisterRouter.scala:87:24] wire out_rimask_122 = \|_out_rimask_T_122; // @[RegisterRouter.scala:87:24] wire out_wimask_122 = &_out_wimask_T_122; // @[RegisterRouter.scala:87:24] wire out_romask_122 = \|_out_romask_T_122; // @[RegisterRouter.scala:87:24] wire out_womask_122 = &_out_womask_T_122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_122 = out_rivalid_122 & out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1339 = out_f_rivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_roready_122 = out_roready_122 & out_romask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_14 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1340 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_122 = out_wivalid_122 & out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1341 = out_f_wivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_woready_122 = out_woready_122 & out_womask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_14 = out_f_woready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1342 = out_f_woready_122; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_14 = out_f_woready_122 ? _out_T_1338 : abstractDataMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_1343 = ~out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1344 = ~out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1345 = ~out_romask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1346 = ~out_womask_122; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_95 = {abstractDataMem_14, _out_prepend_T_95}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1347 = out_prepend_95; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1348 = _out_T_1347; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_96 = _out_T_1348; // @[RegisterRouter.scala:87:24] wire out_rimask_123 = \|_out_rimask_T_123; // @[RegisterRouter.scala:87:24] wire out_wimask_123 = &_out_wimask_T_123; // @[RegisterRouter.scala:87:24] wire out_romask_123 = \|_out_romask_T_123; // @[RegisterRouter.scala:87:24] wire out_womask_123 = &_out_womask_T_123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_123 = out_rivalid_123 & out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1350 = out_f_rivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_roready_123 = out_roready_123 & out_romask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_15 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1351 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_123 = out_wivalid_123 & out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1352 = out_f_wivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_woready_123 = out_woready_123 & out_womask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_15 = out_f_woready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1353 = out_f_woready_123; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_15 = out_f_woready_123 ? _out_T_1349 : abstractDataMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_1354 = ~out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1355 = ~out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1356 = ~out_romask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1357 = ~out_womask_123; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_96 = {abstractDataMem_15, _out_prepend_T_96}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1358 = out_prepend_96; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1359 = _out_T_1358; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_7 = _out_T_1359; // @[MuxLiteral.scala:49:48] wire out_rimask_124 = \|_out_rimask_T_124; // @[RegisterRouter.scala:87:24] wire out_wimask_124 = &_out_wimask_T_124; // @[RegisterRouter.scala:87:24] wire out_romask_124 = \|_out_romask_T_124; // @[RegisterRouter.scala:87:24] wire out_womask_124 = &_out_womask_T_124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_124 = out_rivalid_124 & out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1361 = out_f_rivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_roready_124 = out_roready_124 & out_romask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_28 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1362 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_124 = out_wivalid_124 & out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1363 = out_f_wivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_woready_124 = out_woready_124 & out_womask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_28 = out_f_woready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1364 = out_f_woready_124; // @[RegisterRouter.scala:87:24] assign programBufferNxt_28 = out_f_woready_124 ? _out_T_1360 : programBufferMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1365 = ~out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1366 = ~out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1367 = ~out_romask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1368 = ~out_womask_124; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1370 = _out_T_1369; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_97 = _out_T_1370; // @[RegisterRouter.scala:87:24] wire out_rimask_125 = \|_out_rimask_T_125; // @[RegisterRouter.scala:87:24] wire out_wimask_125 = &_out_wimask_T_125; // @[RegisterRouter.scala:87:24] wire out_romask_125 = \|_out_romask_T_125; // @[RegisterRouter.scala:87:24] wire out_womask_125 = &_out_womask_T_125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_125 = out_rivalid_125 & out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1372 = out_f_rivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_roready_125 = out_roready_125 & out_romask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_29 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1373 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_125 = out_wivalid_125 & out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1374 = out_f_wivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_woready_125 = out_woready_125 & out_womask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_29 = out_f_woready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1375 = out_f_woready_125; // @[RegisterRouter.scala:87:24] assign programBufferNxt_29 = out_f_woready_125 ? _out_T_1371 : programBufferMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1376 = ~out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1377 = ~out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1378 = ~out_romask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1379 = ~out_womask_125; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_97 = {programBufferMem_29, _out_prepend_T_97}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1380 = out_prepend_97; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1381 = _out_T_1380; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_98 = _out_T_1381; // @[RegisterRouter.scala:87:24] wire out_rimask_126 = \|_out_rimask_T_126; // @[RegisterRouter.scala:87:24] wire out_wimask_126 = &_out_wimask_T_126; // @[RegisterRouter.scala:87:24] wire out_romask_126 = \|_out_romask_T_126; // @[RegisterRouter.scala:87:24] wire out_womask_126 = &_out_womask_T_126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_126 = out_rivalid_126 & out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1383 = out_f_rivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_roready_126 = out_roready_126 & out_romask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_30 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1384 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_126 = out_wivalid_126 & out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1385 = out_f_wivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_woready_126 = out_woready_126 & out_womask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_30 = out_f_woready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1386 = out_f_woready_126; // @[RegisterRouter.scala:87:24] assign programBufferNxt_30 = out_f_woready_126 ? _out_T_1382 : programBufferMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1387 = ~out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1388 = ~out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1389 = ~out_romask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1390 = ~out_womask_126; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_98 = {programBufferMem_30, _out_prepend_T_98}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1391 = out_prepend_98; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1392 = _out_T_1391; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_99 = _out_T_1392; // @[RegisterRouter.scala:87:24] wire out_rimask_127 = \|_out_rimask_T_127; // @[RegisterRouter.scala:87:24] wire out_wimask_127 = &_out_wimask_T_127; // @[RegisterRouter.scala:87:24] wire out_romask_127 = \|_out_romask_T_127; // @[RegisterRouter.scala:87:24] wire out_womask_127 = &_out_womask_T_127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_127 = out_rivalid_127 & out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1394 = out_f_rivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_roready_127 = out_roready_127 & out_romask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_31 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1395 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_127 = out_wivalid_127 & out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1396 = out_f_wivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_woready_127 = out_woready_127 & out_womask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_31 = out_f_woready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1397 = out_f_woready_127; // @[RegisterRouter.scala:87:24] assign programBufferNxt_31 = out_f_woready_127 ? _out_T_1393 : programBufferMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1398 = ~out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1399 = ~out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1400 = ~out_romask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1401 = ~out_womask_127; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_99 = {programBufferMem_31, _out_prepend_T_99}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1402 = out_prepend_99; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1403 = _out_T_1402; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_39 = _out_T_1403; // @[MuxLiteral.scala:49:48] wire out_rimask_128 = \|_out_rimask_T_128; // @[RegisterRouter.scala:87:24] wire out_wimask_128 = &_out_wimask_T_128; // @[RegisterRouter.scala:87:24] wire out_romask_128 = \|_out_romask_T_128; // @[RegisterRouter.scala:87:24] wire out_womask_128 = &_out_womask_T_128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_128 = out_rivalid_128 & out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1405 = out_f_rivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_roready_128 = out_roready_128 & out_romask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_28 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1406 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_128 = out_wivalid_128 & out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1407 = out_f_wivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_woready_128 = out_woready_128 & out_womask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_28 = out_f_woready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1408 = out_f_woready_128; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_28 = out_f_woready_128 ? _out_T_1404 : abstractDataMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1409 = ~out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1410 = ~out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1411 = ~out_romask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1412 = ~out_womask_128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1414 = _out_T_1413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_100 = _out_T_1414; // @[RegisterRouter.scala:87:24] wire out_rimask_129 = \|_out_rimask_T_129; // @[RegisterRouter.scala:87:24] wire out_wimask_129 = &_out_wimask_T_129; // @[RegisterRouter.scala:87:24] wire out_romask_129 = \|_out_romask_T_129; // @[RegisterRouter.scala:87:24] wire out_womask_129 = &_out_womask_T_129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_129 = out_rivalid_129 & out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1416 = out_f_rivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_roready_129 = out_roready_129 & out_romask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_29 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1417 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_129 = out_wivalid_129 & out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1418 = out_f_wivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_woready_129 = out_woready_129 & out_womask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_29 = out_f_woready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1419 = out_f_woready_129; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_29 = out_f_woready_129 ? _out_T_1415 : abstractDataMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1420 = ~out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1421 = ~out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1422 = ~out_romask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1423 = ~out_womask_129; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_100 = {abstractDataMem_29, _out_prepend_T_100}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1424 = out_prepend_100; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1425 = _out_T_1424; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_101 = _out_T_1425; // @[RegisterRouter.scala:87:24] wire out_rimask_130 = \|_out_rimask_T_130; // @[RegisterRouter.scala:87:24] wire out_wimask_130 = &_out_wimask_T_130; // @[RegisterRouter.scala:87:24] wire out_romask_130 = \|_out_romask_T_130; // @[RegisterRouter.scala:87:24] wire out_womask_130 = &_out_womask_T_130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_130 = out_rivalid_130 & out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1427 = out_f_rivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_roready_130 = out_roready_130 & out_romask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_30 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1428 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_130 = out_wivalid_130 & out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1429 = out_f_wivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_woready_130 = out_woready_130 & out_womask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_30 = out_f_woready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1430 = out_f_woready_130; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_30 = out_f_woready_130 ? _out_T_1426 : abstractDataMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1431 = ~out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1432 = ~out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1433 = ~out_romask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1434 = ~out_womask_130; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_101 = {abstractDataMem_30, _out_prepend_T_101}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1435 = out_prepend_101; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1436 = _out_T_1435; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_102 = _out_T_1436; // @[RegisterRouter.scala:87:24] wire out_rimask_131 = \|_out_rimask_T_131; // @[RegisterRouter.scala:87:24] wire out_wimask_131 = &_out_wimask_T_131; // @[RegisterRouter.scala:87:24] wire out_romask_131 = \|_out_romask_T_131; // @[RegisterRouter.scala:87:24] wire out_womask_131 = &_out_womask_T_131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_131 = out_rivalid_131 & out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1438 = out_f_rivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_roready_131 = out_roready_131 & out_romask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_31 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1439 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_131 = out_wivalid_131 & out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1440 = out_f_wivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_woready_131 = out_woready_131 & out_womask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_31 = out_f_woready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1441 = out_f_woready_131; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_31 = out_f_woready_131 ? _out_T_1437 : abstractDataMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1442 = ~out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1443 = ~out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1444 = ~out_romask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1445 = ~out_womask_131; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_102 = {abstractDataMem_31, _out_prepend_T_102}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1446 = out_prepend_102; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1447 = _out_T_1446; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_11 = _out_T_1447; // @[MuxLiteral.scala:49:48] wire out_rimask_132 = \|_out_rimask_T_132; // @[RegisterRouter.scala:87:24] wire out_wimask_132 = &_out_wimask_T_132; // @[RegisterRouter.scala:87:24] wire out_romask_132 = \|_out_romask_T_132; // @[RegisterRouter.scala:87:24] wire out_womask_132 = &_out_womask_T_132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_132 = out_rivalid_132 & out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1449 = out_f_rivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_roready_132 = out_roready_132 & out_romask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_44 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1450 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_132 = out_wivalid_132 & out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1451 = out_f_wivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_woready_132 = out_woready_132 & out_womask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_44 = out_f_woready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1452 = out_f_woready_132; // @[RegisterRouter.scala:87:24] assign programBufferNxt_44 = out_f_woready_132 ? _out_T_1448 : programBufferMem_44; // @[RegisterRouter.scala:87:24] wire _out_T_1453 = ~out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1454 = ~out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1455 = ~out_romask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1456 = ~out_womask_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1458 = _out_T_1457; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_103 = _out_T_1458; // @[RegisterRouter.scala:87:24] wire out_rimask_133 = \|_out_rimask_T_133; // @[RegisterRouter.scala:87:24] wire out_wimask_133 = &_out_wimask_T_133; // @[RegisterRouter.scala:87:24] wire out_romask_133 = \|_out_romask_T_133; // @[RegisterRouter.scala:87:24] wire out_womask_133 = &_out_womask_T_133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_133 = out_rivalid_133 & out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1460 = out_f_rivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_roready_133 = out_roready_133 & out_romask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_45 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1461 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_133 = out_wivalid_133 & out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1462 = out_f_wivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_woready_133 = out_woready_133 & out_womask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_45 = out_f_woready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1463 = out_f_woready_133; // @[RegisterRouter.scala:87:24] assign programBufferNxt_45 = out_f_woready_133 ? _out_T_1459 : programBufferMem_45; // @[RegisterRouter.scala:87:24] wire _out_T_1464 = ~out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1465 = ~out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1466 = ~out_romask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1467 = ~out_womask_133; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_103 = {programBufferMem_45, _out_prepend_T_103}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1468 = out_prepend_103; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1469 = _out_T_1468; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_104 = _out_T_1469; // @[RegisterRouter.scala:87:24] wire out_rimask_134 = \|_out_rimask_T_134; // @[RegisterRouter.scala:87:24] wire out_wimask_134 = &_out_wimask_T_134; // @[RegisterRouter.scala:87:24] wire out_romask_134 = \|_out_romask_T_134; // @[RegisterRouter.scala:87:24] wire out_womask_134 = &_out_womask_T_134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_134 = out_rivalid_134 & out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1471 = out_f_rivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_roready_134 = out_roready_134 & out_romask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_46 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1472 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_134 = out_wivalid_134 & out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1473 = out_f_wivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_woready_134 = out_woready_134 & out_womask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_46 = out_f_woready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1474 = out_f_woready_134; // @[RegisterRouter.scala:87:24] assign programBufferNxt_46 = out_f_woready_134 ? _out_T_1470 : programBufferMem_46; // @[RegisterRouter.scala:87:24] wire _out_T_1475 = ~out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1476 = ~out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1477 = ~out_romask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1478 = ~out_womask_134; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_104 = {programBufferMem_46, _out_prepend_T_104}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1479 = out_prepend_104; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1480 = _out_T_1479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_105 = _out_T_1480; // @[RegisterRouter.scala:87:24] wire out_rimask_135 = \|_out_rimask_T_135; // @[RegisterRouter.scala:87:24] wire out_wimask_135 = &_out_wimask_T_135; // @[RegisterRouter.scala:87:24] wire out_romask_135 = \|_out_romask_T_135; // @[RegisterRouter.scala:87:24] wire out_womask_135 = &_out_womask_T_135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_135 = out_rivalid_135 & out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1482 = out_f_rivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_roready_135 = out_roready_135 & out_romask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_47 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1483 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_135 = out_wivalid_135 & out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1484 = out_f_wivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_woready_135 = out_woready_135 & out_womask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_47 = out_f_woready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1485 = out_f_woready_135; // @[RegisterRouter.scala:87:24] assign programBufferNxt_47 = out_f_woready_135 ? _out_T_1481 : programBufferMem_47; // @[RegisterRouter.scala:87:24] wire _out_T_1486 = ~out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1487 = ~out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1488 = ~out_romask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1489 = ~out_womask_135; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_105 = {programBufferMem_47, _out_prepend_T_105}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1490 = out_prepend_105; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1491 = _out_T_1490; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_43 = _out_T_1491; // @[MuxLiteral.scala:49:48] wire out_rimask_136 = \|_out_rimask_T_136; // @[RegisterRouter.scala:87:24] wire out_wimask_136 = &_out_wimask_T_136; // @[RegisterRouter.scala:87:24] wire out_romask_136 = \|_out_romask_T_136; // @[RegisterRouter.scala:87:24] wire out_womask_136 = &_out_womask_T_136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_136 = out_rivalid_136 & out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1493 = out_f_rivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_roready_136 = out_roready_136 & out_romask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_32 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1494 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_136 = out_wivalid_136 & out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1495 = out_f_wivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_woready_136 = out_woready_136 & out_womask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_32 = out_f_woready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1496 = out_f_woready_136; // @[RegisterRouter.scala:87:24] assign programBufferNxt_32 = out_f_woready_136 ? _out_T_1492 : programBufferMem_32; // @[RegisterRouter.scala:87:24] wire _out_T_1497 = ~out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1498 = ~out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1499 = ~out_romask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1500 = ~out_womask_136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1502 = _out_T_1501; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_106 = _out_T_1502; // @[RegisterRouter.scala:87:24] wire out_rimask_137 = \|_out_rimask_T_137; // @[RegisterRouter.scala:87:24] wire out_wimask_137 = &_out_wimask_T_137; // @[RegisterRouter.scala:87:24] wire out_romask_137 = \|_out_romask_T_137; // @[RegisterRouter.scala:87:24] wire out_womask_137 = &_out_womask_T_137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_137 = out_rivalid_137 & out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1504 = out_f_rivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_roready_137 = out_roready_137 & out_romask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_33 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1505 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_137 = out_wivalid_137 & out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1506 = out_f_wivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_woready_137 = out_woready_137 & out_womask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_33 = out_f_woready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1507 = out_f_woready_137; // @[RegisterRouter.scala:87:24] assign programBufferNxt_33 = out_f_woready_137 ? _out_T_1503 : programBufferMem_33; // @[RegisterRouter.scala:87:24] wire _out_T_1508 = ~out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1509 = ~out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1510 = ~out_romask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1511 = ~out_womask_137; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_106 = {programBufferMem_33, _out_prepend_T_106}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1512 = out_prepend_106; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1513 = _out_T_1512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_107 = _out_T_1513; // @[RegisterRouter.scala:87:24] wire out_rimask_138 = \|_out_rimask_T_138; // @[RegisterRouter.scala:87:24] wire out_wimask_138 = &_out_wimask_T_138; // @[RegisterRouter.scala:87:24] wire out_romask_138 = \|_out_romask_T_138; // @[RegisterRouter.scala:87:24] wire out_womask_138 = &_out_womask_T_138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_138 = out_rivalid_138 & out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1515 = out_f_rivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_roready_138 = out_roready_138 & out_romask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_34 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1516 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_138 = out_wivalid_138 & out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1517 = out_f_wivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_woready_138 = out_woready_138 & out_womask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_34 = out_f_woready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1518 = out_f_woready_138; // @[RegisterRouter.scala:87:24] assign programBufferNxt_34 = out_f_woready_138 ? _out_T_1514 : programBufferMem_34; // @[RegisterRouter.scala:87:24] wire _out_T_1519 = ~out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1520 = ~out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1521 = ~out_romask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1522 = ~out_womask_138; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_107 = {programBufferMem_34, _out_prepend_T_107}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1523 = out_prepend_107; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1524 = _out_T_1523; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_108 = _out_T_1524; // @[RegisterRouter.scala:87:24] wire out_rimask_139 = \|_out_rimask_T_139; // @[RegisterRouter.scala:87:24] wire out_wimask_139 = &_out_wimask_T_139; // @[RegisterRouter.scala:87:24] wire out_romask_139 = \|_out_romask_T_139; // @[RegisterRouter.scala:87:24] wire out_womask_139 = &_out_womask_T_139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_139 = out_rivalid_139 & out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1526 = out_f_rivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_roready_139 = out_roready_139 & out_romask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_35 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1527 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_139 = out_wivalid_139 & out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1528 = out_f_wivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_woready_139 = out_woready_139 & out_womask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_35 = out_f_woready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1529 = out_f_woready_139; // @[RegisterRouter.scala:87:24] assign programBufferNxt_35 = out_f_woready_139 ? _out_T_1525 : programBufferMem_35; // @[RegisterRouter.scala:87:24] wire _out_T_1530 = ~out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1531 = ~out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1532 = ~out_romask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1533 = ~out_womask_139; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_108 = {programBufferMem_35, _out_prepend_T_108}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1534 = out_prepend_108; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1535 = _out_T_1534; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_40 = _out_T_1535; // @[MuxLiteral.scala:49:48] wire out_rimask_140 = \|_out_rimask_T_140; // @[RegisterRouter.scala:87:24] wire out_wimask_140 = &_out_wimask_T_140; // @[RegisterRouter.scala:87:24] wire out_romask_140 = \|_out_romask_T_140; // @[RegisterRouter.scala:87:24] wire out_womask_140 = &_out_womask_T_140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_140 = out_rivalid_140 & out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1537 = out_f_rivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_roready_140 = out_roready_140 & out_romask_140; // @[RegisterRouter.scala:87:24] assign COMMANDRdEn = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1538 = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_140 = out_wivalid_140 & out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1539 = out_f_wivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_woready_140 = out_woready_140 & out_womask_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrEnMaybe = out_f_woready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1540 = out_f_woready_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrDataVal = out_f_woready_140 ? _out_T_1536 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1541 = ~out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1542 = ~out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1543 = ~out_romask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1544 = ~out_womask_140; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1546 = _out_T_1545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_23 = _out_T_1546; // @[MuxLiteral.scala:49:48] wire out_rimask_141 = \|_out_rimask_T_141; // @[RegisterRouter.scala:87:24] wire out_wimask_141 = &_out_wimask_T_141; // @[RegisterRouter.scala:87:24] wire out_romask_141 = \|_out_romask_T_141; // @[RegisterRouter.scala:87:24] wire out_womask_141 = &_out_womask_T_141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_141 = out_rivalid_141 & out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1548 = out_f_rivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_roready_141 = out_roready_141 & out_romask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_16 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1549 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_141 = out_wivalid_141 & out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1550 = out_f_wivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_woready_141 = out_woready_141 & out_womask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_16 = out_f_woready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1551 = out_f_woready_141; // @[RegisterRouter.scala:87:24] assign programBufferNxt_16 = out_f_woready_141 ? _out_T_1547 : programBufferMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_1552 = ~out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1553 = ~out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1554 = ~out_romask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1555 = ~out_womask_141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1557 = _out_T_1556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_109 = _out_T_1557; // @[RegisterRouter.scala:87:24] wire out_rimask_142 = \|_out_rimask_T_142; // @[RegisterRouter.scala:87:24] wire out_wimask_142 = &_out_wimask_T_142; // @[RegisterRouter.scala:87:24] wire out_romask_142 = \|_out_romask_T_142; // @[RegisterRouter.scala:87:24] wire out_womask_142 = &_out_womask_T_142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_142 = out_rivalid_142 & out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1559 = out_f_rivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_roready_142 = out_roready_142 & out_romask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_17 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1560 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_142 = out_wivalid_142 & out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1561 = out_f_wivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_woready_142 = out_woready_142 & out_womask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_17 = out_f_woready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1562 = out_f_woready_142; // @[RegisterRouter.scala:87:24] assign programBufferNxt_17 = out_f_woready_142 ? _out_T_1558 : programBufferMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_1563 = ~out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1564 = ~out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1565 = ~out_romask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1566 = ~out_womask_142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_109 = {programBufferMem_17, _out_prepend_T_109}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1567 = out_prepend_109; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1568 = _out_T_1567; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_110 = _out_T_1568; // @[RegisterRouter.scala:87:24] wire out_rimask_143 = \|_out_rimask_T_143; // @[RegisterRouter.scala:87:24] wire out_wimask_143 = &_out_wimask_T_143; // @[RegisterRouter.scala:87:24] wire out_romask_143 = \|_out_romask_T_143; // @[RegisterRouter.scala:87:24] wire out_womask_143 = &_out_womask_T_143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_143 = out_rivalid_143 & out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1570 = out_f_rivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_roready_143 = out_roready_143 & out_romask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_18 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1571 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_143 = out_wivalid_143 & out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1572 = out_f_wivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_woready_143 = out_woready_143 & out_womask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_18 = out_f_woready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1573 = out_f_woready_143; // @[RegisterRouter.scala:87:24] assign programBufferNxt_18 = out_f_woready_143 ? _out_T_1569 : programBufferMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_1574 = ~out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1575 = ~out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1576 = ~out_romask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1577 = ~out_womask_143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_110 = {programBufferMem_18, _out_prepend_T_110}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1578 = out_prepend_110; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1579 = _out_T_1578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_111 = _out_T_1579; // @[RegisterRouter.scala:87:24] wire out_rimask_144 = \|_out_rimask_T_144; // @[RegisterRouter.scala:87:24] wire out_wimask_144 = &_out_wimask_T_144; // @[RegisterRouter.scala:87:24] wire out_romask_144 = \|_out_romask_T_144; // @[RegisterRouter.scala:87:24] wire out_womask_144 = &_out_womask_T_144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_144 = out_rivalid_144 & out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1581 = out_f_rivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_roready_144 = out_roready_144 & out_romask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_19 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1582 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_144 = out_wivalid_144 & out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1583 = out_f_wivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_woready_144 = out_woready_144 & out_womask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_19 = out_f_woready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1584 = out_f_woready_144; // @[RegisterRouter.scala:87:24] assign programBufferNxt_19 = out_f_woready_144 ? _out_T_1580 : programBufferMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_1585 = ~out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1586 = ~out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1587 = ~out_romask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1588 = ~out_womask_144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_111 = {programBufferMem_19, _out_prepend_T_111}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1589 = out_prepend_111; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1590 = _out_T_1589; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_36 = _out_T_1590; // @[MuxLiteral.scala:49:48] wire out_rimask_145 = \|_out_rimask_T_145; // @[RegisterRouter.scala:87:24] wire out_wimask_145 = &_out_wimask_T_145; // @[RegisterRouter.scala:87:24] wire out_romask_145 = \|_out_romask_T_145; // @[RegisterRouter.scala:87:24] wire out_womask_145 = &_out_womask_T_145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_145 = out_rivalid_145 & out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1592 = out_f_rivalid_145; // @[RegisterRouter.scala:87:24] wire out_f_roready_145 = out_roready_145 & out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1593 = out_f_roready_145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_145 = out_wivalid_145 & out_wimask_145; // @[RegisterRouter.scala:87:24] wire out_f_woready_145 = out_woready_145 & out_womask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1594 = ~out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1595 = ~out_wimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1596 = ~out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1597 = ~out_womask_145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1599 = _out_T_1598; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_19 = _out_T_1599; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_lo = {out_iindex_lo_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi = {_out_iindex_T_5, _out_iindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_hi = {out_iindex_hi_hi, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_iindex = {out_iindex_hi, out_iindex_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_lo = {out_oindex_lo_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi = {_out_oindex_T_5, _out_oindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_hi = {out_oindex_hi_hi, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_oindex = {out_oindex_hi, out_oindex_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_frontSel_T = 64'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire out_frontSel_8 = _out_frontSel_T[8]; // @[OneHot.scala:58:35] wire out_frontSel_9 = _out_frontSel_T[9]; // @[OneHot.scala:58:35] wire out_frontSel_10 = _out_frontSel_T[10]; // @[OneHot.scala:58:35] wire out_frontSel_11 = _out_frontSel_T[11]; // @[OneHot.scala:58:35] wire out_frontSel_12 = _out_frontSel_T[12]; // @[OneHot.scala:58:35] wire out_frontSel_13 = _out_frontSel_T[13]; // @[OneHot.scala:58:35] wire out_frontSel_14 = _out_frontSel_T[14]; // @[OneHot.scala:58:35] wire out_frontSel_15 = _out_frontSel_T[15]; // @[OneHot.scala:58:35] wire out_frontSel_16 = _out_frontSel_T[16]; // @[OneHot.scala:58:35] wire out_frontSel_17 = _out_frontSel_T[17]; // @[OneHot.scala:58:35] wire out_frontSel_18 = _out_frontSel_T[18]; // @[OneHot.scala:58:35] wire out_frontSel_19 = _out_frontSel_T[19]; // @[OneHot.scala:58:35] wire out_frontSel_20 = _out_frontSel_T[20]; // @[OneHot.scala:58:35] wire out_frontSel_21 = _out_frontSel_T[21]; // @[OneHot.scala:58:35] wire out_frontSel_22 = _out_frontSel_T[22]; // @[OneHot.scala:58:35] wire out_frontSel_23 = _out_frontSel_T[23]; // @[OneHot.scala:58:35] wire out_frontSel_24 = _out_frontSel_T[24]; // @[OneHot.scala:58:35] wire out_frontSel_25 = _out_frontSel_T[25]; // @[OneHot.scala:58:35] wire out_frontSel_26 = _out_frontSel_T[26]; // @[OneHot.scala:58:35] wire out_frontSel_27 = _out_frontSel_T[27]; // @[OneHot.scala:58:35] wire out_frontSel_28 = _out_frontSel_T[28]; // @[OneHot.scala:58:35] wire out_frontSel_29 = _out_frontSel_T[29]; // @[OneHot.scala:58:35] wire out_frontSel_30 = _out_frontSel_T[30]; // @[OneHot.scala:58:35] wire out_frontSel_31 = _out_frontSel_T[31]; // @[OneHot.scala:58:35] wire out_frontSel_32 = _out_frontSel_T[32]; // @[OneHot.scala:58:35] wire out_frontSel_33 = _out_frontSel_T[33]; // @[OneHot.scala:58:35] wire out_frontSel_34 = _out_frontSel_T[34]; // @[OneHot.scala:58:35] wire out_frontSel_35 = _out_frontSel_T[35]; // @[OneHot.scala:58:35] wire out_frontSel_36 = _out_frontSel_T[36]; // @[OneHot.scala:58:35] wire out_frontSel_37 = _out_frontSel_T[37]; // @[OneHot.scala:58:35] wire out_frontSel_38 = _out_frontSel_T[38]; // @[OneHot.scala:58:35] wire out_frontSel_39 = _out_frontSel_T[39]; // @[OneHot.scala:58:35] wire out_frontSel_40 = _out_frontSel_T[40]; // @[OneHot.scala:58:35] wire out_frontSel_41 = _out_frontSel_T[41]; // @[OneHot.scala:58:35] wire out_frontSel_42 = _out_frontSel_T[42]; // @[OneHot.scala:58:35] wire out_frontSel_43 = _out_frontSel_T[43]; // @[OneHot.scala:58:35] wire out_frontSel_44 = _out_frontSel_T[44]; // @[OneHot.scala:58:35] wire out_frontSel_45 = _out_frontSel_T[45]; // @[OneHot.scala:58:35] wire out_frontSel_46 = _out_frontSel_T[46]; // @[OneHot.scala:58:35] wire out_frontSel_47 = _out_frontSel_T[47]; // @[OneHot.scala:58:35] wire out_frontSel_48 = _out_frontSel_T[48]; // @[OneHot.scala:58:35] wire out_frontSel_49 = _out_frontSel_T[49]; // @[OneHot.scala:58:35] wire out_frontSel_50 = _out_frontSel_T[50]; // @[OneHot.scala:58:35] wire out_frontSel_51 = _out_frontSel_T[51]; // @[OneHot.scala:58:35] wire out_frontSel_52 = _out_frontSel_T[52]; // @[OneHot.scala:58:35] wire out_frontSel_53 = _out_frontSel_T[53]; // @[OneHot.scala:58:35] wire out_frontSel_54 = _out_frontSel_T[54]; // @[OneHot.scala:58:35] wire out_frontSel_55 = _out_frontSel_T[55]; // @[OneHot.scala:58:35] wire out_frontSel_56 = _out_frontSel_T[56]; // @[OneHot.scala:58:35] wire out_frontSel_57 = _out_frontSel_T[57]; // @[OneHot.scala:58:35] wire out_frontSel_58 = _out_frontSel_T[58]; // @[OneHot.scala:58:35] wire out_frontSel_59 = _out_frontSel_T[59]; // @[OneHot.scala:58:35] wire out_frontSel_60 = _out_frontSel_T[60]; // @[OneHot.scala:58:35] wire out_frontSel_61 = _out_frontSel_T[61]; // @[OneHot.scala:58:35] wire out_frontSel_62 = _out_frontSel_T[62]; // @[OneHot.scala:58:35] wire out_frontSel_63 = _out_frontSel_T[63]; // @[OneHot.scala:58:35] wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire out_backSel_8 = _out_backSel_T[8]; // @[OneHot.scala:58:35] wire out_backSel_9 = _out_backSel_T[9]; // @[OneHot.scala:58:35] wire out_backSel_10 = _out_backSel_T[10]; // @[OneHot.scala:58:35] wire out_backSel_11 = _out_backSel_T[11]; // @[OneHot.scala:58:35] wire out_backSel_12 = _out_backSel_T[12]; // @[OneHot.scala:58:35] wire out_backSel_13 = _out_backSel_T[13]; // @[OneHot.scala:58:35] wire out_backSel_14 = _out_backSel_T[14]; // @[OneHot.scala:58:35] wire out_backSel_15 = _out_backSel_T[15]; // @[OneHot.scala:58:35] wire out_backSel_16 = _out_backSel_T[16]; // @[OneHot.scala:58:35] wire out_backSel_17 = _out_backSel_T[17]; // @[OneHot.scala:58:35] wire out_backSel_18 = _out_backSel_T[18]; // @[OneHot.scala:58:35] wire out_backSel_19 = _out_backSel_T[19]; // @[OneHot.scala:58:35] wire out_backSel_20 = _out_backSel_T[20]; // @[OneHot.scala:58:35] wire out_backSel_21 = _out_backSel_T[21]; // @[OneHot.scala:58:35] wire out_backSel_22 = _out_backSel_T[22]; // @[OneHot.scala:58:35] wire out_backSel_23 = _out_backSel_T[23]; // @[OneHot.scala:58:35] wire out_backSel_24 = _out_backSel_T[24]; // @[OneHot.scala:58:35] wire out_backSel_25 = _out_backSel_T[25]; // @[OneHot.scala:58:35] wire out_backSel_26 = _out_backSel_T[26]; // @[OneHot.scala:58:35] wire out_backSel_27 = _out_backSel_T[27]; // @[OneHot.scala:58:35] wire out_backSel_28 = _out_backSel_T[28]; // @[OneHot.scala:58:35] wire out_backSel_29 = _out_backSel_T[29]; // @[OneHot.scala:58:35] wire out_backSel_30 = _out_backSel_T[30]; // @[OneHot.scala:58:35] wire out_backSel_31 = _out_backSel_T[31]; // @[OneHot.scala:58:35] wire out_backSel_32 = _out_backSel_T[32]; // @[OneHot.scala:58:35] wire out_backSel_33 = _out_backSel_T[33]; // @[OneHot.scala:58:35] wire out_backSel_34 = _out_backSel_T[34]; // @[OneHot.scala:58:35] wire out_backSel_35 = _out_backSel_T[35]; // @[OneHot.scala:58:35] wire out_backSel_36 = _out_backSel_T[36]; // @[OneHot.scala:58:35] wire out_backSel_37 = _out_backSel_T[37]; // @[OneHot.scala:58:35] wire out_backSel_38 = _out_backSel_T[38]; // @[OneHot.scala:58:35] wire out_backSel_39 = _out_backSel_T[39]; // @[OneHot.scala:58:35] wire out_backSel_40 = _out_backSel_T[40]; // @[OneHot.scala:58:35] wire out_backSel_41 = _out_backSel_T[41]; // @[OneHot.scala:58:35] wire out_backSel_42 = _out_backSel_T[42]; // @[OneHot.scala:58:35] wire out_backSel_43 = _out_backSel_T[43]; // @[OneHot.scala:58:35] wire out_backSel_44 = _out_backSel_T[44]; // @[OneHot.scala:58:35] wire out_backSel_45 = _out_backSel_T[45]; // @[OneHot.scala:58:35] wire out_backSel_46 = _out_backSel_T[46]; // @[OneHot.scala:58:35] wire out_backSel_47 = _out_backSel_T[47]; // @[OneHot.scala:58:35] wire out_backSel_48 = _out_backSel_T[48]; // @[OneHot.scala:58:35] wire out_backSel_49 = _out_backSel_T[49]; // @[OneHot.scala:58:35] wire out_backSel_50 = _out_backSel_T[50]; // @[OneHot.scala:58:35] wire out_backSel_51 = _out_backSel_T[51]; // @[OneHot.scala:58:35] wire out_backSel_52 = _out_backSel_T[52]; // @[OneHot.scala:58:35] wire out_backSel_53 = _out_backSel_T[53]; // @[OneHot.scala:58:35] wire out_backSel_54 = _out_backSel_T[54]; // @[OneHot.scala:58:35] wire out_backSel_55 = _out_backSel_T[55]; // @[OneHot.scala:58:35] wire out_backSel_56 = _out_backSel_T[56]; // @[OneHot.scala:58:35] wire out_backSel_57 = _out_backSel_T[57]; // @[OneHot.scala:58:35] wire out_backSel_58 = _out_backSel_T[58]; // @[OneHot.scala:58:35] wire out_backSel_59 = _out_backSel_T[59]; // @[OneHot.scala:58:35] wire out_backSel_60 = _out_backSel_T[60]; // @[OneHot.scala:58:35] wire out_backSel_61 = _out_backSel_T[61]; // @[OneHot.scala:58:35] wire out_backSel_62 = _out_backSel_T[62]; // @[OneHot.scala:58:35] wire out_backSel_63 = _out_backSel_T[63]; // @[OneHot.scala:58:35] wire _GEN_11 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_rivalid_81 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_21 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_22 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_23 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_24 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_rivalid_64 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_65 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_66 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_67 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_rivalid_120 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_121 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_122 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_123 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = _out_rifireMux_T_1 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_35 = _out_rifireMux_T_34 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_18 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_19 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_20 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_36 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_38 = _out_rifireMux_T_1 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_39 = _out_rifireMux_T_38 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_42 = _out_rifireMux_T_1 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_43 = _out_rifireMux_T_42 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_rivalid_29 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_30 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_31 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_32 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_44 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_46 = _out_rifireMux_T_1 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_47 = _out_rifireMux_T_46 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_rivalid_128 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_129 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_130 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_131 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_50 = _out_rifireMux_T_1 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_51 = _out_rifireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_54 = _out_rifireMux_T_1 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_55 = _out_rifireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_58 = _out_rifireMux_T_1 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_59 = _out_rifireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_62 = _out_rifireMux_T_1 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_63 = _out_rifireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = _out_rifireMux_T_1 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67 = _out_rifireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_70 = _out_rifireMux_T_1 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_71 = _out_rifireMux_T_70 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_rivalid_82 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_83 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_84 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_85 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_86 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_87 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_88 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_89 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_90 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_91 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_92 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_93 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_94 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_95 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_96 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_97 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_98 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_99 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_100 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_72 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_74 = _out_rifireMux_T_1 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_75 = _out_rifireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_78 = _out_rifireMux_T_1 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_79 = _out_rifireMux_T_78 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_rivalid_145 = _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_80 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_82 = _out_rifireMux_T_1 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83 = _out_rifireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_86 = _out_rifireMux_T_1 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_87 = _out_rifireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_90 = _out_rifireMux_T_1 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_91 = _out_rifireMux_T_90 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_rivalid_109 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_110 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_111 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_112 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_113 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_114 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_115 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_92 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_94 = _out_rifireMux_T_1 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_95 = _out_rifireMux_T_94 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_rivalid_140 = _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_96 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_98 = _out_rifireMux_T_1 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_99 = _out_rifireMux_T_98 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_rivalid_52 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_53 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_54 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_102 = _out_rifireMux_T_1 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_103 = _out_rifireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_106 = _out_rifireMux_T_1 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_107 = _out_rifireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_110 = _out_rifireMux_T_1 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_111 = _out_rifireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_114 = _out_rifireMux_T_1 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_115 = _out_rifireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_118 = _out_rifireMux_T_1 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_119 = _out_rifireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_122 = _out_rifireMux_T_1 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_123 = _out_rifireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_126 = _out_rifireMux_T_1 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_127 = _out_rifireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_130 = _out_rifireMux_T_1 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_131 = _out_rifireMux_T_130 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_rivalid_101 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_102 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_103 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_104 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_132 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_134 = _out_rifireMux_T_1 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_135 = _out_rifireMux_T_134 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_rivalid_73 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_74 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_75 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_76 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_136 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_138 = _out_rifireMux_T_1 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_139 = _out_rifireMux_T_138 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_rivalid_105 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_106 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_107 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_108 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_140 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_142 = _out_rifireMux_T_1 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_143 = _out_rifireMux_T_142 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_144 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_146 = _out_rifireMux_T_1 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_147 = _out_rifireMux_T_146 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_rivalid_141 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_142 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_143 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_144 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_148 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_150 = _out_rifireMux_T_1 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_151 = _out_rifireMux_T_150 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_rivalid_55 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_56 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_57 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_58 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_152 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_154 = _out_rifireMux_T_1 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_155 = _out_rifireMux_T_154 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_rivalid_69 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_70 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_71 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_72 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_156 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_158 = _out_rifireMux_T_1 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_159 = _out_rifireMux_T_158 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_rivalid_124 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_125 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_126 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_127 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_160 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_162 = _out_rifireMux_T_1 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_163 = _out_rifireMux_T_162 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_rivalid_136 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_137 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_138 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_139 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_164 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_166 = _out_rifireMux_T_1 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_167 = _out_rifireMux_T_166 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_168 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_170 = _out_rifireMux_T_1 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_171 = _out_rifireMux_T_170 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_rivalid_48 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_49 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_50 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_51 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_172 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_174 = _out_rifireMux_T_1 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_175 = _out_rifireMux_T_174 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_rivalid_132 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_133 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_134 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_135 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_176 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_178 = _out_rifireMux_T_1 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_179 = _out_rifireMux_T_178 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_rivalid_116 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_117 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_118 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_119 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_180 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_182 = _out_rifireMux_T_1 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_183 = _out_rifireMux_T_182 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_rivalid_77 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_78 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_79 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_80 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_184 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_186 = _out_rifireMux_T_1 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_187 = _out_rifireMux_T_186 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_rivalid_59 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_60 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_61 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_62 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_188 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_190 = _out_rifireMux_T_1 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_191 = _out_rifireMux_T_190 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_rivalid_25 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_26 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_27 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_28 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_192 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_194 = _out_rifireMux_T_1 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_195 = _out_rifireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_198 = _out_rifireMux_T_1 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_199 = _out_rifireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_202 = _out_rifireMux_T_1 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_203 = _out_rifireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_206 = _out_rifireMux_T_1 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_207 = _out_rifireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_210 = _out_rifireMux_T_1 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_211 = _out_rifireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_214 = _out_rifireMux_T_1 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_215 = _out_rifireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_218 = _out_rifireMux_T_1 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_219 = _out_rifireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_222 = _out_rifireMux_T_1 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_223 = _out_rifireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_226 = _out_rifireMux_T_1 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_227 = _out_rifireMux_T_226 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_rivalid_33 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_34 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_35 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_36 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_37 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_38 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_39 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_40 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_41 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_42 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_43 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_44 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_45 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_46 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_47 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_228 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_230 = _out_rifireMux_T_1 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_231 = _out_rifireMux_T_230 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_rivalid_63 = _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_232 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_234 = _out_rifireMux_T_1 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_235 = _out_rifireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_238 = _out_rifireMux_T_1 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_239 = _out_rifireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_242 = _out_rifireMux_T_1 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_243 = _out_rifireMux_T_242 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_rivalid_68 = _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_244 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_246 = _out_rifireMux_T_1 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_247 = _out_rifireMux_T_246 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_248 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_250 = _out_rifireMux_T_1 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_251 = _out_rifireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_254 = _out_rifireMux_T_1 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_255 = _out_rifireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_81 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_21 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_22 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_23 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_24 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_wivalid_64 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_65 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_66 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_67 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_wivalid_120 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_121 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_122 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_123 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = _out_wifireMux_T_2 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_36 = _out_wifireMux_T_35 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_18 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_19 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_20 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_37 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_39 = _out_wifireMux_T_2 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_40 = _out_wifireMux_T_39 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_43 = _out_wifireMux_T_2 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_44 = _out_wifireMux_T_43 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_29 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_30 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_31 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_32 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_45 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_47 = _out_wifireMux_T_2 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_48 = _out_wifireMux_T_47 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_wivalid_128 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_129 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_130 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_131 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_51 = _out_wifireMux_T_2 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_52 = _out_wifireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_55 = _out_wifireMux_T_2 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_56 = _out_wifireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_59 = _out_wifireMux_T_2 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_60 = _out_wifireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_63 = _out_wifireMux_T_2 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_64 = _out_wifireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = _out_wifireMux_T_2 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68 = _out_wifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_71 = _out_wifireMux_T_2 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_72 = _out_wifireMux_T_71 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_wivalid_82 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_83 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_84 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_85 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_86 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_87 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_88 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_89 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_90 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_91 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_92 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_93 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_94 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_95 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_96 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_97 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_98 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_99 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_100 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_73 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_75 = _out_wifireMux_T_2 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_76 = _out_wifireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_79 = _out_wifireMux_T_2 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_80 = _out_wifireMux_T_79 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_wivalid_145 = _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_81 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_83 = _out_wifireMux_T_2 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84 = _out_wifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_87 = _out_wifireMux_T_2 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_88 = _out_wifireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_91 = _out_wifireMux_T_2 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_92 = _out_wifireMux_T_91 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_109 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_110 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_111 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_112 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_113 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_114 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_115 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_93 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_95 = _out_wifireMux_T_2 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_96 = _out_wifireMux_T_95 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_wivalid_140 = _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_97 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_99 = _out_wifireMux_T_2 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_100 = _out_wifireMux_T_99 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_wivalid_52 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_53 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_54 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_103 = _out_wifireMux_T_2 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_104 = _out_wifireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_107 = _out_wifireMux_T_2 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_108 = _out_wifireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_111 = _out_wifireMux_T_2 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_112 = _out_wifireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_115 = _out_wifireMux_T_2 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_116 = _out_wifireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_119 = _out_wifireMux_T_2 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_120 = _out_wifireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_123 = _out_wifireMux_T_2 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_124 = _out_wifireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_127 = _out_wifireMux_T_2 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_128 = _out_wifireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_131 = _out_wifireMux_T_2 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_132 = _out_wifireMux_T_131 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_101 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_102 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_103 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_104 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_133 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_135 = _out_wifireMux_T_2 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_136 = _out_wifireMux_T_135 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_73 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_74 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_75 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_76 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_137 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_139 = _out_wifireMux_T_2 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_140 = _out_wifireMux_T_139 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_wivalid_105 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_106 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_107 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_108 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_141 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_143 = _out_wifireMux_T_2 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_144 = _out_wifireMux_T_143 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_145 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_147 = _out_wifireMux_T_2 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_148 = _out_wifireMux_T_147 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_wivalid_141 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_142 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_143 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_144 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_149 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_151 = _out_wifireMux_T_2 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_152 = _out_wifireMux_T_151 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_55 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_56 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_57 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_58 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_153 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_155 = _out_wifireMux_T_2 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_156 = _out_wifireMux_T_155 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_wivalid_69 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_70 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_71 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_72 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_157 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_159 = _out_wifireMux_T_2 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_160 = _out_wifireMux_T_159 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_wivalid_124 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_125 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_126 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_127 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_161 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_163 = _out_wifireMux_T_2 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_164 = _out_wifireMux_T_163 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_wivalid_136 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_137 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_138 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_139 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_165 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_167 = _out_wifireMux_T_2 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_168 = _out_wifireMux_T_167 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_169 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_171 = _out_wifireMux_T_2 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_172 = _out_wifireMux_T_171 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_48 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_49 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_50 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_51 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_173 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_175 = _out_wifireMux_T_2 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_176 = _out_wifireMux_T_175 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_wivalid_132 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_133 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_134 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_135 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_177 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_179 = _out_wifireMux_T_2 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_180 = _out_wifireMux_T_179 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_wivalid_116 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_117 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_118 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_119 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_181 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_183 = _out_wifireMux_T_2 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_184 = _out_wifireMux_T_183 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_wivalid_77 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_78 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_79 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_80 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_185 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_187 = _out_wifireMux_T_2 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_188 = _out_wifireMux_T_187 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_wivalid_59 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_60 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_61 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_62 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_189 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_191 = _out_wifireMux_T_2 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_192 = _out_wifireMux_T_191 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_wivalid_25 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_26 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_27 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_28 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_193 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_195 = _out_wifireMux_T_2 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_196 = _out_wifireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_199 = _out_wifireMux_T_2 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_200 = _out_wifireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_203 = _out_wifireMux_T_2 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_204 = _out_wifireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_207 = _out_wifireMux_T_2 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_208 = _out_wifireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_211 = _out_wifireMux_T_2 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_212 = _out_wifireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_215 = _out_wifireMux_T_2 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_216 = _out_wifireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_219 = _out_wifireMux_T_2 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_220 = _out_wifireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_223 = _out_wifireMux_T_2 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_224 = _out_wifireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_227 = _out_wifireMux_T_2 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_228 = _out_wifireMux_T_227 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_wivalid_33 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_34 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_35 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_36 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_37 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_38 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_39 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_40 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_41 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_42 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_43 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_44 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_45 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_46 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_47 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_229 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_231 = _out_wifireMux_T_2 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_232 = _out_wifireMux_T_231 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_63 = _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_233 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_235 = _out_wifireMux_T_2 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_236 = _out_wifireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_239 = _out_wifireMux_T_2 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_240 = _out_wifireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_243 = _out_wifireMux_T_2 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_244 = _out_wifireMux_T_243 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_68 = _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_245 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_247 = _out_wifireMux_T_2 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_248 = _out_wifireMux_T_247 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_249 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_251 = _out_wifireMux_T_2 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_252 = _out_wifireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_255 = _out_wifireMux_T_2 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_256 = _out_wifireMux_T_255; // @[RegisterRouter.scala:87:24] wire _GEN_12 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_roready_81 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_21 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_22 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_23 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_24 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_64 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_65 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_66 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_67 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_roready_120 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_121 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_122 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_123 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = _out_rofireMux_T_1 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_35 = _out_rofireMux_T_34 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_18 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_19 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_36 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_38 = _out_rofireMux_T_1 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_39 = _out_rofireMux_T_38 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_42 = _out_rofireMux_T_1 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_43 = _out_rofireMux_T_42 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_roready_29 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_30 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_31 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_44 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_46 = _out_rofireMux_T_1 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_47 = _out_rofireMux_T_46 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_roready_128 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_129 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_130 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_131 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_50 = _out_rofireMux_T_1 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_51 = _out_rofireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_54 = _out_rofireMux_T_1 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_55 = _out_rofireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_58 = _out_rofireMux_T_1 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_59 = _out_rofireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_62 = _out_rofireMux_T_1 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_63 = _out_rofireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = _out_rofireMux_T_1 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67 = _out_rofireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_70 = _out_rofireMux_T_1 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_71 = _out_rofireMux_T_70 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_82 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_83 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_84 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_85 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_86 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_87 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_88 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_89 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_90 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_91 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_92 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_93 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_94 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_95 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_96 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_97 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_98 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_99 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_100 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_72 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_74 = _out_rofireMux_T_1 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_75 = _out_rofireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_78 = _out_rofireMux_T_1 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_79 = _out_rofireMux_T_78 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_roready_145 = _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_80 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_82 = _out_rofireMux_T_1 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83 = _out_rofireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_86 = _out_rofireMux_T_1 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_87 = _out_rofireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_90 = _out_rofireMux_T_1 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_91 = _out_rofireMux_T_90 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_roready_109 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_110 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_111 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_112 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_113 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_114 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_115 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_92 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_94 = _out_rofireMux_T_1 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_95 = _out_rofireMux_T_94 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_roready_140 = _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_96 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_98 = _out_rofireMux_T_1 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_99 = _out_rofireMux_T_98 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_52 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_53 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_54 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_102 = _out_rofireMux_T_1 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_103 = _out_rofireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_106 = _out_rofireMux_T_1 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_107 = _out_rofireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_110 = _out_rofireMux_T_1 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_111 = _out_rofireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_114 = _out_rofireMux_T_1 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_115 = _out_rofireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_118 = _out_rofireMux_T_1 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_119 = _out_rofireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_122 = _out_rofireMux_T_1 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_123 = _out_rofireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_126 = _out_rofireMux_T_1 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_127 = _out_rofireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_130 = _out_rofireMux_T_1 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_131 = _out_rofireMux_T_130 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_roready_101 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_102 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_103 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_104 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_132 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_134 = _out_rofireMux_T_1 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_135 = _out_rofireMux_T_134 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_roready_73 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_74 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_75 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_76 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_136 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_138 = _out_rofireMux_T_1 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_139 = _out_rofireMux_T_138 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_105 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_106 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_107 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_108 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_140 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_142 = _out_rofireMux_T_1 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_143 = _out_rofireMux_T_142 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_144 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_146 = _out_rofireMux_T_1 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_147 = _out_rofireMux_T_146 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_roready_141 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_142 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_143 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_144 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_148 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_150 = _out_rofireMux_T_1 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_151 = _out_rofireMux_T_150 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_roready_55 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_56 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_57 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_58 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_152 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_154 = _out_rofireMux_T_1 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_155 = _out_rofireMux_T_154 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_69 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_70 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_71 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_72 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_156 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_158 = _out_rofireMux_T_1 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_159 = _out_rofireMux_T_158 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_roready_124 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_125 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_126 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_127 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_160 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_162 = _out_rofireMux_T_1 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_163 = _out_rofireMux_T_162 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_roready_136 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_137 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_138 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_139 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_164 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_166 = _out_rofireMux_T_1 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_167 = _out_rofireMux_T_166 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_168 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_170 = _out_rofireMux_T_1 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_171 = _out_rofireMux_T_170 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_roready_48 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_49 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_50 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_51 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_172 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_174 = _out_rofireMux_T_1 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_175 = _out_rofireMux_T_174 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_roready_132 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_133 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_134 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_135 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_176 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_178 = _out_rofireMux_T_1 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_179 = _out_rofireMux_T_178 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_roready_116 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_117 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_118 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_119 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_180 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_182 = _out_rofireMux_T_1 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_183 = _out_rofireMux_T_182 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_77 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_78 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_79 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_80 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_184 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_186 = _out_rofireMux_T_1 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_187 = _out_rofireMux_T_186 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_59 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_60 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_61 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_62 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_188 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_190 = _out_rofireMux_T_1 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_191 = _out_rofireMux_T_190 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_25 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_26 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_27 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_192 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_194 = _out_rofireMux_T_1 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_195 = _out_rofireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_198 = _out_rofireMux_T_1 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_199 = _out_rofireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_202 = _out_rofireMux_T_1 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_203 = _out_rofireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_206 = _out_rofireMux_T_1 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_207 = _out_rofireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_210 = _out_rofireMux_T_1 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_211 = _out_rofireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_214 = _out_rofireMux_T_1 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_215 = _out_rofireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_218 = _out_rofireMux_T_1 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_219 = _out_rofireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_222 = _out_rofireMux_T_1 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_223 = _out_rofireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_226 = _out_rofireMux_T_1 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_227 = _out_rofireMux_T_226 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_33 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_34 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_35 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_36 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_37 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_38 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_39 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_40 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_41 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_42 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_43 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_44 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_45 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_46 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_47 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_228 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_230 = _out_rofireMux_T_1 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_231 = _out_rofireMux_T_230 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_roready_63 = _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_232 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_234 = _out_rofireMux_T_1 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_235 = _out_rofireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_238 = _out_rofireMux_T_1 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_239 = _out_rofireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_242 = _out_rofireMux_T_1 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_243 = _out_rofireMux_T_242 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_roready_68 = _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_244 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_246 = _out_rofireMux_T_1 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_247 = _out_rofireMux_T_246 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_248 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_250 = _out_rofireMux_T_1 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_251 = _out_rofireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_254 = _out_rofireMux_T_1 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_255 = _out_rofireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_woready_81 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_21 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_22 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_23 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_24 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_woready_64 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_65 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_66 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_67 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_woready_120 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_121 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_122 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_123 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = _out_wofireMux_T_2 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_36 = _out_wofireMux_T_35 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_18 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_19 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_37 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_39 = _out_wofireMux_T_2 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_40 = _out_wofireMux_T_39 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_43 = _out_wofireMux_T_2 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_44 = _out_wofireMux_T_43 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_woready_29 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_30 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_31 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_45 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_47 = _out_wofireMux_T_2 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_48 = _out_wofireMux_T_47 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_woready_128 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_129 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_130 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_131 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_51 = _out_wofireMux_T_2 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_52 = _out_wofireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_55 = _out_wofireMux_T_2 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_56 = _out_wofireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_59 = _out_wofireMux_T_2 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_60 = _out_wofireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_63 = _out_wofireMux_T_2 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_64 = _out_wofireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = _out_wofireMux_T_2 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68 = _out_wofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_71 = _out_wofireMux_T_2 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_72 = _out_wofireMux_T_71 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_woready_82 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_83 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_84 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_85 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_86 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_87 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_88 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_89 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_90 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_91 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_92 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_93 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_94 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_95 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_96 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_97 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_98 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_99 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_100 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_73 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_75 = _out_wofireMux_T_2 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_76 = _out_wofireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_79 = _out_wofireMux_T_2 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_80 = _out_wofireMux_T_79 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_woready_145 = _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_81 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_83 = _out_wofireMux_T_2 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84 = _out_wofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_87 = _out_wofireMux_T_2 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_88 = _out_wofireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_91 = _out_wofireMux_T_2 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_92 = _out_wofireMux_T_91 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_woready_109 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_110 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_111 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_112 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_113 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_114 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_115 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_93 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_95 = _out_wofireMux_T_2 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_96 = _out_wofireMux_T_95 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_woready_140 = _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_97 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_99 = _out_wofireMux_T_2 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_100 = _out_wofireMux_T_99 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_woready_52 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_53 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_54 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_103 = _out_wofireMux_T_2 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_104 = _out_wofireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_107 = _out_wofireMux_T_2 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_108 = _out_wofireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_111 = _out_wofireMux_T_2 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_112 = _out_wofireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_115 = _out_wofireMux_T_2 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_116 = _out_wofireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_119 = _out_wofireMux_T_2 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_120 = _out_wofireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_123 = _out_wofireMux_T_2 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_124 = _out_wofireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_127 = _out_wofireMux_T_2 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_128 = _out_wofireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_131 = _out_wofireMux_T_2 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_132 = _out_wofireMux_T_131 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_woready_101 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_102 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_103 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_104 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_133 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_135 = _out_wofireMux_T_2 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_136 = _out_wofireMux_T_135 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_woready_73 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_74 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_75 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_76 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_137 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_139 = _out_wofireMux_T_2 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_140 = _out_wofireMux_T_139 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_woready_105 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_106 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_107 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_108 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_141 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_143 = _out_wofireMux_T_2 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_144 = _out_wofireMux_T_143 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_145 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_147 = _out_wofireMux_T_2 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_148 = _out_wofireMux_T_147 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_woready_141 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_142 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_143 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_144 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_149 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_151 = _out_wofireMux_T_2 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_152 = _out_wofireMux_T_151 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_woready_55 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_56 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_57 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_58 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_153 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_155 = _out_wofireMux_T_2 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_156 = _out_wofireMux_T_155 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_woready_69 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_70 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_71 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_72 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_157 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_159 = _out_wofireMux_T_2 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_160 = _out_wofireMux_T_159 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_woready_124 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_125 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_126 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_127 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_161 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_163 = _out_wofireMux_T_2 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_164 = _out_wofireMux_T_163 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_woready_136 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_137 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_138 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_139 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_165 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_167 = _out_wofireMux_T_2 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_168 = _out_wofireMux_T_167 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_169 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_171 = _out_wofireMux_T_2 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_172 = _out_wofireMux_T_171 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_woready_48 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_49 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_50 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_51 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_173 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_175 = _out_wofireMux_T_2 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_176 = _out_wofireMux_T_175 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_woready_132 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_133 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_134 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_135 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_177 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_179 = _out_wofireMux_T_2 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_180 = _out_wofireMux_T_179 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_woready_116 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_117 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_118 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_119 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_181 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_183 = _out_wofireMux_T_2 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_184 = _out_wofireMux_T_183 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_woready_77 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_78 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_79 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_80 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_185 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_187 = _out_wofireMux_T_2 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_188 = _out_wofireMux_T_187 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_woready_59 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_60 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_61 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_62 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_189 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_191 = _out_wofireMux_T_2 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_192 = _out_wofireMux_T_191 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_woready_25 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_26 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_27 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_193 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_195 = _out_wofireMux_T_2 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_196 = _out_wofireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_199 = _out_wofireMux_T_2 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_200 = _out_wofireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_203 = _out_wofireMux_T_2 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_204 = _out_wofireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_207 = _out_wofireMux_T_2 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_208 = _out_wofireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_211 = _out_wofireMux_T_2 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_212 = _out_wofireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_215 = _out_wofireMux_T_2 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_216 = _out_wofireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_219 = _out_wofireMux_T_2 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_220 = _out_wofireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_223 = _out_wofireMux_T_2 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_224 = _out_wofireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_227 = _out_wofireMux_T_2 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_228 = _out_wofireMux_T_227 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_woready_33 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_34 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_35 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_36 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_37 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_38 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_39 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_40 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_41 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_42 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_43 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_44 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_46 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_47 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_229 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_231 = _out_wofireMux_T_2 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_232 = _out_wofireMux_T_231 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_woready_63 = _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_233 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_235 = _out_wofireMux_T_2 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_236 = _out_wofireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_239 = _out_wofireMux_T_2 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_240 = _out_wofireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_243 = _out_wofireMux_T_2 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_244 = _out_wofireMux_T_243 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_woready_68 = _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_245 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_247 = _out_wofireMux_T_2 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_248 = _out_wofireMux_T_247 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_249 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_251 = _out_wofireMux_T_2 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_252 = _out_wofireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_255 = _out_wofireMux_T_2 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_256 = _out_wofireMux_T_255; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _GEN_13 = {{1'h1}, {1'h1}, {_out_out_bits_data_WIRE_61}, {_out_out_bits_data_WIRE_60}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_57}, {_out_out_bits_data_WIRE_56}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_47}, {_out_out_bits_data_WIRE_46}, {_out_out_bits_data_WIRE_45}, {_out_out_bits_data_WIRE_44}, {_out_out_bits_data_WIRE_43}, {_out_out_bits_data_WIRE_42}, {_out_out_bits_data_WIRE_41}, {_out_out_bits_data_WIRE_40}, {_out_out_bits_data_WIRE_39}, {_out_out_bits_data_WIRE_38}, {_out_out_bits_data_WIRE_37}, {_out_out_bits_data_WIRE_36}, {_out_out_bits_data_WIRE_35}, {_out_out_bits_data_WIRE_34}, {_out_out_bits_data_WIRE_33}, {_out_out_bits_data_WIRE_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_24}, {_out_out_bits_data_WIRE_23}, {_out_out_bits_data_WIRE_22}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_19}, {1'h1}, {_out_out_bits_data_WIRE_17}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_11}, {_out_out_bits_data_WIRE_10}, {_out_out_bits_data_WIRE_9}, {_out_out_bits_data_WIRE_8}, {_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_13[out_oindex]; // @[MuxLiteral.scala:49:10] wire [31:0] _out_out_bits_data_WIRE_1_17 = {9'h0, _out_T_1118}; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_22 = {3'h0, _out_T_1271}; // @[MuxLiteral.scala:49:48] wire [63:0][31:0] _GEN_14 = {{32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_61}, {_out_out_bits_data_WIRE_1_60}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_57}, {_out_out_bits_data_WIRE_1_56}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_47}, {_out_out_bits_data_WIRE_1_46}, {_out_out_bits_data_WIRE_1_45}, {_out_out_bits_data_WIRE_1_44}, {_out_out_bits_data_WIRE_1_43}, {_out_out_bits_data_WIRE_1_42}, {_out_out_bits_data_WIRE_1_41}, {_out_out_bits_data_WIRE_1_40}, {_out_out_bits_data_WIRE_1_39}, {_out_out_bits_data_WIRE_1_38}, {_out_out_bits_data_WIRE_1_37}, {_out_out_bits_data_WIRE_1_36}, {_out_out_bits_data_WIRE_1_35}, {_out_out_bits_data_WIRE_1_34}, {_out_out_bits_data_WIRE_1_33}, {_out_out_bits_data_WIRE_1_32}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_24}, {_out_out_bits_data_WIRE_1_23}, {_out_out_bits_data_WIRE_1_22}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_19}, {32'h0}, {_out_out_bits_data_WIRE_1_17}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_11}, {_out_out_bits_data_WIRE_1_10}, {_out_out_bits_data_WIRE_1_9}, {_out_out_bits_data_WIRE_1_8}, {_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [31:0] _out_out_bits_data_T_3 = _GEN_14[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_size = dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_source = dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg goReg; // @[Debug.scala:1494:27] wire flags_0_go = goReg; // @[Debug.scala:1494:27, :1517:25] wire goAbstract; // @[Debug.scala:1495:32] wire goCustom; // @[Debug.scala:1496:32] wire flags_0_resume; // @[Debug.scala:1517:25] assign flags_0_resume = _flags_resume_T; // @[Debug.scala:1517:25, :1524:80] wire [31:0] _accessRegisterCommandWr_T = {COMMANDWrData_cmdtype, COMMANDWrData_control}; // @[Debug.scala:1280:39, :1531:59] wire [31:0] _accessRegisterCommandWr_WIRE_1 = _accessRegisterCommandWr_T; // @[Debug.scala:1531:{59,74}] wire [7:0] _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] wire [7:0] accessRegisterCommandWr_cmdtype = _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:{44,74}] wire [2:0] _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved0 = _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] wire [2:0] accessRegisterCommandWr_size = _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved1 = _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_postexec = _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_transfer = _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:{44,74}] wire [15:0] _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_write = _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:{44,74}] wire [15:0] accessRegisterCommandWr_regno = _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:{44,74}] assign _accessRegisterCommandWr_T_1 = _accessRegisterCommandWr_WIRE_1[15:0]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_regno = _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_2 = _accessRegisterCommandWr_WIRE_1[16]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_write = _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_3 = _accessRegisterCommandWr_WIRE_1[17]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_transfer = _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_4 = _accessRegisterCommandWr_WIRE_1[18]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_postexec = _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_5 = _accessRegisterCommandWr_WIRE_1[19]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved1 = _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_6 = _accessRegisterCommandWr_WIRE_1[22:20]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_size = _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_7 = _accessRegisterCommandWr_WIRE_1[23]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved0 = _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_8 = _accessRegisterCommandWr_WIRE_1[31:24]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_cmdtype = _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire [31:0] _accessRegisterCommandReg_WIRE_1 = _accessRegisterCommandReg_T; // @[Debug.scala:1533:{56,71}] wire [7:0] _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] wire [7:0] accessRegisterCommandReg_cmdtype = _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:{44,71}] wire [2:0] _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved0 = _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved1 = _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:{44,71}] wire [15:0] _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_write = _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:{44,71}] wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:{44,71}] assign _accessRegisterCommandReg_T_1 = _accessRegisterCommandReg_WIRE_1[15:0]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_regno = _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_2 = _accessRegisterCommandReg_WIRE_1[16]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_write = _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_3 = _accessRegisterCommandReg_WIRE_1[17]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_transfer = _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_4 = _accessRegisterCommandReg_WIRE_1[18]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_postexec = _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_5 = _accessRegisterCommandReg_WIRE_1[19]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved1 = _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_6 = _accessRegisterCommandReg_WIRE_1[22:20]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_size = _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_7 = _accessRegisterCommandReg_WIRE_1[23]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved0 = _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_8 = _accessRegisterCommandReg_WIRE_1[31:24]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_cmdtype = _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire [2:0] abstractGeneratedMem_0_inst_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1589:22] wire [2:0] abstractGeneratedMem_0_inst_1_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1601:22] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35] wire [31:0] _out_T_8286 = abstractGeneratedMem_0; // @[RegisterRouter.scala:87:24] reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35] wire [4:0] abstractGeneratedMem_0_inst_rd; // @[Debug.scala:1589:22] wire [15:0] _GEN_15 = {11'h0, accessRegisterCommandReg_regno[4:0]}; // @[Debug.scala:1533:44, :1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rd_T; // @[Debug.scala:1593:54] assign _abstractGeneratedMem_0_inst_rd_T = _GEN_15; // @[Debug.scala:1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rs2_T; // @[Debug.scala:1608:54] assign _abstractGeneratedMem_0_inst_rs2_T = _GEN_15; // @[Debug.scala:1593:54, :1608:54] assign abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala:1589:22, :1593:{19,54}] wire [11:0] abstractGeneratedMem_0_lo = {abstractGeneratedMem_0_inst_rd, 7'h3}; // @[Debug.scala:1589:22, :1597:12] wire [19:0] abstractGeneratedMem_0_hi = {17'h7000, abstractGeneratedMem_0_inst_funct3}; // @[Debug.scala:1589:22, :1597:12] wire [31:0] _abstractGeneratedMem_0_T = {abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo}; // @[Debug.scala:1597:12] wire [4:0] abstractGeneratedMem_0_inst_1_rs2; // @[Debug.scala:1601:22] assign abstractGeneratedMem_0_inst_1_rs2 = _abstractGeneratedMem_0_inst_rs2_T[4:0]; // @[Debug.scala:1601:22, :1608:{19,54}] wire [7:0] abstractGeneratedMem_0_lo_hi = {abstractGeneratedMem_0_inst_1_funct3, 5'h0}; // @[Debug.scala:1601:22, :1610:12] wire [14:0] abstractGeneratedMem_0_lo_1 = {abstractGeneratedMem_0_lo_hi, 7'h23}; // @[Debug.scala:1610:12] wire [11:0] abstractGeneratedMem_0_hi_hi_1 = {7'h1C, abstractGeneratedMem_0_inst_1_rs2}; // @[Debug.scala:1601:22, :1610:12] wire [16:0] abstractGeneratedMem_0_hi_1 = {abstractGeneratedMem_0_hi_hi_1, 5'h0}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_1 = {abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_2 = accessRegisterCommandReg_write ? _abstractGeneratedMem_0_T : _abstractGeneratedMem_0_T_1; // @[Debug.scala:1533:44, :1597:12, :1610:12, :1641:14] wire [31:0] _abstractGeneratedMem_0_T_4 = accessRegisterCommandReg_transfer ? _abstractGeneratedMem_0_T_2 : 32'h13; // @[Debug.scala:1533:44, :1640:39, :1641:14] wire [31:0] _abstractGeneratedMem_1_T_1 = accessRegisterCommandReg_postexec ? 32'h13 : 32'h100073; // @[Debug.scala:1533:44, :1644:39] wire [6:0] _GEN_16 = {6'h0, flags_0_resume}; // @[Debug.scala:1517:25, :1702:60] wire [6:0] hi_1; // @[Debug.scala:1702:60] assign hi_1 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_2; // @[Debug.scala:1702:60] assign hi_2 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_3; // @[Debug.scala:1702:60] assign hi_3 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_4; // @[Debug.scala:1702:60] assign hi_4 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_5; // @[Debug.scala:1702:60] assign hi_5 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_6; // @[Debug.scala:1702:60] assign hi_6 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_7; // @[Debug.scala:1702:60] assign hi_7 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_8; // @[Debug.scala:1702:60] assign hi_8 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_9; // @[Debug.scala:1702:60] assign hi_9 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_10; // @[Debug.scala:1702:60] assign hi_10 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_11; // @[Debug.scala:1702:60] assign hi_11 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_12; // @[Debug.scala:1702:60] assign hi_12 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_13; // @[Debug.scala:1702:60] assign hi_13 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_14; // @[Debug.scala:1702:60] assign hi_14 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_15; // @[Debug.scala:1702:60] assign hi_15 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_16; // @[Debug.scala:1702:60] assign hi_16 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_17; // @[Debug.scala:1702:60] assign hi_17 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_18; // @[Debug.scala:1702:60] assign hi_18 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_19; // @[Debug.scala:1702:60] assign hi_19 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_20; // @[Debug.scala:1702:60] assign hi_20 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_21; // @[Debug.scala:1702:60] assign hi_21 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_22; // @[Debug.scala:1702:60] assign hi_22 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_23; // @[Debug.scala:1702:60] assign hi_23 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_24; // @[Debug.scala:1702:60] assign hi_24 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_25; // @[Debug.scala:1702:60] assign hi_25 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_26; // @[Debug.scala:1702:60] assign hi_26 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_27; // @[Debug.scala:1702:60] assign hi_27 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_28; // @[Debug.scala:1702:60] assign hi_28 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_29; // @[Debug.scala:1702:60] assign hi_29 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_30; // @[Debug.scala:1702:60] assign hi_30 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_31; // @[Debug.scala:1702:60] assign hi_31 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_32; // @[Debug.scala:1702:60] assign hi_32 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_33; // @[Debug.scala:1702:60] assign hi_33 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_34; // @[Debug.scala:1702:60] assign hi_34 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_35; // @[Debug.scala:1702:60] assign hi_35 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_36; // @[Debug.scala:1702:60] assign hi_36 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_37; // @[Debug.scala:1702:60] assign hi_37 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_38; // @[Debug.scala:1702:60] assign hi_38 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_39; // @[Debug.scala:1702:60] assign hi_39 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_40; // @[Debug.scala:1702:60] assign hi_40 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_41; // @[Debug.scala:1702:60] assign hi_41 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_42; // @[Debug.scala:1702:60] assign hi_42 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_43; // @[Debug.scala:1702:60] assign hi_43 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_44; // @[Debug.scala:1702:60] assign hi_44 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_45; // @[Debug.scala:1702:60] assign hi_45 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_46; // @[Debug.scala:1702:60] assign hi_46 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_47; // @[Debug.scala:1702:60] assign hi_47 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_48; // @[Debug.scala:1702:60] assign hi_48 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_49; // @[Debug.scala:1702:60] assign hi_49 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_50; // @[Debug.scala:1702:60] assign hi_50 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_51; // @[Debug.scala:1702:60] assign hi_51 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_52; // @[Debug.scala:1702:60] assign hi_52 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_53; // @[Debug.scala:1702:60] assign hi_53 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_54; // @[Debug.scala:1702:60] assign hi_54 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_55; // @[Debug.scala:1702:60] assign hi_55 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_56; // @[Debug.scala:1702:60] assign hi_56 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_57; // @[Debug.scala:1702:60] assign hi_57 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_58; // @[Debug.scala:1702:60] assign hi_58 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_59; // @[Debug.scala:1702:60] assign hi_59 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_60; // @[Debug.scala:1702:60] assign hi_60 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_61; // @[Debug.scala:1702:60] assign hi_61 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_62; // @[Debug.scala:1702:60] assign hi_62 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_63; // @[Debug.scala:1702:60] assign hi_63 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_64; // @[Debug.scala:1702:60] assign hi_64 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_65; // @[Debug.scala:1702:60] assign hi_65 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_66; // @[Debug.scala:1702:60] assign hi_66 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_67; // @[Debug.scala:1702:60] assign hi_67 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_68; // @[Debug.scala:1702:60] assign hi_68 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_69; // @[Debug.scala:1702:60] assign hi_69 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_70; // @[Debug.scala:1702:60] assign hi_70 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_71; // @[Debug.scala:1702:60] assign hi_71 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_72; // @[Debug.scala:1702:60] assign hi_72 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_73; // @[Debug.scala:1702:60] assign hi_73 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_74; // @[Debug.scala:1702:60] assign hi_74 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_75; // @[Debug.scala:1702:60] assign hi_75 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_76; // @[Debug.scala:1702:60] assign hi_76 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_77; // @[Debug.scala:1702:60] assign hi_77 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_78; // @[Debug.scala:1702:60] assign hi_78 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_79; // @[Debug.scala:1702:60] assign hi_79 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_80; // @[Debug.scala:1702:60] assign hi_80 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_81; // @[Debug.scala:1702:60] assign hi_81 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_82; // @[Debug.scala:1702:60] assign hi_82 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_83; // @[Debug.scala:1702:60] assign hi_83 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_84; // @[Debug.scala:1702:60] assign hi_84 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_85; // @[Debug.scala:1702:60] assign hi_85 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_86; // @[Debug.scala:1702:60] assign hi_86 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_87; // @[Debug.scala:1702:60] assign hi_87 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_88; // @[Debug.scala:1702:60] assign hi_88 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_89; // @[Debug.scala:1702:60] assign hi_89 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_90; // @[Debug.scala:1702:60] assign hi_90 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_91; // @[Debug.scala:1702:60] assign hi_91 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_92; // @[Debug.scala:1702:60] assign hi_92 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_93; // @[Debug.scala:1702:60] assign hi_93 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_94; // @[Debug.scala:1702:60] assign hi_94 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_95; // @[Debug.scala:1702:60] assign hi_95 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_96; // @[Debug.scala:1702:60] assign hi_96 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_97; // @[Debug.scala:1702:60] assign hi_97 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_98; // @[Debug.scala:1702:60] assign hi_98 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_99; // @[Debug.scala:1702:60] assign hi_99 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_100; // @[Debug.scala:1702:60] assign hi_100 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_101; // @[Debug.scala:1702:60] assign hi_101 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_102; // @[Debug.scala:1702:60] assign hi_102 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_103; // @[Debug.scala:1702:60] assign hi_103 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_104; // @[Debug.scala:1702:60] assign hi_104 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_105; // @[Debug.scala:1702:60] assign hi_105 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_106; // @[Debug.scala:1702:60] assign hi_106 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_107; // @[Debug.scala:1702:60] assign hi_107 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_108; // @[Debug.scala:1702:60] assign hi_108 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_109; // @[Debug.scala:1702:60] assign hi_109 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_110; // @[Debug.scala:1702:60] assign hi_110 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_111; // @[Debug.scala:1702:60] assign hi_111 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_112; // @[Debug.scala:1702:60] assign hi_112 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_113; // @[Debug.scala:1702:60] assign hi_113 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_114; // @[Debug.scala:1702:60] assign hi_114 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_115; // @[Debug.scala:1702:60] assign hi_115 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_116; // @[Debug.scala:1702:60] assign hi_116 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_117; // @[Debug.scala:1702:60] assign hi_117 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_118; // @[Debug.scala:1702:60] assign hi_118 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_119; // @[Debug.scala:1702:60] assign hi_119 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_120; // @[Debug.scala:1702:60] assign hi_120 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_121; // @[Debug.scala:1702:60] assign hi_121 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_122; // @[Debug.scala:1702:60] assign hi_122 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_123; // @[Debug.scala:1702:60] assign hi_123 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_124; // @[Debug.scala:1702:60] assign hi_124 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_125; // @[Debug.scala:1702:60] assign hi_125 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_126; // @[Debug.scala:1702:60] assign hi_126 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_127; // @[Debug.scala:1702:60] assign hi_127 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_128; // @[Debug.scala:1702:60] assign hi_128 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_129; // @[Debug.scala:1702:60] assign hi_129 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_130; // @[Debug.scala:1702:60] assign hi_130 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_131; // @[Debug.scala:1702:60] assign hi_131 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_132; // @[Debug.scala:1702:60] assign hi_132 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_133; // @[Debug.scala:1702:60] assign hi_133 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_134; // @[Debug.scala:1702:60] assign hi_134 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_135; // @[Debug.scala:1702:60] assign hi_135 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_136; // @[Debug.scala:1702:60] assign hi_136 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_137; // @[Debug.scala:1702:60] assign hi_137 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_138; // @[Debug.scala:1702:60] assign hi_138 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_139; // @[Debug.scala:1702:60] assign hi_139 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_140; // @[Debug.scala:1702:60] assign hi_140 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_141; // @[Debug.scala:1702:60] assign hi_141 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_142; // @[Debug.scala:1702:60] assign hi_142 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_143; // @[Debug.scala:1702:60] assign hi_143 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_144; // @[Debug.scala:1702:60] assign hi_144 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_145; // @[Debug.scala:1702:60] assign hi_145 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_146; // @[Debug.scala:1702:60] assign hi_146 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_147; // @[Debug.scala:1702:60] assign hi_147 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_148; // @[Debug.scala:1702:60] assign hi_148 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_149; // @[Debug.scala:1702:60] assign hi_149 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_150; // @[Debug.scala:1702:60] assign hi_150 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_151; // @[Debug.scala:1702:60] assign hi_151 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_152; // @[Debug.scala:1702:60] assign hi_152 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_153; // @[Debug.scala:1702:60] assign hi_153 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_154; // @[Debug.scala:1702:60] assign hi_154 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_155; // @[Debug.scala:1702:60] assign hi_155 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_156; // @[Debug.scala:1702:60] assign hi_156 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_157; // @[Debug.scala:1702:60] assign hi_157 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_158; // @[Debug.scala:1702:60] assign hi_158 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_159; // @[Debug.scala:1702:60] assign hi_159 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_160; // @[Debug.scala:1702:60] assign hi_160 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_161; // @[Debug.scala:1702:60] assign hi_161 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_162; // @[Debug.scala:1702:60] assign hi_162 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_163; // @[Debug.scala:1702:60] assign hi_163 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_164; // @[Debug.scala:1702:60] assign hi_164 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_165; // @[Debug.scala:1702:60] assign hi_165 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_166; // @[Debug.scala:1702:60] assign hi_166 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_167; // @[Debug.scala:1702:60] assign hi_167 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_168; // @[Debug.scala:1702:60] assign hi_168 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_169; // @[Debug.scala:1702:60] assign hi_169 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_170; // @[Debug.scala:1702:60] assign hi_170 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_171; // @[Debug.scala:1702:60] assign hi_171 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_172; // @[Debug.scala:1702:60] assign hi_172 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_173; // @[Debug.scala:1702:60] assign hi_173 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_174; // @[Debug.scala:1702:60] assign hi_174 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_175; // @[Debug.scala:1702:60] assign hi_175 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_176; // @[Debug.scala:1702:60] assign hi_176 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_177; // @[Debug.scala:1702:60] assign hi_177 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_178; // @[Debug.scala:1702:60] assign hi_178 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_179; // @[Debug.scala:1702:60] assign hi_179 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_180; // @[Debug.scala:1702:60] assign hi_180 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_181; // @[Debug.scala:1702:60] assign hi_181 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_182; // @[Debug.scala:1702:60] assign hi_182 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_183; // @[Debug.scala:1702:60] assign hi_183 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_184; // @[Debug.scala:1702:60] assign hi_184 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_185; // @[Debug.scala:1702:60] assign hi_185 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_186; // @[Debug.scala:1702:60] assign hi_186 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_187; // @[Debug.scala:1702:60] assign hi_187 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_188; // @[Debug.scala:1702:60] assign hi_188 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_189; // @[Debug.scala:1702:60] assign hi_189 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_190; // @[Debug.scala:1702:60] assign hi_190 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_191; // @[Debug.scala:1702:60] assign hi_191 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_192; // @[Debug.scala:1702:60] assign hi_192 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_193; // @[Debug.scala:1702:60] assign hi_193 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_194; // @[Debug.scala:1702:60] assign hi_194 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_195; // @[Debug.scala:1702:60] assign hi_195 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_196; // @[Debug.scala:1702:60] assign hi_196 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_197; // @[Debug.scala:1702:60] assign hi_197 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_198; // @[Debug.scala:1702:60] assign hi_198 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_199; // @[Debug.scala:1702:60] assign hi_199 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_200; // @[Debug.scala:1702:60] assign hi_200 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_201; // @[Debug.scala:1702:60] assign hi_201 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_202; // @[Debug.scala:1702:60] assign hi_202 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_203; // @[Debug.scala:1702:60] assign hi_203 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_204; // @[Debug.scala:1702:60] assign hi_204 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_205; // @[Debug.scala:1702:60] assign hi_205 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_206; // @[Debug.scala:1702:60] assign hi_206 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_207; // @[Debug.scala:1702:60] assign hi_207 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_208; // @[Debug.scala:1702:60] assign hi_208 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_209; // @[Debug.scala:1702:60] assign hi_209 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_210; // @[Debug.scala:1702:60] assign hi_210 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_211; // @[Debug.scala:1702:60] assign hi_211 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_212; // @[Debug.scala:1702:60] assign hi_212 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_213; // @[Debug.scala:1702:60] assign hi_213 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_214; // @[Debug.scala:1702:60] assign hi_214 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_215; // @[Debug.scala:1702:60] assign hi_215 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_216; // @[Debug.scala:1702:60] assign hi_216 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_217; // @[Debug.scala:1702:60] assign hi_217 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_218; // @[Debug.scala:1702:60] assign hi_218 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_219; // @[Debug.scala:1702:60] assign hi_219 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_220; // @[Debug.scala:1702:60] assign hi_220 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_221; // @[Debug.scala:1702:60] assign hi_221 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_222; // @[Debug.scala:1702:60] assign hi_222 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_223; // @[Debug.scala:1702:60] assign hi_223 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_224; // @[Debug.scala:1702:60] assign hi_224 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_225; // @[Debug.scala:1702:60] assign hi_225 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_226; // @[Debug.scala:1702:60] assign hi_226 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_227; // @[Debug.scala:1702:60] assign hi_227 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_228; // @[Debug.scala:1702:60] assign hi_228 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_229; // @[Debug.scala:1702:60] assign hi_229 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_230; // @[Debug.scala:1702:60] assign hi_230 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_231; // @[Debug.scala:1702:60] assign hi_231 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_232; // @[Debug.scala:1702:60] assign hi_232 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_233; // @[Debug.scala:1702:60] assign hi_233 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_234; // @[Debug.scala:1702:60] assign hi_234 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_235; // @[Debug.scala:1702:60] assign hi_235 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_236; // @[Debug.scala:1702:60] assign hi_236 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_237; // @[Debug.scala:1702:60] assign hi_237 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_238; // @[Debug.scala:1702:60] assign hi_238 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_239; // @[Debug.scala:1702:60] assign hi_239 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_240; // @[Debug.scala:1702:60] assign hi_240 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_241; // @[Debug.scala:1702:60] assign hi_241 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_242; // @[Debug.scala:1702:60] assign hi_242 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_243; // @[Debug.scala:1702:60] assign hi_243 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_244; // @[Debug.scala:1702:60] assign hi_244 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_245; // @[Debug.scala:1702:60] assign hi_245 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_246; // @[Debug.scala:1702:60] assign hi_246 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_247; // @[Debug.scala:1702:60] assign hi_247 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_248; // @[Debug.scala:1702:60] assign hi_248 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_249; // @[Debug.scala:1702:60] assign hi_249 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_250; // @[Debug.scala:1702:60] assign hi_250 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_251; // @[Debug.scala:1702:60] assign hi_251 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_252; // @[Debug.scala:1702:60] assign hi_252 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_253; // @[Debug.scala:1702:60] assign hi_253 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_254; // @[Debug.scala:1702:60] assign hi_254 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_255; // @[Debug.scala:1702:60] assign hi_255 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_256; // @[Debug.scala:1702:60] assign hi_256 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_257; // @[Debug.scala:1702:60] assign hi_257 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_258; // @[Debug.scala:1702:60] assign hi_258 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_259; // @[Debug.scala:1702:60] assign hi_259 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_260; // @[Debug.scala:1702:60] assign hi_260 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_261; // @[Debug.scala:1702:60] assign hi_261 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_262; // @[Debug.scala:1702:60] assign hi_262 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_263; // @[Debug.scala:1702:60] assign hi_263 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_264; // @[Debug.scala:1702:60] assign hi_264 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_265; // @[Debug.scala:1702:60] assign hi_265 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_266; // @[Debug.scala:1702:60] assign hi_266 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_267; // @[Debug.scala:1702:60] assign hi_267 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_268; // @[Debug.scala:1702:60] assign hi_268 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_269; // @[Debug.scala:1702:60] assign hi_269 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_270; // @[Debug.scala:1702:60] assign hi_270 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_271; // @[Debug.scala:1702:60] assign hi_271 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_272; // @[Debug.scala:1702:60] assign hi_272 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_273; // @[Debug.scala:1702:60] assign hi_273 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_274; // @[Debug.scala:1702:60] assign hi_274 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_275; // @[Debug.scala:1702:60] assign hi_275 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_276; // @[Debug.scala:1702:60] assign hi_276 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_277; // @[Debug.scala:1702:60] assign hi_277 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_278; // @[Debug.scala:1702:60] assign hi_278 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_279; // @[Debug.scala:1702:60] assign hi_279 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_280; // @[Debug.scala:1702:60] assign hi_280 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_281; // @[Debug.scala:1702:60] assign hi_281 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_282; // @[Debug.scala:1702:60] assign hi_282 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_283; // @[Debug.scala:1702:60] assign hi_283 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_284; // @[Debug.scala:1702:60] assign hi_284 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_285; // @[Debug.scala:1702:60] assign hi_285 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_286; // @[Debug.scala:1702:60] assign hi_286 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_287; // @[Debug.scala:1702:60] assign hi_287 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_288; // @[Debug.scala:1702:60] assign hi_288 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_289; // @[Debug.scala:1702:60] assign hi_289 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_290; // @[Debug.scala:1702:60] assign hi_290 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_291; // @[Debug.scala:1702:60] assign hi_291 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_292; // @[Debug.scala:1702:60] assign hi_292 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_293; // @[Debug.scala:1702:60] assign hi_293 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_294; // @[Debug.scala:1702:60] assign hi_294 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_295; // @[Debug.scala:1702:60] assign hi_295 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_296; // @[Debug.scala:1702:60] assign hi_296 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_297; // @[Debug.scala:1702:60] assign hi_297 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_298; // @[Debug.scala:1702:60] assign hi_298 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_299; // @[Debug.scala:1702:60] assign hi_299 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_300; // @[Debug.scala:1702:60] assign hi_300 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_301; // @[Debug.scala:1702:60] assign hi_301 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_302; // @[Debug.scala:1702:60] assign hi_302 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_303; // @[Debug.scala:1702:60] assign hi_303 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_304; // @[Debug.scala:1702:60] assign hi_304 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_305; // @[Debug.scala:1702:60] assign hi_305 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_306; // @[Debug.scala:1702:60] assign hi_306 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_307; // @[Debug.scala:1702:60] assign hi_307 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_308; // @[Debug.scala:1702:60] assign hi_308 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_309; // @[Debug.scala:1702:60] assign hi_309 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_310; // @[Debug.scala:1702:60] assign hi_310 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_311; // @[Debug.scala:1702:60] assign hi_311 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_312; // @[Debug.scala:1702:60] assign hi_312 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_313; // @[Debug.scala:1702:60] assign hi_313 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_314; // @[Debug.scala:1702:60] assign hi_314 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_315; // @[Debug.scala:1702:60] assign hi_315 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_316; // @[Debug.scala:1702:60] assign hi_316 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_317; // @[Debug.scala:1702:60] assign hi_317 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_318; // @[Debug.scala:1702:60] assign hi_318 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_319; // @[Debug.scala:1702:60] assign hi_319 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_320; // @[Debug.scala:1702:60] assign hi_320 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_321; // @[Debug.scala:1702:60] assign hi_321 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_322; // @[Debug.scala:1702:60] assign hi_322 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_323; // @[Debug.scala:1702:60] assign hi_323 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_324; // @[Debug.scala:1702:60] assign hi_324 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_325; // @[Debug.scala:1702:60] assign hi_325 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_326; // @[Debug.scala:1702:60] assign hi_326 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_327; // @[Debug.scala:1702:60] assign hi_327 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_328; // @[Debug.scala:1702:60] assign hi_328 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_329; // @[Debug.scala:1702:60] assign hi_329 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_330; // @[Debug.scala:1702:60] assign hi_330 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_331; // @[Debug.scala:1702:60] assign hi_331 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_332; // @[Debug.scala:1702:60] assign hi_332 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_333; // @[Debug.scala:1702:60] assign hi_333 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_334; // @[Debug.scala:1702:60] assign hi_334 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_335; // @[Debug.scala:1702:60] assign hi_335 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_336; // @[Debug.scala:1702:60] assign hi_336 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_337; // @[Debug.scala:1702:60] assign hi_337 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_338; // @[Debug.scala:1702:60] assign hi_338 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_339; // @[Debug.scala:1702:60] assign hi_339 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_340; // @[Debug.scala:1702:60] assign hi_340 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_341; // @[Debug.scala:1702:60] assign hi_341 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_342; // @[Debug.scala:1702:60] assign hi_342 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_343; // @[Debug.scala:1702:60] assign hi_343 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_344; // @[Debug.scala:1702:60] assign hi_344 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_345; // @[Debug.scala:1702:60] assign hi_345 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_346; // @[Debug.scala:1702:60] assign hi_346 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_347; // @[Debug.scala:1702:60] assign hi_347 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_348; // @[Debug.scala:1702:60] assign hi_348 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_349; // @[Debug.scala:1702:60] assign hi_349 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_350; // @[Debug.scala:1702:60] assign hi_350 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_351; // @[Debug.scala:1702:60] assign hi_351 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_352; // @[Debug.scala:1702:60] assign hi_352 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_353; // @[Debug.scala:1702:60] assign hi_353 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_354; // @[Debug.scala:1702:60] assign hi_354 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_355; // @[Debug.scala:1702:60] assign hi_355 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_356; // @[Debug.scala:1702:60] assign hi_356 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_357; // @[Debug.scala:1702:60] assign hi_357 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_358; // @[Debug.scala:1702:60] assign hi_358 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_359; // @[Debug.scala:1702:60] assign hi_359 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_360; // @[Debug.scala:1702:60] assign hi_360 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_361; // @[Debug.scala:1702:60] assign hi_361 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_362; // @[Debug.scala:1702:60] assign hi_362 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_363; // @[Debug.scala:1702:60] assign hi_363 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_364; // @[Debug.scala:1702:60] assign hi_364 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_365; // @[Debug.scala:1702:60] assign hi_365 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_366; // @[Debug.scala:1702:60] assign hi_366 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_367; // @[Debug.scala:1702:60] assign hi_367 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_368; // @[Debug.scala:1702:60] assign hi_368 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_369; // @[Debug.scala:1702:60] assign hi_369 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_370; // @[Debug.scala:1702:60] assign hi_370 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_371; // @[Debug.scala:1702:60] assign hi_371 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_372; // @[Debug.scala:1702:60] assign hi_372 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_373; // @[Debug.scala:1702:60] assign hi_373 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_374; // @[Debug.scala:1702:60] assign hi_374 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_375; // @[Debug.scala:1702:60] assign hi_375 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_376; // @[Debug.scala:1702:60] assign hi_376 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_377; // @[Debug.scala:1702:60] assign hi_377 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_378; // @[Debug.scala:1702:60] assign hi_378 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_379; // @[Debug.scala:1702:60] assign hi_379 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_380; // @[Debug.scala:1702:60] assign hi_380 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_381; // @[Debug.scala:1702:60] assign hi_381 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_382; // @[Debug.scala:1702:60] assign hi_382 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_383; // @[Debug.scala:1702:60] assign hi_383 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_384; // @[Debug.scala:1702:60] assign hi_384 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_385; // @[Debug.scala:1702:60] assign hi_385 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_386; // @[Debug.scala:1702:60] assign hi_386 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_387; // @[Debug.scala:1702:60] assign hi_387 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_388; // @[Debug.scala:1702:60] assign hi_388 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_389; // @[Debug.scala:1702:60] assign hi_389 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_390; // @[Debug.scala:1702:60] assign hi_390 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_391; // @[Debug.scala:1702:60] assign hi_391 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_392; // @[Debug.scala:1702:60] assign hi_392 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_393; // @[Debug.scala:1702:60] assign hi_393 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_394; // @[Debug.scala:1702:60] assign hi_394 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_395; // @[Debug.scala:1702:60] assign hi_395 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_396; // @[Debug.scala:1702:60] assign hi_396 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_397; // @[Debug.scala:1702:60] assign hi_397 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_398; // @[Debug.scala:1702:60] assign hi_398 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_399; // @[Debug.scala:1702:60] assign hi_399 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_400; // @[Debug.scala:1702:60] assign hi_400 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_401; // @[Debug.scala:1702:60] assign hi_401 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_402; // @[Debug.scala:1702:60] assign hi_402 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_403; // @[Debug.scala:1702:60] assign hi_403 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_404; // @[Debug.scala:1702:60] assign hi_404 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_405; // @[Debug.scala:1702:60] assign hi_405 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_406; // @[Debug.scala:1702:60] assign hi_406 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_407; // @[Debug.scala:1702:60] assign hi_407 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_408; // @[Debug.scala:1702:60] assign hi_408 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_409; // @[Debug.scala:1702:60] assign hi_409 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_410; // @[Debug.scala:1702:60] assign hi_410 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_411; // @[Debug.scala:1702:60] assign hi_411 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_412; // @[Debug.scala:1702:60] assign hi_412 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_413; // @[Debug.scala:1702:60] assign hi_413 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_414; // @[Debug.scala:1702:60] assign hi_414 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_415; // @[Debug.scala:1702:60] assign hi_415 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_416; // @[Debug.scala:1702:60] assign hi_416 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_417; // @[Debug.scala:1702:60] assign hi_417 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_418; // @[Debug.scala:1702:60] assign hi_418 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_419; // @[Debug.scala:1702:60] assign hi_419 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_420; // @[Debug.scala:1702:60] assign hi_420 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_421; // @[Debug.scala:1702:60] assign hi_421 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_422; // @[Debug.scala:1702:60] assign hi_422 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_423; // @[Debug.scala:1702:60] assign hi_423 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_424; // @[Debug.scala:1702:60] assign hi_424 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_425; // @[Debug.scala:1702:60] assign hi_425 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_426; // @[Debug.scala:1702:60] assign hi_426 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_427; // @[Debug.scala:1702:60] assign hi_427 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_428; // @[Debug.scala:1702:60] assign hi_428 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_429; // @[Debug.scala:1702:60] assign hi_429 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_430; // @[Debug.scala:1702:60] assign hi_430 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_431; // @[Debug.scala:1702:60] assign hi_431 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_432; // @[Debug.scala:1702:60] assign hi_432 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_433; // @[Debug.scala:1702:60] assign hi_433 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_434; // @[Debug.scala:1702:60] assign hi_434 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_435; // @[Debug.scala:1702:60] assign hi_435 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_436; // @[Debug.scala:1702:60] assign hi_436 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_437; // @[Debug.scala:1702:60] assign hi_437 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_438; // @[Debug.scala:1702:60] assign hi_438 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_439; // @[Debug.scala:1702:60] assign hi_439 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_440; // @[Debug.scala:1702:60] assign hi_440 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_441; // @[Debug.scala:1702:60] assign hi_441 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_442; // @[Debug.scala:1702:60] assign hi_442 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_443; // @[Debug.scala:1702:60] assign hi_443 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_444; // @[Debug.scala:1702:60] assign hi_444 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_445; // @[Debug.scala:1702:60] assign hi_445 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_446; // @[Debug.scala:1702:60] assign hi_446 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_447; // @[Debug.scala:1702:60] assign hi_447 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_448; // @[Debug.scala:1702:60] assign hi_448 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_449; // @[Debug.scala:1702:60] assign hi_449 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_450; // @[Debug.scala:1702:60] assign hi_450 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_451; // @[Debug.scala:1702:60] assign hi_451 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_452; // @[Debug.scala:1702:60] assign hi_452 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_453; // @[Debug.scala:1702:60] assign hi_453 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_454; // @[Debug.scala:1702:60] assign hi_454 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_455; // @[Debug.scala:1702:60] assign hi_455 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_456; // @[Debug.scala:1702:60] assign hi_456 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_457; // @[Debug.scala:1702:60] assign hi_457 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_458; // @[Debug.scala:1702:60] assign hi_458 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_459; // @[Debug.scala:1702:60] assign hi_459 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_460; // @[Debug.scala:1702:60] assign hi_460 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_461; // @[Debug.scala:1702:60] assign hi_461 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_462; // @[Debug.scala:1702:60] assign hi_462 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_463; // @[Debug.scala:1702:60] assign hi_463 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_464; // @[Debug.scala:1702:60] assign hi_464 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_465; // @[Debug.scala:1702:60] assign hi_465 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_466; // @[Debug.scala:1702:60] assign hi_466 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_467; // @[Debug.scala:1702:60] assign hi_467 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_468; // @[Debug.scala:1702:60] assign hi_468 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_469; // @[Debug.scala:1702:60] assign hi_469 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_470; // @[Debug.scala:1702:60] assign hi_470 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_471; // @[Debug.scala:1702:60] assign hi_471 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_472; // @[Debug.scala:1702:60] assign hi_472 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_473; // @[Debug.scala:1702:60] assign hi_473 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_474; // @[Debug.scala:1702:60] assign hi_474 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_475; // @[Debug.scala:1702:60] assign hi_475 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_476; // @[Debug.scala:1702:60] assign hi_476 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_477; // @[Debug.scala:1702:60] assign hi_477 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_478; // @[Debug.scala:1702:60] assign hi_478 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_479; // @[Debug.scala:1702:60] assign hi_479 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_480; // @[Debug.scala:1702:60] assign hi_480 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_481; // @[Debug.scala:1702:60] assign hi_481 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_482; // @[Debug.scala:1702:60] assign hi_482 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_483; // @[Debug.scala:1702:60] assign hi_483 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_484; // @[Debug.scala:1702:60] assign hi_484 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_485; // @[Debug.scala:1702:60] assign hi_485 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_486; // @[Debug.scala:1702:60] assign hi_486 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_487; // @[Debug.scala:1702:60] assign hi_487 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_488; // @[Debug.scala:1702:60] assign hi_488 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_489; // @[Debug.scala:1702:60] assign hi_489 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_490; // @[Debug.scala:1702:60] assign hi_490 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_491; // @[Debug.scala:1702:60] assign hi_491 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_492; // @[Debug.scala:1702:60] assign hi_492 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_493; // @[Debug.scala:1702:60] assign hi_493 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_494; // @[Debug.scala:1702:60] assign hi_494 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_495; // @[Debug.scala:1702:60] assign hi_495 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_496; // @[Debug.scala:1702:60] assign hi_496 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_497; // @[Debug.scala:1702:60] assign hi_497 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_498; // @[Debug.scala:1702:60] assign hi_498 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_499; // @[Debug.scala:1702:60] assign hi_499 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_500; // @[Debug.scala:1702:60] assign hi_500 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_501; // @[Debug.scala:1702:60] assign hi_501 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_502; // @[Debug.scala:1702:60] assign hi_502 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_503; // @[Debug.scala:1702:60] assign hi_503 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_504; // @[Debug.scala:1702:60] assign hi_504 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_505; // @[Debug.scala:1702:60] assign hi_505 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_506; // @[Debug.scala:1702:60] assign hi_506 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_507; // @[Debug.scala:1702:60] assign hi_507 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_508; // @[Debug.scala:1702:60] assign hi_508 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_509; // @[Debug.scala:1702:60] assign hi_509 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_510; // @[Debug.scala:1702:60] assign hi_510 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_511; // @[Debug.scala:1702:60] assign hi_511 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_512; // @[Debug.scala:1702:60] assign hi_512 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_513; // @[Debug.scala:1702:60] assign hi_513 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_514; // @[Debug.scala:1702:60] assign hi_514 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_515; // @[Debug.scala:1702:60] assign hi_515 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_516; // @[Debug.scala:1702:60] assign hi_516 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_517; // @[Debug.scala:1702:60] assign hi_517 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_518; // @[Debug.scala:1702:60] assign hi_518 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_519; // @[Debug.scala:1702:60] assign hi_519 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_520; // @[Debug.scala:1702:60] assign hi_520 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_521; // @[Debug.scala:1702:60] assign hi_521 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_522; // @[Debug.scala:1702:60] assign hi_522 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_523; // @[Debug.scala:1702:60] assign hi_523 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_524; // @[Debug.scala:1702:60] assign hi_524 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_525; // @[Debug.scala:1702:60] assign hi_525 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_526; // @[Debug.scala:1702:60] assign hi_526 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_527; // @[Debug.scala:1702:60] assign hi_527 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_528; // @[Debug.scala:1702:60] assign hi_528 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_529; // @[Debug.scala:1702:60] assign hi_529 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_530; // @[Debug.scala:1702:60] assign hi_530 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_531; // @[Debug.scala:1702:60] assign hi_531 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_532; // @[Debug.scala:1702:60] assign hi_532 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_533; // @[Debug.scala:1702:60] assign hi_533 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_534; // @[Debug.scala:1702:60] assign hi_534 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_535; // @[Debug.scala:1702:60] assign hi_535 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_536; // @[Debug.scala:1702:60] assign hi_536 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_537; // @[Debug.scala:1702:60] assign hi_537 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_538; // @[Debug.scala:1702:60] assign hi_538 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_539; // @[Debug.scala:1702:60] assign hi_539 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_540; // @[Debug.scala:1702:60] assign hi_540 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_541; // @[Debug.scala:1702:60] assign hi_541 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_542; // @[Debug.scala:1702:60] assign hi_542 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_543; // @[Debug.scala:1702:60] assign hi_543 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_544; // @[Debug.scala:1702:60] assign hi_544 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_545; // @[Debug.scala:1702:60] assign hi_545 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_546; // @[Debug.scala:1702:60] assign hi_546 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_547; // @[Debug.scala:1702:60] assign hi_547 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_548; // @[Debug.scala:1702:60] assign hi_548 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_549; // @[Debug.scala:1702:60] assign hi_549 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_550; // @[Debug.scala:1702:60] assign hi_550 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_551; // @[Debug.scala:1702:60] assign hi_551 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_552; // @[Debug.scala:1702:60] assign hi_552 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_553; // @[Debug.scala:1702:60] assign hi_553 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_554; // @[Debug.scala:1702:60] assign hi_554 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_555; // @[Debug.scala:1702:60] assign hi_555 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_556; // @[Debug.scala:1702:60] assign hi_556 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_557; // @[Debug.scala:1702:60] assign hi_557 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_558; // @[Debug.scala:1702:60] assign hi_558 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_559; // @[Debug.scala:1702:60] assign hi_559 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_560; // @[Debug.scala:1702:60] assign hi_560 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_561; // @[Debug.scala:1702:60] assign hi_561 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_562; // @[Debug.scala:1702:60] assign hi_562 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_563; // @[Debug.scala:1702:60] assign hi_563 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_564; // @[Debug.scala:1702:60] assign hi_564 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_565; // @[Debug.scala:1702:60] assign hi_565 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_566; // @[Debug.scala:1702:60] assign hi_566 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_567; // @[Debug.scala:1702:60] assign hi_567 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_568; // @[Debug.scala:1702:60] assign hi_568 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_569; // @[Debug.scala:1702:60] assign hi_569 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_570; // @[Debug.scala:1702:60] assign hi_570 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_571; // @[Debug.scala:1702:60] assign hi_571 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_572; // @[Debug.scala:1702:60] assign hi_572 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_573; // @[Debug.scala:1702:60] assign hi_573 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_574; // @[Debug.scala:1702:60] assign hi_574 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_575; // @[Debug.scala:1702:60] assign hi_575 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_576; // @[Debug.scala:1702:60] assign hi_576 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_577; // @[Debug.scala:1702:60] assign hi_577 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_578; // @[Debug.scala:1702:60] assign hi_578 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_579; // @[Debug.scala:1702:60] assign hi_579 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_580; // @[Debug.scala:1702:60] assign hi_580 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_581; // @[Debug.scala:1702:60] assign hi_581 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_582; // @[Debug.scala:1702:60] assign hi_582 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_583; // @[Debug.scala:1702:60] assign hi_583 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_584; // @[Debug.scala:1702:60] assign hi_584 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_585; // @[Debug.scala:1702:60] assign hi_585 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_586; // @[Debug.scala:1702:60] assign hi_586 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_587; // @[Debug.scala:1702:60] assign hi_587 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_588; // @[Debug.scala:1702:60] assign hi_588 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_589; // @[Debug.scala:1702:60] assign hi_589 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_590; // @[Debug.scala:1702:60] assign hi_590 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_591; // @[Debug.scala:1702:60] assign hi_591 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_592; // @[Debug.scala:1702:60] assign hi_592 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_593; // @[Debug.scala:1702:60] assign hi_593 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_594; // @[Debug.scala:1702:60] assign hi_594 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_595; // @[Debug.scala:1702:60] assign hi_595 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_596; // @[Debug.scala:1702:60] assign hi_596 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_597; // @[Debug.scala:1702:60] assign hi_597 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_598; // @[Debug.scala:1702:60] assign hi_598 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_599; // @[Debug.scala:1702:60] assign hi_599 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_600; // @[Debug.scala:1702:60] assign hi_600 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_601; // @[Debug.scala:1702:60] assign hi_601 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_602; // @[Debug.scala:1702:60] assign hi_602 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_603; // @[Debug.scala:1702:60] assign hi_603 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_604; // @[Debug.scala:1702:60] assign hi_604 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_605; // @[Debug.scala:1702:60] assign hi_605 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_606; // @[Debug.scala:1702:60] assign hi_606 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_607; // @[Debug.scala:1702:60] assign hi_607 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_608; // @[Debug.scala:1702:60] assign hi_608 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_609; // @[Debug.scala:1702:60] assign hi_609 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_610; // @[Debug.scala:1702:60] assign hi_610 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_611; // @[Debug.scala:1702:60] assign hi_611 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_612; // @[Debug.scala:1702:60] assign hi_612 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_613; // @[Debug.scala:1702:60] assign hi_613 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_614; // @[Debug.scala:1702:60] assign hi_614 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_615; // @[Debug.scala:1702:60] assign hi_615 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_616; // @[Debug.scala:1702:60] assign hi_616 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_617; // @[Debug.scala:1702:60] assign hi_617 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_618; // @[Debug.scala:1702:60] assign hi_618 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_619; // @[Debug.scala:1702:60] assign hi_619 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_620; // @[Debug.scala:1702:60] assign hi_620 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_621; // @[Debug.scala:1702:60] assign hi_621 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_622; // @[Debug.scala:1702:60] assign hi_622 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_623; // @[Debug.scala:1702:60] assign hi_623 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_624; // @[Debug.scala:1702:60] assign hi_624 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_625; // @[Debug.scala:1702:60] assign hi_625 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_626; // @[Debug.scala:1702:60] assign hi_626 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_627; // @[Debug.scala:1702:60] assign hi_627 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_628; // @[Debug.scala:1702:60] assign hi_628 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_629; // @[Debug.scala:1702:60] assign hi_629 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_630; // @[Debug.scala:1702:60] assign hi_630 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_631; // @[Debug.scala:1702:60] assign hi_631 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_632; // @[Debug.scala:1702:60] assign hi_632 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_633; // @[Debug.scala:1702:60] assign hi_633 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_634; // @[Debug.scala:1702:60] assign hi_634 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_635; // @[Debug.scala:1702:60] assign hi_635 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_636; // @[Debug.scala:1702:60] assign hi_636 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_637; // @[Debug.scala:1702:60] assign hi_637 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_638; // @[Debug.scala:1702:60] assign hi_638 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_639; // @[Debug.scala:1702:60] assign hi_639 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_640; // @[Debug.scala:1702:60] assign hi_640 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_641; // @[Debug.scala:1702:60] assign hi_641 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_642; // @[Debug.scala:1702:60] assign hi_642 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_643; // @[Debug.scala:1702:60] assign hi_643 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_644; // @[Debug.scala:1702:60] assign hi_644 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_645; // @[Debug.scala:1702:60] assign hi_645 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_646; // @[Debug.scala:1702:60] assign hi_646 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_647; // @[Debug.scala:1702:60] assign hi_647 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_648; // @[Debug.scala:1702:60] assign hi_648 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_649; // @[Debug.scala:1702:60] assign hi_649 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_650; // @[Debug.scala:1702:60] assign hi_650 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_651; // @[Debug.scala:1702:60] assign hi_651 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_652; // @[Debug.scala:1702:60] assign hi_652 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_653; // @[Debug.scala:1702:60] assign hi_653 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_654; // @[Debug.scala:1702:60] assign hi_654 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_655; // @[Debug.scala:1702:60] assign hi_655 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_656; // @[Debug.scala:1702:60] assign hi_656 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_657; // @[Debug.scala:1702:60] assign hi_657 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_658; // @[Debug.scala:1702:60] assign hi_658 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_659; // @[Debug.scala:1702:60] assign hi_659 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_660; // @[Debug.scala:1702:60] assign hi_660 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_661; // @[Debug.scala:1702:60] assign hi_661 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_662; // @[Debug.scala:1702:60] assign hi_662 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_663; // @[Debug.scala:1702:60] assign hi_663 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_664; // @[Debug.scala:1702:60] assign hi_664 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_665; // @[Debug.scala:1702:60] assign hi_665 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_666; // @[Debug.scala:1702:60] assign hi_666 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_667; // @[Debug.scala:1702:60] assign hi_667 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_668; // @[Debug.scala:1702:60] assign hi_668 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_669; // @[Debug.scala:1702:60] assign hi_669 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_670; // @[Debug.scala:1702:60] assign hi_670 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_671; // @[Debug.scala:1702:60] assign hi_671 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_672; // @[Debug.scala:1702:60] assign hi_672 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_673; // @[Debug.scala:1702:60] assign hi_673 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_674; // @[Debug.scala:1702:60] assign hi_674 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_675; // @[Debug.scala:1702:60] assign hi_675 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_676; // @[Debug.scala:1702:60] assign hi_676 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_677; // @[Debug.scala:1702:60] assign hi_677 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_678; // @[Debug.scala:1702:60] assign hi_678 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_679; // @[Debug.scala:1702:60] assign hi_679 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_680; // @[Debug.scala:1702:60] assign hi_680 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_681; // @[Debug.scala:1702:60] assign hi_681 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_682; // @[Debug.scala:1702:60] assign hi_682 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_683; // @[Debug.scala:1702:60] assign hi_683 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_684; // @[Debug.scala:1702:60] assign hi_684 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_685; // @[Debug.scala:1702:60] assign hi_685 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_686; // @[Debug.scala:1702:60] assign hi_686 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_687; // @[Debug.scala:1702:60] assign hi_687 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_688; // @[Debug.scala:1702:60] assign hi_688 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_689; // @[Debug.scala:1702:60] assign hi_689 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_690; // @[Debug.scala:1702:60] assign hi_690 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_691; // @[Debug.scala:1702:60] assign hi_691 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_692; // @[Debug.scala:1702:60] assign hi_692 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_693; // @[Debug.scala:1702:60] assign hi_693 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_694; // @[Debug.scala:1702:60] assign hi_694 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_695; // @[Debug.scala:1702:60] assign hi_695 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_696; // @[Debug.scala:1702:60] assign hi_696 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_697; // @[Debug.scala:1702:60] assign hi_697 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_698; // @[Debug.scala:1702:60] assign hi_698 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_699; // @[Debug.scala:1702:60] assign hi_699 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_700; // @[Debug.scala:1702:60] assign hi_700 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_701; // @[Debug.scala:1702:60] assign hi_701 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_702; // @[Debug.scala:1702:60] assign hi_702 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_703; // @[Debug.scala:1702:60] assign hi_703 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_704; // @[Debug.scala:1702:60] assign hi_704 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_705; // @[Debug.scala:1702:60] assign hi_705 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_706; // @[Debug.scala:1702:60] assign hi_706 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_707; // @[Debug.scala:1702:60] assign hi_707 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_708; // @[Debug.scala:1702:60] assign hi_708 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_709; // @[Debug.scala:1702:60] assign hi_709 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_710; // @[Debug.scala:1702:60] assign hi_710 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_711; // @[Debug.scala:1702:60] assign hi_711 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_712; // @[Debug.scala:1702:60] assign hi_712 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_713; // @[Debug.scala:1702:60] assign hi_713 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_714; // @[Debug.scala:1702:60] assign hi_714 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_715; // @[Debug.scala:1702:60] assign hi_715 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_716; // @[Debug.scala:1702:60] assign hi_716 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_717; // @[Debug.scala:1702:60] assign hi_717 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_718; // @[Debug.scala:1702:60] assign hi_718 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_719; // @[Debug.scala:1702:60] assign hi_719 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_720; // @[Debug.scala:1702:60] assign hi_720 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_721; // @[Debug.scala:1702:60] assign hi_721 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_722; // @[Debug.scala:1702:60] assign hi_722 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_723; // @[Debug.scala:1702:60] assign hi_723 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_724; // @[Debug.scala:1702:60] assign hi_724 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_725; // @[Debug.scala:1702:60] assign hi_725 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_726; // @[Debug.scala:1702:60] assign hi_726 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_727; // @[Debug.scala:1702:60] assign hi_727 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_728; // @[Debug.scala:1702:60] assign hi_728 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_729; // @[Debug.scala:1702:60] assign hi_729 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_730; // @[Debug.scala:1702:60] assign hi_730 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_731; // @[Debug.scala:1702:60] assign hi_731 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_732; // @[Debug.scala:1702:60] assign hi_732 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_733; // @[Debug.scala:1702:60] assign hi_733 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_734; // @[Debug.scala:1702:60] assign hi_734 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_735; // @[Debug.scala:1702:60] assign hi_735 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_736; // @[Debug.scala:1702:60] assign hi_736 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_737; // @[Debug.scala:1702:60] assign hi_737 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_738; // @[Debug.scala:1702:60] assign hi_738 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_739; // @[Debug.scala:1702:60] assign hi_739 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_740; // @[Debug.scala:1702:60] assign hi_740 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_741; // @[Debug.scala:1702:60] assign hi_741 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_742; // @[Debug.scala:1702:60] assign hi_742 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_743; // @[Debug.scala:1702:60] assign hi_743 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_744; // @[Debug.scala:1702:60] assign hi_744 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_745; // @[Debug.scala:1702:60] assign hi_745 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_746; // @[Debug.scala:1702:60] assign hi_746 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_747; // @[Debug.scala:1702:60] assign hi_747 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_748; // @[Debug.scala:1702:60] assign hi_748 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_749; // @[Debug.scala:1702:60] assign hi_749 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_750; // @[Debug.scala:1702:60] assign hi_750 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_751; // @[Debug.scala:1702:60] assign hi_751 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_752; // @[Debug.scala:1702:60] assign hi_752 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_753; // @[Debug.scala:1702:60] assign hi_753 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_754; // @[Debug.scala:1702:60] assign hi_754 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_755; // @[Debug.scala:1702:60] assign hi_755 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_756; // @[Debug.scala:1702:60] assign hi_756 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_757; // @[Debug.scala:1702:60] assign hi_757 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_758; // @[Debug.scala:1702:60] assign hi_758 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_759; // @[Debug.scala:1702:60] assign hi_759 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_760; // @[Debug.scala:1702:60] assign hi_760 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_761; // @[Debug.scala:1702:60] assign hi_761 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_762; // @[Debug.scala:1702:60] assign hi_762 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_763; // @[Debug.scala:1702:60] assign hi_763 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_764; // @[Debug.scala:1702:60] assign hi_764 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_765; // @[Debug.scala:1702:60] assign hi_765 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_766; // @[Debug.scala:1702:60] assign hi_766 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_767; // @[Debug.scala:1702:60] assign hi_767 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_768; // @[Debug.scala:1702:60] assign hi_768 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_769; // @[Debug.scala:1702:60] assign hi_769 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_770; // @[Debug.scala:1702:60] assign hi_770 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_771; // @[Debug.scala:1702:60] assign hi_771 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_772; // @[Debug.scala:1702:60] assign hi_772 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_773; // @[Debug.scala:1702:60] assign hi_773 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_774; // @[Debug.scala:1702:60] assign hi_774 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_775; // @[Debug.scala:1702:60] assign hi_775 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_776; // @[Debug.scala:1702:60] assign hi_776 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_777; // @[Debug.scala:1702:60] assign hi_777 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_778; // @[Debug.scala:1702:60] assign hi_778 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_779; // @[Debug.scala:1702:60] assign hi_779 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_780; // @[Debug.scala:1702:60] assign hi_780 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_781; // @[Debug.scala:1702:60] assign hi_781 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_782; // @[Debug.scala:1702:60] assign hi_782 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_783; // @[Debug.scala:1702:60] assign hi_783 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_784; // @[Debug.scala:1702:60] assign hi_784 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_785; // @[Debug.scala:1702:60] assign hi_785 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_786; // @[Debug.scala:1702:60] assign hi_786 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_787; // @[Debug.scala:1702:60] assign hi_787 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_788; // @[Debug.scala:1702:60] assign hi_788 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_789; // @[Debug.scala:1702:60] assign hi_789 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_790; // @[Debug.scala:1702:60] assign hi_790 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_791; // @[Debug.scala:1702:60] assign hi_791 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_792; // @[Debug.scala:1702:60] assign hi_792 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_793; // @[Debug.scala:1702:60] assign hi_793 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_794; // @[Debug.scala:1702:60] assign hi_794 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_795; // @[Debug.scala:1702:60] assign hi_795 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_796; // @[Debug.scala:1702:60] assign hi_796 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_797; // @[Debug.scala:1702:60] assign hi_797 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_798; // @[Debug.scala:1702:60] assign hi_798 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_799; // @[Debug.scala:1702:60] assign hi_799 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_800; // @[Debug.scala:1702:60] assign hi_800 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_801; // @[Debug.scala:1702:60] assign hi_801 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_802; // @[Debug.scala:1702:60] assign hi_802 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_803; // @[Debug.scala:1702:60] assign hi_803 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_804; // @[Debug.scala:1702:60] assign hi_804 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_805; // @[Debug.scala:1702:60] assign hi_805 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_806; // @[Debug.scala:1702:60] assign hi_806 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_807; // @[Debug.scala:1702:60] assign hi_807 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_808; // @[Debug.scala:1702:60] assign hi_808 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_809; // @[Debug.scala:1702:60] assign hi_809 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_810; // @[Debug.scala:1702:60] assign hi_810 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_811; // @[Debug.scala:1702:60] assign hi_811 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_812; // @[Debug.scala:1702:60] assign hi_812 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_813; // @[Debug.scala:1702:60] assign hi_813 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_814; // @[Debug.scala:1702:60] assign hi_814 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_815; // @[Debug.scala:1702:60] assign hi_815 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_816; // @[Debug.scala:1702:60] assign hi_816 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_817; // @[Debug.scala:1702:60] assign hi_817 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_818; // @[Debug.scala:1702:60] assign hi_818 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_819; // @[Debug.scala:1702:60] assign hi_819 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_820; // @[Debug.scala:1702:60] assign hi_820 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_821; // @[Debug.scala:1702:60] assign hi_821 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_822; // @[Debug.scala:1702:60] assign hi_822 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_823; // @[Debug.scala:1702:60] assign hi_823 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_824; // @[Debug.scala:1702:60] assign hi_824 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_825; // @[Debug.scala:1702:60] assign hi_825 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_826; // @[Debug.scala:1702:60] assign hi_826 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_827; // @[Debug.scala:1702:60] assign hi_827 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_828; // @[Debug.scala:1702:60] assign hi_828 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_829; // @[Debug.scala:1702:60] assign hi_829 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_830; // @[Debug.scala:1702:60] assign hi_830 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_831; // @[Debug.scala:1702:60] assign hi_831 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_832; // @[Debug.scala:1702:60] assign hi_832 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_833; // @[Debug.scala:1702:60] assign hi_833 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_834; // @[Debug.scala:1702:60] assign hi_834 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_835; // @[Debug.scala:1702:60] assign hi_835 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_836; // @[Debug.scala:1702:60] assign hi_836 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_837; // @[Debug.scala:1702:60] assign hi_837 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_838; // @[Debug.scala:1702:60] assign hi_838 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_839; // @[Debug.scala:1702:60] assign hi_839 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_840; // @[Debug.scala:1702:60] assign hi_840 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_841; // @[Debug.scala:1702:60] assign hi_841 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_842; // @[Debug.scala:1702:60] assign hi_842 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_843; // @[Debug.scala:1702:60] assign hi_843 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_844; // @[Debug.scala:1702:60] assign hi_844 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_845; // @[Debug.scala:1702:60] assign hi_845 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_846; // @[Debug.scala:1702:60] assign hi_846 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_847; // @[Debug.scala:1702:60] assign hi_847 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_848; // @[Debug.scala:1702:60] assign hi_848 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_849; // @[Debug.scala:1702:60] assign hi_849 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_850; // @[Debug.scala:1702:60] assign hi_850 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_851; // @[Debug.scala:1702:60] assign hi_851 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_852; // @[Debug.scala:1702:60] assign hi_852 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_853; // @[Debug.scala:1702:60] assign hi_853 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_854; // @[Debug.scala:1702:60] assign hi_854 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_855; // @[Debug.scala:1702:60] assign hi_855 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_856; // @[Debug.scala:1702:60] assign hi_856 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_857; // @[Debug.scala:1702:60] assign hi_857 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_858; // @[Debug.scala:1702:60] assign hi_858 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_859; // @[Debug.scala:1702:60] assign hi_859 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_860; // @[Debug.scala:1702:60] assign hi_860 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_861; // @[Debug.scala:1702:60] assign hi_861 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_862; // @[Debug.scala:1702:60] assign hi_862 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_863; // @[Debug.scala:1702:60] assign hi_863 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_864; // @[Debug.scala:1702:60] assign hi_864 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_865; // @[Debug.scala:1702:60] assign hi_865 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_866; // @[Debug.scala:1702:60] assign hi_866 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_867; // @[Debug.scala:1702:60] assign hi_867 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_868; // @[Debug.scala:1702:60] assign hi_868 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_869; // @[Debug.scala:1702:60] assign hi_869 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_870; // @[Debug.scala:1702:60] assign hi_870 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_871; // @[Debug.scala:1702:60] assign hi_871 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_872; // @[Debug.scala:1702:60] assign hi_872 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_873; // @[Debug.scala:1702:60] assign hi_873 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_874; // @[Debug.scala:1702:60] assign hi_874 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_875; // @[Debug.scala:1702:60] assign hi_875 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_876; // @[Debug.scala:1702:60] assign hi_876 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_877; // @[Debug.scala:1702:60] assign hi_877 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_878; // @[Debug.scala:1702:60] assign hi_878 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_879; // @[Debug.scala:1702:60] assign hi_879 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_880; // @[Debug.scala:1702:60] assign hi_880 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_881; // @[Debug.scala:1702:60] assign hi_881 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_882; // @[Debug.scala:1702:60] assign hi_882 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_883; // @[Debug.scala:1702:60] assign hi_883 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_884; // @[Debug.scala:1702:60] assign hi_884 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_885; // @[Debug.scala:1702:60] assign hi_885 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_886; // @[Debug.scala:1702:60] assign hi_886 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_887; // @[Debug.scala:1702:60] assign hi_887 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_888; // @[Debug.scala:1702:60] assign hi_888 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_889; // @[Debug.scala:1702:60] assign hi_889 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_890; // @[Debug.scala:1702:60] assign hi_890 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_891; // @[Debug.scala:1702:60] assign hi_891 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_892; // @[Debug.scala:1702:60] assign hi_892 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_893; // @[Debug.scala:1702:60] assign hi_893 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_894; // @[Debug.scala:1702:60] assign hi_894 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_895; // @[Debug.scala:1702:60] assign hi_895 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_896; // @[Debug.scala:1702:60] assign hi_896 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_897; // @[Debug.scala:1702:60] assign hi_897 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_898; // @[Debug.scala:1702:60] assign hi_898 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_899; // @[Debug.scala:1702:60] assign hi_899 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_900; // @[Debug.scala:1702:60] assign hi_900 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_901; // @[Debug.scala:1702:60] assign hi_901 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_902; // @[Debug.scala:1702:60] assign hi_902 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_903; // @[Debug.scala:1702:60] assign hi_903 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_904; // @[Debug.scala:1702:60] assign hi_904 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_905; // @[Debug.scala:1702:60] assign hi_905 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_906; // @[Debug.scala:1702:60] assign hi_906 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_907; // @[Debug.scala:1702:60] assign hi_907 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_908; // @[Debug.scala:1702:60] assign hi_908 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_909; // @[Debug.scala:1702:60] assign hi_909 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_910; // @[Debug.scala:1702:60] assign hi_910 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_911; // @[Debug.scala:1702:60] assign hi_911 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_912; // @[Debug.scala:1702:60] assign hi_912 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_913; // @[Debug.scala:1702:60] assign hi_913 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_914; // @[Debug.scala:1702:60] assign hi_914 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_915; // @[Debug.scala:1702:60] assign hi_915 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_916; // @[Debug.scala:1702:60] assign hi_916 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_917; // @[Debug.scala:1702:60] assign hi_917 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_918; // @[Debug.scala:1702:60] assign hi_918 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_919; // @[Debug.scala:1702:60] assign hi_919 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_920; // @[Debug.scala:1702:60] assign hi_920 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_921; // @[Debug.scala:1702:60] assign hi_921 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_922; // @[Debug.scala:1702:60] assign hi_922 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_923; // @[Debug.scala:1702:60] assign hi_923 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_924; // @[Debug.scala:1702:60] assign hi_924 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_925; // @[Debug.scala:1702:60] assign hi_925 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_926; // @[Debug.scala:1702:60] assign hi_926 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_927; // @[Debug.scala:1702:60] assign hi_927 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_928; // @[Debug.scala:1702:60] assign hi_928 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_929; // @[Debug.scala:1702:60] assign hi_929 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_930; // @[Debug.scala:1702:60] assign hi_930 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_931; // @[Debug.scala:1702:60] assign hi_931 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_932; // @[Debug.scala:1702:60] assign hi_932 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_933; // @[Debug.scala:1702:60] assign hi_933 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_934; // @[Debug.scala:1702:60] assign hi_934 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_935; // @[Debug.scala:1702:60] assign hi_935 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_936; // @[Debug.scala:1702:60] assign hi_936 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_937; // @[Debug.scala:1702:60] assign hi_937 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_938; // @[Debug.scala:1702:60] assign hi_938 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_939; // @[Debug.scala:1702:60] assign hi_939 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_940; // @[Debug.scala:1702:60] assign hi_940 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_941; // @[Debug.scala:1702:60] assign hi_941 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_942; // @[Debug.scala:1702:60] assign hi_942 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_943; // @[Debug.scala:1702:60] assign hi_943 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_944; // @[Debug.scala:1702:60] assign hi_944 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_945; // @[Debug.scala:1702:60] assign hi_945 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_946; // @[Debug.scala:1702:60] assign hi_946 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_947; // @[Debug.scala:1702:60] assign hi_947 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_948; // @[Debug.scala:1702:60] assign hi_948 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_949; // @[Debug.scala:1702:60] assign hi_949 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_950; // @[Debug.scala:1702:60] assign hi_950 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_951; // @[Debug.scala:1702:60] assign hi_951 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_952; // @[Debug.scala:1702:60] assign hi_952 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_953; // @[Debug.scala:1702:60] assign hi_953 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_954; // @[Debug.scala:1702:60] assign hi_954 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_955; // @[Debug.scala:1702:60] assign hi_955 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_956; // @[Debug.scala:1702:60] assign hi_956 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_957; // @[Debug.scala:1702:60] assign hi_957 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_958; // @[Debug.scala:1702:60] assign hi_958 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_959; // @[Debug.scala:1702:60] assign hi_959 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_960; // @[Debug.scala:1702:60] assign hi_960 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_961; // @[Debug.scala:1702:60] assign hi_961 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_962; // @[Debug.scala:1702:60] assign hi_962 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_963; // @[Debug.scala:1702:60] assign hi_963 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_964; // @[Debug.scala:1702:60] assign hi_964 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_965; // @[Debug.scala:1702:60] assign hi_965 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_966; // @[Debug.scala:1702:60] assign hi_966 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_967; // @[Debug.scala:1702:60] assign hi_967 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_968; // @[Debug.scala:1702:60] assign hi_968 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_969; // @[Debug.scala:1702:60] assign hi_969 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_970; // @[Debug.scala:1702:60] assign hi_970 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_971; // @[Debug.scala:1702:60] assign hi_971 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_972; // @[Debug.scala:1702:60] assign hi_972 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_973; // @[Debug.scala:1702:60] assign hi_973 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_974; // @[Debug.scala:1702:60] assign hi_974 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_975; // @[Debug.scala:1702:60] assign hi_975 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_976; // @[Debug.scala:1702:60] assign hi_976 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_977; // @[Debug.scala:1702:60] assign hi_977 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_978; // @[Debug.scala:1702:60] assign hi_978 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_979; // @[Debug.scala:1702:60] assign hi_979 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_980; // @[Debug.scala:1702:60] assign hi_980 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_981; // @[Debug.scala:1702:60] assign hi_981 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_982; // @[Debug.scala:1702:60] assign hi_982 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_983; // @[Debug.scala:1702:60] assign hi_983 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_984; // @[Debug.scala:1702:60] assign hi_984 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_985; // @[Debug.scala:1702:60] assign hi_985 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_986; // @[Debug.scala:1702:60] assign hi_986 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_987; // @[Debug.scala:1702:60] assign hi_987 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_988; // @[Debug.scala:1702:60] assign hi_988 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_989; // @[Debug.scala:1702:60] assign hi_989 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_990; // @[Debug.scala:1702:60] assign hi_990 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_991; // @[Debug.scala:1702:60] assign hi_991 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_992; // @[Debug.scala:1702:60] assign hi_992 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_993; // @[Debug.scala:1702:60] assign hi_993 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_994; // @[Debug.scala:1702:60] assign hi_994 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_995; // @[Debug.scala:1702:60] assign hi_995 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_996; // @[Debug.scala:1702:60] assign hi_996 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_997; // @[Debug.scala:1702:60] assign hi_997 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_998; // @[Debug.scala:1702:60] assign hi_998 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_999; // @[Debug.scala:1702:60] assign hi_999 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1000; // @[Debug.scala:1702:60] assign hi_1000 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1001; // @[Debug.scala:1702:60] assign hi_1001 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1002; // @[Debug.scala:1702:60] assign hi_1002 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1003; // @[Debug.scala:1702:60] assign hi_1003 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1004; // @[Debug.scala:1702:60] assign hi_1004 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1005; // @[Debug.scala:1702:60] assign hi_1005 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1006; // @[Debug.scala:1702:60] assign hi_1006 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1007; // @[Debug.scala:1702:60] assign hi_1007 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1008; // @[Debug.scala:1702:60] assign hi_1008 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1009; // @[Debug.scala:1702:60] assign hi_1009 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1010; // @[Debug.scala:1702:60] assign hi_1010 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1011; // @[Debug.scala:1702:60] assign hi_1011 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1012; // @[Debug.scala:1702:60] assign hi_1012 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1013; // @[Debug.scala:1702:60] assign hi_1013 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1014; // @[Debug.scala:1702:60] assign hi_1014 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1015; // @[Debug.scala:1702:60] assign hi_1015 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1016; // @[Debug.scala:1702:60] assign hi_1016 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1017; // @[Debug.scala:1702:60] assign hi_1017 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1018; // @[Debug.scala:1702:60] assign hi_1018 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1019; // @[Debug.scala:1702:60] assign hi_1019 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1020; // @[Debug.scala:1702:60] assign hi_1020 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1021; // @[Debug.scala:1702:60] assign hi_1021 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1022; // @[Debug.scala:1702:60] assign hi_1022 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1023; // @[Debug.scala:1702:60] assign hi_1023 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1024; // @[Debug.scala:1702:60] assign hi_1024 = _GEN_16; // @[Debug.scala:1702:60] wire [7:0] _out_T_6436 = {hi_1, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6184 = {hi_9, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8824 = {hi_17, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12272 = {hi_25, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4125 = {hi_33, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4197 = {hi_41, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6256 = {hi_49, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8968 = {hi_57, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11984 = {hi_65, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4989 = {hi_73, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1917 = {hi_81, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11032 = {hi_89, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8304 = {hi_97, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5655 = {hi_105, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2509 = {hi_113, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10208 = {hi_121, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7478 = {hi_129, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9632 = {hi_137, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11464 = {hi_145, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3981 = {hi_153, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6830 = {hi_161, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7118 = {hi_169, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9704 = {hi_177, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11392 = {hi_185, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3245 = {hi_193, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2581 = {hi_201, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10064 = {hi_209, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8448 = {hi_217, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5439 = {hi_225, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3101 = {hi_233, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10728 = {hi_241, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7694 = {hi_249, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4845 = {hi_257, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6974 = {hi_265, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9256 = {hi_273, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12416 = {hi_281, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3533 = {hi_289, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5061 = {hi_297, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6740 = {hi_305, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9184 = {hi_313, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11680 = {hi_321, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5583 = {hi_329, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2133 = {hi_337, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10960 = {hi_345, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7838 = {hi_353, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6112 = {hi_361, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2653 = {hi_369, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10136 = {hi_377, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7190 = {hi_385, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9920 = {hi_393, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12344 = {hi_401, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3605 = {hi_409, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7046 = {hi_417, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7622 = {hi_425, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9992 = {hi_433, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11608 = {hi_441, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2869 = {hi_449, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2725 = {hi_457, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10800 = {hi_465, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7766 = {hi_473, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5511 = {hi_481, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3173 = {hi_489, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11536 = {hi_497, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7262 = {hi_505, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4917 = {hi_513, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5799 = {hi_521, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9560 = {hi_529, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12056 = {hi_537, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3029 = {hi_545, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5295 = {hi_553, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8520 = {hi_561, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9848 = {hi_569, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12488 = {hi_577, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4629 = {hi_585, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2437 = {hi_593, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10280 = {hi_601, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7334 = {hi_609, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6364 = {hi_617, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4413 = {hi_625, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11104 = {hi_633, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8214 = {hi_641, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9400 = {hi_649, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11824 = {hi_657, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3837 = {hi_665, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5871 = {hi_673, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8376 = {hi_681, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11176 = {hi_689, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12648 = {hi_697, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3461 = {hi_705, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2293 = {hi_713, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10352 = {hi_721, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7998 = {hi_729, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4701 = {hi_737, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4053 = {hi_745, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12720 = {hi_753, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8896 = {hi_761, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5367 = {hi_769, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5727 = {hi_777, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9040 = {hi_785, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12936 = {hi_793, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3317 = {hi_801, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5151 = {hi_809, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8070 = {hi_817, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10584 = {hi_825, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12792 = {hi_833, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4485 = {hi_841, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2061 = {hi_849, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11248 = {hi_857, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7550 = {hi_865, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6508 = {hi_873, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3765 = {hi_881, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12128 = {hi_889, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8680 = {hi_897, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9112 = {hi_905, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12200 = {hi_913, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4269 = {hi_921, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6668 = {hi_929, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8142 = {hi_937, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11320 = {hi_945, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2365 = {hi_953, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4557 = {hi_961, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1989 = {hi_969, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10512 = {hi_977, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8752 = {hi_985, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5223 = {hi_993, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3909 = {hi_1001, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12864 = {hi_1009, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9328 = {hi_1017, flags_0_go}; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_1_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T_1; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T_1 = in_1_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T_1; // @[Edges.scala:192:34] wire out_front_1_bits_read = in_1_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_1_bits_index = in_1_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_1_bits_data = in_1_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_1_bits_mask = in_1_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_1_bits_extra_tlrr_extra_source = in_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_1_bits_extra_tlrr_extra_size = in_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T_1 = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_1_bits_read = _in_bits_read_T_1; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T_1 = tlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_1_bits_index = _in_bits_index_T_1; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T_1 = out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_1_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_data = out_1_bits_data; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_source = out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T_1 = out_front_1_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T_1 = out_front_1_valid; // @[RegisterRouter.scala:87:24] assign out_1_bits_read = out_front_1_bits_read; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_source = out_front_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_size = out_front_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN_17 = out_front_1_bits_index & 9'h100; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex_1; // @[RegisterRouter.scala:87:24] assign out_findex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex_1; // @[RegisterRouter.scala:87:24] assign out_bindex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire _GEN_18 = out_findex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1600; // @[RegisterRouter.scala:87:24] assign _out_T_1600 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1602; // @[RegisterRouter.scala:87:24] assign _out_T_1602 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1604; // @[RegisterRouter.scala:87:24] assign _out_T_1604 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1606; // @[RegisterRouter.scala:87:24] assign _out_T_1606 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1608; // @[RegisterRouter.scala:87:24] assign _out_T_1608 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1610; // @[RegisterRouter.scala:87:24] assign _out_T_1610 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1612; // @[RegisterRouter.scala:87:24] assign _out_T_1612 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1614; // @[RegisterRouter.scala:87:24] assign _out_T_1614 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1616; // @[RegisterRouter.scala:87:24] assign _out_T_1616 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1618; // @[RegisterRouter.scala:87:24] assign _out_T_1618 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1620; // @[RegisterRouter.scala:87:24] assign _out_T_1620 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1622; // @[RegisterRouter.scala:87:24] assign _out_T_1622 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1626; // @[RegisterRouter.scala:87:24] assign _out_T_1626 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1628; // @[RegisterRouter.scala:87:24] assign _out_T_1628 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1630; // @[RegisterRouter.scala:87:24] assign _out_T_1630 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1632; // @[RegisterRouter.scala:87:24] assign _out_T_1632 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1634; // @[RegisterRouter.scala:87:24] assign _out_T_1634 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1636; // @[RegisterRouter.scala:87:24] assign _out_T_1636 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1638; // @[RegisterRouter.scala:87:24] assign _out_T_1638 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1642; // @[RegisterRouter.scala:87:24] assign _out_T_1642 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1644; // @[RegisterRouter.scala:87:24] assign _out_T_1644 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1646; // @[RegisterRouter.scala:87:24] assign _out_T_1646 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1648; // @[RegisterRouter.scala:87:24] assign _out_T_1648 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1650; // @[RegisterRouter.scala:87:24] assign _out_T_1650 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1652; // @[RegisterRouter.scala:87:24] assign _out_T_1652 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1654; // @[RegisterRouter.scala:87:24] assign _out_T_1654 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1656; // @[RegisterRouter.scala:87:24] assign _out_T_1656 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1658; // @[RegisterRouter.scala:87:24] assign _out_T_1658 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1660; // @[RegisterRouter.scala:87:24] assign _out_T_1660 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1662; // @[RegisterRouter.scala:87:24] assign _out_T_1662 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1664; // @[RegisterRouter.scala:87:24] assign _out_T_1664 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1668; // @[RegisterRouter.scala:87:24] assign _out_T_1668 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1670; // @[RegisterRouter.scala:87:24] assign _out_T_1670 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1672; // @[RegisterRouter.scala:87:24] assign _out_T_1672 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1674; // @[RegisterRouter.scala:87:24] assign _out_T_1674 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1676; // @[RegisterRouter.scala:87:24] assign _out_T_1676 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1680; // @[RegisterRouter.scala:87:24] assign _out_T_1680 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1682; // @[RegisterRouter.scala:87:24] assign _out_T_1682 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1684; // @[RegisterRouter.scala:87:24] assign _out_T_1684 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1686; // @[RegisterRouter.scala:87:24] assign _out_T_1686 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1688; // @[RegisterRouter.scala:87:24] assign _out_T_1688 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1690; // @[RegisterRouter.scala:87:24] assign _out_T_1690 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1692; // @[RegisterRouter.scala:87:24] assign _out_T_1692 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1694; // @[RegisterRouter.scala:87:24] assign _out_T_1694 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1696; // @[RegisterRouter.scala:87:24] assign _out_T_1696 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1698; // @[RegisterRouter.scala:87:24] assign _out_T_1698 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1700; // @[RegisterRouter.scala:87:24] assign _out_T_1700 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1702; // @[RegisterRouter.scala:87:24] assign _out_T_1702 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1704; // @[RegisterRouter.scala:87:24] assign _out_T_1704 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1706; // @[RegisterRouter.scala:87:24] assign _out_T_1706 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1708; // @[RegisterRouter.scala:87:24] assign _out_T_1708 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1710; // @[RegisterRouter.scala:87:24] assign _out_T_1710 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1712; // @[RegisterRouter.scala:87:24] assign _out_T_1712 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1714; // @[RegisterRouter.scala:87:24] assign _out_T_1714 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1718; // @[RegisterRouter.scala:87:24] assign _out_T_1718 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1720; // @[RegisterRouter.scala:87:24] assign _out_T_1720 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1722; // @[RegisterRouter.scala:87:24] assign _out_T_1722 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1726; // @[RegisterRouter.scala:87:24] assign _out_T_1726 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1728; // @[RegisterRouter.scala:87:24] assign _out_T_1728 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1730; // @[RegisterRouter.scala:87:24] assign _out_T_1730 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1732; // @[RegisterRouter.scala:87:24] assign _out_T_1732 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1734; // @[RegisterRouter.scala:87:24] assign _out_T_1734 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1736; // @[RegisterRouter.scala:87:24] assign _out_T_1736 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1738; // @[RegisterRouter.scala:87:24] assign _out_T_1738 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1740; // @[RegisterRouter.scala:87:24] assign _out_T_1740 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1744; // @[RegisterRouter.scala:87:24] assign _out_T_1744 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1746; // @[RegisterRouter.scala:87:24] assign _out_T_1746 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1748; // @[RegisterRouter.scala:87:24] assign _out_T_1748 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1750; // @[RegisterRouter.scala:87:24] assign _out_T_1750 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1752; // @[RegisterRouter.scala:87:24] assign _out_T_1752 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1754; // @[RegisterRouter.scala:87:24] assign _out_T_1754 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1758; // @[RegisterRouter.scala:87:24] assign _out_T_1758 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1760; // @[RegisterRouter.scala:87:24] assign _out_T_1760 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1762; // @[RegisterRouter.scala:87:24] assign _out_T_1762 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1764; // @[RegisterRouter.scala:87:24] assign _out_T_1764 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1766; // @[RegisterRouter.scala:87:24] assign _out_T_1766 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1768; // @[RegisterRouter.scala:87:24] assign _out_T_1768 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1770; // @[RegisterRouter.scala:87:24] assign _out_T_1770 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1772; // @[RegisterRouter.scala:87:24] assign _out_T_1772 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1774; // @[RegisterRouter.scala:87:24] assign _out_T_1774 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1776; // @[RegisterRouter.scala:87:24] assign _out_T_1776 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1778; // @[RegisterRouter.scala:87:24] assign _out_T_1778 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1780; // @[RegisterRouter.scala:87:24] assign _out_T_1780 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1782; // @[RegisterRouter.scala:87:24] assign _out_T_1782 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1784; // @[RegisterRouter.scala:87:24] assign _out_T_1784 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1786; // @[RegisterRouter.scala:87:24] assign _out_T_1786 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1788; // @[RegisterRouter.scala:87:24] assign _out_T_1788 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1790; // @[RegisterRouter.scala:87:24] assign _out_T_1790 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1792; // @[RegisterRouter.scala:87:24] assign _out_T_1792 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1794; // @[RegisterRouter.scala:87:24] assign _out_T_1794 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1796; // @[RegisterRouter.scala:87:24] assign _out_T_1796 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1798; // @[RegisterRouter.scala:87:24] assign _out_T_1798 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1800; // @[RegisterRouter.scala:87:24] assign _out_T_1800 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1802; // @[RegisterRouter.scala:87:24] assign _out_T_1802 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1804; // @[RegisterRouter.scala:87:24] assign _out_T_1804 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1806; // @[RegisterRouter.scala:87:24] assign _out_T_1806 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1808; // @[RegisterRouter.scala:87:24] assign _out_T_1808 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1810; // @[RegisterRouter.scala:87:24] assign _out_T_1810 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1812; // @[RegisterRouter.scala:87:24] assign _out_T_1812 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1814; // @[RegisterRouter.scala:87:24] assign _out_T_1814 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1816; // @[RegisterRouter.scala:87:24] assign _out_T_1816 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1818; // @[RegisterRouter.scala:87:24] assign _out_T_1818 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1820; // @[RegisterRouter.scala:87:24] assign _out_T_1820 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1824; // @[RegisterRouter.scala:87:24] assign _out_T_1824 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1826; // @[RegisterRouter.scala:87:24] assign _out_T_1826 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1828; // @[RegisterRouter.scala:87:24] assign _out_T_1828 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1830; // @[RegisterRouter.scala:87:24] assign _out_T_1830 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1832; // @[RegisterRouter.scala:87:24] assign _out_T_1832 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1834; // @[RegisterRouter.scala:87:24] assign _out_T_1834 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1836; // @[RegisterRouter.scala:87:24] assign _out_T_1836 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1838; // @[RegisterRouter.scala:87:24] assign _out_T_1838 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1840; // @[RegisterRouter.scala:87:24] assign _out_T_1840 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1842; // @[RegisterRouter.scala:87:24] assign _out_T_1842 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1844; // @[RegisterRouter.scala:87:24] assign _out_T_1844 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1848; // @[RegisterRouter.scala:87:24] assign _out_T_1848 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1850; // @[RegisterRouter.scala:87:24] assign _out_T_1850 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1852; // @[RegisterRouter.scala:87:24] assign _out_T_1852 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1854; // @[RegisterRouter.scala:87:24] assign _out_T_1854 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1856; // @[RegisterRouter.scala:87:24] assign _out_T_1856 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1858; // @[RegisterRouter.scala:87:24] assign _out_T_1858 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1860; // @[RegisterRouter.scala:87:24] assign _out_T_1860 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1862; // @[RegisterRouter.scala:87:24] assign _out_T_1862 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1864; // @[RegisterRouter.scala:87:24] assign _out_T_1864 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1866; // @[RegisterRouter.scala:87:24] assign _out_T_1866 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1868; // @[RegisterRouter.scala:87:24] assign _out_T_1868 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1870; // @[RegisterRouter.scala:87:24] assign _out_T_1870 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1872; // @[RegisterRouter.scala:87:24] assign _out_T_1872 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1874; // @[RegisterRouter.scala:87:24] assign _out_T_1874 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1878; // @[RegisterRouter.scala:87:24] assign _out_T_1878 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1880; // @[RegisterRouter.scala:87:24] assign _out_T_1880 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1882; // @[RegisterRouter.scala:87:24] assign _out_T_1882 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1884; // @[RegisterRouter.scala:87:24] assign _out_T_1884 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1886; // @[RegisterRouter.scala:87:24] assign _out_T_1886 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1888; // @[RegisterRouter.scala:87:24] assign _out_T_1888 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1890; // @[RegisterRouter.scala:87:24] assign _out_T_1890 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1892; // @[RegisterRouter.scala:87:24] assign _out_T_1892 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1894; // @[RegisterRouter.scala:87:24] assign _out_T_1894 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1896; // @[RegisterRouter.scala:87:24] assign _out_T_1896 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1898; // @[RegisterRouter.scala:87:24] assign _out_T_1898 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1900; // @[RegisterRouter.scala:87:24] assign _out_T_1900 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1902; // @[RegisterRouter.scala:87:24] assign _out_T_1902 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1904; // @[RegisterRouter.scala:87:24] assign _out_T_1904 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1906; // @[RegisterRouter.scala:87:24] assign _out_T_1906 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1908; // @[RegisterRouter.scala:87:24] assign _out_T_1908 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _GEN_19 = out_bindex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1601; // @[RegisterRouter.scala:87:24] assign _out_T_1601 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1603; // @[RegisterRouter.scala:87:24] assign _out_T_1603 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1605; // @[RegisterRouter.scala:87:24] assign _out_T_1605 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1607; // @[RegisterRouter.scala:87:24] assign _out_T_1607 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1609; // @[RegisterRouter.scala:87:24] assign _out_T_1609 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1611; // @[RegisterRouter.scala:87:24] assign _out_T_1611 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1613; // @[RegisterRouter.scala:87:24] assign _out_T_1613 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1615; // @[RegisterRouter.scala:87:24] assign _out_T_1615 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1617; // @[RegisterRouter.scala:87:24] assign _out_T_1617 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1619; // @[RegisterRouter.scala:87:24] assign _out_T_1619 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1621; // @[RegisterRouter.scala:87:24] assign _out_T_1621 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1623; // @[RegisterRouter.scala:87:24] assign _out_T_1623 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1627; // @[RegisterRouter.scala:87:24] assign _out_T_1627 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1629; // @[RegisterRouter.scala:87:24] assign _out_T_1629 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1631; // @[RegisterRouter.scala:87:24] assign _out_T_1631 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1633; // @[RegisterRouter.scala:87:24] assign _out_T_1633 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1635; // @[RegisterRouter.scala:87:24] assign _out_T_1635 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1637; // @[RegisterRouter.scala:87:24] assign _out_T_1637 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1639; // @[RegisterRouter.scala:87:24] assign _out_T_1639 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1643; // @[RegisterRouter.scala:87:24] assign _out_T_1643 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1645; // @[RegisterRouter.scala:87:24] assign _out_T_1645 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1647; // @[RegisterRouter.scala:87:24] assign _out_T_1647 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1649; // @[RegisterRouter.scala:87:24] assign _out_T_1649 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1651; // @[RegisterRouter.scala:87:24] assign _out_T_1651 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1653; // @[RegisterRouter.scala:87:24] assign _out_T_1653 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1655; // @[RegisterRouter.scala:87:24] assign _out_T_1655 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1657; // @[RegisterRouter.scala:87:24] assign _out_T_1657 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1659; // @[RegisterRouter.scala:87:24] assign _out_T_1659 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1661; // @[RegisterRouter.scala:87:24] assign _out_T_1661 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1663; // @[RegisterRouter.scala:87:24] assign _out_T_1663 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1665; // @[RegisterRouter.scala:87:24] assign _out_T_1665 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1669; // @[RegisterRouter.scala:87:24] assign _out_T_1669 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1671; // @[RegisterRouter.scala:87:24] assign _out_T_1671 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1673; // @[RegisterRouter.scala:87:24] assign _out_T_1673 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1675; // @[RegisterRouter.scala:87:24] assign _out_T_1675 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1677; // @[RegisterRouter.scala:87:24] assign _out_T_1677 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1681; // @[RegisterRouter.scala:87:24] assign _out_T_1681 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1683; // @[RegisterRouter.scala:87:24] assign _out_T_1683 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1685; // @[RegisterRouter.scala:87:24] assign _out_T_1685 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1687; // @[RegisterRouter.scala:87:24] assign _out_T_1687 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1689; // @[RegisterRouter.scala:87:24] assign _out_T_1689 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1691; // @[RegisterRouter.scala:87:24] assign _out_T_1691 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1693; // @[RegisterRouter.scala:87:24] assign _out_T_1693 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1695; // @[RegisterRouter.scala:87:24] assign _out_T_1695 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1697; // @[RegisterRouter.scala:87:24] assign _out_T_1697 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1699; // @[RegisterRouter.scala:87:24] assign _out_T_1699 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1701; // @[RegisterRouter.scala:87:24] assign _out_T_1701 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1703; // @[RegisterRouter.scala:87:24] assign _out_T_1703 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1705; // @[RegisterRouter.scala:87:24] assign _out_T_1705 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1707; // @[RegisterRouter.scala:87:24] assign _out_T_1707 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1709; // @[RegisterRouter.scala:87:24] assign _out_T_1709 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1711; // @[RegisterRouter.scala:87:24] assign _out_T_1711 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1713; // @[RegisterRouter.scala:87:24] assign _out_T_1713 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1715; // @[RegisterRouter.scala:87:24] assign _out_T_1715 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1719; // @[RegisterRouter.scala:87:24] assign _out_T_1719 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1721; // @[RegisterRouter.scala:87:24] assign _out_T_1721 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1723; // @[RegisterRouter.scala:87:24] assign _out_T_1723 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1727; // @[RegisterRouter.scala:87:24] assign _out_T_1727 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1729; // @[RegisterRouter.scala:87:24] assign _out_T_1729 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1731; // @[RegisterRouter.scala:87:24] assign _out_T_1731 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1733; // @[RegisterRouter.scala:87:24] assign _out_T_1733 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1735; // @[RegisterRouter.scala:87:24] assign _out_T_1735 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1737; // @[RegisterRouter.scala:87:24] assign _out_T_1737 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1739; // @[RegisterRouter.scala:87:24] assign _out_T_1739 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1741; // @[RegisterRouter.scala:87:24] assign _out_T_1741 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1745; // @[RegisterRouter.scala:87:24] assign _out_T_1745 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1747; // @[RegisterRouter.scala:87:24] assign _out_T_1747 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1749; // @[RegisterRouter.scala:87:24] assign _out_T_1749 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1751; // @[RegisterRouter.scala:87:24] assign _out_T_1751 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1753; // @[RegisterRouter.scala:87:24] assign _out_T_1753 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1755; // @[RegisterRouter.scala:87:24] assign _out_T_1755 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1759; // @[RegisterRouter.scala:87:24] assign _out_T_1759 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1761; // @[RegisterRouter.scala:87:24] assign _out_T_1761 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1763; // @[RegisterRouter.scala:87:24] assign _out_T_1763 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1765; // @[RegisterRouter.scala:87:24] assign _out_T_1765 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1767; // @[RegisterRouter.scala:87:24] assign _out_T_1767 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1769; // @[RegisterRouter.scala:87:24] assign _out_T_1769 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1771; // @[RegisterRouter.scala:87:24] assign _out_T_1771 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1773; // @[RegisterRouter.scala:87:24] assign _out_T_1773 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1775; // @[RegisterRouter.scala:87:24] assign _out_T_1775 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1777; // @[RegisterRouter.scala:87:24] assign _out_T_1777 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1779; // @[RegisterRouter.scala:87:24] assign _out_T_1779 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1781; // @[RegisterRouter.scala:87:24] assign _out_T_1781 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1783; // @[RegisterRouter.scala:87:24] assign _out_T_1783 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1785; // @[RegisterRouter.scala:87:24] assign _out_T_1785 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1787; // @[RegisterRouter.scala:87:24] assign _out_T_1787 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1789; // @[RegisterRouter.scala:87:24] assign _out_T_1789 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1791; // @[RegisterRouter.scala:87:24] assign _out_T_1791 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1793; // @[RegisterRouter.scala:87:24] assign _out_T_1793 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1795; // @[RegisterRouter.scala:87:24] assign _out_T_1795 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1797; // @[RegisterRouter.scala:87:24] assign _out_T_1797 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1799; // @[RegisterRouter.scala:87:24] assign _out_T_1799 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1801; // @[RegisterRouter.scala:87:24] assign _out_T_1801 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1803; // @[RegisterRouter.scala:87:24] assign _out_T_1803 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1805; // @[RegisterRouter.scala:87:24] assign _out_T_1805 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1807; // @[RegisterRouter.scala:87:24] assign _out_T_1807 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1809; // @[RegisterRouter.scala:87:24] assign _out_T_1809 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1811; // @[RegisterRouter.scala:87:24] assign _out_T_1811 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1813; // @[RegisterRouter.scala:87:24] assign _out_T_1813 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1815; // @[RegisterRouter.scala:87:24] assign _out_T_1815 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1817; // @[RegisterRouter.scala:87:24] assign _out_T_1817 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1819; // @[RegisterRouter.scala:87:24] assign _out_T_1819 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1821; // @[RegisterRouter.scala:87:24] assign _out_T_1821 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1825; // @[RegisterRouter.scala:87:24] assign _out_T_1825 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1827; // @[RegisterRouter.scala:87:24] assign _out_T_1827 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1829; // @[RegisterRouter.scala:87:24] assign _out_T_1829 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1831; // @[RegisterRouter.scala:87:24] assign _out_T_1831 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1833; // @[RegisterRouter.scala:87:24] assign _out_T_1833 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1835; // @[RegisterRouter.scala:87:24] assign _out_T_1835 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1837; // @[RegisterRouter.scala:87:24] assign _out_T_1837 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1839; // @[RegisterRouter.scala:87:24] assign _out_T_1839 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1841; // @[RegisterRouter.scala:87:24] assign _out_T_1841 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1843; // @[RegisterRouter.scala:87:24] assign _out_T_1843 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1845; // @[RegisterRouter.scala:87:24] assign _out_T_1845 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1849; // @[RegisterRouter.scala:87:24] assign _out_T_1849 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1851; // @[RegisterRouter.scala:87:24] assign _out_T_1851 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1853; // @[RegisterRouter.scala:87:24] assign _out_T_1853 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1855; // @[RegisterRouter.scala:87:24] assign _out_T_1855 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1857; // @[RegisterRouter.scala:87:24] assign _out_T_1857 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1859; // @[RegisterRouter.scala:87:24] assign _out_T_1859 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1861; // @[RegisterRouter.scala:87:24] assign _out_T_1861 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1863; // @[RegisterRouter.scala:87:24] assign _out_T_1863 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1865; // @[RegisterRouter.scala:87:24] assign _out_T_1865 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1867; // @[RegisterRouter.scala:87:24] assign _out_T_1867 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1869; // @[RegisterRouter.scala:87:24] assign _out_T_1869 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1871; // @[RegisterRouter.scala:87:24] assign _out_T_1871 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1873; // @[RegisterRouter.scala:87:24] assign _out_T_1873 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1875; // @[RegisterRouter.scala:87:24] assign _out_T_1875 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1879; // @[RegisterRouter.scala:87:24] assign _out_T_1879 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1881; // @[RegisterRouter.scala:87:24] assign _out_T_1881 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1883; // @[RegisterRouter.scala:87:24] assign _out_T_1883 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1885; // @[RegisterRouter.scala:87:24] assign _out_T_1885 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1887; // @[RegisterRouter.scala:87:24] assign _out_T_1887 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1889; // @[RegisterRouter.scala:87:24] assign _out_T_1889 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1891; // @[RegisterRouter.scala:87:24] assign _out_T_1891 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1893; // @[RegisterRouter.scala:87:24] assign _out_T_1893 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1895; // @[RegisterRouter.scala:87:24] assign _out_T_1895 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1897; // @[RegisterRouter.scala:87:24] assign _out_T_1897 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1899; // @[RegisterRouter.scala:87:24] assign _out_T_1899 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1901; // @[RegisterRouter.scala:87:24] assign _out_T_1901 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1903; // @[RegisterRouter.scala:87:24] assign _out_T_1903 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1905; // @[RegisterRouter.scala:87:24] assign _out_T_1905 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1907; // @[RegisterRouter.scala:87:24] assign _out_T_1907 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1909; // @[RegisterRouter.scala:87:24] assign _out_T_1909 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_138 = _out_T_1601; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_249 = _out_T_1603; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_234 = _out_T_1605; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_170 = _out_T_1607; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_115 = _out_T_1609; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_217 = _out_T_1611; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_247 = _out_T_1613; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_202 = _out_T_1615; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_142 = _out_T_1617; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_153 = _out_T_1619; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_174 = _out_T_1621; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_185 = _out_T_1623; // @[MuxLiteral.scala:49:48] wire _GEN_20 = out_findex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1624; // @[RegisterRouter.scala:87:24] assign _out_T_1624 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1640; // @[RegisterRouter.scala:87:24] assign _out_T_1640 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1666; // @[RegisterRouter.scala:87:24] assign _out_T_1666 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1678; // @[RegisterRouter.scala:87:24] assign _out_T_1678 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1716; // @[RegisterRouter.scala:87:24] assign _out_T_1716 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1724; // @[RegisterRouter.scala:87:24] assign _out_T_1724 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1742; // @[RegisterRouter.scala:87:24] assign _out_T_1742 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1756; // @[RegisterRouter.scala:87:24] assign _out_T_1756 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1822; // @[RegisterRouter.scala:87:24] assign _out_T_1822 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1846; // @[RegisterRouter.scala:87:24] assign _out_T_1846 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1876; // @[RegisterRouter.scala:87:24] assign _out_T_1876 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _GEN_21 = out_bindex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1625; // @[RegisterRouter.scala:87:24] assign _out_T_1625 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1641; // @[RegisterRouter.scala:87:24] assign _out_T_1641 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1667; // @[RegisterRouter.scala:87:24] assign _out_T_1667 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1679; // @[RegisterRouter.scala:87:24] assign _out_T_1679 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1717; // @[RegisterRouter.scala:87:24] assign _out_T_1717 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1725; // @[RegisterRouter.scala:87:24] assign _out_T_1725 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1743; // @[RegisterRouter.scala:87:24] assign _out_T_1743 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1757; // @[RegisterRouter.scala:87:24] assign _out_T_1757 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1823; // @[RegisterRouter.scala:87:24] assign _out_T_1823 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1847; // @[RegisterRouter.scala:87:24] assign _out_T_1847 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1877; // @[RegisterRouter.scala:87:24] assign _out_T_1877 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_1 = _out_T_1625; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_184 = _out_T_1627; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_110 = _out_T_1629; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_196 = _out_T_1631; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_157 = _out_T_1633; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_189 = _out_T_1635; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_152 = _out_T_1637; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_228 = _out_T_1639; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_5 = _out_T_1641; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_216 = _out_T_1643; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_164 = _out_T_1645; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_179 = _out_T_1647; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_106 = _out_T_1649; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_238 = _out_T_1651; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_211 = _out_T_1653; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_253 = _out_T_1655; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_147 = _out_T_1657; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_221 = _out_T_1659; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_132 = _out_T_1661; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_133 = _out_T_1663; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_243 = _out_T_1665; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_9 = _out_T_1667; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_206 = _out_T_1669; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_233 = _out_T_1671; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_248 = _out_T_1673; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_201 = _out_T_1675; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_220 = _out_T_1677; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_4 = _out_T_1679; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_160 = _out_T_1681; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_192 = _out_T_1683; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_137 = _out_T_1685; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_165 = _out_T_1687; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_33 = _out_T_1689; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_229 = _out_T_1691; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_252 = _out_T_1693; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_197 = _out_T_1695; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_224 = _out_T_1697; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_156 = _out_T_1699; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_188 = _out_T_1701; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_169 = _out_T_1703; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_141 = _out_T_1705; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_225 = _out_T_1707; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_193 = _out_T_1709; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_212 = _out_T_1711; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_96 = _out_T_1713; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_109 = _out_T_1715; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_0 = _out_T_1717; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_173 = _out_T_1719; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_129 = _out_T_1721; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_134 = _out_T_1723; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_10 = _out_T_1725; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_205 = _out_T_1727; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_128 = _out_T_1729; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_237 = _out_T_1731; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_105 = _out_T_1733; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_244 = _out_T_1735; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_166 = _out_T_1737; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_32 = _out_T_1739; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_148 = _out_T_1741; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_8 = _out_T_1743; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_161 = _out_T_1745; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_180 = _out_T_1747; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_149 = _out_T_1749; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_176 = _out_T_1751; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_191 = _out_T_1753; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_204 = _out_T_1755; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_3 = _out_T_1757; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_144 = _out_T_1759; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_236 = _out_T_1761; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_181 = _out_T_1763; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_159 = _out_T_1765; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_187 = _out_T_1767; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_172 = _out_T_1769; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_113 = _out_T_1771; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_219 = _out_T_1773; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_230 = _out_T_1775; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_245 = _out_T_1777; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_208 = _out_T_1779; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_103 = _out_T_1781; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_140 = _out_T_1783; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_213 = _out_T_1785; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_155 = _out_T_1787; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_198 = _out_T_1789; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_108 = _out_T_1791; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_240 = _out_T_1793; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_251 = _out_T_1795; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_130 = _out_T_1797; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_223 = _out_T_1799; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_135 = _out_T_1801; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_226 = _out_T_1803; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_241 = _out_T_1805; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_167 = _out_T_1807; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_162 = _out_T_1809; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_255 = _out_T_1811; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_209 = _out_T_1813; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_112 = _out_T_1815; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_194 = _out_T_1817; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_145 = _out_T_1819; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_150 = _out_T_1821; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_7 = _out_T_1823; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_199 = _out_T_1825; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_177 = _out_T_1827; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_182 = _out_T_1829; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_154 = _out_T_1831; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_175 = _out_T_1833; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_143 = _out_T_1835; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_203 = _out_T_1837; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_218 = _out_T_1839; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_104 = _out_T_1841; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_250 = _out_T_1843; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_231 = _out_T_1845; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_2 = _out_T_1847; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_158 = _out_T_1849; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_186 = _out_T_1851; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_114 = _out_T_1853; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_171 = _out_T_1855; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_139 = _out_T_1857; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_207 = _out_T_1859; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_214 = _out_T_1861; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_235 = _out_T_1863; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_246 = _out_T_1865; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_151 = _out_T_1867; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_146 = _out_T_1869; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_190 = _out_T_1871; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_183 = _out_T_1873; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_168 = _out_T_1875; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_6 = _out_T_1877; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_210 = _out_T_1879; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_107 = _out_T_1881; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_136 = _out_T_1883; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_195 = _out_T_1885; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_239 = _out_T_1887; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_242 = _out_T_1889; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_131 = _out_T_1891; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_178 = _out_T_1893; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_163 = _out_T_1895; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_200 = _out_T_1897; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_111 = _out_T_1899; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_215 = _out_T_1901; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_222 = _out_T_1903; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_232 = _out_T_1905; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_254 = _out_T_1907; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_227 = _out_T_1909; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_0; // @[RegisterRouter.scala:87:24] wire out_roready_1_1; // @[RegisterRouter.scala:87:24] wire out_roready_1_2; // @[RegisterRouter.scala:87:24] wire out_roready_1_3; // @[RegisterRouter.scala:87:24] wire out_roready_1_4; // @[RegisterRouter.scala:87:24] wire out_roready_1_5; // @[RegisterRouter.scala:87:24] wire out_roready_1_6; // @[RegisterRouter.scala:87:24] wire out_roready_1_7; // @[RegisterRouter.scala:87:24] wire out_roready_1_8; // @[RegisterRouter.scala:87:24] wire out_roready_1_9; // @[RegisterRouter.scala:87:24] wire out_roready_1_10; // @[RegisterRouter.scala:87:24] wire out_roready_1_11; // @[RegisterRouter.scala:87:24] wire out_roready_1_12; // @[RegisterRouter.scala:87:24] wire out_roready_1_13; // @[RegisterRouter.scala:87:24] wire out_roready_1_14; // @[RegisterRouter.scala:87:24] wire out_roready_1_15; // @[RegisterRouter.scala:87:24] wire out_roready_1_16; // @[RegisterRouter.scala:87:24] wire out_roready_1_17; // @[RegisterRouter.scala:87:24] wire out_roready_1_18; // @[RegisterRouter.scala:87:24] wire out_roready_1_19; // @[RegisterRouter.scala:87:24] wire out_roready_1_20; // @[RegisterRouter.scala:87:24] wire out_roready_1_21; // @[RegisterRouter.scala:87:24] wire out_roready_1_22; // @[RegisterRouter.scala:87:24] wire out_roready_1_23; // @[RegisterRouter.scala:87:24] wire out_roready_1_24; // @[RegisterRouter.scala:87:24] wire out_roready_1_25; // @[RegisterRouter.scala:87:24] wire out_roready_1_26; // @[RegisterRouter.scala:87:24] wire out_roready_1_27; // @[RegisterRouter.scala:87:24] wire out_roready_1_28; // @[RegisterRouter.scala:87:24] wire out_roready_1_29; // @[RegisterRouter.scala:87:24] wire out_roready_1_30; // @[RegisterRouter.scala:87:24] wire out_roready_1_31; // @[RegisterRouter.scala:87:24] wire out_roready_1_32; // @[RegisterRouter.scala:87:24] wire out_roready_1_33; // @[RegisterRouter.scala:87:24] wire out_roready_1_34; // @[RegisterRouter.scala:87:24] wire out_roready_1_35; // @[RegisterRouter.scala:87:24] wire out_roready_1_36; // @[RegisterRouter.scala:87:24] wire out_roready_1_37; // @[RegisterRouter.scala:87:24] wire out_roready_1_38; // @[RegisterRouter.scala:87:24] wire out_roready_1_39; // @[RegisterRouter.scala:87:24] wire out_roready_1_40; // @[RegisterRouter.scala:87:24] wire out_roready_1_41; // @[RegisterRouter.scala:87:24] wire out_roready_1_42; // @[RegisterRouter.scala:87:24] wire out_roready_1_43; // @[RegisterRouter.scala:87:24] wire out_roready_1_44; // @[RegisterRouter.scala:87:24] wire out_roready_1_45; // @[RegisterRouter.scala:87:24] wire out_roready_1_46; // @[RegisterRouter.scala:87:24] wire out_roready_1_47; // @[RegisterRouter.scala:87:24] wire out_roready_1_48; // @[RegisterRouter.scala:87:24] wire out_roready_1_49; // @[RegisterRouter.scala:87:24] wire out_roready_1_50; // @[RegisterRouter.scala:87:24] wire out_roready_1_51; // @[RegisterRouter.scala:87:24] wire out_roready_1_52; // @[RegisterRouter.scala:87:24] wire out_roready_1_53; // @[RegisterRouter.scala:87:24] wire out_roready_1_54; // @[RegisterRouter.scala:87:24] wire out_roready_1_55; // @[RegisterRouter.scala:87:24] wire out_roready_1_56; // @[RegisterRouter.scala:87:24] wire out_roready_1_57; // @[RegisterRouter.scala:87:24] wire out_roready_1_58; // @[RegisterRouter.scala:87:24] wire out_roready_1_59; // @[RegisterRouter.scala:87:24] wire out_roready_1_60; // @[RegisterRouter.scala:87:24] wire out_roready_1_61; // @[RegisterRouter.scala:87:24] wire out_roready_1_62; // @[RegisterRouter.scala:87:24] wire out_roready_1_63; // @[RegisterRouter.scala:87:24] wire out_roready_1_64; // @[RegisterRouter.scala:87:24] wire out_roready_1_65; // @[RegisterRouter.scala:87:24] wire out_roready_1_66; // @[RegisterRouter.scala:87:24] wire out_roready_1_67; // @[RegisterRouter.scala:87:24] wire out_roready_1_68; // @[RegisterRouter.scala:87:24] wire out_roready_1_69; // @[RegisterRouter.scala:87:24] wire out_roready_1_70; // @[RegisterRouter.scala:87:24] wire out_roready_1_71; // @[RegisterRouter.scala:87:24] wire out_roready_1_72; // @[RegisterRouter.scala:87:24] wire out_roready_1_73; // @[RegisterRouter.scala:87:24] wire out_roready_1_74; // @[RegisterRouter.scala:87:24] wire out_roready_1_75; // @[RegisterRouter.scala:87:24] wire out_roready_1_76; // @[RegisterRouter.scala:87:24] wire out_roready_1_77; // @[RegisterRouter.scala:87:24] wire out_roready_1_78; // @[RegisterRouter.scala:87:24] wire out_roready_1_79; // @[RegisterRouter.scala:87:24] wire out_roready_1_80; // @[RegisterRouter.scala:87:24] wire out_roready_1_81; // @[RegisterRouter.scala:87:24] wire out_roready_1_82; // @[RegisterRouter.scala:87:24] wire out_roready_1_83; // @[RegisterRouter.scala:87:24] wire out_roready_1_84; // @[RegisterRouter.scala:87:24] wire out_roready_1_85; // @[RegisterRouter.scala:87:24] wire out_roready_1_86; // @[RegisterRouter.scala:87:24] wire out_roready_1_87; // @[RegisterRouter.scala:87:24] wire out_roready_1_88; // @[RegisterRouter.scala:87:24] wire out_roready_1_89; // @[RegisterRouter.scala:87:24] wire out_roready_1_90; // @[RegisterRouter.scala:87:24] wire out_roready_1_91; // @[RegisterRouter.scala:87:24] wire out_roready_1_92; // @[RegisterRouter.scala:87:24] wire out_roready_1_93; // @[RegisterRouter.scala:87:24] wire out_roready_1_94; // @[RegisterRouter.scala:87:24] wire out_roready_1_95; // @[RegisterRouter.scala:87:24] wire out_roready_1_96; // @[RegisterRouter.scala:87:24] wire out_roready_1_97; // @[RegisterRouter.scala:87:24] wire out_roready_1_98; // @[RegisterRouter.scala:87:24] wire out_roready_1_99; // @[RegisterRouter.scala:87:24] wire out_roready_1_100; // @[RegisterRouter.scala:87:24] wire out_roready_1_101; // @[RegisterRouter.scala:87:24] wire out_roready_1_102; // @[RegisterRouter.scala:87:24] wire out_roready_1_103; // @[RegisterRouter.scala:87:24] wire out_roready_1_104; // @[RegisterRouter.scala:87:24] wire out_roready_1_105; // @[RegisterRouter.scala:87:24] wire out_roready_1_106; // @[RegisterRouter.scala:87:24] wire out_roready_1_107; // @[RegisterRouter.scala:87:24] wire out_roready_1_108; // @[RegisterRouter.scala:87:24] wire out_roready_1_109; // @[RegisterRouter.scala:87:24] wire out_roready_1_110; // @[RegisterRouter.scala:87:24] wire out_roready_1_111; // @[RegisterRouter.scala:87:24] wire out_roready_1_112; // @[RegisterRouter.scala:87:24] wire out_roready_1_113; // @[RegisterRouter.scala:87:24] wire out_roready_1_114; // @[RegisterRouter.scala:87:24] wire out_roready_1_115; // @[RegisterRouter.scala:87:24] wire out_roready_1_116; // @[RegisterRouter.scala:87:24] wire out_roready_1_117; // @[RegisterRouter.scala:87:24] wire out_roready_1_118; // @[RegisterRouter.scala:87:24] wire out_roready_1_119; // @[RegisterRouter.scala:87:24] wire out_roready_1_120; // @[RegisterRouter.scala:87:24] wire out_roready_1_121; // @[RegisterRouter.scala:87:24] wire out_roready_1_122; // @[RegisterRouter.scala:87:24] wire out_roready_1_123; // @[RegisterRouter.scala:87:24] wire out_roready_1_124; // @[RegisterRouter.scala:87:24] wire out_roready_1_125; // @[RegisterRouter.scala:87:24] wire out_roready_1_126; // @[RegisterRouter.scala:87:24] wire out_roready_1_127; // @[RegisterRouter.scala:87:24] wire out_roready_1_128; // @[RegisterRouter.scala:87:24] wire out_roready_1_129; // @[RegisterRouter.scala:87:24] wire out_roready_1_130; // @[RegisterRouter.scala:87:24] wire out_roready_1_131; // @[RegisterRouter.scala:87:24] wire out_roready_1_132; // @[RegisterRouter.scala:87:24] wire out_roready_1_133; // @[RegisterRouter.scala:87:24] wire out_roready_1_134; // @[RegisterRouter.scala:87:24] wire out_roready_1_135; // @[RegisterRouter.scala:87:24] wire out_roready_1_136; // @[RegisterRouter.scala:87:24] wire out_roready_1_137; // @[RegisterRouter.scala:87:24] wire out_roready_1_138; // @[RegisterRouter.scala:87:24] wire out_roready_1_139; // @[RegisterRouter.scala:87:24] wire out_roready_1_140; // @[RegisterRouter.scala:87:24] wire out_roready_1_141; // @[RegisterRouter.scala:87:24] wire out_roready_1_142; // @[RegisterRouter.scala:87:24] wire out_roready_1_143; // @[RegisterRouter.scala:87:24] wire out_roready_1_144; // @[RegisterRouter.scala:87:24] wire out_roready_1_145; // @[RegisterRouter.scala:87:24] wire out_roready_1_146; // @[RegisterRouter.scala:87:24] wire out_roready_1_147; // @[RegisterRouter.scala:87:24] wire out_roready_1_148; // @[RegisterRouter.scala:87:24] wire out_roready_1_149; // @[RegisterRouter.scala:87:24] wire out_roready_1_150; // @[RegisterRouter.scala:87:24] wire out_roready_1_151; // @[RegisterRouter.scala:87:24] wire out_roready_1_152; // @[RegisterRouter.scala:87:24] wire out_roready_1_153; // @[RegisterRouter.scala:87:24] wire out_roready_1_154; // @[RegisterRouter.scala:87:24] wire out_roready_1_155; // @[RegisterRouter.scala:87:24] wire out_roready_1_156; // @[RegisterRouter.scala:87:24] wire out_roready_1_157; // @[RegisterRouter.scala:87:24] wire out_roready_1_158; // @[RegisterRouter.scala:87:24] wire out_roready_1_159; // @[RegisterRouter.scala:87:24] wire out_roready_1_160; // @[RegisterRouter.scala:87:24] wire out_roready_1_161; // @[RegisterRouter.scala:87:24] wire out_roready_1_162; // @[RegisterRouter.scala:87:24] wire out_roready_1_163; // @[RegisterRouter.scala:87:24] wire out_roready_1_164; // @[RegisterRouter.scala:87:24] wire out_roready_1_165; // @[RegisterRouter.scala:87:24] wire out_roready_1_166; // @[RegisterRouter.scala:87:24] wire out_roready_1_167; // @[RegisterRouter.scala:87:24] wire out_roready_1_168; // @[RegisterRouter.scala:87:24] wire out_roready_1_169; // @[RegisterRouter.scala:87:24] wire out_roready_1_170; // @[RegisterRouter.scala:87:24] wire out_roready_1_171; // @[RegisterRouter.scala:87:24] wire out_roready_1_172; // @[RegisterRouter.scala:87:24] wire out_roready_1_173; // @[RegisterRouter.scala:87:24] wire out_roready_1_174; // @[RegisterRouter.scala:87:24] wire out_roready_1_175; // @[RegisterRouter.scala:87:24] wire out_roready_1_176; // @[RegisterRouter.scala:87:24] wire out_roready_1_177; // @[RegisterRouter.scala:87:24] wire out_roready_1_178; // @[RegisterRouter.scala:87:24] wire out_roready_1_179; // @[RegisterRouter.scala:87:24] wire out_roready_1_180; // @[RegisterRouter.scala:87:24] wire out_roready_1_181; // @[RegisterRouter.scala:87:24] wire out_roready_1_182; // @[RegisterRouter.scala:87:24] wire out_roready_1_183; // @[RegisterRouter.scala:87:24] wire out_roready_1_184; // @[RegisterRouter.scala:87:24] wire out_roready_1_185; // @[RegisterRouter.scala:87:24] wire out_roready_1_186; // @[RegisterRouter.scala:87:24] wire out_roready_1_187; // @[RegisterRouter.scala:87:24] wire out_roready_1_188; // @[RegisterRouter.scala:87:24] wire out_roready_1_189; // @[RegisterRouter.scala:87:24] wire out_roready_1_190; // @[RegisterRouter.scala:87:24] wire out_roready_1_191; // @[RegisterRouter.scala:87:24] wire out_roready_1_192; // @[RegisterRouter.scala:87:24] wire out_roready_1_193; // @[RegisterRouter.scala:87:24] wire out_roready_1_194; // @[RegisterRouter.scala:87:24] wire out_roready_1_195; // @[RegisterRouter.scala:87:24] wire out_roready_1_196; // @[RegisterRouter.scala:87:24] wire out_roready_1_197; // @[RegisterRouter.scala:87:24] wire out_roready_1_198; // @[RegisterRouter.scala:87:24] wire out_roready_1_199; // @[RegisterRouter.scala:87:24] wire out_roready_1_200; // @[RegisterRouter.scala:87:24] wire out_roready_1_201; // @[RegisterRouter.scala:87:24] wire out_roready_1_202; // @[RegisterRouter.scala:87:24] wire out_roready_1_203; // @[RegisterRouter.scala:87:24] wire out_roready_1_204; // @[RegisterRouter.scala:87:24] wire out_roready_1_205; // @[RegisterRouter.scala:87:24] wire out_roready_1_206; // @[RegisterRouter.scala:87:24] wire out_roready_1_207; // @[RegisterRouter.scala:87:24] wire out_roready_1_208; // @[RegisterRouter.scala:87:24] wire out_roready_1_209; // @[RegisterRouter.scala:87:24] wire out_roready_1_210; // @[RegisterRouter.scala:87:24] wire out_roready_1_211; // @[RegisterRouter.scala:87:24] wire out_roready_1_212; // @[RegisterRouter.scala:87:24] wire out_roready_1_213; // @[RegisterRouter.scala:87:24] wire out_roready_1_214; // @[RegisterRouter.scala:87:24] wire out_roready_1_215; // @[RegisterRouter.scala:87:24] wire out_roready_1_216; // @[RegisterRouter.scala:87:24] wire out_roready_1_217; // @[RegisterRouter.scala:87:24] wire out_roready_1_218; // @[RegisterRouter.scala:87:24] wire out_roready_1_219; // @[RegisterRouter.scala:87:24] wire out_roready_1_220; // @[RegisterRouter.scala:87:24] wire out_roready_1_221; // @[RegisterRouter.scala:87:24] wire out_roready_1_222; // @[RegisterRouter.scala:87:24] wire out_roready_1_223; // @[RegisterRouter.scala:87:24] wire out_roready_1_224; // @[RegisterRouter.scala:87:24] wire out_roready_1_225; // @[RegisterRouter.scala:87:24] wire out_roready_1_226; // @[RegisterRouter.scala:87:24] wire out_roready_1_227; // @[RegisterRouter.scala:87:24] wire out_roready_1_228; // @[RegisterRouter.scala:87:24] wire out_roready_1_229; // @[RegisterRouter.scala:87:24] wire out_roready_1_230; // @[RegisterRouter.scala:87:24] wire out_roready_1_231; // @[RegisterRouter.scala:87:24] wire out_roready_1_232; // @[RegisterRouter.scala:87:24] wire out_roready_1_233; // @[RegisterRouter.scala:87:24] wire out_roready_1_234; // @[RegisterRouter.scala:87:24] wire out_roready_1_235; // @[RegisterRouter.scala:87:24] wire out_roready_1_236; // @[RegisterRouter.scala:87:24] wire out_roready_1_237; // @[RegisterRouter.scala:87:24] wire out_roready_1_238; // @[RegisterRouter.scala:87:24] wire out_roready_1_239; // @[RegisterRouter.scala:87:24] wire out_roready_1_240; // @[RegisterRouter.scala:87:24] wire out_roready_1_241; // @[RegisterRouter.scala:87:24] wire out_roready_1_242; // @[RegisterRouter.scala:87:24] wire out_roready_1_243; // @[RegisterRouter.scala:87:24] wire out_roready_1_244; // @[RegisterRouter.scala:87:24] wire out_roready_1_245; // @[RegisterRouter.scala:87:24] wire out_roready_1_246; // @[RegisterRouter.scala:87:24] wire out_roready_1_247; // @[RegisterRouter.scala:87:24] wire out_roready_1_248; // @[RegisterRouter.scala:87:24] wire out_roready_1_249; // @[RegisterRouter.scala:87:24] wire out_roready_1_250; // @[RegisterRouter.scala:87:24] wire out_roready_1_251; // @[RegisterRouter.scala:87:24] wire out_roready_1_252; // @[RegisterRouter.scala:87:24] wire out_roready_1_253; // @[RegisterRouter.scala:87:24] wire out_roready_1_254; // @[RegisterRouter.scala:87:24] wire out_roready_1_255; // @[RegisterRouter.scala:87:24] wire out_roready_1_256; // @[RegisterRouter.scala:87:24] wire out_roready_1_257; // @[RegisterRouter.scala:87:24] wire out_roready_1_258; // @[RegisterRouter.scala:87:24] wire out_roready_1_259; // @[RegisterRouter.scala:87:24] wire out_roready_1_260; // @[RegisterRouter.scala:87:24] wire out_roready_1_261; // @[RegisterRouter.scala:87:24] wire out_roready_1_262; // @[RegisterRouter.scala:87:24] wire out_roready_1_263; // @[RegisterRouter.scala:87:24] wire out_roready_1_264; // @[RegisterRouter.scala:87:24] wire out_roready_1_265; // @[RegisterRouter.scala:87:24] wire out_roready_1_266; // @[RegisterRouter.scala:87:24] wire out_roready_1_267; // @[RegisterRouter.scala:87:24] wire out_roready_1_268; // @[RegisterRouter.scala:87:24] wire out_roready_1_269; // @[RegisterRouter.scala:87:24] wire out_roready_1_270; // @[RegisterRouter.scala:87:24] wire out_roready_1_271; // @[RegisterRouter.scala:87:24] wire out_roready_1_272; // @[RegisterRouter.scala:87:24] wire out_roready_1_273; // @[RegisterRouter.scala:87:24] wire out_roready_1_274; // @[RegisterRouter.scala:87:24] wire out_roready_1_275; // @[RegisterRouter.scala:87:24] wire out_roready_1_276; // @[RegisterRouter.scala:87:24] wire out_roready_1_277; // @[RegisterRouter.scala:87:24] wire out_roready_1_278; // @[RegisterRouter.scala:87:24] wire out_roready_1_279; // @[RegisterRouter.scala:87:24] wire out_roready_1_280; // @[RegisterRouter.scala:87:24] wire out_roready_1_281; // @[RegisterRouter.scala:87:24] wire out_roready_1_282; // @[RegisterRouter.scala:87:24] wire out_roready_1_283; // @[RegisterRouter.scala:87:24] wire out_roready_1_284; // @[RegisterRouter.scala:87:24] wire out_roready_1_285; // @[RegisterRouter.scala:87:24] wire out_roready_1_286; // @[RegisterRouter.scala:87:24] wire out_roready_1_287; // @[RegisterRouter.scala:87:24] wire out_roready_1_288; // @[RegisterRouter.scala:87:24] wire out_roready_1_289; // @[RegisterRouter.scala:87:24] wire out_roready_1_290; // @[RegisterRouter.scala:87:24] wire out_roready_1_291; // @[RegisterRouter.scala:87:24] wire out_roready_1_292; // @[RegisterRouter.scala:87:24] wire out_roready_1_293; // @[RegisterRouter.scala:87:24] wire out_roready_1_294; // @[RegisterRouter.scala:87:24] wire out_roready_1_295; // @[RegisterRouter.scala:87:24] wire out_roready_1_296; // @[RegisterRouter.scala:87:24] wire out_roready_1_297; // @[RegisterRouter.scala:87:24] wire out_roready_1_298; // @[RegisterRouter.scala:87:24] wire out_roready_1_299; // @[RegisterRouter.scala:87:24] wire out_roready_1_300; // @[RegisterRouter.scala:87:24] wire out_roready_1_301; // @[RegisterRouter.scala:87:24] wire out_roready_1_302; // @[RegisterRouter.scala:87:24] wire out_roready_1_303; // @[RegisterRouter.scala:87:24] wire out_roready_1_304; // @[RegisterRouter.scala:87:24] wire out_roready_1_305; // @[RegisterRouter.scala:87:24] wire out_roready_1_306; // @[RegisterRouter.scala:87:24] wire out_roready_1_307; // @[RegisterRouter.scala:87:24] wire out_roready_1_308; // @[RegisterRouter.scala:87:24] wire out_roready_1_309; // @[RegisterRouter.scala:87:24] wire out_roready_1_310; // @[RegisterRouter.scala:87:24] wire out_roready_1_311; // @[RegisterRouter.scala:87:24] wire out_roready_1_312; // @[RegisterRouter.scala:87:24] wire out_roready_1_313; // @[RegisterRouter.scala:87:24] wire out_roready_1_314; // @[RegisterRouter.scala:87:24] wire out_roready_1_315; // @[RegisterRouter.scala:87:24] wire out_roready_1_316; // @[RegisterRouter.scala:87:24] wire out_roready_1_317; // @[RegisterRouter.scala:87:24] wire out_roready_1_318; // @[RegisterRouter.scala:87:24] wire out_roready_1_319; // @[RegisterRouter.scala:87:24] wire out_roready_1_320; // @[RegisterRouter.scala:87:24] wire out_roready_1_321; // @[RegisterRouter.scala:87:24] wire out_roready_1_322; // @[RegisterRouter.scala:87:24] wire out_roready_1_323; // @[RegisterRouter.scala:87:24] wire out_roready_1_324; // @[RegisterRouter.scala:87:24] wire out_roready_1_325; // @[RegisterRouter.scala:87:24] wire out_roready_1_326; // @[RegisterRouter.scala:87:24] wire out_roready_1_327; // @[RegisterRouter.scala:87:24] wire out_roready_1_328; // @[RegisterRouter.scala:87:24] wire out_roready_1_329; // @[RegisterRouter.scala:87:24] wire out_roready_1_330; // @[RegisterRouter.scala:87:24] wire out_roready_1_331; // @[RegisterRouter.scala:87:24] wire out_roready_1_332; // @[RegisterRouter.scala:87:24] wire out_roready_1_333; // @[RegisterRouter.scala:87:24] wire out_roready_1_334; // @[RegisterRouter.scala:87:24] wire out_roready_1_335; // @[RegisterRouter.scala:87:24] wire out_roready_1_336; // @[RegisterRouter.scala:87:24] wire out_roready_1_337; // @[RegisterRouter.scala:87:24] wire out_roready_1_338; // @[RegisterRouter.scala:87:24] wire out_roready_1_339; // @[RegisterRouter.scala:87:24] wire out_roready_1_340; // @[RegisterRouter.scala:87:24] wire out_roready_1_341; // @[RegisterRouter.scala:87:24] wire out_roready_1_342; // @[RegisterRouter.scala:87:24] wire out_roready_1_343; // @[RegisterRouter.scala:87:24] wire out_roready_1_344; // @[RegisterRouter.scala:87:24] wire out_roready_1_345; // @[RegisterRouter.scala:87:24] wire out_roready_1_346; // @[RegisterRouter.scala:87:24] wire out_roready_1_347; // @[RegisterRouter.scala:87:24] wire out_roready_1_348; // @[RegisterRouter.scala:87:24] wire out_roready_1_349; // @[RegisterRouter.scala:87:24] wire out_roready_1_350; // @[RegisterRouter.scala:87:24] wire out_roready_1_351; // @[RegisterRouter.scala:87:24] wire out_roready_1_352; // @[RegisterRouter.scala:87:24] wire out_roready_1_353; // @[RegisterRouter.scala:87:24] wire out_roready_1_354; // @[RegisterRouter.scala:87:24] wire out_roready_1_355; // @[RegisterRouter.scala:87:24] wire out_roready_1_356; // @[RegisterRouter.scala:87:24] wire out_roready_1_357; // @[RegisterRouter.scala:87:24] wire out_roready_1_358; // @[RegisterRouter.scala:87:24] wire out_roready_1_359; // @[RegisterRouter.scala:87:24] wire out_roready_1_360; // @[RegisterRouter.scala:87:24] wire out_roready_1_361; // @[RegisterRouter.scala:87:24] wire out_roready_1_362; // @[RegisterRouter.scala:87:24] wire out_roready_1_363; // @[RegisterRouter.scala:87:24] wire out_roready_1_364; // @[RegisterRouter.scala:87:24] wire out_roready_1_365; // @[RegisterRouter.scala:87:24] wire out_roready_1_366; // @[RegisterRouter.scala:87:24] wire out_roready_1_367; // @[RegisterRouter.scala:87:24] wire out_roready_1_368; // @[RegisterRouter.scala:87:24] wire out_roready_1_369; // @[RegisterRouter.scala:87:24] wire out_roready_1_370; // @[RegisterRouter.scala:87:24] wire out_roready_1_371; // @[RegisterRouter.scala:87:24] wire out_roready_1_372; // @[RegisterRouter.scala:87:24] wire out_roready_1_373; // @[RegisterRouter.scala:87:24] wire out_roready_1_374; // @[RegisterRouter.scala:87:24] wire out_roready_1_375; // @[RegisterRouter.scala:87:24] wire out_roready_1_376; // @[RegisterRouter.scala:87:24] wire out_roready_1_377; // @[RegisterRouter.scala:87:24] wire out_roready_1_378; // @[RegisterRouter.scala:87:24] wire out_roready_1_379; // @[RegisterRouter.scala:87:24] wire out_roready_1_380; // @[RegisterRouter.scala:87:24] wire out_roready_1_381; // @[RegisterRouter.scala:87:24] wire out_roready_1_382; // @[RegisterRouter.scala:87:24] wire out_roready_1_383; // @[RegisterRouter.scala:87:24] wire out_roready_1_384; // @[RegisterRouter.scala:87:24] wire out_roready_1_385; // @[RegisterRouter.scala:87:24] wire out_roready_1_386; // @[RegisterRouter.scala:87:24] wire out_roready_1_387; // @[RegisterRouter.scala:87:24] wire out_roready_1_388; // @[RegisterRouter.scala:87:24] wire out_roready_1_389; // @[RegisterRouter.scala:87:24] wire out_roready_1_390; // @[RegisterRouter.scala:87:24] wire out_roready_1_391; // @[RegisterRouter.scala:87:24] wire out_roready_1_392; // @[RegisterRouter.scala:87:24] wire out_roready_1_393; // @[RegisterRouter.scala:87:24] wire out_roready_1_394; // @[RegisterRouter.scala:87:24] wire out_roready_1_395; // @[RegisterRouter.scala:87:24] wire out_roready_1_396; // @[RegisterRouter.scala:87:24] wire out_roready_1_397; // @[RegisterRouter.scala:87:24] wire out_roready_1_398; // @[RegisterRouter.scala:87:24] wire out_roready_1_399; // @[RegisterRouter.scala:87:24] wire out_roready_1_400; // @[RegisterRouter.scala:87:24] wire out_roready_1_401; // @[RegisterRouter.scala:87:24] wire out_roready_1_402; // @[RegisterRouter.scala:87:24] wire out_roready_1_403; // @[RegisterRouter.scala:87:24] wire out_roready_1_404; // @[RegisterRouter.scala:87:24] wire out_roready_1_405; // @[RegisterRouter.scala:87:24] wire out_roready_1_406; // @[RegisterRouter.scala:87:24] wire out_roready_1_407; // @[RegisterRouter.scala:87:24] wire out_roready_1_408; // @[RegisterRouter.scala:87:24] wire out_roready_1_409; // @[RegisterRouter.scala:87:24] wire out_roready_1_410; // @[RegisterRouter.scala:87:24] wire out_roready_1_411; // @[RegisterRouter.scala:87:24] wire out_roready_1_412; // @[RegisterRouter.scala:87:24] wire out_roready_1_413; // @[RegisterRouter.scala:87:24] wire out_roready_1_414; // @[RegisterRouter.scala:87:24] wire out_roready_1_415; // @[RegisterRouter.scala:87:24] wire out_roready_1_416; // @[RegisterRouter.scala:87:24] wire out_roready_1_417; // @[RegisterRouter.scala:87:24] wire out_roready_1_418; // @[RegisterRouter.scala:87:24] wire out_roready_1_419; // @[RegisterRouter.scala:87:24] wire out_roready_1_420; // @[RegisterRouter.scala:87:24] wire out_roready_1_421; // @[RegisterRouter.scala:87:24] wire out_roready_1_422; // @[RegisterRouter.scala:87:24] wire out_roready_1_423; // @[RegisterRouter.scala:87:24] wire out_roready_1_424; // @[RegisterRouter.scala:87:24] wire out_roready_1_425; // @[RegisterRouter.scala:87:24] wire out_roready_1_426; // @[RegisterRouter.scala:87:24] wire out_roready_1_427; // @[RegisterRouter.scala:87:24] wire out_roready_1_428; // @[RegisterRouter.scala:87:24] wire out_roready_1_429; // @[RegisterRouter.scala:87:24] wire out_roready_1_430; // @[RegisterRouter.scala:87:24] wire out_roready_1_431; // @[RegisterRouter.scala:87:24] wire out_roready_1_432; // @[RegisterRouter.scala:87:24] wire out_roready_1_433; // @[RegisterRouter.scala:87:24] wire out_roready_1_434; // @[RegisterRouter.scala:87:24] wire out_roready_1_435; // @[RegisterRouter.scala:87:24] wire out_roready_1_436; // @[RegisterRouter.scala:87:24] wire out_roready_1_437; // @[RegisterRouter.scala:87:24] wire out_roready_1_438; // @[RegisterRouter.scala:87:24] wire out_roready_1_439; // @[RegisterRouter.scala:87:24] wire out_roready_1_440; // @[RegisterRouter.scala:87:24] wire out_roready_1_441; // @[RegisterRouter.scala:87:24] wire out_roready_1_442; // @[RegisterRouter.scala:87:24] wire out_roready_1_443; // @[RegisterRouter.scala:87:24] wire out_roready_1_444; // @[RegisterRouter.scala:87:24] wire out_roready_1_445; // @[RegisterRouter.scala:87:24] wire out_roready_1_446; // @[RegisterRouter.scala:87:24] wire out_roready_1_447; // @[RegisterRouter.scala:87:24] wire out_roready_1_448; // @[RegisterRouter.scala:87:24] wire out_roready_1_449; // @[RegisterRouter.scala:87:24] wire out_roready_1_450; // @[RegisterRouter.scala:87:24] wire out_roready_1_451; // @[RegisterRouter.scala:87:24] wire out_roready_1_452; // @[RegisterRouter.scala:87:24] wire out_roready_1_453; // @[RegisterRouter.scala:87:24] wire out_roready_1_454; // @[RegisterRouter.scala:87:24] wire out_roready_1_455; // @[RegisterRouter.scala:87:24] wire out_roready_1_456; // @[RegisterRouter.scala:87:24] wire out_roready_1_457; // @[RegisterRouter.scala:87:24] wire out_roready_1_458; // @[RegisterRouter.scala:87:24] wire out_roready_1_459; // @[RegisterRouter.scala:87:24] wire out_roready_1_460; // @[RegisterRouter.scala:87:24] wire out_roready_1_461; // @[RegisterRouter.scala:87:24] wire out_roready_1_462; // @[RegisterRouter.scala:87:24] wire out_roready_1_463; // @[RegisterRouter.scala:87:24] wire out_roready_1_464; // @[RegisterRouter.scala:87:24] wire out_roready_1_465; // @[RegisterRouter.scala:87:24] wire out_roready_1_466; // @[RegisterRouter.scala:87:24] wire out_roready_1_467; // @[RegisterRouter.scala:87:24] wire out_roready_1_468; // @[RegisterRouter.scala:87:24] wire out_roready_1_469; // @[RegisterRouter.scala:87:24] wire out_roready_1_470; // @[RegisterRouter.scala:87:24] wire out_roready_1_471; // @[RegisterRouter.scala:87:24] wire out_roready_1_472; // @[RegisterRouter.scala:87:24] wire out_roready_1_473; // @[RegisterRouter.scala:87:24] wire out_roready_1_474; // @[RegisterRouter.scala:87:24] wire out_roready_1_475; // @[RegisterRouter.scala:87:24] wire out_roready_1_476; // @[RegisterRouter.scala:87:24] wire out_roready_1_477; // @[RegisterRouter.scala:87:24] wire out_roready_1_478; // @[RegisterRouter.scala:87:24] wire out_roready_1_479; // @[RegisterRouter.scala:87:24] wire out_roready_1_480; // @[RegisterRouter.scala:87:24] wire out_roready_1_481; // @[RegisterRouter.scala:87:24] wire out_roready_1_482; // @[RegisterRouter.scala:87:24] wire out_roready_1_483; // @[RegisterRouter.scala:87:24] wire out_roready_1_484; // @[RegisterRouter.scala:87:24] wire out_roready_1_485; // @[RegisterRouter.scala:87:24] wire out_roready_1_486; // @[RegisterRouter.scala:87:24] wire out_roready_1_487; // @[RegisterRouter.scala:87:24] wire out_roready_1_488; // @[RegisterRouter.scala:87:24] wire out_roready_1_489; // @[RegisterRouter.scala:87:24] wire out_roready_1_490; // @[RegisterRouter.scala:87:24] wire out_roready_1_491; // @[RegisterRouter.scala:87:24] wire out_roready_1_492; // @[RegisterRouter.scala:87:24] wire out_roready_1_493; // @[RegisterRouter.scala:87:24] wire out_roready_1_494; // @[RegisterRouter.scala:87:24] wire out_roready_1_495; // @[RegisterRouter.scala:87:24] wire out_roready_1_496; // @[RegisterRouter.scala:87:24] wire out_roready_1_497; // @[RegisterRouter.scala:87:24] wire out_roready_1_498; // @[RegisterRouter.scala:87:24] wire out_roready_1_499; // @[RegisterRouter.scala:87:24] wire out_roready_1_500; // @[RegisterRouter.scala:87:24] wire out_roready_1_501; // @[RegisterRouter.scala:87:24] wire out_roready_1_502; // @[RegisterRouter.scala:87:24] wire out_roready_1_503; // @[RegisterRouter.scala:87:24] wire out_roready_1_504; // @[RegisterRouter.scala:87:24] wire out_roready_1_505; // @[RegisterRouter.scala:87:24] wire out_roready_1_506; // @[RegisterRouter.scala:87:24] wire out_roready_1_507; // @[RegisterRouter.scala:87:24] wire out_roready_1_508; // @[RegisterRouter.scala:87:24] wire out_roready_1_509; // @[RegisterRouter.scala:87:24] wire out_roready_1_510; // @[RegisterRouter.scala:87:24] wire out_roready_1_511; // @[RegisterRouter.scala:87:24] wire out_roready_1_512; // @[RegisterRouter.scala:87:24] wire out_roready_1_513; // @[RegisterRouter.scala:87:24] wire out_roready_1_514; // @[RegisterRouter.scala:87:24] wire out_roready_1_515; // @[RegisterRouter.scala:87:24] wire out_roready_1_516; // @[RegisterRouter.scala:87:24] wire out_roready_1_517; // @[RegisterRouter.scala:87:24] wire out_roready_1_518; // @[RegisterRouter.scala:87:24] wire out_roready_1_519; // @[RegisterRouter.scala:87:24] wire out_roready_1_520; // @[RegisterRouter.scala:87:24] wire out_roready_1_521; // @[RegisterRouter.scala:87:24] wire out_roready_1_522; // @[RegisterRouter.scala:87:24] wire out_roready_1_523; // @[RegisterRouter.scala:87:24] wire out_roready_1_524; // @[RegisterRouter.scala:87:24] wire out_roready_1_525; // @[RegisterRouter.scala:87:24] wire out_roready_1_526; // @[RegisterRouter.scala:87:24] wire out_roready_1_527; // @[RegisterRouter.scala:87:24] wire out_roready_1_528; // @[RegisterRouter.scala:87:24] wire out_roready_1_529; // @[RegisterRouter.scala:87:24] wire out_roready_1_530; // @[RegisterRouter.scala:87:24] wire out_roready_1_531; // @[RegisterRouter.scala:87:24] wire out_roready_1_532; // @[RegisterRouter.scala:87:24] wire out_roready_1_533; // @[RegisterRouter.scala:87:24] wire out_roready_1_534; // @[RegisterRouter.scala:87:24] wire out_roready_1_535; // @[RegisterRouter.scala:87:24] wire out_roready_1_536; // @[RegisterRouter.scala:87:24] wire out_roready_1_537; // @[RegisterRouter.scala:87:24] wire out_roready_1_538; // @[RegisterRouter.scala:87:24] wire out_roready_1_539; // @[RegisterRouter.scala:87:24] wire out_roready_1_540; // @[RegisterRouter.scala:87:24] wire out_roready_1_541; // @[RegisterRouter.scala:87:24] wire out_roready_1_542; // @[RegisterRouter.scala:87:24] wire out_roready_1_543; // @[RegisterRouter.scala:87:24] wire out_roready_1_544; // @[RegisterRouter.scala:87:24] wire out_roready_1_545; // @[RegisterRouter.scala:87:24] wire out_roready_1_546; // @[RegisterRouter.scala:87:24] wire out_roready_1_547; // @[RegisterRouter.scala:87:24] wire out_roready_1_548; // @[RegisterRouter.scala:87:24] wire out_roready_1_549; // @[RegisterRouter.scala:87:24] wire out_roready_1_550; // @[RegisterRouter.scala:87:24] wire out_roready_1_551; // @[RegisterRouter.scala:87:24] wire out_roready_1_552; // @[RegisterRouter.scala:87:24] wire out_roready_1_553; // @[RegisterRouter.scala:87:24] wire out_roready_1_554; // @[RegisterRouter.scala:87:24] wire out_roready_1_555; // @[RegisterRouter.scala:87:24] wire out_roready_1_556; // @[RegisterRouter.scala:87:24] wire out_roready_1_557; // @[RegisterRouter.scala:87:24] wire out_roready_1_558; // @[RegisterRouter.scala:87:24] wire out_roready_1_559; // @[RegisterRouter.scala:87:24] wire out_roready_1_560; // @[RegisterRouter.scala:87:24] wire out_roready_1_561; // @[RegisterRouter.scala:87:24] wire out_roready_1_562; // @[RegisterRouter.scala:87:24] wire out_roready_1_563; // @[RegisterRouter.scala:87:24] wire out_roready_1_564; // @[RegisterRouter.scala:87:24] wire out_roready_1_565; // @[RegisterRouter.scala:87:24] wire out_roready_1_566; // @[RegisterRouter.scala:87:24] wire out_roready_1_567; // @[RegisterRouter.scala:87:24] wire out_roready_1_568; // @[RegisterRouter.scala:87:24] wire out_roready_1_569; // @[RegisterRouter.scala:87:24] wire out_roready_1_570; // @[RegisterRouter.scala:87:24] wire out_roready_1_571; // @[RegisterRouter.scala:87:24] wire out_roready_1_572; // @[RegisterRouter.scala:87:24] wire out_roready_1_573; // @[RegisterRouter.scala:87:24] wire out_roready_1_574; // @[RegisterRouter.scala:87:24] wire out_roready_1_575; // @[RegisterRouter.scala:87:24] wire out_roready_1_576; // @[RegisterRouter.scala:87:24] wire out_roready_1_577; // @[RegisterRouter.scala:87:24] wire out_roready_1_578; // @[RegisterRouter.scala:87:24] wire out_roready_1_579; // @[RegisterRouter.scala:87:24] wire out_roready_1_580; // @[RegisterRouter.scala:87:24] wire out_roready_1_581; // @[RegisterRouter.scala:87:24] wire out_roready_1_582; // @[RegisterRouter.scala:87:24] wire out_roready_1_583; // @[RegisterRouter.scala:87:24] wire out_roready_1_584; // @[RegisterRouter.scala:87:24] wire out_roready_1_585; // @[RegisterRouter.scala:87:24] wire out_roready_1_586; // @[RegisterRouter.scala:87:24] wire out_roready_1_587; // @[RegisterRouter.scala:87:24] wire out_roready_1_588; // @[RegisterRouter.scala:87:24] wire out_roready_1_589; // @[RegisterRouter.scala:87:24] wire out_roready_1_590; // @[RegisterRouter.scala:87:24] wire out_roready_1_591; // @[RegisterRouter.scala:87:24] wire out_roready_1_592; // @[RegisterRouter.scala:87:24] wire out_roready_1_593; // @[RegisterRouter.scala:87:24] wire out_roready_1_594; // @[RegisterRouter.scala:87:24] wire out_roready_1_595; // @[RegisterRouter.scala:87:24] wire out_roready_1_596; // @[RegisterRouter.scala:87:24] wire out_roready_1_597; // @[RegisterRouter.scala:87:24] wire out_roready_1_598; // @[RegisterRouter.scala:87:24] wire out_roready_1_599; // @[RegisterRouter.scala:87:24] wire out_roready_1_600; // @[RegisterRouter.scala:87:24] wire out_roready_1_601; // @[RegisterRouter.scala:87:24] wire out_roready_1_602; // @[RegisterRouter.scala:87:24] wire out_roready_1_603; // @[RegisterRouter.scala:87:24] wire out_roready_1_604; // @[RegisterRouter.scala:87:24] wire out_roready_1_605; // @[RegisterRouter.scala:87:24] wire out_roready_1_606; // @[RegisterRouter.scala:87:24] wire out_roready_1_607; // @[RegisterRouter.scala:87:24] wire out_roready_1_608; // @[RegisterRouter.scala:87:24] wire out_roready_1_609; // @[RegisterRouter.scala:87:24] wire out_roready_1_610; // @[RegisterRouter.scala:87:24] wire out_roready_1_611; // @[RegisterRouter.scala:87:24] wire out_roready_1_612; // @[RegisterRouter.scala:87:24] wire out_roready_1_613; // @[RegisterRouter.scala:87:24] wire out_roready_1_614; // @[RegisterRouter.scala:87:24] wire out_roready_1_615; // @[RegisterRouter.scala:87:24] wire out_roready_1_616; // @[RegisterRouter.scala:87:24] wire out_roready_1_617; // @[RegisterRouter.scala:87:24] wire out_roready_1_618; // @[RegisterRouter.scala:87:24] wire out_roready_1_619; // @[RegisterRouter.scala:87:24] wire out_roready_1_620; // @[RegisterRouter.scala:87:24] wire out_roready_1_621; // @[RegisterRouter.scala:87:24] wire out_roready_1_622; // @[RegisterRouter.scala:87:24] wire out_roready_1_623; // @[RegisterRouter.scala:87:24] wire out_roready_1_624; // @[RegisterRouter.scala:87:24] wire out_roready_1_625; // @[RegisterRouter.scala:87:24] wire out_roready_1_626; // @[RegisterRouter.scala:87:24] wire out_roready_1_627; // @[RegisterRouter.scala:87:24] wire out_roready_1_628; // @[RegisterRouter.scala:87:24] wire out_roready_1_629; // @[RegisterRouter.scala:87:24] wire out_roready_1_630; // @[RegisterRouter.scala:87:24] wire out_roready_1_631; // @[RegisterRouter.scala:87:24] wire out_roready_1_632; // @[RegisterRouter.scala:87:24] wire out_roready_1_633; // @[RegisterRouter.scala:87:24] wire out_roready_1_634; // @[RegisterRouter.scala:87:24] wire out_roready_1_635; // @[RegisterRouter.scala:87:24] wire out_roready_1_636; // @[RegisterRouter.scala:87:24] wire out_roready_1_637; // @[RegisterRouter.scala:87:24] wire out_roready_1_638; // @[RegisterRouter.scala:87:24] wire out_roready_1_639; // @[RegisterRouter.scala:87:24] wire out_roready_1_640; // @[RegisterRouter.scala:87:24] wire out_roready_1_641; // @[RegisterRouter.scala:87:24] wire out_roready_1_642; // @[RegisterRouter.scala:87:24] wire out_roready_1_643; // @[RegisterRouter.scala:87:24] wire out_roready_1_644; // @[RegisterRouter.scala:87:24] wire out_roready_1_645; // @[RegisterRouter.scala:87:24] wire out_roready_1_646; // @[RegisterRouter.scala:87:24] wire out_roready_1_647; // @[RegisterRouter.scala:87:24] wire out_roready_1_648; // @[RegisterRouter.scala:87:24] wire out_roready_1_649; // @[RegisterRouter.scala:87:24] wire out_roready_1_650; // @[RegisterRouter.scala:87:24] wire out_roready_1_651; // @[RegisterRouter.scala:87:24] wire out_roready_1_652; // @[RegisterRouter.scala:87:24] wire out_roready_1_653; // @[RegisterRouter.scala:87:24] wire out_roready_1_654; // @[RegisterRouter.scala:87:24] wire out_roready_1_655; // @[RegisterRouter.scala:87:24] wire out_roready_1_656; // @[RegisterRouter.scala:87:24] wire out_roready_1_657; // @[RegisterRouter.scala:87:24] wire out_roready_1_658; // @[RegisterRouter.scala:87:24] wire out_roready_1_659; // @[RegisterRouter.scala:87:24] wire out_roready_1_660; // @[RegisterRouter.scala:87:24] wire out_roready_1_661; // @[RegisterRouter.scala:87:24] wire out_roready_1_662; // @[RegisterRouter.scala:87:24] wire out_roready_1_663; // @[RegisterRouter.scala:87:24] wire out_roready_1_664; // @[RegisterRouter.scala:87:24] wire out_roready_1_665; // @[RegisterRouter.scala:87:24] wire out_roready_1_666; // @[RegisterRouter.scala:87:24] wire out_roready_1_667; // @[RegisterRouter.scala:87:24] wire out_roready_1_668; // @[RegisterRouter.scala:87:24] wire out_roready_1_669; // @[RegisterRouter.scala:87:24] wire out_roready_1_670; // @[RegisterRouter.scala:87:24] wire out_roready_1_671; // @[RegisterRouter.scala:87:24] wire out_roready_1_672; // @[RegisterRouter.scala:87:24] wire out_roready_1_673; // @[RegisterRouter.scala:87:24] wire out_roready_1_674; // @[RegisterRouter.scala:87:24] wire out_roready_1_675; // @[RegisterRouter.scala:87:24] wire out_roready_1_676; // @[RegisterRouter.scala:87:24] wire out_roready_1_677; // @[RegisterRouter.scala:87:24] wire out_roready_1_678; // @[RegisterRouter.scala:87:24] wire out_roready_1_679; // @[RegisterRouter.scala:87:24] wire out_roready_1_680; // @[RegisterRouter.scala:87:24] wire out_roready_1_681; // @[RegisterRouter.scala:87:24] wire out_roready_1_682; // @[RegisterRouter.scala:87:24] wire out_roready_1_683; // @[RegisterRouter.scala:87:24] wire out_roready_1_684; // @[RegisterRouter.scala:87:24] wire out_roready_1_685; // @[RegisterRouter.scala:87:24] wire out_roready_1_686; // @[RegisterRouter.scala:87:24] wire out_roready_1_687; // @[RegisterRouter.scala:87:24] wire out_roready_1_688; // @[RegisterRouter.scala:87:24] wire out_roready_1_689; // @[RegisterRouter.scala:87:24] wire out_roready_1_690; // @[RegisterRouter.scala:87:24] wire out_roready_1_691; // @[RegisterRouter.scala:87:24] wire out_roready_1_692; // @[RegisterRouter.scala:87:24] wire out_roready_1_693; // @[RegisterRouter.scala:87:24] wire out_roready_1_694; // @[RegisterRouter.scala:87:24] wire out_roready_1_695; // @[RegisterRouter.scala:87:24] wire out_roready_1_696; // @[RegisterRouter.scala:87:24] wire out_roready_1_697; // @[RegisterRouter.scala:87:24] wire out_roready_1_698; // @[RegisterRouter.scala:87:24] wire out_roready_1_699; // @[RegisterRouter.scala:87:24] wire out_roready_1_700; // @[RegisterRouter.scala:87:24] wire out_roready_1_701; // @[RegisterRouter.scala:87:24] wire out_roready_1_702; // @[RegisterRouter.scala:87:24] wire out_roready_1_703; // @[RegisterRouter.scala:87:24] wire out_roready_1_704; // @[RegisterRouter.scala:87:24] wire out_roready_1_705; // @[RegisterRouter.scala:87:24] wire out_roready_1_706; // @[RegisterRouter.scala:87:24] wire out_roready_1_707; // @[RegisterRouter.scala:87:24] wire out_roready_1_708; // @[RegisterRouter.scala:87:24] wire out_roready_1_709; // @[RegisterRouter.scala:87:24] wire out_roready_1_710; // @[RegisterRouter.scala:87:24] wire out_roready_1_711; // @[RegisterRouter.scala:87:24] wire out_roready_1_712; // @[RegisterRouter.scala:87:24] wire out_roready_1_713; // @[RegisterRouter.scala:87:24] wire out_roready_1_714; // @[RegisterRouter.scala:87:24] wire out_roready_1_715; // @[RegisterRouter.scala:87:24] wire out_roready_1_716; // @[RegisterRouter.scala:87:24] wire out_roready_1_717; // @[RegisterRouter.scala:87:24] wire out_roready_1_718; // @[RegisterRouter.scala:87:24] wire out_roready_1_719; // @[RegisterRouter.scala:87:24] wire out_roready_1_720; // @[RegisterRouter.scala:87:24] wire out_roready_1_721; // @[RegisterRouter.scala:87:24] wire out_roready_1_722; // @[RegisterRouter.scala:87:24] wire out_roready_1_723; // @[RegisterRouter.scala:87:24] wire out_roready_1_724; // @[RegisterRouter.scala:87:24] wire out_roready_1_725; // @[RegisterRouter.scala:87:24] wire out_roready_1_726; // @[RegisterRouter.scala:87:24] wire out_roready_1_727; // @[RegisterRouter.scala:87:24] wire out_roready_1_728; // @[RegisterRouter.scala:87:24] wire out_roready_1_729; // @[RegisterRouter.scala:87:24] wire out_roready_1_730; // @[RegisterRouter.scala:87:24] wire out_roready_1_731; // @[RegisterRouter.scala:87:24] wire out_roready_1_732; // @[RegisterRouter.scala:87:24] wire out_roready_1_733; // @[RegisterRouter.scala:87:24] wire out_roready_1_734; // @[RegisterRouter.scala:87:24] wire out_roready_1_735; // @[RegisterRouter.scala:87:24] wire out_roready_1_736; // @[RegisterRouter.scala:87:24] wire out_roready_1_737; // @[RegisterRouter.scala:87:24] wire out_roready_1_738; // @[RegisterRouter.scala:87:24] wire out_roready_1_739; // @[RegisterRouter.scala:87:24] wire out_roready_1_740; // @[RegisterRouter.scala:87:24] wire out_roready_1_741; // @[RegisterRouter.scala:87:24] wire out_roready_1_742; // @[RegisterRouter.scala:87:24] wire out_roready_1_743; // @[RegisterRouter.scala:87:24] wire out_roready_1_744; // @[RegisterRouter.scala:87:24] wire out_roready_1_745; // @[RegisterRouter.scala:87:24] wire out_roready_1_746; // @[RegisterRouter.scala:87:24] wire out_roready_1_747; // @[RegisterRouter.scala:87:24] wire out_roready_1_748; // @[RegisterRouter.scala:87:24] wire out_roready_1_749; // @[RegisterRouter.scala:87:24] wire out_roready_1_750; // @[RegisterRouter.scala:87:24] wire out_roready_1_751; // @[RegisterRouter.scala:87:24] wire out_roready_1_752; // @[RegisterRouter.scala:87:24] wire out_roready_1_753; // @[RegisterRouter.scala:87:24] wire out_roready_1_754; // @[RegisterRouter.scala:87:24] wire out_roready_1_755; // @[RegisterRouter.scala:87:24] wire out_roready_1_756; // @[RegisterRouter.scala:87:24] wire out_roready_1_757; // @[RegisterRouter.scala:87:24] wire out_roready_1_758; // @[RegisterRouter.scala:87:24] wire out_roready_1_759; // @[RegisterRouter.scala:87:24] wire out_roready_1_760; // @[RegisterRouter.scala:87:24] wire out_roready_1_761; // @[RegisterRouter.scala:87:24] wire out_roready_1_762; // @[RegisterRouter.scala:87:24] wire out_roready_1_763; // @[RegisterRouter.scala:87:24] wire out_roready_1_764; // @[RegisterRouter.scala:87:24] wire out_roready_1_765; // @[RegisterRouter.scala:87:24] wire out_roready_1_766; // @[RegisterRouter.scala:87:24] wire out_roready_1_767; // @[RegisterRouter.scala:87:24] wire out_roready_1_768; // @[RegisterRouter.scala:87:24] wire out_roready_1_769; // @[RegisterRouter.scala:87:24] wire out_roready_1_770; // @[RegisterRouter.scala:87:24] wire out_roready_1_771; // @[RegisterRouter.scala:87:24] wire out_roready_1_772; // @[RegisterRouter.scala:87:24] wire out_roready_1_773; // @[RegisterRouter.scala:87:24] wire out_roready_1_774; // @[RegisterRouter.scala:87:24] wire out_roready_1_775; // @[RegisterRouter.scala:87:24] wire out_roready_1_776; // @[RegisterRouter.scala:87:24] wire out_roready_1_777; // @[RegisterRouter.scala:87:24] wire out_roready_1_778; // @[RegisterRouter.scala:87:24] wire out_roready_1_779; // @[RegisterRouter.scala:87:24] wire out_roready_1_780; // @[RegisterRouter.scala:87:24] wire out_roready_1_781; // @[RegisterRouter.scala:87:24] wire out_roready_1_782; // @[RegisterRouter.scala:87:24] wire out_roready_1_783; // @[RegisterRouter.scala:87:24] wire out_roready_1_784; // @[RegisterRouter.scala:87:24] wire out_roready_1_785; // @[RegisterRouter.scala:87:24] wire out_roready_1_786; // @[RegisterRouter.scala:87:24] wire out_roready_1_787; // @[RegisterRouter.scala:87:24] wire out_roready_1_788; // @[RegisterRouter.scala:87:24] wire out_roready_1_789; // @[RegisterRouter.scala:87:24] wire out_roready_1_790; // @[RegisterRouter.scala:87:24] wire out_roready_1_791; // @[RegisterRouter.scala:87:24] wire out_roready_1_792; // @[RegisterRouter.scala:87:24] wire out_roready_1_793; // @[RegisterRouter.scala:87:24] wire out_roready_1_794; // @[RegisterRouter.scala:87:24] wire out_roready_1_795; // @[RegisterRouter.scala:87:24] wire out_roready_1_796; // @[RegisterRouter.scala:87:24] wire out_roready_1_797; // @[RegisterRouter.scala:87:24] wire out_roready_1_798; // @[RegisterRouter.scala:87:24] wire out_roready_1_799; // @[RegisterRouter.scala:87:24] wire out_roready_1_800; // @[RegisterRouter.scala:87:24] wire out_roready_1_801; // @[RegisterRouter.scala:87:24] wire out_roready_1_802; // @[RegisterRouter.scala:87:24] wire out_roready_1_803; // @[RegisterRouter.scala:87:24] wire out_roready_1_804; // @[RegisterRouter.scala:87:24] wire out_roready_1_805; // @[RegisterRouter.scala:87:24] wire out_roready_1_806; // @[RegisterRouter.scala:87:24] wire out_roready_1_807; // @[RegisterRouter.scala:87:24] wire out_roready_1_808; // @[RegisterRouter.scala:87:24] wire out_roready_1_809; // @[RegisterRouter.scala:87:24] wire out_roready_1_810; // @[RegisterRouter.scala:87:24] wire out_roready_1_811; // @[RegisterRouter.scala:87:24] wire out_roready_1_812; // @[RegisterRouter.scala:87:24] wire out_roready_1_813; // @[RegisterRouter.scala:87:24] wire out_roready_1_814; // @[RegisterRouter.scala:87:24] wire out_roready_1_815; // @[RegisterRouter.scala:87:24] wire out_roready_1_816; // @[RegisterRouter.scala:87:24] wire out_roready_1_817; // @[RegisterRouter.scala:87:24] wire out_roready_1_818; // @[RegisterRouter.scala:87:24] wire out_roready_1_819; // @[RegisterRouter.scala:87:24] wire out_roready_1_820; // @[RegisterRouter.scala:87:24] wire out_roready_1_821; // @[RegisterRouter.scala:87:24] wire out_roready_1_822; // @[RegisterRouter.scala:87:24] wire out_roready_1_823; // @[RegisterRouter.scala:87:24] wire out_roready_1_824; // @[RegisterRouter.scala:87:24] wire out_roready_1_825; // @[RegisterRouter.scala:87:24] wire out_roready_1_826; // @[RegisterRouter.scala:87:24] wire out_roready_1_827; // @[RegisterRouter.scala:87:24] wire out_roready_1_828; // @[RegisterRouter.scala:87:24] wire out_roready_1_829; // @[RegisterRouter.scala:87:24] wire out_roready_1_830; // @[RegisterRouter.scala:87:24] wire out_roready_1_831; // @[RegisterRouter.scala:87:24] wire out_roready_1_832; // @[RegisterRouter.scala:87:24] wire out_roready_1_833; // @[RegisterRouter.scala:87:24] wire out_roready_1_834; // @[RegisterRouter.scala:87:24] wire out_roready_1_835; // @[RegisterRouter.scala:87:24] wire out_roready_1_836; // @[RegisterRouter.scala:87:24] wire out_roready_1_837; // @[RegisterRouter.scala:87:24] wire out_roready_1_838; // @[RegisterRouter.scala:87:24] wire out_roready_1_839; // @[RegisterRouter.scala:87:24] wire out_roready_1_840; // @[RegisterRouter.scala:87:24] wire out_roready_1_841; // @[RegisterRouter.scala:87:24] wire out_roready_1_842; // @[RegisterRouter.scala:87:24] wire out_roready_1_843; // @[RegisterRouter.scala:87:24] wire out_roready_1_844; // @[RegisterRouter.scala:87:24] wire out_roready_1_845; // @[RegisterRouter.scala:87:24] wire out_roready_1_846; // @[RegisterRouter.scala:87:24] wire out_roready_1_847; // @[RegisterRouter.scala:87:24] wire out_roready_1_848; // @[RegisterRouter.scala:87:24] wire out_roready_1_849; // @[RegisterRouter.scala:87:24] wire out_roready_1_850; // @[RegisterRouter.scala:87:24] wire out_roready_1_851; // @[RegisterRouter.scala:87:24] wire out_roready_1_852; // @[RegisterRouter.scala:87:24] wire out_roready_1_853; // @[RegisterRouter.scala:87:24] wire out_roready_1_854; // @[RegisterRouter.scala:87:24] wire out_roready_1_855; // @[RegisterRouter.scala:87:24] wire out_roready_1_856; // @[RegisterRouter.scala:87:24] wire out_roready_1_857; // @[RegisterRouter.scala:87:24] wire out_roready_1_858; // @[RegisterRouter.scala:87:24] wire out_roready_1_859; // @[RegisterRouter.scala:87:24] wire out_roready_1_860; // @[RegisterRouter.scala:87:24] wire out_roready_1_861; // @[RegisterRouter.scala:87:24] wire out_roready_1_862; // @[RegisterRouter.scala:87:24] wire out_roready_1_863; // @[RegisterRouter.scala:87:24] wire out_roready_1_864; // @[RegisterRouter.scala:87:24] wire out_roready_1_865; // @[RegisterRouter.scala:87:24] wire out_roready_1_866; // @[RegisterRouter.scala:87:24] wire out_roready_1_867; // @[RegisterRouter.scala:87:24] wire out_roready_1_868; // @[RegisterRouter.scala:87:24] wire out_roready_1_869; // @[RegisterRouter.scala:87:24] wire out_roready_1_870; // @[RegisterRouter.scala:87:24] wire out_roready_1_871; // @[RegisterRouter.scala:87:24] wire out_roready_1_872; // @[RegisterRouter.scala:87:24] wire out_roready_1_873; // @[RegisterRouter.scala:87:24] wire out_roready_1_874; // @[RegisterRouter.scala:87:24] wire out_roready_1_875; // @[RegisterRouter.scala:87:24] wire out_roready_1_876; // @[RegisterRouter.scala:87:24] wire out_roready_1_877; // @[RegisterRouter.scala:87:24] wire out_roready_1_878; // @[RegisterRouter.scala:87:24] wire out_roready_1_879; // @[RegisterRouter.scala:87:24] wire out_roready_1_880; // @[RegisterRouter.scala:87:24] wire out_roready_1_881; // @[RegisterRouter.scala:87:24] wire out_roready_1_882; // @[RegisterRouter.scala:87:24] wire out_roready_1_883; // @[RegisterRouter.scala:87:24] wire out_roready_1_884; // @[RegisterRouter.scala:87:24] wire out_roready_1_885; // @[RegisterRouter.scala:87:24] wire out_roready_1_886; // @[RegisterRouter.scala:87:24] wire out_roready_1_887; // @[RegisterRouter.scala:87:24] wire out_roready_1_888; // @[RegisterRouter.scala:87:24] wire out_roready_1_889; // @[RegisterRouter.scala:87:24] wire out_roready_1_890; // @[RegisterRouter.scala:87:24] wire out_roready_1_891; // @[RegisterRouter.scala:87:24] wire out_roready_1_892; // @[RegisterRouter.scala:87:24] wire out_roready_1_893; // @[RegisterRouter.scala:87:24] wire out_roready_1_894; // @[RegisterRouter.scala:87:24] wire out_roready_1_895; // @[RegisterRouter.scala:87:24] wire out_roready_1_896; // @[RegisterRouter.scala:87:24] wire out_roready_1_897; // @[RegisterRouter.scala:87:24] wire out_roready_1_898; // @[RegisterRouter.scala:87:24] wire out_roready_1_899; // @[RegisterRouter.scala:87:24] wire out_roready_1_900; // @[RegisterRouter.scala:87:24] wire out_roready_1_901; // @[RegisterRouter.scala:87:24] wire out_roready_1_902; // @[RegisterRouter.scala:87:24] wire out_roready_1_903; // @[RegisterRouter.scala:87:24] wire out_roready_1_904; // @[RegisterRouter.scala:87:24] wire out_roready_1_905; // @[RegisterRouter.scala:87:24] wire out_roready_1_906; // @[RegisterRouter.scala:87:24] wire out_roready_1_907; // @[RegisterRouter.scala:87:24] wire out_roready_1_908; // @[RegisterRouter.scala:87:24] wire out_roready_1_909; // @[RegisterRouter.scala:87:24] wire out_roready_1_910; // @[RegisterRouter.scala:87:24] wire out_roready_1_911; // @[RegisterRouter.scala:87:24] wire out_roready_1_912; // @[RegisterRouter.scala:87:24] wire out_roready_1_913; // @[RegisterRouter.scala:87:24] wire out_roready_1_914; // @[RegisterRouter.scala:87:24] wire out_roready_1_915; // @[RegisterRouter.scala:87:24] wire out_roready_1_916; // @[RegisterRouter.scala:87:24] wire out_roready_1_917; // @[RegisterRouter.scala:87:24] wire out_roready_1_918; // @[RegisterRouter.scala:87:24] wire out_roready_1_919; // @[RegisterRouter.scala:87:24] wire out_roready_1_920; // @[RegisterRouter.scala:87:24] wire out_roready_1_921; // @[RegisterRouter.scala:87:24] wire out_roready_1_922; // @[RegisterRouter.scala:87:24] wire out_roready_1_923; // @[RegisterRouter.scala:87:24] wire out_roready_1_924; // @[RegisterRouter.scala:87:24] wire out_roready_1_925; // @[RegisterRouter.scala:87:24] wire out_roready_1_926; // @[RegisterRouter.scala:87:24] wire out_roready_1_927; // @[RegisterRouter.scala:87:24] wire out_roready_1_928; // @[RegisterRouter.scala:87:24] wire out_roready_1_929; // @[RegisterRouter.scala:87:24] wire out_roready_1_930; // @[RegisterRouter.scala:87:24] wire out_roready_1_931; // @[RegisterRouter.scala:87:24] wire out_roready_1_932; // @[RegisterRouter.scala:87:24] wire out_roready_1_933; // @[RegisterRouter.scala:87:24] wire out_roready_1_934; // @[RegisterRouter.scala:87:24] wire out_roready_1_935; // @[RegisterRouter.scala:87:24] wire out_roready_1_936; // @[RegisterRouter.scala:87:24] wire out_roready_1_937; // @[RegisterRouter.scala:87:24] wire out_roready_1_938; // @[RegisterRouter.scala:87:24] wire out_roready_1_939; // @[RegisterRouter.scala:87:24] wire out_roready_1_940; // @[RegisterRouter.scala:87:24] wire out_roready_1_941; // @[RegisterRouter.scala:87:24] wire out_roready_1_942; // @[RegisterRouter.scala:87:24] wire out_roready_1_943; // @[RegisterRouter.scala:87:24] wire out_roready_1_944; // @[RegisterRouter.scala:87:24] wire out_roready_1_945; // @[RegisterRouter.scala:87:24] wire out_roready_1_946; // @[RegisterRouter.scala:87:24] wire out_roready_1_947; // @[RegisterRouter.scala:87:24] wire out_roready_1_948; // @[RegisterRouter.scala:87:24] wire out_roready_1_949; // @[RegisterRouter.scala:87:24] wire out_roready_1_950; // @[RegisterRouter.scala:87:24] wire out_roready_1_951; // @[RegisterRouter.scala:87:24] wire out_roready_1_952; // @[RegisterRouter.scala:87:24] wire out_roready_1_953; // @[RegisterRouter.scala:87:24] wire out_roready_1_954; // @[RegisterRouter.scala:87:24] wire out_roready_1_955; // @[RegisterRouter.scala:87:24] wire out_roready_1_956; // @[RegisterRouter.scala:87:24] wire out_roready_1_957; // @[RegisterRouter.scala:87:24] wire out_roready_1_958; // @[RegisterRouter.scala:87:24] wire out_roready_1_959; // @[RegisterRouter.scala:87:24] wire out_roready_1_960; // @[RegisterRouter.scala:87:24] wire out_roready_1_961; // @[RegisterRouter.scala:87:24] wire out_roready_1_962; // @[RegisterRouter.scala:87:24] wire out_roready_1_963; // @[RegisterRouter.scala:87:24] wire out_roready_1_964; // @[RegisterRouter.scala:87:24] wire out_roready_1_965; // @[RegisterRouter.scala:87:24] wire out_roready_1_966; // @[RegisterRouter.scala:87:24] wire out_roready_1_967; // @[RegisterRouter.scala:87:24] wire out_roready_1_968; // @[RegisterRouter.scala:87:24] wire out_roready_1_969; // @[RegisterRouter.scala:87:24] wire out_roready_1_970; // @[RegisterRouter.scala:87:24] wire out_roready_1_971; // @[RegisterRouter.scala:87:24] wire out_roready_1_972; // @[RegisterRouter.scala:87:24] wire out_roready_1_973; // @[RegisterRouter.scala:87:24] wire out_roready_1_974; // @[RegisterRouter.scala:87:24] wire out_roready_1_975; // @[RegisterRouter.scala:87:24] wire out_roready_1_976; // @[RegisterRouter.scala:87:24] wire out_roready_1_977; // @[RegisterRouter.scala:87:24] wire out_roready_1_978; // @[RegisterRouter.scala:87:24] wire out_roready_1_979; // @[RegisterRouter.scala:87:24] wire out_roready_1_980; // @[RegisterRouter.scala:87:24] wire out_roready_1_981; // @[RegisterRouter.scala:87:24] wire out_roready_1_982; // @[RegisterRouter.scala:87:24] wire out_roready_1_983; // @[RegisterRouter.scala:87:24] wire out_roready_1_984; // @[RegisterRouter.scala:87:24] wire out_roready_1_985; // @[RegisterRouter.scala:87:24] wire out_roready_1_986; // @[RegisterRouter.scala:87:24] wire out_roready_1_987; // @[RegisterRouter.scala:87:24] wire out_roready_1_988; // @[RegisterRouter.scala:87:24] wire out_roready_1_989; // @[RegisterRouter.scala:87:24] wire out_roready_1_990; // @[RegisterRouter.scala:87:24] wire out_roready_1_991; // @[RegisterRouter.scala:87:24] wire out_roready_1_992; // @[RegisterRouter.scala:87:24] wire out_roready_1_993; // @[RegisterRouter.scala:87:24] wire out_roready_1_994; // @[RegisterRouter.scala:87:24] wire out_roready_1_995; // @[RegisterRouter.scala:87:24] wire out_roready_1_996; // @[RegisterRouter.scala:87:24] wire out_roready_1_997; // @[RegisterRouter.scala:87:24] wire out_roready_1_998; // @[RegisterRouter.scala:87:24] wire out_roready_1_999; // @[RegisterRouter.scala:87:24] wire out_roready_1_1000; // @[RegisterRouter.scala:87:24] wire out_roready_1_1001; // @[RegisterRouter.scala:87:24] wire out_roready_1_1002; // @[RegisterRouter.scala:87:24] wire out_roready_1_1003; // @[RegisterRouter.scala:87:24] wire out_roready_1_1004; // @[RegisterRouter.scala:87:24] wire out_roready_1_1005; // @[RegisterRouter.scala:87:24] wire out_roready_1_1006; // @[RegisterRouter.scala:87:24] wire out_roready_1_1007; // @[RegisterRouter.scala:87:24] wire out_roready_1_1008; // @[RegisterRouter.scala:87:24] wire out_roready_1_1009; // @[RegisterRouter.scala:87:24] wire out_roready_1_1010; // @[RegisterRouter.scala:87:24] wire out_roready_1_1011; // @[RegisterRouter.scala:87:24] wire out_roready_1_1012; // @[RegisterRouter.scala:87:24] wire out_roready_1_1013; // @[RegisterRouter.scala:87:24] wire out_roready_1_1014; // @[RegisterRouter.scala:87:24] wire out_roready_1_1015; // @[RegisterRouter.scala:87:24] wire out_roready_1_1016; // @[RegisterRouter.scala:87:24] wire out_roready_1_1017; // @[RegisterRouter.scala:87:24] wire out_roready_1_1018; // @[RegisterRouter.scala:87:24] wire out_roready_1_1019; // @[RegisterRouter.scala:87:24] wire out_roready_1_1020; // @[RegisterRouter.scala:87:24] wire out_roready_1_1021; // @[RegisterRouter.scala:87:24] wire out_roready_1_1022; // @[RegisterRouter.scala:87:24] wire out_roready_1_1023; // @[RegisterRouter.scala:87:24] wire out_roready_1_1024; // @[RegisterRouter.scala:87:24] wire out_roready_1_1025; // @[RegisterRouter.scala:87:24] wire out_roready_1_1026; // @[RegisterRouter.scala:87:24] wire out_roready_1_1027; // @[RegisterRouter.scala:87:24] wire out_roready_1_1028; // @[RegisterRouter.scala:87:24] wire out_roready_1_1029; // @[RegisterRouter.scala:87:24] wire out_roready_1_1030; // @[RegisterRouter.scala:87:24] wire out_roready_1_1031; // @[RegisterRouter.scala:87:24] wire out_roready_1_1032; // @[RegisterRouter.scala:87:24] wire out_roready_1_1033; // @[RegisterRouter.scala:87:24] wire out_roready_1_1034; // @[RegisterRouter.scala:87:24] wire out_roready_1_1035; // @[RegisterRouter.scala:87:24] wire out_roready_1_1036; // @[RegisterRouter.scala:87:24] wire out_roready_1_1037; // @[RegisterRouter.scala:87:24] wire out_roready_1_1038; // @[RegisterRouter.scala:87:24] wire out_roready_1_1039; // @[RegisterRouter.scala:87:24] wire out_roready_1_1040; // @[RegisterRouter.scala:87:24] wire out_roready_1_1041; // @[RegisterRouter.scala:87:24] wire out_roready_1_1042; // @[RegisterRouter.scala:87:24] wire out_roready_1_1043; // @[RegisterRouter.scala:87:24] wire out_roready_1_1044; // @[RegisterRouter.scala:87:24] wire out_roready_1_1045; // @[RegisterRouter.scala:87:24] wire out_roready_1_1046; // @[RegisterRouter.scala:87:24] wire out_roready_1_1047; // @[RegisterRouter.scala:87:24] wire out_roready_1_1048; // @[RegisterRouter.scala:87:24] wire out_roready_1_1049; // @[RegisterRouter.scala:87:24] wire out_roready_1_1050; // @[RegisterRouter.scala:87:24] wire out_roready_1_1051; // @[RegisterRouter.scala:87:24] wire out_roready_1_1052; // @[RegisterRouter.scala:87:24] wire out_roready_1_1053; // @[RegisterRouter.scala:87:24] wire out_roready_1_1054; // @[RegisterRouter.scala:87:24] wire out_roready_1_1055; // @[RegisterRouter.scala:87:24] wire out_roready_1_1056; // @[RegisterRouter.scala:87:24] wire out_roready_1_1057; // @[RegisterRouter.scala:87:24] wire out_roready_1_1058; // @[RegisterRouter.scala:87:24] wire out_roready_1_1059; // @[RegisterRouter.scala:87:24] wire out_roready_1_1060; // @[RegisterRouter.scala:87:24] wire out_roready_1_1061; // @[RegisterRouter.scala:87:24] wire out_roready_1_1062; // @[RegisterRouter.scala:87:24] wire out_roready_1_1063; // @[RegisterRouter.scala:87:24] wire out_roready_1_1064; // @[RegisterRouter.scala:87:24] wire out_roready_1_1065; // @[RegisterRouter.scala:87:24] wire out_roready_1_1066; // @[RegisterRouter.scala:87:24] wire out_roready_1_1067; // @[RegisterRouter.scala:87:24] wire out_roready_1_1068; // @[RegisterRouter.scala:87:24] wire out_roready_1_1069; // @[RegisterRouter.scala:87:24] wire out_roready_1_1070; // @[RegisterRouter.scala:87:24] wire out_roready_1_1071; // @[RegisterRouter.scala:87:24] wire out_roready_1_1072; // @[RegisterRouter.scala:87:24] wire out_roready_1_1073; // @[RegisterRouter.scala:87:24] wire out_roready_1_1074; // @[RegisterRouter.scala:87:24] wire out_roready_1_1075; // @[RegisterRouter.scala:87:24] wire out_roready_1_1076; // @[RegisterRouter.scala:87:24] wire out_roready_1_1077; // @[RegisterRouter.scala:87:24] wire out_roready_1_1078; // @[RegisterRouter.scala:87:24] wire out_roready_1_1079; // @[RegisterRouter.scala:87:24] wire out_roready_1_1080; // @[RegisterRouter.scala:87:24] wire out_roready_1_1081; // @[RegisterRouter.scala:87:24] wire out_roready_1_1082; // @[RegisterRouter.scala:87:24] wire out_roready_1_1083; // @[RegisterRouter.scala:87:24] wire out_roready_1_1084; // @[RegisterRouter.scala:87:24] wire out_roready_1_1085; // @[RegisterRouter.scala:87:24] wire out_roready_1_1086; // @[RegisterRouter.scala:87:24] wire out_roready_1_1087; // @[RegisterRouter.scala:87:24] wire out_roready_1_1088; // @[RegisterRouter.scala:87:24] wire out_roready_1_1089; // @[RegisterRouter.scala:87:24] wire out_roready_1_1090; // @[RegisterRouter.scala:87:24] wire out_roready_1_1091; // @[RegisterRouter.scala:87:24] wire out_roready_1_1092; // @[RegisterRouter.scala:87:24] wire out_roready_1_1093; // @[RegisterRouter.scala:87:24] wire out_roready_1_1094; // @[RegisterRouter.scala:87:24] wire out_roready_1_1095; // @[RegisterRouter.scala:87:24] wire out_roready_1_1096; // @[RegisterRouter.scala:87:24] wire out_roready_1_1097; // @[RegisterRouter.scala:87:24] wire out_roready_1_1098; // @[RegisterRouter.scala:87:24] wire out_roready_1_1099; // @[RegisterRouter.scala:87:24] wire out_roready_1_1100; // @[RegisterRouter.scala:87:24] wire out_roready_1_1101; // @[RegisterRouter.scala:87:24] wire out_roready_1_1102; // @[RegisterRouter.scala:87:24] wire out_roready_1_1103; // @[RegisterRouter.scala:87:24] wire out_roready_1_1104; // @[RegisterRouter.scala:87:24] wire out_roready_1_1105; // @[RegisterRouter.scala:87:24] wire out_roready_1_1106; // @[RegisterRouter.scala:87:24] wire out_roready_1_1107; // @[RegisterRouter.scala:87:24] wire out_roready_1_1108; // @[RegisterRouter.scala:87:24] wire out_roready_1_1109; // @[RegisterRouter.scala:87:24] wire out_roready_1_1110; // @[RegisterRouter.scala:87:24] wire out_roready_1_1111; // @[RegisterRouter.scala:87:24] wire out_roready_1_1112; // @[RegisterRouter.scala:87:24] wire out_roready_1_1113; // @[RegisterRouter.scala:87:24] wire out_roready_1_1114; // @[RegisterRouter.scala:87:24] wire out_roready_1_1115; // @[RegisterRouter.scala:87:24] wire out_roready_1_1116; // @[RegisterRouter.scala:87:24] wire out_roready_1_1117; // @[RegisterRouter.scala:87:24] wire out_roready_1_1118; // @[RegisterRouter.scala:87:24] wire out_roready_1_1119; // @[RegisterRouter.scala:87:24] wire out_roready_1_1120; // @[RegisterRouter.scala:87:24] wire out_roready_1_1121; // @[RegisterRouter.scala:87:24] wire out_roready_1_1122; // @[RegisterRouter.scala:87:24] wire out_roready_1_1123; // @[RegisterRouter.scala:87:24] wire out_roready_1_1124; // @[RegisterRouter.scala:87:24] wire out_roready_1_1125; // @[RegisterRouter.scala:87:24] wire out_roready_1_1126; // @[RegisterRouter.scala:87:24] wire out_roready_1_1127; // @[RegisterRouter.scala:87:24] wire out_roready_1_1128; // @[RegisterRouter.scala:87:24] wire out_roready_1_1129; // @[RegisterRouter.scala:87:24] wire out_roready_1_1130; // @[RegisterRouter.scala:87:24] wire out_roready_1_1131; // @[RegisterRouter.scala:87:24] wire out_roready_1_1132; // @[RegisterRouter.scala:87:24] wire out_roready_1_1133; // @[RegisterRouter.scala:87:24] wire out_roready_1_1134; // @[RegisterRouter.scala:87:24] wire out_roready_1_1135; // @[RegisterRouter.scala:87:24] wire out_roready_1_1136; // @[RegisterRouter.scala:87:24] wire out_roready_1_1137; // @[RegisterRouter.scala:87:24] wire out_roready_1_1138; // @[RegisterRouter.scala:87:24] wire out_roready_1_1139; // @[RegisterRouter.scala:87:24] wire out_roready_1_1140; // @[RegisterRouter.scala:87:24] wire out_roready_1_1141; // @[RegisterRouter.scala:87:24] wire out_roready_1_1142; // @[RegisterRouter.scala:87:24] wire out_roready_1_1143; // @[RegisterRouter.scala:87:24] wire out_roready_1_1144; // @[RegisterRouter.scala:87:24] wire out_roready_1_1145; // @[RegisterRouter.scala:87:24] wire out_roready_1_1146; // @[RegisterRouter.scala:87:24] wire out_roready_1_1147; // @[RegisterRouter.scala:87:24] wire out_roready_1_1148; // @[RegisterRouter.scala:87:24] wire out_roready_1_1149; // @[RegisterRouter.scala:87:24] wire out_roready_1_1150; // @[RegisterRouter.scala:87:24] wire out_roready_1_1151; // @[RegisterRouter.scala:87:24] wire out_roready_1_1152; // @[RegisterRouter.scala:87:24] wire out_roready_1_1153; // @[RegisterRouter.scala:87:24] wire out_roready_1_1154; // @[RegisterRouter.scala:87:24] wire out_roready_1_1155; // @[RegisterRouter.scala:87:24] wire out_roready_1_1156; // @[RegisterRouter.scala:87:24] wire out_roready_1_1157; // @[RegisterRouter.scala:87:24] wire out_roready_1_1158; // @[RegisterRouter.scala:87:24] wire out_roready_1_1159; // @[RegisterRouter.scala:87:24] wire out_roready_1_1160; // @[RegisterRouter.scala:87:24] wire out_roready_1_1161; // @[RegisterRouter.scala:87:24] wire out_roready_1_1162; // @[RegisterRouter.scala:87:24] wire out_roready_1_1163; // @[RegisterRouter.scala:87:24] wire out_roready_1_1164; // @[RegisterRouter.scala:87:24] wire out_roready_1_1165; // @[RegisterRouter.scala:87:24] wire out_roready_1_1166; // @[RegisterRouter.scala:87:24] wire out_roready_1_1167; // @[RegisterRouter.scala:87:24] wire out_roready_1_1168; // @[RegisterRouter.scala:87:24] wire out_roready_1_1169; // @[RegisterRouter.scala:87:24] wire out_roready_1_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_1171; // @[RegisterRouter.scala:87:24] wire out_roready_1_1172; // @[RegisterRouter.scala:87:24] wire out_roready_1_1173; // @[RegisterRouter.scala:87:24] wire out_roready_1_1174; // @[RegisterRouter.scala:87:24] wire out_roready_1_1175; // @[RegisterRouter.scala:87:24] wire out_roready_1_1176; // @[RegisterRouter.scala:87:24] wire out_roready_1_1177; // @[RegisterRouter.scala:87:24] wire out_roready_1_1178; // @[RegisterRouter.scala:87:24] wire out_roready_1_1179; // @[RegisterRouter.scala:87:24] wire out_roready_1_1180; // @[RegisterRouter.scala:87:24] wire out_roready_1_1181; // @[RegisterRouter.scala:87:24] wire out_roready_1_1182; // @[RegisterRouter.scala:87:24] wire out_roready_1_1183; // @[RegisterRouter.scala:87:24] wire out_roready_1_1184; // @[RegisterRouter.scala:87:24] wire out_roready_1_1185; // @[RegisterRouter.scala:87:24] wire out_roready_1_1186; // @[RegisterRouter.scala:87:24] wire out_roready_1_1187; // @[RegisterRouter.scala:87:24] wire out_roready_1_1188; // @[RegisterRouter.scala:87:24] wire out_roready_1_1189; // @[RegisterRouter.scala:87:24] wire out_roready_1_1190; // @[RegisterRouter.scala:87:24] wire out_roready_1_1191; // @[RegisterRouter.scala:87:24] wire out_roready_1_1192; // @[RegisterRouter.scala:87:24] wire out_roready_1_1193; // @[RegisterRouter.scala:87:24] wire out_roready_1_1194; // @[RegisterRouter.scala:87:24] wire out_roready_1_1195; // @[RegisterRouter.scala:87:24] wire out_roready_1_1196; // @[RegisterRouter.scala:87:24] wire out_roready_1_1197; // @[RegisterRouter.scala:87:24] wire out_roready_1_1198; // @[RegisterRouter.scala:87:24] wire out_roready_1_1199; // @[RegisterRouter.scala:87:24] wire out_roready_1_1200; // @[RegisterRouter.scala:87:24] wire out_roready_1_1201; // @[RegisterRouter.scala:87:24] wire out_roready_1_1202; // @[RegisterRouter.scala:87:24] wire out_roready_1_1203; // @[RegisterRouter.scala:87:24] wire out_roready_1_1204; // @[RegisterRouter.scala:87:24] wire out_roready_1_1205; // @[RegisterRouter.scala:87:24] wire out_roready_1_1206; // @[RegisterRouter.scala:87:24] wire out_roready_1_1207; // @[RegisterRouter.scala:87:24] wire out_roready_1_1208; // @[RegisterRouter.scala:87:24] wire out_roready_1_1209; // @[RegisterRouter.scala:87:24] wire out_roready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_0; // @[RegisterRouter.scala:87:24] wire out_woready_1_1; // @[RegisterRouter.scala:87:24] wire out_woready_1_2; // @[RegisterRouter.scala:87:24] wire out_woready_1_3; // @[RegisterRouter.scala:87:24] wire out_woready_1_4; // @[RegisterRouter.scala:87:24] wire out_woready_1_5; // @[RegisterRouter.scala:87:24] wire out_woready_1_6; // @[RegisterRouter.scala:87:24] wire out_woready_1_7; // @[RegisterRouter.scala:87:24] wire out_woready_1_8; // @[RegisterRouter.scala:87:24] wire out_woready_1_9; // @[RegisterRouter.scala:87:24] wire out_woready_1_10; // @[RegisterRouter.scala:87:24] wire out_woready_1_11; // @[RegisterRouter.scala:87:24] wire out_woready_1_12; // @[RegisterRouter.scala:87:24] wire out_woready_1_13; // @[RegisterRouter.scala:87:24] wire out_woready_1_14; // @[RegisterRouter.scala:87:24] wire out_woready_1_15; // @[RegisterRouter.scala:87:24] wire out_woready_1_16; // @[RegisterRouter.scala:87:24] wire out_woready_1_17; // @[RegisterRouter.scala:87:24] wire out_woready_1_18; // @[RegisterRouter.scala:87:24] wire out_woready_1_19; // @[RegisterRouter.scala:87:24] wire out_woready_1_20; // @[RegisterRouter.scala:87:24] wire out_woready_1_21; // @[RegisterRouter.scala:87:24] wire out_woready_1_22; // @[RegisterRouter.scala:87:24] wire out_woready_1_23; // @[RegisterRouter.scala:87:24] wire out_woready_1_24; // @[RegisterRouter.scala:87:24] wire out_woready_1_25; // @[RegisterRouter.scala:87:24] wire out_woready_1_26; // @[RegisterRouter.scala:87:24] wire out_woready_1_27; // @[RegisterRouter.scala:87:24] wire out_woready_1_28; // @[RegisterRouter.scala:87:24] wire out_woready_1_29; // @[RegisterRouter.scala:87:24] wire out_woready_1_30; // @[RegisterRouter.scala:87:24] wire out_woready_1_31; // @[RegisterRouter.scala:87:24] wire out_woready_1_32; // @[RegisterRouter.scala:87:24] wire out_woready_1_33; // @[RegisterRouter.scala:87:24] wire out_woready_1_34; // @[RegisterRouter.scala:87:24] wire out_woready_1_35; // @[RegisterRouter.scala:87:24] wire out_woready_1_36; // @[RegisterRouter.scala:87:24] wire out_woready_1_37; // @[RegisterRouter.scala:87:24] wire out_woready_1_38; // @[RegisterRouter.scala:87:24] wire out_woready_1_39; // @[RegisterRouter.scala:87:24] wire out_woready_1_40; // @[RegisterRouter.scala:87:24] wire out_woready_1_41; // @[RegisterRouter.scala:87:24] wire out_woready_1_42; // @[RegisterRouter.scala:87:24] wire out_woready_1_43; // @[RegisterRouter.scala:87:24] wire out_woready_1_44; // @[RegisterRouter.scala:87:24] wire out_woready_1_45; // @[RegisterRouter.scala:87:24] wire out_woready_1_46; // @[RegisterRouter.scala:87:24] wire out_woready_1_47; // @[RegisterRouter.scala:87:24] wire out_woready_1_48; // @[RegisterRouter.scala:87:24] wire out_woready_1_49; // @[RegisterRouter.scala:87:24] wire out_woready_1_50; // @[RegisterRouter.scala:87:24] wire out_woready_1_51; // @[RegisterRouter.scala:87:24] wire out_woready_1_52; // @[RegisterRouter.scala:87:24] wire out_woready_1_53; // @[RegisterRouter.scala:87:24] wire out_woready_1_54; // @[RegisterRouter.scala:87:24] wire out_woready_1_55; // @[RegisterRouter.scala:87:24] wire out_woready_1_56; // @[RegisterRouter.scala:87:24] wire out_woready_1_57; // @[RegisterRouter.scala:87:24] wire out_woready_1_58; // @[RegisterRouter.scala:87:24] wire out_woready_1_59; // @[RegisterRouter.scala:87:24] wire out_woready_1_60; // @[RegisterRouter.scala:87:24] wire out_woready_1_61; // @[RegisterRouter.scala:87:24] wire out_woready_1_62; // @[RegisterRouter.scala:87:24] wire out_woready_1_63; // @[RegisterRouter.scala:87:24] wire out_woready_1_64; // @[RegisterRouter.scala:87:24] wire out_woready_1_65; // @[RegisterRouter.scala:87:24] wire out_woready_1_66; // @[RegisterRouter.scala:87:24] wire out_woready_1_67; // @[RegisterRouter.scala:87:24] wire out_woready_1_68; // @[RegisterRouter.scala:87:24] wire out_woready_1_69; // @[RegisterRouter.scala:87:24] wire out_woready_1_70; // @[RegisterRouter.scala:87:24] wire out_woready_1_71; // @[RegisterRouter.scala:87:24] wire out_woready_1_72; // @[RegisterRouter.scala:87:24] wire out_woready_1_73; // @[RegisterRouter.scala:87:24] wire out_woready_1_74; // @[RegisterRouter.scala:87:24] wire out_woready_1_75; // @[RegisterRouter.scala:87:24] wire out_woready_1_76; // @[RegisterRouter.scala:87:24] wire out_woready_1_77; // @[RegisterRouter.scala:87:24] wire out_woready_1_78; // @[RegisterRouter.scala:87:24] wire out_woready_1_79; // @[RegisterRouter.scala:87:24] wire out_woready_1_80; // @[RegisterRouter.scala:87:24] wire out_woready_1_81; // @[RegisterRouter.scala:87:24] wire out_woready_1_82; // @[RegisterRouter.scala:87:24] wire out_woready_1_83; // @[RegisterRouter.scala:87:24] wire out_woready_1_84; // @[RegisterRouter.scala:87:24] wire out_woready_1_85; // @[RegisterRouter.scala:87:24] wire out_woready_1_86; // @[RegisterRouter.scala:87:24] wire out_woready_1_87; // @[RegisterRouter.scala:87:24] wire out_woready_1_88; // @[RegisterRouter.scala:87:24] wire out_woready_1_89; // @[RegisterRouter.scala:87:24] wire out_woready_1_90; // @[RegisterRouter.scala:87:24] wire out_woready_1_91; // @[RegisterRouter.scala:87:24] wire out_woready_1_92; // @[RegisterRouter.scala:87:24] wire out_woready_1_93; // @[RegisterRouter.scala:87:24] wire out_woready_1_94; // @[RegisterRouter.scala:87:24] wire out_woready_1_95; // @[RegisterRouter.scala:87:24] wire out_woready_1_96; // @[RegisterRouter.scala:87:24] wire out_woready_1_97; // @[RegisterRouter.scala:87:24] wire out_woready_1_98; // @[RegisterRouter.scala:87:24] wire out_woready_1_99; // @[RegisterRouter.scala:87:24] wire out_woready_1_100; // @[RegisterRouter.scala:87:24] wire out_woready_1_101; // @[RegisterRouter.scala:87:24] wire out_woready_1_102; // @[RegisterRouter.scala:87:24] wire out_woready_1_103; // @[RegisterRouter.scala:87:24] wire out_woready_1_104; // @[RegisterRouter.scala:87:24] wire out_woready_1_105; // @[RegisterRouter.scala:87:24] wire out_woready_1_106; // @[RegisterRouter.scala:87:24] wire out_woready_1_107; // @[RegisterRouter.scala:87:24] wire out_woready_1_108; // @[RegisterRouter.scala:87:24] wire out_woready_1_109; // @[RegisterRouter.scala:87:24] wire out_woready_1_110; // @[RegisterRouter.scala:87:24] wire out_woready_1_111; // @[RegisterRouter.scala:87:24] wire out_woready_1_112; // @[RegisterRouter.scala:87:24] wire out_woready_1_113; // @[RegisterRouter.scala:87:24] wire out_woready_1_114; // @[RegisterRouter.scala:87:24] wire out_woready_1_115; // @[RegisterRouter.scala:87:24] wire out_woready_1_116; // @[RegisterRouter.scala:87:24] wire out_woready_1_117; // @[RegisterRouter.scala:87:24] wire out_woready_1_118; // @[RegisterRouter.scala:87:24] wire out_woready_1_119; // @[RegisterRouter.scala:87:24] wire out_woready_1_120; // @[RegisterRouter.scala:87:24] wire out_woready_1_121; // @[RegisterRouter.scala:87:24] wire out_woready_1_122; // @[RegisterRouter.scala:87:24] wire out_woready_1_123; // @[RegisterRouter.scala:87:24] wire out_woready_1_124; // @[RegisterRouter.scala:87:24] wire out_woready_1_125; // @[RegisterRouter.scala:87:24] wire out_woready_1_126; // @[RegisterRouter.scala:87:24] wire out_woready_1_127; // @[RegisterRouter.scala:87:24] wire out_woready_1_128; // @[RegisterRouter.scala:87:24] wire out_woready_1_129; // @[RegisterRouter.scala:87:24] wire out_woready_1_130; // @[RegisterRouter.scala:87:24] wire out_woready_1_131; // @[RegisterRouter.scala:87:24] wire out_woready_1_132; // @[RegisterRouter.scala:87:24] wire out_woready_1_133; // @[RegisterRouter.scala:87:24] wire out_woready_1_134; // @[RegisterRouter.scala:87:24] wire out_woready_1_135; // @[RegisterRouter.scala:87:24] wire out_woready_1_136; // @[RegisterRouter.scala:87:24] wire out_woready_1_137; // @[RegisterRouter.scala:87:24] wire out_woready_1_138; // @[RegisterRouter.scala:87:24] wire out_woready_1_139; // @[RegisterRouter.scala:87:24] wire out_woready_1_140; // @[RegisterRouter.scala:87:24] wire out_woready_1_141; // @[RegisterRouter.scala:87:24] wire out_woready_1_142; // @[RegisterRouter.scala:87:24] wire out_woready_1_143; // @[RegisterRouter.scala:87:24] wire out_woready_1_144; // @[RegisterRouter.scala:87:24] wire out_woready_1_145; // @[RegisterRouter.scala:87:24] wire out_woready_1_146; // @[RegisterRouter.scala:87:24] wire out_woready_1_147; // @[RegisterRouter.scala:87:24] wire out_woready_1_148; // @[RegisterRouter.scala:87:24] wire out_woready_1_149; // @[RegisterRouter.scala:87:24] wire out_woready_1_150; // @[RegisterRouter.scala:87:24] wire out_woready_1_151; // @[RegisterRouter.scala:87:24] wire out_woready_1_152; // @[RegisterRouter.scala:87:24] wire out_woready_1_153; // @[RegisterRouter.scala:87:24] wire out_woready_1_154; // @[RegisterRouter.scala:87:24] wire out_woready_1_155; // @[RegisterRouter.scala:87:24] wire out_woready_1_156; // @[RegisterRouter.scala:87:24] wire out_woready_1_157; // @[RegisterRouter.scala:87:24] wire out_woready_1_158; // @[RegisterRouter.scala:87:24] wire out_woready_1_159; // @[RegisterRouter.scala:87:24] wire out_woready_1_160; // @[RegisterRouter.scala:87:24] wire out_woready_1_161; // @[RegisterRouter.scala:87:24] wire out_woready_1_162; // @[RegisterRouter.scala:87:24] wire out_woready_1_163; // @[RegisterRouter.scala:87:24] wire out_woready_1_164; // @[RegisterRouter.scala:87:24] wire out_woready_1_165; // @[RegisterRouter.scala:87:24] wire out_woready_1_166; // @[RegisterRouter.scala:87:24] wire out_woready_1_167; // @[RegisterRouter.scala:87:24] wire out_woready_1_168; // @[RegisterRouter.scala:87:24] wire out_woready_1_169; // @[RegisterRouter.scala:87:24] wire out_woready_1_170; // @[RegisterRouter.scala:87:24] wire out_woready_1_171; // @[RegisterRouter.scala:87:24] wire out_woready_1_172; // @[RegisterRouter.scala:87:24] wire out_woready_1_173; // @[RegisterRouter.scala:87:24] wire out_woready_1_174; // @[RegisterRouter.scala:87:24] wire out_woready_1_175; // @[RegisterRouter.scala:87:24] wire out_woready_1_176; // @[RegisterRouter.scala:87:24] wire out_woready_1_177; // @[RegisterRouter.scala:87:24] wire out_woready_1_178; // @[RegisterRouter.scala:87:24] wire out_woready_1_179; // @[RegisterRouter.scala:87:24] wire out_woready_1_180; // @[RegisterRouter.scala:87:24] wire out_woready_1_181; // @[RegisterRouter.scala:87:24] wire out_woready_1_182; // @[RegisterRouter.scala:87:24] wire out_woready_1_183; // @[RegisterRouter.scala:87:24] wire out_woready_1_184; // @[RegisterRouter.scala:87:24] wire out_woready_1_185; // @[RegisterRouter.scala:87:24] wire out_woready_1_186; // @[RegisterRouter.scala:87:24] wire out_woready_1_187; // @[RegisterRouter.scala:87:24] wire out_woready_1_188; // @[RegisterRouter.scala:87:24] wire out_woready_1_189; // @[RegisterRouter.scala:87:24] wire out_woready_1_190; // @[RegisterRouter.scala:87:24] wire out_woready_1_191; // @[RegisterRouter.scala:87:24] wire out_woready_1_192; // @[RegisterRouter.scala:87:24] wire out_woready_1_193; // @[RegisterRouter.scala:87:24] wire out_woready_1_194; // @[RegisterRouter.scala:87:24] wire out_woready_1_195; // @[RegisterRouter.scala:87:24] wire out_woready_1_196; // @[RegisterRouter.scala:87:24] wire out_woready_1_197; // @[RegisterRouter.scala:87:24] wire out_woready_1_198; // @[RegisterRouter.scala:87:24] wire out_woready_1_199; // @[RegisterRouter.scala:87:24] wire out_woready_1_200; // @[RegisterRouter.scala:87:24] wire out_woready_1_201; // @[RegisterRouter.scala:87:24] wire out_woready_1_202; // @[RegisterRouter.scala:87:24] wire out_woready_1_203; // @[RegisterRouter.scala:87:24] wire out_woready_1_204; // @[RegisterRouter.scala:87:24] wire out_woready_1_205; // @[RegisterRouter.scala:87:24] wire out_woready_1_206; // @[RegisterRouter.scala:87:24] wire out_woready_1_207; // @[RegisterRouter.scala:87:24] wire out_woready_1_208; // @[RegisterRouter.scala:87:24] wire out_woready_1_209; // @[RegisterRouter.scala:87:24] wire out_woready_1_210; // @[RegisterRouter.scala:87:24] wire out_woready_1_211; // @[RegisterRouter.scala:87:24] wire out_woready_1_212; // @[RegisterRouter.scala:87:24] wire out_woready_1_213; // @[RegisterRouter.scala:87:24] wire out_woready_1_214; // @[RegisterRouter.scala:87:24] wire out_woready_1_215; // @[RegisterRouter.scala:87:24] wire out_woready_1_216; // @[RegisterRouter.scala:87:24] wire out_woready_1_217; // @[RegisterRouter.scala:87:24] wire out_woready_1_218; // @[RegisterRouter.scala:87:24] wire out_woready_1_219; // @[RegisterRouter.scala:87:24] wire out_woready_1_220; // @[RegisterRouter.scala:87:24] wire out_woready_1_221; // @[RegisterRouter.scala:87:24] wire out_woready_1_222; // @[RegisterRouter.scala:87:24] wire out_woready_1_223; // @[RegisterRouter.scala:87:24] wire out_woready_1_224; // @[RegisterRouter.scala:87:24] wire out_woready_1_225; // @[RegisterRouter.scala:87:24] wire out_woready_1_226; // @[RegisterRouter.scala:87:24] wire out_woready_1_227; // @[RegisterRouter.scala:87:24] wire out_woready_1_228; // @[RegisterRouter.scala:87:24] wire out_woready_1_229; // @[RegisterRouter.scala:87:24] wire out_woready_1_230; // @[RegisterRouter.scala:87:24] wire out_woready_1_231; // @[RegisterRouter.scala:87:24] wire out_woready_1_232; // @[RegisterRouter.scala:87:24] wire out_woready_1_233; // @[RegisterRouter.scala:87:24] wire out_woready_1_234; // @[RegisterRouter.scala:87:24] wire out_woready_1_235; // @[RegisterRouter.scala:87:24] wire out_woready_1_236; // @[RegisterRouter.scala:87:24] wire out_woready_1_237; // @[RegisterRouter.scala:87:24] wire out_woready_1_238; // @[RegisterRouter.scala:87:24] wire out_woready_1_239; // @[RegisterRouter.scala:87:24] wire out_woready_1_240; // @[RegisterRouter.scala:87:24] wire out_woready_1_241; // @[RegisterRouter.scala:87:24] wire out_woready_1_242; // @[RegisterRouter.scala:87:24] wire out_woready_1_243; // @[RegisterRouter.scala:87:24] wire out_woready_1_244; // @[RegisterRouter.scala:87:24] wire out_woready_1_245; // @[RegisterRouter.scala:87:24] wire out_woready_1_246; // @[RegisterRouter.scala:87:24] wire out_woready_1_247; // @[RegisterRouter.scala:87:24] wire out_woready_1_248; // @[RegisterRouter.scala:87:24] wire out_woready_1_249; // @[RegisterRouter.scala:87:24] wire out_woready_1_250; // @[RegisterRouter.scala:87:24] wire out_woready_1_251; // @[RegisterRouter.scala:87:24] wire out_woready_1_252; // @[RegisterRouter.scala:87:24] wire out_woready_1_253; // @[RegisterRouter.scala:87:24] wire out_woready_1_254; // @[RegisterRouter.scala:87:24] wire out_woready_1_255; // @[RegisterRouter.scala:87:24] wire out_woready_1_256; // @[RegisterRouter.scala:87:24] wire out_woready_1_257; // @[RegisterRouter.scala:87:24] wire out_woready_1_258; // @[RegisterRouter.scala:87:24] wire out_woready_1_259; // @[RegisterRouter.scala:87:24] wire out_woready_1_260; // @[RegisterRouter.scala:87:24] wire out_woready_1_261; // @[RegisterRouter.scala:87:24] wire out_woready_1_262; // @[RegisterRouter.scala:87:24] wire out_woready_1_263; // @[RegisterRouter.scala:87:24] wire out_woready_1_264; // @[RegisterRouter.scala:87:24] wire out_woready_1_265; // @[RegisterRouter.scala:87:24] wire out_woready_1_266; // @[RegisterRouter.scala:87:24] wire out_woready_1_267; // @[RegisterRouter.scala:87:24] wire out_woready_1_268; // @[RegisterRouter.scala:87:24] wire out_woready_1_269; // @[RegisterRouter.scala:87:24] wire out_woready_1_270; // @[RegisterRouter.scala:87:24] wire out_woready_1_271; // @[RegisterRouter.scala:87:24] wire out_woready_1_272; // @[RegisterRouter.scala:87:24] wire out_woready_1_273; // @[RegisterRouter.scala:87:24] wire out_woready_1_274; // @[RegisterRouter.scala:87:24] wire out_woready_1_275; // @[RegisterRouter.scala:87:24] wire out_woready_1_276; // @[RegisterRouter.scala:87:24] wire out_woready_1_277; // @[RegisterRouter.scala:87:24] wire out_woready_1_278; // @[RegisterRouter.scala:87:24] wire out_woready_1_279; // @[RegisterRouter.scala:87:24] wire out_woready_1_280; // @[RegisterRouter.scala:87:24] wire out_woready_1_281; // @[RegisterRouter.scala:87:24] wire out_woready_1_282; // @[RegisterRouter.scala:87:24] wire out_woready_1_283; // @[RegisterRouter.scala:87:24] wire out_woready_1_284; // @[RegisterRouter.scala:87:24] wire out_woready_1_285; // @[RegisterRouter.scala:87:24] wire out_woready_1_286; // @[RegisterRouter.scala:87:24] wire out_woready_1_287; // @[RegisterRouter.scala:87:24] wire out_woready_1_288; // @[RegisterRouter.scala:87:24] wire out_woready_1_289; // @[RegisterRouter.scala:87:24] wire out_woready_1_290; // @[RegisterRouter.scala:87:24] wire out_woready_1_291; // @[RegisterRouter.scala:87:24] wire out_woready_1_292; // @[RegisterRouter.scala:87:24] wire out_woready_1_293; // @[RegisterRouter.scala:87:24] wire out_woready_1_294; // @[RegisterRouter.scala:87:24] wire out_woready_1_295; // @[RegisterRouter.scala:87:24] wire out_woready_1_296; // @[RegisterRouter.scala:87:24] wire out_woready_1_297; // @[RegisterRouter.scala:87:24] wire out_woready_1_298; // @[RegisterRouter.scala:87:24] wire out_woready_1_299; // @[RegisterRouter.scala:87:24] wire out_woready_1_300; // @[RegisterRouter.scala:87:24] wire out_woready_1_301; // @[RegisterRouter.scala:87:24] wire out_woready_1_302; // @[RegisterRouter.scala:87:24] wire out_woready_1_303; // @[RegisterRouter.scala:87:24] wire out_woready_1_304; // @[RegisterRouter.scala:87:24] wire out_woready_1_305; // @[RegisterRouter.scala:87:24] wire out_woready_1_306; // @[RegisterRouter.scala:87:24] wire out_woready_1_307; // @[RegisterRouter.scala:87:24] wire out_woready_1_308; // @[RegisterRouter.scala:87:24] wire out_woready_1_309; // @[RegisterRouter.scala:87:24] wire out_woready_1_310; // @[RegisterRouter.scala:87:24] wire out_woready_1_311; // @[RegisterRouter.scala:87:24] wire out_woready_1_312; // @[RegisterRouter.scala:87:24] wire out_woready_1_313; // @[RegisterRouter.scala:87:24] wire out_woready_1_314; // @[RegisterRouter.scala:87:24] wire out_woready_1_315; // @[RegisterRouter.scala:87:24] wire out_woready_1_316; // @[RegisterRouter.scala:87:24] wire out_woready_1_317; // @[RegisterRouter.scala:87:24] wire out_woready_1_318; // @[RegisterRouter.scala:87:24] wire out_woready_1_319; // @[RegisterRouter.scala:87:24] wire out_woready_1_320; // @[RegisterRouter.scala:87:24] wire out_woready_1_321; // @[RegisterRouter.scala:87:24] wire out_woready_1_322; // @[RegisterRouter.scala:87:24] wire out_woready_1_323; // @[RegisterRouter.scala:87:24] wire out_woready_1_324; // @[RegisterRouter.scala:87:24] wire out_woready_1_325; // @[RegisterRouter.scala:87:24] wire out_woready_1_326; // @[RegisterRouter.scala:87:24] wire out_woready_1_327; // @[RegisterRouter.scala:87:24] wire out_woready_1_328; // @[RegisterRouter.scala:87:24] wire out_woready_1_329; // @[RegisterRouter.scala:87:24] wire out_woready_1_330; // @[RegisterRouter.scala:87:24] wire out_woready_1_331; // @[RegisterRouter.scala:87:24] wire out_woready_1_332; // @[RegisterRouter.scala:87:24] wire out_woready_1_333; // @[RegisterRouter.scala:87:24] wire out_woready_1_334; // @[RegisterRouter.scala:87:24] wire out_woready_1_335; // @[RegisterRouter.scala:87:24] wire out_woready_1_336; // @[RegisterRouter.scala:87:24] wire out_woready_1_337; // @[RegisterRouter.scala:87:24] wire out_woready_1_338; // @[RegisterRouter.scala:87:24] wire out_woready_1_339; // @[RegisterRouter.scala:87:24] wire out_woready_1_340; // @[RegisterRouter.scala:87:24] wire out_woready_1_341; // @[RegisterRouter.scala:87:24] wire out_woready_1_342; // @[RegisterRouter.scala:87:24] wire out_woready_1_343; // @[RegisterRouter.scala:87:24] wire out_woready_1_344; // @[RegisterRouter.scala:87:24] wire out_woready_1_345; // @[RegisterRouter.scala:87:24] wire out_woready_1_346; // @[RegisterRouter.scala:87:24] wire out_woready_1_347; // @[RegisterRouter.scala:87:24] wire out_woready_1_348; // @[RegisterRouter.scala:87:24] wire out_woready_1_349; // @[RegisterRouter.scala:87:24] wire out_woready_1_350; // @[RegisterRouter.scala:87:24] wire out_woready_1_351; // @[RegisterRouter.scala:87:24] wire out_woready_1_352; // @[RegisterRouter.scala:87:24] wire out_woready_1_353; // @[RegisterRouter.scala:87:24] wire out_woready_1_354; // @[RegisterRouter.scala:87:24] wire out_woready_1_355; // @[RegisterRouter.scala:87:24] wire out_woready_1_356; // @[RegisterRouter.scala:87:24] wire out_woready_1_357; // @[RegisterRouter.scala:87:24] wire out_woready_1_358; // @[RegisterRouter.scala:87:24] wire out_woready_1_359; // @[RegisterRouter.scala:87:24] wire out_woready_1_360; // @[RegisterRouter.scala:87:24] wire out_woready_1_361; // @[RegisterRouter.scala:87:24] wire out_woready_1_362; // @[RegisterRouter.scala:87:24] wire out_woready_1_363; // @[RegisterRouter.scala:87:24] wire out_woready_1_364; // @[RegisterRouter.scala:87:24] wire out_woready_1_365; // @[RegisterRouter.scala:87:24] wire out_woready_1_366; // @[RegisterRouter.scala:87:24] wire out_woready_1_367; // @[RegisterRouter.scala:87:24] wire out_woready_1_368; // @[RegisterRouter.scala:87:24] wire out_woready_1_369; // @[RegisterRouter.scala:87:24] wire out_woready_1_370; // @[RegisterRouter.scala:87:24] wire out_woready_1_371; // @[RegisterRouter.scala:87:24] wire out_woready_1_372; // @[RegisterRouter.scala:87:24] wire out_woready_1_373; // @[RegisterRouter.scala:87:24] wire out_woready_1_374; // @[RegisterRouter.scala:87:24] wire out_woready_1_375; // @[RegisterRouter.scala:87:24] wire out_woready_1_376; // @[RegisterRouter.scala:87:24] wire out_woready_1_377; // @[RegisterRouter.scala:87:24] wire out_woready_1_378; // @[RegisterRouter.scala:87:24] wire out_woready_1_379; // @[RegisterRouter.scala:87:24] wire out_woready_1_380; // @[RegisterRouter.scala:87:24] wire out_woready_1_381; // @[RegisterRouter.scala:87:24] wire out_woready_1_382; // @[RegisterRouter.scala:87:24] wire out_woready_1_383; // @[RegisterRouter.scala:87:24] wire out_woready_1_384; // @[RegisterRouter.scala:87:24] wire out_woready_1_385; // @[RegisterRouter.scala:87:24] wire out_woready_1_386; // @[RegisterRouter.scala:87:24] wire out_woready_1_387; // @[RegisterRouter.scala:87:24] wire out_woready_1_388; // @[RegisterRouter.scala:87:24] wire out_woready_1_389; // @[RegisterRouter.scala:87:24] wire out_woready_1_390; // @[RegisterRouter.scala:87:24] wire out_woready_1_391; // @[RegisterRouter.scala:87:24] wire out_woready_1_392; // @[RegisterRouter.scala:87:24] wire out_woready_1_393; // @[RegisterRouter.scala:87:24] wire out_woready_1_394; // @[RegisterRouter.scala:87:24] wire out_woready_1_395; // @[RegisterRouter.scala:87:24] wire out_woready_1_396; // @[RegisterRouter.scala:87:24] wire out_woready_1_397; // @[RegisterRouter.scala:87:24] wire out_woready_1_398; // @[RegisterRouter.scala:87:24] wire out_woready_1_399; // @[RegisterRouter.scala:87:24] wire out_woready_1_400; // @[RegisterRouter.scala:87:24] wire out_woready_1_401; // @[RegisterRouter.scala:87:24] wire out_woready_1_402; // @[RegisterRouter.scala:87:24] wire out_woready_1_403; // @[RegisterRouter.scala:87:24] wire out_woready_1_404; // @[RegisterRouter.scala:87:24] wire out_woready_1_405; // @[RegisterRouter.scala:87:24] wire out_woready_1_406; // @[RegisterRouter.scala:87:24] wire out_woready_1_407; // @[RegisterRouter.scala:87:24] wire out_woready_1_408; // @[RegisterRouter.scala:87:24] wire out_woready_1_409; // @[RegisterRouter.scala:87:24] wire out_woready_1_410; // @[RegisterRouter.scala:87:24] wire out_woready_1_411; // @[RegisterRouter.scala:87:24] wire out_woready_1_412; // @[RegisterRouter.scala:87:24] wire out_woready_1_413; // @[RegisterRouter.scala:87:24] wire out_woready_1_414; // @[RegisterRouter.scala:87:24] wire out_woready_1_415; // @[RegisterRouter.scala:87:24] wire out_woready_1_416; // @[RegisterRouter.scala:87:24] wire out_woready_1_417; // @[RegisterRouter.scala:87:24] wire out_woready_1_418; // @[RegisterRouter.scala:87:24] wire out_woready_1_419; // @[RegisterRouter.scala:87:24] wire out_woready_1_420; // @[RegisterRouter.scala:87:24] wire out_woready_1_421; // @[RegisterRouter.scala:87:24] wire out_woready_1_422; // @[RegisterRouter.scala:87:24] wire out_woready_1_423; // @[RegisterRouter.scala:87:24] wire out_woready_1_424; // @[RegisterRouter.scala:87:24] wire out_woready_1_425; // @[RegisterRouter.scala:87:24] wire out_woready_1_426; // @[RegisterRouter.scala:87:24] wire out_woready_1_427; // @[RegisterRouter.scala:87:24] wire out_woready_1_428; // @[RegisterRouter.scala:87:24] wire out_woready_1_429; // @[RegisterRouter.scala:87:24] wire out_woready_1_430; // @[RegisterRouter.scala:87:24] wire out_woready_1_431; // @[RegisterRouter.scala:87:24] wire out_woready_1_432; // @[RegisterRouter.scala:87:24] wire out_woready_1_433; // @[RegisterRouter.scala:87:24] wire out_woready_1_434; // @[RegisterRouter.scala:87:24] wire out_woready_1_435; // @[RegisterRouter.scala:87:24] wire out_woready_1_436; // @[RegisterRouter.scala:87:24] wire out_woready_1_437; // @[RegisterRouter.scala:87:24] wire out_woready_1_438; // @[RegisterRouter.scala:87:24] wire out_woready_1_439; // @[RegisterRouter.scala:87:24] wire out_woready_1_440; // @[RegisterRouter.scala:87:24] wire out_woready_1_441; // @[RegisterRouter.scala:87:24] wire out_woready_1_442; // @[RegisterRouter.scala:87:24] wire out_woready_1_443; // @[RegisterRouter.scala:87:24] wire out_woready_1_444; // @[RegisterRouter.scala:87:24] wire out_woready_1_445; // @[RegisterRouter.scala:87:24] wire out_woready_1_446; // @[RegisterRouter.scala:87:24] wire out_woready_1_447; // @[RegisterRouter.scala:87:24] wire out_woready_1_448; // @[RegisterRouter.scala:87:24] wire out_woready_1_449; // @[RegisterRouter.scala:87:24] wire out_woready_1_450; // @[RegisterRouter.scala:87:24] wire out_woready_1_451; // @[RegisterRouter.scala:87:24] wire out_woready_1_452; // @[RegisterRouter.scala:87:24] wire out_woready_1_453; // @[RegisterRouter.scala:87:24] wire out_woready_1_454; // @[RegisterRouter.scala:87:24] wire out_woready_1_455; // @[RegisterRouter.scala:87:24] wire out_woready_1_456; // @[RegisterRouter.scala:87:24] wire out_woready_1_457; // @[RegisterRouter.scala:87:24] wire out_woready_1_458; // @[RegisterRouter.scala:87:24] wire out_woready_1_459; // @[RegisterRouter.scala:87:24] wire out_woready_1_460; // @[RegisterRouter.scala:87:24] wire out_woready_1_461; // @[RegisterRouter.scala:87:24] wire out_woready_1_462; // @[RegisterRouter.scala:87:24] wire out_woready_1_463; // @[RegisterRouter.scala:87:24] wire out_woready_1_464; // @[RegisterRouter.scala:87:24] wire out_woready_1_465; // @[RegisterRouter.scala:87:24] wire out_woready_1_466; // @[RegisterRouter.scala:87:24] wire out_woready_1_467; // @[RegisterRouter.scala:87:24] wire out_woready_1_468; // @[RegisterRouter.scala:87:24] wire out_woready_1_469; // @[RegisterRouter.scala:87:24] wire out_woready_1_470; // @[RegisterRouter.scala:87:24] wire out_woready_1_471; // @[RegisterRouter.scala:87:24] wire out_woready_1_472; // @[RegisterRouter.scala:87:24] wire out_woready_1_473; // @[RegisterRouter.scala:87:24] wire out_woready_1_474; // @[RegisterRouter.scala:87:24] wire out_woready_1_475; // @[RegisterRouter.scala:87:24] wire out_woready_1_476; // @[RegisterRouter.scala:87:24] wire out_woready_1_477; // @[RegisterRouter.scala:87:24] wire out_woready_1_478; // @[RegisterRouter.scala:87:24] wire out_woready_1_479; // @[RegisterRouter.scala:87:24] wire out_woready_1_480; // @[RegisterRouter.scala:87:24] wire out_woready_1_481; // @[RegisterRouter.scala:87:24] wire out_woready_1_482; // @[RegisterRouter.scala:87:24] wire out_woready_1_483; // @[RegisterRouter.scala:87:24] wire out_woready_1_484; // @[RegisterRouter.scala:87:24] wire out_woready_1_485; // @[RegisterRouter.scala:87:24] wire out_woready_1_486; // @[RegisterRouter.scala:87:24] wire out_woready_1_487; // @[RegisterRouter.scala:87:24] wire out_woready_1_488; // @[RegisterRouter.scala:87:24] wire out_woready_1_489; // @[RegisterRouter.scala:87:24] wire out_woready_1_490; // @[RegisterRouter.scala:87:24] wire out_woready_1_491; // @[RegisterRouter.scala:87:24] wire out_woready_1_492; // @[RegisterRouter.scala:87:24] wire out_woready_1_493; // @[RegisterRouter.scala:87:24] wire out_woready_1_494; // @[RegisterRouter.scala:87:24] wire out_woready_1_495; // @[RegisterRouter.scala:87:24] wire out_woready_1_496; // @[RegisterRouter.scala:87:24] wire out_woready_1_497; // @[RegisterRouter.scala:87:24] wire out_woready_1_498; // @[RegisterRouter.scala:87:24] wire out_woready_1_499; // @[RegisterRouter.scala:87:24] wire out_woready_1_500; // @[RegisterRouter.scala:87:24] wire out_woready_1_501; // @[RegisterRouter.scala:87:24] wire out_woready_1_502; // @[RegisterRouter.scala:87:24] wire out_woready_1_503; // @[RegisterRouter.scala:87:24] wire out_woready_1_504; // @[RegisterRouter.scala:87:24] wire out_woready_1_505; // @[RegisterRouter.scala:87:24] wire out_woready_1_506; // @[RegisterRouter.scala:87:24] wire out_woready_1_507; // @[RegisterRouter.scala:87:24] wire out_woready_1_508; // @[RegisterRouter.scala:87:24] wire out_woready_1_509; // @[RegisterRouter.scala:87:24] wire out_woready_1_510; // @[RegisterRouter.scala:87:24] wire out_woready_1_511; // @[RegisterRouter.scala:87:24] wire out_woready_1_512; // @[RegisterRouter.scala:87:24] wire out_woready_1_513; // @[RegisterRouter.scala:87:24] wire out_woready_1_514; // @[RegisterRouter.scala:87:24] wire out_woready_1_515; // @[RegisterRouter.scala:87:24] wire out_woready_1_516; // @[RegisterRouter.scala:87:24] wire out_woready_1_517; // @[RegisterRouter.scala:87:24] wire out_woready_1_518; // @[RegisterRouter.scala:87:24] wire out_woready_1_519; // @[RegisterRouter.scala:87:24] wire out_woready_1_520; // @[RegisterRouter.scala:87:24] wire out_woready_1_521; // @[RegisterRouter.scala:87:24] wire out_woready_1_522; // @[RegisterRouter.scala:87:24] wire out_woready_1_523; // @[RegisterRouter.scala:87:24] wire out_woready_1_524; // @[RegisterRouter.scala:87:24] wire out_woready_1_525; // @[RegisterRouter.scala:87:24] wire out_woready_1_526; // @[RegisterRouter.scala:87:24] wire out_woready_1_527; // @[RegisterRouter.scala:87:24] wire out_woready_1_528; // @[RegisterRouter.scala:87:24] wire out_woready_1_529; // @[RegisterRouter.scala:87:24] wire out_woready_1_530; // @[RegisterRouter.scala:87:24] wire out_woready_1_531; // @[RegisterRouter.scala:87:24] wire out_woready_1_532; // @[RegisterRouter.scala:87:24] wire out_woready_1_533; // @[RegisterRouter.scala:87:24] wire out_woready_1_534; // @[RegisterRouter.scala:87:24] wire out_woready_1_535; // @[RegisterRouter.scala:87:24] wire out_woready_1_536; // @[RegisterRouter.scala:87:24] wire out_woready_1_537; // @[RegisterRouter.scala:87:24] wire out_woready_1_538; // @[RegisterRouter.scala:87:24] wire out_woready_1_539; // @[RegisterRouter.scala:87:24] wire out_woready_1_540; // @[RegisterRouter.scala:87:24] wire out_woready_1_541; // @[RegisterRouter.scala:87:24] wire out_woready_1_542; // @[RegisterRouter.scala:87:24] wire out_woready_1_543; // @[RegisterRouter.scala:87:24] wire out_woready_1_544; // @[RegisterRouter.scala:87:24] wire out_woready_1_545; // @[RegisterRouter.scala:87:24] wire out_woready_1_546; // @[RegisterRouter.scala:87:24] wire out_woready_1_547; // @[RegisterRouter.scala:87:24] wire out_woready_1_548; // @[RegisterRouter.scala:87:24] wire out_woready_1_549; // @[RegisterRouter.scala:87:24] wire out_woready_1_550; // @[RegisterRouter.scala:87:24] wire out_woready_1_551; // @[RegisterRouter.scala:87:24] wire out_woready_1_552; // @[RegisterRouter.scala:87:24] wire out_woready_1_553; // @[RegisterRouter.scala:87:24] wire out_woready_1_554; // @[RegisterRouter.scala:87:24] wire out_woready_1_555; // @[RegisterRouter.scala:87:24] wire out_woready_1_556; // @[RegisterRouter.scala:87:24] wire out_woready_1_557; // @[RegisterRouter.scala:87:24] wire out_woready_1_558; // @[RegisterRouter.scala:87:24] wire out_woready_1_559; // @[RegisterRouter.scala:87:24] wire out_woready_1_560; // @[RegisterRouter.scala:87:24] wire out_woready_1_561; // @[RegisterRouter.scala:87:24] wire out_woready_1_562; // @[RegisterRouter.scala:87:24] wire out_woready_1_563; // @[RegisterRouter.scala:87:24] wire out_woready_1_564; // @[RegisterRouter.scala:87:24] wire out_woready_1_565; // @[RegisterRouter.scala:87:24] wire out_woready_1_566; // @[RegisterRouter.scala:87:24] wire out_woready_1_567; // @[RegisterRouter.scala:87:24] wire out_woready_1_568; // @[RegisterRouter.scala:87:24] wire out_woready_1_569; // @[RegisterRouter.scala:87:24] wire out_woready_1_570; // @[RegisterRouter.scala:87:24] wire out_woready_1_571; // @[RegisterRouter.scala:87:24] wire out_woready_1_572; // @[RegisterRouter.scala:87:24] wire out_woready_1_573; // @[RegisterRouter.scala:87:24] wire out_woready_1_574; // @[RegisterRouter.scala:87:24] wire out_woready_1_575; // @[RegisterRouter.scala:87:24] wire out_woready_1_576; // @[RegisterRouter.scala:87:24] wire out_woready_1_577; // @[RegisterRouter.scala:87:24] wire out_woready_1_578; // @[RegisterRouter.scala:87:24] wire out_woready_1_579; // @[RegisterRouter.scala:87:24] wire out_woready_1_580; // @[RegisterRouter.scala:87:24] wire out_woready_1_581; // @[RegisterRouter.scala:87:24] wire out_woready_1_582; // @[RegisterRouter.scala:87:24] wire out_woready_1_583; // @[RegisterRouter.scala:87:24] wire out_woready_1_584; // @[RegisterRouter.scala:87:24] wire out_woready_1_585; // @[RegisterRouter.scala:87:24] wire out_woready_1_586; // @[RegisterRouter.scala:87:24] wire out_woready_1_587; // @[RegisterRouter.scala:87:24] wire out_woready_1_588; // @[RegisterRouter.scala:87:24] wire out_woready_1_589; // @[RegisterRouter.scala:87:24] wire out_woready_1_590; // @[RegisterRouter.scala:87:24] wire out_woready_1_591; // @[RegisterRouter.scala:87:24] wire out_woready_1_592; // @[RegisterRouter.scala:87:24] wire out_woready_1_593; // @[RegisterRouter.scala:87:24] wire out_woready_1_594; // @[RegisterRouter.scala:87:24] wire out_woready_1_595; // @[RegisterRouter.scala:87:24] wire out_woready_1_596; // @[RegisterRouter.scala:87:24] wire out_woready_1_597; // @[RegisterRouter.scala:87:24] wire out_woready_1_598; // @[RegisterRouter.scala:87:24] wire out_woready_1_599; // @[RegisterRouter.scala:87:24] wire out_woready_1_600; // @[RegisterRouter.scala:87:24] wire out_woready_1_601; // @[RegisterRouter.scala:87:24] wire out_woready_1_602; // @[RegisterRouter.scala:87:24] wire out_woready_1_603; // @[RegisterRouter.scala:87:24] wire out_woready_1_604; // @[RegisterRouter.scala:87:24] wire out_woready_1_605; // @[RegisterRouter.scala:87:24] wire out_woready_1_606; // @[RegisterRouter.scala:87:24] wire out_woready_1_607; // @[RegisterRouter.scala:87:24] wire out_woready_1_608; // @[RegisterRouter.scala:87:24] wire out_woready_1_609; // @[RegisterRouter.scala:87:24] wire out_woready_1_610; // @[RegisterRouter.scala:87:24] wire out_woready_1_611; // @[RegisterRouter.scala:87:24] wire out_woready_1_612; // @[RegisterRouter.scala:87:24] wire out_woready_1_613; // @[RegisterRouter.scala:87:24] wire out_woready_1_614; // @[RegisterRouter.scala:87:24] wire out_woready_1_615; // @[RegisterRouter.scala:87:24] wire out_woready_1_616; // @[RegisterRouter.scala:87:24] wire out_woready_1_617; // @[RegisterRouter.scala:87:24] wire out_woready_1_618; // @[RegisterRouter.scala:87:24] wire out_woready_1_619; // @[RegisterRouter.scala:87:24] wire out_woready_1_620; // @[RegisterRouter.scala:87:24] wire out_woready_1_621; // @[RegisterRouter.scala:87:24] wire out_woready_1_622; // @[RegisterRouter.scala:87:24] wire out_woready_1_623; // @[RegisterRouter.scala:87:24] wire out_woready_1_624; // @[RegisterRouter.scala:87:24] wire out_woready_1_625; // @[RegisterRouter.scala:87:24] wire out_woready_1_626; // @[RegisterRouter.scala:87:24] wire out_woready_1_627; // @[RegisterRouter.scala:87:24] wire out_woready_1_628; // @[RegisterRouter.scala:87:24] wire out_woready_1_629; // @[RegisterRouter.scala:87:24] wire out_woready_1_630; // @[RegisterRouter.scala:87:24] wire out_woready_1_631; // @[RegisterRouter.scala:87:24] wire out_woready_1_632; // @[RegisterRouter.scala:87:24] wire out_woready_1_633; // @[RegisterRouter.scala:87:24] wire out_woready_1_634; // @[RegisterRouter.scala:87:24] wire out_woready_1_635; // @[RegisterRouter.scala:87:24] wire out_woready_1_636; // @[RegisterRouter.scala:87:24] wire out_woready_1_637; // @[RegisterRouter.scala:87:24] wire out_woready_1_638; // @[RegisterRouter.scala:87:24] wire out_woready_1_639; // @[RegisterRouter.scala:87:24] wire out_woready_1_640; // @[RegisterRouter.scala:87:24] wire out_woready_1_641; // @[RegisterRouter.scala:87:24] wire out_woready_1_642; // @[RegisterRouter.scala:87:24] wire out_woready_1_643; // @[RegisterRouter.scala:87:24] wire out_woready_1_644; // @[RegisterRouter.scala:87:24] wire out_woready_1_645; // @[RegisterRouter.scala:87:24] wire out_woready_1_646; // @[RegisterRouter.scala:87:24] wire out_woready_1_647; // @[RegisterRouter.scala:87:24] wire out_woready_1_648; // @[RegisterRouter.scala:87:24] wire out_woready_1_649; // @[RegisterRouter.scala:87:24] wire out_woready_1_650; // @[RegisterRouter.scala:87:24] wire out_woready_1_651; // @[RegisterRouter.scala:87:24] wire out_woready_1_652; // @[RegisterRouter.scala:87:24] wire out_woready_1_653; // @[RegisterRouter.scala:87:24] wire out_woready_1_654; // @[RegisterRouter.scala:87:24] wire out_woready_1_655; // @[RegisterRouter.scala:87:24] wire out_woready_1_656; // @[RegisterRouter.scala:87:24] wire out_woready_1_657; // @[RegisterRouter.scala:87:24] wire out_woready_1_658; // @[RegisterRouter.scala:87:24] wire out_woready_1_659; // @[RegisterRouter.scala:87:24] wire out_woready_1_660; // @[RegisterRouter.scala:87:24] wire out_woready_1_661; // @[RegisterRouter.scala:87:24] wire out_woready_1_662; // @[RegisterRouter.scala:87:24] wire out_woready_1_663; // @[RegisterRouter.scala:87:24] wire out_woready_1_664; // @[RegisterRouter.scala:87:24] wire out_woready_1_665; // @[RegisterRouter.scala:87:24] wire out_woready_1_666; // @[RegisterRouter.scala:87:24] wire out_woready_1_667; // @[RegisterRouter.scala:87:24] wire out_woready_1_668; // @[RegisterRouter.scala:87:24] wire out_woready_1_669; // @[RegisterRouter.scala:87:24] wire out_woready_1_670; // @[RegisterRouter.scala:87:24] wire out_woready_1_671; // @[RegisterRouter.scala:87:24] wire out_woready_1_672; // @[RegisterRouter.scala:87:24] wire out_woready_1_673; // @[RegisterRouter.scala:87:24] wire out_woready_1_674; // @[RegisterRouter.scala:87:24] wire out_woready_1_675; // @[RegisterRouter.scala:87:24] wire out_woready_1_676; // @[RegisterRouter.scala:87:24] wire out_woready_1_677; // @[RegisterRouter.scala:87:24] wire out_woready_1_678; // @[RegisterRouter.scala:87:24] wire out_woready_1_679; // @[RegisterRouter.scala:87:24] wire out_woready_1_680; // @[RegisterRouter.scala:87:24] wire out_woready_1_681; // @[RegisterRouter.scala:87:24] wire out_woready_1_682; // @[RegisterRouter.scala:87:24] wire out_woready_1_683; // @[RegisterRouter.scala:87:24] wire out_woready_1_684; // @[RegisterRouter.scala:87:24] wire out_woready_1_685; // @[RegisterRouter.scala:87:24] wire out_woready_1_686; // @[RegisterRouter.scala:87:24] wire out_woready_1_687; // @[RegisterRouter.scala:87:24] wire out_woready_1_688; // @[RegisterRouter.scala:87:24] wire out_woready_1_689; // @[RegisterRouter.scala:87:24] wire out_woready_1_690; // @[RegisterRouter.scala:87:24] wire out_woready_1_691; // @[RegisterRouter.scala:87:24] wire out_woready_1_692; // @[RegisterRouter.scala:87:24] wire out_woready_1_693; // @[RegisterRouter.scala:87:24] wire out_woready_1_694; // @[RegisterRouter.scala:87:24] wire out_woready_1_695; // @[RegisterRouter.scala:87:24] wire out_woready_1_696; // @[RegisterRouter.scala:87:24] wire out_woready_1_697; // @[RegisterRouter.scala:87:24] wire out_woready_1_698; // @[RegisterRouter.scala:87:24] wire out_woready_1_699; // @[RegisterRouter.scala:87:24] wire out_woready_1_700; // @[RegisterRouter.scala:87:24] wire out_woready_1_701; // @[RegisterRouter.scala:87:24] wire out_woready_1_702; // @[RegisterRouter.scala:87:24] wire out_woready_1_703; // @[RegisterRouter.scala:87:24] wire out_woready_1_704; // @[RegisterRouter.scala:87:24] wire out_woready_1_705; // @[RegisterRouter.scala:87:24] wire out_woready_1_706; // @[RegisterRouter.scala:87:24] wire out_woready_1_707; // @[RegisterRouter.scala:87:24] wire out_woready_1_708; // @[RegisterRouter.scala:87:24] wire out_woready_1_709; // @[RegisterRouter.scala:87:24] wire out_woready_1_710; // @[RegisterRouter.scala:87:24] wire out_woready_1_711; // @[RegisterRouter.scala:87:24] wire out_woready_1_712; // @[RegisterRouter.scala:87:24] wire out_woready_1_713; // @[RegisterRouter.scala:87:24] wire out_woready_1_714; // @[RegisterRouter.scala:87:24] wire out_woready_1_715; // @[RegisterRouter.scala:87:24] wire out_woready_1_716; // @[RegisterRouter.scala:87:24] wire out_woready_1_717; // @[RegisterRouter.scala:87:24] wire out_woready_1_718; // @[RegisterRouter.scala:87:24] wire out_woready_1_719; // @[RegisterRouter.scala:87:24] wire out_woready_1_720; // @[RegisterRouter.scala:87:24] wire out_woready_1_721; // @[RegisterRouter.scala:87:24] wire out_woready_1_722; // @[RegisterRouter.scala:87:24] wire out_woready_1_723; // @[RegisterRouter.scala:87:24] wire out_woready_1_724; // @[RegisterRouter.scala:87:24] wire out_woready_1_725; // @[RegisterRouter.scala:87:24] wire out_woready_1_726; // @[RegisterRouter.scala:87:24] wire out_woready_1_727; // @[RegisterRouter.scala:87:24] wire out_woready_1_728; // @[RegisterRouter.scala:87:24] wire out_woready_1_729; // @[RegisterRouter.scala:87:24] wire out_woready_1_730; // @[RegisterRouter.scala:87:24] wire out_woready_1_731; // @[RegisterRouter.scala:87:24] wire out_woready_1_732; // @[RegisterRouter.scala:87:24] wire out_woready_1_733; // @[RegisterRouter.scala:87:24] wire out_woready_1_734; // @[RegisterRouter.scala:87:24] wire out_woready_1_735; // @[RegisterRouter.scala:87:24] wire out_woready_1_736; // @[RegisterRouter.scala:87:24] wire out_woready_1_737; // @[RegisterRouter.scala:87:24] wire out_woready_1_738; // @[RegisterRouter.scala:87:24] wire out_woready_1_739; // @[RegisterRouter.scala:87:24] wire out_woready_1_740; // @[RegisterRouter.scala:87:24] wire out_woready_1_741; // @[RegisterRouter.scala:87:24] wire out_woready_1_742; // @[RegisterRouter.scala:87:24] wire out_woready_1_743; // @[RegisterRouter.scala:87:24] wire out_woready_1_744; // @[RegisterRouter.scala:87:24] wire out_woready_1_745; // @[RegisterRouter.scala:87:24] wire out_woready_1_746; // @[RegisterRouter.scala:87:24] wire out_woready_1_747; // @[RegisterRouter.scala:87:24] wire out_woready_1_748; // @[RegisterRouter.scala:87:24] wire out_woready_1_749; // @[RegisterRouter.scala:87:24] wire out_woready_1_750; // @[RegisterRouter.scala:87:24] wire out_woready_1_751; // @[RegisterRouter.scala:87:24] wire out_woready_1_752; // @[RegisterRouter.scala:87:24] wire out_woready_1_753; // @[RegisterRouter.scala:87:24] wire out_woready_1_754; // @[RegisterRouter.scala:87:24] wire out_woready_1_755; // @[RegisterRouter.scala:87:24] wire out_woready_1_756; // @[RegisterRouter.scala:87:24] wire out_woready_1_757; // @[RegisterRouter.scala:87:24] wire out_woready_1_758; // @[RegisterRouter.scala:87:24] wire out_woready_1_759; // @[RegisterRouter.scala:87:24] wire out_woready_1_760; // @[RegisterRouter.scala:87:24] wire out_woready_1_761; // @[RegisterRouter.scala:87:24] wire out_woready_1_762; // @[RegisterRouter.scala:87:24] wire out_woready_1_763; // @[RegisterRouter.scala:87:24] wire out_woready_1_764; // @[RegisterRouter.scala:87:24] wire out_woready_1_765; // @[RegisterRouter.scala:87:24] wire out_woready_1_766; // @[RegisterRouter.scala:87:24] wire out_woready_1_767; // @[RegisterRouter.scala:87:24] wire out_woready_1_768; // @[RegisterRouter.scala:87:24] wire out_woready_1_769; // @[RegisterRouter.scala:87:24] wire out_woready_1_770; // @[RegisterRouter.scala:87:24] wire out_woready_1_771; // @[RegisterRouter.scala:87:24] wire out_woready_1_772; // @[RegisterRouter.scala:87:24] wire out_woready_1_773; // @[RegisterRouter.scala:87:24] wire out_woready_1_774; // @[RegisterRouter.scala:87:24] wire out_woready_1_775; // @[RegisterRouter.scala:87:24] wire out_woready_1_776; // @[RegisterRouter.scala:87:24] wire out_woready_1_777; // @[RegisterRouter.scala:87:24] wire out_woready_1_778; // @[RegisterRouter.scala:87:24] wire out_woready_1_779; // @[RegisterRouter.scala:87:24] wire out_woready_1_780; // @[RegisterRouter.scala:87:24] wire out_woready_1_781; // @[RegisterRouter.scala:87:24] wire out_woready_1_782; // @[RegisterRouter.scala:87:24] wire out_woready_1_783; // @[RegisterRouter.scala:87:24] wire out_woready_1_784; // @[RegisterRouter.scala:87:24] wire out_woready_1_785; // @[RegisterRouter.scala:87:24] wire out_woready_1_786; // @[RegisterRouter.scala:87:24] wire out_woready_1_787; // @[RegisterRouter.scala:87:24] wire out_woready_1_788; // @[RegisterRouter.scala:87:24] wire out_woready_1_789; // @[RegisterRouter.scala:87:24] wire out_woready_1_790; // @[RegisterRouter.scala:87:24] wire out_woready_1_791; // @[RegisterRouter.scala:87:24] wire out_woready_1_792; // @[RegisterRouter.scala:87:24] wire out_woready_1_793; // @[RegisterRouter.scala:87:24] wire out_woready_1_794; // @[RegisterRouter.scala:87:24] wire out_woready_1_795; // @[RegisterRouter.scala:87:24] wire out_woready_1_796; // @[RegisterRouter.scala:87:24] wire out_woready_1_797; // @[RegisterRouter.scala:87:24] wire out_woready_1_798; // @[RegisterRouter.scala:87:24] wire out_woready_1_799; // @[RegisterRouter.scala:87:24] wire out_woready_1_800; // @[RegisterRouter.scala:87:24] wire out_woready_1_801; // @[RegisterRouter.scala:87:24] wire out_woready_1_802; // @[RegisterRouter.scala:87:24] wire out_woready_1_803; // @[RegisterRouter.scala:87:24] wire out_woready_1_804; // @[RegisterRouter.scala:87:24] wire out_woready_1_805; // @[RegisterRouter.scala:87:24] wire out_woready_1_806; // @[RegisterRouter.scala:87:24] wire out_woready_1_807; // @[RegisterRouter.scala:87:24] wire out_woready_1_808; // @[RegisterRouter.scala:87:24] wire out_woready_1_809; // @[RegisterRouter.scala:87:24] wire out_woready_1_810; // @[RegisterRouter.scala:87:24] wire out_woready_1_811; // @[RegisterRouter.scala:87:24] wire out_woready_1_812; // @[RegisterRouter.scala:87:24] wire out_woready_1_813; // @[RegisterRouter.scala:87:24] wire out_woready_1_814; // @[RegisterRouter.scala:87:24] wire out_woready_1_815; // @[RegisterRouter.scala:87:24] wire out_woready_1_816; // @[RegisterRouter.scala:87:24] wire out_woready_1_817; // @[RegisterRouter.scala:87:24] wire out_woready_1_818; // @[RegisterRouter.scala:87:24] wire out_woready_1_819; // @[RegisterRouter.scala:87:24] wire out_woready_1_820; // @[RegisterRouter.scala:87:24] wire out_woready_1_821; // @[RegisterRouter.scala:87:24] wire out_woready_1_822; // @[RegisterRouter.scala:87:24] wire out_woready_1_823; // @[RegisterRouter.scala:87:24] wire out_woready_1_824; // @[RegisterRouter.scala:87:24] wire out_woready_1_825; // @[RegisterRouter.scala:87:24] wire out_woready_1_826; // @[RegisterRouter.scala:87:24] wire out_woready_1_827; // @[RegisterRouter.scala:87:24] wire out_woready_1_828; // @[RegisterRouter.scala:87:24] wire out_woready_1_829; // @[RegisterRouter.scala:87:24] wire out_woready_1_830; // @[RegisterRouter.scala:87:24] wire out_woready_1_831; // @[RegisterRouter.scala:87:24] wire out_woready_1_832; // @[RegisterRouter.scala:87:24] wire out_woready_1_833; // @[RegisterRouter.scala:87:24] wire out_woready_1_834; // @[RegisterRouter.scala:87:24] wire out_woready_1_835; // @[RegisterRouter.scala:87:24] wire out_woready_1_836; // @[RegisterRouter.scala:87:24] wire out_woready_1_837; // @[RegisterRouter.scala:87:24] wire out_woready_1_838; // @[RegisterRouter.scala:87:24] wire out_woready_1_839; // @[RegisterRouter.scala:87:24] wire out_woready_1_840; // @[RegisterRouter.scala:87:24] wire out_woready_1_841; // @[RegisterRouter.scala:87:24] wire out_woready_1_842; // @[RegisterRouter.scala:87:24] wire out_woready_1_843; // @[RegisterRouter.scala:87:24] wire out_woready_1_844; // @[RegisterRouter.scala:87:24] wire out_woready_1_845; // @[RegisterRouter.scala:87:24] wire out_woready_1_846; // @[RegisterRouter.scala:87:24] wire out_woready_1_847; // @[RegisterRouter.scala:87:24] wire out_woready_1_848; // @[RegisterRouter.scala:87:24] wire out_woready_1_849; // @[RegisterRouter.scala:87:24] wire out_woready_1_850; // @[RegisterRouter.scala:87:24] wire out_woready_1_851; // @[RegisterRouter.scala:87:24] wire out_woready_1_852; // @[RegisterRouter.scala:87:24] wire out_woready_1_853; // @[RegisterRouter.scala:87:24] wire out_woready_1_854; // @[RegisterRouter.scala:87:24] wire out_woready_1_855; // @[RegisterRouter.scala:87:24] wire out_woready_1_856; // @[RegisterRouter.scala:87:24] wire out_woready_1_857; // @[RegisterRouter.scala:87:24] wire out_woready_1_858; // @[RegisterRouter.scala:87:24] wire out_woready_1_859; // @[RegisterRouter.scala:87:24] wire out_woready_1_860; // @[RegisterRouter.scala:87:24] wire out_woready_1_861; // @[RegisterRouter.scala:87:24] wire out_woready_1_862; // @[RegisterRouter.scala:87:24] wire out_woready_1_863; // @[RegisterRouter.scala:87:24] wire out_woready_1_864; // @[RegisterRouter.scala:87:24] wire out_woready_1_865; // @[RegisterRouter.scala:87:24] wire out_woready_1_866; // @[RegisterRouter.scala:87:24] wire out_woready_1_867; // @[RegisterRouter.scala:87:24] wire out_woready_1_868; // @[RegisterRouter.scala:87:24] wire out_woready_1_869; // @[RegisterRouter.scala:87:24] wire out_woready_1_870; // @[RegisterRouter.scala:87:24] wire out_woready_1_871; // @[RegisterRouter.scala:87:24] wire out_woready_1_872; // @[RegisterRouter.scala:87:24] wire out_woready_1_873; // @[RegisterRouter.scala:87:24] wire out_woready_1_874; // @[RegisterRouter.scala:87:24] wire out_woready_1_875; // @[RegisterRouter.scala:87:24] wire out_woready_1_876; // @[RegisterRouter.scala:87:24] wire out_woready_1_877; // @[RegisterRouter.scala:87:24] wire out_woready_1_878; // @[RegisterRouter.scala:87:24] wire out_woready_1_879; // @[RegisterRouter.scala:87:24] wire out_woready_1_880; // @[RegisterRouter.scala:87:24] wire out_woready_1_881; // @[RegisterRouter.scala:87:24] wire out_woready_1_882; // @[RegisterRouter.scala:87:24] wire out_woready_1_883; // @[RegisterRouter.scala:87:24] wire out_woready_1_884; // @[RegisterRouter.scala:87:24] wire out_woready_1_885; // @[RegisterRouter.scala:87:24] wire out_woready_1_886; // @[RegisterRouter.scala:87:24] wire out_woready_1_887; // @[RegisterRouter.scala:87:24] wire out_woready_1_888; // @[RegisterRouter.scala:87:24] wire out_woready_1_889; // @[RegisterRouter.scala:87:24] wire out_woready_1_890; // @[RegisterRouter.scala:87:24] wire out_woready_1_891; // @[RegisterRouter.scala:87:24] wire out_woready_1_892; // @[RegisterRouter.scala:87:24] wire out_woready_1_893; // @[RegisterRouter.scala:87:24] wire out_woready_1_894; // @[RegisterRouter.scala:87:24] wire out_woready_1_895; // @[RegisterRouter.scala:87:24] wire out_woready_1_896; // @[RegisterRouter.scala:87:24] wire out_woready_1_897; // @[RegisterRouter.scala:87:24] wire out_woready_1_898; // @[RegisterRouter.scala:87:24] wire out_woready_1_899; // @[RegisterRouter.scala:87:24] wire out_woready_1_900; // @[RegisterRouter.scala:87:24] wire out_woready_1_901; // @[RegisterRouter.scala:87:24] wire out_woready_1_902; // @[RegisterRouter.scala:87:24] wire out_woready_1_903; // @[RegisterRouter.scala:87:24] wire out_woready_1_904; // @[RegisterRouter.scala:87:24] wire out_woready_1_905; // @[RegisterRouter.scala:87:24] wire out_woready_1_906; // @[RegisterRouter.scala:87:24] wire out_woready_1_907; // @[RegisterRouter.scala:87:24] wire out_woready_1_908; // @[RegisterRouter.scala:87:24] wire out_woready_1_909; // @[RegisterRouter.scala:87:24] wire out_woready_1_910; // @[RegisterRouter.scala:87:24] wire out_woready_1_911; // @[RegisterRouter.scala:87:24] wire out_woready_1_912; // @[RegisterRouter.scala:87:24] wire out_woready_1_913; // @[RegisterRouter.scala:87:24] wire out_woready_1_914; // @[RegisterRouter.scala:87:24] wire out_woready_1_915; // @[RegisterRouter.scala:87:24] wire out_woready_1_916; // @[RegisterRouter.scala:87:24] wire out_woready_1_917; // @[RegisterRouter.scala:87:24] wire out_woready_1_918; // @[RegisterRouter.scala:87:24] wire out_woready_1_919; // @[RegisterRouter.scala:87:24] wire out_woready_1_920; // @[RegisterRouter.scala:87:24] wire out_woready_1_921; // @[RegisterRouter.scala:87:24] wire out_woready_1_922; // @[RegisterRouter.scala:87:24] wire out_woready_1_923; // @[RegisterRouter.scala:87:24] wire out_woready_1_924; // @[RegisterRouter.scala:87:24] wire out_woready_1_925; // @[RegisterRouter.scala:87:24] wire out_woready_1_926; // @[RegisterRouter.scala:87:24] wire out_woready_1_927; // @[RegisterRouter.scala:87:24] wire out_woready_1_928; // @[RegisterRouter.scala:87:24] wire out_woready_1_929; // @[RegisterRouter.scala:87:24] wire out_woready_1_930; // @[RegisterRouter.scala:87:24] wire out_woready_1_931; // @[RegisterRouter.scala:87:24] wire out_woready_1_932; // @[RegisterRouter.scala:87:24] wire out_woready_1_933; // @[RegisterRouter.scala:87:24] wire out_woready_1_934; // @[RegisterRouter.scala:87:24] wire out_woready_1_935; // @[RegisterRouter.scala:87:24] wire out_woready_1_936; // @[RegisterRouter.scala:87:24] wire out_woready_1_937; // @[RegisterRouter.scala:87:24] wire out_woready_1_938; // @[RegisterRouter.scala:87:24] wire out_woready_1_939; // @[RegisterRouter.scala:87:24] wire out_woready_1_940; // @[RegisterRouter.scala:87:24] wire out_woready_1_941; // @[RegisterRouter.scala:87:24] wire out_woready_1_942; // @[RegisterRouter.scala:87:24] wire out_woready_1_943; // @[RegisterRouter.scala:87:24] wire out_woready_1_944; // @[RegisterRouter.scala:87:24] wire out_woready_1_945; // @[RegisterRouter.scala:87:24] wire out_woready_1_946; // @[RegisterRouter.scala:87:24] wire out_woready_1_947; // @[RegisterRouter.scala:87:24] wire out_woready_1_948; // @[RegisterRouter.scala:87:24] wire out_woready_1_949; // @[RegisterRouter.scala:87:24] wire out_woready_1_950; // @[RegisterRouter.scala:87:24] wire out_woready_1_951; // @[RegisterRouter.scala:87:24] wire out_woready_1_952; // @[RegisterRouter.scala:87:24] wire out_woready_1_953; // @[RegisterRouter.scala:87:24] wire out_woready_1_954; // @[RegisterRouter.scala:87:24] wire out_woready_1_955; // @[RegisterRouter.scala:87:24] wire out_woready_1_956; // @[RegisterRouter.scala:87:24] wire out_woready_1_957; // @[RegisterRouter.scala:87:24] wire out_woready_1_958; // @[RegisterRouter.scala:87:24] wire out_woready_1_959; // @[RegisterRouter.scala:87:24] wire out_woready_1_960; // @[RegisterRouter.scala:87:24] wire out_woready_1_961; // @[RegisterRouter.scala:87:24] wire out_woready_1_962; // @[RegisterRouter.scala:87:24] wire out_woready_1_963; // @[RegisterRouter.scala:87:24] wire out_woready_1_964; // @[RegisterRouter.scala:87:24] wire out_woready_1_965; // @[RegisterRouter.scala:87:24] wire out_woready_1_966; // @[RegisterRouter.scala:87:24] wire out_woready_1_967; // @[RegisterRouter.scala:87:24] wire out_woready_1_968; // @[RegisterRouter.scala:87:24] wire out_woready_1_969; // @[RegisterRouter.scala:87:24] wire out_woready_1_970; // @[RegisterRouter.scala:87:24] wire out_woready_1_971; // @[RegisterRouter.scala:87:24] wire out_woready_1_972; // @[RegisterRouter.scala:87:24] wire out_woready_1_973; // @[RegisterRouter.scala:87:24] wire out_woready_1_974; // @[RegisterRouter.scala:87:24] wire out_woready_1_975; // @[RegisterRouter.scala:87:24] wire out_woready_1_976; // @[RegisterRouter.scala:87:24] wire out_woready_1_977; // @[RegisterRouter.scala:87:24] wire out_woready_1_978; // @[RegisterRouter.scala:87:24] wire out_woready_1_979; // @[RegisterRouter.scala:87:24] wire out_woready_1_980; // @[RegisterRouter.scala:87:24] wire out_woready_1_981; // @[RegisterRouter.scala:87:24] wire out_woready_1_982; // @[RegisterRouter.scala:87:24] wire out_woready_1_983; // @[RegisterRouter.scala:87:24] wire out_woready_1_984; // @[RegisterRouter.scala:87:24] wire out_woready_1_985; // @[RegisterRouter.scala:87:24] wire out_woready_1_986; // @[RegisterRouter.scala:87:24] wire out_woready_1_987; // @[RegisterRouter.scala:87:24] wire out_woready_1_988; // @[RegisterRouter.scala:87:24] wire out_woready_1_989; // @[RegisterRouter.scala:87:24] wire out_woready_1_990; // @[RegisterRouter.scala:87:24] wire out_woready_1_991; // @[RegisterRouter.scala:87:24] wire out_woready_1_992; // @[RegisterRouter.scala:87:24] wire out_woready_1_993; // @[RegisterRouter.scala:87:24] wire out_woready_1_994; // @[RegisterRouter.scala:87:24] wire out_woready_1_995; // @[RegisterRouter.scala:87:24] wire out_woready_1_996; // @[RegisterRouter.scala:87:24] wire out_woready_1_997; // @[RegisterRouter.scala:87:24] wire out_woready_1_998; // @[RegisterRouter.scala:87:24] wire out_woready_1_999; // @[RegisterRouter.scala:87:24] wire out_woready_1_1000; // @[RegisterRouter.scala:87:24] wire out_woready_1_1001; // @[RegisterRouter.scala:87:24] wire out_woready_1_1002; // @[RegisterRouter.scala:87:24] wire out_woready_1_1003; // @[RegisterRouter.scala:87:24] wire out_woready_1_1004; // @[RegisterRouter.scala:87:24] wire out_woready_1_1005; // @[RegisterRouter.scala:87:24] wire out_woready_1_1006; // @[RegisterRouter.scala:87:24] wire out_woready_1_1007; // @[RegisterRouter.scala:87:24] wire out_woready_1_1008; // @[RegisterRouter.scala:87:24] wire out_woready_1_1009; // @[RegisterRouter.scala:87:24] wire out_woready_1_1010; // @[RegisterRouter.scala:87:24] wire out_woready_1_1011; // @[RegisterRouter.scala:87:24] wire out_woready_1_1012; // @[RegisterRouter.scala:87:24] wire out_woready_1_1013; // @[RegisterRouter.scala:87:24] wire out_woready_1_1014; // @[RegisterRouter.scala:87:24] wire out_woready_1_1015; // @[RegisterRouter.scala:87:24] wire out_woready_1_1016; // @[RegisterRouter.scala:87:24] wire out_woready_1_1017; // @[RegisterRouter.scala:87:24] wire out_woready_1_1018; // @[RegisterRouter.scala:87:24] wire out_woready_1_1019; // @[RegisterRouter.scala:87:24] wire out_woready_1_1020; // @[RegisterRouter.scala:87:24] wire out_woready_1_1021; // @[RegisterRouter.scala:87:24] wire out_woready_1_1022; // @[RegisterRouter.scala:87:24] wire out_woready_1_1023; // @[RegisterRouter.scala:87:24] wire out_woready_1_1024; // @[RegisterRouter.scala:87:24] wire out_woready_1_1025; // @[RegisterRouter.scala:87:24] wire out_woready_1_1026; // @[RegisterRouter.scala:87:24] wire out_woready_1_1027; // @[RegisterRouter.scala:87:24] wire out_woready_1_1028; // @[RegisterRouter.scala:87:24] wire out_woready_1_1029; // @[RegisterRouter.scala:87:24] wire out_woready_1_1030; // @[RegisterRouter.scala:87:24] wire out_woready_1_1031; // @[RegisterRouter.scala:87:24] wire out_woready_1_1032; // @[RegisterRouter.scala:87:24] wire out_woready_1_1033; // @[RegisterRouter.scala:87:24] wire out_woready_1_1034; // @[RegisterRouter.scala:87:24] wire out_woready_1_1035; // @[RegisterRouter.scala:87:24] wire out_woready_1_1036; // @[RegisterRouter.scala:87:24] wire out_woready_1_1037; // @[RegisterRouter.scala:87:24] wire out_woready_1_1038; // @[RegisterRouter.scala:87:24] wire out_woready_1_1039; // @[RegisterRouter.scala:87:24] wire out_woready_1_1040; // @[RegisterRouter.scala:87:24] wire out_woready_1_1041; // @[RegisterRouter.scala:87:24] wire out_woready_1_1042; // @[RegisterRouter.scala:87:24] wire out_woready_1_1043; // @[RegisterRouter.scala:87:24] wire out_woready_1_1044; // @[RegisterRouter.scala:87:24] wire out_woready_1_1045; // @[RegisterRouter.scala:87:24] wire out_woready_1_1046; // @[RegisterRouter.scala:87:24] wire out_woready_1_1047; // @[RegisterRouter.scala:87:24] wire out_woready_1_1048; // @[RegisterRouter.scala:87:24] wire out_woready_1_1049; // @[RegisterRouter.scala:87:24] wire out_woready_1_1050; // @[RegisterRouter.scala:87:24] wire out_woready_1_1051; // @[RegisterRouter.scala:87:24] wire out_woready_1_1052; // @[RegisterRouter.scala:87:24] wire out_woready_1_1053; // @[RegisterRouter.scala:87:24] wire out_woready_1_1054; // @[RegisterRouter.scala:87:24] wire out_woready_1_1055; // @[RegisterRouter.scala:87:24] wire out_woready_1_1056; // @[RegisterRouter.scala:87:24] wire out_woready_1_1057; // @[RegisterRouter.scala:87:24] wire out_woready_1_1058; // @[RegisterRouter.scala:87:24] wire out_woready_1_1059; // @[RegisterRouter.scala:87:24] wire out_woready_1_1060; // @[RegisterRouter.scala:87:24] wire out_woready_1_1061; // @[RegisterRouter.scala:87:24] wire out_woready_1_1062; // @[RegisterRouter.scala:87:24] wire out_woready_1_1063; // @[RegisterRouter.scala:87:24] wire out_woready_1_1064; // @[RegisterRouter.scala:87:24] wire out_woready_1_1065; // @[RegisterRouter.scala:87:24] wire out_woready_1_1066; // @[RegisterRouter.scala:87:24] wire out_woready_1_1067; // @[RegisterRouter.scala:87:24] wire out_woready_1_1068; // @[RegisterRouter.scala:87:24] wire out_woready_1_1069; // @[RegisterRouter.scala:87:24] wire out_woready_1_1070; // @[RegisterRouter.scala:87:24] wire out_woready_1_1071; // @[RegisterRouter.scala:87:24] wire out_woready_1_1072; // @[RegisterRouter.scala:87:24] wire out_woready_1_1073; // @[RegisterRouter.scala:87:24] wire out_woready_1_1074; // @[RegisterRouter.scala:87:24] wire out_woready_1_1075; // @[RegisterRouter.scala:87:24] wire out_woready_1_1076; // @[RegisterRouter.scala:87:24] wire out_woready_1_1077; // @[RegisterRouter.scala:87:24] wire out_woready_1_1078; // @[RegisterRouter.scala:87:24] wire out_woready_1_1079; // @[RegisterRouter.scala:87:24] wire out_woready_1_1080; // @[RegisterRouter.scala:87:24] wire out_woready_1_1081; // @[RegisterRouter.scala:87:24] wire out_woready_1_1082; // @[RegisterRouter.scala:87:24] wire out_woready_1_1083; // @[RegisterRouter.scala:87:24] wire out_woready_1_1084; // @[RegisterRouter.scala:87:24] wire out_woready_1_1085; // @[RegisterRouter.scala:87:24] wire out_woready_1_1086; // @[RegisterRouter.scala:87:24] wire out_woready_1_1087; // @[RegisterRouter.scala:87:24] wire out_woready_1_1088; // @[RegisterRouter.scala:87:24] wire out_woready_1_1089; // @[RegisterRouter.scala:87:24] wire out_woready_1_1090; // @[RegisterRouter.scala:87:24] wire out_woready_1_1091; // @[RegisterRouter.scala:87:24] wire out_woready_1_1092; // @[RegisterRouter.scala:87:24] wire out_woready_1_1093; // @[RegisterRouter.scala:87:24] wire out_woready_1_1094; // @[RegisterRouter.scala:87:24] wire out_woready_1_1095; // @[RegisterRouter.scala:87:24] wire out_woready_1_1096; // @[RegisterRouter.scala:87:24] wire out_woready_1_1097; // @[RegisterRouter.scala:87:24] wire out_woready_1_1098; // @[RegisterRouter.scala:87:24] wire out_woready_1_1099; // @[RegisterRouter.scala:87:24] wire out_woready_1_1100; // @[RegisterRouter.scala:87:24] wire out_woready_1_1101; // @[RegisterRouter.scala:87:24] wire out_woready_1_1102; // @[RegisterRouter.scala:87:24] wire out_woready_1_1103; // @[RegisterRouter.scala:87:24] wire out_woready_1_1104; // @[RegisterRouter.scala:87:24] wire out_woready_1_1105; // @[RegisterRouter.scala:87:24] wire out_woready_1_1106; // @[RegisterRouter.scala:87:24] wire out_woready_1_1107; // @[RegisterRouter.scala:87:24] wire out_woready_1_1108; // @[RegisterRouter.scala:87:24] wire out_woready_1_1109; // @[RegisterRouter.scala:87:24] wire out_woready_1_1110; // @[RegisterRouter.scala:87:24] wire out_woready_1_1111; // @[RegisterRouter.scala:87:24] wire out_woready_1_1112; // @[RegisterRouter.scala:87:24] wire out_woready_1_1113; // @[RegisterRouter.scala:87:24] wire out_woready_1_1114; // @[RegisterRouter.scala:87:24] wire out_woready_1_1115; // @[RegisterRouter.scala:87:24] wire out_woready_1_1116; // @[RegisterRouter.scala:87:24] wire out_woready_1_1117; // @[RegisterRouter.scala:87:24] wire out_woready_1_1118; // @[RegisterRouter.scala:87:24] wire out_woready_1_1119; // @[RegisterRouter.scala:87:24] wire out_woready_1_1120; // @[RegisterRouter.scala:87:24] wire out_woready_1_1121; // @[RegisterRouter.scala:87:24] wire out_woready_1_1122; // @[RegisterRouter.scala:87:24] wire out_woready_1_1123; // @[RegisterRouter.scala:87:24] wire out_woready_1_1124; // @[RegisterRouter.scala:87:24] wire out_woready_1_1125; // @[RegisterRouter.scala:87:24] wire out_woready_1_1126; // @[RegisterRouter.scala:87:24] wire out_woready_1_1127; // @[RegisterRouter.scala:87:24] wire out_woready_1_1128; // @[RegisterRouter.scala:87:24] wire out_woready_1_1129; // @[RegisterRouter.scala:87:24] wire out_woready_1_1130; // @[RegisterRouter.scala:87:24] wire out_woready_1_1131; // @[RegisterRouter.scala:87:24] wire out_woready_1_1132; // @[RegisterRouter.scala:87:24] wire out_woready_1_1133; // @[RegisterRouter.scala:87:24] wire out_woready_1_1134; // @[RegisterRouter.scala:87:24] wire out_woready_1_1135; // @[RegisterRouter.scala:87:24] wire out_woready_1_1136; // @[RegisterRouter.scala:87:24] wire out_woready_1_1137; // @[RegisterRouter.scala:87:24] wire out_woready_1_1138; // @[RegisterRouter.scala:87:24] wire out_woready_1_1139; // @[RegisterRouter.scala:87:24] wire out_woready_1_1140; // @[RegisterRouter.scala:87:24] wire out_woready_1_1141; // @[RegisterRouter.scala:87:24] wire out_woready_1_1142; // @[RegisterRouter.scala:87:24] wire out_woready_1_1143; // @[RegisterRouter.scala:87:24] wire out_woready_1_1144; // @[RegisterRouter.scala:87:24] wire out_woready_1_1145; // @[RegisterRouter.scala:87:24] wire out_woready_1_1146; // @[RegisterRouter.scala:87:24] wire out_woready_1_1147; // @[RegisterRouter.scala:87:24] wire out_woready_1_1148; // @[RegisterRouter.scala:87:24] wire out_woready_1_1149; // @[RegisterRouter.scala:87:24] wire out_woready_1_1150; // @[RegisterRouter.scala:87:24] wire out_woready_1_1151; // @[RegisterRouter.scala:87:24] wire out_woready_1_1152; // @[RegisterRouter.scala:87:24] wire out_woready_1_1153; // @[RegisterRouter.scala:87:24] wire out_woready_1_1154; // @[RegisterRouter.scala:87:24] wire out_woready_1_1155; // @[RegisterRouter.scala:87:24] wire out_woready_1_1156; // @[RegisterRouter.scala:87:24] wire out_woready_1_1157; // @[RegisterRouter.scala:87:24] wire out_woready_1_1158; // @[RegisterRouter.scala:87:24] wire out_woready_1_1159; // @[RegisterRouter.scala:87:24] wire out_woready_1_1160; // @[RegisterRouter.scala:87:24] wire out_woready_1_1161; // @[RegisterRouter.scala:87:24] wire out_woready_1_1162; // @[RegisterRouter.scala:87:24] wire out_woready_1_1163; // @[RegisterRouter.scala:87:24] wire out_woready_1_1164; // @[RegisterRouter.scala:87:24] wire out_woready_1_1165; // @[RegisterRouter.scala:87:24] wire out_woready_1_1166; // @[RegisterRouter.scala:87:24] wire out_woready_1_1167; // @[RegisterRouter.scala:87:24] wire out_woready_1_1168; // @[RegisterRouter.scala:87:24] wire out_woready_1_1169; // @[RegisterRouter.scala:87:24] wire out_woready_1_1170; // @[RegisterRouter.scala:87:24] wire out_woready_1_1171; // @[RegisterRouter.scala:87:24] wire out_woready_1_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_1173; // @[RegisterRouter.scala:87:24] wire out_woready_1_1174; // @[RegisterRouter.scala:87:24] wire out_woready_1_1175; // @[RegisterRouter.scala:87:24] wire out_woready_1_1176; // @[RegisterRouter.scala:87:24] wire out_woready_1_1177; // @[RegisterRouter.scala:87:24] wire out_woready_1_1178; // @[RegisterRouter.scala:87:24] wire out_woready_1_1179; // @[RegisterRouter.scala:87:24] wire out_woready_1_1180; // @[RegisterRouter.scala:87:24] wire out_woready_1_1181; // @[RegisterRouter.scala:87:24] wire out_woready_1_1182; // @[RegisterRouter.scala:87:24] wire out_woready_1_1183; // @[RegisterRouter.scala:87:24] wire out_woready_1_1184; // @[RegisterRouter.scala:87:24] wire out_woready_1_1185; // @[RegisterRouter.scala:87:24] wire out_woready_1_1186; // @[RegisterRouter.scala:87:24] wire out_woready_1_1187; // @[RegisterRouter.scala:87:24] wire out_woready_1_1188; // @[RegisterRouter.scala:87:24] wire out_woready_1_1189; // @[RegisterRouter.scala:87:24] wire out_woready_1_1190; // @[RegisterRouter.scala:87:24] wire out_woready_1_1191; // @[RegisterRouter.scala:87:24] wire out_woready_1_1192; // @[RegisterRouter.scala:87:24] wire out_woready_1_1193; // @[RegisterRouter.scala:87:24] wire out_woready_1_1194; // @[RegisterRouter.scala:87:24] wire out_woready_1_1195; // @[RegisterRouter.scala:87:24] wire out_woready_1_1196; // @[RegisterRouter.scala:87:24] wire out_woready_1_1197; // @[RegisterRouter.scala:87:24] wire out_woready_1_1198; // @[RegisterRouter.scala:87:24] wire out_woready_1_1199; // @[RegisterRouter.scala:87:24] wire out_woready_1_1200; // @[RegisterRouter.scala:87:24] wire out_woready_1_1201; // @[RegisterRouter.scala:87:24] wire out_woready_1_1202; // @[RegisterRouter.scala:87:24] wire out_woready_1_1203; // @[RegisterRouter.scala:87:24] wire out_woready_1_1204; // @[RegisterRouter.scala:87:24] wire out_woready_1_1205; // @[RegisterRouter.scala:87:24] wire out_woready_1_1206; // @[RegisterRouter.scala:87:24] wire out_woready_1_1207; // @[RegisterRouter.scala:87:24] wire out_woready_1_1208; // @[RegisterRouter.scala:87:24] wire out_woready_1_1209; // @[RegisterRouter.scala:87:24] wire out_woready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_16 = {8{_out_frontMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_17 = {8{_out_frontMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_18 = {8{_out_frontMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_19 = {8{_out_frontMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_20 = {8{_out_frontMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_21 = {8{_out_frontMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_22 = {8{_out_frontMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_23 = {8{_out_frontMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_17, _out_frontMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_19, _out_frontMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo_1 = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_21, _out_frontMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_23, _out_frontMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi_1 = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask_1 = {out_frontMask_hi_1, out_frontMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_16 = {8{_out_backMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_17 = {8{_out_backMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_18 = {8{_out_backMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_19 = {8{_out_backMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_20 = {8{_out_backMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_21 = {8{_out_backMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_22 = {8{_out_backMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_23 = {8{_out_backMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_17, _out_backMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_19, _out_backMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo_1 = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_21, _out_backMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_23, _out_backMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi_1 = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask_1 = {out_backMask_hi_1, out_backMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_146 = \|_out_rimask_T_146; // @[RegisterRouter.scala:87:24] wire out_wimask_146 = &_out_wimask_T_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_146 = \|_out_romask_T_146; // @[RegisterRouter.scala:87:24] wire out_womask_146 = &_out_womask_T_146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_146 = out_rivalid_1_0 & out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1911 = out_f_rivalid_146; // @[RegisterRouter.scala:87:24] wire out_f_roready_146 = out_roready_1_0 & out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1912 = out_f_roready_146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_146 = out_wivalid_1_0 & out_wimask_146; // @[RegisterRouter.scala:87:24] wire out_f_woready_146 = out_woready_1_0 & out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2126 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2198 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2286 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2358 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2430 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2502 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2574 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2646 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2718 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2790 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2862 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2934 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3022 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3094 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3166 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3238 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3310 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3382 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3454 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3526 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3598 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3670 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3758 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3830 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3902 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3974 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4046 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4118 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4190 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4262 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4334 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4406 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4478 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4550 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4622 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4694 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4766 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4838 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5144 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5216 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5288 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5360 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5432 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5504 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5576 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5648 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5720 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5792 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5864 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5945 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6357 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6429 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6501 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6573 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6661 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6733 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6823 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6895 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6967 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7039 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7111 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7183 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7255 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7327 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7399 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7471 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7543 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7615 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7687 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7759 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7831 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7903 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7991 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8063 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8135 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8207 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8297 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8369 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8441 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8513 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8585 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8961 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9393 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9465 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9625 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9697 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9769 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9841 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9913 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9985 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10057 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10129 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10201 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10273 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10345 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10417 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10505 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10577 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10649 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10721 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10793 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10865 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10953 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11025 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11097 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11169 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11241 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11313 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11385 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11457 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11529 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11601 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11977 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12049 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12121 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12193 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12265 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12337 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12409 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12481 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12641 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12713 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12785 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12857 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12929 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_1913 = ~out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1914 = ~out_wimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1915 = ~out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1916 = ~out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1918 = _out_T_1917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_112 = _out_T_1918; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_147 = \|_out_rimask_T_147; // @[RegisterRouter.scala:87:24] wire out_wimask_147 = &_out_wimask_T_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_147 = \|_out_romask_T_147; // @[RegisterRouter.scala:87:24] wire out_womask_147 = &_out_womask_T_147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_147 = out_rivalid_1_1 & out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1920 = out_f_rivalid_147; // @[RegisterRouter.scala:87:24] wire out_f_roready_147 = out_roready_1_1 & out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1921 = out_f_roready_147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_147 = out_wivalid_1_1 & out_wimask_147; // @[RegisterRouter.scala:87:24] wire out_f_woready_147 = out_woready_1_1 & out_womask_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2135 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2209 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2295 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2367 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2439 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2511 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2583 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2655 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2727 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2799 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2871 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2945 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3031 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3103 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3175 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3247 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3319 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3391 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3463 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3535 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3607 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3681 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3767 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3839 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3911 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3983 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4055 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4127 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4199 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4271 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4343 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4415 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4487 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4559 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4631 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4703 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4775 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4847 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5153 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5225 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5297 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5369 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5441 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5513 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5585 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5657 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5729 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5801 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5873 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5956 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6366 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6438 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6510 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6584 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6670 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6742 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6832 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6904 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6976 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7048 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7120 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7192 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7264 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7336 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7408 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7480 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7552 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7624 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7696 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7768 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7840 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7914 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8000 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8072 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8144 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8216 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8306 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8378 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8450 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8522 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8596 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8898 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8970 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9402 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9476 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9562 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9634 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9706 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9778 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9850 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9922 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9994 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10066 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10138 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10210 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10282 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10354 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10428 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10514 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10586 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10658 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10730 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10802 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10876 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10962 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11034 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11106 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11178 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11250 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11322 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11394 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11466 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11538 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11610 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11900 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11986 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12058 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12130 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12202 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12274 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12346 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12418 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12490 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12564 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12650 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12722 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12794 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12866 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12938 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_1922 = ~out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1923 = ~out_wimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1924 = ~out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1925 = ~out_womask_147; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_112 = {hi_82, flags_0_go, _out_prepend_T_112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1926 = out_prepend_112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1927 = _out_T_1926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_113 = _out_T_1927; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_148 = \|_out_rimask_T_148; // @[RegisterRouter.scala:87:24] wire out_wimask_148 = &_out_wimask_T_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_148 = \|_out_romask_T_148; // @[RegisterRouter.scala:87:24] wire out_womask_148 = &_out_womask_T_148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_148 = out_rivalid_1_2 & out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1929 = out_f_rivalid_148; // @[RegisterRouter.scala:87:24] wire out_f_roready_148 = out_roready_1_2 & out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1930 = out_f_roready_148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_148 = out_wivalid_1_2 & out_wimask_148; // @[RegisterRouter.scala:87:24] wire out_f_woready_148 = out_woready_1_2 & out_womask_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2144 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2220 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2304 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2376 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2448 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2520 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2592 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2664 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2736 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2808 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2880 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2956 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3040 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3112 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3184 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3256 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3328 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3400 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3472 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3544 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3616 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3692 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3776 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3848 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3920 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3992 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4064 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4136 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4208 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4280 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4352 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4424 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4496 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4568 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4640 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4712 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4784 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4856 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5162 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5234 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5306 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5378 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5450 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5522 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5594 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5666 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5738 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5810 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5882 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5967 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6375 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6447 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6519 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6679 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6751 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6841 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6913 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6985 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7057 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7129 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7201 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7273 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7345 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7417 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7489 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7561 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7633 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7705 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7777 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7849 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7925 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8009 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8081 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8153 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8225 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8315 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8387 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8459 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8531 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8607 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8907 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8979 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9411 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9487 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9571 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9643 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9715 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9787 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9859 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9931 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10003 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10075 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10147 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10219 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10291 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10363 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10439 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10523 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10667 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10739 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10811 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10887 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10971 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11043 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11115 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11187 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11259 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11331 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11403 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11475 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11547 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11619 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11911 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11995 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12067 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12139 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12211 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12283 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12355 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12427 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12499 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12575 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12659 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12731 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12803 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12875 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12947 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_1931 = ~out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1932 = ~out_wimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1933 = ~out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1934 = ~out_womask_148; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_113 = {hi_83, flags_0_go, _out_prepend_T_113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1935 = out_prepend_113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1936 = _out_T_1935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_114 = _out_T_1936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_149 = \|_out_rimask_T_149; // @[RegisterRouter.scala:87:24] wire out_wimask_149 = &_out_wimask_T_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_149 = \|_out_romask_T_149; // @[RegisterRouter.scala:87:24] wire out_womask_149 = &_out_womask_T_149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_149 = out_rivalid_1_3 & out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1938 = out_f_rivalid_149; // @[RegisterRouter.scala:87:24] wire out_f_roready_149 = out_roready_1_3 & out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1939 = out_f_roready_149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_149 = out_wivalid_1_3 & out_wimask_149; // @[RegisterRouter.scala:87:24] wire out_f_woready_149 = out_woready_1_3 & out_womask_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2153 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2231 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2313 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2385 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2457 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2529 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2601 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2673 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2745 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2817 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2889 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2967 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3049 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3121 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3193 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3265 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3337 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3409 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3481 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3553 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3625 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3703 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3785 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3857 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3929 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4001 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4073 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4145 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4217 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4289 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4361 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4433 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4505 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4577 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4649 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4721 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4793 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4865 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5171 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5243 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5315 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5387 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5459 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5531 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5603 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5675 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5747 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5819 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5891 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5978 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6384 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6456 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6528 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6606 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6688 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6760 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6850 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6994 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7066 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7138 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7210 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7282 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7354 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7426 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7570 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7642 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7714 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7786 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7858 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7936 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8018 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8090 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8162 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8234 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8324 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8396 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8468 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8540 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8618 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8916 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8988 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9420 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9580 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9652 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9724 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9796 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9868 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9940 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10012 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10084 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10156 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10228 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10300 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10372 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10450 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10532 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10604 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10676 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10748 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10820 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10898 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10980 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11052 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11124 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11196 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11268 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11340 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11412 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11484 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11556 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11628 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12004 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12076 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12148 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12220 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12292 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12364 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12436 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12508 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12586 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12668 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12740 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12812 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12884 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12956 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1940 = ~out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1941 = ~out_wimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1942 = ~out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1943 = ~out_womask_149; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_114 = {hi_84, flags_0_go, _out_prepend_T_114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1944 = out_prepend_114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1945 = _out_T_1944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_115 = _out_T_1945; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_150 = \|_out_rimask_T_150; // @[RegisterRouter.scala:87:24] wire out_wimask_150 = &_out_wimask_T_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_150 = \|_out_romask_T_150; // @[RegisterRouter.scala:87:24] wire out_womask_150 = &_out_womask_T_150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_150 = out_rivalid_1_4 & out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1947 = out_f_rivalid_150; // @[RegisterRouter.scala:87:24] wire out_f_roready_150 = out_roready_1_4 & out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1948 = out_f_roready_150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_150 = out_wivalid_1_4 & out_wimask_150; // @[RegisterRouter.scala:87:24] wire out_f_woready_150 = out_woready_1_4 & out_womask_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2162 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2242 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2322 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2394 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2466 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2538 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2610 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2682 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2754 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2826 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2898 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2978 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3058 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3130 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3202 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3274 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3346 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3418 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3490 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3562 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3634 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3714 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3794 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3866 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3938 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4010 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4082 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4154 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4226 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4298 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4370 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4442 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4514 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4586 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4658 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4730 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4802 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4874 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5180 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5252 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5324 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5396 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5468 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5540 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5612 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5684 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5756 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5828 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5900 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6393 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6465 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6537 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6617 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6697 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6769 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6859 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6931 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7003 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7075 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7147 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7219 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7291 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7363 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7435 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7507 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7579 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7651 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7723 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7795 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7867 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7947 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8027 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8099 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8171 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8243 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8333 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8405 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8477 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8549 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8629 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8925 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8997 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9357 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9429 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9509 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9589 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9661 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9733 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9805 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9877 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9949 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10021 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10093 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10165 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10237 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10309 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10381 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10461 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10541 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10613 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10685 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10757 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10829 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10909 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11061 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11133 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11205 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11277 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11349 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11421 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11493 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11565 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11637 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11933 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12013 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12085 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12157 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12229 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12301 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12373 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12445 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12517 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12597 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12677 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12749 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12821 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12893 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12965 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_1949 = ~out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1950 = ~out_wimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1951 = ~out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1952 = ~out_womask_150; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_115 = {hi_85, flags_0_go, _out_prepend_T_115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1953 = out_prepend_115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1954 = _out_T_1953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_116 = _out_T_1954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_151 = \|_out_rimask_T_151; // @[RegisterRouter.scala:87:24] wire out_wimask_151 = &_out_wimask_T_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_151 = \|_out_romask_T_151; // @[RegisterRouter.scala:87:24] wire out_womask_151 = &_out_womask_T_151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_151 = out_rivalid_1_5 & out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1956 = out_f_rivalid_151; // @[RegisterRouter.scala:87:24] wire out_f_roready_151 = out_roready_1_5 & out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1957 = out_f_roready_151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_151 = out_wivalid_1_5 & out_wimask_151; // @[RegisterRouter.scala:87:24] wire out_f_woready_151 = out_woready_1_5 & out_womask_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2171 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2253 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2331 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2403 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2475 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2547 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2619 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2691 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2763 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2835 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2907 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2989 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3067 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3139 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3211 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3283 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3355 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3427 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3499 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3571 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3643 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3725 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3803 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3875 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3947 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4019 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4091 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4163 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4235 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4307 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4379 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4451 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4523 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4595 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4667 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4739 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4811 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4883 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5189 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5261 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5333 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5405 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5477 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5549 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5621 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5693 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5765 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5837 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5909 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6000 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6402 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6474 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6546 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6628 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6706 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6778 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6868 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6940 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7012 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7084 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7156 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7228 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7300 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7372 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7444 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7516 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7588 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7660 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7732 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7804 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7876 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8036 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8108 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8180 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8252 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8342 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8414 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8486 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8558 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8640 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8934 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9006 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9366 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9438 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9520 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9598 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9670 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9742 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9814 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9886 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10030 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10102 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10174 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10246 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10318 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10390 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10472 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10550 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10622 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10694 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10766 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10838 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10920 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10998 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11070 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11142 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11214 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11286 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11358 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11430 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11502 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11574 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11646 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11944 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12022 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12094 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12166 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12238 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12310 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12382 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12454 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12526 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12608 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12686 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12758 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12830 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12902 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12974 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire _out_T_1958 = ~out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1959 = ~out_wimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1960 = ~out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1961 = ~out_womask_151; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_116 = {hi_86, flags_0_go, _out_prepend_T_116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1962 = out_prepend_116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1963 = _out_T_1962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_117 = _out_T_1963; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_152 = \|_out_rimask_T_152; // @[RegisterRouter.scala:87:24] wire out_wimask_152 = &_out_wimask_T_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_152 = \|_out_romask_T_152; // @[RegisterRouter.scala:87:24] wire out_womask_152 = &_out_womask_T_152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_152 = out_rivalid_1_6 & out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1965 = out_f_rivalid_152; // @[RegisterRouter.scala:87:24] wire out_f_roready_152 = out_roready_1_6 & out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1966 = out_f_roready_152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_152 = out_wivalid_1_6 & out_wimask_152; // @[RegisterRouter.scala:87:24] wire out_f_woready_152 = out_woready_1_6 & out_womask_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2180 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2264 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2340 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2412 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2484 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2556 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2628 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2700 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2772 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2844 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2916 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3000 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3076 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3148 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3220 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3292 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3364 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3436 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3508 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3580 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3652 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3736 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3812 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3884 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3956 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4028 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4100 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4172 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4244 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4316 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4388 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4460 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4532 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4604 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4676 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4748 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4820 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4892 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5198 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5270 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5342 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5414 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5486 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5558 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5630 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5702 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5774 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5846 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5918 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6011 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6411 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6555 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6639 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6715 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6787 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6877 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6949 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7021 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7093 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7165 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7237 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7309 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7381 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7453 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7525 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7597 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7669 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7741 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7813 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7885 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7969 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8045 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8117 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8189 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8261 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8351 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8423 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8495 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8567 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8651 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8943 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9015 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9375 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9447 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9531 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9607 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9679 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9751 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9823 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9895 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9967 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10039 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10111 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10183 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10255 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10327 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10399 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10559 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10631 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10703 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10775 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10847 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10931 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11007 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11079 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11151 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11223 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11295 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11367 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11439 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11511 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11583 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11655 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11955 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12031 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12103 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12175 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12247 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12319 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12391 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12463 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12535 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12619 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12695 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12767 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12839 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12911 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12983 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire _out_T_1967 = ~out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1968 = ~out_wimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1969 = ~out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1970 = ~out_womask_152; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_117 = {hi_87, flags_0_go, _out_prepend_T_117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1971 = out_prepend_117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1972 = _out_T_1971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_118 = _out_T_1972; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_153 = \|_out_rimask_T_153; // @[RegisterRouter.scala:87:24] wire out_wimask_153 = &_out_wimask_T_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_153 = \|_out_romask_T_153; // @[RegisterRouter.scala:87:24] wire out_womask_153 = &_out_womask_T_153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_153 = out_rivalid_1_7 & out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1974 = out_f_rivalid_153; // @[RegisterRouter.scala:87:24] wire out_f_roready_153 = out_roready_1_7 & out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1975 = out_f_roready_153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_153 = out_wivalid_1_7 & out_wimask_153; // @[RegisterRouter.scala:87:24] wire out_f_woready_153 = out_woready_1_7 & out_womask_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2189 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2275 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2349 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2421 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2493 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2565 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2637 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2709 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2781 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2853 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2925 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3011 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3085 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3157 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3229 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3301 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3373 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3445 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3517 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3589 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3661 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3747 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3821 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3893 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3965 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4037 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4109 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4181 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4253 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4325 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4397 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4469 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4541 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4613 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4685 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4757 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4829 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4901 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5207 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5279 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5351 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5423 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5495 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5567 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5639 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5711 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5783 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5855 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5927 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6022 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6420 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6492 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6564 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6650 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6724 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6796 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6886 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6958 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7030 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7102 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7174 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7246 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7318 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7390 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7462 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7534 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7606 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7678 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7750 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7822 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7894 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7980 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8054 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8126 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8198 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8270 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8360 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8432 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8504 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8576 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8662 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8952 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9024 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9384 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9456 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9542 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9616 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9688 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9760 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9832 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9904 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9976 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10048 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10120 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10192 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10264 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10336 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10408 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10494 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10568 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10640 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10712 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10784 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10856 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10942 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11016 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11088 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11160 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11232 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11304 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11376 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11448 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11520 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11592 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11664 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11966 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12040 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12112 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12184 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12256 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12328 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12400 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12472 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12544 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12630 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12704 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12776 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12848 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12920 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12992 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire _out_T_1976 = ~out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1977 = ~out_wimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1978 = ~out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1979 = ~out_womask_153; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_118 = {hi_88, flags_0_go, _out_prepend_T_118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1980 = out_prepend_118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1981 = _out_T_1980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_138 = _out_T_1981; // @[MuxLiteral.scala:49:48] wire out_rimask_154 = \|_out_rimask_T_154; // @[RegisterRouter.scala:87:24] wire out_wimask_154 = &_out_wimask_T_154; // @[RegisterRouter.scala:87:24] wire out_romask_154 = \|_out_romask_T_154; // @[RegisterRouter.scala:87:24] wire out_womask_154 = &_out_womask_T_154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_154 = out_rivalid_1_8 & out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1983 = out_f_rivalid_154; // @[RegisterRouter.scala:87:24] wire out_f_roready_154 = out_roready_1_8 & out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1984 = out_f_roready_154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_154 = out_wivalid_1_8 & out_wimask_154; // @[RegisterRouter.scala:87:24] wire out_f_woready_154 = out_woready_1_8 & out_womask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1985 = ~out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1986 = ~out_wimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1987 = ~out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1988 = ~out_womask_154; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1990 = _out_T_1989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_119 = _out_T_1990; // @[RegisterRouter.scala:87:24] wire out_rimask_155 = \|_out_rimask_T_155; // @[RegisterRouter.scala:87:24] wire out_wimask_155 = &_out_wimask_T_155; // @[RegisterRouter.scala:87:24] wire out_romask_155 = \|_out_romask_T_155; // @[RegisterRouter.scala:87:24] wire out_womask_155 = &_out_womask_T_155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_155 = out_rivalid_1_9 & out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1992 = out_f_rivalid_155; // @[RegisterRouter.scala:87:24] wire out_f_roready_155 = out_roready_1_9 & out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1993 = out_f_roready_155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_155 = out_wivalid_1_9 & out_wimask_155; // @[RegisterRouter.scala:87:24] wire out_f_woready_155 = out_woready_1_9 & out_womask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1994 = ~out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1995 = ~out_wimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1996 = ~out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1997 = ~out_womask_155; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_119 = {hi_970, flags_0_go, _out_prepend_T_119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1998 = out_prepend_119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1999 = _out_T_1998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_120 = _out_T_1999; // @[RegisterRouter.scala:87:24] wire out_rimask_156 = \|_out_rimask_T_156; // @[RegisterRouter.scala:87:24] wire out_wimask_156 = &_out_wimask_T_156; // @[RegisterRouter.scala:87:24] wire out_romask_156 = \|_out_romask_T_156; // @[RegisterRouter.scala:87:24] wire out_womask_156 = &_out_womask_T_156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_156 = out_rivalid_1_10 & out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2001 = out_f_rivalid_156; // @[RegisterRouter.scala:87:24] wire out_f_roready_156 = out_roready_1_10 & out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2002 = out_f_roready_156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_156 = out_wivalid_1_10 & out_wimask_156; // @[RegisterRouter.scala:87:24] wire out_f_woready_156 = out_woready_1_10 & out_womask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2003 = ~out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2004 = ~out_wimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2005 = ~out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2006 = ~out_womask_156; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_120 = {hi_971, flags_0_go, _out_prepend_T_120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2007 = out_prepend_120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2008 = _out_T_2007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_121 = _out_T_2008; // @[RegisterRouter.scala:87:24] wire out_rimask_157 = \|_out_rimask_T_157; // @[RegisterRouter.scala:87:24] wire out_wimask_157 = &_out_wimask_T_157; // @[RegisterRouter.scala:87:24] wire out_romask_157 = \|_out_romask_T_157; // @[RegisterRouter.scala:87:24] wire out_womask_157 = &_out_womask_T_157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_157 = out_rivalid_1_11 & out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2010 = out_f_rivalid_157; // @[RegisterRouter.scala:87:24] wire out_f_roready_157 = out_roready_1_11 & out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2011 = out_f_roready_157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_157 = out_wivalid_1_11 & out_wimask_157; // @[RegisterRouter.scala:87:24] wire out_f_woready_157 = out_woready_1_11 & out_womask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2012 = ~out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2013 = ~out_wimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2014 = ~out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2015 = ~out_womask_157; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_121 = {hi_972, flags_0_go, _out_prepend_T_121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2016 = out_prepend_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2017 = _out_T_2016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_122 = _out_T_2017; // @[RegisterRouter.scala:87:24] wire out_rimask_158 = \|_out_rimask_T_158; // @[RegisterRouter.scala:87:24] wire out_wimask_158 = &_out_wimask_T_158; // @[RegisterRouter.scala:87:24] wire out_romask_158 = \|_out_romask_T_158; // @[RegisterRouter.scala:87:24] wire out_womask_158 = &_out_womask_T_158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_158 = out_rivalid_1_12 & out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2019 = out_f_rivalid_158; // @[RegisterRouter.scala:87:24] wire out_f_roready_158 = out_roready_1_12 & out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2020 = out_f_roready_158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_158 = out_wivalid_1_12 & out_wimask_158; // @[RegisterRouter.scala:87:24] wire out_f_woready_158 = out_woready_1_12 & out_womask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2021 = ~out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2022 = ~out_wimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2023 = ~out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2024 = ~out_womask_158; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_122 = {hi_973, flags_0_go, _out_prepend_T_122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2025 = out_prepend_122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2026 = _out_T_2025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_123 = _out_T_2026; // @[RegisterRouter.scala:87:24] wire out_rimask_159 = \|_out_rimask_T_159; // @[RegisterRouter.scala:87:24] wire out_wimask_159 = &_out_wimask_T_159; // @[RegisterRouter.scala:87:24] wire out_romask_159 = \|_out_romask_T_159; // @[RegisterRouter.scala:87:24] wire out_womask_159 = &_out_womask_T_159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_159 = out_rivalid_1_13 & out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2028 = out_f_rivalid_159; // @[RegisterRouter.scala:87:24] wire out_f_roready_159 = out_roready_1_13 & out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2029 = out_f_roready_159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_159 = out_wivalid_1_13 & out_wimask_159; // @[RegisterRouter.scala:87:24] wire out_f_woready_159 = out_woready_1_13 & out_womask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2030 = ~out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2031 = ~out_wimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2032 = ~out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2033 = ~out_womask_159; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_123 = {hi_974, flags_0_go, _out_prepend_T_123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2034 = out_prepend_123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2035 = _out_T_2034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_124 = _out_T_2035; // @[RegisterRouter.scala:87:24] wire out_rimask_160 = \|_out_rimask_T_160; // @[RegisterRouter.scala:87:24] wire out_wimask_160 = &_out_wimask_T_160; // @[RegisterRouter.scala:87:24] wire out_romask_160 = \|_out_romask_T_160; // @[RegisterRouter.scala:87:24] wire out_womask_160 = &_out_womask_T_160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_160 = out_rivalid_1_14 & out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2037 = out_f_rivalid_160; // @[RegisterRouter.scala:87:24] wire out_f_roready_160 = out_roready_1_14 & out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2038 = out_f_roready_160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_160 = out_wivalid_1_14 & out_wimask_160; // @[RegisterRouter.scala:87:24] wire out_f_woready_160 = out_woready_1_14 & out_womask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2039 = ~out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2040 = ~out_wimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2041 = ~out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2042 = ~out_womask_160; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_124 = {hi_975, flags_0_go, _out_prepend_T_124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2043 = out_prepend_124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2044 = _out_T_2043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_125 = _out_T_2044; // @[RegisterRouter.scala:87:24] wire out_rimask_161 = \|_out_rimask_T_161; // @[RegisterRouter.scala:87:24] wire out_wimask_161 = &_out_wimask_T_161; // @[RegisterRouter.scala:87:24] wire out_romask_161 = \|_out_romask_T_161; // @[RegisterRouter.scala:87:24] wire out_womask_161 = &_out_womask_T_161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_161 = out_rivalid_1_15 & out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2046 = out_f_rivalid_161; // @[RegisterRouter.scala:87:24] wire out_f_roready_161 = out_roready_1_15 & out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2047 = out_f_roready_161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_161 = out_wivalid_1_15 & out_wimask_161; // @[RegisterRouter.scala:87:24] wire out_f_woready_161 = out_woready_1_15 & out_womask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2048 = ~out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2049 = ~out_wimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2050 = ~out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2051 = ~out_womask_161; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_125 = {hi_976, flags_0_go, _out_prepend_T_125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2052 = out_prepend_125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2053 = _out_T_2052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_249 = _out_T_2053; // @[MuxLiteral.scala:49:48] wire out_rimask_162 = \|_out_rimask_T_162; // @[RegisterRouter.scala:87:24] wire out_wimask_162 = &_out_wimask_T_162; // @[RegisterRouter.scala:87:24] wire out_romask_162 = \|_out_romask_T_162; // @[RegisterRouter.scala:87:24] wire out_womask_162 = &_out_womask_T_162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_162 = out_rivalid_1_16 & out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2055 = out_f_rivalid_162; // @[RegisterRouter.scala:87:24] wire out_f_roready_162 = out_roready_1_16 & out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2056 = out_f_roready_162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_162 = out_wivalid_1_16 & out_wimask_162; // @[RegisterRouter.scala:87:24] wire out_f_woready_162 = out_woready_1_16 & out_womask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2057 = ~out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2058 = ~out_wimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2059 = ~out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2060 = ~out_womask_162; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2062 = _out_T_2061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_126 = _out_T_2062; // @[RegisterRouter.scala:87:24] wire out_rimask_163 = \|_out_rimask_T_163; // @[RegisterRouter.scala:87:24] wire out_wimask_163 = &_out_wimask_T_163; // @[RegisterRouter.scala:87:24] wire out_romask_163 = \|_out_romask_T_163; // @[RegisterRouter.scala:87:24] wire out_womask_163 = &_out_womask_T_163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_163 = out_rivalid_1_17 & out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2064 = out_f_rivalid_163; // @[RegisterRouter.scala:87:24] wire out_f_roready_163 = out_roready_1_17 & out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2065 = out_f_roready_163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_163 = out_wivalid_1_17 & out_wimask_163; // @[RegisterRouter.scala:87:24] wire out_f_woready_163 = out_woready_1_17 & out_womask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2066 = ~out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2067 = ~out_wimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2068 = ~out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2069 = ~out_womask_163; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_126 = {hi_850, flags_0_go, _out_prepend_T_126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2070 = out_prepend_126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2071 = _out_T_2070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_127 = _out_T_2071; // @[RegisterRouter.scala:87:24] wire out_rimask_164 = \|_out_rimask_T_164; // @[RegisterRouter.scala:87:24] wire out_wimask_164 = &_out_wimask_T_164; // @[RegisterRouter.scala:87:24] wire out_romask_164 = \|_out_romask_T_164; // @[RegisterRouter.scala:87:24] wire out_womask_164 = &_out_womask_T_164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_164 = out_rivalid_1_18 & out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2073 = out_f_rivalid_164; // @[RegisterRouter.scala:87:24] wire out_f_roready_164 = out_roready_1_18 & out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2074 = out_f_roready_164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_164 = out_wivalid_1_18 & out_wimask_164; // @[RegisterRouter.scala:87:24] wire out_f_woready_164 = out_woready_1_18 & out_womask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2075 = ~out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2076 = ~out_wimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2077 = ~out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2078 = ~out_womask_164; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_127 = {hi_851, flags_0_go, _out_prepend_T_127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2079 = out_prepend_127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2080 = _out_T_2079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_128 = _out_T_2080; // @[RegisterRouter.scala:87:24] wire out_rimask_165 = \|_out_rimask_T_165; // @[RegisterRouter.scala:87:24] wire out_wimask_165 = &_out_wimask_T_165; // @[RegisterRouter.scala:87:24] wire out_romask_165 = \|_out_romask_T_165; // @[RegisterRouter.scala:87:24] wire out_womask_165 = &_out_womask_T_165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_165 = out_rivalid_1_19 & out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2082 = out_f_rivalid_165; // @[RegisterRouter.scala:87:24] wire out_f_roready_165 = out_roready_1_19 & out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2083 = out_f_roready_165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_165 = out_wivalid_1_19 & out_wimask_165; // @[RegisterRouter.scala:87:24] wire out_f_woready_165 = out_woready_1_19 & out_womask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2084 = ~out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2085 = ~out_wimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2086 = ~out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2087 = ~out_womask_165; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_128 = {hi_852, flags_0_go, _out_prepend_T_128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2088 = out_prepend_128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2089 = _out_T_2088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_129 = _out_T_2089; // @[RegisterRouter.scala:87:24] wire out_rimask_166 = \|_out_rimask_T_166; // @[RegisterRouter.scala:87:24] wire out_wimask_166 = &_out_wimask_T_166; // @[RegisterRouter.scala:87:24] wire out_romask_166 = \|_out_romask_T_166; // @[RegisterRouter.scala:87:24] wire out_womask_166 = &_out_womask_T_166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_166 = out_rivalid_1_20 & out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2091 = out_f_rivalid_166; // @[RegisterRouter.scala:87:24] wire out_f_roready_166 = out_roready_1_20 & out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2092 = out_f_roready_166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_166 = out_wivalid_1_20 & out_wimask_166; // @[RegisterRouter.scala:87:24] wire out_f_woready_166 = out_woready_1_20 & out_womask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2093 = ~out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2094 = ~out_wimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2095 = ~out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2096 = ~out_womask_166; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_129 = {hi_853, flags_0_go, _out_prepend_T_129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2097 = out_prepend_129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2098 = _out_T_2097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_130 = _out_T_2098; // @[RegisterRouter.scala:87:24] wire out_rimask_167 = \|_out_rimask_T_167; // @[RegisterRouter.scala:87:24] wire out_wimask_167 = &_out_wimask_T_167; // @[RegisterRouter.scala:87:24] wire out_romask_167 = \|_out_romask_T_167; // @[RegisterRouter.scala:87:24] wire out_womask_167 = &_out_womask_T_167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_167 = out_rivalid_1_21 & out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2100 = out_f_rivalid_167; // @[RegisterRouter.scala:87:24] wire out_f_roready_167 = out_roready_1_21 & out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2101 = out_f_roready_167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_167 = out_wivalid_1_21 & out_wimask_167; // @[RegisterRouter.scala:87:24] wire out_f_woready_167 = out_woready_1_21 & out_womask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2102 = ~out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2103 = ~out_wimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2104 = ~out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2105 = ~out_womask_167; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_130 = {hi_854, flags_0_go, _out_prepend_T_130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2106 = out_prepend_130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2107 = _out_T_2106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_131 = _out_T_2107; // @[RegisterRouter.scala:87:24] wire out_rimask_168 = \|_out_rimask_T_168; // @[RegisterRouter.scala:87:24] wire out_wimask_168 = &_out_wimask_T_168; // @[RegisterRouter.scala:87:24] wire out_romask_168 = \|_out_romask_T_168; // @[RegisterRouter.scala:87:24] wire out_womask_168 = &_out_womask_T_168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_168 = out_rivalid_1_22 & out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2109 = out_f_rivalid_168; // @[RegisterRouter.scala:87:24] wire out_f_roready_168 = out_roready_1_22 & out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2110 = out_f_roready_168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_168 = out_wivalid_1_22 & out_wimask_168; // @[RegisterRouter.scala:87:24] wire out_f_woready_168 = out_woready_1_22 & out_womask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2111 = ~out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2112 = ~out_wimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2113 = ~out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2114 = ~out_womask_168; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_131 = {hi_855, flags_0_go, _out_prepend_T_131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2115 = out_prepend_131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2116 = _out_T_2115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_132 = _out_T_2116; // @[RegisterRouter.scala:87:24] wire out_rimask_169 = \|_out_rimask_T_169; // @[RegisterRouter.scala:87:24] wire out_wimask_169 = &_out_wimask_T_169; // @[RegisterRouter.scala:87:24] wire out_romask_169 = \|_out_romask_T_169; // @[RegisterRouter.scala:87:24] wire out_womask_169 = &_out_womask_T_169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_169 = out_rivalid_1_23 & out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2118 = out_f_rivalid_169; // @[RegisterRouter.scala:87:24] wire out_f_roready_169 = out_roready_1_23 & out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2119 = out_f_roready_169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_169 = out_wivalid_1_23 & out_wimask_169; // @[RegisterRouter.scala:87:24] wire out_f_woready_169 = out_woready_1_23 & out_womask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2120 = ~out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2121 = ~out_wimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2122 = ~out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2123 = ~out_womask_169; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_132 = {hi_856, flags_0_go, _out_prepend_T_132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2124 = out_prepend_132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2125 = _out_T_2124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_234 = _out_T_2125; // @[MuxLiteral.scala:49:48] wire out_rimask_170 = \|_out_rimask_T_170; // @[RegisterRouter.scala:87:24] wire out_wimask_170 = &_out_wimask_T_170; // @[RegisterRouter.scala:87:24] wire out_romask_170 = \|_out_romask_T_170; // @[RegisterRouter.scala:87:24] wire out_womask_170 = &_out_womask_T_170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_170 = out_rivalid_1_24 & out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2127 = out_f_rivalid_170; // @[RegisterRouter.scala:87:24] wire out_f_roready_170 = out_roready_1_24 & out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2128 = out_f_roready_170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_170 = out_wivalid_1_24 & out_wimask_170; // @[RegisterRouter.scala:87:24] wire out_f_woready_170 = out_woready_1_24 & out_womask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2129 = ~out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2130 = ~out_wimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2131 = ~out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2132 = ~out_womask_170; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2134 = _out_T_2133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_133 = _out_T_2134; // @[RegisterRouter.scala:87:24] wire out_rimask_171 = \|_out_rimask_T_171; // @[RegisterRouter.scala:87:24] wire out_wimask_171 = &_out_wimask_T_171; // @[RegisterRouter.scala:87:24] wire out_romask_171 = \|_out_romask_T_171; // @[RegisterRouter.scala:87:24] wire out_womask_171 = &_out_womask_T_171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_171 = out_rivalid_1_25 & out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2136 = out_f_rivalid_171; // @[RegisterRouter.scala:87:24] wire out_f_roready_171 = out_roready_1_25 & out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2137 = out_f_roready_171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_171 = out_wivalid_1_25 & out_wimask_171; // @[RegisterRouter.scala:87:24] wire out_f_woready_171 = out_woready_1_25 & out_womask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2138 = ~out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2139 = ~out_wimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2140 = ~out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2141 = ~out_womask_171; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_133 = {hi_338, flags_0_go, _out_prepend_T_133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2142 = out_prepend_133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2143 = _out_T_2142; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_134 = _out_T_2143; // @[RegisterRouter.scala:87:24] wire out_rimask_172 = \|_out_rimask_T_172; // @[RegisterRouter.scala:87:24] wire out_wimask_172 = &_out_wimask_T_172; // @[RegisterRouter.scala:87:24] wire out_romask_172 = \|_out_romask_T_172; // @[RegisterRouter.scala:87:24] wire out_womask_172 = &_out_womask_T_172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_172 = out_rivalid_1_26 & out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2145 = out_f_rivalid_172; // @[RegisterRouter.scala:87:24] wire out_f_roready_172 = out_roready_1_26 & out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2146 = out_f_roready_172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_172 = out_wivalid_1_26 & out_wimask_172; // @[RegisterRouter.scala:87:24] wire out_f_woready_172 = out_woready_1_26 & out_womask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2147 = ~out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2148 = ~out_wimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2149 = ~out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2150 = ~out_womask_172; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_134 = {hi_339, flags_0_go, _out_prepend_T_134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2151 = out_prepend_134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2152 = _out_T_2151; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_135 = _out_T_2152; // @[RegisterRouter.scala:87:24] wire out_rimask_173 = \|_out_rimask_T_173; // @[RegisterRouter.scala:87:24] wire out_wimask_173 = &_out_wimask_T_173; // @[RegisterRouter.scala:87:24] wire out_romask_173 = \|_out_romask_T_173; // @[RegisterRouter.scala:87:24] wire out_womask_173 = &_out_womask_T_173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_173 = out_rivalid_1_27 & out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2154 = out_f_rivalid_173; // @[RegisterRouter.scala:87:24] wire out_f_roready_173 = out_roready_1_27 & out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2155 = out_f_roready_173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_173 = out_wivalid_1_27 & out_wimask_173; // @[RegisterRouter.scala:87:24] wire out_f_woready_173 = out_woready_1_27 & out_womask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2156 = ~out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2157 = ~out_wimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2158 = ~out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2159 = ~out_womask_173; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_135 = {hi_340, flags_0_go, _out_prepend_T_135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2160 = out_prepend_135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2161 = _out_T_2160; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_136 = _out_T_2161; // @[RegisterRouter.scala:87:24] wire out_rimask_174 = \|_out_rimask_T_174; // @[RegisterRouter.scala:87:24] wire out_wimask_174 = &_out_wimask_T_174; // @[RegisterRouter.scala:87:24] wire out_romask_174 = \|_out_romask_T_174; // @[RegisterRouter.scala:87:24] wire out_womask_174 = &_out_womask_T_174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_174 = out_rivalid_1_28 & out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2163 = out_f_rivalid_174; // @[RegisterRouter.scala:87:24] wire out_f_roready_174 = out_roready_1_28 & out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2164 = out_f_roready_174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_174 = out_wivalid_1_28 & out_wimask_174; // @[RegisterRouter.scala:87:24] wire out_f_woready_174 = out_woready_1_28 & out_womask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2165 = ~out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2166 = ~out_wimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2167 = ~out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2168 = ~out_womask_174; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_136 = {hi_341, flags_0_go, _out_prepend_T_136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2169 = out_prepend_136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2170 = _out_T_2169; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_137 = _out_T_2170; // @[RegisterRouter.scala:87:24] wire out_rimask_175 = \|_out_rimask_T_175; // @[RegisterRouter.scala:87:24] wire out_wimask_175 = &_out_wimask_T_175; // @[RegisterRouter.scala:87:24] wire out_romask_175 = \|_out_romask_T_175; // @[RegisterRouter.scala:87:24] wire out_womask_175 = &_out_womask_T_175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_175 = out_rivalid_1_29 & out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2172 = out_f_rivalid_175; // @[RegisterRouter.scala:87:24] wire out_f_roready_175 = out_roready_1_29 & out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2173 = out_f_roready_175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_175 = out_wivalid_1_29 & out_wimask_175; // @[RegisterRouter.scala:87:24] wire out_f_woready_175 = out_woready_1_29 & out_womask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2174 = ~out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2175 = ~out_wimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2176 = ~out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2177 = ~out_womask_175; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_137 = {hi_342, flags_0_go, _out_prepend_T_137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2178 = out_prepend_137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2179 = _out_T_2178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_138 = _out_T_2179; // @[RegisterRouter.scala:87:24] wire out_rimask_176 = \|_out_rimask_T_176; // @[RegisterRouter.scala:87:24] wire out_wimask_176 = &_out_wimask_T_176; // @[RegisterRouter.scala:87:24] wire out_romask_176 = \|_out_romask_T_176; // @[RegisterRouter.scala:87:24] wire out_womask_176 = &_out_womask_T_176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_176 = out_rivalid_1_30 & out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2181 = out_f_rivalid_176; // @[RegisterRouter.scala:87:24] wire out_f_roready_176 = out_roready_1_30 & out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2182 = out_f_roready_176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_176 = out_wivalid_1_30 & out_wimask_176; // @[RegisterRouter.scala:87:24] wire out_f_woready_176 = out_woready_1_30 & out_womask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2183 = ~out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2184 = ~out_wimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2185 = ~out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2186 = ~out_womask_176; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_138 = {hi_343, flags_0_go, _out_prepend_T_138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2187 = out_prepend_138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2188 = _out_T_2187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_139 = _out_T_2188; // @[RegisterRouter.scala:87:24] wire out_rimask_177 = \|_out_rimask_T_177; // @[RegisterRouter.scala:87:24] wire out_wimask_177 = &_out_wimask_T_177; // @[RegisterRouter.scala:87:24] wire out_romask_177 = \|_out_romask_T_177; // @[RegisterRouter.scala:87:24] wire out_womask_177 = &_out_womask_T_177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_177 = out_rivalid_1_31 & out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2190 = out_f_rivalid_177; // @[RegisterRouter.scala:87:24] wire out_f_roready_177 = out_roready_1_31 & out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2191 = out_f_roready_177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_177 = out_wivalid_1_31 & out_wimask_177; // @[RegisterRouter.scala:87:24] wire out_f_woready_177 = out_woready_1_31 & out_womask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2192 = ~out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2193 = ~out_wimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2194 = ~out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2195 = ~out_womask_177; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_139 = {hi_344, flags_0_go, _out_prepend_T_139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2196 = out_prepend_139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2197 = _out_T_2196; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_170 = _out_T_2197; // @[MuxLiteral.scala:49:48] wire out_rimask_178 = \|_out_rimask_T_178; // @[RegisterRouter.scala:87:24] wire out_wimask_178 = &_out_wimask_T_178; // @[RegisterRouter.scala:87:24] wire out_romask_178 = \|_out_romask_T_178; // @[RegisterRouter.scala:87:24] wire out_womask_178 = &_out_womask_T_178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_178 = out_rivalid_1_32 & out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2199 = out_f_rivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_roready_178 = out_roready_1_32 & out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2200 = out_f_roready_178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_178 = out_wivalid_1_32 & out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2201 = out_f_wivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_woready_178 = out_woready_1_32 & out_womask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2202 = out_f_woready_178; // @[RegisterRouter.scala:87:24] wire _out_T_2203 = ~out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2204 = ~out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2205 = ~out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2206 = ~out_womask_178; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2208 = _out_T_2207; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_140 = _out_T_2208; // @[RegisterRouter.scala:87:24] wire out_rimask_179 = \|_out_rimask_T_179; // @[RegisterRouter.scala:87:24] wire out_wimask_179 = &_out_wimask_T_179; // @[RegisterRouter.scala:87:24] wire out_romask_179 = \|_out_romask_T_179; // @[RegisterRouter.scala:87:24] wire out_womask_179 = &_out_womask_T_179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_179 = out_rivalid_1_33 & out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2210 = out_f_rivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_roready_179 = out_roready_1_33 & out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2211 = out_f_roready_179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_179 = out_wivalid_1_33 & out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2212 = out_f_wivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_woready_179 = out_woready_1_33 & out_womask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2213 = out_f_woready_179; // @[RegisterRouter.scala:87:24] wire _out_T_2214 = ~out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2215 = ~out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2216 = ~out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2217 = ~out_womask_179; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_140 = {abstractDataMem_25, _out_prepend_T_140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2218 = out_prepend_140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2219 = _out_T_2218; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_141 = _out_T_2219; // @[RegisterRouter.scala:87:24] wire out_rimask_180 = \|_out_rimask_T_180; // @[RegisterRouter.scala:87:24] wire out_wimask_180 = &_out_wimask_T_180; // @[RegisterRouter.scala:87:24] wire out_romask_180 = \|_out_romask_T_180; // @[RegisterRouter.scala:87:24] wire out_womask_180 = &_out_womask_T_180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_180 = out_rivalid_1_34 & out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2221 = out_f_rivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_roready_180 = out_roready_1_34 & out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2222 = out_f_roready_180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_180 = out_wivalid_1_34 & out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2223 = out_f_wivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_woready_180 = out_woready_1_34 & out_womask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2224 = out_f_woready_180; // @[RegisterRouter.scala:87:24] wire _out_T_2225 = ~out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2226 = ~out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2227 = ~out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2228 = ~out_womask_180; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_141 = {abstractDataMem_26, _out_prepend_T_141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2229 = out_prepend_141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2230 = _out_T_2229; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_142 = _out_T_2230; // @[RegisterRouter.scala:87:24] wire out_rimask_181 = \|_out_rimask_T_181; // @[RegisterRouter.scala:87:24] wire out_wimask_181 = &_out_wimask_T_181; // @[RegisterRouter.scala:87:24] wire out_romask_181 = \|_out_romask_T_181; // @[RegisterRouter.scala:87:24] wire out_womask_181 = &_out_womask_T_181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_181 = out_rivalid_1_35 & out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2232 = out_f_rivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_roready_181 = out_roready_1_35 & out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2233 = out_f_roready_181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_181 = out_wivalid_1_35 & out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2234 = out_f_wivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_woready_181 = out_woready_1_35 & out_womask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2235 = out_f_woready_181; // @[RegisterRouter.scala:87:24] wire _out_T_2236 = ~out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2237 = ~out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2238 = ~out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2239 = ~out_womask_181; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_142 = {abstractDataMem_27, _out_prepend_T_142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2240 = out_prepend_142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2241 = _out_T_2240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_143 = _out_T_2241; // @[RegisterRouter.scala:87:24] wire out_rimask_182 = \|_out_rimask_T_182; // @[RegisterRouter.scala:87:24] wire out_wimask_182 = &_out_wimask_T_182; // @[RegisterRouter.scala:87:24] wire out_romask_182 = \|_out_romask_T_182; // @[RegisterRouter.scala:87:24] wire out_womask_182 = &_out_womask_T_182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_182 = out_rivalid_1_36 & out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2243 = out_f_rivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_roready_182 = out_roready_1_36 & out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2244 = out_f_roready_182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_182 = out_wivalid_1_36 & out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2245 = out_f_wivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_woready_182 = out_woready_1_36 & out_womask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2246 = out_f_woready_182; // @[RegisterRouter.scala:87:24] wire _out_T_2247 = ~out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2248 = ~out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2249 = ~out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2250 = ~out_womask_182; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_143 = {abstractDataMem_28, _out_prepend_T_143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2251 = out_prepend_143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2252 = _out_T_2251; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_144 = _out_T_2252; // @[RegisterRouter.scala:87:24] wire out_rimask_183 = \|_out_rimask_T_183; // @[RegisterRouter.scala:87:24] wire out_wimask_183 = &_out_wimask_T_183; // @[RegisterRouter.scala:87:24] wire out_romask_183 = \|_out_romask_T_183; // @[RegisterRouter.scala:87:24] wire out_womask_183 = &_out_womask_T_183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_183 = out_rivalid_1_37 & out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2254 = out_f_rivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_roready_183 = out_roready_1_37 & out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2255 = out_f_roready_183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_183 = out_wivalid_1_37 & out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2256 = out_f_wivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_woready_183 = out_woready_1_37 & out_womask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2257 = out_f_woready_183; // @[RegisterRouter.scala:87:24] wire _out_T_2258 = ~out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2259 = ~out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2260 = ~out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2261 = ~out_womask_183; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_144 = {abstractDataMem_29, _out_prepend_T_144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2262 = out_prepend_144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2263 = _out_T_2262; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_145 = _out_T_2263; // @[RegisterRouter.scala:87:24] wire out_rimask_184 = \|_out_rimask_T_184; // @[RegisterRouter.scala:87:24] wire out_wimask_184 = &_out_wimask_T_184; // @[RegisterRouter.scala:87:24] wire out_romask_184 = \|_out_romask_T_184; // @[RegisterRouter.scala:87:24] wire out_womask_184 = &_out_womask_T_184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_184 = out_rivalid_1_38 & out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2265 = out_f_rivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_roready_184 = out_roready_1_38 & out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2266 = out_f_roready_184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_184 = out_wivalid_1_38 & out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2267 = out_f_wivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_woready_184 = out_woready_1_38 & out_womask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2268 = out_f_woready_184; // @[RegisterRouter.scala:87:24] wire _out_T_2269 = ~out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2270 = ~out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2271 = ~out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2272 = ~out_womask_184; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_145 = {abstractDataMem_30, _out_prepend_T_145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2273 = out_prepend_145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2274 = _out_T_2273; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_146 = _out_T_2274; // @[RegisterRouter.scala:87:24] wire out_rimask_185 = \|_out_rimask_T_185; // @[RegisterRouter.scala:87:24] wire out_wimask_185 = &_out_wimask_T_185; // @[RegisterRouter.scala:87:24] wire out_romask_185 = \|_out_romask_T_185; // @[RegisterRouter.scala:87:24] wire out_womask_185 = &_out_womask_T_185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_185 = out_rivalid_1_39 & out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2276 = out_f_rivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_roready_185 = out_roready_1_39 & out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2277 = out_f_roready_185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_185 = out_wivalid_1_39 & out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2278 = out_f_wivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_woready_185 = out_woready_1_39 & out_womask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2279 = out_f_woready_185; // @[RegisterRouter.scala:87:24] wire _out_T_2280 = ~out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2281 = ~out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2282 = ~out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2283 = ~out_womask_185; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_146 = {abstractDataMem_31, _out_prepend_T_146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2284 = out_prepend_146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2285 = _out_T_2284; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_115 = _out_T_2285; // @[MuxLiteral.scala:49:48] wire out_rimask_186 = \|_out_rimask_T_186; // @[RegisterRouter.scala:87:24] wire out_wimask_186 = &_out_wimask_T_186; // @[RegisterRouter.scala:87:24] wire out_romask_186 = \|_out_romask_T_186; // @[RegisterRouter.scala:87:24] wire out_womask_186 = &_out_womask_T_186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_186 = out_rivalid_1_40 & out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2287 = out_f_rivalid_186; // @[RegisterRouter.scala:87:24] wire out_f_roready_186 = out_roready_1_40 & out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2288 = out_f_roready_186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_186 = out_wivalid_1_40 & out_wimask_186; // @[RegisterRouter.scala:87:24] wire out_f_woready_186 = out_woready_1_40 & out_womask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2289 = ~out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2290 = ~out_wimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2291 = ~out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2292 = ~out_womask_186; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2294 = _out_T_2293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_147 = _out_T_2294; // @[RegisterRouter.scala:87:24] wire out_rimask_187 = \|_out_rimask_T_187; // @[RegisterRouter.scala:87:24] wire out_wimask_187 = &_out_wimask_T_187; // @[RegisterRouter.scala:87:24] wire out_romask_187 = \|_out_romask_T_187; // @[RegisterRouter.scala:87:24] wire out_womask_187 = &_out_womask_T_187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_187 = out_rivalid_1_41 & out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2296 = out_f_rivalid_187; // @[RegisterRouter.scala:87:24] wire out_f_roready_187 = out_roready_1_41 & out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2297 = out_f_roready_187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_187 = out_wivalid_1_41 & out_wimask_187; // @[RegisterRouter.scala:87:24] wire out_f_woready_187 = out_woready_1_41 & out_womask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2298 = ~out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2299 = ~out_wimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2300 = ~out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2301 = ~out_womask_187; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_147 = {hi_714, flags_0_go, _out_prepend_T_147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2302 = out_prepend_147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2303 = _out_T_2302; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_148 = _out_T_2303; // @[RegisterRouter.scala:87:24] wire out_rimask_188 = \|_out_rimask_T_188; // @[RegisterRouter.scala:87:24] wire out_wimask_188 = &_out_wimask_T_188; // @[RegisterRouter.scala:87:24] wire out_romask_188 = \|_out_romask_T_188; // @[RegisterRouter.scala:87:24] wire out_womask_188 = &_out_womask_T_188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_188 = out_rivalid_1_42 & out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2305 = out_f_rivalid_188; // @[RegisterRouter.scala:87:24] wire out_f_roready_188 = out_roready_1_42 & out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2306 = out_f_roready_188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_188 = out_wivalid_1_42 & out_wimask_188; // @[RegisterRouter.scala:87:24] wire out_f_woready_188 = out_woready_1_42 & out_womask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2307 = ~out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2308 = ~out_wimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2309 = ~out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2310 = ~out_womask_188; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_148 = {hi_715, flags_0_go, _out_prepend_T_148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2311 = out_prepend_148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2312 = _out_T_2311; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_149 = _out_T_2312; // @[RegisterRouter.scala:87:24] wire out_rimask_189 = \|_out_rimask_T_189; // @[RegisterRouter.scala:87:24] wire out_wimask_189 = &_out_wimask_T_189; // @[RegisterRouter.scala:87:24] wire out_romask_189 = \|_out_romask_T_189; // @[RegisterRouter.scala:87:24] wire out_womask_189 = &_out_womask_T_189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_189 = out_rivalid_1_43 & out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2314 = out_f_rivalid_189; // @[RegisterRouter.scala:87:24] wire out_f_roready_189 = out_roready_1_43 & out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2315 = out_f_roready_189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_189 = out_wivalid_1_43 & out_wimask_189; // @[RegisterRouter.scala:87:24] wire out_f_woready_189 = out_woready_1_43 & out_womask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2316 = ~out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2317 = ~out_wimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2318 = ~out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2319 = ~out_womask_189; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_149 = {hi_716, flags_0_go, _out_prepend_T_149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2320 = out_prepend_149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2321 = _out_T_2320; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_150 = _out_T_2321; // @[RegisterRouter.scala:87:24] wire out_rimask_190 = \|_out_rimask_T_190; // @[RegisterRouter.scala:87:24] wire out_wimask_190 = &_out_wimask_T_190; // @[RegisterRouter.scala:87:24] wire out_romask_190 = \|_out_romask_T_190; // @[RegisterRouter.scala:87:24] wire out_womask_190 = &_out_womask_T_190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_190 = out_rivalid_1_44 & out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2323 = out_f_rivalid_190; // @[RegisterRouter.scala:87:24] wire out_f_roready_190 = out_roready_1_44 & out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2324 = out_f_roready_190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_190 = out_wivalid_1_44 & out_wimask_190; // @[RegisterRouter.scala:87:24] wire out_f_woready_190 = out_woready_1_44 & out_womask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2325 = ~out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2326 = ~out_wimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2327 = ~out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2328 = ~out_womask_190; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_150 = {hi_717, flags_0_go, _out_prepend_T_150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2329 = out_prepend_150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2330 = _out_T_2329; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_151 = _out_T_2330; // @[RegisterRouter.scala:87:24] wire out_rimask_191 = \|_out_rimask_T_191; // @[RegisterRouter.scala:87:24] wire out_wimask_191 = &_out_wimask_T_191; // @[RegisterRouter.scala:87:24] wire out_romask_191 = \|_out_romask_T_191; // @[RegisterRouter.scala:87:24] wire out_womask_191 = &_out_womask_T_191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_191 = out_rivalid_1_45 & out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2332 = out_f_rivalid_191; // @[RegisterRouter.scala:87:24] wire out_f_roready_191 = out_roready_1_45 & out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2333 = out_f_roready_191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_191 = out_wivalid_1_45 & out_wimask_191; // @[RegisterRouter.scala:87:24] wire out_f_woready_191 = out_woready_1_45 & out_womask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2334 = ~out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2335 = ~out_wimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2336 = ~out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2337 = ~out_womask_191; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_151 = {hi_718, flags_0_go, _out_prepend_T_151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2338 = out_prepend_151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2339 = _out_T_2338; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_152 = _out_T_2339; // @[RegisterRouter.scala:87:24] wire out_rimask_192 = \|_out_rimask_T_192; // @[RegisterRouter.scala:87:24] wire out_wimask_192 = &_out_wimask_T_192; // @[RegisterRouter.scala:87:24] wire out_romask_192 = \|_out_romask_T_192; // @[RegisterRouter.scala:87:24] wire out_womask_192 = &_out_womask_T_192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_192 = out_rivalid_1_46 & out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2341 = out_f_rivalid_192; // @[RegisterRouter.scala:87:24] wire out_f_roready_192 = out_roready_1_46 & out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2342 = out_f_roready_192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_192 = out_wivalid_1_46 & out_wimask_192; // @[RegisterRouter.scala:87:24] wire out_f_woready_192 = out_woready_1_46 & out_womask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2343 = ~out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2344 = ~out_wimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2345 = ~out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2346 = ~out_womask_192; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_152 = {hi_719, flags_0_go, _out_prepend_T_152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2347 = out_prepend_152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2348 = _out_T_2347; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_153 = _out_T_2348; // @[RegisterRouter.scala:87:24] wire out_rimask_193 = \|_out_rimask_T_193; // @[RegisterRouter.scala:87:24] wire out_wimask_193 = &_out_wimask_T_193; // @[RegisterRouter.scala:87:24] wire out_romask_193 = \|_out_romask_T_193; // @[RegisterRouter.scala:87:24] wire out_womask_193 = &_out_womask_T_193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_193 = out_rivalid_1_47 & out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2350 = out_f_rivalid_193; // @[RegisterRouter.scala:87:24] wire out_f_roready_193 = out_roready_1_47 & out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2351 = out_f_roready_193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_193 = out_wivalid_1_47 & out_wimask_193; // @[RegisterRouter.scala:87:24] wire out_f_woready_193 = out_woready_1_47 & out_womask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2352 = ~out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2353 = ~out_wimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2354 = ~out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2355 = ~out_womask_193; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_153 = {hi_720, flags_0_go, _out_prepend_T_153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2356 = out_prepend_153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2357 = _out_T_2356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_217 = _out_T_2357; // @[MuxLiteral.scala:49:48] wire out_rimask_194 = \|_out_rimask_T_194; // @[RegisterRouter.scala:87:24] wire out_wimask_194 = &_out_wimask_T_194; // @[RegisterRouter.scala:87:24] wire out_romask_194 = \|_out_romask_T_194; // @[RegisterRouter.scala:87:24] wire out_womask_194 = &_out_womask_T_194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_194 = out_rivalid_1_48 & out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2359 = out_f_rivalid_194; // @[RegisterRouter.scala:87:24] wire out_f_roready_194 = out_roready_1_48 & out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2360 = out_f_roready_194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_194 = out_wivalid_1_48 & out_wimask_194; // @[RegisterRouter.scala:87:24] wire out_f_woready_194 = out_woready_1_48 & out_womask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2361 = ~out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2362 = ~out_wimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2363 = ~out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2364 = ~out_womask_194; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2366 = _out_T_2365; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_154 = _out_T_2366; // @[RegisterRouter.scala:87:24] wire out_rimask_195 = \|_out_rimask_T_195; // @[RegisterRouter.scala:87:24] wire out_wimask_195 = &_out_wimask_T_195; // @[RegisterRouter.scala:87:24] wire out_romask_195 = \|_out_romask_T_195; // @[RegisterRouter.scala:87:24] wire out_womask_195 = &_out_womask_T_195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_195 = out_rivalid_1_49 & out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2368 = out_f_rivalid_195; // @[RegisterRouter.scala:87:24] wire out_f_roready_195 = out_roready_1_49 & out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2369 = out_f_roready_195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_195 = out_wivalid_1_49 & out_wimask_195; // @[RegisterRouter.scala:87:24] wire out_f_woready_195 = out_woready_1_49 & out_womask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2370 = ~out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2371 = ~out_wimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2372 = ~out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2373 = ~out_womask_195; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_154 = {hi_954, flags_0_go, _out_prepend_T_154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2374 = out_prepend_154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2375 = _out_T_2374; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_155 = _out_T_2375; // @[RegisterRouter.scala:87:24] wire out_rimask_196 = \|_out_rimask_T_196; // @[RegisterRouter.scala:87:24] wire out_wimask_196 = &_out_wimask_T_196; // @[RegisterRouter.scala:87:24] wire out_romask_196 = \|_out_romask_T_196; // @[RegisterRouter.scala:87:24] wire out_womask_196 = &_out_womask_T_196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_196 = out_rivalid_1_50 & out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2377 = out_f_rivalid_196; // @[RegisterRouter.scala:87:24] wire out_f_roready_196 = out_roready_1_50 & out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2378 = out_f_roready_196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_196 = out_wivalid_1_50 & out_wimask_196; // @[RegisterRouter.scala:87:24] wire out_f_woready_196 = out_woready_1_50 & out_womask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2379 = ~out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2380 = ~out_wimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2381 = ~out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2382 = ~out_womask_196; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_155 = {hi_955, flags_0_go, _out_prepend_T_155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2383 = out_prepend_155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2384 = _out_T_2383; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_156 = _out_T_2384; // @[RegisterRouter.scala:87:24] wire out_rimask_197 = \|_out_rimask_T_197; // @[RegisterRouter.scala:87:24] wire out_wimask_197 = &_out_wimask_T_197; // @[RegisterRouter.scala:87:24] wire out_romask_197 = \|_out_romask_T_197; // @[RegisterRouter.scala:87:24] wire out_womask_197 = &_out_womask_T_197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_197 = out_rivalid_1_51 & out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2386 = out_f_rivalid_197; // @[RegisterRouter.scala:87:24] wire out_f_roready_197 = out_roready_1_51 & out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2387 = out_f_roready_197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_197 = out_wivalid_1_51 & out_wimask_197; // @[RegisterRouter.scala:87:24] wire out_f_woready_197 = out_woready_1_51 & out_womask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2388 = ~out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2389 = ~out_wimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2390 = ~out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2391 = ~out_womask_197; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_156 = {hi_956, flags_0_go, _out_prepend_T_156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2392 = out_prepend_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2393 = _out_T_2392; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_157 = _out_T_2393; // @[RegisterRouter.scala:87:24] wire out_rimask_198 = \|_out_rimask_T_198; // @[RegisterRouter.scala:87:24] wire out_wimask_198 = &_out_wimask_T_198; // @[RegisterRouter.scala:87:24] wire out_romask_198 = \|_out_romask_T_198; // @[RegisterRouter.scala:87:24] wire out_womask_198 = &_out_womask_T_198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_198 = out_rivalid_1_52 & out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2395 = out_f_rivalid_198; // @[RegisterRouter.scala:87:24] wire out_f_roready_198 = out_roready_1_52 & out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2396 = out_f_roready_198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_198 = out_wivalid_1_52 & out_wimask_198; // @[RegisterRouter.scala:87:24] wire out_f_woready_198 = out_woready_1_52 & out_womask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2397 = ~out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2398 = ~out_wimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2399 = ~out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2400 = ~out_womask_198; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_157 = {hi_957, flags_0_go, _out_prepend_T_157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2401 = out_prepend_157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2402 = _out_T_2401; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_158 = _out_T_2402; // @[RegisterRouter.scala:87:24] wire out_rimask_199 = \|_out_rimask_T_199; // @[RegisterRouter.scala:87:24] wire out_wimask_199 = &_out_wimask_T_199; // @[RegisterRouter.scala:87:24] wire out_romask_199 = \|_out_romask_T_199; // @[RegisterRouter.scala:87:24] wire out_womask_199 = &_out_womask_T_199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_199 = out_rivalid_1_53 & out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2404 = out_f_rivalid_199; // @[RegisterRouter.scala:87:24] wire out_f_roready_199 = out_roready_1_53 & out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2405 = out_f_roready_199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_199 = out_wivalid_1_53 & out_wimask_199; // @[RegisterRouter.scala:87:24] wire out_f_woready_199 = out_woready_1_53 & out_womask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2406 = ~out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2407 = ~out_wimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2408 = ~out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2409 = ~out_womask_199; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_158 = {hi_958, flags_0_go, _out_prepend_T_158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2410 = out_prepend_158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2411 = _out_T_2410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_159 = _out_T_2411; // @[RegisterRouter.scala:87:24] wire out_rimask_200 = \|_out_rimask_T_200; // @[RegisterRouter.scala:87:24] wire out_wimask_200 = &_out_wimask_T_200; // @[RegisterRouter.scala:87:24] wire out_romask_200 = \|_out_romask_T_200; // @[RegisterRouter.scala:87:24] wire out_womask_200 = &_out_womask_T_200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_200 = out_rivalid_1_54 & out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2413 = out_f_rivalid_200; // @[RegisterRouter.scala:87:24] wire out_f_roready_200 = out_roready_1_54 & out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2414 = out_f_roready_200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_200 = out_wivalid_1_54 & out_wimask_200; // @[RegisterRouter.scala:87:24] wire out_f_woready_200 = out_woready_1_54 & out_womask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2415 = ~out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2416 = ~out_wimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2417 = ~out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2418 = ~out_womask_200; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_159 = {hi_959, flags_0_go, _out_prepend_T_159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2419 = out_prepend_159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2420 = _out_T_2419; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_160 = _out_T_2420; // @[RegisterRouter.scala:87:24] wire out_rimask_201 = \|_out_rimask_T_201; // @[RegisterRouter.scala:87:24] wire out_wimask_201 = &_out_wimask_T_201; // @[RegisterRouter.scala:87:24] wire out_romask_201 = \|_out_romask_T_201; // @[RegisterRouter.scala:87:24] wire out_womask_201 = &_out_womask_T_201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_201 = out_rivalid_1_55 & out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2422 = out_f_rivalid_201; // @[RegisterRouter.scala:87:24] wire out_f_roready_201 = out_roready_1_55 & out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2423 = out_f_roready_201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_201 = out_wivalid_1_55 & out_wimask_201; // @[RegisterRouter.scala:87:24] wire out_f_woready_201 = out_woready_1_55 & out_womask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2424 = ~out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2425 = ~out_wimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2426 = ~out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2427 = ~out_womask_201; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_160 = {hi_960, flags_0_go, _out_prepend_T_160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2428 = out_prepend_160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2429 = _out_T_2428; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_247 = _out_T_2429; // @[MuxLiteral.scala:49:48] wire out_rimask_202 = \|_out_rimask_T_202; // @[RegisterRouter.scala:87:24] wire out_wimask_202 = &_out_wimask_T_202; // @[RegisterRouter.scala:87:24] wire out_romask_202 = \|_out_romask_T_202; // @[RegisterRouter.scala:87:24] wire out_womask_202 = &_out_womask_T_202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_202 = out_rivalid_1_56 & out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2431 = out_f_rivalid_202; // @[RegisterRouter.scala:87:24] wire out_f_roready_202 = out_roready_1_56 & out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2432 = out_f_roready_202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_202 = out_wivalid_1_56 & out_wimask_202; // @[RegisterRouter.scala:87:24] wire out_f_woready_202 = out_woready_1_56 & out_womask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2433 = ~out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2434 = ~out_wimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2435 = ~out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2436 = ~out_womask_202; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2438 = _out_T_2437; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_161 = _out_T_2438; // @[RegisterRouter.scala:87:24] wire out_rimask_203 = \|_out_rimask_T_203; // @[RegisterRouter.scala:87:24] wire out_wimask_203 = &_out_wimask_T_203; // @[RegisterRouter.scala:87:24] wire out_romask_203 = \|_out_romask_T_203; // @[RegisterRouter.scala:87:24] wire out_womask_203 = &_out_womask_T_203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_203 = out_rivalid_1_57 & out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2440 = out_f_rivalid_203; // @[RegisterRouter.scala:87:24] wire out_f_roready_203 = out_roready_1_57 & out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2441 = out_f_roready_203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_203 = out_wivalid_1_57 & out_wimask_203; // @[RegisterRouter.scala:87:24] wire out_f_woready_203 = out_woready_1_57 & out_womask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2442 = ~out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2443 = ~out_wimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2444 = ~out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2445 = ~out_womask_203; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_161 = {hi_594, flags_0_go, _out_prepend_T_161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2446 = out_prepend_161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2447 = _out_T_2446; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_162 = _out_T_2447; // @[RegisterRouter.scala:87:24] wire out_rimask_204 = \|_out_rimask_T_204; // @[RegisterRouter.scala:87:24] wire out_wimask_204 = &_out_wimask_T_204; // @[RegisterRouter.scala:87:24] wire out_romask_204 = \|_out_romask_T_204; // @[RegisterRouter.scala:87:24] wire out_womask_204 = &_out_womask_T_204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_204 = out_rivalid_1_58 & out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2449 = out_f_rivalid_204; // @[RegisterRouter.scala:87:24] wire out_f_roready_204 = out_roready_1_58 & out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2450 = out_f_roready_204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_204 = out_wivalid_1_58 & out_wimask_204; // @[RegisterRouter.scala:87:24] wire out_f_woready_204 = out_woready_1_58 & out_womask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2451 = ~out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2452 = ~out_wimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2453 = ~out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2454 = ~out_womask_204; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_162 = {hi_595, flags_0_go, _out_prepend_T_162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2455 = out_prepend_162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2456 = _out_T_2455; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_163 = _out_T_2456; // @[RegisterRouter.scala:87:24] wire out_rimask_205 = \|_out_rimask_T_205; // @[RegisterRouter.scala:87:24] wire out_wimask_205 = &_out_wimask_T_205; // @[RegisterRouter.scala:87:24] wire out_romask_205 = \|_out_romask_T_205; // @[RegisterRouter.scala:87:24] wire out_womask_205 = &_out_womask_T_205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_205 = out_rivalid_1_59 & out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2458 = out_f_rivalid_205; // @[RegisterRouter.scala:87:24] wire out_f_roready_205 = out_roready_1_59 & out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2459 = out_f_roready_205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_205 = out_wivalid_1_59 & out_wimask_205; // @[RegisterRouter.scala:87:24] wire out_f_woready_205 = out_woready_1_59 & out_womask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2460 = ~out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2461 = ~out_wimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2462 = ~out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2463 = ~out_womask_205; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_163 = {hi_596, flags_0_go, _out_prepend_T_163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2464 = out_prepend_163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2465 = _out_T_2464; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_164 = _out_T_2465; // @[RegisterRouter.scala:87:24] wire out_rimask_206 = \|_out_rimask_T_206; // @[RegisterRouter.scala:87:24] wire out_wimask_206 = &_out_wimask_T_206; // @[RegisterRouter.scala:87:24] wire out_romask_206 = \|_out_romask_T_206; // @[RegisterRouter.scala:87:24] wire out_womask_206 = &_out_womask_T_206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_206 = out_rivalid_1_60 & out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2467 = out_f_rivalid_206; // @[RegisterRouter.scala:87:24] wire out_f_roready_206 = out_roready_1_60 & out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2468 = out_f_roready_206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_206 = out_wivalid_1_60 & out_wimask_206; // @[RegisterRouter.scala:87:24] wire out_f_woready_206 = out_woready_1_60 & out_womask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2469 = ~out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2470 = ~out_wimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2471 = ~out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2472 = ~out_womask_206; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_164 = {hi_597, flags_0_go, _out_prepend_T_164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2473 = out_prepend_164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2474 = _out_T_2473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_165 = _out_T_2474; // @[RegisterRouter.scala:87:24] wire out_rimask_207 = \|_out_rimask_T_207; // @[RegisterRouter.scala:87:24] wire out_wimask_207 = &_out_wimask_T_207; // @[RegisterRouter.scala:87:24] wire out_romask_207 = \|_out_romask_T_207; // @[RegisterRouter.scala:87:24] wire out_womask_207 = &_out_womask_T_207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_207 = out_rivalid_1_61 & out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2476 = out_f_rivalid_207; // @[RegisterRouter.scala:87:24] wire out_f_roready_207 = out_roready_1_61 & out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2477 = out_f_roready_207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_207 = out_wivalid_1_61 & out_wimask_207; // @[RegisterRouter.scala:87:24] wire out_f_woready_207 = out_woready_1_61 & out_womask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2478 = ~out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2479 = ~out_wimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2480 = ~out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2481 = ~out_womask_207; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_165 = {hi_598, flags_0_go, _out_prepend_T_165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2482 = out_prepend_165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2483 = _out_T_2482; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_166 = _out_T_2483; // @[RegisterRouter.scala:87:24] wire out_rimask_208 = \|_out_rimask_T_208; // @[RegisterRouter.scala:87:24] wire out_wimask_208 = &_out_wimask_T_208; // @[RegisterRouter.scala:87:24] wire out_romask_208 = \|_out_romask_T_208; // @[RegisterRouter.scala:87:24] wire out_womask_208 = &_out_womask_T_208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_208 = out_rivalid_1_62 & out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2485 = out_f_rivalid_208; // @[RegisterRouter.scala:87:24] wire out_f_roready_208 = out_roready_1_62 & out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2486 = out_f_roready_208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_208 = out_wivalid_1_62 & out_wimask_208; // @[RegisterRouter.scala:87:24] wire out_f_woready_208 = out_woready_1_62 & out_womask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2487 = ~out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2488 = ~out_wimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2489 = ~out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2490 = ~out_womask_208; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_166 = {hi_599, flags_0_go, _out_prepend_T_166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2491 = out_prepend_166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2492 = _out_T_2491; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_167 = _out_T_2492; // @[RegisterRouter.scala:87:24] wire out_rimask_209 = \|_out_rimask_T_209; // @[RegisterRouter.scala:87:24] wire out_wimask_209 = &_out_wimask_T_209; // @[RegisterRouter.scala:87:24] wire out_romask_209 = \|_out_romask_T_209; // @[RegisterRouter.scala:87:24] wire out_womask_209 = &_out_womask_T_209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_209 = out_rivalid_1_63 & out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2494 = out_f_rivalid_209; // @[RegisterRouter.scala:87:24] wire out_f_roready_209 = out_roready_1_63 & out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2495 = out_f_roready_209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_209 = out_wivalid_1_63 & out_wimask_209; // @[RegisterRouter.scala:87:24] wire out_f_woready_209 = out_woready_1_63 & out_womask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2496 = ~out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2497 = ~out_wimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2498 = ~out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2499 = ~out_womask_209; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_167 = {hi_600, flags_0_go, _out_prepend_T_167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2500 = out_prepend_167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2501 = _out_T_2500; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_202 = _out_T_2501; // @[MuxLiteral.scala:49:48] wire out_rimask_210 = \|_out_rimask_T_210; // @[RegisterRouter.scala:87:24] wire out_wimask_210 = &_out_wimask_T_210; // @[RegisterRouter.scala:87:24] wire out_romask_210 = \|_out_romask_T_210; // @[RegisterRouter.scala:87:24] wire out_womask_210 = &_out_womask_T_210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_210 = out_rivalid_1_64 & out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2503 = out_f_rivalid_210; // @[RegisterRouter.scala:87:24] wire out_f_roready_210 = out_roready_1_64 & out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2504 = out_f_roready_210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_210 = out_wivalid_1_64 & out_wimask_210; // @[RegisterRouter.scala:87:24] wire out_f_woready_210 = out_woready_1_64 & out_womask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2505 = ~out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2506 = ~out_wimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2507 = ~out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2508 = ~out_womask_210; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2510 = _out_T_2509; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_168 = _out_T_2510; // @[RegisterRouter.scala:87:24] wire out_rimask_211 = \|_out_rimask_T_211; // @[RegisterRouter.scala:87:24] wire out_wimask_211 = &_out_wimask_T_211; // @[RegisterRouter.scala:87:24] wire out_romask_211 = \|_out_romask_T_211; // @[RegisterRouter.scala:87:24] wire out_womask_211 = &_out_womask_T_211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_211 = out_rivalid_1_65 & out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2512 = out_f_rivalid_211; // @[RegisterRouter.scala:87:24] wire out_f_roready_211 = out_roready_1_65 & out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2513 = out_f_roready_211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_211 = out_wivalid_1_65 & out_wimask_211; // @[RegisterRouter.scala:87:24] wire out_f_woready_211 = out_woready_1_65 & out_womask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2514 = ~out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2515 = ~out_wimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2516 = ~out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2517 = ~out_womask_211; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_168 = {hi_114, flags_0_go, _out_prepend_T_168}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2518 = out_prepend_168; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2519 = _out_T_2518; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_169 = _out_T_2519; // @[RegisterRouter.scala:87:24] wire out_rimask_212 = \|_out_rimask_T_212; // @[RegisterRouter.scala:87:24] wire out_wimask_212 = &_out_wimask_T_212; // @[RegisterRouter.scala:87:24] wire out_romask_212 = \|_out_romask_T_212; // @[RegisterRouter.scala:87:24] wire out_womask_212 = &_out_womask_T_212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_212 = out_rivalid_1_66 & out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2521 = out_f_rivalid_212; // @[RegisterRouter.scala:87:24] wire out_f_roready_212 = out_roready_1_66 & out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2522 = out_f_roready_212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_212 = out_wivalid_1_66 & out_wimask_212; // @[RegisterRouter.scala:87:24] wire out_f_woready_212 = out_woready_1_66 & out_womask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2523 = ~out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2524 = ~out_wimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2525 = ~out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2526 = ~out_womask_212; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_169 = {hi_115, flags_0_go, _out_prepend_T_169}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2527 = out_prepend_169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2528 = _out_T_2527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_170 = _out_T_2528; // @[RegisterRouter.scala:87:24] wire out_rimask_213 = \|_out_rimask_T_213; // @[RegisterRouter.scala:87:24] wire out_wimask_213 = &_out_wimask_T_213; // @[RegisterRouter.scala:87:24] wire out_romask_213 = \|_out_romask_T_213; // @[RegisterRouter.scala:87:24] wire out_womask_213 = &_out_womask_T_213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_213 = out_rivalid_1_67 & out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2530 = out_f_rivalid_213; // @[RegisterRouter.scala:87:24] wire out_f_roready_213 = out_roready_1_67 & out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2531 = out_f_roready_213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_213 = out_wivalid_1_67 & out_wimask_213; // @[RegisterRouter.scala:87:24] wire out_f_woready_213 = out_woready_1_67 & out_womask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2532 = ~out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2533 = ~out_wimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2534 = ~out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2535 = ~out_womask_213; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_170 = {hi_116, flags_0_go, _out_prepend_T_170}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2536 = out_prepend_170; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2537 = _out_T_2536; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_171 = _out_T_2537; // @[RegisterRouter.scala:87:24] wire out_rimask_214 = \|_out_rimask_T_214; // @[RegisterRouter.scala:87:24] wire out_wimask_214 = &_out_wimask_T_214; // @[RegisterRouter.scala:87:24] wire out_romask_214 = \|_out_romask_T_214; // @[RegisterRouter.scala:87:24] wire out_womask_214 = &_out_womask_T_214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_214 = out_rivalid_1_68 & out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2539 = out_f_rivalid_214; // @[RegisterRouter.scala:87:24] wire out_f_roready_214 = out_roready_1_68 & out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2540 = out_f_roready_214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_214 = out_wivalid_1_68 & out_wimask_214; // @[RegisterRouter.scala:87:24] wire out_f_woready_214 = out_woready_1_68 & out_womask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2541 = ~out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2542 = ~out_wimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2543 = ~out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2544 = ~out_womask_214; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_171 = {hi_117, flags_0_go, _out_prepend_T_171}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2545 = out_prepend_171; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2546 = _out_T_2545; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_172 = _out_T_2546; // @[RegisterRouter.scala:87:24] wire out_rimask_215 = \|_out_rimask_T_215; // @[RegisterRouter.scala:87:24] wire out_wimask_215 = &_out_wimask_T_215; // @[RegisterRouter.scala:87:24] wire out_romask_215 = \|_out_romask_T_215; // @[RegisterRouter.scala:87:24] wire out_womask_215 = &_out_womask_T_215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_215 = out_rivalid_1_69 & out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2548 = out_f_rivalid_215; // @[RegisterRouter.scala:87:24] wire out_f_roready_215 = out_roready_1_69 & out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2549 = out_f_roready_215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_215 = out_wivalid_1_69 & out_wimask_215; // @[RegisterRouter.scala:87:24] wire out_f_woready_215 = out_woready_1_69 & out_womask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2550 = ~out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2551 = ~out_wimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2552 = ~out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2553 = ~out_womask_215; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_172 = {hi_118, flags_0_go, _out_prepend_T_172}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2554 = out_prepend_172; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2555 = _out_T_2554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_173 = _out_T_2555; // @[RegisterRouter.scala:87:24] wire out_rimask_216 = \|_out_rimask_T_216; // @[RegisterRouter.scala:87:24] wire out_wimask_216 = &_out_wimask_T_216; // @[RegisterRouter.scala:87:24] wire out_romask_216 = \|_out_romask_T_216; // @[RegisterRouter.scala:87:24] wire out_womask_216 = &_out_womask_T_216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_216 = out_rivalid_1_70 & out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2557 = out_f_rivalid_216; // @[RegisterRouter.scala:87:24] wire out_f_roready_216 = out_roready_1_70 & out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2558 = out_f_roready_216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_216 = out_wivalid_1_70 & out_wimask_216; // @[RegisterRouter.scala:87:24] wire out_f_woready_216 = out_woready_1_70 & out_womask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2559 = ~out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2560 = ~out_wimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2561 = ~out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2562 = ~out_womask_216; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_173 = {hi_119, flags_0_go, _out_prepend_T_173}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2563 = out_prepend_173; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2564 = _out_T_2563; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_174 = _out_T_2564; // @[RegisterRouter.scala:87:24] wire out_rimask_217 = \|_out_rimask_T_217; // @[RegisterRouter.scala:87:24] wire out_wimask_217 = &_out_wimask_T_217; // @[RegisterRouter.scala:87:24] wire out_romask_217 = \|_out_romask_T_217; // @[RegisterRouter.scala:87:24] wire out_womask_217 = &_out_womask_T_217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_217 = out_rivalid_1_71 & out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2566 = out_f_rivalid_217; // @[RegisterRouter.scala:87:24] wire out_f_roready_217 = out_roready_1_71 & out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2567 = out_f_roready_217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_217 = out_wivalid_1_71 & out_wimask_217; // @[RegisterRouter.scala:87:24] wire out_f_woready_217 = out_woready_1_71 & out_womask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2568 = ~out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2569 = ~out_wimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2570 = ~out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2571 = ~out_womask_217; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_174 = {hi_120, flags_0_go, _out_prepend_T_174}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2572 = out_prepend_174; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2573 = _out_T_2572; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_142 = _out_T_2573; // @[MuxLiteral.scala:49:48] wire out_rimask_218 = \|_out_rimask_T_218; // @[RegisterRouter.scala:87:24] wire out_wimask_218 = &_out_wimask_T_218; // @[RegisterRouter.scala:87:24] wire out_romask_218 = \|_out_romask_T_218; // @[RegisterRouter.scala:87:24] wire out_womask_218 = &_out_womask_T_218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_218 = out_rivalid_1_72 & out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2575 = out_f_rivalid_218; // @[RegisterRouter.scala:87:24] wire out_f_roready_218 = out_roready_1_72 & out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2576 = out_f_roready_218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_218 = out_wivalid_1_72 & out_wimask_218; // @[RegisterRouter.scala:87:24] wire out_f_woready_218 = out_woready_1_72 & out_womask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2577 = ~out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2578 = ~out_wimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2579 = ~out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2580 = ~out_womask_218; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2582 = _out_T_2581; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_175 = _out_T_2582; // @[RegisterRouter.scala:87:24] wire out_rimask_219 = \|_out_rimask_T_219; // @[RegisterRouter.scala:87:24] wire out_wimask_219 = &_out_wimask_T_219; // @[RegisterRouter.scala:87:24] wire out_romask_219 = \|_out_romask_T_219; // @[RegisterRouter.scala:87:24] wire out_womask_219 = &_out_womask_T_219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_219 = out_rivalid_1_73 & out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2584 = out_f_rivalid_219; // @[RegisterRouter.scala:87:24] wire out_f_roready_219 = out_roready_1_73 & out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2585 = out_f_roready_219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_219 = out_wivalid_1_73 & out_wimask_219; // @[RegisterRouter.scala:87:24] wire out_f_woready_219 = out_woready_1_73 & out_womask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2586 = ~out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2587 = ~out_wimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2588 = ~out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2589 = ~out_womask_219; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_175 = {hi_202, flags_0_go, _out_prepend_T_175}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2590 = out_prepend_175; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2591 = _out_T_2590; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_176 = _out_T_2591; // @[RegisterRouter.scala:87:24] wire out_rimask_220 = \|_out_rimask_T_220; // @[RegisterRouter.scala:87:24] wire out_wimask_220 = &_out_wimask_T_220; // @[RegisterRouter.scala:87:24] wire out_romask_220 = \|_out_romask_T_220; // @[RegisterRouter.scala:87:24] wire out_womask_220 = &_out_womask_T_220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_220 = out_rivalid_1_74 & out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2593 = out_f_rivalid_220; // @[RegisterRouter.scala:87:24] wire out_f_roready_220 = out_roready_1_74 & out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2594 = out_f_roready_220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_220 = out_wivalid_1_74 & out_wimask_220; // @[RegisterRouter.scala:87:24] wire out_f_woready_220 = out_woready_1_74 & out_womask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2595 = ~out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2596 = ~out_wimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2597 = ~out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2598 = ~out_womask_220; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_176 = {hi_203, flags_0_go, _out_prepend_T_176}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2599 = out_prepend_176; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2600 = _out_T_2599; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_177 = _out_T_2600; // @[RegisterRouter.scala:87:24] wire out_rimask_221 = \|_out_rimask_T_221; // @[RegisterRouter.scala:87:24] wire out_wimask_221 = &_out_wimask_T_221; // @[RegisterRouter.scala:87:24] wire out_romask_221 = \|_out_romask_T_221; // @[RegisterRouter.scala:87:24] wire out_womask_221 = &_out_womask_T_221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_221 = out_rivalid_1_75 & out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2602 = out_f_rivalid_221; // @[RegisterRouter.scala:87:24] wire out_f_roready_221 = out_roready_1_75 & out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2603 = out_f_roready_221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_221 = out_wivalid_1_75 & out_wimask_221; // @[RegisterRouter.scala:87:24] wire out_f_woready_221 = out_woready_1_75 & out_womask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2604 = ~out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2605 = ~out_wimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2606 = ~out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2607 = ~out_womask_221; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_177 = {hi_204, flags_0_go, _out_prepend_T_177}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2608 = out_prepend_177; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2609 = _out_T_2608; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_178 = _out_T_2609; // @[RegisterRouter.scala:87:24] wire out_rimask_222 = \|_out_rimask_T_222; // @[RegisterRouter.scala:87:24] wire out_wimask_222 = &_out_wimask_T_222; // @[RegisterRouter.scala:87:24] wire out_romask_222 = \|_out_romask_T_222; // @[RegisterRouter.scala:87:24] wire out_womask_222 = &_out_womask_T_222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_222 = out_rivalid_1_76 & out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2611 = out_f_rivalid_222; // @[RegisterRouter.scala:87:24] wire out_f_roready_222 = out_roready_1_76 & out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2612 = out_f_roready_222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_222 = out_wivalid_1_76 & out_wimask_222; // @[RegisterRouter.scala:87:24] wire out_f_woready_222 = out_woready_1_76 & out_womask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2613 = ~out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2614 = ~out_wimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2615 = ~out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2616 = ~out_womask_222; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_178 = {hi_205, flags_0_go, _out_prepend_T_178}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2617 = out_prepend_178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2618 = _out_T_2617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_179 = _out_T_2618; // @[RegisterRouter.scala:87:24] wire out_rimask_223 = \|_out_rimask_T_223; // @[RegisterRouter.scala:87:24] wire out_wimask_223 = &_out_wimask_T_223; // @[RegisterRouter.scala:87:24] wire out_romask_223 = \|_out_romask_T_223; // @[RegisterRouter.scala:87:24] wire out_womask_223 = &_out_womask_T_223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_223 = out_rivalid_1_77 & out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2620 = out_f_rivalid_223; // @[RegisterRouter.scala:87:24] wire out_f_roready_223 = out_roready_1_77 & out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2621 = out_f_roready_223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_223 = out_wivalid_1_77 & out_wimask_223; // @[RegisterRouter.scala:87:24] wire out_f_woready_223 = out_woready_1_77 & out_womask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2622 = ~out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2623 = ~out_wimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2624 = ~out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2625 = ~out_womask_223; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_179 = {hi_206, flags_0_go, _out_prepend_T_179}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2626 = out_prepend_179; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2627 = _out_T_2626; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_180 = _out_T_2627; // @[RegisterRouter.scala:87:24] wire out_rimask_224 = \|_out_rimask_T_224; // @[RegisterRouter.scala:87:24] wire out_wimask_224 = &_out_wimask_T_224; // @[RegisterRouter.scala:87:24] wire out_romask_224 = \|_out_romask_T_224; // @[RegisterRouter.scala:87:24] wire out_womask_224 = &_out_womask_T_224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_224 = out_rivalid_1_78 & out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2629 = out_f_rivalid_224; // @[RegisterRouter.scala:87:24] wire out_f_roready_224 = out_roready_1_78 & out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2630 = out_f_roready_224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_224 = out_wivalid_1_78 & out_wimask_224; // @[RegisterRouter.scala:87:24] wire out_f_woready_224 = out_woready_1_78 & out_womask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2631 = ~out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2632 = ~out_wimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2633 = ~out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2634 = ~out_womask_224; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_180 = {hi_207, flags_0_go, _out_prepend_T_180}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2635 = out_prepend_180; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2636 = _out_T_2635; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_181 = _out_T_2636; // @[RegisterRouter.scala:87:24] wire out_rimask_225 = \|_out_rimask_T_225; // @[RegisterRouter.scala:87:24] wire out_wimask_225 = &_out_wimask_T_225; // @[RegisterRouter.scala:87:24] wire out_romask_225 = \|_out_romask_T_225; // @[RegisterRouter.scala:87:24] wire out_womask_225 = &_out_womask_T_225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_225 = out_rivalid_1_79 & out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2638 = out_f_rivalid_225; // @[RegisterRouter.scala:87:24] wire out_f_roready_225 = out_roready_1_79 & out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2639 = out_f_roready_225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_225 = out_wivalid_1_79 & out_wimask_225; // @[RegisterRouter.scala:87:24] wire out_f_woready_225 = out_woready_1_79 & out_womask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2640 = ~out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2641 = ~out_wimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2642 = ~out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2643 = ~out_womask_225; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_181 = {hi_208, flags_0_go, _out_prepend_T_181}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2644 = out_prepend_181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2645 = _out_T_2644; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_153 = _out_T_2645; // @[MuxLiteral.scala:49:48] wire out_rimask_226 = \|_out_rimask_T_226; // @[RegisterRouter.scala:87:24] wire out_wimask_226 = &_out_wimask_T_226; // @[RegisterRouter.scala:87:24] wire out_romask_226 = \|_out_romask_T_226; // @[RegisterRouter.scala:87:24] wire out_womask_226 = &_out_womask_T_226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_226 = out_rivalid_1_80 & out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2647 = out_f_rivalid_226; // @[RegisterRouter.scala:87:24] wire out_f_roready_226 = out_roready_1_80 & out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2648 = out_f_roready_226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_226 = out_wivalid_1_80 & out_wimask_226; // @[RegisterRouter.scala:87:24] wire out_f_woready_226 = out_woready_1_80 & out_womask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2649 = ~out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2650 = ~out_wimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2651 = ~out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2652 = ~out_womask_226; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2654 = _out_T_2653; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_182 = _out_T_2654; // @[RegisterRouter.scala:87:24] wire out_rimask_227 = \|_out_rimask_T_227; // @[RegisterRouter.scala:87:24] wire out_wimask_227 = &_out_wimask_T_227; // @[RegisterRouter.scala:87:24] wire out_romask_227 = \|_out_romask_T_227; // @[RegisterRouter.scala:87:24] wire out_womask_227 = &_out_womask_T_227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_227 = out_rivalid_1_81 & out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2656 = out_f_rivalid_227; // @[RegisterRouter.scala:87:24] wire out_f_roready_227 = out_roready_1_81 & out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2657 = out_f_roready_227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_227 = out_wivalid_1_81 & out_wimask_227; // @[RegisterRouter.scala:87:24] wire out_f_woready_227 = out_woready_1_81 & out_womask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2658 = ~out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2659 = ~out_wimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2660 = ~out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2661 = ~out_womask_227; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_182 = {hi_370, flags_0_go, _out_prepend_T_182}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2662 = out_prepend_182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2663 = _out_T_2662; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_183 = _out_T_2663; // @[RegisterRouter.scala:87:24] wire out_rimask_228 = \|_out_rimask_T_228; // @[RegisterRouter.scala:87:24] wire out_wimask_228 = &_out_wimask_T_228; // @[RegisterRouter.scala:87:24] wire out_romask_228 = \|_out_romask_T_228; // @[RegisterRouter.scala:87:24] wire out_womask_228 = &_out_womask_T_228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_228 = out_rivalid_1_82 & out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2665 = out_f_rivalid_228; // @[RegisterRouter.scala:87:24] wire out_f_roready_228 = out_roready_1_82 & out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2666 = out_f_roready_228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_228 = out_wivalid_1_82 & out_wimask_228; // @[RegisterRouter.scala:87:24] wire out_f_woready_228 = out_woready_1_82 & out_womask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2667 = ~out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2668 = ~out_wimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2669 = ~out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2670 = ~out_womask_228; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_183 = {hi_371, flags_0_go, _out_prepend_T_183}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2671 = out_prepend_183; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2672 = _out_T_2671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_184 = _out_T_2672; // @[RegisterRouter.scala:87:24] wire out_rimask_229 = \|_out_rimask_T_229; // @[RegisterRouter.scala:87:24] wire out_wimask_229 = &_out_wimask_T_229; // @[RegisterRouter.scala:87:24] wire out_romask_229 = \|_out_romask_T_229; // @[RegisterRouter.scala:87:24] wire out_womask_229 = &_out_womask_T_229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_229 = out_rivalid_1_83 & out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2674 = out_f_rivalid_229; // @[RegisterRouter.scala:87:24] wire out_f_roready_229 = out_roready_1_83 & out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2675 = out_f_roready_229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_229 = out_wivalid_1_83 & out_wimask_229; // @[RegisterRouter.scala:87:24] wire out_f_woready_229 = out_woready_1_83 & out_womask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2676 = ~out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2677 = ~out_wimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2678 = ~out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2679 = ~out_womask_229; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_184 = {hi_372, flags_0_go, _out_prepend_T_184}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2680 = out_prepend_184; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2681 = _out_T_2680; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_185 = _out_T_2681; // @[RegisterRouter.scala:87:24] wire out_rimask_230 = \|_out_rimask_T_230; // @[RegisterRouter.scala:87:24] wire out_wimask_230 = &_out_wimask_T_230; // @[RegisterRouter.scala:87:24] wire out_romask_230 = \|_out_romask_T_230; // @[RegisterRouter.scala:87:24] wire out_womask_230 = &_out_womask_T_230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_230 = out_rivalid_1_84 & out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2683 = out_f_rivalid_230; // @[RegisterRouter.scala:87:24] wire out_f_roready_230 = out_roready_1_84 & out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2684 = out_f_roready_230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_230 = out_wivalid_1_84 & out_wimask_230; // @[RegisterRouter.scala:87:24] wire out_f_woready_230 = out_woready_1_84 & out_womask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2685 = ~out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2686 = ~out_wimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2687 = ~out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2688 = ~out_womask_230; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_185 = {hi_373, flags_0_go, _out_prepend_T_185}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2689 = out_prepend_185; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2690 = _out_T_2689; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_186 = _out_T_2690; // @[RegisterRouter.scala:87:24] wire out_rimask_231 = \|_out_rimask_T_231; // @[RegisterRouter.scala:87:24] wire out_wimask_231 = &_out_wimask_T_231; // @[RegisterRouter.scala:87:24] wire out_romask_231 = \|_out_romask_T_231; // @[RegisterRouter.scala:87:24] wire out_womask_231 = &_out_womask_T_231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_231 = out_rivalid_1_85 & out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2692 = out_f_rivalid_231; // @[RegisterRouter.scala:87:24] wire out_f_roready_231 = out_roready_1_85 & out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2693 = out_f_roready_231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_231 = out_wivalid_1_85 & out_wimask_231; // @[RegisterRouter.scala:87:24] wire out_f_woready_231 = out_woready_1_85 & out_womask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2694 = ~out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2695 = ~out_wimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2696 = ~out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2697 = ~out_womask_231; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_186 = {hi_374, flags_0_go, _out_prepend_T_186}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2698 = out_prepend_186; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2699 = _out_T_2698; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_187 = _out_T_2699; // @[RegisterRouter.scala:87:24] wire out_rimask_232 = \|_out_rimask_T_232; // @[RegisterRouter.scala:87:24] wire out_wimask_232 = &_out_wimask_T_232; // @[RegisterRouter.scala:87:24] wire out_romask_232 = \|_out_romask_T_232; // @[RegisterRouter.scala:87:24] wire out_womask_232 = &_out_womask_T_232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_232 = out_rivalid_1_86 & out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2701 = out_f_rivalid_232; // @[RegisterRouter.scala:87:24] wire out_f_roready_232 = out_roready_1_86 & out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2702 = out_f_roready_232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_232 = out_wivalid_1_86 & out_wimask_232; // @[RegisterRouter.scala:87:24] wire out_f_woready_232 = out_woready_1_86 & out_womask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2703 = ~out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2704 = ~out_wimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2705 = ~out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2706 = ~out_womask_232; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_187 = {hi_375, flags_0_go, _out_prepend_T_187}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2707 = out_prepend_187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2708 = _out_T_2707; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_188 = _out_T_2708; // @[RegisterRouter.scala:87:24] wire out_rimask_233 = \|_out_rimask_T_233; // @[RegisterRouter.scala:87:24] wire out_wimask_233 = &_out_wimask_T_233; // @[RegisterRouter.scala:87:24] wire out_romask_233 = \|_out_romask_T_233; // @[RegisterRouter.scala:87:24] wire out_womask_233 = &_out_womask_T_233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_233 = out_rivalid_1_87 & out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2710 = out_f_rivalid_233; // @[RegisterRouter.scala:87:24] wire out_f_roready_233 = out_roready_1_87 & out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2711 = out_f_roready_233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_233 = out_wivalid_1_87 & out_wimask_233; // @[RegisterRouter.scala:87:24] wire out_f_woready_233 = out_woready_1_87 & out_womask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2712 = ~out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2713 = ~out_wimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2714 = ~out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2715 = ~out_womask_233; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_188 = {hi_376, flags_0_go, _out_prepend_T_188}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2716 = out_prepend_188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2717 = _out_T_2716; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_174 = _out_T_2717; // @[MuxLiteral.scala:49:48] wire out_rimask_234 = \|_out_rimask_T_234; // @[RegisterRouter.scala:87:24] wire out_wimask_234 = &_out_wimask_T_234; // @[RegisterRouter.scala:87:24] wire out_romask_234 = \|_out_romask_T_234; // @[RegisterRouter.scala:87:24] wire out_womask_234 = &_out_womask_T_234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_234 = out_rivalid_1_88 & out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2719 = out_f_rivalid_234; // @[RegisterRouter.scala:87:24] wire out_f_roready_234 = out_roready_1_88 & out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2720 = out_f_roready_234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_234 = out_wivalid_1_88 & out_wimask_234; // @[RegisterRouter.scala:87:24] wire out_f_woready_234 = out_woready_1_88 & out_womask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2721 = ~out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2722 = ~out_wimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2723 = ~out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2724 = ~out_womask_234; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2726 = _out_T_2725; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_189 = _out_T_2726; // @[RegisterRouter.scala:87:24] wire out_rimask_235 = \|_out_rimask_T_235; // @[RegisterRouter.scala:87:24] wire out_wimask_235 = &_out_wimask_T_235; // @[RegisterRouter.scala:87:24] wire out_romask_235 = \|_out_romask_T_235; // @[RegisterRouter.scala:87:24] wire out_womask_235 = &_out_womask_T_235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_235 = out_rivalid_1_89 & out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2728 = out_f_rivalid_235; // @[RegisterRouter.scala:87:24] wire out_f_roready_235 = out_roready_1_89 & out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2729 = out_f_roready_235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_235 = out_wivalid_1_89 & out_wimask_235; // @[RegisterRouter.scala:87:24] wire out_f_woready_235 = out_woready_1_89 & out_womask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2730 = ~out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2731 = ~out_wimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2732 = ~out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2733 = ~out_womask_235; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_189 = {hi_458, flags_0_go, _out_prepend_T_189}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2734 = out_prepend_189; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2735 = _out_T_2734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_190 = _out_T_2735; // @[RegisterRouter.scala:87:24] wire out_rimask_236 = \|_out_rimask_T_236; // @[RegisterRouter.scala:87:24] wire out_wimask_236 = &_out_wimask_T_236; // @[RegisterRouter.scala:87:24] wire out_romask_236 = \|_out_romask_T_236; // @[RegisterRouter.scala:87:24] wire out_womask_236 = &_out_womask_T_236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_236 = out_rivalid_1_90 & out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2737 = out_f_rivalid_236; // @[RegisterRouter.scala:87:24] wire out_f_roready_236 = out_roready_1_90 & out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2738 = out_f_roready_236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_236 = out_wivalid_1_90 & out_wimask_236; // @[RegisterRouter.scala:87:24] wire out_f_woready_236 = out_woready_1_90 & out_womask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2739 = ~out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2740 = ~out_wimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2741 = ~out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2742 = ~out_womask_236; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_190 = {hi_459, flags_0_go, _out_prepend_T_190}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2743 = out_prepend_190; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2744 = _out_T_2743; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_191 = _out_T_2744; // @[RegisterRouter.scala:87:24] wire out_rimask_237 = \|_out_rimask_T_237; // @[RegisterRouter.scala:87:24] wire out_wimask_237 = &_out_wimask_T_237; // @[RegisterRouter.scala:87:24] wire out_romask_237 = \|_out_romask_T_237; // @[RegisterRouter.scala:87:24] wire out_womask_237 = &_out_womask_T_237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_237 = out_rivalid_1_91 & out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2746 = out_f_rivalid_237; // @[RegisterRouter.scala:87:24] wire out_f_roready_237 = out_roready_1_91 & out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2747 = out_f_roready_237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_237 = out_wivalid_1_91 & out_wimask_237; // @[RegisterRouter.scala:87:24] wire out_f_woready_237 = out_woready_1_91 & out_womask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2748 = ~out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2749 = ~out_wimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2750 = ~out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2751 = ~out_womask_237; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_191 = {hi_460, flags_0_go, _out_prepend_T_191}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2752 = out_prepend_191; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2753 = _out_T_2752; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_192 = _out_T_2753; // @[RegisterRouter.scala:87:24] wire out_rimask_238 = \|_out_rimask_T_238; // @[RegisterRouter.scala:87:24] wire out_wimask_238 = &_out_wimask_T_238; // @[RegisterRouter.scala:87:24] wire out_romask_238 = \|_out_romask_T_238; // @[RegisterRouter.scala:87:24] wire out_womask_238 = &_out_womask_T_238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_238 = out_rivalid_1_92 & out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2755 = out_f_rivalid_238; // @[RegisterRouter.scala:87:24] wire out_f_roready_238 = out_roready_1_92 & out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2756 = out_f_roready_238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_238 = out_wivalid_1_92 & out_wimask_238; // @[RegisterRouter.scala:87:24] wire out_f_woready_238 = out_woready_1_92 & out_womask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2757 = ~out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2758 = ~out_wimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2759 = ~out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2760 = ~out_womask_238; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_192 = {hi_461, flags_0_go, _out_prepend_T_192}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2761 = out_prepend_192; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2762 = _out_T_2761; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_193 = _out_T_2762; // @[RegisterRouter.scala:87:24] wire out_rimask_239 = \|_out_rimask_T_239; // @[RegisterRouter.scala:87:24] wire out_wimask_239 = &_out_wimask_T_239; // @[RegisterRouter.scala:87:24] wire out_romask_239 = \|_out_romask_T_239; // @[RegisterRouter.scala:87:24] wire out_womask_239 = &_out_womask_T_239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_239 = out_rivalid_1_93 & out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2764 = out_f_rivalid_239; // @[RegisterRouter.scala:87:24] wire out_f_roready_239 = out_roready_1_93 & out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2765 = out_f_roready_239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_239 = out_wivalid_1_93 & out_wimask_239; // @[RegisterRouter.scala:87:24] wire out_f_woready_239 = out_woready_1_93 & out_womask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2766 = ~out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2767 = ~out_wimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2768 = ~out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2769 = ~out_womask_239; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_193 = {hi_462, flags_0_go, _out_prepend_T_193}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2770 = out_prepend_193; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2771 = _out_T_2770; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_194 = _out_T_2771; // @[RegisterRouter.scala:87:24] wire out_rimask_240 = \|_out_rimask_T_240; // @[RegisterRouter.scala:87:24] wire out_wimask_240 = &_out_wimask_T_240; // @[RegisterRouter.scala:87:24] wire out_romask_240 = \|_out_romask_T_240; // @[RegisterRouter.scala:87:24] wire out_womask_240 = &_out_womask_T_240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_240 = out_rivalid_1_94 & out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2773 = out_f_rivalid_240; // @[RegisterRouter.scala:87:24] wire out_f_roready_240 = out_roready_1_94 & out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2774 = out_f_roready_240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_240 = out_wivalid_1_94 & out_wimask_240; // @[RegisterRouter.scala:87:24] wire out_f_woready_240 = out_woready_1_94 & out_womask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2775 = ~out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2776 = ~out_wimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2777 = ~out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2778 = ~out_womask_240; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_194 = {hi_463, flags_0_go, _out_prepend_T_194}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2779 = out_prepend_194; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2780 = _out_T_2779; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_195 = _out_T_2780; // @[RegisterRouter.scala:87:24] wire out_rimask_241 = \|_out_rimask_T_241; // @[RegisterRouter.scala:87:24] wire out_wimask_241 = &_out_wimask_T_241; // @[RegisterRouter.scala:87:24] wire out_romask_241 = \|_out_romask_T_241; // @[RegisterRouter.scala:87:24] wire out_womask_241 = &_out_womask_T_241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_241 = out_rivalid_1_95 & out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2782 = out_f_rivalid_241; // @[RegisterRouter.scala:87:24] wire out_f_roready_241 = out_roready_1_95 & out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2783 = out_f_roready_241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_241 = out_wivalid_1_95 & out_wimask_241; // @[RegisterRouter.scala:87:24] wire out_f_woready_241 = out_woready_1_95 & out_womask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2784 = ~out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2785 = ~out_wimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2786 = ~out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2787 = ~out_womask_241; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_195 = {hi_464, flags_0_go, _out_prepend_T_195}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2788 = out_prepend_195; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2789 = _out_T_2788; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_185 = _out_T_2789; // @[MuxLiteral.scala:49:48] wire out_rimask_242 = \|_out_rimask_T_242; // @[RegisterRouter.scala:87:24] wire out_wimask_242 = &_out_wimask_T_242; // @[RegisterRouter.scala:87:24] wire out_romask_242 = \|_out_romask_T_242; // @[RegisterRouter.scala:87:24] wire out_womask_242 = &_out_womask_T_242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_242 = out_rivalid_1_96 & out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2791 = out_f_rivalid_242; // @[RegisterRouter.scala:87:24] wire out_f_roready_242 = out_roready_1_96 & out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2792 = out_f_roready_242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_242 = out_wivalid_1_96 & out_wimask_242; // @[RegisterRouter.scala:87:24] wire out_f_woready_242 = out_woready_1_96 & out_womask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2793 = ~out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2794 = ~out_wimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2795 = ~out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2796 = ~out_womask_242; // @[RegisterRouter.scala:87:24] wire out_rimask_243 = \|_out_rimask_T_243; // @[RegisterRouter.scala:87:24] wire out_wimask_243 = &_out_wimask_T_243; // @[RegisterRouter.scala:87:24] wire out_romask_243 = \|_out_romask_T_243; // @[RegisterRouter.scala:87:24] wire out_womask_243 = &_out_womask_T_243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_243 = out_rivalid_1_97 & out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2800 = out_f_rivalid_243; // @[RegisterRouter.scala:87:24] wire out_f_roready_243 = out_roready_1_97 & out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2801 = out_f_roready_243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_243 = out_wivalid_1_97 & out_wimask_243; // @[RegisterRouter.scala:87:24] wire out_f_woready_243 = out_woready_1_97 & out_womask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2802 = ~out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2803 = ~out_wimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2804 = ~out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2805 = ~out_womask_243; // @[RegisterRouter.scala:87:24] wire out_rimask_244 = \|_out_rimask_T_244; // @[RegisterRouter.scala:87:24] wire out_wimask_244 = &_out_wimask_T_244; // @[RegisterRouter.scala:87:24] wire out_romask_244 = \|_out_romask_T_244; // @[RegisterRouter.scala:87:24] wire out_womask_244 = &_out_womask_T_244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_244 = out_rivalid_1_98 & out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2809 = out_f_rivalid_244; // @[RegisterRouter.scala:87:24] wire out_f_roready_244 = out_roready_1_98 & out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2810 = out_f_roready_244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_244 = out_wivalid_1_98 & out_wimask_244; // @[RegisterRouter.scala:87:24] wire out_f_woready_244 = out_woready_1_98 & out_womask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2811 = ~out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2812 = ~out_wimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2813 = ~out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2814 = ~out_womask_244; // @[RegisterRouter.scala:87:24] wire out_rimask_245 = \|_out_rimask_T_245; // @[RegisterRouter.scala:87:24] wire out_wimask_245 = &_out_wimask_T_245; // @[RegisterRouter.scala:87:24] wire out_romask_245 = \|_out_romask_T_245; // @[RegisterRouter.scala:87:24] wire out_womask_245 = &_out_womask_T_245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_245 = out_rivalid_1_99 & out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2818 = out_f_rivalid_245; // @[RegisterRouter.scala:87:24] wire out_f_roready_245 = out_roready_1_99 & out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2819 = out_f_roready_245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_245 = out_wivalid_1_99 & out_wimask_245; // @[RegisterRouter.scala:87:24] wire out_f_woready_245 = out_woready_1_99 & out_womask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2820 = ~out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2821 = ~out_wimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2822 = ~out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2823 = ~out_womask_245; // @[RegisterRouter.scala:87:24] wire out_rimask_246 = \|_out_rimask_T_246; // @[RegisterRouter.scala:87:24] wire out_wimask_246 = &_out_wimask_T_246; // @[RegisterRouter.scala:87:24] wire out_romask_246 = \|_out_romask_T_246; // @[RegisterRouter.scala:87:24] wire out_womask_246 = &_out_womask_T_246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_246 = out_rivalid_1_100 & out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2827 = out_f_rivalid_246; // @[RegisterRouter.scala:87:24] wire out_f_roready_246 = out_roready_1_100 & out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2828 = out_f_roready_246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_246 = out_wivalid_1_100 & out_wimask_246; // @[RegisterRouter.scala:87:24] wire out_f_woready_246 = out_woready_1_100 & out_womask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2829 = ~out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2830 = ~out_wimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2831 = ~out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2832 = ~out_womask_246; // @[RegisterRouter.scala:87:24] wire out_rimask_247 = \|_out_rimask_T_247; // @[RegisterRouter.scala:87:24] wire out_wimask_247 = &_out_wimask_T_247; // @[RegisterRouter.scala:87:24] wire out_romask_247 = \|_out_romask_T_247; // @[RegisterRouter.scala:87:24] wire out_womask_247 = &_out_womask_T_247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_247 = out_rivalid_1_101 & out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2836 = out_f_rivalid_247; // @[RegisterRouter.scala:87:24] wire out_f_roready_247 = out_roready_1_101 & out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2837 = out_f_roready_247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_247 = out_wivalid_1_101 & out_wimask_247; // @[RegisterRouter.scala:87:24] wire out_f_woready_247 = out_woready_1_101 & out_womask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2838 = ~out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2839 = ~out_wimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2840 = ~out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2841 = ~out_womask_247; // @[RegisterRouter.scala:87:24] wire out_rimask_248 = \|_out_rimask_T_248; // @[RegisterRouter.scala:87:24] wire out_wimask_248 = &_out_wimask_T_248; // @[RegisterRouter.scala:87:24] wire out_romask_248 = \|_out_romask_T_248; // @[RegisterRouter.scala:87:24] wire out_womask_248 = &_out_womask_T_248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_248 = out_rivalid_1_102 & out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2845 = out_f_rivalid_248; // @[RegisterRouter.scala:87:24] wire out_f_roready_248 = out_roready_1_102 & out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2846 = out_f_roready_248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_248 = out_wivalid_1_102 & out_wimask_248; // @[RegisterRouter.scala:87:24] wire out_f_woready_248 = out_woready_1_102 & out_womask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2847 = ~out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2848 = ~out_wimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2849 = ~out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2850 = ~out_womask_248; // @[RegisterRouter.scala:87:24] wire out_rimask_249 = \|_out_rimask_T_249; // @[RegisterRouter.scala:87:24] wire out_wimask_249 = &_out_wimask_T_249; // @[RegisterRouter.scala:87:24] wire out_romask_249 = \|_out_romask_T_249; // @[RegisterRouter.scala:87:24] wire out_womask_249 = &_out_womask_T_249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_249 = out_rivalid_1_103 & out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2854 = out_f_rivalid_249; // @[RegisterRouter.scala:87:24] wire out_f_roready_249 = out_roready_1_103 & out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2855 = out_f_roready_249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_249 = out_wivalid_1_103 & out_wimask_249; // @[RegisterRouter.scala:87:24] wire out_f_woready_249 = out_woready_1_103 & out_womask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2856 = ~out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2857 = ~out_wimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2858 = ~out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2859 = ~out_womask_249; // @[RegisterRouter.scala:87:24] wire out_rimask_250 = \|_out_rimask_T_250; // @[RegisterRouter.scala:87:24] wire out_wimask_250 = &_out_wimask_T_250; // @[RegisterRouter.scala:87:24] wire out_romask_250 = \|_out_romask_T_250; // @[RegisterRouter.scala:87:24] wire out_womask_250 = &_out_womask_T_250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_250 = out_rivalid_1_104 & out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2863 = out_f_rivalid_250; // @[RegisterRouter.scala:87:24] wire out_f_roready_250 = out_roready_1_104 & out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2864 = out_f_roready_250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_250 = out_wivalid_1_104 & out_wimask_250; // @[RegisterRouter.scala:87:24] wire out_f_woready_250 = out_woready_1_104 & out_womask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2865 = ~out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2866 = ~out_wimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2867 = ~out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2868 = ~out_womask_250; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2870 = _out_T_2869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_203 = _out_T_2870; // @[RegisterRouter.scala:87:24] wire out_rimask_251 = \|_out_rimask_T_251; // @[RegisterRouter.scala:87:24] wire out_wimask_251 = &_out_wimask_T_251; // @[RegisterRouter.scala:87:24] wire out_romask_251 = \|_out_romask_T_251; // @[RegisterRouter.scala:87:24] wire out_womask_251 = &_out_womask_T_251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_251 = out_rivalid_1_105 & out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2872 = out_f_rivalid_251; // @[RegisterRouter.scala:87:24] wire out_f_roready_251 = out_roready_1_105 & out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2873 = out_f_roready_251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_251 = out_wivalid_1_105 & out_wimask_251; // @[RegisterRouter.scala:87:24] wire out_f_woready_251 = out_woready_1_105 & out_womask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2874 = ~out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2875 = ~out_wimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2876 = ~out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2877 = ~out_womask_251; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_203 = {hi_450, flags_0_go, _out_prepend_T_203}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2878 = out_prepend_203; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2879 = _out_T_2878; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_204 = _out_T_2879; // @[RegisterRouter.scala:87:24] wire out_rimask_252 = \|_out_rimask_T_252; // @[RegisterRouter.scala:87:24] wire out_wimask_252 = &_out_wimask_T_252; // @[RegisterRouter.scala:87:24] wire out_romask_252 = \|_out_romask_T_252; // @[RegisterRouter.scala:87:24] wire out_womask_252 = &_out_womask_T_252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_252 = out_rivalid_1_106 & out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2881 = out_f_rivalid_252; // @[RegisterRouter.scala:87:24] wire out_f_roready_252 = out_roready_1_106 & out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2882 = out_f_roready_252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_252 = out_wivalid_1_106 & out_wimask_252; // @[RegisterRouter.scala:87:24] wire out_f_woready_252 = out_woready_1_106 & out_womask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2883 = ~out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2884 = ~out_wimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2885 = ~out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2886 = ~out_womask_252; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_204 = {hi_451, flags_0_go, _out_prepend_T_204}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2887 = out_prepend_204; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2888 = _out_T_2887; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_205 = _out_T_2888; // @[RegisterRouter.scala:87:24] wire out_rimask_253 = \|_out_rimask_T_253; // @[RegisterRouter.scala:87:24] wire out_wimask_253 = &_out_wimask_T_253; // @[RegisterRouter.scala:87:24] wire out_romask_253 = \|_out_romask_T_253; // @[RegisterRouter.scala:87:24] wire out_womask_253 = &_out_womask_T_253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_253 = out_rivalid_1_107 & out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2890 = out_f_rivalid_253; // @[RegisterRouter.scala:87:24] wire out_f_roready_253 = out_roready_1_107 & out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2891 = out_f_roready_253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_253 = out_wivalid_1_107 & out_wimask_253; // @[RegisterRouter.scala:87:24] wire out_f_woready_253 = out_woready_1_107 & out_womask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2892 = ~out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2893 = ~out_wimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2894 = ~out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2895 = ~out_womask_253; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_205 = {hi_452, flags_0_go, _out_prepend_T_205}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2896 = out_prepend_205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2897 = _out_T_2896; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_206 = _out_T_2897; // @[RegisterRouter.scala:87:24] wire out_rimask_254 = \|_out_rimask_T_254; // @[RegisterRouter.scala:87:24] wire out_wimask_254 = &_out_wimask_T_254; // @[RegisterRouter.scala:87:24] wire out_romask_254 = \|_out_romask_T_254; // @[RegisterRouter.scala:87:24] wire out_womask_254 = &_out_womask_T_254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_254 = out_rivalid_1_108 & out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2899 = out_f_rivalid_254; // @[RegisterRouter.scala:87:24] wire out_f_roready_254 = out_roready_1_108 & out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2900 = out_f_roready_254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_254 = out_wivalid_1_108 & out_wimask_254; // @[RegisterRouter.scala:87:24] wire out_f_woready_254 = out_woready_1_108 & out_womask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2901 = ~out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2902 = ~out_wimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2903 = ~out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2904 = ~out_womask_254; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_206 = {hi_453, flags_0_go, _out_prepend_T_206}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2905 = out_prepend_206; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2906 = _out_T_2905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_207 = _out_T_2906; // @[RegisterRouter.scala:87:24] wire out_rimask_255 = \|_out_rimask_T_255; // @[RegisterRouter.scala:87:24] wire out_wimask_255 = &_out_wimask_T_255; // @[RegisterRouter.scala:87:24] wire out_romask_255 = \|_out_romask_T_255; // @[RegisterRouter.scala:87:24] wire out_womask_255 = &_out_womask_T_255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_255 = out_rivalid_1_109 & out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2908 = out_f_rivalid_255; // @[RegisterRouter.scala:87:24] wire out_f_roready_255 = out_roready_1_109 & out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2909 = out_f_roready_255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_255 = out_wivalid_1_109 & out_wimask_255; // @[RegisterRouter.scala:87:24] wire out_f_woready_255 = out_woready_1_109 & out_womask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2910 = ~out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2911 = ~out_wimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2912 = ~out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2913 = ~out_womask_255; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_207 = {hi_454, flags_0_go, _out_prepend_T_207}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2914 = out_prepend_207; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2915 = _out_T_2914; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_208 = _out_T_2915; // @[RegisterRouter.scala:87:24] wire out_rimask_256 = \|_out_rimask_T_256; // @[RegisterRouter.scala:87:24] wire out_wimask_256 = &_out_wimask_T_256; // @[RegisterRouter.scala:87:24] wire out_romask_256 = \|_out_romask_T_256; // @[RegisterRouter.scala:87:24] wire out_womask_256 = &_out_womask_T_256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_256 = out_rivalid_1_110 & out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2917 = out_f_rivalid_256; // @[RegisterRouter.scala:87:24] wire out_f_roready_256 = out_roready_1_110 & out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2918 = out_f_roready_256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_256 = out_wivalid_1_110 & out_wimask_256; // @[RegisterRouter.scala:87:24] wire out_f_woready_256 = out_woready_1_110 & out_womask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2919 = ~out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2920 = ~out_wimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2921 = ~out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2922 = ~out_womask_256; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_208 = {hi_455, flags_0_go, _out_prepend_T_208}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2923 = out_prepend_208; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2924 = _out_T_2923; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_209 = _out_T_2924; // @[RegisterRouter.scala:87:24] wire out_rimask_257 = \|_out_rimask_T_257; // @[RegisterRouter.scala:87:24] wire out_wimask_257 = &_out_wimask_T_257; // @[RegisterRouter.scala:87:24] wire out_romask_257 = \|_out_romask_T_257; // @[RegisterRouter.scala:87:24] wire out_womask_257 = &_out_womask_T_257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_257 = out_rivalid_1_111 & out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2926 = out_f_rivalid_257; // @[RegisterRouter.scala:87:24] wire out_f_roready_257 = out_roready_1_111 & out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2927 = out_f_roready_257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_257 = out_wivalid_1_111 & out_wimask_257; // @[RegisterRouter.scala:87:24] wire out_f_woready_257 = out_woready_1_111 & out_womask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2928 = ~out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2929 = ~out_wimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2930 = ~out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2931 = ~out_womask_257; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_209 = {hi_456, flags_0_go, _out_prepend_T_209}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2932 = out_prepend_209; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2933 = _out_T_2932; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_184 = _out_T_2933; // @[MuxLiteral.scala:49:48] wire out_rimask_258 = \|_out_rimask_T_258; // @[RegisterRouter.scala:87:24] wire out_wimask_258 = &_out_wimask_T_258; // @[RegisterRouter.scala:87:24] wire out_romask_258 = \|_out_romask_T_258; // @[RegisterRouter.scala:87:24] wire out_womask_258 = &_out_womask_T_258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_258 = out_rivalid_1_112 & out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2935 = out_f_rivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_roready_258 = out_roready_1_112 & out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2936 = out_f_roready_258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_258 = out_wivalid_1_112 & out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2937 = out_f_wivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_woready_258 = out_woready_1_112 & out_womask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2938 = out_f_woready_258; // @[RegisterRouter.scala:87:24] wire _out_T_2939 = ~out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2940 = ~out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2941 = ~out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2942 = ~out_womask_258; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2944 = _out_T_2943; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_210 = _out_T_2944; // @[RegisterRouter.scala:87:24] wire out_rimask_259 = \|_out_rimask_T_259; // @[RegisterRouter.scala:87:24] wire out_wimask_259 = &_out_wimask_T_259; // @[RegisterRouter.scala:87:24] wire out_romask_259 = \|_out_romask_T_259; // @[RegisterRouter.scala:87:24] wire out_womask_259 = &_out_womask_T_259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_259 = out_rivalid_1_113 & out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2946 = out_f_rivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_roready_259 = out_roready_1_113 & out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2947 = out_f_roready_259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_259 = out_wivalid_1_113 & out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2948 = out_f_wivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_woready_259 = out_woready_1_113 & out_womask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2949 = out_f_woready_259; // @[RegisterRouter.scala:87:24] wire _out_T_2950 = ~out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2951 = ~out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2952 = ~out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2953 = ~out_womask_259; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_210 = {programBufferMem_49, _out_prepend_T_210}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2954 = out_prepend_210; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2955 = _out_T_2954; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_211 = _out_T_2955; // @[RegisterRouter.scala:87:24] wire out_rimask_260 = \|_out_rimask_T_260; // @[RegisterRouter.scala:87:24] wire out_wimask_260 = &_out_wimask_T_260; // @[RegisterRouter.scala:87:24] wire out_romask_260 = \|_out_romask_T_260; // @[RegisterRouter.scala:87:24] wire out_womask_260 = &_out_womask_T_260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_260 = out_rivalid_1_114 & out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2957 = out_f_rivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_roready_260 = out_roready_1_114 & out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2958 = out_f_roready_260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_260 = out_wivalid_1_114 & out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2959 = out_f_wivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_woready_260 = out_woready_1_114 & out_womask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2960 = out_f_woready_260; // @[RegisterRouter.scala:87:24] wire _out_T_2961 = ~out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2962 = ~out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2963 = ~out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2964 = ~out_womask_260; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_211 = {programBufferMem_50, _out_prepend_T_211}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2965 = out_prepend_211; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2966 = _out_T_2965; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_212 = _out_T_2966; // @[RegisterRouter.scala:87:24] wire out_rimask_261 = \|_out_rimask_T_261; // @[RegisterRouter.scala:87:24] wire out_wimask_261 = &_out_wimask_T_261; // @[RegisterRouter.scala:87:24] wire out_romask_261 = \|_out_romask_T_261; // @[RegisterRouter.scala:87:24] wire out_womask_261 = &_out_womask_T_261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_261 = out_rivalid_1_115 & out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2968 = out_f_rivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_roready_261 = out_roready_1_115 & out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2969 = out_f_roready_261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_261 = out_wivalid_1_115 & out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2970 = out_f_wivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_woready_261 = out_woready_1_115 & out_womask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2971 = out_f_woready_261; // @[RegisterRouter.scala:87:24] wire _out_T_2972 = ~out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2973 = ~out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2974 = ~out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2975 = ~out_womask_261; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_212 = {programBufferMem_51, _out_prepend_T_212}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2976 = out_prepend_212; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2977 = _out_T_2976; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_213 = _out_T_2977; // @[RegisterRouter.scala:87:24] wire out_rimask_262 = \|_out_rimask_T_262; // @[RegisterRouter.scala:87:24] wire out_wimask_262 = &_out_wimask_T_262; // @[RegisterRouter.scala:87:24] wire out_romask_262 = \|_out_romask_T_262; // @[RegisterRouter.scala:87:24] wire out_womask_262 = &_out_womask_T_262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_262 = out_rivalid_1_116 & out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2979 = out_f_rivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_roready_262 = out_roready_1_116 & out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2980 = out_f_roready_262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_262 = out_wivalid_1_116 & out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2981 = out_f_wivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_woready_262 = out_woready_1_116 & out_womask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2982 = out_f_woready_262; // @[RegisterRouter.scala:87:24] wire _out_T_2983 = ~out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2984 = ~out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2985 = ~out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2986 = ~out_womask_262; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_213 = {programBufferMem_52, _out_prepend_T_213}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2987 = out_prepend_213; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2988 = _out_T_2987; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_214 = _out_T_2988; // @[RegisterRouter.scala:87:24] wire out_rimask_263 = \|_out_rimask_T_263; // @[RegisterRouter.scala:87:24] wire out_wimask_263 = &_out_wimask_T_263; // @[RegisterRouter.scala:87:24] wire out_romask_263 = \|_out_romask_T_263; // @[RegisterRouter.scala:87:24] wire out_womask_263 = &_out_womask_T_263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_263 = out_rivalid_1_117 & out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2990 = out_f_rivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_roready_263 = out_roready_1_117 & out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2991 = out_f_roready_263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_263 = out_wivalid_1_117 & out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2992 = out_f_wivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_woready_263 = out_woready_1_117 & out_womask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2993 = out_f_woready_263; // @[RegisterRouter.scala:87:24] wire _out_T_2994 = ~out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2995 = ~out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2996 = ~out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2997 = ~out_womask_263; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_214 = {programBufferMem_53, _out_prepend_T_214}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2998 = out_prepend_214; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2999 = _out_T_2998; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_215 = _out_T_2999; // @[RegisterRouter.scala:87:24] wire out_rimask_264 = \|_out_rimask_T_264; // @[RegisterRouter.scala:87:24] wire out_wimask_264 = &_out_wimask_T_264; // @[RegisterRouter.scala:87:24] wire out_romask_264 = \|_out_romask_T_264; // @[RegisterRouter.scala:87:24] wire out_womask_264 = &_out_womask_T_264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_264 = out_rivalid_1_118 & out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3001 = out_f_rivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_roready_264 = out_roready_1_118 & out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3002 = out_f_roready_264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_264 = out_wivalid_1_118 & out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3003 = out_f_wivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_woready_264 = out_woready_1_118 & out_womask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3004 = out_f_woready_264; // @[RegisterRouter.scala:87:24] wire _out_T_3005 = ~out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3006 = ~out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3007 = ~out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3008 = ~out_womask_264; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_215 = {programBufferMem_54, _out_prepend_T_215}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3009 = out_prepend_215; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3010 = _out_T_3009; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_216 = _out_T_3010; // @[RegisterRouter.scala:87:24] wire out_rimask_265 = \|_out_rimask_T_265; // @[RegisterRouter.scala:87:24] wire out_wimask_265 = &_out_wimask_T_265; // @[RegisterRouter.scala:87:24] wire out_romask_265 = \|_out_romask_T_265; // @[RegisterRouter.scala:87:24] wire out_womask_265 = &_out_womask_T_265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_265 = out_rivalid_1_119 & out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3012 = out_f_rivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_roready_265 = out_roready_1_119 & out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3013 = out_f_roready_265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_265 = out_wivalid_1_119 & out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3014 = out_f_wivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_woready_265 = out_woready_1_119 & out_womask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3015 = out_f_woready_265; // @[RegisterRouter.scala:87:24] wire _out_T_3016 = ~out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3017 = ~out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3018 = ~out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3019 = ~out_womask_265; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_216 = {programBufferMem_55, _out_prepend_T_216}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3020 = out_prepend_216; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3021 = _out_T_3020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_110 = _out_T_3021; // @[MuxLiteral.scala:49:48] wire out_rimask_266 = \|_out_rimask_T_266; // @[RegisterRouter.scala:87:24] wire out_wimask_266 = &_out_wimask_T_266; // @[RegisterRouter.scala:87:24] wire out_romask_266 = \|_out_romask_T_266; // @[RegisterRouter.scala:87:24] wire out_womask_266 = &_out_womask_T_266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_266 = out_rivalid_1_120 & out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3023 = out_f_rivalid_266; // @[RegisterRouter.scala:87:24] wire out_f_roready_266 = out_roready_1_120 & out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3024 = out_f_roready_266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_266 = out_wivalid_1_120 & out_wimask_266; // @[RegisterRouter.scala:87:24] wire out_f_woready_266 = out_woready_1_120 & out_womask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3025 = ~out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3026 = ~out_wimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3027 = ~out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3028 = ~out_womask_266; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3030 = _out_T_3029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_217 = _out_T_3030; // @[RegisterRouter.scala:87:24] wire out_rimask_267 = \|_out_rimask_T_267; // @[RegisterRouter.scala:87:24] wire out_wimask_267 = &_out_wimask_T_267; // @[RegisterRouter.scala:87:24] wire out_romask_267 = \|_out_romask_T_267; // @[RegisterRouter.scala:87:24] wire out_womask_267 = &_out_womask_T_267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_267 = out_rivalid_1_121 & out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3032 = out_f_rivalid_267; // @[RegisterRouter.scala:87:24] wire out_f_roready_267 = out_roready_1_121 & out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3033 = out_f_roready_267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_267 = out_wivalid_1_121 & out_wimask_267; // @[RegisterRouter.scala:87:24] wire out_f_woready_267 = out_woready_1_121 & out_womask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3034 = ~out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3035 = ~out_wimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3036 = ~out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3037 = ~out_womask_267; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_217 = {hi_546, flags_0_go, _out_prepend_T_217}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3038 = out_prepend_217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3039 = _out_T_3038; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_218 = _out_T_3039; // @[RegisterRouter.scala:87:24] wire out_rimask_268 = \|_out_rimask_T_268; // @[RegisterRouter.scala:87:24] wire out_wimask_268 = &_out_wimask_T_268; // @[RegisterRouter.scala:87:24] wire out_romask_268 = \|_out_romask_T_268; // @[RegisterRouter.scala:87:24] wire out_womask_268 = &_out_womask_T_268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_268 = out_rivalid_1_122 & out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3041 = out_f_rivalid_268; // @[RegisterRouter.scala:87:24] wire out_f_roready_268 = out_roready_1_122 & out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3042 = out_f_roready_268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_268 = out_wivalid_1_122 & out_wimask_268; // @[RegisterRouter.scala:87:24] wire out_f_woready_268 = out_woready_1_122 & out_womask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3043 = ~out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3044 = ~out_wimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3045 = ~out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3046 = ~out_womask_268; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_218 = {hi_547, flags_0_go, _out_prepend_T_218}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3047 = out_prepend_218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3048 = _out_T_3047; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_219 = _out_T_3048; // @[RegisterRouter.scala:87:24] wire out_rimask_269 = \|_out_rimask_T_269; // @[RegisterRouter.scala:87:24] wire out_wimask_269 = &_out_wimask_T_269; // @[RegisterRouter.scala:87:24] wire out_romask_269 = \|_out_romask_T_269; // @[RegisterRouter.scala:87:24] wire out_womask_269 = &_out_womask_T_269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_269 = out_rivalid_1_123 & out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3050 = out_f_rivalid_269; // @[RegisterRouter.scala:87:24] wire out_f_roready_269 = out_roready_1_123 & out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3051 = out_f_roready_269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_269 = out_wivalid_1_123 & out_wimask_269; // @[RegisterRouter.scala:87:24] wire out_f_woready_269 = out_woready_1_123 & out_womask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3052 = ~out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3053 = ~out_wimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3054 = ~out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3055 = ~out_womask_269; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_219 = {hi_548, flags_0_go, _out_prepend_T_219}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3056 = out_prepend_219; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3057 = _out_T_3056; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_220 = _out_T_3057; // @[RegisterRouter.scala:87:24] wire out_rimask_270 = \|_out_rimask_T_270; // @[RegisterRouter.scala:87:24] wire out_wimask_270 = &_out_wimask_T_270; // @[RegisterRouter.scala:87:24] wire out_romask_270 = \|_out_romask_T_270; // @[RegisterRouter.scala:87:24] wire out_womask_270 = &_out_womask_T_270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_270 = out_rivalid_1_124 & out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3059 = out_f_rivalid_270; // @[RegisterRouter.scala:87:24] wire out_f_roready_270 = out_roready_1_124 & out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3060 = out_f_roready_270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_270 = out_wivalid_1_124 & out_wimask_270; // @[RegisterRouter.scala:87:24] wire out_f_woready_270 = out_woready_1_124 & out_womask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3061 = ~out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3062 = ~out_wimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3063 = ~out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3064 = ~out_womask_270; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_220 = {hi_549, flags_0_go, _out_prepend_T_220}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3065 = out_prepend_220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3066 = _out_T_3065; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_221 = _out_T_3066; // @[RegisterRouter.scala:87:24] wire out_rimask_271 = \|_out_rimask_T_271; // @[RegisterRouter.scala:87:24] wire out_wimask_271 = &_out_wimask_T_271; // @[RegisterRouter.scala:87:24] wire out_romask_271 = \|_out_romask_T_271; // @[RegisterRouter.scala:87:24] wire out_womask_271 = &_out_womask_T_271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_271 = out_rivalid_1_125 & out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3068 = out_f_rivalid_271; // @[RegisterRouter.scala:87:24] wire out_f_roready_271 = out_roready_1_125 & out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3069 = out_f_roready_271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_271 = out_wivalid_1_125 & out_wimask_271; // @[RegisterRouter.scala:87:24] wire out_f_woready_271 = out_woready_1_125 & out_womask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3070 = ~out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3071 = ~out_wimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3072 = ~out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3073 = ~out_womask_271; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_221 = {hi_550, flags_0_go, _out_prepend_T_221}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3074 = out_prepend_221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3075 = _out_T_3074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_222 = _out_T_3075; // @[RegisterRouter.scala:87:24] wire out_rimask_272 = \|_out_rimask_T_272; // @[RegisterRouter.scala:87:24] wire out_wimask_272 = &_out_wimask_T_272; // @[RegisterRouter.scala:87:24] wire out_romask_272 = \|_out_romask_T_272; // @[RegisterRouter.scala:87:24] wire out_womask_272 = &_out_womask_T_272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_272 = out_rivalid_1_126 & out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3077 = out_f_rivalid_272; // @[RegisterRouter.scala:87:24] wire out_f_roready_272 = out_roready_1_126 & out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3078 = out_f_roready_272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_272 = out_wivalid_1_126 & out_wimask_272; // @[RegisterRouter.scala:87:24] wire out_f_woready_272 = out_woready_1_126 & out_womask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3079 = ~out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3080 = ~out_wimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3081 = ~out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3082 = ~out_womask_272; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_222 = {hi_551, flags_0_go, _out_prepend_T_222}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3083 = out_prepend_222; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3084 = _out_T_3083; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_223 = _out_T_3084; // @[RegisterRouter.scala:87:24] wire out_rimask_273 = \|_out_rimask_T_273; // @[RegisterRouter.scala:87:24] wire out_wimask_273 = &_out_wimask_T_273; // @[RegisterRouter.scala:87:24] wire out_romask_273 = \|_out_romask_T_273; // @[RegisterRouter.scala:87:24] wire out_womask_273 = &_out_womask_T_273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_273 = out_rivalid_1_127 & out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3086 = out_f_rivalid_273; // @[RegisterRouter.scala:87:24] wire out_f_roready_273 = out_roready_1_127 & out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3087 = out_f_roready_273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_273 = out_wivalid_1_127 & out_wimask_273; // @[RegisterRouter.scala:87:24] wire out_f_woready_273 = out_woready_1_127 & out_womask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3088 = ~out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3089 = ~out_wimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3090 = ~out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3091 = ~out_womask_273; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_223 = {hi_552, flags_0_go, _out_prepend_T_223}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3092 = out_prepend_223; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3093 = _out_T_3092; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_196 = _out_T_3093; // @[MuxLiteral.scala:49:48] wire out_rimask_274 = \|_out_rimask_T_274; // @[RegisterRouter.scala:87:24] wire out_wimask_274 = &_out_wimask_T_274; // @[RegisterRouter.scala:87:24] wire out_romask_274 = \|_out_romask_T_274; // @[RegisterRouter.scala:87:24] wire out_womask_274 = &_out_womask_T_274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_274 = out_rivalid_1_128 & out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3095 = out_f_rivalid_274; // @[RegisterRouter.scala:87:24] wire out_f_roready_274 = out_roready_1_128 & out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3096 = out_f_roready_274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_274 = out_wivalid_1_128 & out_wimask_274; // @[RegisterRouter.scala:87:24] wire out_f_woready_274 = out_woready_1_128 & out_womask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3097 = ~out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3098 = ~out_wimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3099 = ~out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3100 = ~out_womask_274; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3102 = _out_T_3101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_224 = _out_T_3102; // @[RegisterRouter.scala:87:24] wire out_rimask_275 = \|_out_rimask_T_275; // @[RegisterRouter.scala:87:24] wire out_wimask_275 = &_out_wimask_T_275; // @[RegisterRouter.scala:87:24] wire out_romask_275 = \|_out_romask_T_275; // @[RegisterRouter.scala:87:24] wire out_womask_275 = &_out_womask_T_275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_275 = out_rivalid_1_129 & out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3104 = out_f_rivalid_275; // @[RegisterRouter.scala:87:24] wire out_f_roready_275 = out_roready_1_129 & out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3105 = out_f_roready_275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_275 = out_wivalid_1_129 & out_wimask_275; // @[RegisterRouter.scala:87:24] wire out_f_woready_275 = out_woready_1_129 & out_womask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3106 = ~out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3107 = ~out_wimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3108 = ~out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3109 = ~out_womask_275; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_224 = {hi_234, flags_0_go, _out_prepend_T_224}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3110 = out_prepend_224; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3111 = _out_T_3110; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_225 = _out_T_3111; // @[RegisterRouter.scala:87:24] wire out_rimask_276 = \|_out_rimask_T_276; // @[RegisterRouter.scala:87:24] wire out_wimask_276 = &_out_wimask_T_276; // @[RegisterRouter.scala:87:24] wire out_romask_276 = \|_out_romask_T_276; // @[RegisterRouter.scala:87:24] wire out_womask_276 = &_out_womask_T_276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_276 = out_rivalid_1_130 & out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3113 = out_f_rivalid_276; // @[RegisterRouter.scala:87:24] wire out_f_roready_276 = out_roready_1_130 & out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3114 = out_f_roready_276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_276 = out_wivalid_1_130 & out_wimask_276; // @[RegisterRouter.scala:87:24] wire out_f_woready_276 = out_woready_1_130 & out_womask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3115 = ~out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3116 = ~out_wimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3117 = ~out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3118 = ~out_womask_276; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_225 = {hi_235, flags_0_go, _out_prepend_T_225}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3119 = out_prepend_225; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3120 = _out_T_3119; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_226 = _out_T_3120; // @[RegisterRouter.scala:87:24] wire out_rimask_277 = \|_out_rimask_T_277; // @[RegisterRouter.scala:87:24] wire out_wimask_277 = &_out_wimask_T_277; // @[RegisterRouter.scala:87:24] wire out_romask_277 = \|_out_romask_T_277; // @[RegisterRouter.scala:87:24] wire out_womask_277 = &_out_womask_T_277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_277 = out_rivalid_1_131 & out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3122 = out_f_rivalid_277; // @[RegisterRouter.scala:87:24] wire out_f_roready_277 = out_roready_1_131 & out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3123 = out_f_roready_277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_277 = out_wivalid_1_131 & out_wimask_277; // @[RegisterRouter.scala:87:24] wire out_f_woready_277 = out_woready_1_131 & out_womask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3124 = ~out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3125 = ~out_wimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3126 = ~out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3127 = ~out_womask_277; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_226 = {hi_236, flags_0_go, _out_prepend_T_226}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3128 = out_prepend_226; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3129 = _out_T_3128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_227 = _out_T_3129; // @[RegisterRouter.scala:87:24] wire out_rimask_278 = \|_out_rimask_T_278; // @[RegisterRouter.scala:87:24] wire out_wimask_278 = &_out_wimask_T_278; // @[RegisterRouter.scala:87:24] wire out_romask_278 = \|_out_romask_T_278; // @[RegisterRouter.scala:87:24] wire out_womask_278 = &_out_womask_T_278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_278 = out_rivalid_1_132 & out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3131 = out_f_rivalid_278; // @[RegisterRouter.scala:87:24] wire out_f_roready_278 = out_roready_1_132 & out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3132 = out_f_roready_278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_278 = out_wivalid_1_132 & out_wimask_278; // @[RegisterRouter.scala:87:24] wire out_f_woready_278 = out_woready_1_132 & out_womask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3133 = ~out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3134 = ~out_wimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3135 = ~out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3136 = ~out_womask_278; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_227 = {hi_237, flags_0_go, _out_prepend_T_227}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3137 = out_prepend_227; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3138 = _out_T_3137; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_228 = _out_T_3138; // @[RegisterRouter.scala:87:24] wire out_rimask_279 = \|_out_rimask_T_279; // @[RegisterRouter.scala:87:24] wire out_wimask_279 = &_out_wimask_T_279; // @[RegisterRouter.scala:87:24] wire out_romask_279 = \|_out_romask_T_279; // @[RegisterRouter.scala:87:24] wire out_womask_279 = &_out_womask_T_279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_279 = out_rivalid_1_133 & out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3140 = out_f_rivalid_279; // @[RegisterRouter.scala:87:24] wire out_f_roready_279 = out_roready_1_133 & out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3141 = out_f_roready_279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_279 = out_wivalid_1_133 & out_wimask_279; // @[RegisterRouter.scala:87:24] wire out_f_woready_279 = out_woready_1_133 & out_womask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3142 = ~out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3143 = ~out_wimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3144 = ~out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3145 = ~out_womask_279; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_228 = {hi_238, flags_0_go, _out_prepend_T_228}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3146 = out_prepend_228; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3147 = _out_T_3146; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_229 = _out_T_3147; // @[RegisterRouter.scala:87:24] wire out_rimask_280 = \|_out_rimask_T_280; // @[RegisterRouter.scala:87:24] wire out_wimask_280 = &_out_wimask_T_280; // @[RegisterRouter.scala:87:24] wire out_romask_280 = \|_out_romask_T_280; // @[RegisterRouter.scala:87:24] wire out_womask_280 = &_out_womask_T_280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_280 = out_rivalid_1_134 & out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3149 = out_f_rivalid_280; // @[RegisterRouter.scala:87:24] wire out_f_roready_280 = out_roready_1_134 & out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3150 = out_f_roready_280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_280 = out_wivalid_1_134 & out_wimask_280; // @[RegisterRouter.scala:87:24] wire out_f_woready_280 = out_woready_1_134 & out_womask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3151 = ~out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3152 = ~out_wimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3153 = ~out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3154 = ~out_womask_280; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_229 = {hi_239, flags_0_go, _out_prepend_T_229}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3155 = out_prepend_229; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3156 = _out_T_3155; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_230 = _out_T_3156; // @[RegisterRouter.scala:87:24] wire out_rimask_281 = \|_out_rimask_T_281; // @[RegisterRouter.scala:87:24] wire out_wimask_281 = &_out_wimask_T_281; // @[RegisterRouter.scala:87:24] wire out_romask_281 = \|_out_romask_T_281; // @[RegisterRouter.scala:87:24] wire out_womask_281 = &_out_womask_T_281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_281 = out_rivalid_1_135 & out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3158 = out_f_rivalid_281; // @[RegisterRouter.scala:87:24] wire out_f_roready_281 = out_roready_1_135 & out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3159 = out_f_roready_281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_281 = out_wivalid_1_135 & out_wimask_281; // @[RegisterRouter.scala:87:24] wire out_f_woready_281 = out_woready_1_135 & out_womask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3160 = ~out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3161 = ~out_wimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3162 = ~out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3163 = ~out_womask_281; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_230 = {hi_240, flags_0_go, _out_prepend_T_230}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3164 = out_prepend_230; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3165 = _out_T_3164; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_157 = _out_T_3165; // @[MuxLiteral.scala:49:48] wire out_rimask_282 = \|_out_rimask_T_282; // @[RegisterRouter.scala:87:24] wire out_wimask_282 = &_out_wimask_T_282; // @[RegisterRouter.scala:87:24] wire out_romask_282 = \|_out_romask_T_282; // @[RegisterRouter.scala:87:24] wire out_womask_282 = &_out_womask_T_282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_282 = out_rivalid_1_136 & out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3167 = out_f_rivalid_282; // @[RegisterRouter.scala:87:24] wire out_f_roready_282 = out_roready_1_136 & out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3168 = out_f_roready_282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_282 = out_wivalid_1_136 & out_wimask_282; // @[RegisterRouter.scala:87:24] wire out_f_woready_282 = out_woready_1_136 & out_womask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3169 = ~out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3170 = ~out_wimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3171 = ~out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3172 = ~out_womask_282; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3174 = _out_T_3173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_231 = _out_T_3174; // @[RegisterRouter.scala:87:24] wire out_rimask_283 = \|_out_rimask_T_283; // @[RegisterRouter.scala:87:24] wire out_wimask_283 = &_out_wimask_T_283; // @[RegisterRouter.scala:87:24] wire out_romask_283 = \|_out_romask_T_283; // @[RegisterRouter.scala:87:24] wire out_womask_283 = &_out_womask_T_283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_283 = out_rivalid_1_137 & out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3176 = out_f_rivalid_283; // @[RegisterRouter.scala:87:24] wire out_f_roready_283 = out_roready_1_137 & out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3177 = out_f_roready_283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_283 = out_wivalid_1_137 & out_wimask_283; // @[RegisterRouter.scala:87:24] wire out_f_woready_283 = out_woready_1_137 & out_womask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3178 = ~out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3179 = ~out_wimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3180 = ~out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3181 = ~out_womask_283; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_231 = {hi_490, flags_0_go, _out_prepend_T_231}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3182 = out_prepend_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3183 = _out_T_3182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_232 = _out_T_3183; // @[RegisterRouter.scala:87:24] wire out_rimask_284 = \|_out_rimask_T_284; // @[RegisterRouter.scala:87:24] wire out_wimask_284 = &_out_wimask_T_284; // @[RegisterRouter.scala:87:24] wire out_romask_284 = \|_out_romask_T_284; // @[RegisterRouter.scala:87:24] wire out_womask_284 = &_out_womask_T_284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_284 = out_rivalid_1_138 & out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3185 = out_f_rivalid_284; // @[RegisterRouter.scala:87:24] wire out_f_roready_284 = out_roready_1_138 & out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3186 = out_f_roready_284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_284 = out_wivalid_1_138 & out_wimask_284; // @[RegisterRouter.scala:87:24] wire out_f_woready_284 = out_woready_1_138 & out_womask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3187 = ~out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3188 = ~out_wimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3189 = ~out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3190 = ~out_womask_284; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_232 = {hi_491, flags_0_go, _out_prepend_T_232}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3191 = out_prepend_232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3192 = _out_T_3191; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_233 = _out_T_3192; // @[RegisterRouter.scala:87:24] wire out_rimask_285 = \|_out_rimask_T_285; // @[RegisterRouter.scala:87:24] wire out_wimask_285 = &_out_wimask_T_285; // @[RegisterRouter.scala:87:24] wire out_romask_285 = \|_out_romask_T_285; // @[RegisterRouter.scala:87:24] wire out_womask_285 = &_out_womask_T_285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_285 = out_rivalid_1_139 & out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3194 = out_f_rivalid_285; // @[RegisterRouter.scala:87:24] wire out_f_roready_285 = out_roready_1_139 & out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3195 = out_f_roready_285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_285 = out_wivalid_1_139 & out_wimask_285; // @[RegisterRouter.scala:87:24] wire out_f_woready_285 = out_woready_1_139 & out_womask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3196 = ~out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3197 = ~out_wimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3198 = ~out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3199 = ~out_womask_285; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_233 = {hi_492, flags_0_go, _out_prepend_T_233}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3200 = out_prepend_233; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3201 = _out_T_3200; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_234 = _out_T_3201; // @[RegisterRouter.scala:87:24] wire out_rimask_286 = \|_out_rimask_T_286; // @[RegisterRouter.scala:87:24] wire out_wimask_286 = &_out_wimask_T_286; // @[RegisterRouter.scala:87:24] wire out_romask_286 = \|_out_romask_T_286; // @[RegisterRouter.scala:87:24] wire out_womask_286 = &_out_womask_T_286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_286 = out_rivalid_1_140 & out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3203 = out_f_rivalid_286; // @[RegisterRouter.scala:87:24] wire out_f_roready_286 = out_roready_1_140 & out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3204 = out_f_roready_286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_286 = out_wivalid_1_140 & out_wimask_286; // @[RegisterRouter.scala:87:24] wire out_f_woready_286 = out_woready_1_140 & out_womask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3205 = ~out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3206 = ~out_wimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3207 = ~out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3208 = ~out_womask_286; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_234 = {hi_493, flags_0_go, _out_prepend_T_234}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3209 = out_prepend_234; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3210 = _out_T_3209; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_235 = _out_T_3210; // @[RegisterRouter.scala:87:24] wire out_rimask_287 = \|_out_rimask_T_287; // @[RegisterRouter.scala:87:24] wire out_wimask_287 = &_out_wimask_T_287; // @[RegisterRouter.scala:87:24] wire out_romask_287 = \|_out_romask_T_287; // @[RegisterRouter.scala:87:24] wire out_womask_287 = &_out_womask_T_287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_287 = out_rivalid_1_141 & out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3212 = out_f_rivalid_287; // @[RegisterRouter.scala:87:24] wire out_f_roready_287 = out_roready_1_141 & out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3213 = out_f_roready_287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_287 = out_wivalid_1_141 & out_wimask_287; // @[RegisterRouter.scala:87:24] wire out_f_woready_287 = out_woready_1_141 & out_womask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3214 = ~out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3215 = ~out_wimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3216 = ~out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3217 = ~out_womask_287; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_235 = {hi_494, flags_0_go, _out_prepend_T_235}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3218 = out_prepend_235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3219 = _out_T_3218; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_236 = _out_T_3219; // @[RegisterRouter.scala:87:24] wire out_rimask_288 = \|_out_rimask_T_288; // @[RegisterRouter.scala:87:24] wire out_wimask_288 = &_out_wimask_T_288; // @[RegisterRouter.scala:87:24] wire out_romask_288 = \|_out_romask_T_288; // @[RegisterRouter.scala:87:24] wire out_womask_288 = &_out_womask_T_288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_288 = out_rivalid_1_142 & out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3221 = out_f_rivalid_288; // @[RegisterRouter.scala:87:24] wire out_f_roready_288 = out_roready_1_142 & out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3222 = out_f_roready_288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_288 = out_wivalid_1_142 & out_wimask_288; // @[RegisterRouter.scala:87:24] wire out_f_woready_288 = out_woready_1_142 & out_womask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3223 = ~out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3224 = ~out_wimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3225 = ~out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3226 = ~out_womask_288; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_236 = {hi_495, flags_0_go, _out_prepend_T_236}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3227 = out_prepend_236; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3228 = _out_T_3227; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_237 = _out_T_3228; // @[RegisterRouter.scala:87:24] wire out_rimask_289 = \|_out_rimask_T_289; // @[RegisterRouter.scala:87:24] wire out_wimask_289 = &_out_wimask_T_289; // @[RegisterRouter.scala:87:24] wire out_romask_289 = \|_out_romask_T_289; // @[RegisterRouter.scala:87:24] wire out_womask_289 = &_out_womask_T_289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_289 = out_rivalid_1_143 & out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3230 = out_f_rivalid_289; // @[RegisterRouter.scala:87:24] wire out_f_roready_289 = out_roready_1_143 & out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3231 = out_f_roready_289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_289 = out_wivalid_1_143 & out_wimask_289; // @[RegisterRouter.scala:87:24] wire out_f_woready_289 = out_woready_1_143 & out_womask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3232 = ~out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3233 = ~out_wimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3234 = ~out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3235 = ~out_womask_289; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_237 = {hi_496, flags_0_go, _out_prepend_T_237}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3236 = out_prepend_237; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3237 = _out_T_3236; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_189 = _out_T_3237; // @[MuxLiteral.scala:49:48] wire out_rimask_290 = \|_out_rimask_T_290; // @[RegisterRouter.scala:87:24] wire out_wimask_290 = &_out_wimask_T_290; // @[RegisterRouter.scala:87:24] wire out_romask_290 = \|_out_romask_T_290; // @[RegisterRouter.scala:87:24] wire out_womask_290 = &_out_womask_T_290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_290 = out_rivalid_1_144 & out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3239 = out_f_rivalid_290; // @[RegisterRouter.scala:87:24] wire out_f_roready_290 = out_roready_1_144 & out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3240 = out_f_roready_290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_290 = out_wivalid_1_144 & out_wimask_290; // @[RegisterRouter.scala:87:24] wire out_f_woready_290 = out_woready_1_144 & out_womask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3241 = ~out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3242 = ~out_wimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3243 = ~out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3244 = ~out_womask_290; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3246 = _out_T_3245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_238 = _out_T_3246; // @[RegisterRouter.scala:87:24] wire out_rimask_291 = \|_out_rimask_T_291; // @[RegisterRouter.scala:87:24] wire out_wimask_291 = &_out_wimask_T_291; // @[RegisterRouter.scala:87:24] wire out_romask_291 = \|_out_romask_T_291; // @[RegisterRouter.scala:87:24] wire out_womask_291 = &_out_womask_T_291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_291 = out_rivalid_1_145 & out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3248 = out_f_rivalid_291; // @[RegisterRouter.scala:87:24] wire out_f_roready_291 = out_roready_1_145 & out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3249 = out_f_roready_291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_291 = out_wivalid_1_145 & out_wimask_291; // @[RegisterRouter.scala:87:24] wire out_f_woready_291 = out_woready_1_145 & out_womask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3250 = ~out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3251 = ~out_wimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3252 = ~out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3253 = ~out_womask_291; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_238 = {hi_194, flags_0_go, _out_prepend_T_238}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3254 = out_prepend_238; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3255 = _out_T_3254; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_239 = _out_T_3255; // @[RegisterRouter.scala:87:24] wire out_rimask_292 = \|_out_rimask_T_292; // @[RegisterRouter.scala:87:24] wire out_wimask_292 = &_out_wimask_T_292; // @[RegisterRouter.scala:87:24] wire out_romask_292 = \|_out_romask_T_292; // @[RegisterRouter.scala:87:24] wire out_womask_292 = &_out_womask_T_292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_292 = out_rivalid_1_146 & out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3257 = out_f_rivalid_292; // @[RegisterRouter.scala:87:24] wire out_f_roready_292 = out_roready_1_146 & out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3258 = out_f_roready_292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_292 = out_wivalid_1_146 & out_wimask_292; // @[RegisterRouter.scala:87:24] wire out_f_woready_292 = out_woready_1_146 & out_womask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3259 = ~out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3260 = ~out_wimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3261 = ~out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3262 = ~out_womask_292; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_239 = {hi_195, flags_0_go, _out_prepend_T_239}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3263 = out_prepend_239; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3264 = _out_T_3263; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_240 = _out_T_3264; // @[RegisterRouter.scala:87:24] wire out_rimask_293 = \|_out_rimask_T_293; // @[RegisterRouter.scala:87:24] wire out_wimask_293 = &_out_wimask_T_293; // @[RegisterRouter.scala:87:24] wire out_romask_293 = \|_out_romask_T_293; // @[RegisterRouter.scala:87:24] wire out_womask_293 = &_out_womask_T_293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_293 = out_rivalid_1_147 & out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3266 = out_f_rivalid_293; // @[RegisterRouter.scala:87:24] wire out_f_roready_293 = out_roready_1_147 & out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3267 = out_f_roready_293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_293 = out_wivalid_1_147 & out_wimask_293; // @[RegisterRouter.scala:87:24] wire out_f_woready_293 = out_woready_1_147 & out_womask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3268 = ~out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3269 = ~out_wimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3270 = ~out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3271 = ~out_womask_293; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_240 = {hi_196, flags_0_go, _out_prepend_T_240}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3272 = out_prepend_240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3273 = _out_T_3272; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_241 = _out_T_3273; // @[RegisterRouter.scala:87:24] wire out_rimask_294 = \|_out_rimask_T_294; // @[RegisterRouter.scala:87:24] wire out_wimask_294 = &_out_wimask_T_294; // @[RegisterRouter.scala:87:24] wire out_romask_294 = \|_out_romask_T_294; // @[RegisterRouter.scala:87:24] wire out_womask_294 = &_out_womask_T_294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_294 = out_rivalid_1_148 & out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3275 = out_f_rivalid_294; // @[RegisterRouter.scala:87:24] wire out_f_roready_294 = out_roready_1_148 & out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3276 = out_f_roready_294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_294 = out_wivalid_1_148 & out_wimask_294; // @[RegisterRouter.scala:87:24] wire out_f_woready_294 = out_woready_1_148 & out_womask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3277 = ~out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3278 = ~out_wimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3279 = ~out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3280 = ~out_womask_294; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_241 = {hi_197, flags_0_go, _out_prepend_T_241}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3281 = out_prepend_241; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3282 = _out_T_3281; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_242 = _out_T_3282; // @[RegisterRouter.scala:87:24] wire out_rimask_295 = \|_out_rimask_T_295; // @[RegisterRouter.scala:87:24] wire out_wimask_295 = &_out_wimask_T_295; // @[RegisterRouter.scala:87:24] wire out_romask_295 = \|_out_romask_T_295; // @[RegisterRouter.scala:87:24] wire out_womask_295 = &_out_womask_T_295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_295 = out_rivalid_1_149 & out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3284 = out_f_rivalid_295; // @[RegisterRouter.scala:87:24] wire out_f_roready_295 = out_roready_1_149 & out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3285 = out_f_roready_295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_295 = out_wivalid_1_149 & out_wimask_295; // @[RegisterRouter.scala:87:24] wire out_f_woready_295 = out_woready_1_149 & out_womask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3286 = ~out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3287 = ~out_wimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3288 = ~out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3289 = ~out_womask_295; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_242 = {hi_198, flags_0_go, _out_prepend_T_242}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3290 = out_prepend_242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3291 = _out_T_3290; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_243 = _out_T_3291; // @[RegisterRouter.scala:87:24] wire out_rimask_296 = \|_out_rimask_T_296; // @[RegisterRouter.scala:87:24] wire out_wimask_296 = &_out_wimask_T_296; // @[RegisterRouter.scala:87:24] wire out_romask_296 = \|_out_romask_T_296; // @[RegisterRouter.scala:87:24] wire out_womask_296 = &_out_womask_T_296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_296 = out_rivalid_1_150 & out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3293 = out_f_rivalid_296; // @[RegisterRouter.scala:87:24] wire out_f_roready_296 = out_roready_1_150 & out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3294 = out_f_roready_296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_296 = out_wivalid_1_150 & out_wimask_296; // @[RegisterRouter.scala:87:24] wire out_f_woready_296 = out_woready_1_150 & out_womask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3295 = ~out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3296 = ~out_wimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3297 = ~out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3298 = ~out_womask_296; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_243 = {hi_199, flags_0_go, _out_prepend_T_243}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3299 = out_prepend_243; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3300 = _out_T_3299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_244 = _out_T_3300; // @[RegisterRouter.scala:87:24] wire out_rimask_297 = \|_out_rimask_T_297; // @[RegisterRouter.scala:87:24] wire out_wimask_297 = &_out_wimask_T_297; // @[RegisterRouter.scala:87:24] wire out_romask_297 = \|_out_romask_T_297; // @[RegisterRouter.scala:87:24] wire out_womask_297 = &_out_womask_T_297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_297 = out_rivalid_1_151 & out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3302 = out_f_rivalid_297; // @[RegisterRouter.scala:87:24] wire out_f_roready_297 = out_roready_1_151 & out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3303 = out_f_roready_297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_297 = out_wivalid_1_151 & out_wimask_297; // @[RegisterRouter.scala:87:24] wire out_f_woready_297 = out_woready_1_151 & out_womask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3304 = ~out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3305 = ~out_wimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3306 = ~out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3307 = ~out_womask_297; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_244 = {hi_200, flags_0_go, _out_prepend_T_244}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3308 = out_prepend_244; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3309 = _out_T_3308; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_152 = _out_T_3309; // @[MuxLiteral.scala:49:48] wire out_rimask_298 = \|_out_rimask_T_298; // @[RegisterRouter.scala:87:24] wire out_wimask_298 = &_out_wimask_T_298; // @[RegisterRouter.scala:87:24] wire out_romask_298 = \|_out_romask_T_298; // @[RegisterRouter.scala:87:24] wire out_womask_298 = &_out_womask_T_298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_298 = out_rivalid_1_152 & out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3311 = out_f_rivalid_298; // @[RegisterRouter.scala:87:24] wire out_f_roready_298 = out_roready_1_152 & out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3312 = out_f_roready_298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_298 = out_wivalid_1_152 & out_wimask_298; // @[RegisterRouter.scala:87:24] wire out_f_woready_298 = out_woready_1_152 & out_womask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3313 = ~out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3314 = ~out_wimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3315 = ~out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3316 = ~out_womask_298; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3318 = _out_T_3317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_245 = _out_T_3318; // @[RegisterRouter.scala:87:24] wire out_rimask_299 = \|_out_rimask_T_299; // @[RegisterRouter.scala:87:24] wire out_wimask_299 = &_out_wimask_T_299; // @[RegisterRouter.scala:87:24] wire out_romask_299 = \|_out_romask_T_299; // @[RegisterRouter.scala:87:24] wire out_womask_299 = &_out_womask_T_299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_299 = out_rivalid_1_153 & out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3320 = out_f_rivalid_299; // @[RegisterRouter.scala:87:24] wire out_f_roready_299 = out_roready_1_153 & out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3321 = out_f_roready_299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_299 = out_wivalid_1_153 & out_wimask_299; // @[RegisterRouter.scala:87:24] wire out_f_woready_299 = out_woready_1_153 & out_womask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3322 = ~out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3323 = ~out_wimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3324 = ~out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3325 = ~out_womask_299; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_245 = {hi_802, flags_0_go, _out_prepend_T_245}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3326 = out_prepend_245; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3327 = _out_T_3326; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_246 = _out_T_3327; // @[RegisterRouter.scala:87:24] wire out_rimask_300 = \|_out_rimask_T_300; // @[RegisterRouter.scala:87:24] wire out_wimask_300 = &_out_wimask_T_300; // @[RegisterRouter.scala:87:24] wire out_romask_300 = \|_out_romask_T_300; // @[RegisterRouter.scala:87:24] wire out_womask_300 = &_out_womask_T_300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_300 = out_rivalid_1_154 & out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3329 = out_f_rivalid_300; // @[RegisterRouter.scala:87:24] wire out_f_roready_300 = out_roready_1_154 & out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3330 = out_f_roready_300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_300 = out_wivalid_1_154 & out_wimask_300; // @[RegisterRouter.scala:87:24] wire out_f_woready_300 = out_woready_1_154 & out_womask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3331 = ~out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3332 = ~out_wimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3333 = ~out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3334 = ~out_womask_300; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_246 = {hi_803, flags_0_go, _out_prepend_T_246}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3335 = out_prepend_246; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3336 = _out_T_3335; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_247 = _out_T_3336; // @[RegisterRouter.scala:87:24] wire out_rimask_301 = \|_out_rimask_T_301; // @[RegisterRouter.scala:87:24] wire out_wimask_301 = &_out_wimask_T_301; // @[RegisterRouter.scala:87:24] wire out_romask_301 = \|_out_romask_T_301; // @[RegisterRouter.scala:87:24] wire out_womask_301 = &_out_womask_T_301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_301 = out_rivalid_1_155 & out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3338 = out_f_rivalid_301; // @[RegisterRouter.scala:87:24] wire out_f_roready_301 = out_roready_1_155 & out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3339 = out_f_roready_301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_301 = out_wivalid_1_155 & out_wimask_301; // @[RegisterRouter.scala:87:24] wire out_f_woready_301 = out_woready_1_155 & out_womask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3340 = ~out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3341 = ~out_wimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3342 = ~out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3343 = ~out_womask_301; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_247 = {hi_804, flags_0_go, _out_prepend_T_247}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3344 = out_prepend_247; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3345 = _out_T_3344; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_248 = _out_T_3345; // @[RegisterRouter.scala:87:24] wire out_rimask_302 = \|_out_rimask_T_302; // @[RegisterRouter.scala:87:24] wire out_wimask_302 = &_out_wimask_T_302; // @[RegisterRouter.scala:87:24] wire out_romask_302 = \|_out_romask_T_302; // @[RegisterRouter.scala:87:24] wire out_womask_302 = &_out_womask_T_302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_302 = out_rivalid_1_156 & out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3347 = out_f_rivalid_302; // @[RegisterRouter.scala:87:24] wire out_f_roready_302 = out_roready_1_156 & out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3348 = out_f_roready_302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_302 = out_wivalid_1_156 & out_wimask_302; // @[RegisterRouter.scala:87:24] wire out_f_woready_302 = out_woready_1_156 & out_womask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3349 = ~out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3350 = ~out_wimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3351 = ~out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3352 = ~out_womask_302; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_248 = {hi_805, flags_0_go, _out_prepend_T_248}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3353 = out_prepend_248; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3354 = _out_T_3353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_249 = _out_T_3354; // @[RegisterRouter.scala:87:24] wire out_rimask_303 = \|_out_rimask_T_303; // @[RegisterRouter.scala:87:24] wire out_wimask_303 = &_out_wimask_T_303; // @[RegisterRouter.scala:87:24] wire out_romask_303 = \|_out_romask_T_303; // @[RegisterRouter.scala:87:24] wire out_womask_303 = &_out_womask_T_303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_303 = out_rivalid_1_157 & out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3356 = out_f_rivalid_303; // @[RegisterRouter.scala:87:24] wire out_f_roready_303 = out_roready_1_157 & out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3357 = out_f_roready_303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_303 = out_wivalid_1_157 & out_wimask_303; // @[RegisterRouter.scala:87:24] wire out_f_woready_303 = out_woready_1_157 & out_womask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3358 = ~out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3359 = ~out_wimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3360 = ~out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3361 = ~out_womask_303; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_249 = {hi_806, flags_0_go, _out_prepend_T_249}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3362 = out_prepend_249; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3363 = _out_T_3362; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_250 = _out_T_3363; // @[RegisterRouter.scala:87:24] wire out_rimask_304 = \|_out_rimask_T_304; // @[RegisterRouter.scala:87:24] wire out_wimask_304 = &_out_wimask_T_304; // @[RegisterRouter.scala:87:24] wire out_romask_304 = \|_out_romask_T_304; // @[RegisterRouter.scala:87:24] wire out_womask_304 = &_out_womask_T_304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_304 = out_rivalid_1_158 & out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3365 = out_f_rivalid_304; // @[RegisterRouter.scala:87:24] wire out_f_roready_304 = out_roready_1_158 & out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3366 = out_f_roready_304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_304 = out_wivalid_1_158 & out_wimask_304; // @[RegisterRouter.scala:87:24] wire out_f_woready_304 = out_woready_1_158 & out_womask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3367 = ~out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3368 = ~out_wimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3369 = ~out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3370 = ~out_womask_304; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_250 = {hi_807, flags_0_go, _out_prepend_T_250}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3371 = out_prepend_250; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3372 = _out_T_3371; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_251 = _out_T_3372; // @[RegisterRouter.scala:87:24] wire out_rimask_305 = \|_out_rimask_T_305; // @[RegisterRouter.scala:87:24] wire out_wimask_305 = &_out_wimask_T_305; // @[RegisterRouter.scala:87:24] wire out_romask_305 = \|_out_romask_T_305; // @[RegisterRouter.scala:87:24] wire out_womask_305 = &_out_womask_T_305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_305 = out_rivalid_1_159 & out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3374 = out_f_rivalid_305; // @[RegisterRouter.scala:87:24] wire out_f_roready_305 = out_roready_1_159 & out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3375 = out_f_roready_305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_305 = out_wivalid_1_159 & out_wimask_305; // @[RegisterRouter.scala:87:24] wire out_f_woready_305 = out_woready_1_159 & out_womask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3376 = ~out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3377 = ~out_wimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3378 = ~out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3379 = ~out_womask_305; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_251 = {hi_808, flags_0_go, _out_prepend_T_251}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3380 = out_prepend_251; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3381 = _out_T_3380; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_228 = _out_T_3381; // @[MuxLiteral.scala:49:48] wire out_rimask_306 = \|_out_rimask_T_306; // @[RegisterRouter.scala:87:24] wire out_wimask_306 = &_out_wimask_T_306; // @[RegisterRouter.scala:87:24] wire out_romask_306 = \|_out_romask_T_306; // @[RegisterRouter.scala:87:24] wire out_womask_306 = &_out_womask_T_306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_306 = out_rivalid_1_160 & out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3383 = out_f_rivalid_306; // @[RegisterRouter.scala:87:24] wire out_f_roready_306 = out_roready_1_160 & out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3384 = out_f_roready_306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_306 = out_wivalid_1_160 & out_wimask_306; // @[RegisterRouter.scala:87:24] wire out_f_woready_306 = out_woready_1_160 & out_womask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3385 = ~out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3386 = ~out_wimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3387 = ~out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3388 = ~out_womask_306; // @[RegisterRouter.scala:87:24] wire out_rimask_307 = \|_out_rimask_T_307; // @[RegisterRouter.scala:87:24] wire out_wimask_307 = &_out_wimask_T_307; // @[RegisterRouter.scala:87:24] wire out_romask_307 = \|_out_romask_T_307; // @[RegisterRouter.scala:87:24] wire out_womask_307 = &_out_womask_T_307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_307 = out_rivalid_1_161 & out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3392 = out_f_rivalid_307; // @[RegisterRouter.scala:87:24] wire out_f_roready_307 = out_roready_1_161 & out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3393 = out_f_roready_307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_307 = out_wivalid_1_161 & out_wimask_307; // @[RegisterRouter.scala:87:24] wire out_f_woready_307 = out_woready_1_161 & out_womask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3394 = ~out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3395 = ~out_wimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3396 = ~out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3397 = ~out_womask_307; // @[RegisterRouter.scala:87:24] wire out_rimask_308 = \|_out_rimask_T_308; // @[RegisterRouter.scala:87:24] wire out_wimask_308 = &_out_wimask_T_308; // @[RegisterRouter.scala:87:24] wire out_romask_308 = \|_out_romask_T_308; // @[RegisterRouter.scala:87:24] wire out_womask_308 = &_out_womask_T_308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_308 = out_rivalid_1_162 & out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3401 = out_f_rivalid_308; // @[RegisterRouter.scala:87:24] wire out_f_roready_308 = out_roready_1_162 & out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3402 = out_f_roready_308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_308 = out_wivalid_1_162 & out_wimask_308; // @[RegisterRouter.scala:87:24] wire out_f_woready_308 = out_woready_1_162 & out_womask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3403 = ~out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3404 = ~out_wimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3405 = ~out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3406 = ~out_womask_308; // @[RegisterRouter.scala:87:24] wire out_rimask_309 = \|_out_rimask_T_309; // @[RegisterRouter.scala:87:24] wire out_wimask_309 = &_out_wimask_T_309; // @[RegisterRouter.scala:87:24] wire out_romask_309 = \|_out_romask_T_309; // @[RegisterRouter.scala:87:24] wire out_womask_309 = &_out_womask_T_309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_309 = out_rivalid_1_163 & out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3410 = out_f_rivalid_309; // @[RegisterRouter.scala:87:24] wire out_f_roready_309 = out_roready_1_163 & out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3411 = out_f_roready_309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_309 = out_wivalid_1_163 & out_wimask_309; // @[RegisterRouter.scala:87:24] wire out_f_woready_309 = out_woready_1_163 & out_womask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3412 = ~out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3413 = ~out_wimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3414 = ~out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3415 = ~out_womask_309; // @[RegisterRouter.scala:87:24] wire out_rimask_310 = \|_out_rimask_T_310; // @[RegisterRouter.scala:87:24] wire out_wimask_310 = &_out_wimask_T_310; // @[RegisterRouter.scala:87:24] wire out_romask_310 = \|_out_romask_T_310; // @[RegisterRouter.scala:87:24] wire out_womask_310 = &_out_womask_T_310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_310 = out_rivalid_1_164 & out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3419 = out_f_rivalid_310; // @[RegisterRouter.scala:87:24] wire out_f_roready_310 = out_roready_1_164 & out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3420 = out_f_roready_310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_310 = out_wivalid_1_164 & out_wimask_310; // @[RegisterRouter.scala:87:24] wire out_f_woready_310 = out_woready_1_164 & out_womask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3421 = ~out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3422 = ~out_wimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3423 = ~out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3424 = ~out_womask_310; // @[RegisterRouter.scala:87:24] wire out_rimask_311 = \|_out_rimask_T_311; // @[RegisterRouter.scala:87:24] wire out_wimask_311 = &_out_wimask_T_311; // @[RegisterRouter.scala:87:24] wire out_romask_311 = \|_out_romask_T_311; // @[RegisterRouter.scala:87:24] wire out_womask_311 = &_out_womask_T_311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_311 = out_rivalid_1_165 & out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3428 = out_f_rivalid_311; // @[RegisterRouter.scala:87:24] wire out_f_roready_311 = out_roready_1_165 & out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3429 = out_f_roready_311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_311 = out_wivalid_1_165 & out_wimask_311; // @[RegisterRouter.scala:87:24] wire out_f_woready_311 = out_woready_1_165 & out_womask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3430 = ~out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3431 = ~out_wimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3432 = ~out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3433 = ~out_womask_311; // @[RegisterRouter.scala:87:24] wire out_rimask_312 = \|_out_rimask_T_312; // @[RegisterRouter.scala:87:24] wire out_wimask_312 = &_out_wimask_T_312; // @[RegisterRouter.scala:87:24] wire out_romask_312 = \|_out_romask_T_312; // @[RegisterRouter.scala:87:24] wire out_womask_312 = &_out_womask_T_312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_312 = out_rivalid_1_166 & out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3437 = out_f_rivalid_312; // @[RegisterRouter.scala:87:24] wire out_f_roready_312 = out_roready_1_166 & out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3438 = out_f_roready_312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_312 = out_wivalid_1_166 & out_wimask_312; // @[RegisterRouter.scala:87:24] wire out_f_woready_312 = out_woready_1_166 & out_womask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3439 = ~out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3440 = ~out_wimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3441 = ~out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3442 = ~out_womask_312; // @[RegisterRouter.scala:87:24] wire out_rimask_313 = \|_out_rimask_T_313; // @[RegisterRouter.scala:87:24] wire out_wimask_313 = &_out_wimask_T_313; // @[RegisterRouter.scala:87:24] wire out_romask_313 = \|_out_romask_T_313; // @[RegisterRouter.scala:87:24] wire out_womask_313 = &_out_womask_T_313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_313 = out_rivalid_1_167 & out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3446 = out_f_rivalid_313; // @[RegisterRouter.scala:87:24] wire out_f_roready_313 = out_roready_1_167 & out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3447 = out_f_roready_313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_313 = out_wivalid_1_167 & out_wimask_313; // @[RegisterRouter.scala:87:24] wire out_f_woready_313 = out_woready_1_167 & out_womask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3448 = ~out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3449 = ~out_wimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3450 = ~out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3451 = ~out_womask_313; // @[RegisterRouter.scala:87:24] wire out_rimask_314 = \|_out_rimask_T_314; // @[RegisterRouter.scala:87:24] wire out_wimask_314 = &_out_wimask_T_314; // @[RegisterRouter.scala:87:24] wire out_romask_314 = \|_out_romask_T_314; // @[RegisterRouter.scala:87:24] wire out_womask_314 = &_out_womask_T_314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_314 = out_rivalid_1_168 & out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3455 = out_f_rivalid_314; // @[RegisterRouter.scala:87:24] wire out_f_roready_314 = out_roready_1_168 & out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3456 = out_f_roready_314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_314 = out_wivalid_1_168 & out_wimask_314; // @[RegisterRouter.scala:87:24] wire out_f_woready_314 = out_woready_1_168 & out_womask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3457 = ~out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3458 = ~out_wimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3459 = ~out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3460 = ~out_womask_314; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3462 = _out_T_3461; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_259 = _out_T_3462; // @[RegisterRouter.scala:87:24] wire out_rimask_315 = \|_out_rimask_T_315; // @[RegisterRouter.scala:87:24] wire out_wimask_315 = &_out_wimask_T_315; // @[RegisterRouter.scala:87:24] wire out_romask_315 = \|_out_romask_T_315; // @[RegisterRouter.scala:87:24] wire out_womask_315 = &_out_womask_T_315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_315 = out_rivalid_1_169 & out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3464 = out_f_rivalid_315; // @[RegisterRouter.scala:87:24] wire out_f_roready_315 = out_roready_1_169 & out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3465 = out_f_roready_315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_315 = out_wivalid_1_169 & out_wimask_315; // @[RegisterRouter.scala:87:24] wire out_f_woready_315 = out_woready_1_169 & out_womask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3466 = ~out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3467 = ~out_wimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3468 = ~out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3469 = ~out_womask_315; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_259 = {hi_706, flags_0_go, _out_prepend_T_259}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3470 = out_prepend_259; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3471 = _out_T_3470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_260 = _out_T_3471; // @[RegisterRouter.scala:87:24] wire out_rimask_316 = \|_out_rimask_T_316; // @[RegisterRouter.scala:87:24] wire out_wimask_316 = &_out_wimask_T_316; // @[RegisterRouter.scala:87:24] wire out_romask_316 = \|_out_romask_T_316; // @[RegisterRouter.scala:87:24] wire out_womask_316 = &_out_womask_T_316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_316 = out_rivalid_1_170 & out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3473 = out_f_rivalid_316; // @[RegisterRouter.scala:87:24] wire out_f_roready_316 = out_roready_1_170 & out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3474 = out_f_roready_316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_316 = out_wivalid_1_170 & out_wimask_316; // @[RegisterRouter.scala:87:24] wire out_f_woready_316 = out_woready_1_170 & out_womask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3475 = ~out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3476 = ~out_wimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3477 = ~out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3478 = ~out_womask_316; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_260 = {hi_707, flags_0_go, _out_prepend_T_260}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3479 = out_prepend_260; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3480 = _out_T_3479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_261 = _out_T_3480; // @[RegisterRouter.scala:87:24] wire out_rimask_317 = \|_out_rimask_T_317; // @[RegisterRouter.scala:87:24] wire out_wimask_317 = &_out_wimask_T_317; // @[RegisterRouter.scala:87:24] wire out_romask_317 = \|_out_romask_T_317; // @[RegisterRouter.scala:87:24] wire out_womask_317 = &_out_womask_T_317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_317 = out_rivalid_1_171 & out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3482 = out_f_rivalid_317; // @[RegisterRouter.scala:87:24] wire out_f_roready_317 = out_roready_1_171 & out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3483 = out_f_roready_317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_317 = out_wivalid_1_171 & out_wimask_317; // @[RegisterRouter.scala:87:24] wire out_f_woready_317 = out_woready_1_171 & out_womask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3484 = ~out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3485 = ~out_wimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3486 = ~out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3487 = ~out_womask_317; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_261 = {hi_708, flags_0_go, _out_prepend_T_261}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3488 = out_prepend_261; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3489 = _out_T_3488; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_262 = _out_T_3489; // @[RegisterRouter.scala:87:24] wire out_rimask_318 = \|_out_rimask_T_318; // @[RegisterRouter.scala:87:24] wire out_wimask_318 = &_out_wimask_T_318; // @[RegisterRouter.scala:87:24] wire out_romask_318 = \|_out_romask_T_318; // @[RegisterRouter.scala:87:24] wire out_womask_318 = &_out_womask_T_318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_318 = out_rivalid_1_172 & out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3491 = out_f_rivalid_318; // @[RegisterRouter.scala:87:24] wire out_f_roready_318 = out_roready_1_172 & out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3492 = out_f_roready_318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_318 = out_wivalid_1_172 & out_wimask_318; // @[RegisterRouter.scala:87:24] wire out_f_woready_318 = out_woready_1_172 & out_womask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3493 = ~out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3494 = ~out_wimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3495 = ~out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3496 = ~out_womask_318; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_262 = {hi_709, flags_0_go, _out_prepend_T_262}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3497 = out_prepend_262; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3498 = _out_T_3497; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_263 = _out_T_3498; // @[RegisterRouter.scala:87:24] wire out_rimask_319 = \|_out_rimask_T_319; // @[RegisterRouter.scala:87:24] wire out_wimask_319 = &_out_wimask_T_319; // @[RegisterRouter.scala:87:24] wire out_romask_319 = \|_out_romask_T_319; // @[RegisterRouter.scala:87:24] wire out_womask_319 = &_out_womask_T_319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_319 = out_rivalid_1_173 & out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3500 = out_f_rivalid_319; // @[RegisterRouter.scala:87:24] wire out_f_roready_319 = out_roready_1_173 & out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3501 = out_f_roready_319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_319 = out_wivalid_1_173 & out_wimask_319; // @[RegisterRouter.scala:87:24] wire out_f_woready_319 = out_woready_1_173 & out_womask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3502 = ~out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3503 = ~out_wimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3504 = ~out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3505 = ~out_womask_319; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_263 = {hi_710, flags_0_go, _out_prepend_T_263}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3506 = out_prepend_263; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3507 = _out_T_3506; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_264 = _out_T_3507; // @[RegisterRouter.scala:87:24] wire out_rimask_320 = \|_out_rimask_T_320; // @[RegisterRouter.scala:87:24] wire out_wimask_320 = &_out_wimask_T_320; // @[RegisterRouter.scala:87:24] wire out_romask_320 = \|_out_romask_T_320; // @[RegisterRouter.scala:87:24] wire out_womask_320 = &_out_womask_T_320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_320 = out_rivalid_1_174 & out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3509 = out_f_rivalid_320; // @[RegisterRouter.scala:87:24] wire out_f_roready_320 = out_roready_1_174 & out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3510 = out_f_roready_320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_320 = out_wivalid_1_174 & out_wimask_320; // @[RegisterRouter.scala:87:24] wire out_f_woready_320 = out_woready_1_174 & out_womask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3511 = ~out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3512 = ~out_wimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3513 = ~out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3514 = ~out_womask_320; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_264 = {hi_711, flags_0_go, _out_prepend_T_264}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3515 = out_prepend_264; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3516 = _out_T_3515; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_265 = _out_T_3516; // @[RegisterRouter.scala:87:24] wire out_rimask_321 = \|_out_rimask_T_321; // @[RegisterRouter.scala:87:24] wire out_wimask_321 = &_out_wimask_T_321; // @[RegisterRouter.scala:87:24] wire out_romask_321 = \|_out_romask_T_321; // @[RegisterRouter.scala:87:24] wire out_womask_321 = &_out_womask_T_321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_321 = out_rivalid_1_175 & out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3518 = out_f_rivalid_321; // @[RegisterRouter.scala:87:24] wire out_f_roready_321 = out_roready_1_175 & out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3519 = out_f_roready_321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_321 = out_wivalid_1_175 & out_wimask_321; // @[RegisterRouter.scala:87:24] wire out_f_woready_321 = out_woready_1_175 & out_womask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3520 = ~out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3521 = ~out_wimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3522 = ~out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3523 = ~out_womask_321; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_265 = {hi_712, flags_0_go, _out_prepend_T_265}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3524 = out_prepend_265; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3525 = _out_T_3524; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_216 = _out_T_3525; // @[MuxLiteral.scala:49:48] wire out_rimask_322 = \|_out_rimask_T_322; // @[RegisterRouter.scala:87:24] wire out_wimask_322 = &_out_wimask_T_322; // @[RegisterRouter.scala:87:24] wire out_romask_322 = \|_out_romask_T_322; // @[RegisterRouter.scala:87:24] wire out_womask_322 = &_out_womask_T_322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_322 = out_rivalid_1_176 & out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3527 = out_f_rivalid_322; // @[RegisterRouter.scala:87:24] wire out_f_roready_322 = out_roready_1_176 & out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3528 = out_f_roready_322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_322 = out_wivalid_1_176 & out_wimask_322; // @[RegisterRouter.scala:87:24] wire out_f_woready_322 = out_woready_1_176 & out_womask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3529 = ~out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3530 = ~out_wimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3531 = ~out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3532 = ~out_womask_322; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3534 = _out_T_3533; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_266 = _out_T_3534; // @[RegisterRouter.scala:87:24] wire out_rimask_323 = \|_out_rimask_T_323; // @[RegisterRouter.scala:87:24] wire out_wimask_323 = &_out_wimask_T_323; // @[RegisterRouter.scala:87:24] wire out_romask_323 = \|_out_romask_T_323; // @[RegisterRouter.scala:87:24] wire out_womask_323 = &_out_womask_T_323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_323 = out_rivalid_1_177 & out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3536 = out_f_rivalid_323; // @[RegisterRouter.scala:87:24] wire out_f_roready_323 = out_roready_1_177 & out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3537 = out_f_roready_323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_323 = out_wivalid_1_177 & out_wimask_323; // @[RegisterRouter.scala:87:24] wire out_f_woready_323 = out_woready_1_177 & out_womask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3538 = ~out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3539 = ~out_wimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3540 = ~out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3541 = ~out_womask_323; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_266 = {hi_290, flags_0_go, _out_prepend_T_266}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3542 = out_prepend_266; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3543 = _out_T_3542; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_267 = _out_T_3543; // @[RegisterRouter.scala:87:24] wire out_rimask_324 = \|_out_rimask_T_324; // @[RegisterRouter.scala:87:24] wire out_wimask_324 = &_out_wimask_T_324; // @[RegisterRouter.scala:87:24] wire out_romask_324 = \|_out_romask_T_324; // @[RegisterRouter.scala:87:24] wire out_womask_324 = &_out_womask_T_324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_324 = out_rivalid_1_178 & out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3545 = out_f_rivalid_324; // @[RegisterRouter.scala:87:24] wire out_f_roready_324 = out_roready_1_178 & out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3546 = out_f_roready_324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_324 = out_wivalid_1_178 & out_wimask_324; // @[RegisterRouter.scala:87:24] wire out_f_woready_324 = out_woready_1_178 & out_womask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3547 = ~out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3548 = ~out_wimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3549 = ~out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3550 = ~out_womask_324; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_267 = {hi_291, flags_0_go, _out_prepend_T_267}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3551 = out_prepend_267; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3552 = _out_T_3551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_268 = _out_T_3552; // @[RegisterRouter.scala:87:24] wire out_rimask_325 = \|_out_rimask_T_325; // @[RegisterRouter.scala:87:24] wire out_wimask_325 = &_out_wimask_T_325; // @[RegisterRouter.scala:87:24] wire out_romask_325 = \|_out_romask_T_325; // @[RegisterRouter.scala:87:24] wire out_womask_325 = &_out_womask_T_325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_325 = out_rivalid_1_179 & out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3554 = out_f_rivalid_325; // @[RegisterRouter.scala:87:24] wire out_f_roready_325 = out_roready_1_179 & out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3555 = out_f_roready_325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_325 = out_wivalid_1_179 & out_wimask_325; // @[RegisterRouter.scala:87:24] wire out_f_woready_325 = out_woready_1_179 & out_womask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3556 = ~out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3557 = ~out_wimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3558 = ~out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3559 = ~out_womask_325; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_268 = {hi_292, flags_0_go, _out_prepend_T_268}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3560 = out_prepend_268; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3561 = _out_T_3560; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_269 = _out_T_3561; // @[RegisterRouter.scala:87:24] wire out_rimask_326 = \|_out_rimask_T_326; // @[RegisterRouter.scala:87:24] wire out_wimask_326 = &_out_wimask_T_326; // @[RegisterRouter.scala:87:24] wire out_romask_326 = \|_out_romask_T_326; // @[RegisterRouter.scala:87:24] wire out_womask_326 = &_out_womask_T_326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_326 = out_rivalid_1_180 & out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3563 = out_f_rivalid_326; // @[RegisterRouter.scala:87:24] wire out_f_roready_326 = out_roready_1_180 & out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3564 = out_f_roready_326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_326 = out_wivalid_1_180 & out_wimask_326; // @[RegisterRouter.scala:87:24] wire out_f_woready_326 = out_woready_1_180 & out_womask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3565 = ~out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3566 = ~out_wimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3567 = ~out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3568 = ~out_womask_326; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_269 = {hi_293, flags_0_go, _out_prepend_T_269}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3569 = out_prepend_269; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3570 = _out_T_3569; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_270 = _out_T_3570; // @[RegisterRouter.scala:87:24] wire out_rimask_327 = \|_out_rimask_T_327; // @[RegisterRouter.scala:87:24] wire out_wimask_327 = &_out_wimask_T_327; // @[RegisterRouter.scala:87:24] wire out_romask_327 = \|_out_romask_T_327; // @[RegisterRouter.scala:87:24] wire out_womask_327 = &_out_womask_T_327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_327 = out_rivalid_1_181 & out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3572 = out_f_rivalid_327; // @[RegisterRouter.scala:87:24] wire out_f_roready_327 = out_roready_1_181 & out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3573 = out_f_roready_327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_327 = out_wivalid_1_181 & out_wimask_327; // @[RegisterRouter.scala:87:24] wire out_f_woready_327 = out_woready_1_181 & out_womask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3574 = ~out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3575 = ~out_wimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3576 = ~out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3577 = ~out_womask_327; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_270 = {hi_294, flags_0_go, _out_prepend_T_270}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3578 = out_prepend_270; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3579 = _out_T_3578; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_271 = _out_T_3579; // @[RegisterRouter.scala:87:24] wire out_rimask_328 = \|_out_rimask_T_328; // @[RegisterRouter.scala:87:24] wire out_wimask_328 = &_out_wimask_T_328; // @[RegisterRouter.scala:87:24] wire out_romask_328 = \|_out_romask_T_328; // @[RegisterRouter.scala:87:24] wire out_womask_328 = &_out_womask_T_328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_328 = out_rivalid_1_182 & out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3581 = out_f_rivalid_328; // @[RegisterRouter.scala:87:24] wire out_f_roready_328 = out_roready_1_182 & out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3582 = out_f_roready_328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_328 = out_wivalid_1_182 & out_wimask_328; // @[RegisterRouter.scala:87:24] wire out_f_woready_328 = out_woready_1_182 & out_womask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3583 = ~out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3584 = ~out_wimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3585 = ~out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3586 = ~out_womask_328; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_271 = {hi_295, flags_0_go, _out_prepend_T_271}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3587 = out_prepend_271; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3588 = _out_T_3587; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_272 = _out_T_3588; // @[RegisterRouter.scala:87:24] wire out_rimask_329 = \|_out_rimask_T_329; // @[RegisterRouter.scala:87:24] wire out_wimask_329 = &_out_wimask_T_329; // @[RegisterRouter.scala:87:24] wire out_romask_329 = \|_out_romask_T_329; // @[RegisterRouter.scala:87:24] wire out_womask_329 = &_out_womask_T_329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_329 = out_rivalid_1_183 & out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3590 = out_f_rivalid_329; // @[RegisterRouter.scala:87:24] wire out_f_roready_329 = out_roready_1_183 & out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3591 = out_f_roready_329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_329 = out_wivalid_1_183 & out_wimask_329; // @[RegisterRouter.scala:87:24] wire out_f_woready_329 = out_woready_1_183 & out_womask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3592 = ~out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3593 = ~out_wimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3594 = ~out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3595 = ~out_womask_329; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_272 = {hi_296, flags_0_go, _out_prepend_T_272}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3596 = out_prepend_272; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3597 = _out_T_3596; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_164 = _out_T_3597; // @[MuxLiteral.scala:49:48] wire out_rimask_330 = \|_out_rimask_T_330; // @[RegisterRouter.scala:87:24] wire out_wimask_330 = &_out_wimask_T_330; // @[RegisterRouter.scala:87:24] wire out_romask_330 = \|_out_romask_T_330; // @[RegisterRouter.scala:87:24] wire out_womask_330 = &_out_womask_T_330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_330 = out_rivalid_1_184 & out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3599 = out_f_rivalid_330; // @[RegisterRouter.scala:87:24] wire out_f_roready_330 = out_roready_1_184 & out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3600 = out_f_roready_330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_330 = out_wivalid_1_184 & out_wimask_330; // @[RegisterRouter.scala:87:24] wire out_f_woready_330 = out_woready_1_184 & out_womask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3601 = ~out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3602 = ~out_wimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3603 = ~out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3604 = ~out_womask_330; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3606 = _out_T_3605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_273 = _out_T_3606; // @[RegisterRouter.scala:87:24] wire out_rimask_331 = \|_out_rimask_T_331; // @[RegisterRouter.scala:87:24] wire out_wimask_331 = &_out_wimask_T_331; // @[RegisterRouter.scala:87:24] wire out_romask_331 = \|_out_romask_T_331; // @[RegisterRouter.scala:87:24] wire out_womask_331 = &_out_womask_T_331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_331 = out_rivalid_1_185 & out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3608 = out_f_rivalid_331; // @[RegisterRouter.scala:87:24] wire out_f_roready_331 = out_roready_1_185 & out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3609 = out_f_roready_331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_331 = out_wivalid_1_185 & out_wimask_331; // @[RegisterRouter.scala:87:24] wire out_f_woready_331 = out_woready_1_185 & out_womask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3610 = ~out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3611 = ~out_wimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3612 = ~out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3613 = ~out_womask_331; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_273 = {hi_410, flags_0_go, _out_prepend_T_273}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3614 = out_prepend_273; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3615 = _out_T_3614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_274 = _out_T_3615; // @[RegisterRouter.scala:87:24] wire out_rimask_332 = \|_out_rimask_T_332; // @[RegisterRouter.scala:87:24] wire out_wimask_332 = &_out_wimask_T_332; // @[RegisterRouter.scala:87:24] wire out_romask_332 = \|_out_romask_T_332; // @[RegisterRouter.scala:87:24] wire out_womask_332 = &_out_womask_T_332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_332 = out_rivalid_1_186 & out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3617 = out_f_rivalid_332; // @[RegisterRouter.scala:87:24] wire out_f_roready_332 = out_roready_1_186 & out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3618 = out_f_roready_332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_332 = out_wivalid_1_186 & out_wimask_332; // @[RegisterRouter.scala:87:24] wire out_f_woready_332 = out_woready_1_186 & out_womask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3619 = ~out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3620 = ~out_wimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3621 = ~out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3622 = ~out_womask_332; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_274 = {hi_411, flags_0_go, _out_prepend_T_274}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3623 = out_prepend_274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3624 = _out_T_3623; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_275 = _out_T_3624; // @[RegisterRouter.scala:87:24] wire out_rimask_333 = \|_out_rimask_T_333; // @[RegisterRouter.scala:87:24] wire out_wimask_333 = &_out_wimask_T_333; // @[RegisterRouter.scala:87:24] wire out_romask_333 = \|_out_romask_T_333; // @[RegisterRouter.scala:87:24] wire out_womask_333 = &_out_womask_T_333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_333 = out_rivalid_1_187 & out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3626 = out_f_rivalid_333; // @[RegisterRouter.scala:87:24] wire out_f_roready_333 = out_roready_1_187 & out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3627 = out_f_roready_333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_333 = out_wivalid_1_187 & out_wimask_333; // @[RegisterRouter.scala:87:24] wire out_f_woready_333 = out_woready_1_187 & out_womask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3628 = ~out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3629 = ~out_wimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3630 = ~out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3631 = ~out_womask_333; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_275 = {hi_412, flags_0_go, _out_prepend_T_275}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3632 = out_prepend_275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3633 = _out_T_3632; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_276 = _out_T_3633; // @[RegisterRouter.scala:87:24] wire out_rimask_334 = \|_out_rimask_T_334; // @[RegisterRouter.scala:87:24] wire out_wimask_334 = &_out_wimask_T_334; // @[RegisterRouter.scala:87:24] wire out_romask_334 = \|_out_romask_T_334; // @[RegisterRouter.scala:87:24] wire out_womask_334 = &_out_womask_T_334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_334 = out_rivalid_1_188 & out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3635 = out_f_rivalid_334; // @[RegisterRouter.scala:87:24] wire out_f_roready_334 = out_roready_1_188 & out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3636 = out_f_roready_334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_334 = out_wivalid_1_188 & out_wimask_334; // @[RegisterRouter.scala:87:24] wire out_f_woready_334 = out_woready_1_188 & out_womask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3637 = ~out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3638 = ~out_wimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3639 = ~out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3640 = ~out_womask_334; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_276 = {hi_413, flags_0_go, _out_prepend_T_276}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3641 = out_prepend_276; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3642 = _out_T_3641; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_277 = _out_T_3642; // @[RegisterRouter.scala:87:24] wire out_rimask_335 = \|_out_rimask_T_335; // @[RegisterRouter.scala:87:24] wire out_wimask_335 = &_out_wimask_T_335; // @[RegisterRouter.scala:87:24] wire out_romask_335 = \|_out_romask_T_335; // @[RegisterRouter.scala:87:24] wire out_womask_335 = &_out_womask_T_335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_335 = out_rivalid_1_189 & out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3644 = out_f_rivalid_335; // @[RegisterRouter.scala:87:24] wire out_f_roready_335 = out_roready_1_189 & out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3645 = out_f_roready_335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_335 = out_wivalid_1_189 & out_wimask_335; // @[RegisterRouter.scala:87:24] wire out_f_woready_335 = out_woready_1_189 & out_womask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3646 = ~out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3647 = ~out_wimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3648 = ~out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3649 = ~out_womask_335; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_277 = {hi_414, flags_0_go, _out_prepend_T_277}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3650 = out_prepend_277; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3651 = _out_T_3650; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_278 = _out_T_3651; // @[RegisterRouter.scala:87:24] wire out_rimask_336 = \|_out_rimask_T_336; // @[RegisterRouter.scala:87:24] wire out_wimask_336 = &_out_wimask_T_336; // @[RegisterRouter.scala:87:24] wire out_romask_336 = \|_out_romask_T_336; // @[RegisterRouter.scala:87:24] wire out_womask_336 = &_out_womask_T_336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_336 = out_rivalid_1_190 & out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3653 = out_f_rivalid_336; // @[RegisterRouter.scala:87:24] wire out_f_roready_336 = out_roready_1_190 & out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3654 = out_f_roready_336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_336 = out_wivalid_1_190 & out_wimask_336; // @[RegisterRouter.scala:87:24] wire out_f_woready_336 = out_woready_1_190 & out_womask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3655 = ~out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3656 = ~out_wimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3657 = ~out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3658 = ~out_womask_336; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_278 = {hi_415, flags_0_go, _out_prepend_T_278}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3659 = out_prepend_278; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3660 = _out_T_3659; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_279 = _out_T_3660; // @[RegisterRouter.scala:87:24] wire out_rimask_337 = \|_out_rimask_T_337; // @[RegisterRouter.scala:87:24] wire out_wimask_337 = &_out_wimask_T_337; // @[RegisterRouter.scala:87:24] wire out_romask_337 = \|_out_romask_T_337; // @[RegisterRouter.scala:87:24] wire out_womask_337 = &_out_womask_T_337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_337 = out_rivalid_1_191 & out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3662 = out_f_rivalid_337; // @[RegisterRouter.scala:87:24] wire out_f_roready_337 = out_roready_1_191 & out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3663 = out_f_roready_337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_337 = out_wivalid_1_191 & out_wimask_337; // @[RegisterRouter.scala:87:24] wire out_f_woready_337 = out_woready_1_191 & out_womask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3664 = ~out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3665 = ~out_wimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3666 = ~out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3667 = ~out_womask_337; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_279 = {hi_416, flags_0_go, _out_prepend_T_279}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3668 = out_prepend_279; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3669 = _out_T_3668; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_179 = _out_T_3669; // @[MuxLiteral.scala:49:48] wire out_rimask_338 = \|_out_rimask_T_338; // @[RegisterRouter.scala:87:24] wire out_wimask_338 = &_out_wimask_T_338; // @[RegisterRouter.scala:87:24] wire out_romask_338 = \|_out_romask_T_338; // @[RegisterRouter.scala:87:24] wire out_womask_338 = &_out_womask_T_338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_338 = out_rivalid_1_192 & out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3671 = out_f_rivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_roready_338 = out_roready_1_192 & out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3672 = out_f_roready_338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_338 = out_wivalid_1_192 & out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3673 = out_f_wivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_woready_338 = out_woready_1_192 & out_womask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3674 = out_f_woready_338; // @[RegisterRouter.scala:87:24] wire _out_T_3675 = ~out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3676 = ~out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3677 = ~out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3678 = ~out_womask_338; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3680 = _out_T_3679; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_280 = _out_T_3680; // @[RegisterRouter.scala:87:24] wire out_rimask_339 = \|_out_rimask_T_339; // @[RegisterRouter.scala:87:24] wire out_wimask_339 = &_out_wimask_T_339; // @[RegisterRouter.scala:87:24] wire out_romask_339 = \|_out_romask_T_339; // @[RegisterRouter.scala:87:24] wire out_womask_339 = &_out_womask_T_339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_339 = out_rivalid_1_193 & out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3682 = out_f_rivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_roready_339 = out_roready_1_193 & out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3683 = out_f_roready_339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_339 = out_wivalid_1_193 & out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3684 = out_f_wivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_woready_339 = out_woready_1_193 & out_womask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3685 = out_f_woready_339; // @[RegisterRouter.scala:87:24] wire _out_T_3686 = ~out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3687 = ~out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3688 = ~out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3689 = ~out_womask_339; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_280 = {programBufferMem_17, _out_prepend_T_280}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3690 = out_prepend_280; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3691 = _out_T_3690; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_281 = _out_T_3691; // @[RegisterRouter.scala:87:24] wire out_rimask_340 = \|_out_rimask_T_340; // @[RegisterRouter.scala:87:24] wire out_wimask_340 = &_out_wimask_T_340; // @[RegisterRouter.scala:87:24] wire out_romask_340 = \|_out_romask_T_340; // @[RegisterRouter.scala:87:24] wire out_womask_340 = &_out_womask_T_340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_340 = out_rivalid_1_194 & out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3693 = out_f_rivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_roready_340 = out_roready_1_194 & out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3694 = out_f_roready_340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_340 = out_wivalid_1_194 & out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3695 = out_f_wivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_woready_340 = out_woready_1_194 & out_womask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3696 = out_f_woready_340; // @[RegisterRouter.scala:87:24] wire _out_T_3697 = ~out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3698 = ~out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3699 = ~out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3700 = ~out_womask_340; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_281 = {programBufferMem_18, _out_prepend_T_281}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3701 = out_prepend_281; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3702 = _out_T_3701; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_282 = _out_T_3702; // @[RegisterRouter.scala:87:24] wire out_rimask_341 = \|_out_rimask_T_341; // @[RegisterRouter.scala:87:24] wire out_wimask_341 = &_out_wimask_T_341; // @[RegisterRouter.scala:87:24] wire out_romask_341 = \|_out_romask_T_341; // @[RegisterRouter.scala:87:24] wire out_womask_341 = &_out_womask_T_341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_341 = out_rivalid_1_195 & out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3704 = out_f_rivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_roready_341 = out_roready_1_195 & out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3705 = out_f_roready_341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_341 = out_wivalid_1_195 & out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3706 = out_f_wivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_woready_341 = out_woready_1_195 & out_womask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3707 = out_f_woready_341; // @[RegisterRouter.scala:87:24] wire _out_T_3708 = ~out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3709 = ~out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3710 = ~out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3711 = ~out_womask_341; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_282 = {programBufferMem_19, _out_prepend_T_282}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3712 = out_prepend_282; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3713 = _out_T_3712; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_283 = _out_T_3713; // @[RegisterRouter.scala:87:24] wire out_rimask_342 = \|_out_rimask_T_342; // @[RegisterRouter.scala:87:24] wire out_wimask_342 = &_out_wimask_T_342; // @[RegisterRouter.scala:87:24] wire out_romask_342 = \|_out_romask_T_342; // @[RegisterRouter.scala:87:24] wire out_womask_342 = &_out_womask_T_342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_342 = out_rivalid_1_196 & out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3715 = out_f_rivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_roready_342 = out_roready_1_196 & out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3716 = out_f_roready_342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_342 = out_wivalid_1_196 & out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3717 = out_f_wivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_woready_342 = out_woready_1_196 & out_womask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3718 = out_f_woready_342; // @[RegisterRouter.scala:87:24] wire _out_T_3719 = ~out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3720 = ~out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3721 = ~out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3722 = ~out_womask_342; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_283 = {programBufferMem_20, _out_prepend_T_283}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3723 = out_prepend_283; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3724 = _out_T_3723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_284 = _out_T_3724; // @[RegisterRouter.scala:87:24] wire out_rimask_343 = \|_out_rimask_T_343; // @[RegisterRouter.scala:87:24] wire out_wimask_343 = &_out_wimask_T_343; // @[RegisterRouter.scala:87:24] wire out_romask_343 = \|_out_romask_T_343; // @[RegisterRouter.scala:87:24] wire out_womask_343 = &_out_womask_T_343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_343 = out_rivalid_1_197 & out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3726 = out_f_rivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_roready_343 = out_roready_1_197 & out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3727 = out_f_roready_343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_343 = out_wivalid_1_197 & out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3728 = out_f_wivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_woready_343 = out_woready_1_197 & out_womask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3729 = out_f_woready_343; // @[RegisterRouter.scala:87:24] wire _out_T_3730 = ~out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3731 = ~out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3732 = ~out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3733 = ~out_womask_343; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_284 = {programBufferMem_21, _out_prepend_T_284}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3734 = out_prepend_284; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3735 = _out_T_3734; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_285 = _out_T_3735; // @[RegisterRouter.scala:87:24] wire out_rimask_344 = \|_out_rimask_T_344; // @[RegisterRouter.scala:87:24] wire out_wimask_344 = &_out_wimask_T_344; // @[RegisterRouter.scala:87:24] wire out_romask_344 = \|_out_romask_T_344; // @[RegisterRouter.scala:87:24] wire out_womask_344 = &_out_womask_T_344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_344 = out_rivalid_1_198 & out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3737 = out_f_rivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_roready_344 = out_roready_1_198 & out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3738 = out_f_roready_344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_344 = out_wivalid_1_198 & out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3739 = out_f_wivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_woready_344 = out_woready_1_198 & out_womask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3740 = out_f_woready_344; // @[RegisterRouter.scala:87:24] wire _out_T_3741 = ~out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3742 = ~out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3743 = ~out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3744 = ~out_womask_344; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_285 = {programBufferMem_22, _out_prepend_T_285}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3745 = out_prepend_285; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3746 = _out_T_3745; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_286 = _out_T_3746; // @[RegisterRouter.scala:87:24] wire out_rimask_345 = \|_out_rimask_T_345; // @[RegisterRouter.scala:87:24] wire out_wimask_345 = &_out_wimask_T_345; // @[RegisterRouter.scala:87:24] wire out_romask_345 = \|_out_romask_T_345; // @[RegisterRouter.scala:87:24] wire out_womask_345 = &_out_womask_T_345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_345 = out_rivalid_1_199 & out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3748 = out_f_rivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_roready_345 = out_roready_1_199 & out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3749 = out_f_roready_345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_345 = out_wivalid_1_199 & out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3750 = out_f_wivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_woready_345 = out_woready_1_199 & out_womask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3751 = out_f_woready_345; // @[RegisterRouter.scala:87:24] wire _out_T_3752 = ~out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3753 = ~out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3754 = ~out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3755 = ~out_womask_345; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_286 = {programBufferMem_23, _out_prepend_T_286}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3756 = out_prepend_286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3757 = _out_T_3756; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_106 = _out_T_3757; // @[MuxLiteral.scala:49:48] wire out_rimask_346 = \|_out_rimask_T_346; // @[RegisterRouter.scala:87:24] wire out_wimask_346 = &_out_wimask_T_346; // @[RegisterRouter.scala:87:24] wire out_romask_346 = \|_out_romask_T_346; // @[RegisterRouter.scala:87:24] wire out_womask_346 = &_out_womask_T_346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_346 = out_rivalid_1_200 & out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3759 = out_f_rivalid_346; // @[RegisterRouter.scala:87:24] wire out_f_roready_346 = out_roready_1_200 & out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3760 = out_f_roready_346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_346 = out_wivalid_1_200 & out_wimask_346; // @[RegisterRouter.scala:87:24] wire out_f_woready_346 = out_woready_1_200 & out_womask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3761 = ~out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3762 = ~out_wimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3763 = ~out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3764 = ~out_womask_346; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3766 = _out_T_3765; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_287 = _out_T_3766; // @[RegisterRouter.scala:87:24] wire out_rimask_347 = \|_out_rimask_T_347; // @[RegisterRouter.scala:87:24] wire out_wimask_347 = &_out_wimask_T_347; // @[RegisterRouter.scala:87:24] wire out_romask_347 = \|_out_romask_T_347; // @[RegisterRouter.scala:87:24] wire out_womask_347 = &_out_womask_T_347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_347 = out_rivalid_1_201 & out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3768 = out_f_rivalid_347; // @[RegisterRouter.scala:87:24] wire out_f_roready_347 = out_roready_1_201 & out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3769 = out_f_roready_347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_347 = out_wivalid_1_201 & out_wimask_347; // @[RegisterRouter.scala:87:24] wire out_f_woready_347 = out_woready_1_201 & out_womask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3770 = ~out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3771 = ~out_wimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3772 = ~out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3773 = ~out_womask_347; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_287 = {hi_882, flags_0_go, _out_prepend_T_287}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3774 = out_prepend_287; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3775 = _out_T_3774; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_288 = _out_T_3775; // @[RegisterRouter.scala:87:24] wire out_rimask_348 = \|_out_rimask_T_348; // @[RegisterRouter.scala:87:24] wire out_wimask_348 = &_out_wimask_T_348; // @[RegisterRouter.scala:87:24] wire out_romask_348 = \|_out_romask_T_348; // @[RegisterRouter.scala:87:24] wire out_womask_348 = &_out_womask_T_348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_348 = out_rivalid_1_202 & out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3777 = out_f_rivalid_348; // @[RegisterRouter.scala:87:24] wire out_f_roready_348 = out_roready_1_202 & out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3778 = out_f_roready_348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_348 = out_wivalid_1_202 & out_wimask_348; // @[RegisterRouter.scala:87:24] wire out_f_woready_348 = out_woready_1_202 & out_womask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3779 = ~out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3780 = ~out_wimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3781 = ~out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3782 = ~out_womask_348; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_288 = {hi_883, flags_0_go, _out_prepend_T_288}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3783 = out_prepend_288; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3784 = _out_T_3783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_289 = _out_T_3784; // @[RegisterRouter.scala:87:24] wire out_rimask_349 = \|_out_rimask_T_349; // @[RegisterRouter.scala:87:24] wire out_wimask_349 = &_out_wimask_T_349; // @[RegisterRouter.scala:87:24] wire out_romask_349 = \|_out_romask_T_349; // @[RegisterRouter.scala:87:24] wire out_womask_349 = &_out_womask_T_349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_349 = out_rivalid_1_203 & out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3786 = out_f_rivalid_349; // @[RegisterRouter.scala:87:24] wire out_f_roready_349 = out_roready_1_203 & out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3787 = out_f_roready_349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_349 = out_wivalid_1_203 & out_wimask_349; // @[RegisterRouter.scala:87:24] wire out_f_woready_349 = out_woready_1_203 & out_womask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3788 = ~out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3789 = ~out_wimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3790 = ~out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3791 = ~out_womask_349; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_289 = {hi_884, flags_0_go, _out_prepend_T_289}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3792 = out_prepend_289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3793 = _out_T_3792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_290 = _out_T_3793; // @[RegisterRouter.scala:87:24] wire out_rimask_350 = \|_out_rimask_T_350; // @[RegisterRouter.scala:87:24] wire out_wimask_350 = &_out_wimask_T_350; // @[RegisterRouter.scala:87:24] wire out_romask_350 = \|_out_romask_T_350; // @[RegisterRouter.scala:87:24] wire out_womask_350 = &_out_womask_T_350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_350 = out_rivalid_1_204 & out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3795 = out_f_rivalid_350; // @[RegisterRouter.scala:87:24] wire out_f_roready_350 = out_roready_1_204 & out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3796 = out_f_roready_350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_350 = out_wivalid_1_204 & out_wimask_350; // @[RegisterRouter.scala:87:24] wire out_f_woready_350 = out_woready_1_204 & out_womask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3797 = ~out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3798 = ~out_wimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3799 = ~out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3800 = ~out_womask_350; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_290 = {hi_885, flags_0_go, _out_prepend_T_290}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3801 = out_prepend_290; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3802 = _out_T_3801; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_291 = _out_T_3802; // @[RegisterRouter.scala:87:24] wire out_rimask_351 = \|_out_rimask_T_351; // @[RegisterRouter.scala:87:24] wire out_wimask_351 = &_out_wimask_T_351; // @[RegisterRouter.scala:87:24] wire out_romask_351 = \|_out_romask_T_351; // @[RegisterRouter.scala:87:24] wire out_womask_351 = &_out_womask_T_351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_351 = out_rivalid_1_205 & out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3804 = out_f_rivalid_351; // @[RegisterRouter.scala:87:24] wire out_f_roready_351 = out_roready_1_205 & out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3805 = out_f_roready_351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_351 = out_wivalid_1_205 & out_wimask_351; // @[RegisterRouter.scala:87:24] wire out_f_woready_351 = out_woready_1_205 & out_womask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3806 = ~out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3807 = ~out_wimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3808 = ~out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3809 = ~out_womask_351; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_291 = {hi_886, flags_0_go, _out_prepend_T_291}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3810 = out_prepend_291; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3811 = _out_T_3810; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_292 = _out_T_3811; // @[RegisterRouter.scala:87:24] wire out_rimask_352 = \|_out_rimask_T_352; // @[RegisterRouter.scala:87:24] wire out_wimask_352 = &_out_wimask_T_352; // @[RegisterRouter.scala:87:24] wire out_romask_352 = \|_out_romask_T_352; // @[RegisterRouter.scala:87:24] wire out_womask_352 = &_out_womask_T_352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_352 = out_rivalid_1_206 & out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3813 = out_f_rivalid_352; // @[RegisterRouter.scala:87:24] wire out_f_roready_352 = out_roready_1_206 & out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3814 = out_f_roready_352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_352 = out_wivalid_1_206 & out_wimask_352; // @[RegisterRouter.scala:87:24] wire out_f_woready_352 = out_woready_1_206 & out_womask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3815 = ~out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3816 = ~out_wimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3817 = ~out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3818 = ~out_womask_352; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_292 = {hi_887, flags_0_go, _out_prepend_T_292}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3819 = out_prepend_292; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3820 = _out_T_3819; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_293 = _out_T_3820; // @[RegisterRouter.scala:87:24] wire out_rimask_353 = \|_out_rimask_T_353; // @[RegisterRouter.scala:87:24] wire out_wimask_353 = &_out_wimask_T_353; // @[RegisterRouter.scala:87:24] wire out_romask_353 = \|_out_romask_T_353; // @[RegisterRouter.scala:87:24] wire out_womask_353 = &_out_womask_T_353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_353 = out_rivalid_1_207 & out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3822 = out_f_rivalid_353; // @[RegisterRouter.scala:87:24] wire out_f_roready_353 = out_roready_1_207 & out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3823 = out_f_roready_353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_353 = out_wivalid_1_207 & out_wimask_353; // @[RegisterRouter.scala:87:24] wire out_f_woready_353 = out_woready_1_207 & out_womask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3824 = ~out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3825 = ~out_wimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3826 = ~out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3827 = ~out_womask_353; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_293 = {hi_888, flags_0_go, _out_prepend_T_293}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3828 = out_prepend_293; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3829 = _out_T_3828; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_238 = _out_T_3829; // @[MuxLiteral.scala:49:48] wire out_rimask_354 = \|_out_rimask_T_354; // @[RegisterRouter.scala:87:24] wire out_wimask_354 = &_out_wimask_T_354; // @[RegisterRouter.scala:87:24] wire out_romask_354 = \|_out_romask_T_354; // @[RegisterRouter.scala:87:24] wire out_womask_354 = &_out_womask_T_354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_354 = out_rivalid_1_208 & out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3831 = out_f_rivalid_354; // @[RegisterRouter.scala:87:24] wire out_f_roready_354 = out_roready_1_208 & out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3832 = out_f_roready_354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_354 = out_wivalid_1_208 & out_wimask_354; // @[RegisterRouter.scala:87:24] wire out_f_woready_354 = out_woready_1_208 & out_womask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3833 = ~out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3834 = ~out_wimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3835 = ~out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3836 = ~out_womask_354; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3838 = _out_T_3837; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_294 = _out_T_3838; // @[RegisterRouter.scala:87:24] wire out_rimask_355 = \|_out_rimask_T_355; // @[RegisterRouter.scala:87:24] wire out_wimask_355 = &_out_wimask_T_355; // @[RegisterRouter.scala:87:24] wire out_romask_355 = \|_out_romask_T_355; // @[RegisterRouter.scala:87:24] wire out_womask_355 = &_out_womask_T_355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_355 = out_rivalid_1_209 & out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3840 = out_f_rivalid_355; // @[RegisterRouter.scala:87:24] wire out_f_roready_355 = out_roready_1_209 & out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3841 = out_f_roready_355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_355 = out_wivalid_1_209 & out_wimask_355; // @[RegisterRouter.scala:87:24] wire out_f_woready_355 = out_woready_1_209 & out_womask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3842 = ~out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3843 = ~out_wimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3844 = ~out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3845 = ~out_womask_355; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_294 = {hi_666, flags_0_go, _out_prepend_T_294}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3846 = out_prepend_294; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3847 = _out_T_3846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_295 = _out_T_3847; // @[RegisterRouter.scala:87:24] wire out_rimask_356 = \|_out_rimask_T_356; // @[RegisterRouter.scala:87:24] wire out_wimask_356 = &_out_wimask_T_356; // @[RegisterRouter.scala:87:24] wire out_romask_356 = \|_out_romask_T_356; // @[RegisterRouter.scala:87:24] wire out_womask_356 = &_out_womask_T_356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_356 = out_rivalid_1_210 & out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3849 = out_f_rivalid_356; // @[RegisterRouter.scala:87:24] wire out_f_roready_356 = out_roready_1_210 & out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3850 = out_f_roready_356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_356 = out_wivalid_1_210 & out_wimask_356; // @[RegisterRouter.scala:87:24] wire out_f_woready_356 = out_woready_1_210 & out_womask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3851 = ~out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3852 = ~out_wimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3853 = ~out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3854 = ~out_womask_356; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_295 = {hi_667, flags_0_go, _out_prepend_T_295}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3855 = out_prepend_295; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3856 = _out_T_3855; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_296 = _out_T_3856; // @[RegisterRouter.scala:87:24] wire out_rimask_357 = \|_out_rimask_T_357; // @[RegisterRouter.scala:87:24] wire out_wimask_357 = &_out_wimask_T_357; // @[RegisterRouter.scala:87:24] wire out_romask_357 = \|_out_romask_T_357; // @[RegisterRouter.scala:87:24] wire out_womask_357 = &_out_womask_T_357; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_357 = out_rivalid_1_211 & out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3858 = out_f_rivalid_357; // @[RegisterRouter.scala:87:24] wire out_f_roready_357 = out_roready_1_211 & out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3859 = out_f_roready_357; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_357 = out_wivalid_1_211 & out_wimask_357; // @[RegisterRouter.scala:87:24] wire out_f_woready_357 = out_woready_1_211 & out_womask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3860 = ~out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3861 = ~out_wimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3862 = ~out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3863 = ~out_womask_357; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_296 = {hi_668, flags_0_go, _out_prepend_T_296}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3864 = out_prepend_296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3865 = _out_T_3864; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_297 = _out_T_3865; // @[RegisterRouter.scala:87:24] wire out_rimask_358 = \|_out_rimask_T_358; // @[RegisterRouter.scala:87:24] wire out_wimask_358 = &_out_wimask_T_358; // @[RegisterRouter.scala:87:24] wire out_romask_358 = \|_out_romask_T_358; // @[RegisterRouter.scala:87:24] wire out_womask_358 = &_out_womask_T_358; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_358 = out_rivalid_1_212 & out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3867 = out_f_rivalid_358; // @[RegisterRouter.scala:87:24] wire out_f_roready_358 = out_roready_1_212 & out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3868 = out_f_roready_358; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_358 = out_wivalid_1_212 & out_wimask_358; // @[RegisterRouter.scala:87:24] wire out_f_woready_358 = out_woready_1_212 & out_womask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3869 = ~out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3870 = ~out_wimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3871 = ~out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3872 = ~out_womask_358; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_297 = {hi_669, flags_0_go, _out_prepend_T_297}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3873 = out_prepend_297; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3874 = _out_T_3873; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_298 = _out_T_3874; // @[RegisterRouter.scala:87:24] wire out_rimask_359 = \|_out_rimask_T_359; // @[RegisterRouter.scala:87:24] wire out_wimask_359 = &_out_wimask_T_359; // @[RegisterRouter.scala:87:24] wire out_romask_359 = \|_out_romask_T_359; // @[RegisterRouter.scala:87:24] wire out_womask_359 = &_out_womask_T_359; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_359 = out_rivalid_1_213 & out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3876 = out_f_rivalid_359; // @[RegisterRouter.scala:87:24] wire out_f_roready_359 = out_roready_1_213 & out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3877 = out_f_roready_359; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_359 = out_wivalid_1_213 & out_wimask_359; // @[RegisterRouter.scala:87:24] wire out_f_woready_359 = out_woready_1_213 & out_womask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3878 = ~out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3879 = ~out_wimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3880 = ~out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3881 = ~out_womask_359; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_298 = {hi_670, flags_0_go, _out_prepend_T_298}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3882 = out_prepend_298; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3883 = _out_T_3882; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_299 = _out_T_3883; // @[RegisterRouter.scala:87:24] wire out_rimask_360 = \|_out_rimask_T_360; // @[RegisterRouter.scala:87:24] wire out_wimask_360 = &_out_wimask_T_360; // @[RegisterRouter.scala:87:24] wire out_romask_360 = \|_out_romask_T_360; // @[RegisterRouter.scala:87:24] wire out_womask_360 = &_out_womask_T_360; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_360 = out_rivalid_1_214 & out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3885 = out_f_rivalid_360; // @[RegisterRouter.scala:87:24] wire out_f_roready_360 = out_roready_1_214 & out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3886 = out_f_roready_360; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_360 = out_wivalid_1_214 & out_wimask_360; // @[RegisterRouter.scala:87:24] wire out_f_woready_360 = out_woready_1_214 & out_womask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3887 = ~out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3888 = ~out_wimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3889 = ~out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3890 = ~out_womask_360; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_299 = {hi_671, flags_0_go, _out_prepend_T_299}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3891 = out_prepend_299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3892 = _out_T_3891; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_300 = _out_T_3892; // @[RegisterRouter.scala:87:24] wire out_rimask_361 = \|_out_rimask_T_361; // @[RegisterRouter.scala:87:24] wire out_wimask_361 = &_out_wimask_T_361; // @[RegisterRouter.scala:87:24] wire out_romask_361 = \|_out_romask_T_361; // @[RegisterRouter.scala:87:24] wire out_womask_361 = &_out_womask_T_361; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_361 = out_rivalid_1_215 & out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3894 = out_f_rivalid_361; // @[RegisterRouter.scala:87:24] wire out_f_roready_361 = out_roready_1_215 & out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3895 = out_f_roready_361; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_361 = out_wivalid_1_215 & out_wimask_361; // @[RegisterRouter.scala:87:24] wire out_f_woready_361 = out_woready_1_215 & out_womask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3896 = ~out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3897 = ~out_wimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3898 = ~out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3899 = ~out_womask_361; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_300 = {hi_672, flags_0_go, _out_prepend_T_300}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3900 = out_prepend_300; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3901 = _out_T_3900; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_211 = _out_T_3901; // @[MuxLiteral.scala:49:48] wire out_rimask_362 = \|_out_rimask_T_362; // @[RegisterRouter.scala:87:24] wire out_wimask_362 = &_out_wimask_T_362; // @[RegisterRouter.scala:87:24] wire out_romask_362 = \|_out_romask_T_362; // @[RegisterRouter.scala:87:24] wire out_womask_362 = &_out_womask_T_362; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_362 = out_rivalid_1_216 & out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3903 = out_f_rivalid_362; // @[RegisterRouter.scala:87:24] wire out_f_roready_362 = out_roready_1_216 & out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3904 = out_f_roready_362; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_362 = out_wivalid_1_216 & out_wimask_362; // @[RegisterRouter.scala:87:24] wire out_f_woready_362 = out_woready_1_216 & out_womask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3905 = ~out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3906 = ~out_wimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3907 = ~out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3908 = ~out_womask_362; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3910 = _out_T_3909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_301 = _out_T_3910; // @[RegisterRouter.scala:87:24] wire out_rimask_363 = \|_out_rimask_T_363; // @[RegisterRouter.scala:87:24] wire out_wimask_363 = &_out_wimask_T_363; // @[RegisterRouter.scala:87:24] wire out_romask_363 = \|_out_romask_T_363; // @[RegisterRouter.scala:87:24] wire out_womask_363 = &_out_womask_T_363; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_363 = out_rivalid_1_217 & out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3912 = out_f_rivalid_363; // @[RegisterRouter.scala:87:24] wire out_f_roready_363 = out_roready_1_217 & out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3913 = out_f_roready_363; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_363 = out_wivalid_1_217 & out_wimask_363; // @[RegisterRouter.scala:87:24] wire out_f_woready_363 = out_woready_1_217 & out_womask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3914 = ~out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3915 = ~out_wimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3916 = ~out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3917 = ~out_womask_363; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_301 = {hi_1002, flags_0_go, _out_prepend_T_301}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3918 = out_prepend_301; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3919 = _out_T_3918; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_302 = _out_T_3919; // @[RegisterRouter.scala:87:24] wire out_rimask_364 = \|_out_rimask_T_364; // @[RegisterRouter.scala:87:24] wire out_wimask_364 = &_out_wimask_T_364; // @[RegisterRouter.scala:87:24] wire out_romask_364 = \|_out_romask_T_364; // @[RegisterRouter.scala:87:24] wire out_womask_364 = &_out_womask_T_364; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_364 = out_rivalid_1_218 & out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3921 = out_f_rivalid_364; // @[RegisterRouter.scala:87:24] wire out_f_roready_364 = out_roready_1_218 & out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3922 = out_f_roready_364; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_364 = out_wivalid_1_218 & out_wimask_364; // @[RegisterRouter.scala:87:24] wire out_f_woready_364 = out_woready_1_218 & out_womask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3923 = ~out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3924 = ~out_wimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3925 = ~out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3926 = ~out_womask_364; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_302 = {hi_1003, flags_0_go, _out_prepend_T_302}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3927 = out_prepend_302; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3928 = _out_T_3927; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_303 = _out_T_3928; // @[RegisterRouter.scala:87:24] wire out_rimask_365 = \|_out_rimask_T_365; // @[RegisterRouter.scala:87:24] wire out_wimask_365 = &_out_wimask_T_365; // @[RegisterRouter.scala:87:24] wire out_romask_365 = \|_out_romask_T_365; // @[RegisterRouter.scala:87:24] wire out_womask_365 = &_out_womask_T_365; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_365 = out_rivalid_1_219 & out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3930 = out_f_rivalid_365; // @[RegisterRouter.scala:87:24] wire out_f_roready_365 = out_roready_1_219 & out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3931 = out_f_roready_365; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_365 = out_wivalid_1_219 & out_wimask_365; // @[RegisterRouter.scala:87:24] wire out_f_woready_365 = out_woready_1_219 & out_womask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3932 = ~out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3933 = ~out_wimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3934 = ~out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3935 = ~out_womask_365; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_303 = {hi_1004, flags_0_go, _out_prepend_T_303}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3936 = out_prepend_303; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3937 = _out_T_3936; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_304 = _out_T_3937; // @[RegisterRouter.scala:87:24] wire out_rimask_366 = \|_out_rimask_T_366; // @[RegisterRouter.scala:87:24] wire out_wimask_366 = &_out_wimask_T_366; // @[RegisterRouter.scala:87:24] wire out_romask_366 = \|_out_romask_T_366; // @[RegisterRouter.scala:87:24] wire out_womask_366 = &_out_womask_T_366; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_366 = out_rivalid_1_220 & out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3939 = out_f_rivalid_366; // @[RegisterRouter.scala:87:24] wire out_f_roready_366 = out_roready_1_220 & out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3940 = out_f_roready_366; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_366 = out_wivalid_1_220 & out_wimask_366; // @[RegisterRouter.scala:87:24] wire out_f_woready_366 = out_woready_1_220 & out_womask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3941 = ~out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3942 = ~out_wimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3943 = ~out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3944 = ~out_womask_366; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_304 = {hi_1005, flags_0_go, _out_prepend_T_304}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3945 = out_prepend_304; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3946 = _out_T_3945; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_305 = _out_T_3946; // @[RegisterRouter.scala:87:24] wire out_rimask_367 = \|_out_rimask_T_367; // @[RegisterRouter.scala:87:24] wire out_wimask_367 = &_out_wimask_T_367; // @[RegisterRouter.scala:87:24] wire out_romask_367 = \|_out_romask_T_367; // @[RegisterRouter.scala:87:24] wire out_womask_367 = &_out_womask_T_367; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_367 = out_rivalid_1_221 & out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3948 = out_f_rivalid_367; // @[RegisterRouter.scala:87:24] wire out_f_roready_367 = out_roready_1_221 & out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3949 = out_f_roready_367; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_367 = out_wivalid_1_221 & out_wimask_367; // @[RegisterRouter.scala:87:24] wire out_f_woready_367 = out_woready_1_221 & out_womask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3950 = ~out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3951 = ~out_wimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3952 = ~out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3953 = ~out_womask_367; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_305 = {hi_1006, flags_0_go, _out_prepend_T_305}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3954 = out_prepend_305; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3955 = _out_T_3954; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_306 = _out_T_3955; // @[RegisterRouter.scala:87:24] wire out_rimask_368 = \|_out_rimask_T_368; // @[RegisterRouter.scala:87:24] wire out_wimask_368 = &_out_wimask_T_368; // @[RegisterRouter.scala:87:24] wire out_romask_368 = \|_out_romask_T_368; // @[RegisterRouter.scala:87:24] wire out_womask_368 = &_out_womask_T_368; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_368 = out_rivalid_1_222 & out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3957 = out_f_rivalid_368; // @[RegisterRouter.scala:87:24] wire out_f_roready_368 = out_roready_1_222 & out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3958 = out_f_roready_368; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_368 = out_wivalid_1_222 & out_wimask_368; // @[RegisterRouter.scala:87:24] wire out_f_woready_368 = out_woready_1_222 & out_womask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3959 = ~out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3960 = ~out_wimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3961 = ~out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3962 = ~out_womask_368; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_306 = {hi_1007, flags_0_go, _out_prepend_T_306}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3963 = out_prepend_306; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3964 = _out_T_3963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_307 = _out_T_3964; // @[RegisterRouter.scala:87:24] wire out_rimask_369 = \|_out_rimask_T_369; // @[RegisterRouter.scala:87:24] wire out_wimask_369 = &_out_wimask_T_369; // @[RegisterRouter.scala:87:24] wire out_romask_369 = \|_out_romask_T_369; // @[RegisterRouter.scala:87:24] wire out_womask_369 = &_out_womask_T_369; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_369 = out_rivalid_1_223 & out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3966 = out_f_rivalid_369; // @[RegisterRouter.scala:87:24] wire out_f_roready_369 = out_roready_1_223 & out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3967 = out_f_roready_369; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_369 = out_wivalid_1_223 & out_wimask_369; // @[RegisterRouter.scala:87:24] wire out_f_woready_369 = out_woready_1_223 & out_womask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3968 = ~out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3969 = ~out_wimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3970 = ~out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3971 = ~out_womask_369; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_307 = {hi_1008, flags_0_go, _out_prepend_T_307}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3972 = out_prepend_307; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3973 = _out_T_3972; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_253 = _out_T_3973; // @[MuxLiteral.scala:49:48] wire out_rimask_370 = \|_out_rimask_T_370; // @[RegisterRouter.scala:87:24] wire out_wimask_370 = &_out_wimask_T_370; // @[RegisterRouter.scala:87:24] wire out_romask_370 = \|_out_romask_T_370; // @[RegisterRouter.scala:87:24] wire out_womask_370 = &_out_womask_T_370; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_370 = out_rivalid_1_224 & out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3975 = out_f_rivalid_370; // @[RegisterRouter.scala:87:24] wire out_f_roready_370 = out_roready_1_224 & out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3976 = out_f_roready_370; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_370 = out_wivalid_1_224 & out_wimask_370; // @[RegisterRouter.scala:87:24] wire out_f_woready_370 = out_woready_1_224 & out_womask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3977 = ~out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3978 = ~out_wimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3979 = ~out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3980 = ~out_womask_370; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3982 = _out_T_3981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_308 = _out_T_3982; // @[RegisterRouter.scala:87:24] wire out_rimask_371 = \|_out_rimask_T_371; // @[RegisterRouter.scala:87:24] wire out_wimask_371 = &_out_wimask_T_371; // @[RegisterRouter.scala:87:24] wire out_romask_371 = \|_out_romask_T_371; // @[RegisterRouter.scala:87:24] wire out_womask_371 = &_out_womask_T_371; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_371 = out_rivalid_1_225 & out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3984 = out_f_rivalid_371; // @[RegisterRouter.scala:87:24] wire out_f_roready_371 = out_roready_1_225 & out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3985 = out_f_roready_371; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_371 = out_wivalid_1_225 & out_wimask_371; // @[RegisterRouter.scala:87:24] wire out_f_woready_371 = out_woready_1_225 & out_womask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3986 = ~out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3987 = ~out_wimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3988 = ~out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3989 = ~out_womask_371; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_308 = {hi_154, flags_0_go, _out_prepend_T_308}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3990 = out_prepend_308; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3991 = _out_T_3990; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_309 = _out_T_3991; // @[RegisterRouter.scala:87:24] wire out_rimask_372 = \|_out_rimask_T_372; // @[RegisterRouter.scala:87:24] wire out_wimask_372 = &_out_wimask_T_372; // @[RegisterRouter.scala:87:24] wire out_romask_372 = \|_out_romask_T_372; // @[RegisterRouter.scala:87:24] wire out_womask_372 = &_out_womask_T_372; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_372 = out_rivalid_1_226 & out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3993 = out_f_rivalid_372; // @[RegisterRouter.scala:87:24] wire out_f_roready_372 = out_roready_1_226 & out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3994 = out_f_roready_372; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_372 = out_wivalid_1_226 & out_wimask_372; // @[RegisterRouter.scala:87:24] wire out_f_woready_372 = out_woready_1_226 & out_womask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3995 = ~out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3996 = ~out_wimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3997 = ~out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3998 = ~out_womask_372; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_309 = {hi_155, flags_0_go, _out_prepend_T_309}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3999 = out_prepend_309; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4000 = _out_T_3999; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_310 = _out_T_4000; // @[RegisterRouter.scala:87:24] wire out_rimask_373 = \|_out_rimask_T_373; // @[RegisterRouter.scala:87:24] wire out_wimask_373 = &_out_wimask_T_373; // @[RegisterRouter.scala:87:24] wire out_romask_373 = \|_out_romask_T_373; // @[RegisterRouter.scala:87:24] wire out_womask_373 = &_out_womask_T_373; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_373 = out_rivalid_1_227 & out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4002 = out_f_rivalid_373; // @[RegisterRouter.scala:87:24] wire out_f_roready_373 = out_roready_1_227 & out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4003 = out_f_roready_373; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_373 = out_wivalid_1_227 & out_wimask_373; // @[RegisterRouter.scala:87:24] wire out_f_woready_373 = out_woready_1_227 & out_womask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4004 = ~out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4005 = ~out_wimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4006 = ~out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4007 = ~out_womask_373; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_310 = {hi_156, flags_0_go, _out_prepend_T_310}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4008 = out_prepend_310; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4009 = _out_T_4008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_311 = _out_T_4009; // @[RegisterRouter.scala:87:24] wire out_rimask_374 = \|_out_rimask_T_374; // @[RegisterRouter.scala:87:24] wire out_wimask_374 = &_out_wimask_T_374; // @[RegisterRouter.scala:87:24] wire out_romask_374 = \|_out_romask_T_374; // @[RegisterRouter.scala:87:24] wire out_womask_374 = &_out_womask_T_374; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_374 = out_rivalid_1_228 & out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4011 = out_f_rivalid_374; // @[RegisterRouter.scala:87:24] wire out_f_roready_374 = out_roready_1_228 & out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4012 = out_f_roready_374; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_374 = out_wivalid_1_228 & out_wimask_374; // @[RegisterRouter.scala:87:24] wire out_f_woready_374 = out_woready_1_228 & out_womask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4013 = ~out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4014 = ~out_wimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4015 = ~out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4016 = ~out_womask_374; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_311 = {hi_157, flags_0_go, _out_prepend_T_311}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4017 = out_prepend_311; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4018 = _out_T_4017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_312 = _out_T_4018; // @[RegisterRouter.scala:87:24] wire out_rimask_375 = \|_out_rimask_T_375; // @[RegisterRouter.scala:87:24] wire out_wimask_375 = &_out_wimask_T_375; // @[RegisterRouter.scala:87:24] wire out_romask_375 = \|_out_romask_T_375; // @[RegisterRouter.scala:87:24] wire out_womask_375 = &_out_womask_T_375; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_375 = out_rivalid_1_229 & out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4020 = out_f_rivalid_375; // @[RegisterRouter.scala:87:24] wire out_f_roready_375 = out_roready_1_229 & out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4021 = out_f_roready_375; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_375 = out_wivalid_1_229 & out_wimask_375; // @[RegisterRouter.scala:87:24] wire out_f_woready_375 = out_woready_1_229 & out_womask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4022 = ~out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4023 = ~out_wimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4024 = ~out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4025 = ~out_womask_375; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_312 = {hi_158, flags_0_go, _out_prepend_T_312}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4026 = out_prepend_312; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4027 = _out_T_4026; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_313 = _out_T_4027; // @[RegisterRouter.scala:87:24] wire out_rimask_376 = \|_out_rimask_T_376; // @[RegisterRouter.scala:87:24] wire out_wimask_376 = &_out_wimask_T_376; // @[RegisterRouter.scala:87:24] wire out_romask_376 = \|_out_romask_T_376; // @[RegisterRouter.scala:87:24] wire out_womask_376 = &_out_womask_T_376; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_376 = out_rivalid_1_230 & out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4029 = out_f_rivalid_376; // @[RegisterRouter.scala:87:24] wire out_f_roready_376 = out_roready_1_230 & out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4030 = out_f_roready_376; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_376 = out_wivalid_1_230 & out_wimask_376; // @[RegisterRouter.scala:87:24] wire out_f_woready_376 = out_woready_1_230 & out_womask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4031 = ~out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4032 = ~out_wimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4033 = ~out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4034 = ~out_womask_376; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_313 = {hi_159, flags_0_go, _out_prepend_T_313}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4035 = out_prepend_313; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4036 = _out_T_4035; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_314 = _out_T_4036; // @[RegisterRouter.scala:87:24] wire out_rimask_377 = \|_out_rimask_T_377; // @[RegisterRouter.scala:87:24] wire out_wimask_377 = &_out_wimask_T_377; // @[RegisterRouter.scala:87:24] wire out_romask_377 = \|_out_romask_T_377; // @[RegisterRouter.scala:87:24] wire out_womask_377 = &_out_womask_T_377; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_377 = out_rivalid_1_231 & out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4038 = out_f_rivalid_377; // @[RegisterRouter.scala:87:24] wire out_f_roready_377 = out_roready_1_231 & out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4039 = out_f_roready_377; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_377 = out_wivalid_1_231 & out_wimask_377; // @[RegisterRouter.scala:87:24] wire out_f_woready_377 = out_woready_1_231 & out_womask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4040 = ~out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4041 = ~out_wimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4042 = ~out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4043 = ~out_womask_377; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_314 = {hi_160, flags_0_go, _out_prepend_T_314}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4044 = out_prepend_314; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4045 = _out_T_4044; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_147 = _out_T_4045; // @[MuxLiteral.scala:49:48] wire out_rimask_378 = \|_out_rimask_T_378; // @[RegisterRouter.scala:87:24] wire out_wimask_378 = &_out_wimask_T_378; // @[RegisterRouter.scala:87:24] wire out_romask_378 = \|_out_romask_T_378; // @[RegisterRouter.scala:87:24] wire out_womask_378 = &_out_womask_T_378; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_378 = out_rivalid_1_232 & out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4047 = out_f_rivalid_378; // @[RegisterRouter.scala:87:24] wire out_f_roready_378 = out_roready_1_232 & out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4048 = out_f_roready_378; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_378 = out_wivalid_1_232 & out_wimask_378; // @[RegisterRouter.scala:87:24] wire out_f_woready_378 = out_woready_1_232 & out_womask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4049 = ~out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4050 = ~out_wimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4051 = ~out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4052 = ~out_womask_378; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4054 = _out_T_4053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_315 = _out_T_4054; // @[RegisterRouter.scala:87:24] wire out_rimask_379 = \|_out_rimask_T_379; // @[RegisterRouter.scala:87:24] wire out_wimask_379 = &_out_wimask_T_379; // @[RegisterRouter.scala:87:24] wire out_romask_379 = \|_out_romask_T_379; // @[RegisterRouter.scala:87:24] wire out_womask_379 = &_out_womask_T_379; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_379 = out_rivalid_1_233 & out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4056 = out_f_rivalid_379; // @[RegisterRouter.scala:87:24] wire out_f_roready_379 = out_roready_1_233 & out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4057 = out_f_roready_379; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_379 = out_wivalid_1_233 & out_wimask_379; // @[RegisterRouter.scala:87:24] wire out_f_woready_379 = out_woready_1_233 & out_womask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4058 = ~out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4059 = ~out_wimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4060 = ~out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4061 = ~out_womask_379; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_315 = {hi_746, flags_0_go, _out_prepend_T_315}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4062 = out_prepend_315; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4063 = _out_T_4062; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_316 = _out_T_4063; // @[RegisterRouter.scala:87:24] wire out_rimask_380 = \|_out_rimask_T_380; // @[RegisterRouter.scala:87:24] wire out_wimask_380 = &_out_wimask_T_380; // @[RegisterRouter.scala:87:24] wire out_romask_380 = \|_out_romask_T_380; // @[RegisterRouter.scala:87:24] wire out_womask_380 = &_out_womask_T_380; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_380 = out_rivalid_1_234 & out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4065 = out_f_rivalid_380; // @[RegisterRouter.scala:87:24] wire out_f_roready_380 = out_roready_1_234 & out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4066 = out_f_roready_380; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_380 = out_wivalid_1_234 & out_wimask_380; // @[RegisterRouter.scala:87:24] wire out_f_woready_380 = out_woready_1_234 & out_womask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4067 = ~out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4068 = ~out_wimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4069 = ~out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4070 = ~out_womask_380; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_316 = {hi_747, flags_0_go, _out_prepend_T_316}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4071 = out_prepend_316; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4072 = _out_T_4071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_317 = _out_T_4072; // @[RegisterRouter.scala:87:24] wire out_rimask_381 = \|_out_rimask_T_381; // @[RegisterRouter.scala:87:24] wire out_wimask_381 = &_out_wimask_T_381; // @[RegisterRouter.scala:87:24] wire out_romask_381 = \|_out_romask_T_381; // @[RegisterRouter.scala:87:24] wire out_womask_381 = &_out_womask_T_381; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_381 = out_rivalid_1_235 & out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4074 = out_f_rivalid_381; // @[RegisterRouter.scala:87:24] wire out_f_roready_381 = out_roready_1_235 & out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4075 = out_f_roready_381; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_381 = out_wivalid_1_235 & out_wimask_381; // @[RegisterRouter.scala:87:24] wire out_f_woready_381 = out_woready_1_235 & out_womask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4076 = ~out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4077 = ~out_wimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4078 = ~out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4079 = ~out_womask_381; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_317 = {hi_748, flags_0_go, _out_prepend_T_317}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4080 = out_prepend_317; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4081 = _out_T_4080; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_318 = _out_T_4081; // @[RegisterRouter.scala:87:24] wire out_rimask_382 = \|_out_rimask_T_382; // @[RegisterRouter.scala:87:24] wire out_wimask_382 = &_out_wimask_T_382; // @[RegisterRouter.scala:87:24] wire out_romask_382 = \|_out_romask_T_382; // @[RegisterRouter.scala:87:24] wire out_womask_382 = &_out_womask_T_382; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_382 = out_rivalid_1_236 & out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4083 = out_f_rivalid_382; // @[RegisterRouter.scala:87:24] wire out_f_roready_382 = out_roready_1_236 & out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4084 = out_f_roready_382; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_382 = out_wivalid_1_236 & out_wimask_382; // @[RegisterRouter.scala:87:24] wire out_f_woready_382 = out_woready_1_236 & out_womask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4085 = ~out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4086 = ~out_wimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4087 = ~out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4088 = ~out_womask_382; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_318 = {hi_749, flags_0_go, _out_prepend_T_318}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4089 = out_prepend_318; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4090 = _out_T_4089; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_319 = _out_T_4090; // @[RegisterRouter.scala:87:24] wire out_rimask_383 = \|_out_rimask_T_383; // @[RegisterRouter.scala:87:24] wire out_wimask_383 = &_out_wimask_T_383; // @[RegisterRouter.scala:87:24] wire out_romask_383 = \|_out_romask_T_383; // @[RegisterRouter.scala:87:24] wire out_womask_383 = &_out_womask_T_383; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_383 = out_rivalid_1_237 & out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4092 = out_f_rivalid_383; // @[RegisterRouter.scala:87:24] wire out_f_roready_383 = out_roready_1_237 & out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4093 = out_f_roready_383; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_383 = out_wivalid_1_237 & out_wimask_383; // @[RegisterRouter.scala:87:24] wire out_f_woready_383 = out_woready_1_237 & out_womask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4094 = ~out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4095 = ~out_wimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4096 = ~out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4097 = ~out_womask_383; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_319 = {hi_750, flags_0_go, _out_prepend_T_319}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4098 = out_prepend_319; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4099 = _out_T_4098; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_320 = _out_T_4099; // @[RegisterRouter.scala:87:24] wire out_rimask_384 = \|_out_rimask_T_384; // @[RegisterRouter.scala:87:24] wire out_wimask_384 = &_out_wimask_T_384; // @[RegisterRouter.scala:87:24] wire out_romask_384 = \|_out_romask_T_384; // @[RegisterRouter.scala:87:24] wire out_womask_384 = &_out_womask_T_384; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_384 = out_rivalid_1_238 & out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4101 = out_f_rivalid_384; // @[RegisterRouter.scala:87:24] wire out_f_roready_384 = out_roready_1_238 & out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4102 = out_f_roready_384; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_384 = out_wivalid_1_238 & out_wimask_384; // @[RegisterRouter.scala:87:24] wire out_f_woready_384 = out_woready_1_238 & out_womask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4103 = ~out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4104 = ~out_wimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4105 = ~out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4106 = ~out_womask_384; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_320 = {hi_751, flags_0_go, _out_prepend_T_320}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4107 = out_prepend_320; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4108 = _out_T_4107; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_321 = _out_T_4108; // @[RegisterRouter.scala:87:24] wire out_rimask_385 = \|_out_rimask_T_385; // @[RegisterRouter.scala:87:24] wire out_wimask_385 = &_out_wimask_T_385; // @[RegisterRouter.scala:87:24] wire out_romask_385 = \|_out_romask_T_385; // @[RegisterRouter.scala:87:24] wire out_womask_385 = &_out_womask_T_385; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_385 = out_rivalid_1_239 & out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4110 = out_f_rivalid_385; // @[RegisterRouter.scala:87:24] wire out_f_roready_385 = out_roready_1_239 & out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4111 = out_f_roready_385; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_385 = out_wivalid_1_239 & out_wimask_385; // @[RegisterRouter.scala:87:24] wire out_f_woready_385 = out_woready_1_239 & out_womask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4112 = ~out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4113 = ~out_wimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4114 = ~out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4115 = ~out_womask_385; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_321 = {hi_752, flags_0_go, _out_prepend_T_321}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4116 = out_prepend_321; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4117 = _out_T_4116; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_221 = _out_T_4117; // @[MuxLiteral.scala:49:48] wire out_rimask_386 = \|_out_rimask_T_386; // @[RegisterRouter.scala:87:24] wire out_wimask_386 = &_out_wimask_T_386; // @[RegisterRouter.scala:87:24] wire out_romask_386 = \|_out_romask_T_386; // @[RegisterRouter.scala:87:24] wire out_womask_386 = &_out_womask_T_386; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_386 = out_rivalid_1_240 & out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4119 = out_f_rivalid_386; // @[RegisterRouter.scala:87:24] wire out_f_roready_386 = out_roready_1_240 & out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4120 = out_f_roready_386; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_386 = out_wivalid_1_240 & out_wimask_386; // @[RegisterRouter.scala:87:24] wire out_f_woready_386 = out_woready_1_240 & out_womask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4121 = ~out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4122 = ~out_wimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4123 = ~out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4124 = ~out_womask_386; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4126 = _out_T_4125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_322 = _out_T_4126; // @[RegisterRouter.scala:87:24] wire out_rimask_387 = \|_out_rimask_T_387; // @[RegisterRouter.scala:87:24] wire out_wimask_387 = &_out_wimask_T_387; // @[RegisterRouter.scala:87:24] wire out_romask_387 = \|_out_romask_T_387; // @[RegisterRouter.scala:87:24] wire out_womask_387 = &_out_womask_T_387; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_387 = out_rivalid_1_241 & out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4128 = out_f_rivalid_387; // @[RegisterRouter.scala:87:24] wire out_f_roready_387 = out_roready_1_241 & out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4129 = out_f_roready_387; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_387 = out_wivalid_1_241 & out_wimask_387; // @[RegisterRouter.scala:87:24] wire out_f_woready_387 = out_woready_1_241 & out_womask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4130 = ~out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4131 = ~out_wimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4132 = ~out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4133 = ~out_womask_387; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_322 = {hi_34, flags_0_go, _out_prepend_T_322}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4134 = out_prepend_322; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4135 = _out_T_4134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_323 = _out_T_4135; // @[RegisterRouter.scala:87:24] wire out_rimask_388 = \|_out_rimask_T_388; // @[RegisterRouter.scala:87:24] wire out_wimask_388 = &_out_wimask_T_388; // @[RegisterRouter.scala:87:24] wire out_romask_388 = \|_out_romask_T_388; // @[RegisterRouter.scala:87:24] wire out_womask_388 = &_out_womask_T_388; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_388 = out_rivalid_1_242 & out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4137 = out_f_rivalid_388; // @[RegisterRouter.scala:87:24] wire out_f_roready_388 = out_roready_1_242 & out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4138 = out_f_roready_388; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_388 = out_wivalid_1_242 & out_wimask_388; // @[RegisterRouter.scala:87:24] wire out_f_woready_388 = out_woready_1_242 & out_womask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4139 = ~out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4140 = ~out_wimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4141 = ~out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4142 = ~out_womask_388; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_323 = {hi_35, flags_0_go, _out_prepend_T_323}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4143 = out_prepend_323; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4144 = _out_T_4143; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_324 = _out_T_4144; // @[RegisterRouter.scala:87:24] wire out_rimask_389 = \|_out_rimask_T_389; // @[RegisterRouter.scala:87:24] wire out_wimask_389 = &_out_wimask_T_389; // @[RegisterRouter.scala:87:24] wire out_romask_389 = \|_out_romask_T_389; // @[RegisterRouter.scala:87:24] wire out_womask_389 = &_out_womask_T_389; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_389 = out_rivalid_1_243 & out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4146 = out_f_rivalid_389; // @[RegisterRouter.scala:87:24] wire out_f_roready_389 = out_roready_1_243 & out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4147 = out_f_roready_389; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_389 = out_wivalid_1_243 & out_wimask_389; // @[RegisterRouter.scala:87:24] wire out_f_woready_389 = out_woready_1_243 & out_womask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4148 = ~out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4149 = ~out_wimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4150 = ~out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4151 = ~out_womask_389; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_324 = {hi_36, flags_0_go, _out_prepend_T_324}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4152 = out_prepend_324; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4153 = _out_T_4152; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_325 = _out_T_4153; // @[RegisterRouter.scala:87:24] wire out_rimask_390 = \|_out_rimask_T_390; // @[RegisterRouter.scala:87:24] wire out_wimask_390 = &_out_wimask_T_390; // @[RegisterRouter.scala:87:24] wire out_romask_390 = \|_out_romask_T_390; // @[RegisterRouter.scala:87:24] wire out_womask_390 = &_out_womask_T_390; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_390 = out_rivalid_1_244 & out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4155 = out_f_rivalid_390; // @[RegisterRouter.scala:87:24] wire out_f_roready_390 = out_roready_1_244 & out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4156 = out_f_roready_390; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_390 = out_wivalid_1_244 & out_wimask_390; // @[RegisterRouter.scala:87:24] wire out_f_woready_390 = out_woready_1_244 & out_womask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4157 = ~out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4158 = ~out_wimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4159 = ~out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4160 = ~out_womask_390; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_325 = {hi_37, flags_0_go, _out_prepend_T_325}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4161 = out_prepend_325; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4162 = _out_T_4161; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_326 = _out_T_4162; // @[RegisterRouter.scala:87:24] wire out_rimask_391 = \|_out_rimask_T_391; // @[RegisterRouter.scala:87:24] wire out_wimask_391 = &_out_wimask_T_391; // @[RegisterRouter.scala:87:24] wire out_romask_391 = \|_out_romask_T_391; // @[RegisterRouter.scala:87:24] wire out_womask_391 = &_out_womask_T_391; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_391 = out_rivalid_1_245 & out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4164 = out_f_rivalid_391; // @[RegisterRouter.scala:87:24] wire out_f_roready_391 = out_roready_1_245 & out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4165 = out_f_roready_391; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_391 = out_wivalid_1_245 & out_wimask_391; // @[RegisterRouter.scala:87:24] wire out_f_woready_391 = out_woready_1_245 & out_womask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4166 = ~out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4167 = ~out_wimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4168 = ~out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4169 = ~out_womask_391; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_326 = {hi_38, flags_0_go, _out_prepend_T_326}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4170 = out_prepend_326; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4171 = _out_T_4170; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_327 = _out_T_4171; // @[RegisterRouter.scala:87:24] wire out_rimask_392 = \|_out_rimask_T_392; // @[RegisterRouter.scala:87:24] wire out_wimask_392 = &_out_wimask_T_392; // @[RegisterRouter.scala:87:24] wire out_romask_392 = \|_out_romask_T_392; // @[RegisterRouter.scala:87:24] wire out_womask_392 = &_out_womask_T_392; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_392 = out_rivalid_1_246 & out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4173 = out_f_rivalid_392; // @[RegisterRouter.scala:87:24] wire out_f_roready_392 = out_roready_1_246 & out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4174 = out_f_roready_392; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_392 = out_wivalid_1_246 & out_wimask_392; // @[RegisterRouter.scala:87:24] wire out_f_woready_392 = out_woready_1_246 & out_womask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4175 = ~out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4176 = ~out_wimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4177 = ~out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4178 = ~out_womask_392; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_327 = {hi_39, flags_0_go, _out_prepend_T_327}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4179 = out_prepend_327; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4180 = _out_T_4179; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_328 = _out_T_4180; // @[RegisterRouter.scala:87:24] wire out_rimask_393 = \|_out_rimask_T_393; // @[RegisterRouter.scala:87:24] wire out_wimask_393 = &_out_wimask_T_393; // @[RegisterRouter.scala:87:24] wire out_romask_393 = \|_out_romask_T_393; // @[RegisterRouter.scala:87:24] wire out_womask_393 = &_out_womask_T_393; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_393 = out_rivalid_1_247 & out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4182 = out_f_rivalid_393; // @[RegisterRouter.scala:87:24] wire out_f_roready_393 = out_roready_1_247 & out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4183 = out_f_roready_393; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_393 = out_wivalid_1_247 & out_wimask_393; // @[RegisterRouter.scala:87:24] wire out_f_woready_393 = out_woready_1_247 & out_womask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4184 = ~out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4185 = ~out_wimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4186 = ~out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4187 = ~out_womask_393; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_328 = {hi_40, flags_0_go, _out_prepend_T_328}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4188 = out_prepend_328; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4189 = _out_T_4188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_132 = _out_T_4189; // @[MuxLiteral.scala:49:48] wire out_rimask_394 = \|_out_rimask_T_394; // @[RegisterRouter.scala:87:24] wire out_wimask_394 = &_out_wimask_T_394; // @[RegisterRouter.scala:87:24] wire out_romask_394 = \|_out_romask_T_394; // @[RegisterRouter.scala:87:24] wire out_womask_394 = &_out_womask_T_394; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_394 = out_rivalid_1_248 & out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4191 = out_f_rivalid_394; // @[RegisterRouter.scala:87:24] wire out_f_roready_394 = out_roready_1_248 & out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4192 = out_f_roready_394; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_394 = out_wivalid_1_248 & out_wimask_394; // @[RegisterRouter.scala:87:24] wire out_f_woready_394 = out_woready_1_248 & out_womask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4193 = ~out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4194 = ~out_wimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4195 = ~out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4196 = ~out_womask_394; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4198 = _out_T_4197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_329 = _out_T_4198; // @[RegisterRouter.scala:87:24] wire out_rimask_395 = \|_out_rimask_T_395; // @[RegisterRouter.scala:87:24] wire out_wimask_395 = &_out_wimask_T_395; // @[RegisterRouter.scala:87:24] wire out_romask_395 = \|_out_romask_T_395; // @[RegisterRouter.scala:87:24] wire out_womask_395 = &_out_womask_T_395; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_395 = out_rivalid_1_249 & out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4200 = out_f_rivalid_395; // @[RegisterRouter.scala:87:24] wire out_f_roready_395 = out_roready_1_249 & out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4201 = out_f_roready_395; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_395 = out_wivalid_1_249 & out_wimask_395; // @[RegisterRouter.scala:87:24] wire out_f_woready_395 = out_woready_1_249 & out_womask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4202 = ~out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4203 = ~out_wimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4204 = ~out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4205 = ~out_womask_395; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_329 = {hi_42, flags_0_go, _out_prepend_T_329}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4206 = out_prepend_329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4207 = _out_T_4206; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_330 = _out_T_4207; // @[RegisterRouter.scala:87:24] wire out_rimask_396 = \|_out_rimask_T_396; // @[RegisterRouter.scala:87:24] wire out_wimask_396 = &_out_wimask_T_396; // @[RegisterRouter.scala:87:24] wire out_romask_396 = \|_out_romask_T_396; // @[RegisterRouter.scala:87:24] wire out_womask_396 = &_out_womask_T_396; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_396 = out_rivalid_1_250 & out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4209 = out_f_rivalid_396; // @[RegisterRouter.scala:87:24] wire out_f_roready_396 = out_roready_1_250 & out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4210 = out_f_roready_396; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_396 = out_wivalid_1_250 & out_wimask_396; // @[RegisterRouter.scala:87:24] wire out_f_woready_396 = out_woready_1_250 & out_womask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4211 = ~out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4212 = ~out_wimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4213 = ~out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4214 = ~out_womask_396; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_330 = {hi_43, flags_0_go, _out_prepend_T_330}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4215 = out_prepend_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4216 = _out_T_4215; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_331 = _out_T_4216; // @[RegisterRouter.scala:87:24] wire out_rimask_397 = \|_out_rimask_T_397; // @[RegisterRouter.scala:87:24] wire out_wimask_397 = &_out_wimask_T_397; // @[RegisterRouter.scala:87:24] wire out_romask_397 = \|_out_romask_T_397; // @[RegisterRouter.scala:87:24] wire out_womask_397 = &_out_womask_T_397; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_397 = out_rivalid_1_251 & out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4218 = out_f_rivalid_397; // @[RegisterRouter.scala:87:24] wire out_f_roready_397 = out_roready_1_251 & out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4219 = out_f_roready_397; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_397 = out_wivalid_1_251 & out_wimask_397; // @[RegisterRouter.scala:87:24] wire out_f_woready_397 = out_woready_1_251 & out_womask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4220 = ~out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4221 = ~out_wimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4222 = ~out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4223 = ~out_womask_397; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_331 = {hi_44, flags_0_go, _out_prepend_T_331}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4224 = out_prepend_331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4225 = _out_T_4224; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_332 = _out_T_4225; // @[RegisterRouter.scala:87:24] wire out_rimask_398 = \|_out_rimask_T_398; // @[RegisterRouter.scala:87:24] wire out_wimask_398 = &_out_wimask_T_398; // @[RegisterRouter.scala:87:24] wire out_romask_398 = \|_out_romask_T_398; // @[RegisterRouter.scala:87:24] wire out_womask_398 = &_out_womask_T_398; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_398 = out_rivalid_1_252 & out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4227 = out_f_rivalid_398; // @[RegisterRouter.scala:87:24] wire out_f_roready_398 = out_roready_1_252 & out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4228 = out_f_roready_398; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_398 = out_wivalid_1_252 & out_wimask_398; // @[RegisterRouter.scala:87:24] wire out_f_woready_398 = out_woready_1_252 & out_womask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4229 = ~out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4230 = ~out_wimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4231 = ~out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4232 = ~out_womask_398; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_332 = {hi_45, flags_0_go, _out_prepend_T_332}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4233 = out_prepend_332; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4234 = _out_T_4233; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_333 = _out_T_4234; // @[RegisterRouter.scala:87:24] wire out_rimask_399 = \|_out_rimask_T_399; // @[RegisterRouter.scala:87:24] wire out_wimask_399 = &_out_wimask_T_399; // @[RegisterRouter.scala:87:24] wire out_romask_399 = \|_out_romask_T_399; // @[RegisterRouter.scala:87:24] wire out_womask_399 = &_out_womask_T_399; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_399 = out_rivalid_1_253 & out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4236 = out_f_rivalid_399; // @[RegisterRouter.scala:87:24] wire out_f_roready_399 = out_roready_1_253 & out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4237 = out_f_roready_399; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_399 = out_wivalid_1_253 & out_wimask_399; // @[RegisterRouter.scala:87:24] wire out_f_woready_399 = out_woready_1_253 & out_womask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4238 = ~out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4239 = ~out_wimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4240 = ~out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4241 = ~out_womask_399; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_333 = {hi_46, flags_0_go, _out_prepend_T_333}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4242 = out_prepend_333; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4243 = _out_T_4242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_334 = _out_T_4243; // @[RegisterRouter.scala:87:24] wire out_rimask_400 = \|_out_rimask_T_400; // @[RegisterRouter.scala:87:24] wire out_wimask_400 = &_out_wimask_T_400; // @[RegisterRouter.scala:87:24] wire out_romask_400 = \|_out_romask_T_400; // @[RegisterRouter.scala:87:24] wire out_womask_400 = &_out_womask_T_400; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_400 = out_rivalid_1_254 & out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4245 = out_f_rivalid_400; // @[RegisterRouter.scala:87:24] wire out_f_roready_400 = out_roready_1_254 & out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4246 = out_f_roready_400; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_400 = out_wivalid_1_254 & out_wimask_400; // @[RegisterRouter.scala:87:24] wire out_f_woready_400 = out_woready_1_254 & out_womask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4247 = ~out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4248 = ~out_wimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4249 = ~out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4250 = ~out_womask_400; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_334 = {hi_47, flags_0_go, _out_prepend_T_334}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4251 = out_prepend_334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4252 = _out_T_4251; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_335 = _out_T_4252; // @[RegisterRouter.scala:87:24] wire out_rimask_401 = \|_out_rimask_T_401; // @[RegisterRouter.scala:87:24] wire out_wimask_401 = &_out_wimask_T_401; // @[RegisterRouter.scala:87:24] wire out_romask_401 = \|_out_romask_T_401; // @[RegisterRouter.scala:87:24] wire out_womask_401 = &_out_womask_T_401; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_401 = out_rivalid_1_255 & out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4254 = out_f_rivalid_401; // @[RegisterRouter.scala:87:24] wire out_f_roready_401 = out_roready_1_255 & out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4255 = out_f_roready_401; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_401 = out_wivalid_1_255 & out_wimask_401; // @[RegisterRouter.scala:87:24] wire out_f_woready_401 = out_woready_1_255 & out_womask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4256 = ~out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4257 = ~out_wimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4258 = ~out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4259 = ~out_womask_401; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_335 = {hi_48, flags_0_go, _out_prepend_T_335}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4260 = out_prepend_335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4261 = _out_T_4260; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_133 = _out_T_4261; // @[MuxLiteral.scala:49:48] wire out_rimask_402 = \|_out_rimask_T_402; // @[RegisterRouter.scala:87:24] wire out_wimask_402 = &_out_wimask_T_402; // @[RegisterRouter.scala:87:24] wire out_romask_402 = \|_out_romask_T_402; // @[RegisterRouter.scala:87:24] wire out_womask_402 = &_out_womask_T_402; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_402 = out_rivalid_1_256 & out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4263 = out_f_rivalid_402; // @[RegisterRouter.scala:87:24] wire out_f_roready_402 = out_roready_1_256 & out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4264 = out_f_roready_402; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_402 = out_wivalid_1_256 & out_wimask_402; // @[RegisterRouter.scala:87:24] wire out_f_woready_402 = out_woready_1_256 & out_womask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4265 = ~out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4266 = ~out_wimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4267 = ~out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4268 = ~out_womask_402; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4270 = _out_T_4269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_336 = _out_T_4270; // @[RegisterRouter.scala:87:24] wire out_rimask_403 = \|_out_rimask_T_403; // @[RegisterRouter.scala:87:24] wire out_wimask_403 = &_out_wimask_T_403; // @[RegisterRouter.scala:87:24] wire out_romask_403 = \|_out_romask_T_403; // @[RegisterRouter.scala:87:24] wire out_womask_403 = &_out_womask_T_403; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_403 = out_rivalid_1_257 & out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4272 = out_f_rivalid_403; // @[RegisterRouter.scala:87:24] wire out_f_roready_403 = out_roready_1_257 & out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4273 = out_f_roready_403; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_403 = out_wivalid_1_257 & out_wimask_403; // @[RegisterRouter.scala:87:24] wire out_f_woready_403 = out_woready_1_257 & out_womask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4274 = ~out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4275 = ~out_wimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4276 = ~out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4277 = ~out_womask_403; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_336 = {hi_922, flags_0_go, _out_prepend_T_336}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4278 = out_prepend_336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4279 = _out_T_4278; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_337 = _out_T_4279; // @[RegisterRouter.scala:87:24] wire out_rimask_404 = \|_out_rimask_T_404; // @[RegisterRouter.scala:87:24] wire out_wimask_404 = &_out_wimask_T_404; // @[RegisterRouter.scala:87:24] wire out_romask_404 = \|_out_romask_T_404; // @[RegisterRouter.scala:87:24] wire out_womask_404 = &_out_womask_T_404; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_404 = out_rivalid_1_258 & out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4281 = out_f_rivalid_404; // @[RegisterRouter.scala:87:24] wire out_f_roready_404 = out_roready_1_258 & out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4282 = out_f_roready_404; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_404 = out_wivalid_1_258 & out_wimask_404; // @[RegisterRouter.scala:87:24] wire out_f_woready_404 = out_woready_1_258 & out_womask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4283 = ~out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4284 = ~out_wimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4285 = ~out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4286 = ~out_womask_404; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_337 = {hi_923, flags_0_go, _out_prepend_T_337}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4287 = out_prepend_337; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4288 = _out_T_4287; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_338 = _out_T_4288; // @[RegisterRouter.scala:87:24] wire out_rimask_405 = \|_out_rimask_T_405; // @[RegisterRouter.scala:87:24] wire out_wimask_405 = &_out_wimask_T_405; // @[RegisterRouter.scala:87:24] wire out_romask_405 = \|_out_romask_T_405; // @[RegisterRouter.scala:87:24] wire out_womask_405 = &_out_womask_T_405; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_405 = out_rivalid_1_259 & out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4290 = out_f_rivalid_405; // @[RegisterRouter.scala:87:24] wire out_f_roready_405 = out_roready_1_259 & out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4291 = out_f_roready_405; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_405 = out_wivalid_1_259 & out_wimask_405; // @[RegisterRouter.scala:87:24] wire out_f_woready_405 = out_woready_1_259 & out_womask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4292 = ~out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4293 = ~out_wimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4294 = ~out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4295 = ~out_womask_405; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_338 = {hi_924, flags_0_go, _out_prepend_T_338}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4296 = out_prepend_338; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4297 = _out_T_4296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_339 = _out_T_4297; // @[RegisterRouter.scala:87:24] wire out_rimask_406 = \|_out_rimask_T_406; // @[RegisterRouter.scala:87:24] wire out_wimask_406 = &_out_wimask_T_406; // @[RegisterRouter.scala:87:24] wire out_romask_406 = \|_out_romask_T_406; // @[RegisterRouter.scala:87:24] wire out_womask_406 = &_out_womask_T_406; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_406 = out_rivalid_1_260 & out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4299 = out_f_rivalid_406; // @[RegisterRouter.scala:87:24] wire out_f_roready_406 = out_roready_1_260 & out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4300 = out_f_roready_406; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_406 = out_wivalid_1_260 & out_wimask_406; // @[RegisterRouter.scala:87:24] wire out_f_woready_406 = out_woready_1_260 & out_womask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4301 = ~out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4302 = ~out_wimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4303 = ~out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4304 = ~out_womask_406; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_339 = {hi_925, flags_0_go, _out_prepend_T_339}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4305 = out_prepend_339; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4306 = _out_T_4305; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_340 = _out_T_4306; // @[RegisterRouter.scala:87:24] wire out_rimask_407 = \|_out_rimask_T_407; // @[RegisterRouter.scala:87:24] wire out_wimask_407 = &_out_wimask_T_407; // @[RegisterRouter.scala:87:24] wire out_romask_407 = \|_out_romask_T_407; // @[RegisterRouter.scala:87:24] wire out_womask_407 = &_out_womask_T_407; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_407 = out_rivalid_1_261 & out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4308 = out_f_rivalid_407; // @[RegisterRouter.scala:87:24] wire out_f_roready_407 = out_roready_1_261 & out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4309 = out_f_roready_407; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_407 = out_wivalid_1_261 & out_wimask_407; // @[RegisterRouter.scala:87:24] wire out_f_woready_407 = out_woready_1_261 & out_womask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4310 = ~out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4311 = ~out_wimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4312 = ~out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4313 = ~out_womask_407; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_340 = {hi_926, flags_0_go, _out_prepend_T_340}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4314 = out_prepend_340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4315 = _out_T_4314; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_341 = _out_T_4315; // @[RegisterRouter.scala:87:24] wire out_rimask_408 = \|_out_rimask_T_408; // @[RegisterRouter.scala:87:24] wire out_wimask_408 = &_out_wimask_T_408; // @[RegisterRouter.scala:87:24] wire out_romask_408 = \|_out_romask_T_408; // @[RegisterRouter.scala:87:24] wire out_womask_408 = &_out_womask_T_408; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_408 = out_rivalid_1_262 & out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4317 = out_f_rivalid_408; // @[RegisterRouter.scala:87:24] wire out_f_roready_408 = out_roready_1_262 & out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4318 = out_f_roready_408; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_408 = out_wivalid_1_262 & out_wimask_408; // @[RegisterRouter.scala:87:24] wire out_f_woready_408 = out_woready_1_262 & out_womask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4319 = ~out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4320 = ~out_wimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4321 = ~out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4322 = ~out_womask_408; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_341 = {hi_927, flags_0_go, _out_prepend_T_341}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4323 = out_prepend_341; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4324 = _out_T_4323; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_342 = _out_T_4324; // @[RegisterRouter.scala:87:24] wire out_rimask_409 = \|_out_rimask_T_409; // @[RegisterRouter.scala:87:24] wire out_wimask_409 = &_out_wimask_T_409; // @[RegisterRouter.scala:87:24] wire out_romask_409 = \|_out_romask_T_409; // @[RegisterRouter.scala:87:24] wire out_womask_409 = &_out_womask_T_409; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_409 = out_rivalid_1_263 & out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4326 = out_f_rivalid_409; // @[RegisterRouter.scala:87:24] wire out_f_roready_409 = out_roready_1_263 & out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4327 = out_f_roready_409; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_409 = out_wivalid_1_263 & out_wimask_409; // @[RegisterRouter.scala:87:24] wire out_f_woready_409 = out_woready_1_263 & out_womask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4328 = ~out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4329 = ~out_wimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4330 = ~out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4331 = ~out_womask_409; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_342 = {hi_928, flags_0_go, _out_prepend_T_342}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4332 = out_prepend_342; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4333 = _out_T_4332; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_243 = _out_T_4333; // @[MuxLiteral.scala:49:48] wire out_rimask_410 = \|_out_rimask_T_410; // @[RegisterRouter.scala:87:24] wire out_wimask_410 = &_out_wimask_T_410; // @[RegisterRouter.scala:87:24] wire out_romask_410 = \|_out_romask_T_410; // @[RegisterRouter.scala:87:24] wire out_womask_410 = &_out_womask_T_410; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_410 = out_rivalid_1_264 & out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4335 = out_f_rivalid_410; // @[RegisterRouter.scala:87:24] wire out_f_roready_410 = out_roready_1_264 & out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4336 = out_f_roready_410; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_410 = out_wivalid_1_264 & out_wimask_410; // @[RegisterRouter.scala:87:24] wire out_f_woready_410 = out_woready_1_264 & out_womask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4337 = ~out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4338 = ~out_wimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4339 = ~out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4340 = ~out_womask_410; // @[RegisterRouter.scala:87:24] wire out_rimask_411 = \|_out_rimask_T_411; // @[RegisterRouter.scala:87:24] wire out_wimask_411 = &_out_wimask_T_411; // @[RegisterRouter.scala:87:24] wire out_romask_411 = \|_out_romask_T_411; // @[RegisterRouter.scala:87:24] wire out_womask_411 = &_out_womask_T_411; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_411 = out_rivalid_1_265 & out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4344 = out_f_rivalid_411; // @[RegisterRouter.scala:87:24] wire out_f_roready_411 = out_roready_1_265 & out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4345 = out_f_roready_411; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_411 = out_wivalid_1_265 & out_wimask_411; // @[RegisterRouter.scala:87:24] wire out_f_woready_411 = out_woready_1_265 & out_womask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4346 = ~out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4347 = ~out_wimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4348 = ~out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4349 = ~out_womask_411; // @[RegisterRouter.scala:87:24] wire out_rimask_412 = \|_out_rimask_T_412; // @[RegisterRouter.scala:87:24] wire out_wimask_412 = &_out_wimask_T_412; // @[RegisterRouter.scala:87:24] wire out_romask_412 = \|_out_romask_T_412; // @[RegisterRouter.scala:87:24] wire out_womask_412 = &_out_womask_T_412; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_412 = out_rivalid_1_266 & out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4353 = out_f_rivalid_412; // @[RegisterRouter.scala:87:24] wire out_f_roready_412 = out_roready_1_266 & out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4354 = out_f_roready_412; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_412 = out_wivalid_1_266 & out_wimask_412; // @[RegisterRouter.scala:87:24] wire out_f_woready_412 = out_woready_1_266 & out_womask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4355 = ~out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4356 = ~out_wimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4357 = ~out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4358 = ~out_womask_412; // @[RegisterRouter.scala:87:24] wire out_rimask_413 = \|_out_rimask_T_413; // @[RegisterRouter.scala:87:24] wire out_wimask_413 = &_out_wimask_T_413; // @[RegisterRouter.scala:87:24] wire out_romask_413 = \|_out_romask_T_413; // @[RegisterRouter.scala:87:24] wire out_womask_413 = &_out_womask_T_413; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_413 = out_rivalid_1_267 & out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4362 = out_f_rivalid_413; // @[RegisterRouter.scala:87:24] wire out_f_roready_413 = out_roready_1_267 & out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4363 = out_f_roready_413; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_413 = out_wivalid_1_267 & out_wimask_413; // @[RegisterRouter.scala:87:24] wire out_f_woready_413 = out_woready_1_267 & out_womask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4364 = ~out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4365 = ~out_wimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4366 = ~out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4367 = ~out_womask_413; // @[RegisterRouter.scala:87:24] wire out_rimask_414 = \|_out_rimask_T_414; // @[RegisterRouter.scala:87:24] wire out_wimask_414 = &_out_wimask_T_414; // @[RegisterRouter.scala:87:24] wire out_romask_414 = \|_out_romask_T_414; // @[RegisterRouter.scala:87:24] wire out_womask_414 = &_out_womask_T_414; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_414 = out_rivalid_1_268 & out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4371 = out_f_rivalid_414; // @[RegisterRouter.scala:87:24] wire out_f_roready_414 = out_roready_1_268 & out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4372 = out_f_roready_414; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_414 = out_wivalid_1_268 & out_wimask_414; // @[RegisterRouter.scala:87:24] wire out_f_woready_414 = out_woready_1_268 & out_womask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4373 = ~out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4374 = ~out_wimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4375 = ~out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4376 = ~out_womask_414; // @[RegisterRouter.scala:87:24] wire out_rimask_415 = \|_out_rimask_T_415; // @[RegisterRouter.scala:87:24] wire out_wimask_415 = &_out_wimask_T_415; // @[RegisterRouter.scala:87:24] wire out_romask_415 = \|_out_romask_T_415; // @[RegisterRouter.scala:87:24] wire out_womask_415 = &_out_womask_T_415; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_415 = out_rivalid_1_269 & out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4380 = out_f_rivalid_415; // @[RegisterRouter.scala:87:24] wire out_f_roready_415 = out_roready_1_269 & out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4381 = out_f_roready_415; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_415 = out_wivalid_1_269 & out_wimask_415; // @[RegisterRouter.scala:87:24] wire out_f_woready_415 = out_woready_1_269 & out_womask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4382 = ~out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4383 = ~out_wimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4384 = ~out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4385 = ~out_womask_415; // @[RegisterRouter.scala:87:24] wire out_rimask_416 = \|_out_rimask_T_416; // @[RegisterRouter.scala:87:24] wire out_wimask_416 = &_out_wimask_T_416; // @[RegisterRouter.scala:87:24] wire out_romask_416 = \|_out_romask_T_416; // @[RegisterRouter.scala:87:24] wire out_womask_416 = &_out_womask_T_416; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_416 = out_rivalid_1_270 & out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4389 = out_f_rivalid_416; // @[RegisterRouter.scala:87:24] wire out_f_roready_416 = out_roready_1_270 & out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4390 = out_f_roready_416; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_416 = out_wivalid_1_270 & out_wimask_416; // @[RegisterRouter.scala:87:24] wire out_f_woready_416 = out_woready_1_270 & out_womask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4391 = ~out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4392 = ~out_wimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4393 = ~out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4394 = ~out_womask_416; // @[RegisterRouter.scala:87:24] wire out_rimask_417 = \|_out_rimask_T_417; // @[RegisterRouter.scala:87:24] wire out_wimask_417 = &_out_wimask_T_417; // @[RegisterRouter.scala:87:24] wire out_romask_417 = \|_out_romask_T_417; // @[RegisterRouter.scala:87:24] wire out_womask_417 = &_out_womask_T_417; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_417 = out_rivalid_1_271 & out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4398 = out_f_rivalid_417; // @[RegisterRouter.scala:87:24] wire out_f_roready_417 = out_roready_1_271 & out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4399 = out_f_roready_417; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_417 = out_wivalid_1_271 & out_wimask_417; // @[RegisterRouter.scala:87:24] wire out_f_woready_417 = out_woready_1_271 & out_womask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4400 = ~out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4401 = ~out_wimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4402 = ~out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4403 = ~out_womask_417; // @[RegisterRouter.scala:87:24] wire out_rimask_418 = \|_out_rimask_T_418; // @[RegisterRouter.scala:87:24] wire out_wimask_418 = &_out_wimask_T_418; // @[RegisterRouter.scala:87:24] wire out_romask_418 = \|_out_romask_T_418; // @[RegisterRouter.scala:87:24] wire out_womask_418 = &_out_womask_T_418; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_418 = out_rivalid_1_272 & out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4407 = out_f_rivalid_418; // @[RegisterRouter.scala:87:24] wire out_f_roready_418 = out_roready_1_272 & out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4408 = out_f_roready_418; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_418 = out_wivalid_1_272 & out_wimask_418; // @[RegisterRouter.scala:87:24] wire out_f_woready_418 = out_woready_1_272 & out_womask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4409 = ~out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4410 = ~out_wimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4411 = ~out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4412 = ~out_womask_418; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4414 = _out_T_4413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_350 = _out_T_4414; // @[RegisterRouter.scala:87:24] wire out_rimask_419 = \|_out_rimask_T_419; // @[RegisterRouter.scala:87:24] wire out_wimask_419 = &_out_wimask_T_419; // @[RegisterRouter.scala:87:24] wire out_romask_419 = \|_out_romask_T_419; // @[RegisterRouter.scala:87:24] wire out_womask_419 = &_out_womask_T_419; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_419 = out_rivalid_1_273 & out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4416 = out_f_rivalid_419; // @[RegisterRouter.scala:87:24] wire out_f_roready_419 = out_roready_1_273 & out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4417 = out_f_roready_419; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_419 = out_wivalid_1_273 & out_wimask_419; // @[RegisterRouter.scala:87:24] wire out_f_woready_419 = out_woready_1_273 & out_womask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4418 = ~out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4419 = ~out_wimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4420 = ~out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4421 = ~out_womask_419; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_350 = {hi_626, flags_0_go, _out_prepend_T_350}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4422 = out_prepend_350; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4423 = _out_T_4422; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_351 = _out_T_4423; // @[RegisterRouter.scala:87:24] wire out_rimask_420 = \|_out_rimask_T_420; // @[RegisterRouter.scala:87:24] wire out_wimask_420 = &_out_wimask_T_420; // @[RegisterRouter.scala:87:24] wire out_romask_420 = \|_out_romask_T_420; // @[RegisterRouter.scala:87:24] wire out_womask_420 = &_out_womask_T_420; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_420 = out_rivalid_1_274 & out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4425 = out_f_rivalid_420; // @[RegisterRouter.scala:87:24] wire out_f_roready_420 = out_roready_1_274 & out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4426 = out_f_roready_420; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_420 = out_wivalid_1_274 & out_wimask_420; // @[RegisterRouter.scala:87:24] wire out_f_woready_420 = out_woready_1_274 & out_womask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4427 = ~out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4428 = ~out_wimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4429 = ~out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4430 = ~out_womask_420; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_351 = {hi_627, flags_0_go, _out_prepend_T_351}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4431 = out_prepend_351; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4432 = _out_T_4431; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_352 = _out_T_4432; // @[RegisterRouter.scala:87:24] wire out_rimask_421 = \|_out_rimask_T_421; // @[RegisterRouter.scala:87:24] wire out_wimask_421 = &_out_wimask_T_421; // @[RegisterRouter.scala:87:24] wire out_romask_421 = \|_out_romask_T_421; // @[RegisterRouter.scala:87:24] wire out_womask_421 = &_out_womask_T_421; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_421 = out_rivalid_1_275 & out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4434 = out_f_rivalid_421; // @[RegisterRouter.scala:87:24] wire out_f_roready_421 = out_roready_1_275 & out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4435 = out_f_roready_421; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_421 = out_wivalid_1_275 & out_wimask_421; // @[RegisterRouter.scala:87:24] wire out_f_woready_421 = out_woready_1_275 & out_womask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4436 = ~out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4437 = ~out_wimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4438 = ~out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4439 = ~out_womask_421; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_352 = {hi_628, flags_0_go, _out_prepend_T_352}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4440 = out_prepend_352; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4441 = _out_T_4440; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_353 = _out_T_4441; // @[RegisterRouter.scala:87:24] wire out_rimask_422 = \|_out_rimask_T_422; // @[RegisterRouter.scala:87:24] wire out_wimask_422 = &_out_wimask_T_422; // @[RegisterRouter.scala:87:24] wire out_romask_422 = \|_out_romask_T_422; // @[RegisterRouter.scala:87:24] wire out_womask_422 = &_out_womask_T_422; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_422 = out_rivalid_1_276 & out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4443 = out_f_rivalid_422; // @[RegisterRouter.scala:87:24] wire out_f_roready_422 = out_roready_1_276 & out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4444 = out_f_roready_422; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_422 = out_wivalid_1_276 & out_wimask_422; // @[RegisterRouter.scala:87:24] wire out_f_woready_422 = out_woready_1_276 & out_womask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4445 = ~out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4446 = ~out_wimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4447 = ~out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4448 = ~out_womask_422; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_353 = {hi_629, flags_0_go, _out_prepend_T_353}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4449 = out_prepend_353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4450 = _out_T_4449; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_354 = _out_T_4450; // @[RegisterRouter.scala:87:24] wire out_rimask_423 = \|_out_rimask_T_423; // @[RegisterRouter.scala:87:24] wire out_wimask_423 = &_out_wimask_T_423; // @[RegisterRouter.scala:87:24] wire out_romask_423 = \|_out_romask_T_423; // @[RegisterRouter.scala:87:24] wire out_womask_423 = &_out_womask_T_423; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_423 = out_rivalid_1_277 & out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4452 = out_f_rivalid_423; // @[RegisterRouter.scala:87:24] wire out_f_roready_423 = out_roready_1_277 & out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4453 = out_f_roready_423; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_423 = out_wivalid_1_277 & out_wimask_423; // @[RegisterRouter.scala:87:24] wire out_f_woready_423 = out_woready_1_277 & out_womask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4454 = ~out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4455 = ~out_wimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4456 = ~out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4457 = ~out_womask_423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_354 = {hi_630, flags_0_go, _out_prepend_T_354}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4458 = out_prepend_354; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4459 = _out_T_4458; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_355 = _out_T_4459; // @[RegisterRouter.scala:87:24] wire out_rimask_424 = \|_out_rimask_T_424; // @[RegisterRouter.scala:87:24] wire out_wimask_424 = &_out_wimask_T_424; // @[RegisterRouter.scala:87:24] wire out_romask_424 = \|_out_romask_T_424; // @[RegisterRouter.scala:87:24] wire out_womask_424 = &_out_womask_T_424; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_424 = out_rivalid_1_278 & out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4461 = out_f_rivalid_424; // @[RegisterRouter.scala:87:24] wire out_f_roready_424 = out_roready_1_278 & out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4462 = out_f_roready_424; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_424 = out_wivalid_1_278 & out_wimask_424; // @[RegisterRouter.scala:87:24] wire out_f_woready_424 = out_woready_1_278 & out_womask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4463 = ~out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4464 = ~out_wimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4465 = ~out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4466 = ~out_womask_424; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_355 = {hi_631, flags_0_go, _out_prepend_T_355}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4467 = out_prepend_355; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4468 = _out_T_4467; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_356 = _out_T_4468; // @[RegisterRouter.scala:87:24] wire out_rimask_425 = \|_out_rimask_T_425; // @[RegisterRouter.scala:87:24] wire out_wimask_425 = &_out_wimask_T_425; // @[RegisterRouter.scala:87:24] wire out_romask_425 = \|_out_romask_T_425; // @[RegisterRouter.scala:87:24] wire out_womask_425 = &_out_womask_T_425; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_425 = out_rivalid_1_279 & out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4470 = out_f_rivalid_425; // @[RegisterRouter.scala:87:24] wire out_f_roready_425 = out_roready_1_279 & out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4471 = out_f_roready_425; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_425 = out_wivalid_1_279 & out_wimask_425; // @[RegisterRouter.scala:87:24] wire out_f_woready_425 = out_woready_1_279 & out_womask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4472 = ~out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4473 = ~out_wimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4474 = ~out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4475 = ~out_womask_425; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_356 = {hi_632, flags_0_go, _out_prepend_T_356}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4476 = out_prepend_356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4477 = _out_T_4476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_206 = _out_T_4477; // @[MuxLiteral.scala:49:48] wire out_rimask_426 = \|_out_rimask_T_426; // @[RegisterRouter.scala:87:24] wire out_wimask_426 = &_out_wimask_T_426; // @[RegisterRouter.scala:87:24] wire out_romask_426 = \|_out_romask_T_426; // @[RegisterRouter.scala:87:24] wire out_womask_426 = &_out_womask_T_426; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_426 = out_rivalid_1_280 & out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4479 = out_f_rivalid_426; // @[RegisterRouter.scala:87:24] wire out_f_roready_426 = out_roready_1_280 & out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4480 = out_f_roready_426; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_426 = out_wivalid_1_280 & out_wimask_426; // @[RegisterRouter.scala:87:24] wire out_f_woready_426 = out_woready_1_280 & out_womask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4481 = ~out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4482 = ~out_wimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4483 = ~out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4484 = ~out_womask_426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4486 = _out_T_4485; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_357 = _out_T_4486; // @[RegisterRouter.scala:87:24] wire out_rimask_427 = \|_out_rimask_T_427; // @[RegisterRouter.scala:87:24] wire out_wimask_427 = &_out_wimask_T_427; // @[RegisterRouter.scala:87:24] wire out_romask_427 = \|_out_romask_T_427; // @[RegisterRouter.scala:87:24] wire out_womask_427 = &_out_womask_T_427; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_427 = out_rivalid_1_281 & out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4488 = out_f_rivalid_427; // @[RegisterRouter.scala:87:24] wire out_f_roready_427 = out_roready_1_281 & out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4489 = out_f_roready_427; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_427 = out_wivalid_1_281 & out_wimask_427; // @[RegisterRouter.scala:87:24] wire out_f_woready_427 = out_woready_1_281 & out_womask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4490 = ~out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4491 = ~out_wimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4492 = ~out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4493 = ~out_womask_427; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_357 = {hi_842, flags_0_go, _out_prepend_T_357}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4494 = out_prepend_357; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4495 = _out_T_4494; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_358 = _out_T_4495; // @[RegisterRouter.scala:87:24] wire out_rimask_428 = \|_out_rimask_T_428; // @[RegisterRouter.scala:87:24] wire out_wimask_428 = &_out_wimask_T_428; // @[RegisterRouter.scala:87:24] wire out_romask_428 = \|_out_romask_T_428; // @[RegisterRouter.scala:87:24] wire out_womask_428 = &_out_womask_T_428; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_428 = out_rivalid_1_282 & out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4497 = out_f_rivalid_428; // @[RegisterRouter.scala:87:24] wire out_f_roready_428 = out_roready_1_282 & out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4498 = out_f_roready_428; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_428 = out_wivalid_1_282 & out_wimask_428; // @[RegisterRouter.scala:87:24] wire out_f_woready_428 = out_woready_1_282 & out_womask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4499 = ~out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4500 = ~out_wimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4501 = ~out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4502 = ~out_womask_428; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_358 = {hi_843, flags_0_go, _out_prepend_T_358}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4503 = out_prepend_358; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4504 = _out_T_4503; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_359 = _out_T_4504; // @[RegisterRouter.scala:87:24] wire out_rimask_429 = \|_out_rimask_T_429; // @[RegisterRouter.scala:87:24] wire out_wimask_429 = &_out_wimask_T_429; // @[RegisterRouter.scala:87:24] wire out_romask_429 = \|_out_romask_T_429; // @[RegisterRouter.scala:87:24] wire out_womask_429 = &_out_womask_T_429; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_429 = out_rivalid_1_283 & out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4506 = out_f_rivalid_429; // @[RegisterRouter.scala:87:24] wire out_f_roready_429 = out_roready_1_283 & out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4507 = out_f_roready_429; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_429 = out_wivalid_1_283 & out_wimask_429; // @[RegisterRouter.scala:87:24] wire out_f_woready_429 = out_woready_1_283 & out_womask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4508 = ~out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4509 = ~out_wimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4510 = ~out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4511 = ~out_womask_429; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_359 = {hi_844, flags_0_go, _out_prepend_T_359}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4512 = out_prepend_359; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4513 = _out_T_4512; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_360 = _out_T_4513; // @[RegisterRouter.scala:87:24] wire out_rimask_430 = \|_out_rimask_T_430; // @[RegisterRouter.scala:87:24] wire out_wimask_430 = &_out_wimask_T_430; // @[RegisterRouter.scala:87:24] wire out_romask_430 = \|_out_romask_T_430; // @[RegisterRouter.scala:87:24] wire out_womask_430 = &_out_womask_T_430; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_430 = out_rivalid_1_284 & out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4515 = out_f_rivalid_430; // @[RegisterRouter.scala:87:24] wire out_f_roready_430 = out_roready_1_284 & out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4516 = out_f_roready_430; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_430 = out_wivalid_1_284 & out_wimask_430; // @[RegisterRouter.scala:87:24] wire out_f_woready_430 = out_woready_1_284 & out_womask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4517 = ~out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4518 = ~out_wimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4519 = ~out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4520 = ~out_womask_430; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_360 = {hi_845, flags_0_go, _out_prepend_T_360}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4521 = out_prepend_360; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4522 = _out_T_4521; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_361 = _out_T_4522; // @[RegisterRouter.scala:87:24] wire out_rimask_431 = \|_out_rimask_T_431; // @[RegisterRouter.scala:87:24] wire out_wimask_431 = &_out_wimask_T_431; // @[RegisterRouter.scala:87:24] wire out_romask_431 = \|_out_romask_T_431; // @[RegisterRouter.scala:87:24] wire out_womask_431 = &_out_womask_T_431; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_431 = out_rivalid_1_285 & out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4524 = out_f_rivalid_431; // @[RegisterRouter.scala:87:24] wire out_f_roready_431 = out_roready_1_285 & out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4525 = out_f_roready_431; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_431 = out_wivalid_1_285 & out_wimask_431; // @[RegisterRouter.scala:87:24] wire out_f_woready_431 = out_woready_1_285 & out_womask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4526 = ~out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4527 = ~out_wimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4528 = ~out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4529 = ~out_womask_431; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_361 = {hi_846, flags_0_go, _out_prepend_T_361}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4530 = out_prepend_361; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4531 = _out_T_4530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_362 = _out_T_4531; // @[RegisterRouter.scala:87:24] wire out_rimask_432 = \|_out_rimask_T_432; // @[RegisterRouter.scala:87:24] wire out_wimask_432 = &_out_wimask_T_432; // @[RegisterRouter.scala:87:24] wire out_romask_432 = \|_out_romask_T_432; // @[RegisterRouter.scala:87:24] wire out_womask_432 = &_out_womask_T_432; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_432 = out_rivalid_1_286 & out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4533 = out_f_rivalid_432; // @[RegisterRouter.scala:87:24] wire out_f_roready_432 = out_roready_1_286 & out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4534 = out_f_roready_432; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_432 = out_wivalid_1_286 & out_wimask_432; // @[RegisterRouter.scala:87:24] wire out_f_woready_432 = out_woready_1_286 & out_womask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4535 = ~out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4536 = ~out_wimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4537 = ~out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4538 = ~out_womask_432; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_362 = {hi_847, flags_0_go, _out_prepend_T_362}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4539 = out_prepend_362; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4540 = _out_T_4539; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_363 = _out_T_4540; // @[RegisterRouter.scala:87:24] wire out_rimask_433 = \|_out_rimask_T_433; // @[RegisterRouter.scala:87:24] wire out_wimask_433 = &_out_wimask_T_433; // @[RegisterRouter.scala:87:24] wire out_romask_433 = \|_out_romask_T_433; // @[RegisterRouter.scala:87:24] wire out_womask_433 = &_out_womask_T_433; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_433 = out_rivalid_1_287 & out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4542 = out_f_rivalid_433; // @[RegisterRouter.scala:87:24] wire out_f_roready_433 = out_roready_1_287 & out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4543 = out_f_roready_433; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_433 = out_wivalid_1_287 & out_wimask_433; // @[RegisterRouter.scala:87:24] wire out_f_woready_433 = out_woready_1_287 & out_womask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4544 = ~out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4545 = ~out_wimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4546 = ~out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4547 = ~out_womask_433; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_363 = {hi_848, flags_0_go, _out_prepend_T_363}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4548 = out_prepend_363; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4549 = _out_T_4548; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_233 = _out_T_4549; // @[MuxLiteral.scala:49:48] wire out_rimask_434 = \|_out_rimask_T_434; // @[RegisterRouter.scala:87:24] wire out_wimask_434 = &_out_wimask_T_434; // @[RegisterRouter.scala:87:24] wire out_romask_434 = \|_out_romask_T_434; // @[RegisterRouter.scala:87:24] wire out_womask_434 = &_out_womask_T_434; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_434 = out_rivalid_1_288 & out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4551 = out_f_rivalid_434; // @[RegisterRouter.scala:87:24] wire out_f_roready_434 = out_roready_1_288 & out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4552 = out_f_roready_434; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_434 = out_wivalid_1_288 & out_wimask_434; // @[RegisterRouter.scala:87:24] wire out_f_woready_434 = out_woready_1_288 & out_womask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4553 = ~out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4554 = ~out_wimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4555 = ~out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4556 = ~out_womask_434; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4558 = _out_T_4557; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_364 = _out_T_4558; // @[RegisterRouter.scala:87:24] wire out_rimask_435 = \|_out_rimask_T_435; // @[RegisterRouter.scala:87:24] wire out_wimask_435 = &_out_wimask_T_435; // @[RegisterRouter.scala:87:24] wire out_romask_435 = \|_out_romask_T_435; // @[RegisterRouter.scala:87:24] wire out_womask_435 = &_out_womask_T_435; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_435 = out_rivalid_1_289 & out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4560 = out_f_rivalid_435; // @[RegisterRouter.scala:87:24] wire out_f_roready_435 = out_roready_1_289 & out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4561 = out_f_roready_435; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_435 = out_wivalid_1_289 & out_wimask_435; // @[RegisterRouter.scala:87:24] wire out_f_woready_435 = out_woready_1_289 & out_womask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4562 = ~out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4563 = ~out_wimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4564 = ~out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4565 = ~out_womask_435; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_364 = {hi_962, flags_0_go, _out_prepend_T_364}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4566 = out_prepend_364; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4567 = _out_T_4566; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_365 = _out_T_4567; // @[RegisterRouter.scala:87:24] wire out_rimask_436 = \|_out_rimask_T_436; // @[RegisterRouter.scala:87:24] wire out_wimask_436 = &_out_wimask_T_436; // @[RegisterRouter.scala:87:24] wire out_romask_436 = \|_out_romask_T_436; // @[RegisterRouter.scala:87:24] wire out_womask_436 = &_out_womask_T_436; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_436 = out_rivalid_1_290 & out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4569 = out_f_rivalid_436; // @[RegisterRouter.scala:87:24] wire out_f_roready_436 = out_roready_1_290 & out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4570 = out_f_roready_436; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_436 = out_wivalid_1_290 & out_wimask_436; // @[RegisterRouter.scala:87:24] wire out_f_woready_436 = out_woready_1_290 & out_womask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4571 = ~out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4572 = ~out_wimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4573 = ~out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4574 = ~out_womask_436; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_365 = {hi_963, flags_0_go, _out_prepend_T_365}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4575 = out_prepend_365; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4576 = _out_T_4575; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_366 = _out_T_4576; // @[RegisterRouter.scala:87:24] wire out_rimask_437 = \|_out_rimask_T_437; // @[RegisterRouter.scala:87:24] wire out_wimask_437 = &_out_wimask_T_437; // @[RegisterRouter.scala:87:24] wire out_romask_437 = \|_out_romask_T_437; // @[RegisterRouter.scala:87:24] wire out_womask_437 = &_out_womask_T_437; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_437 = out_rivalid_1_291 & out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4578 = out_f_rivalid_437; // @[RegisterRouter.scala:87:24] wire out_f_roready_437 = out_roready_1_291 & out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4579 = out_f_roready_437; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_437 = out_wivalid_1_291 & out_wimask_437; // @[RegisterRouter.scala:87:24] wire out_f_woready_437 = out_woready_1_291 & out_womask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4580 = ~out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4581 = ~out_wimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4582 = ~out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4583 = ~out_womask_437; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_366 = {hi_964, flags_0_go, _out_prepend_T_366}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4584 = out_prepend_366; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4585 = _out_T_4584; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_367 = _out_T_4585; // @[RegisterRouter.scala:87:24] wire out_rimask_438 = \|_out_rimask_T_438; // @[RegisterRouter.scala:87:24] wire out_wimask_438 = &_out_wimask_T_438; // @[RegisterRouter.scala:87:24] wire out_romask_438 = \|_out_romask_T_438; // @[RegisterRouter.scala:87:24] wire out_womask_438 = &_out_womask_T_438; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_438 = out_rivalid_1_292 & out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4587 = out_f_rivalid_438; // @[RegisterRouter.scala:87:24] wire out_f_roready_438 = out_roready_1_292 & out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4588 = out_f_roready_438; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_438 = out_wivalid_1_292 & out_wimask_438; // @[RegisterRouter.scala:87:24] wire out_f_woready_438 = out_woready_1_292 & out_womask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4589 = ~out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4590 = ~out_wimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4591 = ~out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4592 = ~out_womask_438; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_367 = {hi_965, flags_0_go, _out_prepend_T_367}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4593 = out_prepend_367; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4594 = _out_T_4593; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_368 = _out_T_4594; // @[RegisterRouter.scala:87:24] wire out_rimask_439 = \|_out_rimask_T_439; // @[RegisterRouter.scala:87:24] wire out_wimask_439 = &_out_wimask_T_439; // @[RegisterRouter.scala:87:24] wire out_romask_439 = \|_out_romask_T_439; // @[RegisterRouter.scala:87:24] wire out_womask_439 = &_out_womask_T_439; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_439 = out_rivalid_1_293 & out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4596 = out_f_rivalid_439; // @[RegisterRouter.scala:87:24] wire out_f_roready_439 = out_roready_1_293 & out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4597 = out_f_roready_439; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_439 = out_wivalid_1_293 & out_wimask_439; // @[RegisterRouter.scala:87:24] wire out_f_woready_439 = out_woready_1_293 & out_womask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4598 = ~out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4599 = ~out_wimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4600 = ~out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4601 = ~out_womask_439; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_368 = {hi_966, flags_0_go, _out_prepend_T_368}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4602 = out_prepend_368; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4603 = _out_T_4602; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_369 = _out_T_4603; // @[RegisterRouter.scala:87:24] wire out_rimask_440 = \|_out_rimask_T_440; // @[RegisterRouter.scala:87:24] wire out_wimask_440 = &_out_wimask_T_440; // @[RegisterRouter.scala:87:24] wire out_romask_440 = \|_out_romask_T_440; // @[RegisterRouter.scala:87:24] wire out_womask_440 = &_out_womask_T_440; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_440 = out_rivalid_1_294 & out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4605 = out_f_rivalid_440; // @[RegisterRouter.scala:87:24] wire out_f_roready_440 = out_roready_1_294 & out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4606 = out_f_roready_440; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_440 = out_wivalid_1_294 & out_wimask_440; // @[RegisterRouter.scala:87:24] wire out_f_woready_440 = out_woready_1_294 & out_womask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4607 = ~out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4608 = ~out_wimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4609 = ~out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4610 = ~out_womask_440; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_369 = {hi_967, flags_0_go, _out_prepend_T_369}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4611 = out_prepend_369; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4612 = _out_T_4611; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_370 = _out_T_4612; // @[RegisterRouter.scala:87:24] wire out_rimask_441 = \|_out_rimask_T_441; // @[RegisterRouter.scala:87:24] wire out_wimask_441 = &_out_wimask_T_441; // @[RegisterRouter.scala:87:24] wire out_romask_441 = \|_out_romask_T_441; // @[RegisterRouter.scala:87:24] wire out_womask_441 = &_out_womask_T_441; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_441 = out_rivalid_1_295 & out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4614 = out_f_rivalid_441; // @[RegisterRouter.scala:87:24] wire out_f_roready_441 = out_roready_1_295 & out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4615 = out_f_roready_441; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_441 = out_wivalid_1_295 & out_wimask_441; // @[RegisterRouter.scala:87:24] wire out_f_woready_441 = out_woready_1_295 & out_womask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4616 = ~out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4617 = ~out_wimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4618 = ~out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4619 = ~out_womask_441; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_370 = {hi_968, flags_0_go, _out_prepend_T_370}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4620 = out_prepend_370; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4621 = _out_T_4620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_248 = _out_T_4621; // @[MuxLiteral.scala:49:48] wire out_rimask_442 = \|_out_rimask_T_442; // @[RegisterRouter.scala:87:24] wire out_wimask_442 = &_out_wimask_T_442; // @[RegisterRouter.scala:87:24] wire out_romask_442 = \|_out_romask_T_442; // @[RegisterRouter.scala:87:24] wire out_womask_442 = &_out_womask_T_442; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_442 = out_rivalid_1_296 & out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4623 = out_f_rivalid_442; // @[RegisterRouter.scala:87:24] wire out_f_roready_442 = out_roready_1_296 & out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4624 = out_f_roready_442; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_442 = out_wivalid_1_296 & out_wimask_442; // @[RegisterRouter.scala:87:24] wire out_f_woready_442 = out_woready_1_296 & out_womask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4625 = ~out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4626 = ~out_wimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4627 = ~out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4628 = ~out_womask_442; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4630 = _out_T_4629; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_371 = _out_T_4630; // @[RegisterRouter.scala:87:24] wire out_rimask_443 = \|_out_rimask_T_443; // @[RegisterRouter.scala:87:24] wire out_wimask_443 = &_out_wimask_T_443; // @[RegisterRouter.scala:87:24] wire out_romask_443 = \|_out_romask_T_443; // @[RegisterRouter.scala:87:24] wire out_womask_443 = &_out_womask_T_443; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_443 = out_rivalid_1_297 & out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4632 = out_f_rivalid_443; // @[RegisterRouter.scala:87:24] wire out_f_roready_443 = out_roready_1_297 & out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4633 = out_f_roready_443; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_443 = out_wivalid_1_297 & out_wimask_443; // @[RegisterRouter.scala:87:24] wire out_f_woready_443 = out_woready_1_297 & out_womask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4634 = ~out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4635 = ~out_wimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4636 = ~out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4637 = ~out_womask_443; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_371 = {hi_586, flags_0_go, _out_prepend_T_371}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4638 = out_prepend_371; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4639 = _out_T_4638; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_372 = _out_T_4639; // @[RegisterRouter.scala:87:24] wire out_rimask_444 = \|_out_rimask_T_444; // @[RegisterRouter.scala:87:24] wire out_wimask_444 = &_out_wimask_T_444; // @[RegisterRouter.scala:87:24] wire out_romask_444 = \|_out_romask_T_444; // @[RegisterRouter.scala:87:24] wire out_womask_444 = &_out_womask_T_444; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_444 = out_rivalid_1_298 & out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4641 = out_f_rivalid_444; // @[RegisterRouter.scala:87:24] wire out_f_roready_444 = out_roready_1_298 & out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4642 = out_f_roready_444; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_444 = out_wivalid_1_298 & out_wimask_444; // @[RegisterRouter.scala:87:24] wire out_f_woready_444 = out_woready_1_298 & out_womask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4643 = ~out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4644 = ~out_wimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4645 = ~out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4646 = ~out_womask_444; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_372 = {hi_587, flags_0_go, _out_prepend_T_372}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4647 = out_prepend_372; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4648 = _out_T_4647; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_373 = _out_T_4648; // @[RegisterRouter.scala:87:24] wire out_rimask_445 = \|_out_rimask_T_445; // @[RegisterRouter.scala:87:24] wire out_wimask_445 = &_out_wimask_T_445; // @[RegisterRouter.scala:87:24] wire out_romask_445 = \|_out_romask_T_445; // @[RegisterRouter.scala:87:24] wire out_womask_445 = &_out_womask_T_445; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_445 = out_rivalid_1_299 & out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4650 = out_f_rivalid_445; // @[RegisterRouter.scala:87:24] wire out_f_roready_445 = out_roready_1_299 & out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4651 = out_f_roready_445; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_445 = out_wivalid_1_299 & out_wimask_445; // @[RegisterRouter.scala:87:24] wire out_f_woready_445 = out_woready_1_299 & out_womask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4652 = ~out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4653 = ~out_wimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4654 = ~out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4655 = ~out_womask_445; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_373 = {hi_588, flags_0_go, _out_prepend_T_373}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4656 = out_prepend_373; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4657 = _out_T_4656; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_374 = _out_T_4657; // @[RegisterRouter.scala:87:24] wire out_rimask_446 = \|_out_rimask_T_446; // @[RegisterRouter.scala:87:24] wire out_wimask_446 = &_out_wimask_T_446; // @[RegisterRouter.scala:87:24] wire out_romask_446 = \|_out_romask_T_446; // @[RegisterRouter.scala:87:24] wire out_womask_446 = &_out_womask_T_446; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_446 = out_rivalid_1_300 & out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4659 = out_f_rivalid_446; // @[RegisterRouter.scala:87:24] wire out_f_roready_446 = out_roready_1_300 & out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4660 = out_f_roready_446; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_446 = out_wivalid_1_300 & out_wimask_446; // @[RegisterRouter.scala:87:24] wire out_f_woready_446 = out_woready_1_300 & out_womask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4661 = ~out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4662 = ~out_wimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4663 = ~out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4664 = ~out_womask_446; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_374 = {hi_589, flags_0_go, _out_prepend_T_374}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4665 = out_prepend_374; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4666 = _out_T_4665; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_375 = _out_T_4666; // @[RegisterRouter.scala:87:24] wire out_rimask_447 = \|_out_rimask_T_447; // @[RegisterRouter.scala:87:24] wire out_wimask_447 = &_out_wimask_T_447; // @[RegisterRouter.scala:87:24] wire out_romask_447 = \|_out_romask_T_447; // @[RegisterRouter.scala:87:24] wire out_womask_447 = &_out_womask_T_447; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_447 = out_rivalid_1_301 & out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4668 = out_f_rivalid_447; // @[RegisterRouter.scala:87:24] wire out_f_roready_447 = out_roready_1_301 & out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4669 = out_f_roready_447; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_447 = out_wivalid_1_301 & out_wimask_447; // @[RegisterRouter.scala:87:24] wire out_f_woready_447 = out_woready_1_301 & out_womask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4670 = ~out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4671 = ~out_wimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4672 = ~out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4673 = ~out_womask_447; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_375 = {hi_590, flags_0_go, _out_prepend_T_375}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4674 = out_prepend_375; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4675 = _out_T_4674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_376 = _out_T_4675; // @[RegisterRouter.scala:87:24] wire out_rimask_448 = \|_out_rimask_T_448; // @[RegisterRouter.scala:87:24] wire out_wimask_448 = &_out_wimask_T_448; // @[RegisterRouter.scala:87:24] wire out_romask_448 = \|_out_romask_T_448; // @[RegisterRouter.scala:87:24] wire out_womask_448 = &_out_womask_T_448; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_448 = out_rivalid_1_302 & out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4677 = out_f_rivalid_448; // @[RegisterRouter.scala:87:24] wire out_f_roready_448 = out_roready_1_302 & out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4678 = out_f_roready_448; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_448 = out_wivalid_1_302 & out_wimask_448; // @[RegisterRouter.scala:87:24] wire out_f_woready_448 = out_woready_1_302 & out_womask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4679 = ~out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4680 = ~out_wimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4681 = ~out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4682 = ~out_womask_448; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_376 = {hi_591, flags_0_go, _out_prepend_T_376}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4683 = out_prepend_376; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4684 = _out_T_4683; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_377 = _out_T_4684; // @[RegisterRouter.scala:87:24] wire out_rimask_449 = \|_out_rimask_T_449; // @[RegisterRouter.scala:87:24] wire out_wimask_449 = &_out_wimask_T_449; // @[RegisterRouter.scala:87:24] wire out_romask_449 = \|_out_romask_T_449; // @[RegisterRouter.scala:87:24] wire out_womask_449 = &_out_womask_T_449; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_449 = out_rivalid_1_303 & out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4686 = out_f_rivalid_449; // @[RegisterRouter.scala:87:24] wire out_f_roready_449 = out_roready_1_303 & out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4687 = out_f_roready_449; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_449 = out_wivalid_1_303 & out_wimask_449; // @[RegisterRouter.scala:87:24] wire out_f_woready_449 = out_woready_1_303 & out_womask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4688 = ~out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4689 = ~out_wimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4690 = ~out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4691 = ~out_womask_449; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_377 = {hi_592, flags_0_go, _out_prepend_T_377}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4692 = out_prepend_377; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4693 = _out_T_4692; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_201 = _out_T_4693; // @[MuxLiteral.scala:49:48] wire out_rimask_450 = \|_out_rimask_T_450; // @[RegisterRouter.scala:87:24] wire out_wimask_450 = &_out_wimask_T_450; // @[RegisterRouter.scala:87:24] wire out_romask_450 = \|_out_romask_T_450; // @[RegisterRouter.scala:87:24] wire out_womask_450 = &_out_womask_T_450; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_450 = out_rivalid_1_304 & out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4695 = out_f_rivalid_450; // @[RegisterRouter.scala:87:24] wire out_f_roready_450 = out_roready_1_304 & out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4696 = out_f_roready_450; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_450 = out_wivalid_1_304 & out_wimask_450; // @[RegisterRouter.scala:87:24] wire out_f_woready_450 = out_woready_1_304 & out_womask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4697 = ~out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4698 = ~out_wimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4699 = ~out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4700 = ~out_womask_450; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4702 = _out_T_4701; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_378 = _out_T_4702; // @[RegisterRouter.scala:87:24] wire out_rimask_451 = \|_out_rimask_T_451; // @[RegisterRouter.scala:87:24] wire out_wimask_451 = &_out_wimask_T_451; // @[RegisterRouter.scala:87:24] wire out_romask_451 = \|_out_romask_T_451; // @[RegisterRouter.scala:87:24] wire out_womask_451 = &_out_womask_T_451; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_451 = out_rivalid_1_305 & out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4704 = out_f_rivalid_451; // @[RegisterRouter.scala:87:24] wire out_f_roready_451 = out_roready_1_305 & out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4705 = out_f_roready_451; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_451 = out_wivalid_1_305 & out_wimask_451; // @[RegisterRouter.scala:87:24] wire out_f_woready_451 = out_woready_1_305 & out_womask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4706 = ~out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4707 = ~out_wimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4708 = ~out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4709 = ~out_womask_451; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_378 = {hi_738, flags_0_go, _out_prepend_T_378}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4710 = out_prepend_378; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4711 = _out_T_4710; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_379 = _out_T_4711; // @[RegisterRouter.scala:87:24] wire out_rimask_452 = \|_out_rimask_T_452; // @[RegisterRouter.scala:87:24] wire out_wimask_452 = &_out_wimask_T_452; // @[RegisterRouter.scala:87:24] wire out_romask_452 = \|_out_romask_T_452; // @[RegisterRouter.scala:87:24] wire out_womask_452 = &_out_womask_T_452; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_452 = out_rivalid_1_306 & out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4713 = out_f_rivalid_452; // @[RegisterRouter.scala:87:24] wire out_f_roready_452 = out_roready_1_306 & out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4714 = out_f_roready_452; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_452 = out_wivalid_1_306 & out_wimask_452; // @[RegisterRouter.scala:87:24] wire out_f_woready_452 = out_woready_1_306 & out_womask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4715 = ~out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4716 = ~out_wimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4717 = ~out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4718 = ~out_womask_452; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_379 = {hi_739, flags_0_go, _out_prepend_T_379}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4719 = out_prepend_379; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4720 = _out_T_4719; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_380 = _out_T_4720; // @[RegisterRouter.scala:87:24] wire out_rimask_453 = \|_out_rimask_T_453; // @[RegisterRouter.scala:87:24] wire out_wimask_453 = &_out_wimask_T_453; // @[RegisterRouter.scala:87:24] wire out_romask_453 = \|_out_romask_T_453; // @[RegisterRouter.scala:87:24] wire out_womask_453 = &_out_womask_T_453; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_453 = out_rivalid_1_307 & out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4722 = out_f_rivalid_453; // @[RegisterRouter.scala:87:24] wire out_f_roready_453 = out_roready_1_307 & out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4723 = out_f_roready_453; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_453 = out_wivalid_1_307 & out_wimask_453; // @[RegisterRouter.scala:87:24] wire out_f_woready_453 = out_woready_1_307 & out_womask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4724 = ~out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4725 = ~out_wimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4726 = ~out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4727 = ~out_womask_453; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_380 = {hi_740, flags_0_go, _out_prepend_T_380}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4728 = out_prepend_380; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4729 = _out_T_4728; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_381 = _out_T_4729; // @[RegisterRouter.scala:87:24] wire out_rimask_454 = \|_out_rimask_T_454; // @[RegisterRouter.scala:87:24] wire out_wimask_454 = &_out_wimask_T_454; // @[RegisterRouter.scala:87:24] wire out_romask_454 = \|_out_romask_T_454; // @[RegisterRouter.scala:87:24] wire out_womask_454 = &_out_womask_T_454; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_454 = out_rivalid_1_308 & out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4731 = out_f_rivalid_454; // @[RegisterRouter.scala:87:24] wire out_f_roready_454 = out_roready_1_308 & out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4732 = out_f_roready_454; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_454 = out_wivalid_1_308 & out_wimask_454; // @[RegisterRouter.scala:87:24] wire out_f_woready_454 = out_woready_1_308 & out_womask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4733 = ~out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4734 = ~out_wimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4735 = ~out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4736 = ~out_womask_454; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_381 = {hi_741, flags_0_go, _out_prepend_T_381}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4737 = out_prepend_381; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4738 = _out_T_4737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_382 = _out_T_4738; // @[RegisterRouter.scala:87:24] wire out_rimask_455 = \|_out_rimask_T_455; // @[RegisterRouter.scala:87:24] wire out_wimask_455 = &_out_wimask_T_455; // @[RegisterRouter.scala:87:24] wire out_romask_455 = \|_out_romask_T_455; // @[RegisterRouter.scala:87:24] wire out_womask_455 = &_out_womask_T_455; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_455 = out_rivalid_1_309 & out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4740 = out_f_rivalid_455; // @[RegisterRouter.scala:87:24] wire out_f_roready_455 = out_roready_1_309 & out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4741 = out_f_roready_455; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_455 = out_wivalid_1_309 & out_wimask_455; // @[RegisterRouter.scala:87:24] wire out_f_woready_455 = out_woready_1_309 & out_womask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4742 = ~out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4743 = ~out_wimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4744 = ~out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4745 = ~out_womask_455; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_382 = {hi_742, flags_0_go, _out_prepend_T_382}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4746 = out_prepend_382; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4747 = _out_T_4746; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_383 = _out_T_4747; // @[RegisterRouter.scala:87:24] wire out_rimask_456 = \|_out_rimask_T_456; // @[RegisterRouter.scala:87:24] wire out_wimask_456 = &_out_wimask_T_456; // @[RegisterRouter.scala:87:24] wire out_romask_456 = \|_out_romask_T_456; // @[RegisterRouter.scala:87:24] wire out_womask_456 = &_out_womask_T_456; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_456 = out_rivalid_1_310 & out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4749 = out_f_rivalid_456; // @[RegisterRouter.scala:87:24] wire out_f_roready_456 = out_roready_1_310 & out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4750 = out_f_roready_456; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_456 = out_wivalid_1_310 & out_wimask_456; // @[RegisterRouter.scala:87:24] wire out_f_woready_456 = out_woready_1_310 & out_womask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4751 = ~out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4752 = ~out_wimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4753 = ~out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4754 = ~out_womask_456; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_383 = {hi_743, flags_0_go, _out_prepend_T_383}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4755 = out_prepend_383; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4756 = _out_T_4755; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_384 = _out_T_4756; // @[RegisterRouter.scala:87:24] wire out_rimask_457 = \|_out_rimask_T_457; // @[RegisterRouter.scala:87:24] wire out_wimask_457 = &_out_wimask_T_457; // @[RegisterRouter.scala:87:24] wire out_romask_457 = \|_out_romask_T_457; // @[RegisterRouter.scala:87:24] wire out_womask_457 = &_out_womask_T_457; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_457 = out_rivalid_1_311 & out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4758 = out_f_rivalid_457; // @[RegisterRouter.scala:87:24] wire out_f_roready_457 = out_roready_1_311 & out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4759 = out_f_roready_457; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_457 = out_wivalid_1_311 & out_wimask_457; // @[RegisterRouter.scala:87:24] wire out_f_woready_457 = out_woready_1_311 & out_womask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4760 = ~out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4761 = ~out_wimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4762 = ~out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4763 = ~out_womask_457; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_384 = {hi_744, flags_0_go, _out_prepend_T_384}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4764 = out_prepend_384; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4765 = _out_T_4764; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_220 = _out_T_4765; // @[MuxLiteral.scala:49:48] wire out_rimask_458 = \|_out_rimask_T_458; // @[RegisterRouter.scala:87:24] wire out_wimask_458 = &_out_wimask_T_458; // @[RegisterRouter.scala:87:24] wire out_romask_458 = \|_out_romask_T_458; // @[RegisterRouter.scala:87:24] wire out_womask_458 = &_out_womask_T_458; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_458 = out_rivalid_1_312 & out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4767 = out_f_rivalid_458; // @[RegisterRouter.scala:87:24] wire out_f_roready_458 = out_roready_1_312 & out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4768 = out_f_roready_458; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_458 = out_wivalid_1_312 & out_wimask_458; // @[RegisterRouter.scala:87:24] wire out_f_woready_458 = out_woready_1_312 & out_womask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4769 = ~out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4770 = ~out_wimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4771 = ~out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4772 = ~out_womask_458; // @[RegisterRouter.scala:87:24] wire out_rimask_459 = \|_out_rimask_T_459; // @[RegisterRouter.scala:87:24] wire out_wimask_459 = &_out_wimask_T_459; // @[RegisterRouter.scala:87:24] wire out_romask_459 = \|_out_romask_T_459; // @[RegisterRouter.scala:87:24] wire out_womask_459 = &_out_womask_T_459; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_459 = out_rivalid_1_313 & out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4776 = out_f_rivalid_459; // @[RegisterRouter.scala:87:24] wire out_f_roready_459 = out_roready_1_313 & out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4777 = out_f_roready_459; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_459 = out_wivalid_1_313 & out_wimask_459; // @[RegisterRouter.scala:87:24] wire out_f_woready_459 = out_woready_1_313 & out_womask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4778 = ~out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4779 = ~out_wimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4780 = ~out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4781 = ~out_womask_459; // @[RegisterRouter.scala:87:24] wire out_rimask_460 = \|_out_rimask_T_460; // @[RegisterRouter.scala:87:24] wire out_wimask_460 = &_out_wimask_T_460; // @[RegisterRouter.scala:87:24] wire out_romask_460 = \|_out_romask_T_460; // @[RegisterRouter.scala:87:24] wire out_womask_460 = &_out_womask_T_460; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_460 = out_rivalid_1_314 & out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4785 = out_f_rivalid_460; // @[RegisterRouter.scala:87:24] wire out_f_roready_460 = out_roready_1_314 & out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4786 = out_f_roready_460; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_460 = out_wivalid_1_314 & out_wimask_460; // @[RegisterRouter.scala:87:24] wire out_f_woready_460 = out_woready_1_314 & out_womask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4787 = ~out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4788 = ~out_wimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4789 = ~out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4790 = ~out_womask_460; // @[RegisterRouter.scala:87:24] wire out_rimask_461 = \|_out_rimask_T_461; // @[RegisterRouter.scala:87:24] wire out_wimask_461 = &_out_wimask_T_461; // @[RegisterRouter.scala:87:24] wire out_romask_461 = \|_out_romask_T_461; // @[RegisterRouter.scala:87:24] wire out_womask_461 = &_out_womask_T_461; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_461 = out_rivalid_1_315 & out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4794 = out_f_rivalid_461; // @[RegisterRouter.scala:87:24] wire out_f_roready_461 = out_roready_1_315 & out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4795 = out_f_roready_461; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_461 = out_wivalid_1_315 & out_wimask_461; // @[RegisterRouter.scala:87:24] wire out_f_woready_461 = out_woready_1_315 & out_womask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4796 = ~out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4797 = ~out_wimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4798 = ~out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4799 = ~out_womask_461; // @[RegisterRouter.scala:87:24] wire out_rimask_462 = \|_out_rimask_T_462; // @[RegisterRouter.scala:87:24] wire out_wimask_462 = &_out_wimask_T_462; // @[RegisterRouter.scala:87:24] wire out_romask_462 = \|_out_romask_T_462; // @[RegisterRouter.scala:87:24] wire out_womask_462 = &_out_womask_T_462; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_462 = out_rivalid_1_316 & out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4803 = out_f_rivalid_462; // @[RegisterRouter.scala:87:24] wire out_f_roready_462 = out_roready_1_316 & out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4804 = out_f_roready_462; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_462 = out_wivalid_1_316 & out_wimask_462; // @[RegisterRouter.scala:87:24] wire out_f_woready_462 = out_woready_1_316 & out_womask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4805 = ~out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4806 = ~out_wimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4807 = ~out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4808 = ~out_womask_462; // @[RegisterRouter.scala:87:24] wire out_rimask_463 = \|_out_rimask_T_463; // @[RegisterRouter.scala:87:24] wire out_wimask_463 = &_out_wimask_T_463; // @[RegisterRouter.scala:87:24] wire out_romask_463 = \|_out_romask_T_463; // @[RegisterRouter.scala:87:24] wire out_womask_463 = &_out_womask_T_463; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_463 = out_rivalid_1_317 & out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4812 = out_f_rivalid_463; // @[RegisterRouter.scala:87:24] wire out_f_roready_463 = out_roready_1_317 & out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4813 = out_f_roready_463; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_463 = out_wivalid_1_317 & out_wimask_463; // @[RegisterRouter.scala:87:24] wire out_f_woready_463 = out_woready_1_317 & out_womask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4814 = ~out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4815 = ~out_wimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4816 = ~out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4817 = ~out_womask_463; // @[RegisterRouter.scala:87:24] wire out_rimask_464 = \|_out_rimask_T_464; // @[RegisterRouter.scala:87:24] wire out_wimask_464 = &_out_wimask_T_464; // @[RegisterRouter.scala:87:24] wire out_romask_464 = \|_out_romask_T_464; // @[RegisterRouter.scala:87:24] wire out_womask_464 = &_out_womask_T_464; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_464 = out_rivalid_1_318 & out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4821 = out_f_rivalid_464; // @[RegisterRouter.scala:87:24] wire out_f_roready_464 = out_roready_1_318 & out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4822 = out_f_roready_464; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_464 = out_wivalid_1_318 & out_wimask_464; // @[RegisterRouter.scala:87:24] wire out_f_woready_464 = out_woready_1_318 & out_womask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4823 = ~out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4824 = ~out_wimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4825 = ~out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4826 = ~out_womask_464; // @[RegisterRouter.scala:87:24] wire out_rimask_465 = \|_out_rimask_T_465; // @[RegisterRouter.scala:87:24] wire out_wimask_465 = &_out_wimask_T_465; // @[RegisterRouter.scala:87:24] wire out_romask_465 = \|_out_romask_T_465; // @[RegisterRouter.scala:87:24] wire out_womask_465 = &_out_womask_T_465; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_465 = out_rivalid_1_319 & out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4830 = out_f_rivalid_465; // @[RegisterRouter.scala:87:24] wire out_f_roready_465 = out_roready_1_319 & out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4831 = out_f_roready_465; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_465 = out_wivalid_1_319 & out_wimask_465; // @[RegisterRouter.scala:87:24] wire out_f_woready_465 = out_woready_1_319 & out_womask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4832 = ~out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4833 = ~out_wimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4834 = ~out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4835 = ~out_womask_465; // @[RegisterRouter.scala:87:24] wire out_rimask_466 = \|_out_rimask_T_466; // @[RegisterRouter.scala:87:24] wire out_wimask_466 = &_out_wimask_T_466; // @[RegisterRouter.scala:87:24] wire out_romask_466 = \|_out_romask_T_466; // @[RegisterRouter.scala:87:24] wire out_womask_466 = &_out_womask_T_466; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_466 = out_rivalid_1_320 & out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4839 = out_f_rivalid_466; // @[RegisterRouter.scala:87:24] wire out_f_roready_466 = out_roready_1_320 & out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4840 = out_f_roready_466; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_466 = out_wivalid_1_320 & out_wimask_466; // @[RegisterRouter.scala:87:24] wire out_f_woready_466 = out_woready_1_320 & out_womask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4841 = ~out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4842 = ~out_wimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4843 = ~out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4844 = ~out_womask_466; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4846 = _out_T_4845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_392 = _out_T_4846; // @[RegisterRouter.scala:87:24] wire out_rimask_467 = \|_out_rimask_T_467; // @[RegisterRouter.scala:87:24] wire out_wimask_467 = &_out_wimask_T_467; // @[RegisterRouter.scala:87:24] wire out_romask_467 = \|_out_romask_T_467; // @[RegisterRouter.scala:87:24] wire out_womask_467 = &_out_womask_T_467; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_467 = out_rivalid_1_321 & out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4848 = out_f_rivalid_467; // @[RegisterRouter.scala:87:24] wire out_f_roready_467 = out_roready_1_321 & out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4849 = out_f_roready_467; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_467 = out_wivalid_1_321 & out_wimask_467; // @[RegisterRouter.scala:87:24] wire out_f_woready_467 = out_woready_1_321 & out_womask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4850 = ~out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4851 = ~out_wimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4852 = ~out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4853 = ~out_womask_467; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_392 = {hi_258, flags_0_go, _out_prepend_T_392}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4854 = out_prepend_392; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4855 = _out_T_4854; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_393 = _out_T_4855; // @[RegisterRouter.scala:87:24] wire out_rimask_468 = \|_out_rimask_T_468; // @[RegisterRouter.scala:87:24] wire out_wimask_468 = &_out_wimask_T_468; // @[RegisterRouter.scala:87:24] wire out_romask_468 = \|_out_romask_T_468; // @[RegisterRouter.scala:87:24] wire out_womask_468 = &_out_womask_T_468; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_468 = out_rivalid_1_322 & out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4857 = out_f_rivalid_468; // @[RegisterRouter.scala:87:24] wire out_f_roready_468 = out_roready_1_322 & out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4858 = out_f_roready_468; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_468 = out_wivalid_1_322 & out_wimask_468; // @[RegisterRouter.scala:87:24] wire out_f_woready_468 = out_woready_1_322 & out_womask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4859 = ~out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4860 = ~out_wimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4861 = ~out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4862 = ~out_womask_468; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_393 = {hi_259, flags_0_go, _out_prepend_T_393}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4863 = out_prepend_393; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4864 = _out_T_4863; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_394 = _out_T_4864; // @[RegisterRouter.scala:87:24] wire out_rimask_469 = \|_out_rimask_T_469; // @[RegisterRouter.scala:87:24] wire out_wimask_469 = &_out_wimask_T_469; // @[RegisterRouter.scala:87:24] wire out_romask_469 = \|_out_romask_T_469; // @[RegisterRouter.scala:87:24] wire out_womask_469 = &_out_womask_T_469; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_469 = out_rivalid_1_323 & out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4866 = out_f_rivalid_469; // @[RegisterRouter.scala:87:24] wire out_f_roready_469 = out_roready_1_323 & out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4867 = out_f_roready_469; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_469 = out_wivalid_1_323 & out_wimask_469; // @[RegisterRouter.scala:87:24] wire out_f_woready_469 = out_woready_1_323 & out_womask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4868 = ~out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4869 = ~out_wimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4870 = ~out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4871 = ~out_womask_469; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_394 = {hi_260, flags_0_go, _out_prepend_T_394}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4872 = out_prepend_394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4873 = _out_T_4872; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_395 = _out_T_4873; // @[RegisterRouter.scala:87:24] wire out_rimask_470 = \|_out_rimask_T_470; // @[RegisterRouter.scala:87:24] wire out_wimask_470 = &_out_wimask_T_470; // @[RegisterRouter.scala:87:24] wire out_romask_470 = \|_out_romask_T_470; // @[RegisterRouter.scala:87:24] wire out_womask_470 = &_out_womask_T_470; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_470 = out_rivalid_1_324 & out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4875 = out_f_rivalid_470; // @[RegisterRouter.scala:87:24] wire out_f_roready_470 = out_roready_1_324 & out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4876 = out_f_roready_470; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_470 = out_wivalid_1_324 & out_wimask_470; // @[RegisterRouter.scala:87:24] wire out_f_woready_470 = out_woready_1_324 & out_womask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4877 = ~out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4878 = ~out_wimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4879 = ~out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4880 = ~out_womask_470; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_395 = {hi_261, flags_0_go, _out_prepend_T_395}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4881 = out_prepend_395; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4882 = _out_T_4881; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_396 = _out_T_4882; // @[RegisterRouter.scala:87:24] wire out_rimask_471 = \|_out_rimask_T_471; // @[RegisterRouter.scala:87:24] wire out_wimask_471 = &_out_wimask_T_471; // @[RegisterRouter.scala:87:24] wire out_romask_471 = \|_out_romask_T_471; // @[RegisterRouter.scala:87:24] wire out_womask_471 = &_out_womask_T_471; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_471 = out_rivalid_1_325 & out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4884 = out_f_rivalid_471; // @[RegisterRouter.scala:87:24] wire out_f_roready_471 = out_roready_1_325 & out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4885 = out_f_roready_471; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_471 = out_wivalid_1_325 & out_wimask_471; // @[RegisterRouter.scala:87:24] wire out_f_woready_471 = out_woready_1_325 & out_womask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4886 = ~out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4887 = ~out_wimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4888 = ~out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4889 = ~out_womask_471; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_396 = {hi_262, flags_0_go, _out_prepend_T_396}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4890 = out_prepend_396; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4891 = _out_T_4890; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_397 = _out_T_4891; // @[RegisterRouter.scala:87:24] wire out_rimask_472 = \|_out_rimask_T_472; // @[RegisterRouter.scala:87:24] wire out_wimask_472 = &_out_wimask_T_472; // @[RegisterRouter.scala:87:24] wire out_romask_472 = \|_out_romask_T_472; // @[RegisterRouter.scala:87:24] wire out_womask_472 = &_out_womask_T_472; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_472 = out_rivalid_1_326 & out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4893 = out_f_rivalid_472; // @[RegisterRouter.scala:87:24] wire out_f_roready_472 = out_roready_1_326 & out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4894 = out_f_roready_472; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_472 = out_wivalid_1_326 & out_wimask_472; // @[RegisterRouter.scala:87:24] wire out_f_woready_472 = out_woready_1_326 & out_womask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4895 = ~out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4896 = ~out_wimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4897 = ~out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4898 = ~out_womask_472; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_397 = {hi_263, flags_0_go, _out_prepend_T_397}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4899 = out_prepend_397; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4900 = _out_T_4899; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_398 = _out_T_4900; // @[RegisterRouter.scala:87:24] wire out_rimask_473 = \|_out_rimask_T_473; // @[RegisterRouter.scala:87:24] wire out_wimask_473 = &_out_wimask_T_473; // @[RegisterRouter.scala:87:24] wire out_romask_473 = \|_out_romask_T_473; // @[RegisterRouter.scala:87:24] wire out_womask_473 = &_out_womask_T_473; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_473 = out_rivalid_1_327 & out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4902 = out_f_rivalid_473; // @[RegisterRouter.scala:87:24] wire out_f_roready_473 = out_roready_1_327 & out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4903 = out_f_roready_473; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_473 = out_wivalid_1_327 & out_wimask_473; // @[RegisterRouter.scala:87:24] wire out_f_woready_473 = out_woready_1_327 & out_womask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4904 = ~out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4905 = ~out_wimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4906 = ~out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4907 = ~out_womask_473; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_398 = {hi_264, flags_0_go, _out_prepend_T_398}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4908 = out_prepend_398; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4909 = _out_T_4908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_160 = _out_T_4909; // @[MuxLiteral.scala:49:48] wire out_rimask_474 = \|_out_rimask_T_474; // @[RegisterRouter.scala:87:24] wire out_wimask_474 = &_out_wimask_T_474; // @[RegisterRouter.scala:87:24] wire out_romask_474 = \|_out_romask_T_474; // @[RegisterRouter.scala:87:24] wire out_womask_474 = &_out_womask_T_474; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_474 = out_rivalid_1_328 & out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4911 = out_f_rivalid_474; // @[RegisterRouter.scala:87:24] wire out_f_roready_474 = out_roready_1_328 & out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4912 = out_f_roready_474; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_474 = out_wivalid_1_328 & out_wimask_474; // @[RegisterRouter.scala:87:24] wire out_f_woready_474 = out_woready_1_328 & out_womask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4913 = ~out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4914 = ~out_wimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4915 = ~out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4916 = ~out_womask_474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4918 = _out_T_4917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_399 = _out_T_4918; // @[RegisterRouter.scala:87:24] wire out_rimask_475 = \|_out_rimask_T_475; // @[RegisterRouter.scala:87:24] wire out_wimask_475 = &_out_wimask_T_475; // @[RegisterRouter.scala:87:24] wire out_romask_475 = \|_out_romask_T_475; // @[RegisterRouter.scala:87:24] wire out_womask_475 = &_out_womask_T_475; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_475 = out_rivalid_1_329 & out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4920 = out_f_rivalid_475; // @[RegisterRouter.scala:87:24] wire out_f_roready_475 = out_roready_1_329 & out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4921 = out_f_roready_475; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_475 = out_wivalid_1_329 & out_wimask_475; // @[RegisterRouter.scala:87:24] wire out_f_woready_475 = out_woready_1_329 & out_womask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4922 = ~out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4923 = ~out_wimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4924 = ~out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4925 = ~out_womask_475; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_399 = {hi_514, flags_0_go, _out_prepend_T_399}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4926 = out_prepend_399; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4927 = _out_T_4926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_400 = _out_T_4927; // @[RegisterRouter.scala:87:24] wire out_rimask_476 = \|_out_rimask_T_476; // @[RegisterRouter.scala:87:24] wire out_wimask_476 = &_out_wimask_T_476; // @[RegisterRouter.scala:87:24] wire out_romask_476 = \|_out_romask_T_476; // @[RegisterRouter.scala:87:24] wire out_womask_476 = &_out_womask_T_476; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_476 = out_rivalid_1_330 & out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4929 = out_f_rivalid_476; // @[RegisterRouter.scala:87:24] wire out_f_roready_476 = out_roready_1_330 & out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4930 = out_f_roready_476; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_476 = out_wivalid_1_330 & out_wimask_476; // @[RegisterRouter.scala:87:24] wire out_f_woready_476 = out_woready_1_330 & out_womask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4931 = ~out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4932 = ~out_wimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4933 = ~out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4934 = ~out_womask_476; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_400 = {hi_515, flags_0_go, _out_prepend_T_400}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4935 = out_prepend_400; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4936 = _out_T_4935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_401 = _out_T_4936; // @[RegisterRouter.scala:87:24] wire out_rimask_477 = \|_out_rimask_T_477; // @[RegisterRouter.scala:87:24] wire out_wimask_477 = &_out_wimask_T_477; // @[RegisterRouter.scala:87:24] wire out_romask_477 = \|_out_romask_T_477; // @[RegisterRouter.scala:87:24] wire out_womask_477 = &_out_womask_T_477; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_477 = out_rivalid_1_331 & out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4938 = out_f_rivalid_477; // @[RegisterRouter.scala:87:24] wire out_f_roready_477 = out_roready_1_331 & out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4939 = out_f_roready_477; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_477 = out_wivalid_1_331 & out_wimask_477; // @[RegisterRouter.scala:87:24] wire out_f_woready_477 = out_woready_1_331 & out_womask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4940 = ~out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4941 = ~out_wimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4942 = ~out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4943 = ~out_womask_477; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_401 = {hi_516, flags_0_go, _out_prepend_T_401}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4944 = out_prepend_401; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4945 = _out_T_4944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_402 = _out_T_4945; // @[RegisterRouter.scala:87:24] wire out_rimask_478 = \|_out_rimask_T_478; // @[RegisterRouter.scala:87:24] wire out_wimask_478 = &_out_wimask_T_478; // @[RegisterRouter.scala:87:24] wire out_romask_478 = \|_out_romask_T_478; // @[RegisterRouter.scala:87:24] wire out_womask_478 = &_out_womask_T_478; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_478 = out_rivalid_1_332 & out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4947 = out_f_rivalid_478; // @[RegisterRouter.scala:87:24] wire out_f_roready_478 = out_roready_1_332 & out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4948 = out_f_roready_478; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_478 = out_wivalid_1_332 & out_wimask_478; // @[RegisterRouter.scala:87:24] wire out_f_woready_478 = out_woready_1_332 & out_womask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4949 = ~out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4950 = ~out_wimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4951 = ~out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4952 = ~out_womask_478; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_402 = {hi_517, flags_0_go, _out_prepend_T_402}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4953 = out_prepend_402; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4954 = _out_T_4953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_403 = _out_T_4954; // @[RegisterRouter.scala:87:24] wire out_rimask_479 = \|_out_rimask_T_479; // @[RegisterRouter.scala:87:24] wire out_wimask_479 = &_out_wimask_T_479; // @[RegisterRouter.scala:87:24] wire out_romask_479 = \|_out_romask_T_479; // @[RegisterRouter.scala:87:24] wire out_womask_479 = &_out_womask_T_479; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_479 = out_rivalid_1_333 & out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4956 = out_f_rivalid_479; // @[RegisterRouter.scala:87:24] wire out_f_roready_479 = out_roready_1_333 & out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4957 = out_f_roready_479; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_479 = out_wivalid_1_333 & out_wimask_479; // @[RegisterRouter.scala:87:24] wire out_f_woready_479 = out_woready_1_333 & out_womask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4958 = ~out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4959 = ~out_wimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4960 = ~out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4961 = ~out_womask_479; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_403 = {hi_518, flags_0_go, _out_prepend_T_403}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4962 = out_prepend_403; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4963 = _out_T_4962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_404 = _out_T_4963; // @[RegisterRouter.scala:87:24] wire out_rimask_480 = \|_out_rimask_T_480; // @[RegisterRouter.scala:87:24] wire out_wimask_480 = &_out_wimask_T_480; // @[RegisterRouter.scala:87:24] wire out_romask_480 = \|_out_romask_T_480; // @[RegisterRouter.scala:87:24] wire out_womask_480 = &_out_womask_T_480; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_480 = out_rivalid_1_334 & out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4965 = out_f_rivalid_480; // @[RegisterRouter.scala:87:24] wire out_f_roready_480 = out_roready_1_334 & out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4966 = out_f_roready_480; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_480 = out_wivalid_1_334 & out_wimask_480; // @[RegisterRouter.scala:87:24] wire out_f_woready_480 = out_woready_1_334 & out_womask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4967 = ~out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4968 = ~out_wimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4969 = ~out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4970 = ~out_womask_480; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_404 = {hi_519, flags_0_go, _out_prepend_T_404}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4971 = out_prepend_404; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4972 = _out_T_4971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_405 = _out_T_4972; // @[RegisterRouter.scala:87:24] wire out_rimask_481 = \|_out_rimask_T_481; // @[RegisterRouter.scala:87:24] wire out_wimask_481 = &_out_wimask_T_481; // @[RegisterRouter.scala:87:24] wire out_romask_481 = \|_out_romask_T_481; // @[RegisterRouter.scala:87:24] wire out_womask_481 = &_out_womask_T_481; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_481 = out_rivalid_1_335 & out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4974 = out_f_rivalid_481; // @[RegisterRouter.scala:87:24] wire out_f_roready_481 = out_roready_1_335 & out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4975 = out_f_roready_481; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_481 = out_wivalid_1_335 & out_wimask_481; // @[RegisterRouter.scala:87:24] wire out_f_woready_481 = out_woready_1_335 & out_womask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4976 = ~out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4977 = ~out_wimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4978 = ~out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4979 = ~out_womask_481; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_405 = {hi_520, flags_0_go, _out_prepend_T_405}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4980 = out_prepend_405; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4981 = _out_T_4980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_192 = _out_T_4981; // @[MuxLiteral.scala:49:48] wire out_rimask_482 = \|_out_rimask_T_482; // @[RegisterRouter.scala:87:24] wire out_wimask_482 = &_out_wimask_T_482; // @[RegisterRouter.scala:87:24] wire out_romask_482 = \|_out_romask_T_482; // @[RegisterRouter.scala:87:24] wire out_womask_482 = &_out_womask_T_482; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_482 = out_rivalid_1_336 & out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4983 = out_f_rivalid_482; // @[RegisterRouter.scala:87:24] wire out_f_roready_482 = out_roready_1_336 & out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4984 = out_f_roready_482; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_482 = out_wivalid_1_336 & out_wimask_482; // @[RegisterRouter.scala:87:24] wire out_f_woready_482 = out_woready_1_336 & out_womask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4985 = ~out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4986 = ~out_wimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4987 = ~out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4988 = ~out_womask_482; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4990 = _out_T_4989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_406 = _out_T_4990; // @[RegisterRouter.scala:87:24] wire out_rimask_483 = \|_out_rimask_T_483; // @[RegisterRouter.scala:87:24] wire out_wimask_483 = &_out_wimask_T_483; // @[RegisterRouter.scala:87:24] wire out_romask_483 = \|_out_romask_T_483; // @[RegisterRouter.scala:87:24] wire out_womask_483 = &_out_womask_T_483; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_483 = out_rivalid_1_337 & out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4992 = out_f_rivalid_483; // @[RegisterRouter.scala:87:24] wire out_f_roready_483 = out_roready_1_337 & out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4993 = out_f_roready_483; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_483 = out_wivalid_1_337 & out_wimask_483; // @[RegisterRouter.scala:87:24] wire out_f_woready_483 = out_woready_1_337 & out_womask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4994 = ~out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4995 = ~out_wimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4996 = ~out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4997 = ~out_womask_483; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_406 = {hi_74, flags_0_go, _out_prepend_T_406}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4998 = out_prepend_406; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4999 = _out_T_4998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_407 = _out_T_4999; // @[RegisterRouter.scala:87:24] wire out_rimask_484 = \|_out_rimask_T_484; // @[RegisterRouter.scala:87:24] wire out_wimask_484 = &_out_wimask_T_484; // @[RegisterRouter.scala:87:24] wire out_romask_484 = \|_out_romask_T_484; // @[RegisterRouter.scala:87:24] wire out_womask_484 = &_out_womask_T_484; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_484 = out_rivalid_1_338 & out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5001 = out_f_rivalid_484; // @[RegisterRouter.scala:87:24] wire out_f_roready_484 = out_roready_1_338 & out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5002 = out_f_roready_484; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_484 = out_wivalid_1_338 & out_wimask_484; // @[RegisterRouter.scala:87:24] wire out_f_woready_484 = out_woready_1_338 & out_womask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5003 = ~out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5004 = ~out_wimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5005 = ~out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5006 = ~out_womask_484; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_407 = {hi_75, flags_0_go, _out_prepend_T_407}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5007 = out_prepend_407; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5008 = _out_T_5007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_408 = _out_T_5008; // @[RegisterRouter.scala:87:24] wire out_rimask_485 = \|_out_rimask_T_485; // @[RegisterRouter.scala:87:24] wire out_wimask_485 = &_out_wimask_T_485; // @[RegisterRouter.scala:87:24] wire out_romask_485 = \|_out_romask_T_485; // @[RegisterRouter.scala:87:24] wire out_womask_485 = &_out_womask_T_485; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_485 = out_rivalid_1_339 & out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5010 = out_f_rivalid_485; // @[RegisterRouter.scala:87:24] wire out_f_roready_485 = out_roready_1_339 & out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5011 = out_f_roready_485; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_485 = out_wivalid_1_339 & out_wimask_485; // @[RegisterRouter.scala:87:24] wire out_f_woready_485 = out_woready_1_339 & out_womask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5012 = ~out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5013 = ~out_wimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5014 = ~out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5015 = ~out_womask_485; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_408 = {hi_76, flags_0_go, _out_prepend_T_408}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5016 = out_prepend_408; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5017 = _out_T_5016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_409 = _out_T_5017; // @[RegisterRouter.scala:87:24] wire out_rimask_486 = \|_out_rimask_T_486; // @[RegisterRouter.scala:87:24] wire out_wimask_486 = &_out_wimask_T_486; // @[RegisterRouter.scala:87:24] wire out_romask_486 = \|_out_romask_T_486; // @[RegisterRouter.scala:87:24] wire out_womask_486 = &_out_womask_T_486; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_486 = out_rivalid_1_340 & out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5019 = out_f_rivalid_486; // @[RegisterRouter.scala:87:24] wire out_f_roready_486 = out_roready_1_340 & out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5020 = out_f_roready_486; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_486 = out_wivalid_1_340 & out_wimask_486; // @[RegisterRouter.scala:87:24] wire out_f_woready_486 = out_woready_1_340 & out_womask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5021 = ~out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5022 = ~out_wimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5023 = ~out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5024 = ~out_womask_486; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_409 = {hi_77, flags_0_go, _out_prepend_T_409}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5025 = out_prepend_409; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5026 = _out_T_5025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_410 = _out_T_5026; // @[RegisterRouter.scala:87:24] wire out_rimask_487 = \|_out_rimask_T_487; // @[RegisterRouter.scala:87:24] wire out_wimask_487 = &_out_wimask_T_487; // @[RegisterRouter.scala:87:24] wire out_romask_487 = \|_out_romask_T_487; // @[RegisterRouter.scala:87:24] wire out_womask_487 = &_out_womask_T_487; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_487 = out_rivalid_1_341 & out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5028 = out_f_rivalid_487; // @[RegisterRouter.scala:87:24] wire out_f_roready_487 = out_roready_1_341 & out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5029 = out_f_roready_487; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_487 = out_wivalid_1_341 & out_wimask_487; // @[RegisterRouter.scala:87:24] wire out_f_woready_487 = out_woready_1_341 & out_womask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5030 = ~out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5031 = ~out_wimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5032 = ~out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5033 = ~out_womask_487; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_410 = {hi_78, flags_0_go, _out_prepend_T_410}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5034 = out_prepend_410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5035 = _out_T_5034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_411 = _out_T_5035; // @[RegisterRouter.scala:87:24] wire out_rimask_488 = \|_out_rimask_T_488; // @[RegisterRouter.scala:87:24] wire out_wimask_488 = &_out_wimask_T_488; // @[RegisterRouter.scala:87:24] wire out_romask_488 = \|_out_romask_T_488; // @[RegisterRouter.scala:87:24] wire out_womask_488 = &_out_womask_T_488; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_488 = out_rivalid_1_342 & out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5037 = out_f_rivalid_488; // @[RegisterRouter.scala:87:24] wire out_f_roready_488 = out_roready_1_342 & out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5038 = out_f_roready_488; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_488 = out_wivalid_1_342 & out_wimask_488; // @[RegisterRouter.scala:87:24] wire out_f_woready_488 = out_woready_1_342 & out_womask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5039 = ~out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5040 = ~out_wimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5041 = ~out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5042 = ~out_womask_488; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_411 = {hi_79, flags_0_go, _out_prepend_T_411}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5043 = out_prepend_411; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5044 = _out_T_5043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_412 = _out_T_5044; // @[RegisterRouter.scala:87:24] wire out_rimask_489 = \|_out_rimask_T_489; // @[RegisterRouter.scala:87:24] wire out_wimask_489 = &_out_wimask_T_489; // @[RegisterRouter.scala:87:24] wire out_romask_489 = \|_out_romask_T_489; // @[RegisterRouter.scala:87:24] wire out_womask_489 = &_out_womask_T_489; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_489 = out_rivalid_1_343 & out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5046 = out_f_rivalid_489; // @[RegisterRouter.scala:87:24] wire out_f_roready_489 = out_roready_1_343 & out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5047 = out_f_roready_489; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_489 = out_wivalid_1_343 & out_wimask_489; // @[RegisterRouter.scala:87:24] wire out_f_woready_489 = out_woready_1_343 & out_womask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5048 = ~out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5049 = ~out_wimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5050 = ~out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5051 = ~out_womask_489; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_412 = {hi_80, flags_0_go, _out_prepend_T_412}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5052 = out_prepend_412; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5053 = _out_T_5052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_137 = _out_T_5053; // @[MuxLiteral.scala:49:48] wire out_rimask_490 = \|_out_rimask_T_490; // @[RegisterRouter.scala:87:24] wire out_wimask_490 = &_out_wimask_T_490; // @[RegisterRouter.scala:87:24] wire out_romask_490 = \|_out_romask_T_490; // @[RegisterRouter.scala:87:24] wire out_womask_490 = &_out_womask_T_490; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_490 = out_rivalid_1_344 & out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5055 = out_f_rivalid_490; // @[RegisterRouter.scala:87:24] wire out_f_roready_490 = out_roready_1_344 & out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5056 = out_f_roready_490; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_490 = out_wivalid_1_344 & out_wimask_490; // @[RegisterRouter.scala:87:24] wire out_f_woready_490 = out_woready_1_344 & out_womask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5057 = ~out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5058 = ~out_wimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5059 = ~out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5060 = ~out_womask_490; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5062 = _out_T_5061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_413 = _out_T_5062; // @[RegisterRouter.scala:87:24] wire out_rimask_491 = \|_out_rimask_T_491; // @[RegisterRouter.scala:87:24] wire out_wimask_491 = &_out_wimask_T_491; // @[RegisterRouter.scala:87:24] wire out_romask_491 = \|_out_romask_T_491; // @[RegisterRouter.scala:87:24] wire out_womask_491 = &_out_womask_T_491; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_491 = out_rivalid_1_345 & out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5064 = out_f_rivalid_491; // @[RegisterRouter.scala:87:24] wire out_f_roready_491 = out_roready_1_345 & out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5065 = out_f_roready_491; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_491 = out_wivalid_1_345 & out_wimask_491; // @[RegisterRouter.scala:87:24] wire out_f_woready_491 = out_woready_1_345 & out_womask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5066 = ~out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5067 = ~out_wimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5068 = ~out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5069 = ~out_womask_491; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_413 = {hi_298, flags_0_go, _out_prepend_T_413}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5070 = out_prepend_413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5071 = _out_T_5070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_414 = _out_T_5071; // @[RegisterRouter.scala:87:24] wire out_rimask_492 = \|_out_rimask_T_492; // @[RegisterRouter.scala:87:24] wire out_wimask_492 = &_out_wimask_T_492; // @[RegisterRouter.scala:87:24] wire out_romask_492 = \|_out_romask_T_492; // @[RegisterRouter.scala:87:24] wire out_womask_492 = &_out_womask_T_492; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_492 = out_rivalid_1_346 & out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5073 = out_f_rivalid_492; // @[RegisterRouter.scala:87:24] wire out_f_roready_492 = out_roready_1_346 & out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5074 = out_f_roready_492; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_492 = out_wivalid_1_346 & out_wimask_492; // @[RegisterRouter.scala:87:24] wire out_f_woready_492 = out_woready_1_346 & out_womask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5075 = ~out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5076 = ~out_wimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5077 = ~out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5078 = ~out_womask_492; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_414 = {hi_299, flags_0_go, _out_prepend_T_414}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5079 = out_prepend_414; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5080 = _out_T_5079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_415 = _out_T_5080; // @[RegisterRouter.scala:87:24] wire out_rimask_493 = \|_out_rimask_T_493; // @[RegisterRouter.scala:87:24] wire out_wimask_493 = &_out_wimask_T_493; // @[RegisterRouter.scala:87:24] wire out_romask_493 = \|_out_romask_T_493; // @[RegisterRouter.scala:87:24] wire out_womask_493 = &_out_womask_T_493; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_493 = out_rivalid_1_347 & out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5082 = out_f_rivalid_493; // @[RegisterRouter.scala:87:24] wire out_f_roready_493 = out_roready_1_347 & out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5083 = out_f_roready_493; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_493 = out_wivalid_1_347 & out_wimask_493; // @[RegisterRouter.scala:87:24] wire out_f_woready_493 = out_woready_1_347 & out_womask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5084 = ~out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5085 = ~out_wimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5086 = ~out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5087 = ~out_womask_493; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_415 = {hi_300, flags_0_go, _out_prepend_T_415}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5088 = out_prepend_415; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5089 = _out_T_5088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_416 = _out_T_5089; // @[RegisterRouter.scala:87:24] wire out_rimask_494 = \|_out_rimask_T_494; // @[RegisterRouter.scala:87:24] wire out_wimask_494 = &_out_wimask_T_494; // @[RegisterRouter.scala:87:24] wire out_romask_494 = \|_out_romask_T_494; // @[RegisterRouter.scala:87:24] wire out_womask_494 = &_out_womask_T_494; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_494 = out_rivalid_1_348 & out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5091 = out_f_rivalid_494; // @[RegisterRouter.scala:87:24] wire out_f_roready_494 = out_roready_1_348 & out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5092 = out_f_roready_494; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_494 = out_wivalid_1_348 & out_wimask_494; // @[RegisterRouter.scala:87:24] wire out_f_woready_494 = out_woready_1_348 & out_womask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5093 = ~out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5094 = ~out_wimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5095 = ~out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5096 = ~out_womask_494; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_416 = {hi_301, flags_0_go, _out_prepend_T_416}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5097 = out_prepend_416; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5098 = _out_T_5097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_417 = _out_T_5098; // @[RegisterRouter.scala:87:24] wire out_rimask_495 = \|_out_rimask_T_495; // @[RegisterRouter.scala:87:24] wire out_wimask_495 = &_out_wimask_T_495; // @[RegisterRouter.scala:87:24] wire out_romask_495 = \|_out_romask_T_495; // @[RegisterRouter.scala:87:24] wire out_womask_495 = &_out_womask_T_495; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_495 = out_rivalid_1_349 & out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5100 = out_f_rivalid_495; // @[RegisterRouter.scala:87:24] wire out_f_roready_495 = out_roready_1_349 & out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5101 = out_f_roready_495; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_495 = out_wivalid_1_349 & out_wimask_495; // @[RegisterRouter.scala:87:24] wire out_f_woready_495 = out_woready_1_349 & out_womask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5102 = ~out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5103 = ~out_wimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5104 = ~out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5105 = ~out_womask_495; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_417 = {hi_302, flags_0_go, _out_prepend_T_417}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5106 = out_prepend_417; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5107 = _out_T_5106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_418 = _out_T_5107; // @[RegisterRouter.scala:87:24] wire out_rimask_496 = \|_out_rimask_T_496; // @[RegisterRouter.scala:87:24] wire out_wimask_496 = &_out_wimask_T_496; // @[RegisterRouter.scala:87:24] wire out_romask_496 = \|_out_romask_T_496; // @[RegisterRouter.scala:87:24] wire out_womask_496 = &_out_womask_T_496; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_496 = out_rivalid_1_350 & out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5109 = out_f_rivalid_496; // @[RegisterRouter.scala:87:24] wire out_f_roready_496 = out_roready_1_350 & out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5110 = out_f_roready_496; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_496 = out_wivalid_1_350 & out_wimask_496; // @[RegisterRouter.scala:87:24] wire out_f_woready_496 = out_woready_1_350 & out_womask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5111 = ~out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5112 = ~out_wimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5113 = ~out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5114 = ~out_womask_496; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_418 = {hi_303, flags_0_go, _out_prepend_T_418}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5115 = out_prepend_418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5116 = _out_T_5115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_419 = _out_T_5116; // @[RegisterRouter.scala:87:24] wire out_rimask_497 = \|_out_rimask_T_497; // @[RegisterRouter.scala:87:24] wire out_wimask_497 = &_out_wimask_T_497; // @[RegisterRouter.scala:87:24] wire out_romask_497 = \|_out_romask_T_497; // @[RegisterRouter.scala:87:24] wire out_womask_497 = &_out_womask_T_497; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_497 = out_rivalid_1_351 & out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5118 = out_f_rivalid_497; // @[RegisterRouter.scala:87:24] wire out_f_roready_497 = out_roready_1_351 & out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5119 = out_f_roready_497; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_497 = out_wivalid_1_351 & out_wimask_497; // @[RegisterRouter.scala:87:24] wire out_f_woready_497 = out_woready_1_351 & out_womask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5120 = ~out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5121 = ~out_wimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5122 = ~out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5123 = ~out_womask_497; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_419 = {hi_304, flags_0_go, _out_prepend_T_419}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5124 = out_prepend_419; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5125 = _out_T_5124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_165 = _out_T_5125; // @[MuxLiteral.scala:49:48] wire [9:0] _out_rimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_498 = \|_out_rimask_T_498; // @[RegisterRouter.scala:87:24] wire out_wimask_498 = &_out_wimask_T_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_romask_498 = \|_out_romask_T_498; // @[RegisterRouter.scala:87:24] wire out_womask_498 = &_out_womask_T_498; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_498 = out_rivalid_1_352 & out_rimask_498; // @[RegisterRouter.scala:87:24] wire out_f_roready_498 = out_roready_1_352 & out_romask_498; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_498 = out_wivalid_1_352 & out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5127 = out_f_wivalid_498; // @[RegisterRouter.scala:87:24] assign out_f_woready_498 = out_woready_1_352 & out_womask_498; // @[RegisterRouter.scala:87:24] assign hartResumingWrEn = out_f_woready_498; // @[RegisterRouter.scala:87:24] wire _out_T_5128 = out_f_woready_498; // @[RegisterRouter.scala:87:24] assign _out_T_5126 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign _out_T_6805 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign hartResumingId = _out_T_5126; // @[RegisterRouter.scala:87:24] wire _out_T_5129 = ~out_rimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5130 = ~out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5131 = ~out_romask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5132 = ~out_womask_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_499 = \|_out_rimask_T_499; // @[RegisterRouter.scala:87:24] wire out_wimask_499 = &_out_wimask_T_499; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_romask_499 = \|_out_romask_T_499; // @[RegisterRouter.scala:87:24] wire out_womask_499 = &_out_womask_T_499; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_499 = out_rivalid_1_353 & out_rimask_499; // @[RegisterRouter.scala:87:24] wire out_f_roready_499 = out_roready_1_353 & out_romask_499; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_499 = out_wivalid_1_353 & out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5136 = out_f_wivalid_499; // @[RegisterRouter.scala:87:24] assign out_f_woready_499 = out_woready_1_353 & out_womask_499; // @[RegisterRouter.scala:87:24] assign hartExceptionWrEn = out_f_woready_499; // @[RegisterRouter.scala:87:24] wire _out_T_5137 = out_f_woready_499; // @[RegisterRouter.scala:87:24] assign _out_T_5135 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign _out_T_6814 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign hartExceptionId = _out_T_5135; // @[RegisterRouter.scala:87:24] wire _out_T_5138 = ~out_rimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5139 = ~out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5140 = ~out_romask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5141 = ~out_womask_499; // @[RegisterRouter.scala:87:24] wire out_rimask_500 = \|_out_rimask_T_500; // @[RegisterRouter.scala:87:24] wire out_wimask_500 = &_out_wimask_T_500; // @[RegisterRouter.scala:87:24] wire out_romask_500 = \|_out_romask_T_500; // @[RegisterRouter.scala:87:24] wire out_womask_500 = &_out_womask_T_500; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_500 = out_rivalid_1_354 & out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5145 = out_f_rivalid_500; // @[RegisterRouter.scala:87:24] wire out_f_roready_500 = out_roready_1_354 & out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5146 = out_f_roready_500; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_500 = out_wivalid_1_354 & out_wimask_500; // @[RegisterRouter.scala:87:24] wire out_f_woready_500 = out_woready_1_354 & out_womask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5147 = ~out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5148 = ~out_wimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5149 = ~out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5150 = ~out_womask_500; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5152 = _out_T_5151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_421 = _out_T_5152; // @[RegisterRouter.scala:87:24] wire out_rimask_501 = \|_out_rimask_T_501; // @[RegisterRouter.scala:87:24] wire out_wimask_501 = &_out_wimask_T_501; // @[RegisterRouter.scala:87:24] wire out_romask_501 = \|_out_romask_T_501; // @[RegisterRouter.scala:87:24] wire out_womask_501 = &_out_womask_T_501; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_501 = out_rivalid_1_355 & out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5154 = out_f_rivalid_501; // @[RegisterRouter.scala:87:24] wire out_f_roready_501 = out_roready_1_355 & out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5155 = out_f_roready_501; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_501 = out_wivalid_1_355 & out_wimask_501; // @[RegisterRouter.scala:87:24] wire out_f_woready_501 = out_woready_1_355 & out_womask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5156 = ~out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5157 = ~out_wimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5158 = ~out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5159 = ~out_womask_501; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_421 = {hi_810, flags_0_go, _out_prepend_T_421}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5160 = out_prepend_421; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5161 = _out_T_5160; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_422 = _out_T_5161; // @[RegisterRouter.scala:87:24] wire out_rimask_502 = \|_out_rimask_T_502; // @[RegisterRouter.scala:87:24] wire out_wimask_502 = &_out_wimask_T_502; // @[RegisterRouter.scala:87:24] wire out_romask_502 = \|_out_romask_T_502; // @[RegisterRouter.scala:87:24] wire out_womask_502 = &_out_womask_T_502; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_502 = out_rivalid_1_356 & out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5163 = out_f_rivalid_502; // @[RegisterRouter.scala:87:24] wire out_f_roready_502 = out_roready_1_356 & out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5164 = out_f_roready_502; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_502 = out_wivalid_1_356 & out_wimask_502; // @[RegisterRouter.scala:87:24] wire out_f_woready_502 = out_woready_1_356 & out_womask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5165 = ~out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5166 = ~out_wimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5167 = ~out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5168 = ~out_womask_502; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_422 = {hi_811, flags_0_go, _out_prepend_T_422}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5169 = out_prepend_422; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5170 = _out_T_5169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_423 = _out_T_5170; // @[RegisterRouter.scala:87:24] wire out_rimask_503 = \|_out_rimask_T_503; // @[RegisterRouter.scala:87:24] wire out_wimask_503 = &_out_wimask_T_503; // @[RegisterRouter.scala:87:24] wire out_romask_503 = \|_out_romask_T_503; // @[RegisterRouter.scala:87:24] wire out_womask_503 = &_out_womask_T_503; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_503 = out_rivalid_1_357 & out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5172 = out_f_rivalid_503; // @[RegisterRouter.scala:87:24] wire out_f_roready_503 = out_roready_1_357 & out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5173 = out_f_roready_503; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_503 = out_wivalid_1_357 & out_wimask_503; // @[RegisterRouter.scala:87:24] wire out_f_woready_503 = out_woready_1_357 & out_womask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5174 = ~out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5175 = ~out_wimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5176 = ~out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5177 = ~out_womask_503; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_423 = {hi_812, flags_0_go, _out_prepend_T_423}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5178 = out_prepend_423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5179 = _out_T_5178; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_424 = _out_T_5179; // @[RegisterRouter.scala:87:24] wire out_rimask_504 = \|_out_rimask_T_504; // @[RegisterRouter.scala:87:24] wire out_wimask_504 = &_out_wimask_T_504; // @[RegisterRouter.scala:87:24] wire out_romask_504 = \|_out_romask_T_504; // @[RegisterRouter.scala:87:24] wire out_womask_504 = &_out_womask_T_504; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_504 = out_rivalid_1_358 & out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5181 = out_f_rivalid_504; // @[RegisterRouter.scala:87:24] wire out_f_roready_504 = out_roready_1_358 & out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5182 = out_f_roready_504; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_504 = out_wivalid_1_358 & out_wimask_504; // @[RegisterRouter.scala:87:24] wire out_f_woready_504 = out_woready_1_358 & out_womask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5183 = ~out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5184 = ~out_wimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5185 = ~out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5186 = ~out_womask_504; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_424 = {hi_813, flags_0_go, _out_prepend_T_424}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5187 = out_prepend_424; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5188 = _out_T_5187; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_425 = _out_T_5188; // @[RegisterRouter.scala:87:24] wire out_rimask_505 = \|_out_rimask_T_505; // @[RegisterRouter.scala:87:24] wire out_wimask_505 = &_out_wimask_T_505; // @[RegisterRouter.scala:87:24] wire out_romask_505 = \|_out_romask_T_505; // @[RegisterRouter.scala:87:24] wire out_womask_505 = &_out_womask_T_505; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_505 = out_rivalid_1_359 & out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5190 = out_f_rivalid_505; // @[RegisterRouter.scala:87:24] wire out_f_roready_505 = out_roready_1_359 & out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5191 = out_f_roready_505; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_505 = out_wivalid_1_359 & out_wimask_505; // @[RegisterRouter.scala:87:24] wire out_f_woready_505 = out_woready_1_359 & out_womask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5192 = ~out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5193 = ~out_wimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5194 = ~out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5195 = ~out_womask_505; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_425 = {hi_814, flags_0_go, _out_prepend_T_425}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5196 = out_prepend_425; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5197 = _out_T_5196; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_426 = _out_T_5197; // @[RegisterRouter.scala:87:24] wire out_rimask_506 = \|_out_rimask_T_506; // @[RegisterRouter.scala:87:24] wire out_wimask_506 = &_out_wimask_T_506; // @[RegisterRouter.scala:87:24] wire out_romask_506 = \|_out_romask_T_506; // @[RegisterRouter.scala:87:24] wire out_womask_506 = &_out_womask_T_506; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_506 = out_rivalid_1_360 & out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5199 = out_f_rivalid_506; // @[RegisterRouter.scala:87:24] wire out_f_roready_506 = out_roready_1_360 & out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5200 = out_f_roready_506; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_506 = out_wivalid_1_360 & out_wimask_506; // @[RegisterRouter.scala:87:24] wire out_f_woready_506 = out_woready_1_360 & out_womask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5201 = ~out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5202 = ~out_wimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5203 = ~out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5204 = ~out_womask_506; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_426 = {hi_815, flags_0_go, _out_prepend_T_426}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5205 = out_prepend_426; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5206 = _out_T_5205; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_427 = _out_T_5206; // @[RegisterRouter.scala:87:24] wire out_rimask_507 = \|_out_rimask_T_507; // @[RegisterRouter.scala:87:24] wire out_wimask_507 = &_out_wimask_T_507; // @[RegisterRouter.scala:87:24] wire out_romask_507 = \|_out_romask_T_507; // @[RegisterRouter.scala:87:24] wire out_womask_507 = &_out_womask_T_507; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_507 = out_rivalid_1_361 & out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5208 = out_f_rivalid_507; // @[RegisterRouter.scala:87:24] wire out_f_roready_507 = out_roready_1_361 & out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5209 = out_f_roready_507; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_507 = out_wivalid_1_361 & out_wimask_507; // @[RegisterRouter.scala:87:24] wire out_f_woready_507 = out_woready_1_361 & out_womask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5210 = ~out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5211 = ~out_wimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5212 = ~out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5213 = ~out_womask_507; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_427 = {hi_816, flags_0_go, _out_prepend_T_427}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5214 = out_prepend_427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5215 = _out_T_5214; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_229 = _out_T_5215; // @[MuxLiteral.scala:49:48] wire out_rimask_508 = \|_out_rimask_T_508; // @[RegisterRouter.scala:87:24] wire out_wimask_508 = &_out_wimask_T_508; // @[RegisterRouter.scala:87:24] wire out_romask_508 = \|_out_romask_T_508; // @[RegisterRouter.scala:87:24] wire out_womask_508 = &_out_womask_T_508; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_508 = out_rivalid_1_362 & out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5217 = out_f_rivalid_508; // @[RegisterRouter.scala:87:24] wire out_f_roready_508 = out_roready_1_362 & out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5218 = out_f_roready_508; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_508 = out_wivalid_1_362 & out_wimask_508; // @[RegisterRouter.scala:87:24] wire out_f_woready_508 = out_woready_1_362 & out_womask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5219 = ~out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5220 = ~out_wimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5221 = ~out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5222 = ~out_womask_508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5224 = _out_T_5223; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_428 = _out_T_5224; // @[RegisterRouter.scala:87:24] wire out_rimask_509 = \|_out_rimask_T_509; // @[RegisterRouter.scala:87:24] wire out_wimask_509 = &_out_wimask_T_509; // @[RegisterRouter.scala:87:24] wire out_romask_509 = \|_out_romask_T_509; // @[RegisterRouter.scala:87:24] wire out_womask_509 = &_out_womask_T_509; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_509 = out_rivalid_1_363 & out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5226 = out_f_rivalid_509; // @[RegisterRouter.scala:87:24] wire out_f_roready_509 = out_roready_1_363 & out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5227 = out_f_roready_509; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_509 = out_wivalid_1_363 & out_wimask_509; // @[RegisterRouter.scala:87:24] wire out_f_woready_509 = out_woready_1_363 & out_womask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5228 = ~out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5229 = ~out_wimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5230 = ~out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5231 = ~out_womask_509; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_428 = {hi_994, flags_0_go, _out_prepend_T_428}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5232 = out_prepend_428; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5233 = _out_T_5232; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_429 = _out_T_5233; // @[RegisterRouter.scala:87:24] wire out_rimask_510 = \|_out_rimask_T_510; // @[RegisterRouter.scala:87:24] wire out_wimask_510 = &_out_wimask_T_510; // @[RegisterRouter.scala:87:24] wire out_romask_510 = \|_out_romask_T_510; // @[RegisterRouter.scala:87:24] wire out_womask_510 = &_out_womask_T_510; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_510 = out_rivalid_1_364 & out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5235 = out_f_rivalid_510; // @[RegisterRouter.scala:87:24] wire out_f_roready_510 = out_roready_1_364 & out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5236 = out_f_roready_510; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_510 = out_wivalid_1_364 & out_wimask_510; // @[RegisterRouter.scala:87:24] wire out_f_woready_510 = out_woready_1_364 & out_womask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5237 = ~out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5238 = ~out_wimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5239 = ~out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5240 = ~out_womask_510; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_429 = {hi_995, flags_0_go, _out_prepend_T_429}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5241 = out_prepend_429; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5242 = _out_T_5241; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_430 = _out_T_5242; // @[RegisterRouter.scala:87:24] wire out_rimask_511 = \|_out_rimask_T_511; // @[RegisterRouter.scala:87:24] wire out_wimask_511 = &_out_wimask_T_511; // @[RegisterRouter.scala:87:24] wire out_romask_511 = \|_out_romask_T_511; // @[RegisterRouter.scala:87:24] wire out_womask_511 = &_out_womask_T_511; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_511 = out_rivalid_1_365 & out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5244 = out_f_rivalid_511; // @[RegisterRouter.scala:87:24] wire out_f_roready_511 = out_roready_1_365 & out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5245 = out_f_roready_511; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_511 = out_wivalid_1_365 & out_wimask_511; // @[RegisterRouter.scala:87:24] wire out_f_woready_511 = out_woready_1_365 & out_womask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5246 = ~out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5247 = ~out_wimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5248 = ~out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5249 = ~out_womask_511; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_430 = {hi_996, flags_0_go, _out_prepend_T_430}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5250 = out_prepend_430; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5251 = _out_T_5250; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_431 = _out_T_5251; // @[RegisterRouter.scala:87:24] wire out_rimask_512 = \|_out_rimask_T_512; // @[RegisterRouter.scala:87:24] wire out_wimask_512 = &_out_wimask_T_512; // @[RegisterRouter.scala:87:24] wire out_romask_512 = \|_out_romask_T_512; // @[RegisterRouter.scala:87:24] wire out_womask_512 = &_out_womask_T_512; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_512 = out_rivalid_1_366 & out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5253 = out_f_rivalid_512; // @[RegisterRouter.scala:87:24] wire out_f_roready_512 = out_roready_1_366 & out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5254 = out_f_roready_512; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_512 = out_wivalid_1_366 & out_wimask_512; // @[RegisterRouter.scala:87:24] wire out_f_woready_512 = out_woready_1_366 & out_womask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5255 = ~out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5256 = ~out_wimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5257 = ~out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5258 = ~out_womask_512; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_431 = {hi_997, flags_0_go, _out_prepend_T_431}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5259 = out_prepend_431; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5260 = _out_T_5259; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_432 = _out_T_5260; // @[RegisterRouter.scala:87:24] wire out_rimask_513 = \|_out_rimask_T_513; // @[RegisterRouter.scala:87:24] wire out_wimask_513 = &_out_wimask_T_513; // @[RegisterRouter.scala:87:24] wire out_romask_513 = \|_out_romask_T_513; // @[RegisterRouter.scala:87:24] wire out_womask_513 = &_out_womask_T_513; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_513 = out_rivalid_1_367 & out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5262 = out_f_rivalid_513; // @[RegisterRouter.scala:87:24] wire out_f_roready_513 = out_roready_1_367 & out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5263 = out_f_roready_513; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_513 = out_wivalid_1_367 & out_wimask_513; // @[RegisterRouter.scala:87:24] wire out_f_woready_513 = out_woready_1_367 & out_womask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5264 = ~out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5265 = ~out_wimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5266 = ~out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5267 = ~out_womask_513; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_432 = {hi_998, flags_0_go, _out_prepend_T_432}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5268 = out_prepend_432; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5269 = _out_T_5268; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_433 = _out_T_5269; // @[RegisterRouter.scala:87:24] wire out_rimask_514 = \|_out_rimask_T_514; // @[RegisterRouter.scala:87:24] wire out_wimask_514 = &_out_wimask_T_514; // @[RegisterRouter.scala:87:24] wire out_romask_514 = \|_out_romask_T_514; // @[RegisterRouter.scala:87:24] wire out_womask_514 = &_out_womask_T_514; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_514 = out_rivalid_1_368 & out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5271 = out_f_rivalid_514; // @[RegisterRouter.scala:87:24] wire out_f_roready_514 = out_roready_1_368 & out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5272 = out_f_roready_514; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_514 = out_wivalid_1_368 & out_wimask_514; // @[RegisterRouter.scala:87:24] wire out_f_woready_514 = out_woready_1_368 & out_womask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5273 = ~out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5274 = ~out_wimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5275 = ~out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5276 = ~out_womask_514; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_433 = {hi_999, flags_0_go, _out_prepend_T_433}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5277 = out_prepend_433; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5278 = _out_T_5277; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_434 = _out_T_5278; // @[RegisterRouter.scala:87:24] wire out_rimask_515 = \|_out_rimask_T_515; // @[RegisterRouter.scala:87:24] wire out_wimask_515 = &_out_wimask_T_515; // @[RegisterRouter.scala:87:24] wire out_romask_515 = \|_out_romask_T_515; // @[RegisterRouter.scala:87:24] wire out_womask_515 = &_out_womask_T_515; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_515 = out_rivalid_1_369 & out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5280 = out_f_rivalid_515; // @[RegisterRouter.scala:87:24] wire out_f_roready_515 = out_roready_1_369 & out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5281 = out_f_roready_515; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_515 = out_wivalid_1_369 & out_wimask_515; // @[RegisterRouter.scala:87:24] wire out_f_woready_515 = out_woready_1_369 & out_womask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5282 = ~out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5283 = ~out_wimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5284 = ~out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5285 = ~out_womask_515; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_434 = {hi_1000, flags_0_go, _out_prepend_T_434}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5286 = out_prepend_434; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5287 = _out_T_5286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_252 = _out_T_5287; // @[MuxLiteral.scala:49:48] wire out_rimask_516 = \|_out_rimask_T_516; // @[RegisterRouter.scala:87:24] wire out_wimask_516 = &_out_wimask_T_516; // @[RegisterRouter.scala:87:24] wire out_romask_516 = \|_out_romask_T_516; // @[RegisterRouter.scala:87:24] wire out_womask_516 = &_out_womask_T_516; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_516 = out_rivalid_1_370 & out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5289 = out_f_rivalid_516; // @[RegisterRouter.scala:87:24] wire out_f_roready_516 = out_roready_1_370 & out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5290 = out_f_roready_516; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_516 = out_wivalid_1_370 & out_wimask_516; // @[RegisterRouter.scala:87:24] wire out_f_woready_516 = out_woready_1_370 & out_womask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5291 = ~out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5292 = ~out_wimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5293 = ~out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5294 = ~out_womask_516; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5296 = _out_T_5295; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_435 = _out_T_5296; // @[RegisterRouter.scala:87:24] wire out_rimask_517 = \|_out_rimask_T_517; // @[RegisterRouter.scala:87:24] wire out_wimask_517 = &_out_wimask_T_517; // @[RegisterRouter.scala:87:24] wire out_romask_517 = \|_out_romask_T_517; // @[RegisterRouter.scala:87:24] wire out_womask_517 = &_out_womask_T_517; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_517 = out_rivalid_1_371 & out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5298 = out_f_rivalid_517; // @[RegisterRouter.scala:87:24] wire out_f_roready_517 = out_roready_1_371 & out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5299 = out_f_roready_517; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_517 = out_wivalid_1_371 & out_wimask_517; // @[RegisterRouter.scala:87:24] wire out_f_woready_517 = out_woready_1_371 & out_womask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5300 = ~out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5301 = ~out_wimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5302 = ~out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5303 = ~out_womask_517; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_435 = {hi_554, flags_0_go, _out_prepend_T_435}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5304 = out_prepend_435; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5305 = _out_T_5304; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_436 = _out_T_5305; // @[RegisterRouter.scala:87:24] wire out_rimask_518 = \|_out_rimask_T_518; // @[RegisterRouter.scala:87:24] wire out_wimask_518 = &_out_wimask_T_518; // @[RegisterRouter.scala:87:24] wire out_romask_518 = \|_out_romask_T_518; // @[RegisterRouter.scala:87:24] wire out_womask_518 = &_out_womask_T_518; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_518 = out_rivalid_1_372 & out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5307 = out_f_rivalid_518; // @[RegisterRouter.scala:87:24] wire out_f_roready_518 = out_roready_1_372 & out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5308 = out_f_roready_518; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_518 = out_wivalid_1_372 & out_wimask_518; // @[RegisterRouter.scala:87:24] wire out_f_woready_518 = out_woready_1_372 & out_womask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5309 = ~out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5310 = ~out_wimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5311 = ~out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5312 = ~out_womask_518; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_436 = {hi_555, flags_0_go, _out_prepend_T_436}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5313 = out_prepend_436; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5314 = _out_T_5313; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_437 = _out_T_5314; // @[RegisterRouter.scala:87:24] wire out_rimask_519 = \|_out_rimask_T_519; // @[RegisterRouter.scala:87:24] wire out_wimask_519 = &_out_wimask_T_519; // @[RegisterRouter.scala:87:24] wire out_romask_519 = \|_out_romask_T_519; // @[RegisterRouter.scala:87:24] wire out_womask_519 = &_out_womask_T_519; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_519 = out_rivalid_1_373 & out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5316 = out_f_rivalid_519; // @[RegisterRouter.scala:87:24] wire out_f_roready_519 = out_roready_1_373 & out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5317 = out_f_roready_519; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_519 = out_wivalid_1_373 & out_wimask_519; // @[RegisterRouter.scala:87:24] wire out_f_woready_519 = out_woready_1_373 & out_womask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5318 = ~out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5319 = ~out_wimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5320 = ~out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5321 = ~out_womask_519; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_437 = {hi_556, flags_0_go, _out_prepend_T_437}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5322 = out_prepend_437; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5323 = _out_T_5322; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_438 = _out_T_5323; // @[RegisterRouter.scala:87:24] wire out_rimask_520 = \|_out_rimask_T_520; // @[RegisterRouter.scala:87:24] wire out_wimask_520 = &_out_wimask_T_520; // @[RegisterRouter.scala:87:24] wire out_romask_520 = \|_out_romask_T_520; // @[RegisterRouter.scala:87:24] wire out_womask_520 = &_out_womask_T_520; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_520 = out_rivalid_1_374 & out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5325 = out_f_rivalid_520; // @[RegisterRouter.scala:87:24] wire out_f_roready_520 = out_roready_1_374 & out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5326 = out_f_roready_520; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_520 = out_wivalid_1_374 & out_wimask_520; // @[RegisterRouter.scala:87:24] wire out_f_woready_520 = out_woready_1_374 & out_womask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5327 = ~out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5328 = ~out_wimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5329 = ~out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5330 = ~out_womask_520; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_438 = {hi_557, flags_0_go, _out_prepend_T_438}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5331 = out_prepend_438; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5332 = _out_T_5331; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_439 = _out_T_5332; // @[RegisterRouter.scala:87:24] wire out_rimask_521 = \|_out_rimask_T_521; // @[RegisterRouter.scala:87:24] wire out_wimask_521 = &_out_wimask_T_521; // @[RegisterRouter.scala:87:24] wire out_romask_521 = \|_out_romask_T_521; // @[RegisterRouter.scala:87:24] wire out_womask_521 = &_out_womask_T_521; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_521 = out_rivalid_1_375 & out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5334 = out_f_rivalid_521; // @[RegisterRouter.scala:87:24] wire out_f_roready_521 = out_roready_1_375 & out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5335 = out_f_roready_521; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_521 = out_wivalid_1_375 & out_wimask_521; // @[RegisterRouter.scala:87:24] wire out_f_woready_521 = out_woready_1_375 & out_womask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5336 = ~out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5337 = ~out_wimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5338 = ~out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5339 = ~out_womask_521; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_439 = {hi_558, flags_0_go, _out_prepend_T_439}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5340 = out_prepend_439; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5341 = _out_T_5340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_440 = _out_T_5341; // @[RegisterRouter.scala:87:24] wire out_rimask_522 = \|_out_rimask_T_522; // @[RegisterRouter.scala:87:24] wire out_wimask_522 = &_out_wimask_T_522; // @[RegisterRouter.scala:87:24] wire out_romask_522 = \|_out_romask_T_522; // @[RegisterRouter.scala:87:24] wire out_womask_522 = &_out_womask_T_522; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_522 = out_rivalid_1_376 & out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5343 = out_f_rivalid_522; // @[RegisterRouter.scala:87:24] wire out_f_roready_522 = out_roready_1_376 & out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5344 = out_f_roready_522; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_522 = out_wivalid_1_376 & out_wimask_522; // @[RegisterRouter.scala:87:24] wire out_f_woready_522 = out_woready_1_376 & out_womask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5345 = ~out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5346 = ~out_wimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5347 = ~out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5348 = ~out_womask_522; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_440 = {hi_559, flags_0_go, _out_prepend_T_440}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5349 = out_prepend_440; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5350 = _out_T_5349; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_441 = _out_T_5350; // @[RegisterRouter.scala:87:24] wire out_rimask_523 = \|_out_rimask_T_523; // @[RegisterRouter.scala:87:24] wire out_wimask_523 = &_out_wimask_T_523; // @[RegisterRouter.scala:87:24] wire out_romask_523 = \|_out_romask_T_523; // @[RegisterRouter.scala:87:24] wire out_womask_523 = &_out_womask_T_523; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_523 = out_rivalid_1_377 & out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5352 = out_f_rivalid_523; // @[RegisterRouter.scala:87:24] wire out_f_roready_523 = out_roready_1_377 & out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5353 = out_f_roready_523; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_523 = out_wivalid_1_377 & out_wimask_523; // @[RegisterRouter.scala:87:24] wire out_f_woready_523 = out_woready_1_377 & out_womask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5354 = ~out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5355 = ~out_wimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5356 = ~out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5357 = ~out_womask_523; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_441 = {hi_560, flags_0_go, _out_prepend_T_441}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5358 = out_prepend_441; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5359 = _out_T_5358; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_197 = _out_T_5359; // @[MuxLiteral.scala:49:48] wire out_rimask_524 = \|_out_rimask_T_524; // @[RegisterRouter.scala:87:24] wire out_wimask_524 = &_out_wimask_T_524; // @[RegisterRouter.scala:87:24] wire out_romask_524 = \|_out_romask_T_524; // @[RegisterRouter.scala:87:24] wire out_womask_524 = &_out_womask_T_524; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_524 = out_rivalid_1_378 & out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5361 = out_f_rivalid_524; // @[RegisterRouter.scala:87:24] wire out_f_roready_524 = out_roready_1_378 & out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5362 = out_f_roready_524; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_524 = out_wivalid_1_378 & out_wimask_524; // @[RegisterRouter.scala:87:24] wire out_f_woready_524 = out_woready_1_378 & out_womask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5363 = ~out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5364 = ~out_wimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5365 = ~out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5366 = ~out_womask_524; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5368 = _out_T_5367; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_442 = _out_T_5368; // @[RegisterRouter.scala:87:24] wire out_rimask_525 = \|_out_rimask_T_525; // @[RegisterRouter.scala:87:24] wire out_wimask_525 = &_out_wimask_T_525; // @[RegisterRouter.scala:87:24] wire out_romask_525 = \|_out_romask_T_525; // @[RegisterRouter.scala:87:24] wire out_womask_525 = &_out_womask_T_525; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_525 = out_rivalid_1_379 & out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5370 = out_f_rivalid_525; // @[RegisterRouter.scala:87:24] wire out_f_roready_525 = out_roready_1_379 & out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5371 = out_f_roready_525; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_525 = out_wivalid_1_379 & out_wimask_525; // @[RegisterRouter.scala:87:24] wire out_f_woready_525 = out_woready_1_379 & out_womask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5372 = ~out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5373 = ~out_wimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5374 = ~out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5375 = ~out_womask_525; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_442 = {hi_770, flags_0_go, _out_prepend_T_442}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5376 = out_prepend_442; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5377 = _out_T_5376; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_443 = _out_T_5377; // @[RegisterRouter.scala:87:24] wire out_rimask_526 = \|_out_rimask_T_526; // @[RegisterRouter.scala:87:24] wire out_wimask_526 = &_out_wimask_T_526; // @[RegisterRouter.scala:87:24] wire out_romask_526 = \|_out_romask_T_526; // @[RegisterRouter.scala:87:24] wire out_womask_526 = &_out_womask_T_526; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_526 = out_rivalid_1_380 & out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5379 = out_f_rivalid_526; // @[RegisterRouter.scala:87:24] wire out_f_roready_526 = out_roready_1_380 & out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5380 = out_f_roready_526; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_526 = out_wivalid_1_380 & out_wimask_526; // @[RegisterRouter.scala:87:24] wire out_f_woready_526 = out_woready_1_380 & out_womask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5381 = ~out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5382 = ~out_wimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5383 = ~out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5384 = ~out_womask_526; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_443 = {hi_771, flags_0_go, _out_prepend_T_443}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5385 = out_prepend_443; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5386 = _out_T_5385; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_444 = _out_T_5386; // @[RegisterRouter.scala:87:24] wire out_rimask_527 = \|_out_rimask_T_527; // @[RegisterRouter.scala:87:24] wire out_wimask_527 = &_out_wimask_T_527; // @[RegisterRouter.scala:87:24] wire out_romask_527 = \|_out_romask_T_527; // @[RegisterRouter.scala:87:24] wire out_womask_527 = &_out_womask_T_527; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_527 = out_rivalid_1_381 & out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5388 = out_f_rivalid_527; // @[RegisterRouter.scala:87:24] wire out_f_roready_527 = out_roready_1_381 & out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5389 = out_f_roready_527; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_527 = out_wivalid_1_381 & out_wimask_527; // @[RegisterRouter.scala:87:24] wire out_f_woready_527 = out_woready_1_381 & out_womask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5390 = ~out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5391 = ~out_wimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5392 = ~out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5393 = ~out_womask_527; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_444 = {hi_772, flags_0_go, _out_prepend_T_444}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5394 = out_prepend_444; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5395 = _out_T_5394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_445 = _out_T_5395; // @[RegisterRouter.scala:87:24] wire out_rimask_528 = \|_out_rimask_T_528; // @[RegisterRouter.scala:87:24] wire out_wimask_528 = &_out_wimask_T_528; // @[RegisterRouter.scala:87:24] wire out_romask_528 = \|_out_romask_T_528; // @[RegisterRouter.scala:87:24] wire out_womask_528 = &_out_womask_T_528; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_528 = out_rivalid_1_382 & out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5397 = out_f_rivalid_528; // @[RegisterRouter.scala:87:24] wire out_f_roready_528 = out_roready_1_382 & out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5398 = out_f_roready_528; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_528 = out_wivalid_1_382 & out_wimask_528; // @[RegisterRouter.scala:87:24] wire out_f_woready_528 = out_woready_1_382 & out_womask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5399 = ~out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5400 = ~out_wimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5401 = ~out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5402 = ~out_womask_528; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_445 = {hi_773, flags_0_go, _out_prepend_T_445}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5403 = out_prepend_445; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5404 = _out_T_5403; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_446 = _out_T_5404; // @[RegisterRouter.scala:87:24] wire out_rimask_529 = \|_out_rimask_T_529; // @[RegisterRouter.scala:87:24] wire out_wimask_529 = &_out_wimask_T_529; // @[RegisterRouter.scala:87:24] wire out_romask_529 = \|_out_romask_T_529; // @[RegisterRouter.scala:87:24] wire out_womask_529 = &_out_womask_T_529; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_529 = out_rivalid_1_383 & out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5406 = out_f_rivalid_529; // @[RegisterRouter.scala:87:24] wire out_f_roready_529 = out_roready_1_383 & out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5407 = out_f_roready_529; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_529 = out_wivalid_1_383 & out_wimask_529; // @[RegisterRouter.scala:87:24] wire out_f_woready_529 = out_woready_1_383 & out_womask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5408 = ~out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5409 = ~out_wimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5410 = ~out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5411 = ~out_womask_529; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_446 = {hi_774, flags_0_go, _out_prepend_T_446}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5412 = out_prepend_446; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5413 = _out_T_5412; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_447 = _out_T_5413; // @[RegisterRouter.scala:87:24] wire out_rimask_530 = \|_out_rimask_T_530; // @[RegisterRouter.scala:87:24] wire out_wimask_530 = &_out_wimask_T_530; // @[RegisterRouter.scala:87:24] wire out_romask_530 = \|_out_romask_T_530; // @[RegisterRouter.scala:87:24] wire out_womask_530 = &_out_womask_T_530; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_530 = out_rivalid_1_384 & out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5415 = out_f_rivalid_530; // @[RegisterRouter.scala:87:24] wire out_f_roready_530 = out_roready_1_384 & out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5416 = out_f_roready_530; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_530 = out_wivalid_1_384 & out_wimask_530; // @[RegisterRouter.scala:87:24] wire out_f_woready_530 = out_woready_1_384 & out_womask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5417 = ~out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5418 = ~out_wimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5419 = ~out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5420 = ~out_womask_530; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_447 = {hi_775, flags_0_go, _out_prepend_T_447}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5421 = out_prepend_447; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5422 = _out_T_5421; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_448 = _out_T_5422; // @[RegisterRouter.scala:87:24] wire out_rimask_531 = \|_out_rimask_T_531; // @[RegisterRouter.scala:87:24] wire out_wimask_531 = &_out_wimask_T_531; // @[RegisterRouter.scala:87:24] wire out_romask_531 = \|_out_romask_T_531; // @[RegisterRouter.scala:87:24] wire out_womask_531 = &_out_womask_T_531; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_531 = out_rivalid_1_385 & out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5424 = out_f_rivalid_531; // @[RegisterRouter.scala:87:24] wire out_f_roready_531 = out_roready_1_385 & out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5425 = out_f_roready_531; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_531 = out_wivalid_1_385 & out_wimask_531; // @[RegisterRouter.scala:87:24] wire out_f_woready_531 = out_woready_1_385 & out_womask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5426 = ~out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5427 = ~out_wimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5428 = ~out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5429 = ~out_womask_531; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_448 = {hi_776, flags_0_go, _out_prepend_T_448}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5430 = out_prepend_448; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5431 = _out_T_5430; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_224 = _out_T_5431; // @[MuxLiteral.scala:49:48] wire out_rimask_532 = \|_out_rimask_T_532; // @[RegisterRouter.scala:87:24] wire out_wimask_532 = &_out_wimask_T_532; // @[RegisterRouter.scala:87:24] wire out_romask_532 = \|_out_romask_T_532; // @[RegisterRouter.scala:87:24] wire out_womask_532 = &_out_womask_T_532; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_532 = out_rivalid_1_386 & out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5433 = out_f_rivalid_532; // @[RegisterRouter.scala:87:24] wire out_f_roready_532 = out_roready_1_386 & out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5434 = out_f_roready_532; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_532 = out_wivalid_1_386 & out_wimask_532; // @[RegisterRouter.scala:87:24] wire out_f_woready_532 = out_woready_1_386 & out_womask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5435 = ~out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5436 = ~out_wimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5437 = ~out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5438 = ~out_womask_532; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5440 = _out_T_5439; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_449 = _out_T_5440; // @[RegisterRouter.scala:87:24] wire out_rimask_533 = \|_out_rimask_T_533; // @[RegisterRouter.scala:87:24] wire out_wimask_533 = &_out_wimask_T_533; // @[RegisterRouter.scala:87:24] wire out_romask_533 = \|_out_romask_T_533; // @[RegisterRouter.scala:87:24] wire out_womask_533 = &_out_womask_T_533; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_533 = out_rivalid_1_387 & out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5442 = out_f_rivalid_533; // @[RegisterRouter.scala:87:24] wire out_f_roready_533 = out_roready_1_387 & out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5443 = out_f_roready_533; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_533 = out_wivalid_1_387 & out_wimask_533; // @[RegisterRouter.scala:87:24] wire out_f_woready_533 = out_woready_1_387 & out_womask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5444 = ~out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5445 = ~out_wimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5446 = ~out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5447 = ~out_womask_533; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_449 = {hi_226, flags_0_go, _out_prepend_T_449}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5448 = out_prepend_449; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5449 = _out_T_5448; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_450 = _out_T_5449; // @[RegisterRouter.scala:87:24] wire out_rimask_534 = \|_out_rimask_T_534; // @[RegisterRouter.scala:87:24] wire out_wimask_534 = &_out_wimask_T_534; // @[RegisterRouter.scala:87:24] wire out_romask_534 = \|_out_romask_T_534; // @[RegisterRouter.scala:87:24] wire out_womask_534 = &_out_womask_T_534; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_534 = out_rivalid_1_388 & out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5451 = out_f_rivalid_534; // @[RegisterRouter.scala:87:24] wire out_f_roready_534 = out_roready_1_388 & out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5452 = out_f_roready_534; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_534 = out_wivalid_1_388 & out_wimask_534; // @[RegisterRouter.scala:87:24] wire out_f_woready_534 = out_woready_1_388 & out_womask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5453 = ~out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5454 = ~out_wimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5455 = ~out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5456 = ~out_womask_534; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_450 = {hi_227, flags_0_go, _out_prepend_T_450}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5457 = out_prepend_450; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5458 = _out_T_5457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_451 = _out_T_5458; // @[RegisterRouter.scala:87:24] wire out_rimask_535 = \|_out_rimask_T_535; // @[RegisterRouter.scala:87:24] wire out_wimask_535 = &_out_wimask_T_535; // @[RegisterRouter.scala:87:24] wire out_romask_535 = \|_out_romask_T_535; // @[RegisterRouter.scala:87:24] wire out_womask_535 = &_out_womask_T_535; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_535 = out_rivalid_1_389 & out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5460 = out_f_rivalid_535; // @[RegisterRouter.scala:87:24] wire out_f_roready_535 = out_roready_1_389 & out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5461 = out_f_roready_535; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_535 = out_wivalid_1_389 & out_wimask_535; // @[RegisterRouter.scala:87:24] wire out_f_woready_535 = out_woready_1_389 & out_womask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5462 = ~out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5463 = ~out_wimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5464 = ~out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5465 = ~out_womask_535; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_451 = {hi_228, flags_0_go, _out_prepend_T_451}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5466 = out_prepend_451; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5467 = _out_T_5466; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_452 = _out_T_5467; // @[RegisterRouter.scala:87:24] wire out_rimask_536 = \|_out_rimask_T_536; // @[RegisterRouter.scala:87:24] wire out_wimask_536 = &_out_wimask_T_536; // @[RegisterRouter.scala:87:24] wire out_romask_536 = \|_out_romask_T_536; // @[RegisterRouter.scala:87:24] wire out_womask_536 = &_out_womask_T_536; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_536 = out_rivalid_1_390 & out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5469 = out_f_rivalid_536; // @[RegisterRouter.scala:87:24] wire out_f_roready_536 = out_roready_1_390 & out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5470 = out_f_roready_536; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_536 = out_wivalid_1_390 & out_wimask_536; // @[RegisterRouter.scala:87:24] wire out_f_woready_536 = out_woready_1_390 & out_womask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5471 = ~out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5472 = ~out_wimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5473 = ~out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5474 = ~out_womask_536; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_452 = {hi_229, flags_0_go, _out_prepend_T_452}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5475 = out_prepend_452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5476 = _out_T_5475; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_453 = _out_T_5476; // @[RegisterRouter.scala:87:24] wire out_rimask_537 = \|_out_rimask_T_537; // @[RegisterRouter.scala:87:24] wire out_wimask_537 = &_out_wimask_T_537; // @[RegisterRouter.scala:87:24] wire out_romask_537 = \|_out_romask_T_537; // @[RegisterRouter.scala:87:24] wire out_womask_537 = &_out_womask_T_537; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_537 = out_rivalid_1_391 & out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5478 = out_f_rivalid_537; // @[RegisterRouter.scala:87:24] wire out_f_roready_537 = out_roready_1_391 & out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5479 = out_f_roready_537; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_537 = out_wivalid_1_391 & out_wimask_537; // @[RegisterRouter.scala:87:24] wire out_f_woready_537 = out_woready_1_391 & out_womask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5480 = ~out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5481 = ~out_wimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5482 = ~out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5483 = ~out_womask_537; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_453 = {hi_230, flags_0_go, _out_prepend_T_453}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5484 = out_prepend_453; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5485 = _out_T_5484; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_454 = _out_T_5485; // @[RegisterRouter.scala:87:24] wire out_rimask_538 = \|_out_rimask_T_538; // @[RegisterRouter.scala:87:24] wire out_wimask_538 = &_out_wimask_T_538; // @[RegisterRouter.scala:87:24] wire out_romask_538 = \|_out_romask_T_538; // @[RegisterRouter.scala:87:24] wire out_womask_538 = &_out_womask_T_538; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_538 = out_rivalid_1_392 & out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5487 = out_f_rivalid_538; // @[RegisterRouter.scala:87:24] wire out_f_roready_538 = out_roready_1_392 & out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5488 = out_f_roready_538; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_538 = out_wivalid_1_392 & out_wimask_538; // @[RegisterRouter.scala:87:24] wire out_f_woready_538 = out_woready_1_392 & out_womask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5489 = ~out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5490 = ~out_wimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5491 = ~out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5492 = ~out_womask_538; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_454 = {hi_231, flags_0_go, _out_prepend_T_454}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5493 = out_prepend_454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5494 = _out_T_5493; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_455 = _out_T_5494; // @[RegisterRouter.scala:87:24] wire out_rimask_539 = \|_out_rimask_T_539; // @[RegisterRouter.scala:87:24] wire out_wimask_539 = &_out_wimask_T_539; // @[RegisterRouter.scala:87:24] wire out_romask_539 = \|_out_romask_T_539; // @[RegisterRouter.scala:87:24] wire out_womask_539 = &_out_womask_T_539; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_539 = out_rivalid_1_393 & out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5496 = out_f_rivalid_539; // @[RegisterRouter.scala:87:24] wire out_f_roready_539 = out_roready_1_393 & out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5497 = out_f_roready_539; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_539 = out_wivalid_1_393 & out_wimask_539; // @[RegisterRouter.scala:87:24] wire out_f_woready_539 = out_woready_1_393 & out_womask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5498 = ~out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5499 = ~out_wimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5500 = ~out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5501 = ~out_womask_539; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_455 = {hi_232, flags_0_go, _out_prepend_T_455}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5502 = out_prepend_455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5503 = _out_T_5502; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_156 = _out_T_5503; // @[MuxLiteral.scala:49:48] wire out_rimask_540 = \|_out_rimask_T_540; // @[RegisterRouter.scala:87:24] wire out_wimask_540 = &_out_wimask_T_540; // @[RegisterRouter.scala:87:24] wire out_romask_540 = \|_out_romask_T_540; // @[RegisterRouter.scala:87:24] wire out_womask_540 = &_out_womask_T_540; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_540 = out_rivalid_1_394 & out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5505 = out_f_rivalid_540; // @[RegisterRouter.scala:87:24] wire out_f_roready_540 = out_roready_1_394 & out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5506 = out_f_roready_540; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_540 = out_wivalid_1_394 & out_wimask_540; // @[RegisterRouter.scala:87:24] wire out_f_woready_540 = out_woready_1_394 & out_womask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5507 = ~out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5508 = ~out_wimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5509 = ~out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5510 = ~out_womask_540; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5512 = _out_T_5511; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_456 = _out_T_5512; // @[RegisterRouter.scala:87:24] wire out_rimask_541 = \|_out_rimask_T_541; // @[RegisterRouter.scala:87:24] wire out_wimask_541 = &_out_wimask_T_541; // @[RegisterRouter.scala:87:24] wire out_romask_541 = \|_out_romask_T_541; // @[RegisterRouter.scala:87:24] wire out_womask_541 = &_out_womask_T_541; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_541 = out_rivalid_1_395 & out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5514 = out_f_rivalid_541; // @[RegisterRouter.scala:87:24] wire out_f_roready_541 = out_roready_1_395 & out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5515 = out_f_roready_541; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_541 = out_wivalid_1_395 & out_wimask_541; // @[RegisterRouter.scala:87:24] wire out_f_woready_541 = out_woready_1_395 & out_womask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5516 = ~out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5517 = ~out_wimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5518 = ~out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5519 = ~out_womask_541; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_456 = {hi_482, flags_0_go, _out_prepend_T_456}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5520 = out_prepend_456; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5521 = _out_T_5520; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_457 = _out_T_5521; // @[RegisterRouter.scala:87:24] wire out_rimask_542 = \|_out_rimask_T_542; // @[RegisterRouter.scala:87:24] wire out_wimask_542 = &_out_wimask_T_542; // @[RegisterRouter.scala:87:24] wire out_romask_542 = \|_out_romask_T_542; // @[RegisterRouter.scala:87:24] wire out_womask_542 = &_out_womask_T_542; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_542 = out_rivalid_1_396 & out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5523 = out_f_rivalid_542; // @[RegisterRouter.scala:87:24] wire out_f_roready_542 = out_roready_1_396 & out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5524 = out_f_roready_542; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_542 = out_wivalid_1_396 & out_wimask_542; // @[RegisterRouter.scala:87:24] wire out_f_woready_542 = out_woready_1_396 & out_womask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5525 = ~out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5526 = ~out_wimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5527 = ~out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5528 = ~out_womask_542; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_457 = {hi_483, flags_0_go, _out_prepend_T_457}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5529 = out_prepend_457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5530 = _out_T_5529; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_458 = _out_T_5530; // @[RegisterRouter.scala:87:24] wire out_rimask_543 = \|_out_rimask_T_543; // @[RegisterRouter.scala:87:24] wire out_wimask_543 = &_out_wimask_T_543; // @[RegisterRouter.scala:87:24] wire out_romask_543 = \|_out_romask_T_543; // @[RegisterRouter.scala:87:24] wire out_womask_543 = &_out_womask_T_543; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_543 = out_rivalid_1_397 & out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5532 = out_f_rivalid_543; // @[RegisterRouter.scala:87:24] wire out_f_roready_543 = out_roready_1_397 & out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5533 = out_f_roready_543; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_543 = out_wivalid_1_397 & out_wimask_543; // @[RegisterRouter.scala:87:24] wire out_f_woready_543 = out_woready_1_397 & out_womask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5534 = ~out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5535 = ~out_wimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5536 = ~out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5537 = ~out_womask_543; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_458 = {hi_484, flags_0_go, _out_prepend_T_458}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5538 = out_prepend_458; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5539 = _out_T_5538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_459 = _out_T_5539; // @[RegisterRouter.scala:87:24] wire out_rimask_544 = \|_out_rimask_T_544; // @[RegisterRouter.scala:87:24] wire out_wimask_544 = &_out_wimask_T_544; // @[RegisterRouter.scala:87:24] wire out_romask_544 = \|_out_romask_T_544; // @[RegisterRouter.scala:87:24] wire out_womask_544 = &_out_womask_T_544; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_544 = out_rivalid_1_398 & out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5541 = out_f_rivalid_544; // @[RegisterRouter.scala:87:24] wire out_f_roready_544 = out_roready_1_398 & out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5542 = out_f_roready_544; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_544 = out_wivalid_1_398 & out_wimask_544; // @[RegisterRouter.scala:87:24] wire out_f_woready_544 = out_woready_1_398 & out_womask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5543 = ~out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5544 = ~out_wimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5545 = ~out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5546 = ~out_womask_544; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_459 = {hi_485, flags_0_go, _out_prepend_T_459}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5547 = out_prepend_459; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5548 = _out_T_5547; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_460 = _out_T_5548; // @[RegisterRouter.scala:87:24] wire out_rimask_545 = \|_out_rimask_T_545; // @[RegisterRouter.scala:87:24] wire out_wimask_545 = &_out_wimask_T_545; // @[RegisterRouter.scala:87:24] wire out_romask_545 = \|_out_romask_T_545; // @[RegisterRouter.scala:87:24] wire out_womask_545 = &_out_womask_T_545; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_545 = out_rivalid_1_399 & out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5550 = out_f_rivalid_545; // @[RegisterRouter.scala:87:24] wire out_f_roready_545 = out_roready_1_399 & out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5551 = out_f_roready_545; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_545 = out_wivalid_1_399 & out_wimask_545; // @[RegisterRouter.scala:87:24] wire out_f_woready_545 = out_woready_1_399 & out_womask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5552 = ~out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5553 = ~out_wimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5554 = ~out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5555 = ~out_womask_545; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_460 = {hi_486, flags_0_go, _out_prepend_T_460}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5556 = out_prepend_460; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5557 = _out_T_5556; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_461 = _out_T_5557; // @[RegisterRouter.scala:87:24] wire out_rimask_546 = \|_out_rimask_T_546; // @[RegisterRouter.scala:87:24] wire out_wimask_546 = &_out_wimask_T_546; // @[RegisterRouter.scala:87:24] wire out_romask_546 = \|_out_romask_T_546; // @[RegisterRouter.scala:87:24] wire out_womask_546 = &_out_womask_T_546; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_546 = out_rivalid_1_400 & out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5559 = out_f_rivalid_546; // @[RegisterRouter.scala:87:24] wire out_f_roready_546 = out_roready_1_400 & out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5560 = out_f_roready_546; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_546 = out_wivalid_1_400 & out_wimask_546; // @[RegisterRouter.scala:87:24] wire out_f_woready_546 = out_woready_1_400 & out_womask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5561 = ~out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5562 = ~out_wimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5563 = ~out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5564 = ~out_womask_546; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_461 = {hi_487, flags_0_go, _out_prepend_T_461}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5565 = out_prepend_461; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5566 = _out_T_5565; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_462 = _out_T_5566; // @[RegisterRouter.scala:87:24] wire out_rimask_547 = \|_out_rimask_T_547; // @[RegisterRouter.scala:87:24] wire out_wimask_547 = &_out_wimask_T_547; // @[RegisterRouter.scala:87:24] wire out_romask_547 = \|_out_romask_T_547; // @[RegisterRouter.scala:87:24] wire out_womask_547 = &_out_womask_T_547; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_547 = out_rivalid_1_401 & out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5568 = out_f_rivalid_547; // @[RegisterRouter.scala:87:24] wire out_f_roready_547 = out_roready_1_401 & out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5569 = out_f_roready_547; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_547 = out_wivalid_1_401 & out_wimask_547; // @[RegisterRouter.scala:87:24] wire out_f_woready_547 = out_woready_1_401 & out_womask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5570 = ~out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5571 = ~out_wimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5572 = ~out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5573 = ~out_womask_547; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_462 = {hi_488, flags_0_go, _out_prepend_T_462}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5574 = out_prepend_462; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5575 = _out_T_5574; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_188 = _out_T_5575; // @[MuxLiteral.scala:49:48] wire out_rimask_548 = \|_out_rimask_T_548; // @[RegisterRouter.scala:87:24] wire out_wimask_548 = &_out_wimask_T_548; // @[RegisterRouter.scala:87:24] wire out_romask_548 = \|_out_romask_T_548; // @[RegisterRouter.scala:87:24] wire out_womask_548 = &_out_womask_T_548; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_548 = out_rivalid_1_402 & out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5577 = out_f_rivalid_548; // @[RegisterRouter.scala:87:24] wire out_f_roready_548 = out_roready_1_402 & out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5578 = out_f_roready_548; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_548 = out_wivalid_1_402 & out_wimask_548; // @[RegisterRouter.scala:87:24] wire out_f_woready_548 = out_woready_1_402 & out_womask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5579 = ~out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5580 = ~out_wimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5581 = ~out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5582 = ~out_womask_548; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5584 = _out_T_5583; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_463 = _out_T_5584; // @[RegisterRouter.scala:87:24] wire out_rimask_549 = \|_out_rimask_T_549; // @[RegisterRouter.scala:87:24] wire out_wimask_549 = &_out_wimask_T_549; // @[RegisterRouter.scala:87:24] wire out_romask_549 = \|_out_romask_T_549; // @[RegisterRouter.scala:87:24] wire out_womask_549 = &_out_womask_T_549; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_549 = out_rivalid_1_403 & out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5586 = out_f_rivalid_549; // @[RegisterRouter.scala:87:24] wire out_f_roready_549 = out_roready_1_403 & out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5587 = out_f_roready_549; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_549 = out_wivalid_1_403 & out_wimask_549; // @[RegisterRouter.scala:87:24] wire out_f_woready_549 = out_woready_1_403 & out_womask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5588 = ~out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5589 = ~out_wimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5590 = ~out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5591 = ~out_womask_549; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_463 = {hi_330, flags_0_go, _out_prepend_T_463}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5592 = out_prepend_463; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5593 = _out_T_5592; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_464 = _out_T_5593; // @[RegisterRouter.scala:87:24] wire out_rimask_550 = \|_out_rimask_T_550; // @[RegisterRouter.scala:87:24] wire out_wimask_550 = &_out_wimask_T_550; // @[RegisterRouter.scala:87:24] wire out_romask_550 = \|_out_romask_T_550; // @[RegisterRouter.scala:87:24] wire out_womask_550 = &_out_womask_T_550; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_550 = out_rivalid_1_404 & out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5595 = out_f_rivalid_550; // @[RegisterRouter.scala:87:24] wire out_f_roready_550 = out_roready_1_404 & out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5596 = out_f_roready_550; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_550 = out_wivalid_1_404 & out_wimask_550; // @[RegisterRouter.scala:87:24] wire out_f_woready_550 = out_woready_1_404 & out_womask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5597 = ~out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5598 = ~out_wimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5599 = ~out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5600 = ~out_womask_550; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_464 = {hi_331, flags_0_go, _out_prepend_T_464}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5601 = out_prepend_464; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5602 = _out_T_5601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_465 = _out_T_5602; // @[RegisterRouter.scala:87:24] wire out_rimask_551 = \|_out_rimask_T_551; // @[RegisterRouter.scala:87:24] wire out_wimask_551 = &_out_wimask_T_551; // @[RegisterRouter.scala:87:24] wire out_romask_551 = \|_out_romask_T_551; // @[RegisterRouter.scala:87:24] wire out_womask_551 = &_out_womask_T_551; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_551 = out_rivalid_1_405 & out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5604 = out_f_rivalid_551; // @[RegisterRouter.scala:87:24] wire out_f_roready_551 = out_roready_1_405 & out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5605 = out_f_roready_551; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_551 = out_wivalid_1_405 & out_wimask_551; // @[RegisterRouter.scala:87:24] wire out_f_woready_551 = out_woready_1_405 & out_womask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5606 = ~out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5607 = ~out_wimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5608 = ~out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5609 = ~out_womask_551; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_465 = {hi_332, flags_0_go, _out_prepend_T_465}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5610 = out_prepend_465; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5611 = _out_T_5610; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_466 = _out_T_5611; // @[RegisterRouter.scala:87:24] wire out_rimask_552 = \|_out_rimask_T_552; // @[RegisterRouter.scala:87:24] wire out_wimask_552 = &_out_wimask_T_552; // @[RegisterRouter.scala:87:24] wire out_romask_552 = \|_out_romask_T_552; // @[RegisterRouter.scala:87:24] wire out_womask_552 = &_out_womask_T_552; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_552 = out_rivalid_1_406 & out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5613 = out_f_rivalid_552; // @[RegisterRouter.scala:87:24] wire out_f_roready_552 = out_roready_1_406 & out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5614 = out_f_roready_552; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_552 = out_wivalid_1_406 & out_wimask_552; // @[RegisterRouter.scala:87:24] wire out_f_woready_552 = out_woready_1_406 & out_womask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5615 = ~out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5616 = ~out_wimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5617 = ~out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5618 = ~out_womask_552; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_466 = {hi_333, flags_0_go, _out_prepend_T_466}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5619 = out_prepend_466; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5620 = _out_T_5619; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_467 = _out_T_5620; // @[RegisterRouter.scala:87:24] wire out_rimask_553 = \|_out_rimask_T_553; // @[RegisterRouter.scala:87:24] wire out_wimask_553 = &_out_wimask_T_553; // @[RegisterRouter.scala:87:24] wire out_romask_553 = \|_out_romask_T_553; // @[RegisterRouter.scala:87:24] wire out_womask_553 = &_out_womask_T_553; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_553 = out_rivalid_1_407 & out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5622 = out_f_rivalid_553; // @[RegisterRouter.scala:87:24] wire out_f_roready_553 = out_roready_1_407 & out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5623 = out_f_roready_553; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_553 = out_wivalid_1_407 & out_wimask_553; // @[RegisterRouter.scala:87:24] wire out_f_woready_553 = out_woready_1_407 & out_womask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5624 = ~out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5625 = ~out_wimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5626 = ~out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5627 = ~out_womask_553; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_467 = {hi_334, flags_0_go, _out_prepend_T_467}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5628 = out_prepend_467; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5629 = _out_T_5628; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_468 = _out_T_5629; // @[RegisterRouter.scala:87:24] wire out_rimask_554 = \|_out_rimask_T_554; // @[RegisterRouter.scala:87:24] wire out_wimask_554 = &_out_wimask_T_554; // @[RegisterRouter.scala:87:24] wire out_romask_554 = \|_out_romask_T_554; // @[RegisterRouter.scala:87:24] wire out_womask_554 = &_out_womask_T_554; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_554 = out_rivalid_1_408 & out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5631 = out_f_rivalid_554; // @[RegisterRouter.scala:87:24] wire out_f_roready_554 = out_roready_1_408 & out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5632 = out_f_roready_554; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_554 = out_wivalid_1_408 & out_wimask_554; // @[RegisterRouter.scala:87:24] wire out_f_woready_554 = out_woready_1_408 & out_womask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5633 = ~out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5634 = ~out_wimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5635 = ~out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5636 = ~out_womask_554; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_468 = {hi_335, flags_0_go, _out_prepend_T_468}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5637 = out_prepend_468; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5638 = _out_T_5637; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_469 = _out_T_5638; // @[RegisterRouter.scala:87:24] wire out_rimask_555 = \|_out_rimask_T_555; // @[RegisterRouter.scala:87:24] wire out_wimask_555 = &_out_wimask_T_555; // @[RegisterRouter.scala:87:24] wire out_romask_555 = \|_out_romask_T_555; // @[RegisterRouter.scala:87:24] wire out_womask_555 = &_out_womask_T_555; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_555 = out_rivalid_1_409 & out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5640 = out_f_rivalid_555; // @[RegisterRouter.scala:87:24] wire out_f_roready_555 = out_roready_1_409 & out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5641 = out_f_roready_555; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_555 = out_wivalid_1_409 & out_wimask_555; // @[RegisterRouter.scala:87:24] wire out_f_woready_555 = out_woready_1_409 & out_womask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5642 = ~out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5643 = ~out_wimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5644 = ~out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5645 = ~out_womask_555; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_469 = {hi_336, flags_0_go, _out_prepend_T_469}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5646 = out_prepend_469; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5647 = _out_T_5646; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_169 = _out_T_5647; // @[MuxLiteral.scala:49:48] wire out_rimask_556 = \|_out_rimask_T_556; // @[RegisterRouter.scala:87:24] wire out_wimask_556 = &_out_wimask_T_556; // @[RegisterRouter.scala:87:24] wire out_romask_556 = \|_out_romask_T_556; // @[RegisterRouter.scala:87:24] wire out_womask_556 = &_out_womask_T_556; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_556 = out_rivalid_1_410 & out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5649 = out_f_rivalid_556; // @[RegisterRouter.scala:87:24] wire out_f_roready_556 = out_roready_1_410 & out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5650 = out_f_roready_556; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_556 = out_wivalid_1_410 & out_wimask_556; // @[RegisterRouter.scala:87:24] wire out_f_woready_556 = out_woready_1_410 & out_womask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5651 = ~out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5652 = ~out_wimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5653 = ~out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5654 = ~out_womask_556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5656 = _out_T_5655; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_470 = _out_T_5656; // @[RegisterRouter.scala:87:24] wire out_rimask_557 = \|_out_rimask_T_557; // @[RegisterRouter.scala:87:24] wire out_wimask_557 = &_out_wimask_T_557; // @[RegisterRouter.scala:87:24] wire out_romask_557 = \|_out_romask_T_557; // @[RegisterRouter.scala:87:24] wire out_womask_557 = &_out_womask_T_557; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_557 = out_rivalid_1_411 & out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5658 = out_f_rivalid_557; // @[RegisterRouter.scala:87:24] wire out_f_roready_557 = out_roready_1_411 & out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5659 = out_f_roready_557; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_557 = out_wivalid_1_411 & out_wimask_557; // @[RegisterRouter.scala:87:24] wire out_f_woready_557 = out_woready_1_411 & out_womask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5660 = ~out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5661 = ~out_wimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5662 = ~out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5663 = ~out_womask_557; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_470 = {hi_106, flags_0_go, _out_prepend_T_470}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5664 = out_prepend_470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5665 = _out_T_5664; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_471 = _out_T_5665; // @[RegisterRouter.scala:87:24] wire out_rimask_558 = \|_out_rimask_T_558; // @[RegisterRouter.scala:87:24] wire out_wimask_558 = &_out_wimask_T_558; // @[RegisterRouter.scala:87:24] wire out_romask_558 = \|_out_romask_T_558; // @[RegisterRouter.scala:87:24] wire out_womask_558 = &_out_womask_T_558; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_558 = out_rivalid_1_412 & out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5667 = out_f_rivalid_558; // @[RegisterRouter.scala:87:24] wire out_f_roready_558 = out_roready_1_412 & out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5668 = out_f_roready_558; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_558 = out_wivalid_1_412 & out_wimask_558; // @[RegisterRouter.scala:87:24] wire out_f_woready_558 = out_woready_1_412 & out_womask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5669 = ~out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5670 = ~out_wimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5671 = ~out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5672 = ~out_womask_558; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_471 = {hi_107, flags_0_go, _out_prepend_T_471}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5673 = out_prepend_471; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5674 = _out_T_5673; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_472 = _out_T_5674; // @[RegisterRouter.scala:87:24] wire out_rimask_559 = \|_out_rimask_T_559; // @[RegisterRouter.scala:87:24] wire out_wimask_559 = &_out_wimask_T_559; // @[RegisterRouter.scala:87:24] wire out_romask_559 = \|_out_romask_T_559; // @[RegisterRouter.scala:87:24] wire out_womask_559 = &_out_womask_T_559; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_559 = out_rivalid_1_413 & out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5676 = out_f_rivalid_559; // @[RegisterRouter.scala:87:24] wire out_f_roready_559 = out_roready_1_413 & out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5677 = out_f_roready_559; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_559 = out_wivalid_1_413 & out_wimask_559; // @[RegisterRouter.scala:87:24] wire out_f_woready_559 = out_woready_1_413 & out_womask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5678 = ~out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5679 = ~out_wimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5680 = ~out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5681 = ~out_womask_559; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_472 = {hi_108, flags_0_go, _out_prepend_T_472}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5682 = out_prepend_472; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5683 = _out_T_5682; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_473 = _out_T_5683; // @[RegisterRouter.scala:87:24] wire out_rimask_560 = \|_out_rimask_T_560; // @[RegisterRouter.scala:87:24] wire out_wimask_560 = &_out_wimask_T_560; // @[RegisterRouter.scala:87:24] wire out_romask_560 = \|_out_romask_T_560; // @[RegisterRouter.scala:87:24] wire out_womask_560 = &_out_womask_T_560; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_560 = out_rivalid_1_414 & out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5685 = out_f_rivalid_560; // @[RegisterRouter.scala:87:24] wire out_f_roready_560 = out_roready_1_414 & out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5686 = out_f_roready_560; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_560 = out_wivalid_1_414 & out_wimask_560; // @[RegisterRouter.scala:87:24] wire out_f_woready_560 = out_woready_1_414 & out_womask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5687 = ~out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5688 = ~out_wimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5689 = ~out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5690 = ~out_womask_560; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_473 = {hi_109, flags_0_go, _out_prepend_T_473}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5691 = out_prepend_473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5692 = _out_T_5691; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_474 = _out_T_5692; // @[RegisterRouter.scala:87:24] wire out_rimask_561 = \|_out_rimask_T_561; // @[RegisterRouter.scala:87:24] wire out_wimask_561 = &_out_wimask_T_561; // @[RegisterRouter.scala:87:24] wire out_romask_561 = \|_out_romask_T_561; // @[RegisterRouter.scala:87:24] wire out_womask_561 = &_out_womask_T_561; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_561 = out_rivalid_1_415 & out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5694 = out_f_rivalid_561; // @[RegisterRouter.scala:87:24] wire out_f_roready_561 = out_roready_1_415 & out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5695 = out_f_roready_561; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_561 = out_wivalid_1_415 & out_wimask_561; // @[RegisterRouter.scala:87:24] wire out_f_woready_561 = out_woready_1_415 & out_womask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5696 = ~out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5697 = ~out_wimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5698 = ~out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5699 = ~out_womask_561; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_474 = {hi_110, flags_0_go, _out_prepend_T_474}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5700 = out_prepend_474; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5701 = _out_T_5700; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_475 = _out_T_5701; // @[RegisterRouter.scala:87:24] wire out_rimask_562 = \|_out_rimask_T_562; // @[RegisterRouter.scala:87:24] wire out_wimask_562 = &_out_wimask_T_562; // @[RegisterRouter.scala:87:24] wire out_romask_562 = \|_out_romask_T_562; // @[RegisterRouter.scala:87:24] wire out_womask_562 = &_out_womask_T_562; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_562 = out_rivalid_1_416 & out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5703 = out_f_rivalid_562; // @[RegisterRouter.scala:87:24] wire out_f_roready_562 = out_roready_1_416 & out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5704 = out_f_roready_562; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_562 = out_wivalid_1_416 & out_wimask_562; // @[RegisterRouter.scala:87:24] wire out_f_woready_562 = out_woready_1_416 & out_womask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5705 = ~out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5706 = ~out_wimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5707 = ~out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5708 = ~out_womask_562; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_475 = {hi_111, flags_0_go, _out_prepend_T_475}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5709 = out_prepend_475; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5710 = _out_T_5709; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_476 = _out_T_5710; // @[RegisterRouter.scala:87:24] wire out_rimask_563 = \|_out_rimask_T_563; // @[RegisterRouter.scala:87:24] wire out_wimask_563 = &_out_wimask_T_563; // @[RegisterRouter.scala:87:24] wire out_romask_563 = \|_out_romask_T_563; // @[RegisterRouter.scala:87:24] wire out_womask_563 = &_out_womask_T_563; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_563 = out_rivalid_1_417 & out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5712 = out_f_rivalid_563; // @[RegisterRouter.scala:87:24] wire out_f_roready_563 = out_roready_1_417 & out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5713 = out_f_roready_563; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_563 = out_wivalid_1_417 & out_wimask_563; // @[RegisterRouter.scala:87:24] wire out_f_woready_563 = out_woready_1_417 & out_womask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5714 = ~out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5715 = ~out_wimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5716 = ~out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5717 = ~out_womask_563; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_476 = {hi_112, flags_0_go, _out_prepend_T_476}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5718 = out_prepend_476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5719 = _out_T_5718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_141 = _out_T_5719; // @[MuxLiteral.scala:49:48] wire out_rimask_564 = \|_out_rimask_T_564; // @[RegisterRouter.scala:87:24] wire out_wimask_564 = &_out_wimask_T_564; // @[RegisterRouter.scala:87:24] wire out_romask_564 = \|_out_romask_T_564; // @[RegisterRouter.scala:87:24] wire out_womask_564 = &_out_womask_T_564; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_564 = out_rivalid_1_418 & out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5721 = out_f_rivalid_564; // @[RegisterRouter.scala:87:24] wire out_f_roready_564 = out_roready_1_418 & out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5722 = out_f_roready_564; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_564 = out_wivalid_1_418 & out_wimask_564; // @[RegisterRouter.scala:87:24] wire out_f_woready_564 = out_woready_1_418 & out_womask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5723 = ~out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5724 = ~out_wimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5725 = ~out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5726 = ~out_womask_564; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5728 = _out_T_5727; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_477 = _out_T_5728; // @[RegisterRouter.scala:87:24] wire out_rimask_565 = \|_out_rimask_T_565; // @[RegisterRouter.scala:87:24] wire out_wimask_565 = &_out_wimask_T_565; // @[RegisterRouter.scala:87:24] wire out_romask_565 = \|_out_romask_T_565; // @[RegisterRouter.scala:87:24] wire out_womask_565 = &_out_womask_T_565; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_565 = out_rivalid_1_419 & out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5730 = out_f_rivalid_565; // @[RegisterRouter.scala:87:24] wire out_f_roready_565 = out_roready_1_419 & out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5731 = out_f_roready_565; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_565 = out_wivalid_1_419 & out_wimask_565; // @[RegisterRouter.scala:87:24] wire out_f_woready_565 = out_woready_1_419 & out_womask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5732 = ~out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5733 = ~out_wimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5734 = ~out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5735 = ~out_womask_565; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_477 = {hi_778, flags_0_go, _out_prepend_T_477}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5736 = out_prepend_477; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5737 = _out_T_5736; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_478 = _out_T_5737; // @[RegisterRouter.scala:87:24] wire out_rimask_566 = \|_out_rimask_T_566; // @[RegisterRouter.scala:87:24] wire out_wimask_566 = &_out_wimask_T_566; // @[RegisterRouter.scala:87:24] wire out_romask_566 = \|_out_romask_T_566; // @[RegisterRouter.scala:87:24] wire out_womask_566 = &_out_womask_T_566; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_566 = out_rivalid_1_420 & out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5739 = out_f_rivalid_566; // @[RegisterRouter.scala:87:24] wire out_f_roready_566 = out_roready_1_420 & out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5740 = out_f_roready_566; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_566 = out_wivalid_1_420 & out_wimask_566; // @[RegisterRouter.scala:87:24] wire out_f_woready_566 = out_woready_1_420 & out_womask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5741 = ~out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5742 = ~out_wimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5743 = ~out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5744 = ~out_womask_566; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_478 = {hi_779, flags_0_go, _out_prepend_T_478}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5745 = out_prepend_478; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5746 = _out_T_5745; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_479 = _out_T_5746; // @[RegisterRouter.scala:87:24] wire out_rimask_567 = \|_out_rimask_T_567; // @[RegisterRouter.scala:87:24] wire out_wimask_567 = &_out_wimask_T_567; // @[RegisterRouter.scala:87:24] wire out_romask_567 = \|_out_romask_T_567; // @[RegisterRouter.scala:87:24] wire out_womask_567 = &_out_womask_T_567; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_567 = out_rivalid_1_421 & out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5748 = out_f_rivalid_567; // @[RegisterRouter.scala:87:24] wire out_f_roready_567 = out_roready_1_421 & out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5749 = out_f_roready_567; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_567 = out_wivalid_1_421 & out_wimask_567; // @[RegisterRouter.scala:87:24] wire out_f_woready_567 = out_woready_1_421 & out_womask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5750 = ~out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5751 = ~out_wimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5752 = ~out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5753 = ~out_womask_567; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_479 = {hi_780, flags_0_go, _out_prepend_T_479}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5754 = out_prepend_479; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5755 = _out_T_5754; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_480 = _out_T_5755; // @[RegisterRouter.scala:87:24] wire out_rimask_568 = \|_out_rimask_T_568; // @[RegisterRouter.scala:87:24] wire out_wimask_568 = &_out_wimask_T_568; // @[RegisterRouter.scala:87:24] wire out_romask_568 = \|_out_romask_T_568; // @[RegisterRouter.scala:87:24] wire out_womask_568 = &_out_womask_T_568; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_568 = out_rivalid_1_422 & out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5757 = out_f_rivalid_568; // @[RegisterRouter.scala:87:24] wire out_f_roready_568 = out_roready_1_422 & out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5758 = out_f_roready_568; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_568 = out_wivalid_1_422 & out_wimask_568; // @[RegisterRouter.scala:87:24] wire out_f_woready_568 = out_woready_1_422 & out_womask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5759 = ~out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5760 = ~out_wimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5761 = ~out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5762 = ~out_womask_568; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_480 = {hi_781, flags_0_go, _out_prepend_T_480}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5763 = out_prepend_480; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5764 = _out_T_5763; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_481 = _out_T_5764; // @[RegisterRouter.scala:87:24] wire out_rimask_569 = \|_out_rimask_T_569; // @[RegisterRouter.scala:87:24] wire out_wimask_569 = &_out_wimask_T_569; // @[RegisterRouter.scala:87:24] wire out_romask_569 = \|_out_romask_T_569; // @[RegisterRouter.scala:87:24] wire out_womask_569 = &_out_womask_T_569; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_569 = out_rivalid_1_423 & out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5766 = out_f_rivalid_569; // @[RegisterRouter.scala:87:24] wire out_f_roready_569 = out_roready_1_423 & out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5767 = out_f_roready_569; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_569 = out_wivalid_1_423 & out_wimask_569; // @[RegisterRouter.scala:87:24] wire out_f_woready_569 = out_woready_1_423 & out_womask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5768 = ~out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5769 = ~out_wimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5770 = ~out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5771 = ~out_womask_569; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_481 = {hi_782, flags_0_go, _out_prepend_T_481}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5772 = out_prepend_481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5773 = _out_T_5772; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_482 = _out_T_5773; // @[RegisterRouter.scala:87:24] wire out_rimask_570 = \|_out_rimask_T_570; // @[RegisterRouter.scala:87:24] wire out_wimask_570 = &_out_wimask_T_570; // @[RegisterRouter.scala:87:24] wire out_romask_570 = \|_out_romask_T_570; // @[RegisterRouter.scala:87:24] wire out_womask_570 = &_out_womask_T_570; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_570 = out_rivalid_1_424 & out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5775 = out_f_rivalid_570; // @[RegisterRouter.scala:87:24] wire out_f_roready_570 = out_roready_1_424 & out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5776 = out_f_roready_570; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_570 = out_wivalid_1_424 & out_wimask_570; // @[RegisterRouter.scala:87:24] wire out_f_woready_570 = out_woready_1_424 & out_womask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5777 = ~out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5778 = ~out_wimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5779 = ~out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5780 = ~out_womask_570; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_482 = {hi_783, flags_0_go, _out_prepend_T_482}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5781 = out_prepend_482; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5782 = _out_T_5781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_483 = _out_T_5782; // @[RegisterRouter.scala:87:24] wire out_rimask_571 = \|_out_rimask_T_571; // @[RegisterRouter.scala:87:24] wire out_wimask_571 = &_out_wimask_T_571; // @[RegisterRouter.scala:87:24] wire out_romask_571 = \|_out_romask_T_571; // @[RegisterRouter.scala:87:24] wire out_womask_571 = &_out_womask_T_571; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_571 = out_rivalid_1_425 & out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5784 = out_f_rivalid_571; // @[RegisterRouter.scala:87:24] wire out_f_roready_571 = out_roready_1_425 & out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5785 = out_f_roready_571; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_571 = out_wivalid_1_425 & out_wimask_571; // @[RegisterRouter.scala:87:24] wire out_f_woready_571 = out_woready_1_425 & out_womask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5786 = ~out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5787 = ~out_wimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5788 = ~out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5789 = ~out_womask_571; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_483 = {hi_784, flags_0_go, _out_prepend_T_483}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5790 = out_prepend_483; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5791 = _out_T_5790; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_225 = _out_T_5791; // @[MuxLiteral.scala:49:48] wire out_rimask_572 = \|_out_rimask_T_572; // @[RegisterRouter.scala:87:24] wire out_wimask_572 = &_out_wimask_T_572; // @[RegisterRouter.scala:87:24] wire out_romask_572 = \|_out_romask_T_572; // @[RegisterRouter.scala:87:24] wire out_womask_572 = &_out_womask_T_572; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_572 = out_rivalid_1_426 & out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5793 = out_f_rivalid_572; // @[RegisterRouter.scala:87:24] wire out_f_roready_572 = out_roready_1_426 & out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5794 = out_f_roready_572; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_572 = out_wivalid_1_426 & out_wimask_572; // @[RegisterRouter.scala:87:24] wire out_f_woready_572 = out_woready_1_426 & out_womask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5795 = ~out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5796 = ~out_wimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5797 = ~out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5798 = ~out_womask_572; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5800 = _out_T_5799; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_484 = _out_T_5800; // @[RegisterRouter.scala:87:24] wire out_rimask_573 = \|_out_rimask_T_573; // @[RegisterRouter.scala:87:24] wire out_wimask_573 = &_out_wimask_T_573; // @[RegisterRouter.scala:87:24] wire out_romask_573 = \|_out_romask_T_573; // @[RegisterRouter.scala:87:24] wire out_womask_573 = &_out_womask_T_573; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_573 = out_rivalid_1_427 & out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5802 = out_f_rivalid_573; // @[RegisterRouter.scala:87:24] wire out_f_roready_573 = out_roready_1_427 & out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5803 = out_f_roready_573; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_573 = out_wivalid_1_427 & out_wimask_573; // @[RegisterRouter.scala:87:24] wire out_f_woready_573 = out_woready_1_427 & out_womask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5804 = ~out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5805 = ~out_wimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5806 = ~out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5807 = ~out_womask_573; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_484 = {hi_522, flags_0_go, _out_prepend_T_484}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5808 = out_prepend_484; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5809 = _out_T_5808; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_485 = _out_T_5809; // @[RegisterRouter.scala:87:24] wire out_rimask_574 = \|_out_rimask_T_574; // @[RegisterRouter.scala:87:24] wire out_wimask_574 = &_out_wimask_T_574; // @[RegisterRouter.scala:87:24] wire out_romask_574 = \|_out_romask_T_574; // @[RegisterRouter.scala:87:24] wire out_womask_574 = &_out_womask_T_574; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_574 = out_rivalid_1_428 & out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5811 = out_f_rivalid_574; // @[RegisterRouter.scala:87:24] wire out_f_roready_574 = out_roready_1_428 & out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5812 = out_f_roready_574; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_574 = out_wivalid_1_428 & out_wimask_574; // @[RegisterRouter.scala:87:24] wire out_f_woready_574 = out_woready_1_428 & out_womask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5813 = ~out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5814 = ~out_wimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5815 = ~out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5816 = ~out_womask_574; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_485 = {hi_523, flags_0_go, _out_prepend_T_485}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5817 = out_prepend_485; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5818 = _out_T_5817; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_486 = _out_T_5818; // @[RegisterRouter.scala:87:24] wire out_rimask_575 = \|_out_rimask_T_575; // @[RegisterRouter.scala:87:24] wire out_wimask_575 = &_out_wimask_T_575; // @[RegisterRouter.scala:87:24] wire out_romask_575 = \|_out_romask_T_575; // @[RegisterRouter.scala:87:24] wire out_womask_575 = &_out_womask_T_575; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_575 = out_rivalid_1_429 & out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5820 = out_f_rivalid_575; // @[RegisterRouter.scala:87:24] wire out_f_roready_575 = out_roready_1_429 & out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5821 = out_f_roready_575; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_575 = out_wivalid_1_429 & out_wimask_575; // @[RegisterRouter.scala:87:24] wire out_f_woready_575 = out_woready_1_429 & out_womask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5822 = ~out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5823 = ~out_wimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5824 = ~out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5825 = ~out_womask_575; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_486 = {hi_524, flags_0_go, _out_prepend_T_486}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5826 = out_prepend_486; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5827 = _out_T_5826; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_487 = _out_T_5827; // @[RegisterRouter.scala:87:24] wire out_rimask_576 = \|_out_rimask_T_576; // @[RegisterRouter.scala:87:24] wire out_wimask_576 = &_out_wimask_T_576; // @[RegisterRouter.scala:87:24] wire out_romask_576 = \|_out_romask_T_576; // @[RegisterRouter.scala:87:24] wire out_womask_576 = &_out_womask_T_576; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_576 = out_rivalid_1_430 & out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5829 = out_f_rivalid_576; // @[RegisterRouter.scala:87:24] wire out_f_roready_576 = out_roready_1_430 & out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5830 = out_f_roready_576; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_576 = out_wivalid_1_430 & out_wimask_576; // @[RegisterRouter.scala:87:24] wire out_f_woready_576 = out_woready_1_430 & out_womask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5831 = ~out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5832 = ~out_wimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5833 = ~out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5834 = ~out_womask_576; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_487 = {hi_525, flags_0_go, _out_prepend_T_487}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5835 = out_prepend_487; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5836 = _out_T_5835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_488 = _out_T_5836; // @[RegisterRouter.scala:87:24] wire out_rimask_577 = \|_out_rimask_T_577; // @[RegisterRouter.scala:87:24] wire out_wimask_577 = &_out_wimask_T_577; // @[RegisterRouter.scala:87:24] wire out_romask_577 = \|_out_romask_T_577; // @[RegisterRouter.scala:87:24] wire out_womask_577 = &_out_womask_T_577; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_577 = out_rivalid_1_431 & out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5838 = out_f_rivalid_577; // @[RegisterRouter.scala:87:24] wire out_f_roready_577 = out_roready_1_431 & out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5839 = out_f_roready_577; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_577 = out_wivalid_1_431 & out_wimask_577; // @[RegisterRouter.scala:87:24] wire out_f_woready_577 = out_woready_1_431 & out_womask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5840 = ~out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5841 = ~out_wimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5842 = ~out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5843 = ~out_womask_577; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_488 = {hi_526, flags_0_go, _out_prepend_T_488}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5844 = out_prepend_488; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5845 = _out_T_5844; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_489 = _out_T_5845; // @[RegisterRouter.scala:87:24] wire out_rimask_578 = \|_out_rimask_T_578; // @[RegisterRouter.scala:87:24] wire out_wimask_578 = &_out_wimask_T_578; // @[RegisterRouter.scala:87:24] wire out_romask_578 = \|_out_romask_T_578; // @[RegisterRouter.scala:87:24] wire out_womask_578 = &_out_womask_T_578; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_578 = out_rivalid_1_432 & out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5847 = out_f_rivalid_578; // @[RegisterRouter.scala:87:24] wire out_f_roready_578 = out_roready_1_432 & out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5848 = out_f_roready_578; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_578 = out_wivalid_1_432 & out_wimask_578; // @[RegisterRouter.scala:87:24] wire out_f_woready_578 = out_woready_1_432 & out_womask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5849 = ~out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5850 = ~out_wimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5851 = ~out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5852 = ~out_womask_578; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_489 = {hi_527, flags_0_go, _out_prepend_T_489}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5853 = out_prepend_489; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5854 = _out_T_5853; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_490 = _out_T_5854; // @[RegisterRouter.scala:87:24] wire out_rimask_579 = \|_out_rimask_T_579; // @[RegisterRouter.scala:87:24] wire out_wimask_579 = &_out_wimask_T_579; // @[RegisterRouter.scala:87:24] wire out_romask_579 = \|_out_romask_T_579; // @[RegisterRouter.scala:87:24] wire out_womask_579 = &_out_womask_T_579; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_579 = out_rivalid_1_433 & out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5856 = out_f_rivalid_579; // @[RegisterRouter.scala:87:24] wire out_f_roready_579 = out_roready_1_433 & out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5857 = out_f_roready_579; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_579 = out_wivalid_1_433 & out_wimask_579; // @[RegisterRouter.scala:87:24] wire out_f_woready_579 = out_woready_1_433 & out_womask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5858 = ~out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5859 = ~out_wimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5860 = ~out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5861 = ~out_womask_579; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_490 = {hi_528, flags_0_go, _out_prepend_T_490}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5862 = out_prepend_490; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5863 = _out_T_5862; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_193 = _out_T_5863; // @[MuxLiteral.scala:49:48] wire out_rimask_580 = \|_out_rimask_T_580; // @[RegisterRouter.scala:87:24] wire out_wimask_580 = &_out_wimask_T_580; // @[RegisterRouter.scala:87:24] wire out_romask_580 = \|_out_romask_T_580; // @[RegisterRouter.scala:87:24] wire out_womask_580 = &_out_womask_T_580; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_580 = out_rivalid_1_434 & out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5865 = out_f_rivalid_580; // @[RegisterRouter.scala:87:24] wire out_f_roready_580 = out_roready_1_434 & out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5866 = out_f_roready_580; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_580 = out_wivalid_1_434 & out_wimask_580; // @[RegisterRouter.scala:87:24] wire out_f_woready_580 = out_woready_1_434 & out_womask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5867 = ~out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5868 = ~out_wimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5869 = ~out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5870 = ~out_womask_580; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5872 = _out_T_5871; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_491 = _out_T_5872; // @[RegisterRouter.scala:87:24] wire out_rimask_581 = \|_out_rimask_T_581; // @[RegisterRouter.scala:87:24] wire out_wimask_581 = &_out_wimask_T_581; // @[RegisterRouter.scala:87:24] wire out_romask_581 = \|_out_romask_T_581; // @[RegisterRouter.scala:87:24] wire out_womask_581 = &_out_womask_T_581; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_581 = out_rivalid_1_435 & out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5874 = out_f_rivalid_581; // @[RegisterRouter.scala:87:24] wire out_f_roready_581 = out_roready_1_435 & out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5875 = out_f_roready_581; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_581 = out_wivalid_1_435 & out_wimask_581; // @[RegisterRouter.scala:87:24] wire out_f_woready_581 = out_woready_1_435 & out_womask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5876 = ~out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5877 = ~out_wimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5878 = ~out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5879 = ~out_womask_581; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_491 = {hi_674, flags_0_go, _out_prepend_T_491}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5880 = out_prepend_491; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5881 = _out_T_5880; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_492 = _out_T_5881; // @[RegisterRouter.scala:87:24] wire out_rimask_582 = \|_out_rimask_T_582; // @[RegisterRouter.scala:87:24] wire out_wimask_582 = &_out_wimask_T_582; // @[RegisterRouter.scala:87:24] wire out_romask_582 = \|_out_romask_T_582; // @[RegisterRouter.scala:87:24] wire out_womask_582 = &_out_womask_T_582; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_582 = out_rivalid_1_436 & out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5883 = out_f_rivalid_582; // @[RegisterRouter.scala:87:24] wire out_f_roready_582 = out_roready_1_436 & out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5884 = out_f_roready_582; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_582 = out_wivalid_1_436 & out_wimask_582; // @[RegisterRouter.scala:87:24] wire out_f_woready_582 = out_woready_1_436 & out_womask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5885 = ~out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5886 = ~out_wimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5887 = ~out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5888 = ~out_womask_582; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_492 = {hi_675, flags_0_go, _out_prepend_T_492}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5889 = out_prepend_492; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5890 = _out_T_5889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_493 = _out_T_5890; // @[RegisterRouter.scala:87:24] wire out_rimask_583 = \|_out_rimask_T_583; // @[RegisterRouter.scala:87:24] wire out_wimask_583 = &_out_wimask_T_583; // @[RegisterRouter.scala:87:24] wire out_romask_583 = \|_out_romask_T_583; // @[RegisterRouter.scala:87:24] wire out_womask_583 = &_out_womask_T_583; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_583 = out_rivalid_1_437 & out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5892 = out_f_rivalid_583; // @[RegisterRouter.scala:87:24] wire out_f_roready_583 = out_roready_1_437 & out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5893 = out_f_roready_583; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_583 = out_wivalid_1_437 & out_wimask_583; // @[RegisterRouter.scala:87:24] wire out_f_woready_583 = out_woready_1_437 & out_womask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5894 = ~out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5895 = ~out_wimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5896 = ~out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5897 = ~out_womask_583; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_493 = {hi_676, flags_0_go, _out_prepend_T_493}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5898 = out_prepend_493; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5899 = _out_T_5898; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_494 = _out_T_5899; // @[RegisterRouter.scala:87:24] wire out_rimask_584 = \|_out_rimask_T_584; // @[RegisterRouter.scala:87:24] wire out_wimask_584 = &_out_wimask_T_584; // @[RegisterRouter.scala:87:24] wire out_romask_584 = \|_out_romask_T_584; // @[RegisterRouter.scala:87:24] wire out_womask_584 = &_out_womask_T_584; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_584 = out_rivalid_1_438 & out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5901 = out_f_rivalid_584; // @[RegisterRouter.scala:87:24] wire out_f_roready_584 = out_roready_1_438 & out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5902 = out_f_roready_584; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_584 = out_wivalid_1_438 & out_wimask_584; // @[RegisterRouter.scala:87:24] wire out_f_woready_584 = out_woready_1_438 & out_womask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5903 = ~out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5904 = ~out_wimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5905 = ~out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5906 = ~out_womask_584; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_494 = {hi_677, flags_0_go, _out_prepend_T_494}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5907 = out_prepend_494; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5908 = _out_T_5907; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_495 = _out_T_5908; // @[RegisterRouter.scala:87:24] wire out_rimask_585 = \|_out_rimask_T_585; // @[RegisterRouter.scala:87:24] wire out_wimask_585 = &_out_wimask_T_585; // @[RegisterRouter.scala:87:24] wire out_romask_585 = \|_out_romask_T_585; // @[RegisterRouter.scala:87:24] wire out_womask_585 = &_out_womask_T_585; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_585 = out_rivalid_1_439 & out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5910 = out_f_rivalid_585; // @[RegisterRouter.scala:87:24] wire out_f_roready_585 = out_roready_1_439 & out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5911 = out_f_roready_585; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_585 = out_wivalid_1_439 & out_wimask_585; // @[RegisterRouter.scala:87:24] wire out_f_woready_585 = out_woready_1_439 & out_womask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5912 = ~out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5913 = ~out_wimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5914 = ~out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5915 = ~out_womask_585; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_495 = {hi_678, flags_0_go, _out_prepend_T_495}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5916 = out_prepend_495; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5917 = _out_T_5916; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_496 = _out_T_5917; // @[RegisterRouter.scala:87:24] wire out_rimask_586 = \|_out_rimask_T_586; // @[RegisterRouter.scala:87:24] wire out_wimask_586 = &_out_wimask_T_586; // @[RegisterRouter.scala:87:24] wire out_romask_586 = \|_out_romask_T_586; // @[RegisterRouter.scala:87:24] wire out_womask_586 = &_out_womask_T_586; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_586 = out_rivalid_1_440 & out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5919 = out_f_rivalid_586; // @[RegisterRouter.scala:87:24] wire out_f_roready_586 = out_roready_1_440 & out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5920 = out_f_roready_586; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_586 = out_wivalid_1_440 & out_wimask_586; // @[RegisterRouter.scala:87:24] wire out_f_woready_586 = out_woready_1_440 & out_womask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5921 = ~out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5922 = ~out_wimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5923 = ~out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5924 = ~out_womask_586; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_496 = {hi_679, flags_0_go, _out_prepend_T_496}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5925 = out_prepend_496; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5926 = _out_T_5925; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_497 = _out_T_5926; // @[RegisterRouter.scala:87:24] wire out_rimask_587 = \|_out_rimask_T_587; // @[RegisterRouter.scala:87:24] wire out_wimask_587 = &_out_wimask_T_587; // @[RegisterRouter.scala:87:24] wire out_romask_587 = \|_out_romask_T_587; // @[RegisterRouter.scala:87:24] wire out_womask_587 = &_out_womask_T_587; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_587 = out_rivalid_1_441 & out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5928 = out_f_rivalid_587; // @[RegisterRouter.scala:87:24] wire out_f_roready_587 = out_roready_1_441 & out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5929 = out_f_roready_587; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_587 = out_wivalid_1_441 & out_wimask_587; // @[RegisterRouter.scala:87:24] wire out_f_woready_587 = out_woready_1_441 & out_womask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5930 = ~out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5931 = ~out_wimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5932 = ~out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5933 = ~out_womask_587; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_497 = {hi_680, flags_0_go, _out_prepend_T_497}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5934 = out_prepend_497; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5935 = _out_T_5934; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_212 = _out_T_5935; // @[MuxLiteral.scala:49:48] wire [31:0] _out_rimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_588 = \|_out_rimask_T_588; // @[RegisterRouter.scala:87:24] wire out_wimask_588 = &_out_wimask_T_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_588 = \|_out_romask_T_588; // @[RegisterRouter.scala:87:24] wire out_womask_588 = &_out_womask_T_588; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_588 = out_rivalid_1_442 & out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5937 = out_f_rivalid_588; // @[RegisterRouter.scala:87:24] wire out_f_roready_588 = out_roready_1_442 & out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5938 = out_f_roready_588; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_588 = out_wivalid_1_442 & out_wimask_588; // @[RegisterRouter.scala:87:24] wire out_f_woready_588 = out_woready_1_442 & out_womask_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5936 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8279 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire _out_T_5939 = ~out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5940 = ~out_wimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5941 = ~out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5942 = ~out_womask_588; // @[RegisterRouter.scala:87:24] wire out_rimask_589 = \|_out_rimask_T_589; // @[RegisterRouter.scala:87:24] wire out_wimask_589 = &_out_wimask_T_589; // @[RegisterRouter.scala:87:24] wire out_romask_589 = \|_out_romask_T_589; // @[RegisterRouter.scala:87:24] wire out_womask_589 = &_out_womask_T_589; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_589 = out_rivalid_1_443 & out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5946 = out_f_rivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_roready_589 = out_roready_1_443 & out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5947 = out_f_roready_589; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_589 = out_wivalid_1_443 & out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5948 = out_f_wivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_woready_589 = out_woready_1_443 & out_womask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5949 = out_f_woready_589; // @[RegisterRouter.scala:87:24] wire _out_T_5950 = ~out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5951 = ~out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5952 = ~out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5953 = ~out_womask_589; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5955 = _out_T_5954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_498 = _out_T_5955; // @[RegisterRouter.scala:87:24] wire out_rimask_590 = \|_out_rimask_T_590; // @[RegisterRouter.scala:87:24] wire out_wimask_590 = &_out_wimask_T_590; // @[RegisterRouter.scala:87:24] wire out_romask_590 = \|_out_romask_T_590; // @[RegisterRouter.scala:87:24] wire out_womask_590 = &_out_womask_T_590; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_590 = out_rivalid_1_444 & out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5957 = out_f_rivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_roready_590 = out_roready_1_444 & out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5958 = out_f_roready_590; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_590 = out_wivalid_1_444 & out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5959 = out_f_wivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_woready_590 = out_woready_1_444 & out_womask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5960 = out_f_woready_590; // @[RegisterRouter.scala:87:24] wire _out_T_5961 = ~out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5962 = ~out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5963 = ~out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5964 = ~out_womask_590; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_498 = {programBufferMem_41, _out_prepend_T_498}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5965 = out_prepend_498; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5966 = _out_T_5965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_499 = _out_T_5966; // @[RegisterRouter.scala:87:24] wire out_rimask_591 = \|_out_rimask_T_591; // @[RegisterRouter.scala:87:24] wire out_wimask_591 = &_out_wimask_T_591; // @[RegisterRouter.scala:87:24] wire out_romask_591 = \|_out_romask_T_591; // @[RegisterRouter.scala:87:24] wire out_womask_591 = &_out_womask_T_591; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_591 = out_rivalid_1_445 & out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5968 = out_f_rivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_roready_591 = out_roready_1_445 & out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5969 = out_f_roready_591; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_591 = out_wivalid_1_445 & out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5970 = out_f_wivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_woready_591 = out_woready_1_445 & out_womask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5971 = out_f_woready_591; // @[RegisterRouter.scala:87:24] wire _out_T_5972 = ~out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5973 = ~out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5974 = ~out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5975 = ~out_womask_591; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_499 = {programBufferMem_42, _out_prepend_T_499}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5976 = out_prepend_499; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5977 = _out_T_5976; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_500 = _out_T_5977; // @[RegisterRouter.scala:87:24] wire out_rimask_592 = \|_out_rimask_T_592; // @[RegisterRouter.scala:87:24] wire out_wimask_592 = &_out_wimask_T_592; // @[RegisterRouter.scala:87:24] wire out_romask_592 = \|_out_romask_T_592; // @[RegisterRouter.scala:87:24] wire out_womask_592 = &_out_womask_T_592; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_592 = out_rivalid_1_446 & out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5979 = out_f_rivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_roready_592 = out_roready_1_446 & out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5980 = out_f_roready_592; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_592 = out_wivalid_1_446 & out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5981 = out_f_wivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_woready_592 = out_woready_1_446 & out_womask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5982 = out_f_woready_592; // @[RegisterRouter.scala:87:24] wire _out_T_5983 = ~out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5984 = ~out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5985 = ~out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5986 = ~out_womask_592; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_500 = {programBufferMem_43, _out_prepend_T_500}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5987 = out_prepend_500; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5988 = _out_T_5987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_501 = _out_T_5988; // @[RegisterRouter.scala:87:24] wire out_rimask_593 = \|_out_rimask_T_593; // @[RegisterRouter.scala:87:24] wire out_wimask_593 = &_out_wimask_T_593; // @[RegisterRouter.scala:87:24] wire out_romask_593 = \|_out_romask_T_593; // @[RegisterRouter.scala:87:24] wire out_womask_593 = &_out_womask_T_593; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_593 = out_rivalid_1_447 & out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5990 = out_f_rivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_roready_593 = out_roready_1_447 & out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5991 = out_f_roready_593; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_593 = out_wivalid_1_447 & out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5992 = out_f_wivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_woready_593 = out_woready_1_447 & out_womask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5993 = out_f_woready_593; // @[RegisterRouter.scala:87:24] wire _out_T_5994 = ~out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5995 = ~out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5996 = ~out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5997 = ~out_womask_593; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_501 = {programBufferMem_44, _out_prepend_T_501}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5998 = out_prepend_501; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5999 = _out_T_5998; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_502 = _out_T_5999; // @[RegisterRouter.scala:87:24] wire out_rimask_594 = \|_out_rimask_T_594; // @[RegisterRouter.scala:87:24] wire out_wimask_594 = &_out_wimask_T_594; // @[RegisterRouter.scala:87:24] wire out_romask_594 = \|_out_romask_T_594; // @[RegisterRouter.scala:87:24] wire out_womask_594 = &_out_womask_T_594; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_594 = out_rivalid_1_448 & out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6001 = out_f_rivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_roready_594 = out_roready_1_448 & out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6002 = out_f_roready_594; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_594 = out_wivalid_1_448 & out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6003 = out_f_wivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_woready_594 = out_woready_1_448 & out_womask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6004 = out_f_woready_594; // @[RegisterRouter.scala:87:24] wire _out_T_6005 = ~out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6006 = ~out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6007 = ~out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6008 = ~out_womask_594; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_502 = {programBufferMem_45, _out_prepend_T_502}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6009 = out_prepend_502; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6010 = _out_T_6009; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_503 = _out_T_6010; // @[RegisterRouter.scala:87:24] wire out_rimask_595 = \|_out_rimask_T_595; // @[RegisterRouter.scala:87:24] wire out_wimask_595 = &_out_wimask_T_595; // @[RegisterRouter.scala:87:24] wire out_romask_595 = \|_out_romask_T_595; // @[RegisterRouter.scala:87:24] wire out_womask_595 = &_out_womask_T_595; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_595 = out_rivalid_1_449 & out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6012 = out_f_rivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_roready_595 = out_roready_1_449 & out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6013 = out_f_roready_595; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_595 = out_wivalid_1_449 & out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6014 = out_f_wivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_woready_595 = out_woready_1_449 & out_womask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6015 = out_f_woready_595; // @[RegisterRouter.scala:87:24] wire _out_T_6016 = ~out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6017 = ~out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6018 = ~out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6019 = ~out_womask_595; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_503 = {programBufferMem_46, _out_prepend_T_503}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6020 = out_prepend_503; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6021 = _out_T_6020; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_504 = _out_T_6021; // @[RegisterRouter.scala:87:24] wire out_rimask_596 = \|_out_rimask_T_596; // @[RegisterRouter.scala:87:24] wire out_wimask_596 = &_out_wimask_T_596; // @[RegisterRouter.scala:87:24] wire out_romask_596 = \|_out_romask_T_596; // @[RegisterRouter.scala:87:24] wire out_womask_596 = &_out_womask_T_596; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_596 = out_rivalid_1_450 & out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6023 = out_f_rivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_roready_596 = out_roready_1_450 & out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6024 = out_f_roready_596; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_596 = out_wivalid_1_450 & out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6025 = out_f_wivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_woready_596 = out_woready_1_450 & out_womask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6026 = out_f_woready_596; // @[RegisterRouter.scala:87:24] wire _out_T_6027 = ~out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6028 = ~out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6029 = ~out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6030 = ~out_womask_596; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_504 = {programBufferMem_47, _out_prepend_T_504}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6031 = out_prepend_504; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6032 = _out_T_6031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_109 = _out_T_6032; // @[MuxLiteral.scala:49:48] wire out_rimask_597 = \|_out_rimask_T_597; // @[RegisterRouter.scala:87:24] wire out_wimask_597 = &_out_wimask_T_597; // @[RegisterRouter.scala:87:24] wire out_romask_597 = \|_out_romask_T_597; // @[RegisterRouter.scala:87:24] wire out_womask_597 = &_out_womask_T_597; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_597 = out_rivalid_1_451 & out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6034 = out_f_rivalid_597; // @[RegisterRouter.scala:87:24] wire out_f_roready_597 = out_roready_1_451 & out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6035 = out_f_roready_597; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_597 = out_wivalid_1_451 & out_wimask_597; // @[RegisterRouter.scala:87:24] wire out_f_woready_597 = out_woready_1_451 & out_womask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6036 = ~out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6037 = ~out_wimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6038 = ~out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6039 = ~out_womask_597; // @[RegisterRouter.scala:87:24] wire out_rimask_598 = \|_out_rimask_T_598; // @[RegisterRouter.scala:87:24] wire out_wimask_598 = &_out_wimask_T_598; // @[RegisterRouter.scala:87:24] wire out_romask_598 = \|_out_romask_T_598; // @[RegisterRouter.scala:87:24] wire out_womask_598 = &_out_womask_T_598; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_598 = out_rivalid_1_452 & out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6043 = out_f_rivalid_598; // @[RegisterRouter.scala:87:24] wire out_f_roready_598 = out_roready_1_452 & out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6044 = out_f_roready_598; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_598 = out_wivalid_1_452 & out_wimask_598; // @[RegisterRouter.scala:87:24] wire out_f_woready_598 = out_woready_1_452 & out_womask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6045 = ~out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6046 = ~out_wimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6047 = ~out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6048 = ~out_womask_598; // @[RegisterRouter.scala:87:24] wire out_rimask_599 = \|_out_rimask_T_599; // @[RegisterRouter.scala:87:24] wire out_wimask_599 = &_out_wimask_T_599; // @[RegisterRouter.scala:87:24] wire out_romask_599 = \|_out_romask_T_599; // @[RegisterRouter.scala:87:24] wire out_womask_599 = &_out_womask_T_599; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_599 = out_rivalid_1_453 & out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6052 = out_f_rivalid_599; // @[RegisterRouter.scala:87:24] wire out_f_roready_599 = out_roready_1_453 & out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6053 = out_f_roready_599; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_599 = out_wivalid_1_453 & out_wimask_599; // @[RegisterRouter.scala:87:24] wire out_f_woready_599 = out_woready_1_453 & out_womask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6054 = ~out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6055 = ~out_wimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6056 = ~out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6057 = ~out_womask_599; // @[RegisterRouter.scala:87:24] wire out_rimask_600 = \|_out_rimask_T_600; // @[RegisterRouter.scala:87:24] wire out_wimask_600 = &_out_wimask_T_600; // @[RegisterRouter.scala:87:24] wire out_romask_600 = \|_out_romask_T_600; // @[RegisterRouter.scala:87:24] wire out_womask_600 = &_out_womask_T_600; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_600 = out_rivalid_1_454 & out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6061 = out_f_rivalid_600; // @[RegisterRouter.scala:87:24] wire out_f_roready_600 = out_roready_1_454 & out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6062 = out_f_roready_600; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_600 = out_wivalid_1_454 & out_wimask_600; // @[RegisterRouter.scala:87:24] wire out_f_woready_600 = out_woready_1_454 & out_womask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6063 = ~out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6064 = ~out_wimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6065 = ~out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6066 = ~out_womask_600; // @[RegisterRouter.scala:87:24] wire out_rimask_601 = \|_out_rimask_T_601; // @[RegisterRouter.scala:87:24] wire out_wimask_601 = &_out_wimask_T_601; // @[RegisterRouter.scala:87:24] wire out_romask_601 = \|_out_romask_T_601; // @[RegisterRouter.scala:87:24] wire out_womask_601 = &_out_womask_T_601; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_601 = out_rivalid_1_455 & out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6070 = out_f_rivalid_601; // @[RegisterRouter.scala:87:24] wire out_f_roready_601 = out_roready_1_455 & out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6071 = out_f_roready_601; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_601 = out_wivalid_1_455 & out_wimask_601; // @[RegisterRouter.scala:87:24] wire out_f_woready_601 = out_woready_1_455 & out_womask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6072 = ~out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6073 = ~out_wimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6074 = ~out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6075 = ~out_womask_601; // @[RegisterRouter.scala:87:24] wire out_rimask_602 = \|_out_rimask_T_602; // @[RegisterRouter.scala:87:24] wire out_wimask_602 = &_out_wimask_T_602; // @[RegisterRouter.scala:87:24] wire out_romask_602 = \|_out_romask_T_602; // @[RegisterRouter.scala:87:24] wire out_womask_602 = &_out_womask_T_602; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_602 = out_rivalid_1_456 & out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6079 = out_f_rivalid_602; // @[RegisterRouter.scala:87:24] wire out_f_roready_602 = out_roready_1_456 & out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6080 = out_f_roready_602; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_602 = out_wivalid_1_456 & out_wimask_602; // @[RegisterRouter.scala:87:24] wire out_f_woready_602 = out_woready_1_456 & out_womask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6081 = ~out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6082 = ~out_wimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6083 = ~out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6084 = ~out_womask_602; // @[RegisterRouter.scala:87:24] wire out_rimask_603 = \|_out_rimask_T_603; // @[RegisterRouter.scala:87:24] wire out_wimask_603 = &_out_wimask_T_603; // @[RegisterRouter.scala:87:24] wire out_romask_603 = \|_out_romask_T_603; // @[RegisterRouter.scala:87:24] wire out_womask_603 = &_out_womask_T_603; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_603 = out_rivalid_1_457 & out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6088 = out_f_rivalid_603; // @[RegisterRouter.scala:87:24] wire out_f_roready_603 = out_roready_1_457 & out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6089 = out_f_roready_603; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_603 = out_wivalid_1_457 & out_wimask_603; // @[RegisterRouter.scala:87:24] wire out_f_woready_603 = out_woready_1_457 & out_womask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6090 = ~out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6091 = ~out_wimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6092 = ~out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6093 = ~out_womask_603; // @[RegisterRouter.scala:87:24] wire out_rimask_604 = \|_out_rimask_T_604; // @[RegisterRouter.scala:87:24] wire out_wimask_604 = &_out_wimask_T_604; // @[RegisterRouter.scala:87:24] wire out_romask_604 = \|_out_romask_T_604; // @[RegisterRouter.scala:87:24] wire out_womask_604 = &_out_womask_T_604; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_604 = out_rivalid_1_458 & out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6097 = out_f_rivalid_604; // @[RegisterRouter.scala:87:24] wire out_f_roready_604 = out_roready_1_458 & out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6098 = out_f_roready_604; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_604 = out_wivalid_1_458 & out_wimask_604; // @[RegisterRouter.scala:87:24] wire out_f_woready_604 = out_woready_1_458 & out_womask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6099 = ~out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6100 = ~out_wimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6101 = ~out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6102 = ~out_womask_604; // @[RegisterRouter.scala:87:24] wire out_rimask_605 = \|_out_rimask_T_605; // @[RegisterRouter.scala:87:24] wire out_wimask_605 = &_out_wimask_T_605; // @[RegisterRouter.scala:87:24] wire out_romask_605 = \|_out_romask_T_605; // @[RegisterRouter.scala:87:24] wire out_womask_605 = &_out_womask_T_605; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_605 = out_rivalid_1_459 & out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6106 = out_f_rivalid_605; // @[RegisterRouter.scala:87:24] wire out_f_roready_605 = out_roready_1_459 & out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6107 = out_f_roready_605; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_605 = out_wivalid_1_459 & out_wimask_605; // @[RegisterRouter.scala:87:24] wire out_f_woready_605 = out_woready_1_459 & out_womask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6108 = ~out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6109 = ~out_wimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6110 = ~out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6111 = ~out_womask_605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6113 = _out_T_6112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_512 = _out_T_6113; // @[RegisterRouter.scala:87:24] wire out_rimask_606 = \|_out_rimask_T_606; // @[RegisterRouter.scala:87:24] wire out_wimask_606 = &_out_wimask_T_606; // @[RegisterRouter.scala:87:24] wire out_romask_606 = \|_out_romask_T_606; // @[RegisterRouter.scala:87:24] wire out_womask_606 = &_out_womask_T_606; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_606 = out_rivalid_1_460 & out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6115 = out_f_rivalid_606; // @[RegisterRouter.scala:87:24] wire out_f_roready_606 = out_roready_1_460 & out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6116 = out_f_roready_606; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_606 = out_wivalid_1_460 & out_wimask_606; // @[RegisterRouter.scala:87:24] wire out_f_woready_606 = out_woready_1_460 & out_womask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6117 = ~out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6118 = ~out_wimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6119 = ~out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6120 = ~out_womask_606; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_512 = {hi_362, flags_0_go, _out_prepend_T_512}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6121 = out_prepend_512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6122 = _out_T_6121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_513 = _out_T_6122; // @[RegisterRouter.scala:87:24] wire out_rimask_607 = \|_out_rimask_T_607; // @[RegisterRouter.scala:87:24] wire out_wimask_607 = &_out_wimask_T_607; // @[RegisterRouter.scala:87:24] wire out_romask_607 = \|_out_romask_T_607; // @[RegisterRouter.scala:87:24] wire out_womask_607 = &_out_womask_T_607; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_607 = out_rivalid_1_461 & out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6124 = out_f_rivalid_607; // @[RegisterRouter.scala:87:24] wire out_f_roready_607 = out_roready_1_461 & out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6125 = out_f_roready_607; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_607 = out_wivalid_1_461 & out_wimask_607; // @[RegisterRouter.scala:87:24] wire out_f_woready_607 = out_woready_1_461 & out_womask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6126 = ~out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6127 = ~out_wimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6128 = ~out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6129 = ~out_womask_607; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_513 = {hi_363, flags_0_go, _out_prepend_T_513}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6130 = out_prepend_513; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6131 = _out_T_6130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_514 = _out_T_6131; // @[RegisterRouter.scala:87:24] wire out_rimask_608 = \|_out_rimask_T_608; // @[RegisterRouter.scala:87:24] wire out_wimask_608 = &_out_wimask_T_608; // @[RegisterRouter.scala:87:24] wire out_romask_608 = \|_out_romask_T_608; // @[RegisterRouter.scala:87:24] wire out_womask_608 = &_out_womask_T_608; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_608 = out_rivalid_1_462 & out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6133 = out_f_rivalid_608; // @[RegisterRouter.scala:87:24] wire out_f_roready_608 = out_roready_1_462 & out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6134 = out_f_roready_608; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_608 = out_wivalid_1_462 & out_wimask_608; // @[RegisterRouter.scala:87:24] wire out_f_woready_608 = out_woready_1_462 & out_womask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6135 = ~out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6136 = ~out_wimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6137 = ~out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6138 = ~out_womask_608; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_514 = {hi_364, flags_0_go, _out_prepend_T_514}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6139 = out_prepend_514; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6140 = _out_T_6139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_515 = _out_T_6140; // @[RegisterRouter.scala:87:24] wire out_rimask_609 = \|_out_rimask_T_609; // @[RegisterRouter.scala:87:24] wire out_wimask_609 = &_out_wimask_T_609; // @[RegisterRouter.scala:87:24] wire out_romask_609 = \|_out_romask_T_609; // @[RegisterRouter.scala:87:24] wire out_womask_609 = &_out_womask_T_609; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_609 = out_rivalid_1_463 & out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6142 = out_f_rivalid_609; // @[RegisterRouter.scala:87:24] wire out_f_roready_609 = out_roready_1_463 & out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6143 = out_f_roready_609; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_609 = out_wivalid_1_463 & out_wimask_609; // @[RegisterRouter.scala:87:24] wire out_f_woready_609 = out_woready_1_463 & out_womask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6144 = ~out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6145 = ~out_wimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6146 = ~out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6147 = ~out_womask_609; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_515 = {hi_365, flags_0_go, _out_prepend_T_515}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6148 = out_prepend_515; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6149 = _out_T_6148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_516 = _out_T_6149; // @[RegisterRouter.scala:87:24] wire out_rimask_610 = \|_out_rimask_T_610; // @[RegisterRouter.scala:87:24] wire out_wimask_610 = &_out_wimask_T_610; // @[RegisterRouter.scala:87:24] wire out_romask_610 = \|_out_romask_T_610; // @[RegisterRouter.scala:87:24] wire out_womask_610 = &_out_womask_T_610; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_610 = out_rivalid_1_464 & out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6151 = out_f_rivalid_610; // @[RegisterRouter.scala:87:24] wire out_f_roready_610 = out_roready_1_464 & out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6152 = out_f_roready_610; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_610 = out_wivalid_1_464 & out_wimask_610; // @[RegisterRouter.scala:87:24] wire out_f_woready_610 = out_woready_1_464 & out_womask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6153 = ~out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6154 = ~out_wimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6155 = ~out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6156 = ~out_womask_610; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_516 = {hi_366, flags_0_go, _out_prepend_T_516}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6157 = out_prepend_516; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6158 = _out_T_6157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_517 = _out_T_6158; // @[RegisterRouter.scala:87:24] wire out_rimask_611 = \|_out_rimask_T_611; // @[RegisterRouter.scala:87:24] wire out_wimask_611 = &_out_wimask_T_611; // @[RegisterRouter.scala:87:24] wire out_romask_611 = \|_out_romask_T_611; // @[RegisterRouter.scala:87:24] wire out_womask_611 = &_out_womask_T_611; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_611 = out_rivalid_1_465 & out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6160 = out_f_rivalid_611; // @[RegisterRouter.scala:87:24] wire out_f_roready_611 = out_roready_1_465 & out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6161 = out_f_roready_611; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_611 = out_wivalid_1_465 & out_wimask_611; // @[RegisterRouter.scala:87:24] wire out_f_woready_611 = out_woready_1_465 & out_womask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6162 = ~out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6163 = ~out_wimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6164 = ~out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6165 = ~out_womask_611; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_517 = {hi_367, flags_0_go, _out_prepend_T_517}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6166 = out_prepend_517; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6167 = _out_T_6166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_518 = _out_T_6167; // @[RegisterRouter.scala:87:24] wire out_rimask_612 = \|_out_rimask_T_612; // @[RegisterRouter.scala:87:24] wire out_wimask_612 = &_out_wimask_T_612; // @[RegisterRouter.scala:87:24] wire out_romask_612 = \|_out_romask_T_612; // @[RegisterRouter.scala:87:24] wire out_womask_612 = &_out_womask_T_612; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_612 = out_rivalid_1_466 & out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6169 = out_f_rivalid_612; // @[RegisterRouter.scala:87:24] wire out_f_roready_612 = out_roready_1_466 & out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6170 = out_f_roready_612; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_612 = out_wivalid_1_466 & out_wimask_612; // @[RegisterRouter.scala:87:24] wire out_f_woready_612 = out_woready_1_466 & out_womask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6171 = ~out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6172 = ~out_wimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6173 = ~out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6174 = ~out_womask_612; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_518 = {hi_368, flags_0_go, _out_prepend_T_518}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6175 = out_prepend_518; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6176 = _out_T_6175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_173 = _out_T_6176; // @[MuxLiteral.scala:49:48] wire out_rimask_613 = \|_out_rimask_T_613; // @[RegisterRouter.scala:87:24] wire out_wimask_613 = &_out_wimask_T_613; // @[RegisterRouter.scala:87:24] wire out_romask_613 = \|_out_romask_T_613; // @[RegisterRouter.scala:87:24] wire out_womask_613 = &_out_womask_T_613; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_613 = out_rivalid_1_467 & out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6178 = out_f_rivalid_613; // @[RegisterRouter.scala:87:24] wire out_f_roready_613 = out_roready_1_467 & out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6179 = out_f_roready_613; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_613 = out_wivalid_1_467 & out_wimask_613; // @[RegisterRouter.scala:87:24] wire out_f_woready_613 = out_woready_1_467 & out_womask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6180 = ~out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6181 = ~out_wimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6182 = ~out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6183 = ~out_womask_613; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6185 = _out_T_6184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_519 = _out_T_6185; // @[RegisterRouter.scala:87:24] wire out_rimask_614 = \|_out_rimask_T_614; // @[RegisterRouter.scala:87:24] wire out_wimask_614 = &_out_wimask_T_614; // @[RegisterRouter.scala:87:24] wire out_romask_614 = \|_out_romask_T_614; // @[RegisterRouter.scala:87:24] wire out_womask_614 = &_out_womask_T_614; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_614 = out_rivalid_1_468 & out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6187 = out_f_rivalid_614; // @[RegisterRouter.scala:87:24] wire out_f_roready_614 = out_roready_1_468 & out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6188 = out_f_roready_614; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_614 = out_wivalid_1_468 & out_wimask_614; // @[RegisterRouter.scala:87:24] wire out_f_woready_614 = out_woready_1_468 & out_womask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6189 = ~out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6190 = ~out_wimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6191 = ~out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6192 = ~out_womask_614; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_519 = {hi_10, flags_0_go, _out_prepend_T_519}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6193 = out_prepend_519; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6194 = _out_T_6193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_520 = _out_T_6194; // @[RegisterRouter.scala:87:24] wire out_rimask_615 = \|_out_rimask_T_615; // @[RegisterRouter.scala:87:24] wire out_wimask_615 = &_out_wimask_T_615; // @[RegisterRouter.scala:87:24] wire out_romask_615 = \|_out_romask_T_615; // @[RegisterRouter.scala:87:24] wire out_womask_615 = &_out_womask_T_615; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_615 = out_rivalid_1_469 & out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6196 = out_f_rivalid_615; // @[RegisterRouter.scala:87:24] wire out_f_roready_615 = out_roready_1_469 & out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6197 = out_f_roready_615; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_615 = out_wivalid_1_469 & out_wimask_615; // @[RegisterRouter.scala:87:24] wire out_f_woready_615 = out_woready_1_469 & out_womask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6198 = ~out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6199 = ~out_wimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6200 = ~out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6201 = ~out_womask_615; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_520 = {hi_11, flags_0_go, _out_prepend_T_520}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6202 = out_prepend_520; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6203 = _out_T_6202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_521 = _out_T_6203; // @[RegisterRouter.scala:87:24] wire out_rimask_616 = \|_out_rimask_T_616; // @[RegisterRouter.scala:87:24] wire out_wimask_616 = &_out_wimask_T_616; // @[RegisterRouter.scala:87:24] wire out_romask_616 = \|_out_romask_T_616; // @[RegisterRouter.scala:87:24] wire out_womask_616 = &_out_womask_T_616; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_616 = out_rivalid_1_470 & out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6205 = out_f_rivalid_616; // @[RegisterRouter.scala:87:24] wire out_f_roready_616 = out_roready_1_470 & out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6206 = out_f_roready_616; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_616 = out_wivalid_1_470 & out_wimask_616; // @[RegisterRouter.scala:87:24] wire out_f_woready_616 = out_woready_1_470 & out_womask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6207 = ~out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6208 = ~out_wimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6209 = ~out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6210 = ~out_womask_616; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_521 = {hi_12, flags_0_go, _out_prepend_T_521}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6211 = out_prepend_521; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6212 = _out_T_6211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_522 = _out_T_6212; // @[RegisterRouter.scala:87:24] wire out_rimask_617 = \|_out_rimask_T_617; // @[RegisterRouter.scala:87:24] wire out_wimask_617 = &_out_wimask_T_617; // @[RegisterRouter.scala:87:24] wire out_romask_617 = \|_out_romask_T_617; // @[RegisterRouter.scala:87:24] wire out_womask_617 = &_out_womask_T_617; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_617 = out_rivalid_1_471 & out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6214 = out_f_rivalid_617; // @[RegisterRouter.scala:87:24] wire out_f_roready_617 = out_roready_1_471 & out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6215 = out_f_roready_617; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_617 = out_wivalid_1_471 & out_wimask_617; // @[RegisterRouter.scala:87:24] wire out_f_woready_617 = out_woready_1_471 & out_womask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6216 = ~out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6217 = ~out_wimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6218 = ~out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6219 = ~out_womask_617; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_522 = {hi_13, flags_0_go, _out_prepend_T_522}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6220 = out_prepend_522; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6221 = _out_T_6220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_523 = _out_T_6221; // @[RegisterRouter.scala:87:24] wire out_rimask_618 = \|_out_rimask_T_618; // @[RegisterRouter.scala:87:24] wire out_wimask_618 = &_out_wimask_T_618; // @[RegisterRouter.scala:87:24] wire out_romask_618 = \|_out_romask_T_618; // @[RegisterRouter.scala:87:24] wire out_womask_618 = &_out_womask_T_618; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_618 = out_rivalid_1_472 & out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6223 = out_f_rivalid_618; // @[RegisterRouter.scala:87:24] wire out_f_roready_618 = out_roready_1_472 & out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6224 = out_f_roready_618; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_618 = out_wivalid_1_472 & out_wimask_618; // @[RegisterRouter.scala:87:24] wire out_f_woready_618 = out_woready_1_472 & out_womask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6225 = ~out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6226 = ~out_wimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6227 = ~out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6228 = ~out_womask_618; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_523 = {hi_14, flags_0_go, _out_prepend_T_523}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6229 = out_prepend_523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6230 = _out_T_6229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_524 = _out_T_6230; // @[RegisterRouter.scala:87:24] wire out_rimask_619 = \|_out_rimask_T_619; // @[RegisterRouter.scala:87:24] wire out_wimask_619 = &_out_wimask_T_619; // @[RegisterRouter.scala:87:24] wire out_romask_619 = \|_out_romask_T_619; // @[RegisterRouter.scala:87:24] wire out_womask_619 = &_out_womask_T_619; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_619 = out_rivalid_1_473 & out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6232 = out_f_rivalid_619; // @[RegisterRouter.scala:87:24] wire out_f_roready_619 = out_roready_1_473 & out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6233 = out_f_roready_619; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_619 = out_wivalid_1_473 & out_wimask_619; // @[RegisterRouter.scala:87:24] wire out_f_woready_619 = out_woready_1_473 & out_womask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6234 = ~out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6235 = ~out_wimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6236 = ~out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6237 = ~out_womask_619; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_524 = {hi_15, flags_0_go, _out_prepend_T_524}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6238 = out_prepend_524; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6239 = _out_T_6238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_525 = _out_T_6239; // @[RegisterRouter.scala:87:24] wire out_rimask_620 = \|_out_rimask_T_620; // @[RegisterRouter.scala:87:24] wire out_wimask_620 = &_out_wimask_T_620; // @[RegisterRouter.scala:87:24] wire out_romask_620 = \|_out_romask_T_620; // @[RegisterRouter.scala:87:24] wire out_womask_620 = &_out_womask_T_620; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_620 = out_rivalid_1_474 & out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6241 = out_f_rivalid_620; // @[RegisterRouter.scala:87:24] wire out_f_roready_620 = out_roready_1_474 & out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6242 = out_f_roready_620; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_620 = out_wivalid_1_474 & out_wimask_620; // @[RegisterRouter.scala:87:24] wire out_f_woready_620 = out_woready_1_474 & out_womask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6243 = ~out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6244 = ~out_wimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6245 = ~out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6246 = ~out_womask_620; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_525 = {hi_16, flags_0_go, _out_prepend_T_525}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6247 = out_prepend_525; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6248 = _out_T_6247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_129 = _out_T_6248; // @[MuxLiteral.scala:49:48] wire out_rimask_621 = \|_out_rimask_T_621; // @[RegisterRouter.scala:87:24] wire out_wimask_621 = &_out_wimask_T_621; // @[RegisterRouter.scala:87:24] wire out_romask_621 = \|_out_romask_T_621; // @[RegisterRouter.scala:87:24] wire out_womask_621 = &_out_womask_T_621; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_621 = out_rivalid_1_475 & out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6250 = out_f_rivalid_621; // @[RegisterRouter.scala:87:24] wire out_f_roready_621 = out_roready_1_475 & out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6251 = out_f_roready_621; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_621 = out_wivalid_1_475 & out_wimask_621; // @[RegisterRouter.scala:87:24] wire out_f_woready_621 = out_woready_1_475 & out_womask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6252 = ~out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6253 = ~out_wimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6254 = ~out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6255 = ~out_womask_621; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6257 = _out_T_6256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_526 = _out_T_6257; // @[RegisterRouter.scala:87:24] wire out_rimask_622 = \|_out_rimask_T_622; // @[RegisterRouter.scala:87:24] wire out_wimask_622 = &_out_wimask_T_622; // @[RegisterRouter.scala:87:24] wire out_romask_622 = \|_out_romask_T_622; // @[RegisterRouter.scala:87:24] wire out_womask_622 = &_out_womask_T_622; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_622 = out_rivalid_1_476 & out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6259 = out_f_rivalid_622; // @[RegisterRouter.scala:87:24] wire out_f_roready_622 = out_roready_1_476 & out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6260 = out_f_roready_622; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_622 = out_wivalid_1_476 & out_wimask_622; // @[RegisterRouter.scala:87:24] wire out_f_woready_622 = out_woready_1_476 & out_womask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6261 = ~out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6262 = ~out_wimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6263 = ~out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6264 = ~out_womask_622; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_526 = {hi_50, flags_0_go, _out_prepend_T_526}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6265 = out_prepend_526; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6266 = _out_T_6265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_527 = _out_T_6266; // @[RegisterRouter.scala:87:24] wire out_rimask_623 = \|_out_rimask_T_623; // @[RegisterRouter.scala:87:24] wire out_wimask_623 = &_out_wimask_T_623; // @[RegisterRouter.scala:87:24] wire out_romask_623 = \|_out_romask_T_623; // @[RegisterRouter.scala:87:24] wire out_womask_623 = &_out_womask_T_623; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_623 = out_rivalid_1_477 & out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6268 = out_f_rivalid_623; // @[RegisterRouter.scala:87:24] wire out_f_roready_623 = out_roready_1_477 & out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6269 = out_f_roready_623; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_623 = out_wivalid_1_477 & out_wimask_623; // @[RegisterRouter.scala:87:24] wire out_f_woready_623 = out_woready_1_477 & out_womask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6270 = ~out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6271 = ~out_wimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6272 = ~out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6273 = ~out_womask_623; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_527 = {hi_51, flags_0_go, _out_prepend_T_527}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6274 = out_prepend_527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6275 = _out_T_6274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_528 = _out_T_6275; // @[RegisterRouter.scala:87:24] wire out_rimask_624 = \|_out_rimask_T_624; // @[RegisterRouter.scala:87:24] wire out_wimask_624 = &_out_wimask_T_624; // @[RegisterRouter.scala:87:24] wire out_romask_624 = \|_out_romask_T_624; // @[RegisterRouter.scala:87:24] wire out_womask_624 = &_out_womask_T_624; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_624 = out_rivalid_1_478 & out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6277 = out_f_rivalid_624; // @[RegisterRouter.scala:87:24] wire out_f_roready_624 = out_roready_1_478 & out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6278 = out_f_roready_624; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_624 = out_wivalid_1_478 & out_wimask_624; // @[RegisterRouter.scala:87:24] wire out_f_woready_624 = out_woready_1_478 & out_womask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6279 = ~out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6280 = ~out_wimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6281 = ~out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6282 = ~out_womask_624; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_528 = {hi_52, flags_0_go, _out_prepend_T_528}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6283 = out_prepend_528; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6284 = _out_T_6283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_529 = _out_T_6284; // @[RegisterRouter.scala:87:24] wire out_rimask_625 = \|_out_rimask_T_625; // @[RegisterRouter.scala:87:24] wire out_wimask_625 = &_out_wimask_T_625; // @[RegisterRouter.scala:87:24] wire out_romask_625 = \|_out_romask_T_625; // @[RegisterRouter.scala:87:24] wire out_womask_625 = &_out_womask_T_625; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_625 = out_rivalid_1_479 & out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6286 = out_f_rivalid_625; // @[RegisterRouter.scala:87:24] wire out_f_roready_625 = out_roready_1_479 & out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6287 = out_f_roready_625; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_625 = out_wivalid_1_479 & out_wimask_625; // @[RegisterRouter.scala:87:24] wire out_f_woready_625 = out_woready_1_479 & out_womask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6288 = ~out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6289 = ~out_wimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6290 = ~out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6291 = ~out_womask_625; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_529 = {hi_53, flags_0_go, _out_prepend_T_529}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6292 = out_prepend_529; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6293 = _out_T_6292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_530 = _out_T_6293; // @[RegisterRouter.scala:87:24] wire out_rimask_626 = \|_out_rimask_T_626; // @[RegisterRouter.scala:87:24] wire out_wimask_626 = &_out_wimask_T_626; // @[RegisterRouter.scala:87:24] wire out_romask_626 = \|_out_romask_T_626; // @[RegisterRouter.scala:87:24] wire out_womask_626 = &_out_womask_T_626; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_626 = out_rivalid_1_480 & out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6295 = out_f_rivalid_626; // @[RegisterRouter.scala:87:24] wire out_f_roready_626 = out_roready_1_480 & out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6296 = out_f_roready_626; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_626 = out_wivalid_1_480 & out_wimask_626; // @[RegisterRouter.scala:87:24] wire out_f_woready_626 = out_woready_1_480 & out_womask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6297 = ~out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6298 = ~out_wimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6299 = ~out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6300 = ~out_womask_626; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_530 = {hi_54, flags_0_go, _out_prepend_T_530}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6301 = out_prepend_530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6302 = _out_T_6301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_531 = _out_T_6302; // @[RegisterRouter.scala:87:24] wire out_rimask_627 = \|_out_rimask_T_627; // @[RegisterRouter.scala:87:24] wire out_wimask_627 = &_out_wimask_T_627; // @[RegisterRouter.scala:87:24] wire out_romask_627 = \|_out_romask_T_627; // @[RegisterRouter.scala:87:24] wire out_womask_627 = &_out_womask_T_627; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_627 = out_rivalid_1_481 & out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6304 = out_f_rivalid_627; // @[RegisterRouter.scala:87:24] wire out_f_roready_627 = out_roready_1_481 & out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6305 = out_f_roready_627; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_627 = out_wivalid_1_481 & out_wimask_627; // @[RegisterRouter.scala:87:24] wire out_f_woready_627 = out_woready_1_481 & out_womask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6306 = ~out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6307 = ~out_wimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6308 = ~out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6309 = ~out_womask_627; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_531 = {hi_55, flags_0_go, _out_prepend_T_531}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6310 = out_prepend_531; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6311 = _out_T_6310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_532 = _out_T_6311; // @[RegisterRouter.scala:87:24] wire out_rimask_628 = \|_out_rimask_T_628; // @[RegisterRouter.scala:87:24] wire out_wimask_628 = &_out_wimask_T_628; // @[RegisterRouter.scala:87:24] wire out_romask_628 = \|_out_romask_T_628; // @[RegisterRouter.scala:87:24] wire out_womask_628 = &_out_womask_T_628; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_628 = out_rivalid_1_482 & out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6313 = out_f_rivalid_628; // @[RegisterRouter.scala:87:24] wire out_f_roready_628 = out_roready_1_482 & out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6314 = out_f_roready_628; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_628 = out_wivalid_1_482 & out_wimask_628; // @[RegisterRouter.scala:87:24] wire out_f_woready_628 = out_woready_1_482 & out_womask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6315 = ~out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6316 = ~out_wimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6317 = ~out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6318 = ~out_womask_628; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_532 = {hi_56, flags_0_go, _out_prepend_T_532}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6319 = out_prepend_532; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6320 = _out_T_6319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_134 = _out_T_6320; // @[MuxLiteral.scala:49:48] wire out_rimask_629 = \|_out_rimask_T_629; // @[RegisterRouter.scala:87:24] wire out_wimask_629 = &_out_wimask_T_629; // @[RegisterRouter.scala:87:24] wire out_romask_629 = \|_out_romask_T_629; // @[RegisterRouter.scala:87:24] wire out_womask_629 = &_out_womask_T_629; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_629 = out_rivalid_1_483 & out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6322 = out_f_rivalid_629; // @[RegisterRouter.scala:87:24] wire out_f_roready_629 = out_roready_1_483 & out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6323 = out_f_roready_629; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_629 = out_wivalid_1_483 & out_wimask_629; // @[RegisterRouter.scala:87:24] wire out_f_woready_629 = out_woready_1_483 & out_womask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6324 = ~out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6325 = ~out_wimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6326 = ~out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6327 = ~out_womask_629; // @[RegisterRouter.scala:87:24] wire out_rimask_630 = \|_out_rimask_T_630; // @[RegisterRouter.scala:87:24] wire out_wimask_630 = &_out_wimask_T_630; // @[RegisterRouter.scala:87:24] wire out_romask_630 = \|_out_romask_T_630; // @[RegisterRouter.scala:87:24] wire out_womask_630 = &_out_womask_T_630; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_630 = out_rivalid_1_484 & out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6331 = out_f_rivalid_630; // @[RegisterRouter.scala:87:24] wire out_f_roready_630 = out_roready_1_484 & out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6332 = out_f_roready_630; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_630 = out_wivalid_1_484 & out_wimask_630; // @[RegisterRouter.scala:87:24] wire out_f_woready_630 = out_woready_1_484 & out_womask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6333 = ~out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6334 = ~out_wimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6335 = ~out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6336 = ~out_womask_630; // @[RegisterRouter.scala:87:24] wire out_rimask_631 = \|_out_rimask_T_631; // @[RegisterRouter.scala:87:24] wire out_wimask_631 = &_out_wimask_T_631; // @[RegisterRouter.scala:87:24] wire out_romask_631 = \|_out_romask_T_631; // @[RegisterRouter.scala:87:24] wire out_womask_631 = &_out_womask_T_631; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_631 = out_rivalid_1_485 & out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6340 = out_f_rivalid_631; // @[RegisterRouter.scala:87:24] wire out_f_roready_631 = out_roready_1_485 & out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6341 = out_f_roready_631; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_631 = out_wivalid_1_485 & out_wimask_631; // @[RegisterRouter.scala:87:24] wire out_f_woready_631 = out_woready_1_485 & out_womask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6342 = ~out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6343 = ~out_wimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6344 = ~out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6345 = ~out_womask_631; // @[RegisterRouter.scala:87:24] wire out_rimask_632 = \|_out_rimask_T_632; // @[RegisterRouter.scala:87:24] wire out_wimask_632 = &_out_wimask_T_632; // @[RegisterRouter.scala:87:24] wire out_romask_632 = \|_out_romask_T_632; // @[RegisterRouter.scala:87:24] wire out_womask_632 = &_out_womask_T_632; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_632 = out_rivalid_1_486 & out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6349 = out_f_rivalid_632; // @[RegisterRouter.scala:87:24] wire out_f_roready_632 = out_roready_1_486 & out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6350 = out_f_roready_632; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_632 = out_wivalid_1_486 & out_wimask_632; // @[RegisterRouter.scala:87:24] wire out_f_woready_632 = out_woready_1_486 & out_womask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6351 = ~out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6352 = ~out_wimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6353 = ~out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6354 = ~out_womask_632; // @[RegisterRouter.scala:87:24] wire out_rimask_633 = \|_out_rimask_T_633; // @[RegisterRouter.scala:87:24] wire out_wimask_633 = &_out_wimask_T_633; // @[RegisterRouter.scala:87:24] wire out_romask_633 = \|_out_romask_T_633; // @[RegisterRouter.scala:87:24] wire out_womask_633 = &_out_womask_T_633; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_633 = out_rivalid_1_487 & out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6358 = out_f_rivalid_633; // @[RegisterRouter.scala:87:24] wire out_f_roready_633 = out_roready_1_487 & out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6359 = out_f_roready_633; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_633 = out_wivalid_1_487 & out_wimask_633; // @[RegisterRouter.scala:87:24] wire out_f_woready_633 = out_woready_1_487 & out_womask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6360 = ~out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6361 = ~out_wimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6362 = ~out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6363 = ~out_womask_633; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6365 = _out_T_6364; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_536 = _out_T_6365; // @[RegisterRouter.scala:87:24] wire out_rimask_634 = \|_out_rimask_T_634; // @[RegisterRouter.scala:87:24] wire out_wimask_634 = &_out_wimask_T_634; // @[RegisterRouter.scala:87:24] wire out_romask_634 = \|_out_romask_T_634; // @[RegisterRouter.scala:87:24] wire out_womask_634 = &_out_womask_T_634; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_634 = out_rivalid_1_488 & out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6367 = out_f_rivalid_634; // @[RegisterRouter.scala:87:24] wire out_f_roready_634 = out_roready_1_488 & out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6368 = out_f_roready_634; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_634 = out_wivalid_1_488 & out_wimask_634; // @[RegisterRouter.scala:87:24] wire out_f_woready_634 = out_woready_1_488 & out_womask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6369 = ~out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6370 = ~out_wimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6371 = ~out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6372 = ~out_womask_634; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_536 = {hi_618, flags_0_go, _out_prepend_T_536}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6373 = out_prepend_536; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6374 = _out_T_6373; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_537 = _out_T_6374; // @[RegisterRouter.scala:87:24] wire out_rimask_635 = \|_out_rimask_T_635; // @[RegisterRouter.scala:87:24] wire out_wimask_635 = &_out_wimask_T_635; // @[RegisterRouter.scala:87:24] wire out_romask_635 = \|_out_romask_T_635; // @[RegisterRouter.scala:87:24] wire out_womask_635 = &_out_womask_T_635; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_635 = out_rivalid_1_489 & out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6376 = out_f_rivalid_635; // @[RegisterRouter.scala:87:24] wire out_f_roready_635 = out_roready_1_489 & out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6377 = out_f_roready_635; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_635 = out_wivalid_1_489 & out_wimask_635; // @[RegisterRouter.scala:87:24] wire out_f_woready_635 = out_woready_1_489 & out_womask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6378 = ~out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6379 = ~out_wimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6380 = ~out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6381 = ~out_womask_635; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_537 = {hi_619, flags_0_go, _out_prepend_T_537}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6382 = out_prepend_537; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6383 = _out_T_6382; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_538 = _out_T_6383; // @[RegisterRouter.scala:87:24] wire out_rimask_636 = \|_out_rimask_T_636; // @[RegisterRouter.scala:87:24] wire out_wimask_636 = &_out_wimask_T_636; // @[RegisterRouter.scala:87:24] wire out_romask_636 = \|_out_romask_T_636; // @[RegisterRouter.scala:87:24] wire out_womask_636 = &_out_womask_T_636; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_636 = out_rivalid_1_490 & out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6385 = out_f_rivalid_636; // @[RegisterRouter.scala:87:24] wire out_f_roready_636 = out_roready_1_490 & out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6386 = out_f_roready_636; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_636 = out_wivalid_1_490 & out_wimask_636; // @[RegisterRouter.scala:87:24] wire out_f_woready_636 = out_woready_1_490 & out_womask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6387 = ~out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6388 = ~out_wimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6389 = ~out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6390 = ~out_womask_636; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_538 = {hi_620, flags_0_go, _out_prepend_T_538}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6391 = out_prepend_538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6392 = _out_T_6391; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_539 = _out_T_6392; // @[RegisterRouter.scala:87:24] wire out_rimask_637 = \|_out_rimask_T_637; // @[RegisterRouter.scala:87:24] wire out_wimask_637 = &_out_wimask_T_637; // @[RegisterRouter.scala:87:24] wire out_romask_637 = \|_out_romask_T_637; // @[RegisterRouter.scala:87:24] wire out_womask_637 = &_out_womask_T_637; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_637 = out_rivalid_1_491 & out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6394 = out_f_rivalid_637; // @[RegisterRouter.scala:87:24] wire out_f_roready_637 = out_roready_1_491 & out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6395 = out_f_roready_637; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_637 = out_wivalid_1_491 & out_wimask_637; // @[RegisterRouter.scala:87:24] wire out_f_woready_637 = out_woready_1_491 & out_womask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6396 = ~out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6397 = ~out_wimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6398 = ~out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6399 = ~out_womask_637; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_539 = {hi_621, flags_0_go, _out_prepend_T_539}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6400 = out_prepend_539; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6401 = _out_T_6400; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_540 = _out_T_6401; // @[RegisterRouter.scala:87:24] wire out_rimask_638 = \|_out_rimask_T_638; // @[RegisterRouter.scala:87:24] wire out_wimask_638 = &_out_wimask_T_638; // @[RegisterRouter.scala:87:24] wire out_romask_638 = \|_out_romask_T_638; // @[RegisterRouter.scala:87:24] wire out_womask_638 = &_out_womask_T_638; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_638 = out_rivalid_1_492 & out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6403 = out_f_rivalid_638; // @[RegisterRouter.scala:87:24] wire out_f_roready_638 = out_roready_1_492 & out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6404 = out_f_roready_638; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_638 = out_wivalid_1_492 & out_wimask_638; // @[RegisterRouter.scala:87:24] wire out_f_woready_638 = out_woready_1_492 & out_womask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6405 = ~out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6406 = ~out_wimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6407 = ~out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6408 = ~out_womask_638; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_540 = {hi_622, flags_0_go, _out_prepend_T_540}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6409 = out_prepend_540; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6410 = _out_T_6409; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_541 = _out_T_6410; // @[RegisterRouter.scala:87:24] wire out_rimask_639 = \|_out_rimask_T_639; // @[RegisterRouter.scala:87:24] wire out_wimask_639 = &_out_wimask_T_639; // @[RegisterRouter.scala:87:24] wire out_romask_639 = \|_out_romask_T_639; // @[RegisterRouter.scala:87:24] wire out_womask_639 = &_out_womask_T_639; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_639 = out_rivalid_1_493 & out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6412 = out_f_rivalid_639; // @[RegisterRouter.scala:87:24] wire out_f_roready_639 = out_roready_1_493 & out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6413 = out_f_roready_639; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_639 = out_wivalid_1_493 & out_wimask_639; // @[RegisterRouter.scala:87:24] wire out_f_woready_639 = out_woready_1_493 & out_womask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6414 = ~out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6415 = ~out_wimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6416 = ~out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6417 = ~out_womask_639; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_541 = {hi_623, flags_0_go, _out_prepend_T_541}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6418 = out_prepend_541; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6419 = _out_T_6418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_542 = _out_T_6419; // @[RegisterRouter.scala:87:24] wire out_rimask_640 = \|_out_rimask_T_640; // @[RegisterRouter.scala:87:24] wire out_wimask_640 = &_out_wimask_T_640; // @[RegisterRouter.scala:87:24] wire out_romask_640 = \|_out_romask_T_640; // @[RegisterRouter.scala:87:24] wire out_womask_640 = &_out_womask_T_640; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_640 = out_rivalid_1_494 & out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6421 = out_f_rivalid_640; // @[RegisterRouter.scala:87:24] wire out_f_roready_640 = out_roready_1_494 & out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6422 = out_f_roready_640; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_640 = out_wivalid_1_494 & out_wimask_640; // @[RegisterRouter.scala:87:24] wire out_f_woready_640 = out_woready_1_494 & out_womask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6423 = ~out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6424 = ~out_wimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6425 = ~out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6426 = ~out_womask_640; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_542 = {hi_624, flags_0_go, _out_prepend_T_542}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6427 = out_prepend_542; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6428 = _out_T_6427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_205 = _out_T_6428; // @[MuxLiteral.scala:49:48] wire out_rimask_641 = \|_out_rimask_T_641; // @[RegisterRouter.scala:87:24] wire out_wimask_641 = &_out_wimask_T_641; // @[RegisterRouter.scala:87:24] wire out_romask_641 = \|_out_romask_T_641; // @[RegisterRouter.scala:87:24] wire out_womask_641 = &_out_womask_T_641; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_641 = out_rivalid_1_495 & out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6430 = out_f_rivalid_641; // @[RegisterRouter.scala:87:24] wire out_f_roready_641 = out_roready_1_495 & out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6431 = out_f_roready_641; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_641 = out_wivalid_1_495 & out_wimask_641; // @[RegisterRouter.scala:87:24] wire out_f_woready_641 = out_woready_1_495 & out_womask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6432 = ~out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6433 = ~out_wimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6434 = ~out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6435 = ~out_womask_641; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6437 = _out_T_6436; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_543 = _out_T_6437; // @[RegisterRouter.scala:87:24] wire out_rimask_642 = \|_out_rimask_T_642; // @[RegisterRouter.scala:87:24] wire out_wimask_642 = &_out_wimask_T_642; // @[RegisterRouter.scala:87:24] wire out_romask_642 = \|_out_romask_T_642; // @[RegisterRouter.scala:87:24] wire out_womask_642 = &_out_womask_T_642; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_642 = out_rivalid_1_496 & out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6439 = out_f_rivalid_642; // @[RegisterRouter.scala:87:24] wire out_f_roready_642 = out_roready_1_496 & out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6440 = out_f_roready_642; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_642 = out_wivalid_1_496 & out_wimask_642; // @[RegisterRouter.scala:87:24] wire out_f_woready_642 = out_woready_1_496 & out_womask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6441 = ~out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6442 = ~out_wimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6443 = ~out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6444 = ~out_womask_642; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_543 = {hi_2, flags_0_go, _out_prepend_T_543}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6445 = out_prepend_543; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6446 = _out_T_6445; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_544 = _out_T_6446; // @[RegisterRouter.scala:87:24] wire out_rimask_643 = \|_out_rimask_T_643; // @[RegisterRouter.scala:87:24] wire out_wimask_643 = &_out_wimask_T_643; // @[RegisterRouter.scala:87:24] wire out_romask_643 = \|_out_romask_T_643; // @[RegisterRouter.scala:87:24] wire out_womask_643 = &_out_womask_T_643; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_643 = out_rivalid_1_497 & out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6448 = out_f_rivalid_643; // @[RegisterRouter.scala:87:24] wire out_f_roready_643 = out_roready_1_497 & out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6449 = out_f_roready_643; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_643 = out_wivalid_1_497 & out_wimask_643; // @[RegisterRouter.scala:87:24] wire out_f_woready_643 = out_woready_1_497 & out_womask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6450 = ~out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6451 = ~out_wimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6452 = ~out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6453 = ~out_womask_643; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_544 = {hi_3, flags_0_go, _out_prepend_T_544}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6454 = out_prepend_544; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6455 = _out_T_6454; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_545 = _out_T_6455; // @[RegisterRouter.scala:87:24] wire out_rimask_644 = \|_out_rimask_T_644; // @[RegisterRouter.scala:87:24] wire out_wimask_644 = &_out_wimask_T_644; // @[RegisterRouter.scala:87:24] wire out_romask_644 = \|_out_romask_T_644; // @[RegisterRouter.scala:87:24] wire out_womask_644 = &_out_womask_T_644; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_644 = out_rivalid_1_498 & out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6457 = out_f_rivalid_644; // @[RegisterRouter.scala:87:24] wire out_f_roready_644 = out_roready_1_498 & out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6458 = out_f_roready_644; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_644 = out_wivalid_1_498 & out_wimask_644; // @[RegisterRouter.scala:87:24] wire out_f_woready_644 = out_woready_1_498 & out_womask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6459 = ~out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6460 = ~out_wimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6461 = ~out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6462 = ~out_womask_644; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_545 = {hi_4, flags_0_go, _out_prepend_T_545}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6463 = out_prepend_545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6464 = _out_T_6463; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_546 = _out_T_6464; // @[RegisterRouter.scala:87:24] wire out_rimask_645 = \|_out_rimask_T_645; // @[RegisterRouter.scala:87:24] wire out_wimask_645 = &_out_wimask_T_645; // @[RegisterRouter.scala:87:24] wire out_romask_645 = \|_out_romask_T_645; // @[RegisterRouter.scala:87:24] wire out_womask_645 = &_out_womask_T_645; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_645 = out_rivalid_1_499 & out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6466 = out_f_rivalid_645; // @[RegisterRouter.scala:87:24] wire out_f_roready_645 = out_roready_1_499 & out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6467 = out_f_roready_645; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_645 = out_wivalid_1_499 & out_wimask_645; // @[RegisterRouter.scala:87:24] wire out_f_woready_645 = out_woready_1_499 & out_womask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6468 = ~out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6469 = ~out_wimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6470 = ~out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6471 = ~out_womask_645; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_546 = {hi_5, flags_0_go, _out_prepend_T_546}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6472 = out_prepend_546; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6473 = _out_T_6472; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_547 = _out_T_6473; // @[RegisterRouter.scala:87:24] wire out_rimask_646 = \|_out_rimask_T_646; // @[RegisterRouter.scala:87:24] wire out_wimask_646 = &_out_wimask_T_646; // @[RegisterRouter.scala:87:24] wire out_romask_646 = \|_out_romask_T_646; // @[RegisterRouter.scala:87:24] wire out_womask_646 = &_out_womask_T_646; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_646 = out_rivalid_1_500 & out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6475 = out_f_rivalid_646; // @[RegisterRouter.scala:87:24] wire out_f_roready_646 = out_roready_1_500 & out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6476 = out_f_roready_646; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_646 = out_wivalid_1_500 & out_wimask_646; // @[RegisterRouter.scala:87:24] wire out_f_woready_646 = out_woready_1_500 & out_womask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6477 = ~out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6478 = ~out_wimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6479 = ~out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6480 = ~out_womask_646; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_547 = {hi_6, flags_0_go, _out_prepend_T_547}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6481 = out_prepend_547; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6482 = _out_T_6481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_548 = _out_T_6482; // @[RegisterRouter.scala:87:24] wire out_rimask_647 = \|_out_rimask_T_647; // @[RegisterRouter.scala:87:24] wire out_wimask_647 = &_out_wimask_T_647; // @[RegisterRouter.scala:87:24] wire out_romask_647 = \|_out_romask_T_647; // @[RegisterRouter.scala:87:24] wire out_womask_647 = &_out_womask_T_647; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_647 = out_rivalid_1_501 & out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6484 = out_f_rivalid_647; // @[RegisterRouter.scala:87:24] wire out_f_roready_647 = out_roready_1_501 & out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6485 = out_f_roready_647; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_647 = out_wivalid_1_501 & out_wimask_647; // @[RegisterRouter.scala:87:24] wire out_f_woready_647 = out_woready_1_501 & out_womask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6486 = ~out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6487 = ~out_wimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6488 = ~out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6489 = ~out_womask_647; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_548 = {hi_7, flags_0_go, _out_prepend_T_548}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6490 = out_prepend_548; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6491 = _out_T_6490; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_549 = _out_T_6491; // @[RegisterRouter.scala:87:24] wire out_rimask_648 = \|_out_rimask_T_648; // @[RegisterRouter.scala:87:24] wire out_wimask_648 = &_out_wimask_T_648; // @[RegisterRouter.scala:87:24] wire out_romask_648 = \|_out_romask_T_648; // @[RegisterRouter.scala:87:24] wire out_womask_648 = &_out_womask_T_648; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_648 = out_rivalid_1_502 & out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6493 = out_f_rivalid_648; // @[RegisterRouter.scala:87:24] wire out_f_roready_648 = out_roready_1_502 & out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6494 = out_f_roready_648; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_648 = out_wivalid_1_502 & out_wimask_648; // @[RegisterRouter.scala:87:24] wire out_f_woready_648 = out_woready_1_502 & out_womask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6495 = ~out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6496 = ~out_wimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6497 = ~out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6498 = ~out_womask_648; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_549 = {hi_8, flags_0_go, _out_prepend_T_549}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6499 = out_prepend_549; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6500 = _out_T_6499; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_128 = _out_T_6500; // @[MuxLiteral.scala:49:48] wire out_rimask_649 = \|_out_rimask_T_649; // @[RegisterRouter.scala:87:24] wire out_wimask_649 = &_out_wimask_T_649; // @[RegisterRouter.scala:87:24] wire out_romask_649 = \|_out_romask_T_649; // @[RegisterRouter.scala:87:24] wire out_womask_649 = &_out_womask_T_649; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_649 = out_rivalid_1_503 & out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6502 = out_f_rivalid_649; // @[RegisterRouter.scala:87:24] wire out_f_roready_649 = out_roready_1_503 & out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6503 = out_f_roready_649; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_649 = out_wivalid_1_503 & out_wimask_649; // @[RegisterRouter.scala:87:24] wire out_f_woready_649 = out_woready_1_503 & out_womask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6504 = ~out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6505 = ~out_wimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6506 = ~out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6507 = ~out_womask_649; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6509 = _out_T_6508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_550 = _out_T_6509; // @[RegisterRouter.scala:87:24] wire out_rimask_650 = \|_out_rimask_T_650; // @[RegisterRouter.scala:87:24] wire out_wimask_650 = &_out_wimask_T_650; // @[RegisterRouter.scala:87:24] wire out_romask_650 = \|_out_romask_T_650; // @[RegisterRouter.scala:87:24] wire out_womask_650 = &_out_womask_T_650; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_650 = out_rivalid_1_504 & out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6511 = out_f_rivalid_650; // @[RegisterRouter.scala:87:24] wire out_f_roready_650 = out_roready_1_504 & out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6512 = out_f_roready_650; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_650 = out_wivalid_1_504 & out_wimask_650; // @[RegisterRouter.scala:87:24] wire out_f_woready_650 = out_woready_1_504 & out_womask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6513 = ~out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6514 = ~out_wimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6515 = ~out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6516 = ~out_womask_650; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_550 = {hi_874, flags_0_go, _out_prepend_T_550}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6517 = out_prepend_550; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6518 = _out_T_6517; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_551 = _out_T_6518; // @[RegisterRouter.scala:87:24] wire out_rimask_651 = \|_out_rimask_T_651; // @[RegisterRouter.scala:87:24] wire out_wimask_651 = &_out_wimask_T_651; // @[RegisterRouter.scala:87:24] wire out_romask_651 = \|_out_romask_T_651; // @[RegisterRouter.scala:87:24] wire out_womask_651 = &_out_womask_T_651; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_651 = out_rivalid_1_505 & out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6520 = out_f_rivalid_651; // @[RegisterRouter.scala:87:24] wire out_f_roready_651 = out_roready_1_505 & out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6521 = out_f_roready_651; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_651 = out_wivalid_1_505 & out_wimask_651; // @[RegisterRouter.scala:87:24] wire out_f_woready_651 = out_woready_1_505 & out_womask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6522 = ~out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6523 = ~out_wimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6524 = ~out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6525 = ~out_womask_651; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_551 = {hi_875, flags_0_go, _out_prepend_T_551}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6526 = out_prepend_551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6527 = _out_T_6526; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_552 = _out_T_6527; // @[RegisterRouter.scala:87:24] wire out_rimask_652 = \|_out_rimask_T_652; // @[RegisterRouter.scala:87:24] wire out_wimask_652 = &_out_wimask_T_652; // @[RegisterRouter.scala:87:24] wire out_romask_652 = \|_out_romask_T_652; // @[RegisterRouter.scala:87:24] wire out_womask_652 = &_out_womask_T_652; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_652 = out_rivalid_1_506 & out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6529 = out_f_rivalid_652; // @[RegisterRouter.scala:87:24] wire out_f_roready_652 = out_roready_1_506 & out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6530 = out_f_roready_652; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_652 = out_wivalid_1_506 & out_wimask_652; // @[RegisterRouter.scala:87:24] wire out_f_woready_652 = out_woready_1_506 & out_womask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6531 = ~out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6532 = ~out_wimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6533 = ~out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6534 = ~out_womask_652; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_552 = {hi_876, flags_0_go, _out_prepend_T_552}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6535 = out_prepend_552; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6536 = _out_T_6535; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_553 = _out_T_6536; // @[RegisterRouter.scala:87:24] wire out_rimask_653 = \|_out_rimask_T_653; // @[RegisterRouter.scala:87:24] wire out_wimask_653 = &_out_wimask_T_653; // @[RegisterRouter.scala:87:24] wire out_romask_653 = \|_out_romask_T_653; // @[RegisterRouter.scala:87:24] wire out_womask_653 = &_out_womask_T_653; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_653 = out_rivalid_1_507 & out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6538 = out_f_rivalid_653; // @[RegisterRouter.scala:87:24] wire out_f_roready_653 = out_roready_1_507 & out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6539 = out_f_roready_653; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_653 = out_wivalid_1_507 & out_wimask_653; // @[RegisterRouter.scala:87:24] wire out_f_woready_653 = out_woready_1_507 & out_womask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6540 = ~out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6541 = ~out_wimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6542 = ~out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6543 = ~out_womask_653; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_553 = {hi_877, flags_0_go, _out_prepend_T_553}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6544 = out_prepend_553; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6545 = _out_T_6544; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_554 = _out_T_6545; // @[RegisterRouter.scala:87:24] wire out_rimask_654 = \|_out_rimask_T_654; // @[RegisterRouter.scala:87:24] wire out_wimask_654 = &_out_wimask_T_654; // @[RegisterRouter.scala:87:24] wire out_romask_654 = \|_out_romask_T_654; // @[RegisterRouter.scala:87:24] wire out_womask_654 = &_out_womask_T_654; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_654 = out_rivalid_1_508 & out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6547 = out_f_rivalid_654; // @[RegisterRouter.scala:87:24] wire out_f_roready_654 = out_roready_1_508 & out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6548 = out_f_roready_654; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_654 = out_wivalid_1_508 & out_wimask_654; // @[RegisterRouter.scala:87:24] wire out_f_woready_654 = out_woready_1_508 & out_womask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6549 = ~out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6550 = ~out_wimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6551 = ~out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6552 = ~out_womask_654; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_554 = {hi_878, flags_0_go, _out_prepend_T_554}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6553 = out_prepend_554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6554 = _out_T_6553; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_555 = _out_T_6554; // @[RegisterRouter.scala:87:24] wire out_rimask_655 = \|_out_rimask_T_655; // @[RegisterRouter.scala:87:24] wire out_wimask_655 = &_out_wimask_T_655; // @[RegisterRouter.scala:87:24] wire out_romask_655 = \|_out_romask_T_655; // @[RegisterRouter.scala:87:24] wire out_womask_655 = &_out_womask_T_655; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_655 = out_rivalid_1_509 & out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6556 = out_f_rivalid_655; // @[RegisterRouter.scala:87:24] wire out_f_roready_655 = out_roready_1_509 & out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6557 = out_f_roready_655; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_655 = out_wivalid_1_509 & out_wimask_655; // @[RegisterRouter.scala:87:24] wire out_f_woready_655 = out_woready_1_509 & out_womask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6558 = ~out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6559 = ~out_wimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6560 = ~out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6561 = ~out_womask_655; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_555 = {hi_879, flags_0_go, _out_prepend_T_555}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6562 = out_prepend_555; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6563 = _out_T_6562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_556 = _out_T_6563; // @[RegisterRouter.scala:87:24] wire out_rimask_656 = \|_out_rimask_T_656; // @[RegisterRouter.scala:87:24] wire out_wimask_656 = &_out_wimask_T_656; // @[RegisterRouter.scala:87:24] wire out_romask_656 = \|_out_romask_T_656; // @[RegisterRouter.scala:87:24] wire out_womask_656 = &_out_womask_T_656; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_656 = out_rivalid_1_510 & out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6565 = out_f_rivalid_656; // @[RegisterRouter.scala:87:24] wire out_f_roready_656 = out_roready_1_510 & out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6566 = out_f_roready_656; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_656 = out_wivalid_1_510 & out_wimask_656; // @[RegisterRouter.scala:87:24] wire out_f_woready_656 = out_woready_1_510 & out_womask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6567 = ~out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6568 = ~out_wimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6569 = ~out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6570 = ~out_womask_656; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_556 = {hi_880, flags_0_go, _out_prepend_T_556}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6571 = out_prepend_556; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6572 = _out_T_6571; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_237 = _out_T_6572; // @[MuxLiteral.scala:49:48] wire out_rimask_657 = \|_out_rimask_T_657; // @[RegisterRouter.scala:87:24] wire out_wimask_657 = &_out_wimask_T_657; // @[RegisterRouter.scala:87:24] wire out_romask_657 = \|_out_romask_T_657; // @[RegisterRouter.scala:87:24] wire out_womask_657 = &_out_womask_T_657; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_657 = out_rivalid_1_511 & out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6574 = out_f_rivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_roready_657 = out_roready_1_511 & out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6575 = out_f_roready_657; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_657 = out_wivalid_1_511 & out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6576 = out_f_wivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_woready_657 = out_woready_1_511 & out_womask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6577 = out_f_woready_657; // @[RegisterRouter.scala:87:24] wire _out_T_6578 = ~out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6579 = ~out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6580 = ~out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6581 = ~out_womask_657; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6583 = _out_T_6582; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_557 = _out_T_6583; // @[RegisterRouter.scala:87:24] wire out_rimask_658 = \|_out_rimask_T_658; // @[RegisterRouter.scala:87:24] wire out_wimask_658 = &_out_wimask_T_658; // @[RegisterRouter.scala:87:24] wire out_romask_658 = \|_out_romask_T_658; // @[RegisterRouter.scala:87:24] wire out_womask_658 = &_out_womask_T_658; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_658 = out_rivalid_1_512 & out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6585 = out_f_rivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_roready_658 = out_roready_1_512 & out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6586 = out_f_roready_658; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_658 = out_wivalid_1_512 & out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6587 = out_f_wivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_woready_658 = out_woready_1_512 & out_womask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6588 = out_f_woready_658; // @[RegisterRouter.scala:87:24] wire _out_T_6589 = ~out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6590 = ~out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6591 = ~out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6592 = ~out_womask_658; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_557 = {programBufferMem_9, _out_prepend_T_557}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6593 = out_prepend_557; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6594 = _out_T_6593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_558 = _out_T_6594; // @[RegisterRouter.scala:87:24] wire out_rimask_659 = \|_out_rimask_T_659; // @[RegisterRouter.scala:87:24] wire out_wimask_659 = &_out_wimask_T_659; // @[RegisterRouter.scala:87:24] wire out_romask_659 = \|_out_romask_T_659; // @[RegisterRouter.scala:87:24] wire out_womask_659 = &_out_womask_T_659; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_659 = out_rivalid_1_513 & out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6596 = out_f_rivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_roready_659 = out_roready_1_513 & out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6597 = out_f_roready_659; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_659 = out_wivalid_1_513 & out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6598 = out_f_wivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_woready_659 = out_woready_1_513 & out_womask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6599 = out_f_woready_659; // @[RegisterRouter.scala:87:24] wire _out_T_6600 = ~out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6601 = ~out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6602 = ~out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6603 = ~out_womask_659; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_558 = {programBufferMem_10, _out_prepend_T_558}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6604 = out_prepend_558; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6605 = _out_T_6604; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_559 = _out_T_6605; // @[RegisterRouter.scala:87:24] wire out_rimask_660 = \|_out_rimask_T_660; // @[RegisterRouter.scala:87:24] wire out_wimask_660 = &_out_wimask_T_660; // @[RegisterRouter.scala:87:24] wire out_romask_660 = \|_out_romask_T_660; // @[RegisterRouter.scala:87:24] wire out_womask_660 = &_out_womask_T_660; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_660 = out_rivalid_1_514 & out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6607 = out_f_rivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_roready_660 = out_roready_1_514 & out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6608 = out_f_roready_660; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_660 = out_wivalid_1_514 & out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6609 = out_f_wivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_woready_660 = out_woready_1_514 & out_womask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6610 = out_f_woready_660; // @[RegisterRouter.scala:87:24] wire _out_T_6611 = ~out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6612 = ~out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6613 = ~out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6614 = ~out_womask_660; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_559 = {programBufferMem_11, _out_prepend_T_559}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6615 = out_prepend_559; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6616 = _out_T_6615; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_560 = _out_T_6616; // @[RegisterRouter.scala:87:24] wire out_rimask_661 = \|_out_rimask_T_661; // @[RegisterRouter.scala:87:24] wire out_wimask_661 = &_out_wimask_T_661; // @[RegisterRouter.scala:87:24] wire out_romask_661 = \|_out_romask_T_661; // @[RegisterRouter.scala:87:24] wire out_womask_661 = &_out_womask_T_661; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_661 = out_rivalid_1_515 & out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6618 = out_f_rivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_roready_661 = out_roready_1_515 & out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6619 = out_f_roready_661; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_661 = out_wivalid_1_515 & out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6620 = out_f_wivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_woready_661 = out_woready_1_515 & out_womask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6621 = out_f_woready_661; // @[RegisterRouter.scala:87:24] wire _out_T_6622 = ~out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6623 = ~out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6624 = ~out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6625 = ~out_womask_661; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_560 = {programBufferMem_12, _out_prepend_T_560}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6626 = out_prepend_560; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6627 = _out_T_6626; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_561 = _out_T_6627; // @[RegisterRouter.scala:87:24] wire out_rimask_662 = \|_out_rimask_T_662; // @[RegisterRouter.scala:87:24] wire out_wimask_662 = &_out_wimask_T_662; // @[RegisterRouter.scala:87:24] wire out_romask_662 = \|_out_romask_T_662; // @[RegisterRouter.scala:87:24] wire out_womask_662 = &_out_womask_T_662; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_662 = out_rivalid_1_516 & out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6629 = out_f_rivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_roready_662 = out_roready_1_516 & out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6630 = out_f_roready_662; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_662 = out_wivalid_1_516 & out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6631 = out_f_wivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_woready_662 = out_woready_1_516 & out_womask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6632 = out_f_woready_662; // @[RegisterRouter.scala:87:24] wire _out_T_6633 = ~out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6634 = ~out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6635 = ~out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6636 = ~out_womask_662; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_561 = {programBufferMem_13, _out_prepend_T_561}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6637 = out_prepend_561; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6638 = _out_T_6637; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_562 = _out_T_6638; // @[RegisterRouter.scala:87:24] wire out_rimask_663 = \|_out_rimask_T_663; // @[RegisterRouter.scala:87:24] wire out_wimask_663 = &_out_wimask_T_663; // @[RegisterRouter.scala:87:24] wire out_romask_663 = \|_out_romask_T_663; // @[RegisterRouter.scala:87:24] wire out_womask_663 = &_out_womask_T_663; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_663 = out_rivalid_1_517 & out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6640 = out_f_rivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_roready_663 = out_roready_1_517 & out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6641 = out_f_roready_663; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_663 = out_wivalid_1_517 & out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6642 = out_f_wivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_woready_663 = out_woready_1_517 & out_womask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6643 = out_f_woready_663; // @[RegisterRouter.scala:87:24] wire _out_T_6644 = ~out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6645 = ~out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6646 = ~out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6647 = ~out_womask_663; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_562 = {programBufferMem_14, _out_prepend_T_562}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6648 = out_prepend_562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6649 = _out_T_6648; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_563 = _out_T_6649; // @[RegisterRouter.scala:87:24] wire out_rimask_664 = \|_out_rimask_T_664; // @[RegisterRouter.scala:87:24] wire out_wimask_664 = &_out_wimask_T_664; // @[RegisterRouter.scala:87:24] wire out_romask_664 = \|_out_romask_T_664; // @[RegisterRouter.scala:87:24] wire out_womask_664 = &_out_womask_T_664; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_664 = out_rivalid_1_518 & out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6651 = out_f_rivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_roready_664 = out_roready_1_518 & out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6652 = out_f_roready_664; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_664 = out_wivalid_1_518 & out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6653 = out_f_wivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_woready_664 = out_woready_1_518 & out_womask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6654 = out_f_woready_664; // @[RegisterRouter.scala:87:24] wire _out_T_6655 = ~out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6656 = ~out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6657 = ~out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6658 = ~out_womask_664; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_563 = {programBufferMem_15, _out_prepend_T_563}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6659 = out_prepend_563; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6660 = _out_T_6659; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_105 = _out_T_6660; // @[MuxLiteral.scala:49:48] wire out_rimask_665 = \|_out_rimask_T_665; // @[RegisterRouter.scala:87:24] wire out_wimask_665 = &_out_wimask_T_665; // @[RegisterRouter.scala:87:24] wire out_romask_665 = \|_out_romask_T_665; // @[RegisterRouter.scala:87:24] wire out_womask_665 = &_out_womask_T_665; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_665 = out_rivalid_1_519 & out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6662 = out_f_rivalid_665; // @[RegisterRouter.scala:87:24] wire out_f_roready_665 = out_roready_1_519 & out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6663 = out_f_roready_665; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_665 = out_wivalid_1_519 & out_wimask_665; // @[RegisterRouter.scala:87:24] wire out_f_woready_665 = out_woready_1_519 & out_womask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6664 = ~out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6665 = ~out_wimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6666 = ~out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6667 = ~out_womask_665; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6669 = _out_T_6668; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_564 = _out_T_6669; // @[RegisterRouter.scala:87:24] wire out_rimask_666 = \|_out_rimask_T_666; // @[RegisterRouter.scala:87:24] wire out_wimask_666 = &_out_wimask_T_666; // @[RegisterRouter.scala:87:24] wire out_romask_666 = \|_out_romask_T_666; // @[RegisterRouter.scala:87:24] wire out_womask_666 = &_out_womask_T_666; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_666 = out_rivalid_1_520 & out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6671 = out_f_rivalid_666; // @[RegisterRouter.scala:87:24] wire out_f_roready_666 = out_roready_1_520 & out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6672 = out_f_roready_666; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_666 = out_wivalid_1_520 & out_wimask_666; // @[RegisterRouter.scala:87:24] wire out_f_woready_666 = out_woready_1_520 & out_womask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6673 = ~out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6674 = ~out_wimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6675 = ~out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6676 = ~out_womask_666; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_564 = {hi_930, flags_0_go, _out_prepend_T_564}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6677 = out_prepend_564; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6678 = _out_T_6677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_565 = _out_T_6678; // @[RegisterRouter.scala:87:24] wire out_rimask_667 = \|_out_rimask_T_667; // @[RegisterRouter.scala:87:24] wire out_wimask_667 = &_out_wimask_T_667; // @[RegisterRouter.scala:87:24] wire out_romask_667 = \|_out_romask_T_667; // @[RegisterRouter.scala:87:24] wire out_womask_667 = &_out_womask_T_667; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_667 = out_rivalid_1_521 & out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6680 = out_f_rivalid_667; // @[RegisterRouter.scala:87:24] wire out_f_roready_667 = out_roready_1_521 & out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6681 = out_f_roready_667; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_667 = out_wivalid_1_521 & out_wimask_667; // @[RegisterRouter.scala:87:24] wire out_f_woready_667 = out_woready_1_521 & out_womask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6682 = ~out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6683 = ~out_wimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6684 = ~out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6685 = ~out_womask_667; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_565 = {hi_931, flags_0_go, _out_prepend_T_565}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6686 = out_prepend_565; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6687 = _out_T_6686; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_566 = _out_T_6687; // @[RegisterRouter.scala:87:24] wire out_rimask_668 = \|_out_rimask_T_668; // @[RegisterRouter.scala:87:24] wire out_wimask_668 = &_out_wimask_T_668; // @[RegisterRouter.scala:87:24] wire out_romask_668 = \|_out_romask_T_668; // @[RegisterRouter.scala:87:24] wire out_womask_668 = &_out_womask_T_668; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_668 = out_rivalid_1_522 & out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6689 = out_f_rivalid_668; // @[RegisterRouter.scala:87:24] wire out_f_roready_668 = out_roready_1_522 & out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6690 = out_f_roready_668; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_668 = out_wivalid_1_522 & out_wimask_668; // @[RegisterRouter.scala:87:24] wire out_f_woready_668 = out_woready_1_522 & out_womask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6691 = ~out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6692 = ~out_wimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6693 = ~out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6694 = ~out_womask_668; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_566 = {hi_932, flags_0_go, _out_prepend_T_566}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6695 = out_prepend_566; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6696 = _out_T_6695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_567 = _out_T_6696; // @[RegisterRouter.scala:87:24] wire out_rimask_669 = \|_out_rimask_T_669; // @[RegisterRouter.scala:87:24] wire out_wimask_669 = &_out_wimask_T_669; // @[RegisterRouter.scala:87:24] wire out_romask_669 = \|_out_romask_T_669; // @[RegisterRouter.scala:87:24] wire out_womask_669 = &_out_womask_T_669; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_669 = out_rivalid_1_523 & out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6698 = out_f_rivalid_669; // @[RegisterRouter.scala:87:24] wire out_f_roready_669 = out_roready_1_523 & out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6699 = out_f_roready_669; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_669 = out_wivalid_1_523 & out_wimask_669; // @[RegisterRouter.scala:87:24] wire out_f_woready_669 = out_woready_1_523 & out_womask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6700 = ~out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6701 = ~out_wimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6702 = ~out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6703 = ~out_womask_669; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_567 = {hi_933, flags_0_go, _out_prepend_T_567}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6704 = out_prepend_567; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6705 = _out_T_6704; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_568 = _out_T_6705; // @[RegisterRouter.scala:87:24] wire out_rimask_670 = \|_out_rimask_T_670; // @[RegisterRouter.scala:87:24] wire out_wimask_670 = &_out_wimask_T_670; // @[RegisterRouter.scala:87:24] wire out_romask_670 = \|_out_romask_T_670; // @[RegisterRouter.scala:87:24] wire out_womask_670 = &_out_womask_T_670; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_670 = out_rivalid_1_524 & out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6707 = out_f_rivalid_670; // @[RegisterRouter.scala:87:24] wire out_f_roready_670 = out_roready_1_524 & out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6708 = out_f_roready_670; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_670 = out_wivalid_1_524 & out_wimask_670; // @[RegisterRouter.scala:87:24] wire out_f_woready_670 = out_woready_1_524 & out_womask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6709 = ~out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6710 = ~out_wimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6711 = ~out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6712 = ~out_womask_670; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_568 = {hi_934, flags_0_go, _out_prepend_T_568}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6713 = out_prepend_568; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6714 = _out_T_6713; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_569 = _out_T_6714; // @[RegisterRouter.scala:87:24] wire out_rimask_671 = \|_out_rimask_T_671; // @[RegisterRouter.scala:87:24] wire out_wimask_671 = &_out_wimask_T_671; // @[RegisterRouter.scala:87:24] wire out_romask_671 = \|_out_romask_T_671; // @[RegisterRouter.scala:87:24] wire out_womask_671 = &_out_womask_T_671; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_671 = out_rivalid_1_525 & out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6716 = out_f_rivalid_671; // @[RegisterRouter.scala:87:24] wire out_f_roready_671 = out_roready_1_525 & out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6717 = out_f_roready_671; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_671 = out_wivalid_1_525 & out_wimask_671; // @[RegisterRouter.scala:87:24] wire out_f_woready_671 = out_woready_1_525 & out_womask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6718 = ~out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6719 = ~out_wimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6720 = ~out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6721 = ~out_womask_671; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_569 = {hi_935, flags_0_go, _out_prepend_T_569}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6722 = out_prepend_569; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6723 = _out_T_6722; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_570 = _out_T_6723; // @[RegisterRouter.scala:87:24] wire out_rimask_672 = \|_out_rimask_T_672; // @[RegisterRouter.scala:87:24] wire out_wimask_672 = &_out_wimask_T_672; // @[RegisterRouter.scala:87:24] wire out_romask_672 = \|_out_romask_T_672; // @[RegisterRouter.scala:87:24] wire out_womask_672 = &_out_womask_T_672; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_672 = out_rivalid_1_526 & out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6725 = out_f_rivalid_672; // @[RegisterRouter.scala:87:24] wire out_f_roready_672 = out_roready_1_526 & out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6726 = out_f_roready_672; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_672 = out_wivalid_1_526 & out_wimask_672; // @[RegisterRouter.scala:87:24] wire out_f_woready_672 = out_woready_1_526 & out_womask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6727 = ~out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6728 = ~out_wimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6729 = ~out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6730 = ~out_womask_672; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_570 = {hi_936, flags_0_go, _out_prepend_T_570}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6731 = out_prepend_570; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6732 = _out_T_6731; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_244 = _out_T_6732; // @[MuxLiteral.scala:49:48] wire out_rimask_673 = \|_out_rimask_T_673; // @[RegisterRouter.scala:87:24] wire out_wimask_673 = &_out_wimask_T_673; // @[RegisterRouter.scala:87:24] wire out_romask_673 = \|_out_romask_T_673; // @[RegisterRouter.scala:87:24] wire out_womask_673 = &_out_womask_T_673; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_673 = out_rivalid_1_527 & out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6734 = out_f_rivalid_673; // @[RegisterRouter.scala:87:24] wire out_f_roready_673 = out_roready_1_527 & out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6735 = out_f_roready_673; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_673 = out_wivalid_1_527 & out_wimask_673; // @[RegisterRouter.scala:87:24] wire out_f_woready_673 = out_woready_1_527 & out_womask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6736 = ~out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6737 = ~out_wimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6738 = ~out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6739 = ~out_womask_673; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6741 = _out_T_6740; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_571 = _out_T_6741; // @[RegisterRouter.scala:87:24] wire out_rimask_674 = \|_out_rimask_T_674; // @[RegisterRouter.scala:87:24] wire out_wimask_674 = &_out_wimask_T_674; // @[RegisterRouter.scala:87:24] wire out_romask_674 = \|_out_romask_T_674; // @[RegisterRouter.scala:87:24] wire out_womask_674 = &_out_womask_T_674; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_674 = out_rivalid_1_528 & out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6743 = out_f_rivalid_674; // @[RegisterRouter.scala:87:24] wire out_f_roready_674 = out_roready_1_528 & out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6744 = out_f_roready_674; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_674 = out_wivalid_1_528 & out_wimask_674; // @[RegisterRouter.scala:87:24] wire out_f_woready_674 = out_woready_1_528 & out_womask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6745 = ~out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6746 = ~out_wimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6747 = ~out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6748 = ~out_womask_674; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_571 = {hi_306, flags_0_go, _out_prepend_T_571}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6749 = out_prepend_571; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6750 = _out_T_6749; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_572 = _out_T_6750; // @[RegisterRouter.scala:87:24] wire out_rimask_675 = \|_out_rimask_T_675; // @[RegisterRouter.scala:87:24] wire out_wimask_675 = &_out_wimask_T_675; // @[RegisterRouter.scala:87:24] wire out_romask_675 = \|_out_romask_T_675; // @[RegisterRouter.scala:87:24] wire out_womask_675 = &_out_womask_T_675; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_675 = out_rivalid_1_529 & out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6752 = out_f_rivalid_675; // @[RegisterRouter.scala:87:24] wire out_f_roready_675 = out_roready_1_529 & out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6753 = out_f_roready_675; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_675 = out_wivalid_1_529 & out_wimask_675; // @[RegisterRouter.scala:87:24] wire out_f_woready_675 = out_woready_1_529 & out_womask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6754 = ~out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6755 = ~out_wimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6756 = ~out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6757 = ~out_womask_675; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_572 = {hi_307, flags_0_go, _out_prepend_T_572}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6758 = out_prepend_572; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6759 = _out_T_6758; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_573 = _out_T_6759; // @[RegisterRouter.scala:87:24] wire out_rimask_676 = \|_out_rimask_T_676; // @[RegisterRouter.scala:87:24] wire out_wimask_676 = &_out_wimask_T_676; // @[RegisterRouter.scala:87:24] wire out_romask_676 = \|_out_romask_T_676; // @[RegisterRouter.scala:87:24] wire out_womask_676 = &_out_womask_T_676; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_676 = out_rivalid_1_530 & out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6761 = out_f_rivalid_676; // @[RegisterRouter.scala:87:24] wire out_f_roready_676 = out_roready_1_530 & out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6762 = out_f_roready_676; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_676 = out_wivalid_1_530 & out_wimask_676; // @[RegisterRouter.scala:87:24] wire out_f_woready_676 = out_woready_1_530 & out_womask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6763 = ~out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6764 = ~out_wimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6765 = ~out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6766 = ~out_womask_676; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_573 = {hi_308, flags_0_go, _out_prepend_T_573}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6767 = out_prepend_573; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6768 = _out_T_6767; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_574 = _out_T_6768; // @[RegisterRouter.scala:87:24] wire out_rimask_677 = \|_out_rimask_T_677; // @[RegisterRouter.scala:87:24] wire out_wimask_677 = &_out_wimask_T_677; // @[RegisterRouter.scala:87:24] wire out_romask_677 = \|_out_romask_T_677; // @[RegisterRouter.scala:87:24] wire out_womask_677 = &_out_womask_T_677; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_677 = out_rivalid_1_531 & out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6770 = out_f_rivalid_677; // @[RegisterRouter.scala:87:24] wire out_f_roready_677 = out_roready_1_531 & out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6771 = out_f_roready_677; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_677 = out_wivalid_1_531 & out_wimask_677; // @[RegisterRouter.scala:87:24] wire out_f_woready_677 = out_woready_1_531 & out_womask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6772 = ~out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6773 = ~out_wimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6774 = ~out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6775 = ~out_womask_677; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_574 = {hi_309, flags_0_go, _out_prepend_T_574}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6776 = out_prepend_574; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6777 = _out_T_6776; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_575 = _out_T_6777; // @[RegisterRouter.scala:87:24] wire out_rimask_678 = \|_out_rimask_T_678; // @[RegisterRouter.scala:87:24] wire out_wimask_678 = &_out_wimask_T_678; // @[RegisterRouter.scala:87:24] wire out_romask_678 = \|_out_romask_T_678; // @[RegisterRouter.scala:87:24] wire out_womask_678 = &_out_womask_T_678; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_678 = out_rivalid_1_532 & out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6779 = out_f_rivalid_678; // @[RegisterRouter.scala:87:24] wire out_f_roready_678 = out_roready_1_532 & out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6780 = out_f_roready_678; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_678 = out_wivalid_1_532 & out_wimask_678; // @[RegisterRouter.scala:87:24] wire out_f_woready_678 = out_woready_1_532 & out_womask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6781 = ~out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6782 = ~out_wimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6783 = ~out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6784 = ~out_womask_678; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_575 = {hi_310, flags_0_go, _out_prepend_T_575}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6785 = out_prepend_575; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6786 = _out_T_6785; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_576 = _out_T_6786; // @[RegisterRouter.scala:87:24] wire out_rimask_679 = \|_out_rimask_T_679; // @[RegisterRouter.scala:87:24] wire out_wimask_679 = &_out_wimask_T_679; // @[RegisterRouter.scala:87:24] wire out_romask_679 = \|_out_romask_T_679; // @[RegisterRouter.scala:87:24] wire out_womask_679 = &_out_womask_T_679; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_679 = out_rivalid_1_533 & out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6788 = out_f_rivalid_679; // @[RegisterRouter.scala:87:24] wire out_f_roready_679 = out_roready_1_533 & out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6789 = out_f_roready_679; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_679 = out_wivalid_1_533 & out_wimask_679; // @[RegisterRouter.scala:87:24] wire out_f_woready_679 = out_woready_1_533 & out_womask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6790 = ~out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6791 = ~out_wimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6792 = ~out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6793 = ~out_womask_679; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_576 = {hi_311, flags_0_go, _out_prepend_T_576}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6794 = out_prepend_576; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6795 = _out_T_6794; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_577 = _out_T_6795; // @[RegisterRouter.scala:87:24] wire out_rimask_680 = \|_out_rimask_T_680; // @[RegisterRouter.scala:87:24] wire out_wimask_680 = &_out_wimask_T_680; // @[RegisterRouter.scala:87:24] wire out_romask_680 = \|_out_romask_T_680; // @[RegisterRouter.scala:87:24] wire out_womask_680 = &_out_womask_T_680; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_680 = out_rivalid_1_534 & out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6797 = out_f_rivalid_680; // @[RegisterRouter.scala:87:24] wire out_f_roready_680 = out_roready_1_534 & out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6798 = out_f_roready_680; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_680 = out_wivalid_1_534 & out_wimask_680; // @[RegisterRouter.scala:87:24] wire out_f_woready_680 = out_woready_1_534 & out_womask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6799 = ~out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6800 = ~out_wimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6801 = ~out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6802 = ~out_womask_680; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_577 = {hi_312, flags_0_go, _out_prepend_T_577}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6803 = out_prepend_577; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6804 = _out_T_6803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_166 = _out_T_6804; // @[MuxLiteral.scala:49:48] wire out_rimask_681 = \|_out_rimask_T_681; // @[RegisterRouter.scala:87:24] wire out_wimask_681 = &_out_wimask_T_681; // @[RegisterRouter.scala:87:24] wire out_romask_681 = \|_out_romask_T_681; // @[RegisterRouter.scala:87:24] wire out_womask_681 = &_out_womask_T_681; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_681 = out_rivalid_1_535 & out_rimask_681; // @[RegisterRouter.scala:87:24] wire out_f_roready_681 = out_roready_1_535 & out_romask_681; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_681 = out_wivalid_1_535 & out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6806 = out_f_wivalid_681; // @[RegisterRouter.scala:87:24] assign out_f_woready_681 = out_woready_1_535 & out_womask_681; // @[RegisterRouter.scala:87:24] assign hartHaltedWrEn = out_f_woready_681; // @[RegisterRouter.scala:87:24] wire _out_T_6807 = out_f_woready_681; // @[RegisterRouter.scala:87:24] assign hartHaltedId = _out_T_6805; // @[RegisterRouter.scala:87:24] wire _out_T_6808 = ~out_rimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6809 = ~out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6810 = ~out_romask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6811 = ~out_womask_681; // @[RegisterRouter.scala:87:24] wire out_rimask_682 = \|_out_rimask_T_682; // @[RegisterRouter.scala:87:24] wire out_wimask_682 = &_out_wimask_T_682; // @[RegisterRouter.scala:87:24] wire out_romask_682 = \|_out_romask_T_682; // @[RegisterRouter.scala:87:24] wire out_womask_682 = &_out_womask_T_682; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_682 = out_rivalid_1_536 & out_rimask_682; // @[RegisterRouter.scala:87:24] wire out_f_roready_682 = out_roready_1_536 & out_romask_682; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_682 = out_wivalid_1_536 & out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6815 = out_f_wivalid_682; // @[RegisterRouter.scala:87:24] assign out_f_woready_682 = out_woready_1_536 & out_womask_682; // @[RegisterRouter.scala:87:24] assign hartGoingWrEn = out_f_woready_682; // @[RegisterRouter.scala:87:24] wire _out_T_6816 = out_f_woready_682; // @[RegisterRouter.scala:87:24] assign hartGoingId = _out_T_6814; // @[RegisterRouter.scala:87:24] wire _out_T_6817 = ~out_rimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6818 = ~out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6819 = ~out_romask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6820 = ~out_womask_682; // @[RegisterRouter.scala:87:24] wire out_rimask_683 = \|_out_rimask_T_683; // @[RegisterRouter.scala:87:24] wire out_wimask_683 = &_out_wimask_T_683; // @[RegisterRouter.scala:87:24] wire out_romask_683 = \|_out_romask_T_683; // @[RegisterRouter.scala:87:24] wire out_womask_683 = &_out_womask_T_683; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_683 = out_rivalid_1_537 & out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6824 = out_f_rivalid_683; // @[RegisterRouter.scala:87:24] wire out_f_roready_683 = out_roready_1_537 & out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6825 = out_f_roready_683; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_683 = out_wivalid_1_537 & out_wimask_683; // @[RegisterRouter.scala:87:24] wire out_f_woready_683 = out_woready_1_537 & out_womask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6826 = ~out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6827 = ~out_wimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6828 = ~out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6829 = ~out_womask_683; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6831 = _out_T_6830; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_579 = _out_T_6831; // @[RegisterRouter.scala:87:24] wire out_rimask_684 = \|_out_rimask_T_684; // @[RegisterRouter.scala:87:24] wire out_wimask_684 = &_out_wimask_T_684; // @[RegisterRouter.scala:87:24] wire out_romask_684 = \|_out_romask_T_684; // @[RegisterRouter.scala:87:24] wire out_womask_684 = &_out_womask_T_684; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_684 = out_rivalid_1_538 & out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6833 = out_f_rivalid_684; // @[RegisterRouter.scala:87:24] wire out_f_roready_684 = out_roready_1_538 & out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6834 = out_f_roready_684; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_684 = out_wivalid_1_538 & out_wimask_684; // @[RegisterRouter.scala:87:24] wire out_f_woready_684 = out_woready_1_538 & out_womask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6835 = ~out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6836 = ~out_wimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6837 = ~out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6838 = ~out_womask_684; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_579 = {hi_162, flags_0_go, _out_prepend_T_579}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6839 = out_prepend_579; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6840 = _out_T_6839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_580 = _out_T_6840; // @[RegisterRouter.scala:87:24] wire out_rimask_685 = \|_out_rimask_T_685; // @[RegisterRouter.scala:87:24] wire out_wimask_685 = &_out_wimask_T_685; // @[RegisterRouter.scala:87:24] wire out_romask_685 = \|_out_romask_T_685; // @[RegisterRouter.scala:87:24] wire out_womask_685 = &_out_womask_T_685; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_685 = out_rivalid_1_539 & out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6842 = out_f_rivalid_685; // @[RegisterRouter.scala:87:24] wire out_f_roready_685 = out_roready_1_539 & out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6843 = out_f_roready_685; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_685 = out_wivalid_1_539 & out_wimask_685; // @[RegisterRouter.scala:87:24] wire out_f_woready_685 = out_woready_1_539 & out_womask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6844 = ~out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6845 = ~out_wimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6846 = ~out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6847 = ~out_womask_685; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_580 = {hi_163, flags_0_go, _out_prepend_T_580}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6848 = out_prepend_580; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6849 = _out_T_6848; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_581 = _out_T_6849; // @[RegisterRouter.scala:87:24] wire out_rimask_686 = \|_out_rimask_T_686; // @[RegisterRouter.scala:87:24] wire out_wimask_686 = &_out_wimask_T_686; // @[RegisterRouter.scala:87:24] wire out_romask_686 = \|_out_romask_T_686; // @[RegisterRouter.scala:87:24] wire out_womask_686 = &_out_womask_T_686; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_686 = out_rivalid_1_540 & out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6851 = out_f_rivalid_686; // @[RegisterRouter.scala:87:24] wire out_f_roready_686 = out_roready_1_540 & out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6852 = out_f_roready_686; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_686 = out_wivalid_1_540 & out_wimask_686; // @[RegisterRouter.scala:87:24] wire out_f_woready_686 = out_woready_1_540 & out_womask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6853 = ~out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6854 = ~out_wimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6855 = ~out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6856 = ~out_womask_686; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_581 = {hi_164, flags_0_go, _out_prepend_T_581}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6857 = out_prepend_581; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6858 = _out_T_6857; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_582 = _out_T_6858; // @[RegisterRouter.scala:87:24] wire out_rimask_687 = \|_out_rimask_T_687; // @[RegisterRouter.scala:87:24] wire out_wimask_687 = &_out_wimask_T_687; // @[RegisterRouter.scala:87:24] wire out_romask_687 = \|_out_romask_T_687; // @[RegisterRouter.scala:87:24] wire out_womask_687 = &_out_womask_T_687; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_687 = out_rivalid_1_541 & out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6860 = out_f_rivalid_687; // @[RegisterRouter.scala:87:24] wire out_f_roready_687 = out_roready_1_541 & out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6861 = out_f_roready_687; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_687 = out_wivalid_1_541 & out_wimask_687; // @[RegisterRouter.scala:87:24] wire out_f_woready_687 = out_woready_1_541 & out_womask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6862 = ~out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6863 = ~out_wimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6864 = ~out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6865 = ~out_womask_687; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_582 = {hi_165, flags_0_go, _out_prepend_T_582}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6866 = out_prepend_582; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6867 = _out_T_6866; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_583 = _out_T_6867; // @[RegisterRouter.scala:87:24] wire out_rimask_688 = \|_out_rimask_T_688; // @[RegisterRouter.scala:87:24] wire out_wimask_688 = &_out_wimask_T_688; // @[RegisterRouter.scala:87:24] wire out_romask_688 = \|_out_romask_T_688; // @[RegisterRouter.scala:87:24] wire out_womask_688 = &_out_womask_T_688; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_688 = out_rivalid_1_542 & out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6869 = out_f_rivalid_688; // @[RegisterRouter.scala:87:24] wire out_f_roready_688 = out_roready_1_542 & out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6870 = out_f_roready_688; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_688 = out_wivalid_1_542 & out_wimask_688; // @[RegisterRouter.scala:87:24] wire out_f_woready_688 = out_woready_1_542 & out_womask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6871 = ~out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6872 = ~out_wimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6873 = ~out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6874 = ~out_womask_688; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_583 = {hi_166, flags_0_go, _out_prepend_T_583}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6875 = out_prepend_583; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6876 = _out_T_6875; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_584 = _out_T_6876; // @[RegisterRouter.scala:87:24] wire out_rimask_689 = \|_out_rimask_T_689; // @[RegisterRouter.scala:87:24] wire out_wimask_689 = &_out_wimask_T_689; // @[RegisterRouter.scala:87:24] wire out_romask_689 = \|_out_romask_T_689; // @[RegisterRouter.scala:87:24] wire out_womask_689 = &_out_womask_T_689; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_689 = out_rivalid_1_543 & out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6878 = out_f_rivalid_689; // @[RegisterRouter.scala:87:24] wire out_f_roready_689 = out_roready_1_543 & out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6879 = out_f_roready_689; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_689 = out_wivalid_1_543 & out_wimask_689; // @[RegisterRouter.scala:87:24] wire out_f_woready_689 = out_woready_1_543 & out_womask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6880 = ~out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6881 = ~out_wimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6882 = ~out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6883 = ~out_womask_689; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_584 = {hi_167, flags_0_go, _out_prepend_T_584}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6884 = out_prepend_584; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6885 = _out_T_6884; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_585 = _out_T_6885; // @[RegisterRouter.scala:87:24] wire out_rimask_690 = \|_out_rimask_T_690; // @[RegisterRouter.scala:87:24] wire out_wimask_690 = &_out_wimask_T_690; // @[RegisterRouter.scala:87:24] wire out_romask_690 = \|_out_romask_T_690; // @[RegisterRouter.scala:87:24] wire out_womask_690 = &_out_womask_T_690; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_690 = out_rivalid_1_544 & out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6887 = out_f_rivalid_690; // @[RegisterRouter.scala:87:24] wire out_f_roready_690 = out_roready_1_544 & out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6888 = out_f_roready_690; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_690 = out_wivalid_1_544 & out_wimask_690; // @[RegisterRouter.scala:87:24] wire out_f_woready_690 = out_woready_1_544 & out_womask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6889 = ~out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6890 = ~out_wimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6891 = ~out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6892 = ~out_womask_690; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_585 = {hi_168, flags_0_go, _out_prepend_T_585}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6893 = out_prepend_585; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6894 = _out_T_6893; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_148 = _out_T_6894; // @[MuxLiteral.scala:49:48] wire out_rimask_691 = \|_out_rimask_T_691; // @[RegisterRouter.scala:87:24] wire out_wimask_691 = &_out_wimask_T_691; // @[RegisterRouter.scala:87:24] wire out_romask_691 = \|_out_romask_T_691; // @[RegisterRouter.scala:87:24] wire out_womask_691 = &_out_womask_T_691; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_691 = out_rivalid_1_545 & out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6896 = out_f_rivalid_691; // @[RegisterRouter.scala:87:24] wire out_f_roready_691 = out_roready_1_545 & out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6897 = out_f_roready_691; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_691 = out_wivalid_1_545 & out_wimask_691; // @[RegisterRouter.scala:87:24] wire out_f_woready_691 = out_woready_1_545 & out_womask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6898 = ~out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6899 = ~out_wimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6900 = ~out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6901 = ~out_womask_691; // @[RegisterRouter.scala:87:24] wire out_rimask_692 = \|_out_rimask_T_692; // @[RegisterRouter.scala:87:24] wire out_wimask_692 = &_out_wimask_T_692; // @[RegisterRouter.scala:87:24] wire out_romask_692 = \|_out_romask_T_692; // @[RegisterRouter.scala:87:24] wire out_womask_692 = &_out_womask_T_692; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_692 = out_rivalid_1_546 & out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6905 = out_f_rivalid_692; // @[RegisterRouter.scala:87:24] wire out_f_roready_692 = out_roready_1_546 & out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6906 = out_f_roready_692; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_692 = out_wivalid_1_546 & out_wimask_692; // @[RegisterRouter.scala:87:24] wire out_f_woready_692 = out_woready_1_546 & out_womask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6907 = ~out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6908 = ~out_wimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6909 = ~out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6910 = ~out_womask_692; // @[RegisterRouter.scala:87:24] wire out_rimask_693 = \|_out_rimask_T_693; // @[RegisterRouter.scala:87:24] wire out_wimask_693 = &_out_wimask_T_693; // @[RegisterRouter.scala:87:24] wire out_romask_693 = \|_out_romask_T_693; // @[RegisterRouter.scala:87:24] wire out_womask_693 = &_out_womask_T_693; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_693 = out_rivalid_1_547 & out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6914 = out_f_rivalid_693; // @[RegisterRouter.scala:87:24] wire out_f_roready_693 = out_roready_1_547 & out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6915 = out_f_roready_693; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_693 = out_wivalid_1_547 & out_wimask_693; // @[RegisterRouter.scala:87:24] wire out_f_woready_693 = out_woready_1_547 & out_womask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6916 = ~out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6917 = ~out_wimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6918 = ~out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6919 = ~out_womask_693; // @[RegisterRouter.scala:87:24] wire out_rimask_694 = \|_out_rimask_T_694; // @[RegisterRouter.scala:87:24] wire out_wimask_694 = &_out_wimask_T_694; // @[RegisterRouter.scala:87:24] wire out_romask_694 = \|_out_romask_T_694; // @[RegisterRouter.scala:87:24] wire out_womask_694 = &_out_womask_T_694; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_694 = out_rivalid_1_548 & out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6923 = out_f_rivalid_694; // @[RegisterRouter.scala:87:24] wire out_f_roready_694 = out_roready_1_548 & out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6924 = out_f_roready_694; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_694 = out_wivalid_1_548 & out_wimask_694; // @[RegisterRouter.scala:87:24] wire out_f_woready_694 = out_woready_1_548 & out_womask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6925 = ~out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6926 = ~out_wimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6927 = ~out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6928 = ~out_womask_694; // @[RegisterRouter.scala:87:24] wire out_rimask_695 = \|_out_rimask_T_695; // @[RegisterRouter.scala:87:24] wire out_wimask_695 = &_out_wimask_T_695; // @[RegisterRouter.scala:87:24] wire out_romask_695 = \|_out_romask_T_695; // @[RegisterRouter.scala:87:24] wire out_womask_695 = &_out_womask_T_695; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_695 = out_rivalid_1_549 & out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6932 = out_f_rivalid_695; // @[RegisterRouter.scala:87:24] wire out_f_roready_695 = out_roready_1_549 & out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6933 = out_f_roready_695; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_695 = out_wivalid_1_549 & out_wimask_695; // @[RegisterRouter.scala:87:24] wire out_f_woready_695 = out_woready_1_549 & out_womask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6934 = ~out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6935 = ~out_wimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6936 = ~out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6937 = ~out_womask_695; // @[RegisterRouter.scala:87:24] wire out_rimask_696 = \|_out_rimask_T_696; // @[RegisterRouter.scala:87:24] wire out_wimask_696 = &_out_wimask_T_696; // @[RegisterRouter.scala:87:24] wire out_romask_696 = \|_out_romask_T_696; // @[RegisterRouter.scala:87:24] wire out_womask_696 = &_out_womask_T_696; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_696 = out_rivalid_1_550 & out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6941 = out_f_rivalid_696; // @[RegisterRouter.scala:87:24] wire out_f_roready_696 = out_roready_1_550 & out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6942 = out_f_roready_696; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_696 = out_wivalid_1_550 & out_wimask_696; // @[RegisterRouter.scala:87:24] wire out_f_woready_696 = out_woready_1_550 & out_womask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6943 = ~out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6944 = ~out_wimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6945 = ~out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6946 = ~out_womask_696; // @[RegisterRouter.scala:87:24] wire out_rimask_697 = \|_out_rimask_T_697; // @[RegisterRouter.scala:87:24] wire out_wimask_697 = &_out_wimask_T_697; // @[RegisterRouter.scala:87:24] wire out_romask_697 = \|_out_romask_T_697; // @[RegisterRouter.scala:87:24] wire out_womask_697 = &_out_womask_T_697; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_697 = out_rivalid_1_551 & out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6950 = out_f_rivalid_697; // @[RegisterRouter.scala:87:24] wire out_f_roready_697 = out_roready_1_551 & out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6951 = out_f_roready_697; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_697 = out_wivalid_1_551 & out_wimask_697; // @[RegisterRouter.scala:87:24] wire out_f_woready_697 = out_woready_1_551 & out_womask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6952 = ~out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6953 = ~out_wimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6954 = ~out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6955 = ~out_womask_697; // @[RegisterRouter.scala:87:24] wire out_rimask_698 = \|_out_rimask_T_698; // @[RegisterRouter.scala:87:24] wire out_wimask_698 = &_out_wimask_T_698; // @[RegisterRouter.scala:87:24] wire out_romask_698 = \|_out_romask_T_698; // @[RegisterRouter.scala:87:24] wire out_womask_698 = &_out_womask_T_698; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_698 = out_rivalid_1_552 & out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6959 = out_f_rivalid_698; // @[RegisterRouter.scala:87:24] wire out_f_roready_698 = out_roready_1_552 & out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6960 = out_f_roready_698; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_698 = out_wivalid_1_552 & out_wimask_698; // @[RegisterRouter.scala:87:24] wire out_f_woready_698 = out_woready_1_552 & out_womask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6961 = ~out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6962 = ~out_wimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6963 = ~out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6964 = ~out_womask_698; // @[RegisterRouter.scala:87:24] wire out_rimask_699 = \|_out_rimask_T_699; // @[RegisterRouter.scala:87:24] wire out_wimask_699 = &_out_wimask_T_699; // @[RegisterRouter.scala:87:24] wire out_romask_699 = \|_out_romask_T_699; // @[RegisterRouter.scala:87:24] wire out_womask_699 = &_out_womask_T_699; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_699 = out_rivalid_1_553 & out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6968 = out_f_rivalid_699; // @[RegisterRouter.scala:87:24] wire out_f_roready_699 = out_roready_1_553 & out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6969 = out_f_roready_699; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_699 = out_wivalid_1_553 & out_wimask_699; // @[RegisterRouter.scala:87:24] wire out_f_woready_699 = out_woready_1_553 & out_womask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6970 = ~out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6971 = ~out_wimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6972 = ~out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6973 = ~out_womask_699; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6975 = _out_T_6974; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_593 = _out_T_6975; // @[RegisterRouter.scala:87:24] wire out_rimask_700 = \|_out_rimask_T_700; // @[RegisterRouter.scala:87:24] wire out_wimask_700 = &_out_wimask_T_700; // @[RegisterRouter.scala:87:24] wire out_romask_700 = \|_out_romask_T_700; // @[RegisterRouter.scala:87:24] wire out_womask_700 = &_out_womask_T_700; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_700 = out_rivalid_1_554 & out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6977 = out_f_rivalid_700; // @[RegisterRouter.scala:87:24] wire out_f_roready_700 = out_roready_1_554 & out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6978 = out_f_roready_700; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_700 = out_wivalid_1_554 & out_wimask_700; // @[RegisterRouter.scala:87:24] wire out_f_woready_700 = out_woready_1_554 & out_womask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6979 = ~out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6980 = ~out_wimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6981 = ~out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6982 = ~out_womask_700; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_593 = {hi_266, flags_0_go, _out_prepend_T_593}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6983 = out_prepend_593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6984 = _out_T_6983; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_594 = _out_T_6984; // @[RegisterRouter.scala:87:24] wire out_rimask_701 = \|_out_rimask_T_701; // @[RegisterRouter.scala:87:24] wire out_wimask_701 = &_out_wimask_T_701; // @[RegisterRouter.scala:87:24] wire out_romask_701 = \|_out_romask_T_701; // @[RegisterRouter.scala:87:24] wire out_womask_701 = &_out_womask_T_701; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_701 = out_rivalid_1_555 & out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6986 = out_f_rivalid_701; // @[RegisterRouter.scala:87:24] wire out_f_roready_701 = out_roready_1_555 & out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6987 = out_f_roready_701; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_701 = out_wivalid_1_555 & out_wimask_701; // @[RegisterRouter.scala:87:24] wire out_f_woready_701 = out_woready_1_555 & out_womask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6988 = ~out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6989 = ~out_wimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6990 = ~out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6991 = ~out_womask_701; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_594 = {hi_267, flags_0_go, _out_prepend_T_594}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6992 = out_prepend_594; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6993 = _out_T_6992; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_595 = _out_T_6993; // @[RegisterRouter.scala:87:24] wire out_rimask_702 = \|_out_rimask_T_702; // @[RegisterRouter.scala:87:24] wire out_wimask_702 = &_out_wimask_T_702; // @[RegisterRouter.scala:87:24] wire out_romask_702 = \|_out_romask_T_702; // @[RegisterRouter.scala:87:24] wire out_womask_702 = &_out_womask_T_702; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_702 = out_rivalid_1_556 & out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6995 = out_f_rivalid_702; // @[RegisterRouter.scala:87:24] wire out_f_roready_702 = out_roready_1_556 & out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6996 = out_f_roready_702; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_702 = out_wivalid_1_556 & out_wimask_702; // @[RegisterRouter.scala:87:24] wire out_f_woready_702 = out_woready_1_556 & out_womask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6997 = ~out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6998 = ~out_wimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6999 = ~out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_7000 = ~out_womask_702; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_595 = {hi_268, flags_0_go, _out_prepend_T_595}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7001 = out_prepend_595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7002 = _out_T_7001; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_596 = _out_T_7002; // @[RegisterRouter.scala:87:24] wire out_rimask_703 = \|_out_rimask_T_703; // @[RegisterRouter.scala:87:24] wire out_wimask_703 = &_out_wimask_T_703; // @[RegisterRouter.scala:87:24] wire out_romask_703 = \|_out_romask_T_703; // @[RegisterRouter.scala:87:24] wire out_womask_703 = &_out_womask_T_703; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_703 = out_rivalid_1_557 & out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7004 = out_f_rivalid_703; // @[RegisterRouter.scala:87:24] wire out_f_roready_703 = out_roready_1_557 & out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7005 = out_f_roready_703; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_703 = out_wivalid_1_557 & out_wimask_703; // @[RegisterRouter.scala:87:24] wire out_f_woready_703 = out_woready_1_557 & out_womask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7006 = ~out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7007 = ~out_wimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7008 = ~out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7009 = ~out_womask_703; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_596 = {hi_269, flags_0_go, _out_prepend_T_596}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7010 = out_prepend_596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7011 = _out_T_7010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_597 = _out_T_7011; // @[RegisterRouter.scala:87:24] wire out_rimask_704 = \|_out_rimask_T_704; // @[RegisterRouter.scala:87:24] wire out_wimask_704 = &_out_wimask_T_704; // @[RegisterRouter.scala:87:24] wire out_romask_704 = \|_out_romask_T_704; // @[RegisterRouter.scala:87:24] wire out_womask_704 = &_out_womask_T_704; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_704 = out_rivalid_1_558 & out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7013 = out_f_rivalid_704; // @[RegisterRouter.scala:87:24] wire out_f_roready_704 = out_roready_1_558 & out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7014 = out_f_roready_704; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_704 = out_wivalid_1_558 & out_wimask_704; // @[RegisterRouter.scala:87:24] wire out_f_woready_704 = out_woready_1_558 & out_womask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7015 = ~out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7016 = ~out_wimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7017 = ~out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7018 = ~out_womask_704; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_597 = {hi_270, flags_0_go, _out_prepend_T_597}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7019 = out_prepend_597; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7020 = _out_T_7019; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_598 = _out_T_7020; // @[RegisterRouter.scala:87:24] wire out_rimask_705 = \|_out_rimask_T_705; // @[RegisterRouter.scala:87:24] wire out_wimask_705 = &_out_wimask_T_705; // @[RegisterRouter.scala:87:24] wire out_romask_705 = \|_out_romask_T_705; // @[RegisterRouter.scala:87:24] wire out_womask_705 = &_out_womask_T_705; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_705 = out_rivalid_1_559 & out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7022 = out_f_rivalid_705; // @[RegisterRouter.scala:87:24] wire out_f_roready_705 = out_roready_1_559 & out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7023 = out_f_roready_705; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_705 = out_wivalid_1_559 & out_wimask_705; // @[RegisterRouter.scala:87:24] wire out_f_woready_705 = out_woready_1_559 & out_womask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7024 = ~out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7025 = ~out_wimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7026 = ~out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7027 = ~out_womask_705; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_598 = {hi_271, flags_0_go, _out_prepend_T_598}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7028 = out_prepend_598; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7029 = _out_T_7028; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_599 = _out_T_7029; // @[RegisterRouter.scala:87:24] wire out_rimask_706 = \|_out_rimask_T_706; // @[RegisterRouter.scala:87:24] wire out_wimask_706 = &_out_wimask_T_706; // @[RegisterRouter.scala:87:24] wire out_romask_706 = \|_out_romask_T_706; // @[RegisterRouter.scala:87:24] wire out_womask_706 = &_out_womask_T_706; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_706 = out_rivalid_1_560 & out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7031 = out_f_rivalid_706; // @[RegisterRouter.scala:87:24] wire out_f_roready_706 = out_roready_1_560 & out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7032 = out_f_roready_706; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_706 = out_wivalid_1_560 & out_wimask_706; // @[RegisterRouter.scala:87:24] wire out_f_woready_706 = out_woready_1_560 & out_womask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7033 = ~out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7034 = ~out_wimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7035 = ~out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7036 = ~out_womask_706; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_599 = {hi_272, flags_0_go, _out_prepend_T_599}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7037 = out_prepend_599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7038 = _out_T_7037; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_161 = _out_T_7038; // @[MuxLiteral.scala:49:48] wire out_rimask_707 = \|_out_rimask_T_707; // @[RegisterRouter.scala:87:24] wire out_wimask_707 = &_out_wimask_T_707; // @[RegisterRouter.scala:87:24] wire out_romask_707 = \|_out_romask_T_707; // @[RegisterRouter.scala:87:24] wire out_womask_707 = &_out_womask_T_707; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_707 = out_rivalid_1_561 & out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7040 = out_f_rivalid_707; // @[RegisterRouter.scala:87:24] wire out_f_roready_707 = out_roready_1_561 & out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7041 = out_f_roready_707; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_707 = out_wivalid_1_561 & out_wimask_707; // @[RegisterRouter.scala:87:24] wire out_f_woready_707 = out_woready_1_561 & out_womask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7042 = ~out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7043 = ~out_wimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7044 = ~out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7045 = ~out_womask_707; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7047 = _out_T_7046; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_600 = _out_T_7047; // @[RegisterRouter.scala:87:24] wire out_rimask_708 = \|_out_rimask_T_708; // @[RegisterRouter.scala:87:24] wire out_wimask_708 = &_out_wimask_T_708; // @[RegisterRouter.scala:87:24] wire out_romask_708 = \|_out_romask_T_708; // @[RegisterRouter.scala:87:24] wire out_womask_708 = &_out_womask_T_708; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_708 = out_rivalid_1_562 & out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7049 = out_f_rivalid_708; // @[RegisterRouter.scala:87:24] wire out_f_roready_708 = out_roready_1_562 & out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7050 = out_f_roready_708; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_708 = out_wivalid_1_562 & out_wimask_708; // @[RegisterRouter.scala:87:24] wire out_f_woready_708 = out_woready_1_562 & out_womask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7051 = ~out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7052 = ~out_wimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7053 = ~out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7054 = ~out_womask_708; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_600 = {hi_418, flags_0_go, _out_prepend_T_600}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7055 = out_prepend_600; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7056 = _out_T_7055; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_601 = _out_T_7056; // @[RegisterRouter.scala:87:24] wire out_rimask_709 = \|_out_rimask_T_709; // @[RegisterRouter.scala:87:24] wire out_wimask_709 = &_out_wimask_T_709; // @[RegisterRouter.scala:87:24] wire out_romask_709 = \|_out_romask_T_709; // @[RegisterRouter.scala:87:24] wire out_womask_709 = &_out_womask_T_709; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_709 = out_rivalid_1_563 & out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7058 = out_f_rivalid_709; // @[RegisterRouter.scala:87:24] wire out_f_roready_709 = out_roready_1_563 & out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7059 = out_f_roready_709; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_709 = out_wivalid_1_563 & out_wimask_709; // @[RegisterRouter.scala:87:24] wire out_f_woready_709 = out_woready_1_563 & out_womask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7060 = ~out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7061 = ~out_wimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7062 = ~out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7063 = ~out_womask_709; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_601 = {hi_419, flags_0_go, _out_prepend_T_601}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7064 = out_prepend_601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7065 = _out_T_7064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_602 = _out_T_7065; // @[RegisterRouter.scala:87:24] wire out_rimask_710 = \|_out_rimask_T_710; // @[RegisterRouter.scala:87:24] wire out_wimask_710 = &_out_wimask_T_710; // @[RegisterRouter.scala:87:24] wire out_romask_710 = \|_out_romask_T_710; // @[RegisterRouter.scala:87:24] wire out_womask_710 = &_out_womask_T_710; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_710 = out_rivalid_1_564 & out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7067 = out_f_rivalid_710; // @[RegisterRouter.scala:87:24] wire out_f_roready_710 = out_roready_1_564 & out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7068 = out_f_roready_710; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_710 = out_wivalid_1_564 & out_wimask_710; // @[RegisterRouter.scala:87:24] wire out_f_woready_710 = out_woready_1_564 & out_womask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7069 = ~out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7070 = ~out_wimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7071 = ~out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7072 = ~out_womask_710; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_602 = {hi_420, flags_0_go, _out_prepend_T_602}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7073 = out_prepend_602; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7074 = _out_T_7073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_603 = _out_T_7074; // @[RegisterRouter.scala:87:24] wire out_rimask_711 = \|_out_rimask_T_711; // @[RegisterRouter.scala:87:24] wire out_wimask_711 = &_out_wimask_T_711; // @[RegisterRouter.scala:87:24] wire out_romask_711 = \|_out_romask_T_711; // @[RegisterRouter.scala:87:24] wire out_womask_711 = &_out_womask_T_711; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_711 = out_rivalid_1_565 & out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7076 = out_f_rivalid_711; // @[RegisterRouter.scala:87:24] wire out_f_roready_711 = out_roready_1_565 & out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7077 = out_f_roready_711; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_711 = out_wivalid_1_565 & out_wimask_711; // @[RegisterRouter.scala:87:24] wire out_f_woready_711 = out_woready_1_565 & out_womask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7078 = ~out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7079 = ~out_wimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7080 = ~out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7081 = ~out_womask_711; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_603 = {hi_421, flags_0_go, _out_prepend_T_603}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7082 = out_prepend_603; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7083 = _out_T_7082; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_604 = _out_T_7083; // @[RegisterRouter.scala:87:24] wire out_rimask_712 = \|_out_rimask_T_712; // @[RegisterRouter.scala:87:24] wire out_wimask_712 = &_out_wimask_T_712; // @[RegisterRouter.scala:87:24] wire out_romask_712 = \|_out_romask_T_712; // @[RegisterRouter.scala:87:24] wire out_womask_712 = &_out_womask_T_712; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_712 = out_rivalid_1_566 & out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7085 = out_f_rivalid_712; // @[RegisterRouter.scala:87:24] wire out_f_roready_712 = out_roready_1_566 & out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7086 = out_f_roready_712; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_712 = out_wivalid_1_566 & out_wimask_712; // @[RegisterRouter.scala:87:24] wire out_f_woready_712 = out_woready_1_566 & out_womask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7087 = ~out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7088 = ~out_wimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7089 = ~out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7090 = ~out_womask_712; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_604 = {hi_422, flags_0_go, _out_prepend_T_604}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7091 = out_prepend_604; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7092 = _out_T_7091; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_605 = _out_T_7092; // @[RegisterRouter.scala:87:24] wire out_rimask_713 = \|_out_rimask_T_713; // @[RegisterRouter.scala:87:24] wire out_wimask_713 = &_out_wimask_T_713; // @[RegisterRouter.scala:87:24] wire out_romask_713 = \|_out_romask_T_713; // @[RegisterRouter.scala:87:24] wire out_womask_713 = &_out_womask_T_713; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_713 = out_rivalid_1_567 & out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7094 = out_f_rivalid_713; // @[RegisterRouter.scala:87:24] wire out_f_roready_713 = out_roready_1_567 & out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7095 = out_f_roready_713; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_713 = out_wivalid_1_567 & out_wimask_713; // @[RegisterRouter.scala:87:24] wire out_f_woready_713 = out_woready_1_567 & out_womask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7096 = ~out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7097 = ~out_wimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7098 = ~out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7099 = ~out_womask_713; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_605 = {hi_423, flags_0_go, _out_prepend_T_605}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7100 = out_prepend_605; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7101 = _out_T_7100; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_606 = _out_T_7101; // @[RegisterRouter.scala:87:24] wire out_rimask_714 = \|_out_rimask_T_714; // @[RegisterRouter.scala:87:24] wire out_wimask_714 = &_out_wimask_T_714; // @[RegisterRouter.scala:87:24] wire out_romask_714 = \|_out_romask_T_714; // @[RegisterRouter.scala:87:24] wire out_womask_714 = &_out_womask_T_714; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_714 = out_rivalid_1_568 & out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7103 = out_f_rivalid_714; // @[RegisterRouter.scala:87:24] wire out_f_roready_714 = out_roready_1_568 & out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7104 = out_f_roready_714; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_714 = out_wivalid_1_568 & out_wimask_714; // @[RegisterRouter.scala:87:24] wire out_f_woready_714 = out_woready_1_568 & out_womask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7105 = ~out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7106 = ~out_wimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7107 = ~out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7108 = ~out_womask_714; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_606 = {hi_424, flags_0_go, _out_prepend_T_606}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7109 = out_prepend_606; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7110 = _out_T_7109; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_180 = _out_T_7110; // @[MuxLiteral.scala:49:48] wire out_rimask_715 = \|_out_rimask_T_715; // @[RegisterRouter.scala:87:24] wire out_wimask_715 = &_out_wimask_T_715; // @[RegisterRouter.scala:87:24] wire out_romask_715 = \|_out_romask_T_715; // @[RegisterRouter.scala:87:24] wire out_womask_715 = &_out_womask_T_715; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_715 = out_rivalid_1_569 & out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7112 = out_f_rivalid_715; // @[RegisterRouter.scala:87:24] wire out_f_roready_715 = out_roready_1_569 & out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7113 = out_f_roready_715; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_715 = out_wivalid_1_569 & out_wimask_715; // @[RegisterRouter.scala:87:24] wire out_f_woready_715 = out_woready_1_569 & out_womask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7114 = ~out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7115 = ~out_wimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7116 = ~out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7117 = ~out_womask_715; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7119 = _out_T_7118; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_607 = _out_T_7119; // @[RegisterRouter.scala:87:24] wire out_rimask_716 = \|_out_rimask_T_716; // @[RegisterRouter.scala:87:24] wire out_wimask_716 = &_out_wimask_T_716; // @[RegisterRouter.scala:87:24] wire out_romask_716 = \|_out_romask_T_716; // @[RegisterRouter.scala:87:24] wire out_womask_716 = &_out_womask_T_716; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_716 = out_rivalid_1_570 & out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7121 = out_f_rivalid_716; // @[RegisterRouter.scala:87:24] wire out_f_roready_716 = out_roready_1_570 & out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7122 = out_f_roready_716; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_716 = out_wivalid_1_570 & out_wimask_716; // @[RegisterRouter.scala:87:24] wire out_f_woready_716 = out_woready_1_570 & out_womask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7123 = ~out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7124 = ~out_wimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7125 = ~out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7126 = ~out_womask_716; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_607 = {hi_170, flags_0_go, _out_prepend_T_607}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7127 = out_prepend_607; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7128 = _out_T_7127; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_608 = _out_T_7128; // @[RegisterRouter.scala:87:24] wire out_rimask_717 = \|_out_rimask_T_717; // @[RegisterRouter.scala:87:24] wire out_wimask_717 = &_out_wimask_T_717; // @[RegisterRouter.scala:87:24] wire out_romask_717 = \|_out_romask_T_717; // @[RegisterRouter.scala:87:24] wire out_womask_717 = &_out_womask_T_717; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_717 = out_rivalid_1_571 & out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7130 = out_f_rivalid_717; // @[RegisterRouter.scala:87:24] wire out_f_roready_717 = out_roready_1_571 & out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7131 = out_f_roready_717; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_717 = out_wivalid_1_571 & out_wimask_717; // @[RegisterRouter.scala:87:24] wire out_f_woready_717 = out_woready_1_571 & out_womask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7132 = ~out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7133 = ~out_wimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7134 = ~out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7135 = ~out_womask_717; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_608 = {hi_171, flags_0_go, _out_prepend_T_608}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7136 = out_prepend_608; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7137 = _out_T_7136; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_609 = _out_T_7137; // @[RegisterRouter.scala:87:24] wire out_rimask_718 = \|_out_rimask_T_718; // @[RegisterRouter.scala:87:24] wire out_wimask_718 = &_out_wimask_T_718; // @[RegisterRouter.scala:87:24] wire out_romask_718 = \|_out_romask_T_718; // @[RegisterRouter.scala:87:24] wire out_womask_718 = &_out_womask_T_718; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_718 = out_rivalid_1_572 & out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7139 = out_f_rivalid_718; // @[RegisterRouter.scala:87:24] wire out_f_roready_718 = out_roready_1_572 & out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7140 = out_f_roready_718; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_718 = out_wivalid_1_572 & out_wimask_718; // @[RegisterRouter.scala:87:24] wire out_f_woready_718 = out_woready_1_572 & out_womask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7141 = ~out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7142 = ~out_wimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7143 = ~out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7144 = ~out_womask_718; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_609 = {hi_172, flags_0_go, _out_prepend_T_609}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7145 = out_prepend_609; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7146 = _out_T_7145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_610 = _out_T_7146; // @[RegisterRouter.scala:87:24] wire out_rimask_719 = \|_out_rimask_T_719; // @[RegisterRouter.scala:87:24] wire out_wimask_719 = &_out_wimask_T_719; // @[RegisterRouter.scala:87:24] wire out_romask_719 = \|_out_romask_T_719; // @[RegisterRouter.scala:87:24] wire out_womask_719 = &_out_womask_T_719; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_719 = out_rivalid_1_573 & out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7148 = out_f_rivalid_719; // @[RegisterRouter.scala:87:24] wire out_f_roready_719 = out_roready_1_573 & out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7149 = out_f_roready_719; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_719 = out_wivalid_1_573 & out_wimask_719; // @[RegisterRouter.scala:87:24] wire out_f_woready_719 = out_woready_1_573 & out_womask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7150 = ~out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7151 = ~out_wimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7152 = ~out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7153 = ~out_womask_719; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_610 = {hi_173, flags_0_go, _out_prepend_T_610}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7154 = out_prepend_610; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7155 = _out_T_7154; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_611 = _out_T_7155; // @[RegisterRouter.scala:87:24] wire out_rimask_720 = \|_out_rimask_T_720; // @[RegisterRouter.scala:87:24] wire out_wimask_720 = &_out_wimask_T_720; // @[RegisterRouter.scala:87:24] wire out_romask_720 = \|_out_romask_T_720; // @[RegisterRouter.scala:87:24] wire out_womask_720 = &_out_womask_T_720; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_720 = out_rivalid_1_574 & out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7157 = out_f_rivalid_720; // @[RegisterRouter.scala:87:24] wire out_f_roready_720 = out_roready_1_574 & out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7158 = out_f_roready_720; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_720 = out_wivalid_1_574 & out_wimask_720; // @[RegisterRouter.scala:87:24] wire out_f_woready_720 = out_woready_1_574 & out_womask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7159 = ~out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7160 = ~out_wimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7161 = ~out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7162 = ~out_womask_720; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_611 = {hi_174, flags_0_go, _out_prepend_T_611}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7163 = out_prepend_611; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7164 = _out_T_7163; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_612 = _out_T_7164; // @[RegisterRouter.scala:87:24] wire out_rimask_721 = \|_out_rimask_T_721; // @[RegisterRouter.scala:87:24] wire out_wimask_721 = &_out_wimask_T_721; // @[RegisterRouter.scala:87:24] wire out_romask_721 = \|_out_romask_T_721; // @[RegisterRouter.scala:87:24] wire out_womask_721 = &_out_womask_T_721; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_721 = out_rivalid_1_575 & out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7166 = out_f_rivalid_721; // @[RegisterRouter.scala:87:24] wire out_f_roready_721 = out_roready_1_575 & out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7167 = out_f_roready_721; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_721 = out_wivalid_1_575 & out_wimask_721; // @[RegisterRouter.scala:87:24] wire out_f_woready_721 = out_woready_1_575 & out_womask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7168 = ~out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7169 = ~out_wimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7170 = ~out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7171 = ~out_womask_721; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_612 = {hi_175, flags_0_go, _out_prepend_T_612}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7172 = out_prepend_612; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7173 = _out_T_7172; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_613 = _out_T_7173; // @[RegisterRouter.scala:87:24] wire out_rimask_722 = \|_out_rimask_T_722; // @[RegisterRouter.scala:87:24] wire out_wimask_722 = &_out_wimask_T_722; // @[RegisterRouter.scala:87:24] wire out_romask_722 = \|_out_romask_T_722; // @[RegisterRouter.scala:87:24] wire out_womask_722 = &_out_womask_T_722; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_722 = out_rivalid_1_576 & out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7175 = out_f_rivalid_722; // @[RegisterRouter.scala:87:24] wire out_f_roready_722 = out_roready_1_576 & out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7176 = out_f_roready_722; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_722 = out_wivalid_1_576 & out_wimask_722; // @[RegisterRouter.scala:87:24] wire out_f_woready_722 = out_woready_1_576 & out_womask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7177 = ~out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7178 = ~out_wimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7179 = ~out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7180 = ~out_womask_722; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_613 = {hi_176, flags_0_go, _out_prepend_T_613}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7181 = out_prepend_613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7182 = _out_T_7181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_149 = _out_T_7182; // @[MuxLiteral.scala:49:48] wire out_rimask_723 = \|_out_rimask_T_723; // @[RegisterRouter.scala:87:24] wire out_wimask_723 = &_out_wimask_T_723; // @[RegisterRouter.scala:87:24] wire out_romask_723 = \|_out_romask_T_723; // @[RegisterRouter.scala:87:24] wire out_womask_723 = &_out_womask_T_723; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_723 = out_rivalid_1_577 & out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7184 = out_f_rivalid_723; // @[RegisterRouter.scala:87:24] wire out_f_roready_723 = out_roready_1_577 & out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7185 = out_f_roready_723; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_723 = out_wivalid_1_577 & out_wimask_723; // @[RegisterRouter.scala:87:24] wire out_f_woready_723 = out_woready_1_577 & out_womask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7186 = ~out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7187 = ~out_wimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7188 = ~out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7189 = ~out_womask_723; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7191 = _out_T_7190; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_614 = _out_T_7191; // @[RegisterRouter.scala:87:24] wire out_rimask_724 = \|_out_rimask_T_724; // @[RegisterRouter.scala:87:24] wire out_wimask_724 = &_out_wimask_T_724; // @[RegisterRouter.scala:87:24] wire out_romask_724 = \|_out_romask_T_724; // @[RegisterRouter.scala:87:24] wire out_womask_724 = &_out_womask_T_724; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_724 = out_rivalid_1_578 & out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7193 = out_f_rivalid_724; // @[RegisterRouter.scala:87:24] wire out_f_roready_724 = out_roready_1_578 & out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7194 = out_f_roready_724; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_724 = out_wivalid_1_578 & out_wimask_724; // @[RegisterRouter.scala:87:24] wire out_f_woready_724 = out_woready_1_578 & out_womask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7195 = ~out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7196 = ~out_wimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7197 = ~out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7198 = ~out_womask_724; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_614 = {hi_386, flags_0_go, _out_prepend_T_614}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7199 = out_prepend_614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7200 = _out_T_7199; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_615 = _out_T_7200; // @[RegisterRouter.scala:87:24] wire out_rimask_725 = \|_out_rimask_T_725; // @[RegisterRouter.scala:87:24] wire out_wimask_725 = &_out_wimask_T_725; // @[RegisterRouter.scala:87:24] wire out_romask_725 = \|_out_romask_T_725; // @[RegisterRouter.scala:87:24] wire out_womask_725 = &_out_womask_T_725; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_725 = out_rivalid_1_579 & out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7202 = out_f_rivalid_725; // @[RegisterRouter.scala:87:24] wire out_f_roready_725 = out_roready_1_579 & out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7203 = out_f_roready_725; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_725 = out_wivalid_1_579 & out_wimask_725; // @[RegisterRouter.scala:87:24] wire out_f_woready_725 = out_woready_1_579 & out_womask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7204 = ~out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7205 = ~out_wimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7206 = ~out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7207 = ~out_womask_725; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_615 = {hi_387, flags_0_go, _out_prepend_T_615}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7208 = out_prepend_615; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7209 = _out_T_7208; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_616 = _out_T_7209; // @[RegisterRouter.scala:87:24] wire out_rimask_726 = \|_out_rimask_T_726; // @[RegisterRouter.scala:87:24] wire out_wimask_726 = &_out_wimask_T_726; // @[RegisterRouter.scala:87:24] wire out_romask_726 = \|_out_romask_T_726; // @[RegisterRouter.scala:87:24] wire out_womask_726 = &_out_womask_T_726; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_726 = out_rivalid_1_580 & out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7211 = out_f_rivalid_726; // @[RegisterRouter.scala:87:24] wire out_f_roready_726 = out_roready_1_580 & out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7212 = out_f_roready_726; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_726 = out_wivalid_1_580 & out_wimask_726; // @[RegisterRouter.scala:87:24] wire out_f_woready_726 = out_woready_1_580 & out_womask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7213 = ~out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7214 = ~out_wimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7215 = ~out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7216 = ~out_womask_726; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_616 = {hi_388, flags_0_go, _out_prepend_T_616}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7217 = out_prepend_616; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7218 = _out_T_7217; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_617 = _out_T_7218; // @[RegisterRouter.scala:87:24] wire out_rimask_727 = \|_out_rimask_T_727; // @[RegisterRouter.scala:87:24] wire out_wimask_727 = &_out_wimask_T_727; // @[RegisterRouter.scala:87:24] wire out_romask_727 = \|_out_romask_T_727; // @[RegisterRouter.scala:87:24] wire out_womask_727 = &_out_womask_T_727; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_727 = out_rivalid_1_581 & out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7220 = out_f_rivalid_727; // @[RegisterRouter.scala:87:24] wire out_f_roready_727 = out_roready_1_581 & out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7221 = out_f_roready_727; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_727 = out_wivalid_1_581 & out_wimask_727; // @[RegisterRouter.scala:87:24] wire out_f_woready_727 = out_woready_1_581 & out_womask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7222 = ~out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7223 = ~out_wimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7224 = ~out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7225 = ~out_womask_727; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_617 = {hi_389, flags_0_go, _out_prepend_T_617}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7226 = out_prepend_617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7227 = _out_T_7226; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_618 = _out_T_7227; // @[RegisterRouter.scala:87:24] wire out_rimask_728 = \|_out_rimask_T_728; // @[RegisterRouter.scala:87:24] wire out_wimask_728 = &_out_wimask_T_728; // @[RegisterRouter.scala:87:24] wire out_romask_728 = \|_out_romask_T_728; // @[RegisterRouter.scala:87:24] wire out_womask_728 = &_out_womask_T_728; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_728 = out_rivalid_1_582 & out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7229 = out_f_rivalid_728; // @[RegisterRouter.scala:87:24] wire out_f_roready_728 = out_roready_1_582 & out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7230 = out_f_roready_728; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_728 = out_wivalid_1_582 & out_wimask_728; // @[RegisterRouter.scala:87:24] wire out_f_woready_728 = out_woready_1_582 & out_womask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7231 = ~out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7232 = ~out_wimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7233 = ~out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7234 = ~out_womask_728; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_618 = {hi_390, flags_0_go, _out_prepend_T_618}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7235 = out_prepend_618; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7236 = _out_T_7235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_619 = _out_T_7236; // @[RegisterRouter.scala:87:24] wire out_rimask_729 = \|_out_rimask_T_729; // @[RegisterRouter.scala:87:24] wire out_wimask_729 = &_out_wimask_T_729; // @[RegisterRouter.scala:87:24] wire out_romask_729 = \|_out_romask_T_729; // @[RegisterRouter.scala:87:24] wire out_womask_729 = &_out_womask_T_729; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_729 = out_rivalid_1_583 & out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7238 = out_f_rivalid_729; // @[RegisterRouter.scala:87:24] wire out_f_roready_729 = out_roready_1_583 & out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7239 = out_f_roready_729; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_729 = out_wivalid_1_583 & out_wimask_729; // @[RegisterRouter.scala:87:24] wire out_f_woready_729 = out_woready_1_583 & out_womask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7240 = ~out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7241 = ~out_wimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7242 = ~out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7243 = ~out_womask_729; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_619 = {hi_391, flags_0_go, _out_prepend_T_619}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7244 = out_prepend_619; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7245 = _out_T_7244; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_620 = _out_T_7245; // @[RegisterRouter.scala:87:24] wire out_rimask_730 = \|_out_rimask_T_730; // @[RegisterRouter.scala:87:24] wire out_wimask_730 = &_out_wimask_T_730; // @[RegisterRouter.scala:87:24] wire out_romask_730 = \|_out_romask_T_730; // @[RegisterRouter.scala:87:24] wire out_womask_730 = &_out_womask_T_730; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_730 = out_rivalid_1_584 & out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7247 = out_f_rivalid_730; // @[RegisterRouter.scala:87:24] wire out_f_roready_730 = out_roready_1_584 & out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7248 = out_f_roready_730; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_730 = out_wivalid_1_584 & out_wimask_730; // @[RegisterRouter.scala:87:24] wire out_f_woready_730 = out_woready_1_584 & out_womask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7249 = ~out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7250 = ~out_wimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7251 = ~out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7252 = ~out_womask_730; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_620 = {hi_392, flags_0_go, _out_prepend_T_620}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7253 = out_prepend_620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7254 = _out_T_7253; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_176 = _out_T_7254; // @[MuxLiteral.scala:49:48] wire out_rimask_731 = \|_out_rimask_T_731; // @[RegisterRouter.scala:87:24] wire out_wimask_731 = &_out_wimask_T_731; // @[RegisterRouter.scala:87:24] wire out_romask_731 = \|_out_romask_T_731; // @[RegisterRouter.scala:87:24] wire out_womask_731 = &_out_womask_T_731; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_731 = out_rivalid_1_585 & out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7256 = out_f_rivalid_731; // @[RegisterRouter.scala:87:24] wire out_f_roready_731 = out_roready_1_585 & out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7257 = out_f_roready_731; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_731 = out_wivalid_1_585 & out_wimask_731; // @[RegisterRouter.scala:87:24] wire out_f_woready_731 = out_woready_1_585 & out_womask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7258 = ~out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7259 = ~out_wimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7260 = ~out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7261 = ~out_womask_731; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7263 = _out_T_7262; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_621 = _out_T_7263; // @[RegisterRouter.scala:87:24] wire out_rimask_732 = \|_out_rimask_T_732; // @[RegisterRouter.scala:87:24] wire out_wimask_732 = &_out_wimask_T_732; // @[RegisterRouter.scala:87:24] wire out_romask_732 = \|_out_romask_T_732; // @[RegisterRouter.scala:87:24] wire out_womask_732 = &_out_womask_T_732; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_732 = out_rivalid_1_586 & out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7265 = out_f_rivalid_732; // @[RegisterRouter.scala:87:24] wire out_f_roready_732 = out_roready_1_586 & out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7266 = out_f_roready_732; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_732 = out_wivalid_1_586 & out_wimask_732; // @[RegisterRouter.scala:87:24] wire out_f_woready_732 = out_woready_1_586 & out_womask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7267 = ~out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7268 = ~out_wimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7269 = ~out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7270 = ~out_womask_732; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_621 = {hi_506, flags_0_go, _out_prepend_T_621}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7271 = out_prepend_621; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7272 = _out_T_7271; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_622 = _out_T_7272; // @[RegisterRouter.scala:87:24] wire out_rimask_733 = \|_out_rimask_T_733; // @[RegisterRouter.scala:87:24] wire out_wimask_733 = &_out_wimask_T_733; // @[RegisterRouter.scala:87:24] wire out_romask_733 = \|_out_romask_T_733; // @[RegisterRouter.scala:87:24] wire out_womask_733 = &_out_womask_T_733; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_733 = out_rivalid_1_587 & out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7274 = out_f_rivalid_733; // @[RegisterRouter.scala:87:24] wire out_f_roready_733 = out_roready_1_587 & out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7275 = out_f_roready_733; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_733 = out_wivalid_1_587 & out_wimask_733; // @[RegisterRouter.scala:87:24] wire out_f_woready_733 = out_woready_1_587 & out_womask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7276 = ~out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7277 = ~out_wimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7278 = ~out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7279 = ~out_womask_733; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_622 = {hi_507, flags_0_go, _out_prepend_T_622}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7280 = out_prepend_622; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7281 = _out_T_7280; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_623 = _out_T_7281; // @[RegisterRouter.scala:87:24] wire out_rimask_734 = \|_out_rimask_T_734; // @[RegisterRouter.scala:87:24] wire out_wimask_734 = &_out_wimask_T_734; // @[RegisterRouter.scala:87:24] wire out_romask_734 = \|_out_romask_T_734; // @[RegisterRouter.scala:87:24] wire out_womask_734 = &_out_womask_T_734; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_734 = out_rivalid_1_588 & out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7283 = out_f_rivalid_734; // @[RegisterRouter.scala:87:24] wire out_f_roready_734 = out_roready_1_588 & out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7284 = out_f_roready_734; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_734 = out_wivalid_1_588 & out_wimask_734; // @[RegisterRouter.scala:87:24] wire out_f_woready_734 = out_woready_1_588 & out_womask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7285 = ~out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7286 = ~out_wimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7287 = ~out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7288 = ~out_womask_734; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_623 = {hi_508, flags_0_go, _out_prepend_T_623}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7289 = out_prepend_623; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7290 = _out_T_7289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_624 = _out_T_7290; // @[RegisterRouter.scala:87:24] wire out_rimask_735 = \|_out_rimask_T_735; // @[RegisterRouter.scala:87:24] wire out_wimask_735 = &_out_wimask_T_735; // @[RegisterRouter.scala:87:24] wire out_romask_735 = \|_out_romask_T_735; // @[RegisterRouter.scala:87:24] wire out_womask_735 = &_out_womask_T_735; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_735 = out_rivalid_1_589 & out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7292 = out_f_rivalid_735; // @[RegisterRouter.scala:87:24] wire out_f_roready_735 = out_roready_1_589 & out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7293 = out_f_roready_735; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_735 = out_wivalid_1_589 & out_wimask_735; // @[RegisterRouter.scala:87:24] wire out_f_woready_735 = out_woready_1_589 & out_womask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7294 = ~out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7295 = ~out_wimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7296 = ~out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7297 = ~out_womask_735; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_624 = {hi_509, flags_0_go, _out_prepend_T_624}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7298 = out_prepend_624; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7299 = _out_T_7298; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_625 = _out_T_7299; // @[RegisterRouter.scala:87:24] wire out_rimask_736 = \|_out_rimask_T_736; // @[RegisterRouter.scala:87:24] wire out_wimask_736 = &_out_wimask_T_736; // @[RegisterRouter.scala:87:24] wire out_romask_736 = \|_out_romask_T_736; // @[RegisterRouter.scala:87:24] wire out_womask_736 = &_out_womask_T_736; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_736 = out_rivalid_1_590 & out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7301 = out_f_rivalid_736; // @[RegisterRouter.scala:87:24] wire out_f_roready_736 = out_roready_1_590 & out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7302 = out_f_roready_736; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_736 = out_wivalid_1_590 & out_wimask_736; // @[RegisterRouter.scala:87:24] wire out_f_woready_736 = out_woready_1_590 & out_womask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7303 = ~out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7304 = ~out_wimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7305 = ~out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7306 = ~out_womask_736; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_625 = {hi_510, flags_0_go, _out_prepend_T_625}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7307 = out_prepend_625; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7308 = _out_T_7307; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_626 = _out_T_7308; // @[RegisterRouter.scala:87:24] wire out_rimask_737 = \|_out_rimask_T_737; // @[RegisterRouter.scala:87:24] wire out_wimask_737 = &_out_wimask_T_737; // @[RegisterRouter.scala:87:24] wire out_romask_737 = \|_out_romask_T_737; // @[RegisterRouter.scala:87:24] wire out_womask_737 = &_out_womask_T_737; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_737 = out_rivalid_1_591 & out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7310 = out_f_rivalid_737; // @[RegisterRouter.scala:87:24] wire out_f_roready_737 = out_roready_1_591 & out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7311 = out_f_roready_737; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_737 = out_wivalid_1_591 & out_wimask_737; // @[RegisterRouter.scala:87:24] wire out_f_woready_737 = out_woready_1_591 & out_womask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7312 = ~out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7313 = ~out_wimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7314 = ~out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7315 = ~out_womask_737; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_626 = {hi_511, flags_0_go, _out_prepend_T_626}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7316 = out_prepend_626; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7317 = _out_T_7316; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_627 = _out_T_7317; // @[RegisterRouter.scala:87:24] wire out_rimask_738 = \|_out_rimask_T_738; // @[RegisterRouter.scala:87:24] wire out_wimask_738 = &_out_wimask_T_738; // @[RegisterRouter.scala:87:24] wire out_romask_738 = \|_out_romask_T_738; // @[RegisterRouter.scala:87:24] wire out_womask_738 = &_out_womask_T_738; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_738 = out_rivalid_1_592 & out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7319 = out_f_rivalid_738; // @[RegisterRouter.scala:87:24] wire out_f_roready_738 = out_roready_1_592 & out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7320 = out_f_roready_738; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_738 = out_wivalid_1_592 & out_wimask_738; // @[RegisterRouter.scala:87:24] wire out_f_woready_738 = out_woready_1_592 & out_womask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7321 = ~out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7322 = ~out_wimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7323 = ~out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7324 = ~out_womask_738; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_627 = {hi_512, flags_0_go, _out_prepend_T_627}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7325 = out_prepend_627; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7326 = _out_T_7325; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_191 = _out_T_7326; // @[MuxLiteral.scala:49:48] wire out_rimask_739 = \|_out_rimask_T_739; // @[RegisterRouter.scala:87:24] wire out_wimask_739 = &_out_wimask_T_739; // @[RegisterRouter.scala:87:24] wire out_romask_739 = \|_out_romask_T_739; // @[RegisterRouter.scala:87:24] wire out_womask_739 = &_out_womask_T_739; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_739 = out_rivalid_1_593 & out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7328 = out_f_rivalid_739; // @[RegisterRouter.scala:87:24] wire out_f_roready_739 = out_roready_1_593 & out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7329 = out_f_roready_739; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_739 = out_wivalid_1_593 & out_wimask_739; // @[RegisterRouter.scala:87:24] wire out_f_woready_739 = out_woready_1_593 & out_womask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7330 = ~out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7331 = ~out_wimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7332 = ~out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7333 = ~out_womask_739; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7335 = _out_T_7334; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_628 = _out_T_7335; // @[RegisterRouter.scala:87:24] wire out_rimask_740 = \|_out_rimask_T_740; // @[RegisterRouter.scala:87:24] wire out_wimask_740 = &_out_wimask_T_740; // @[RegisterRouter.scala:87:24] wire out_romask_740 = \|_out_romask_T_740; // @[RegisterRouter.scala:87:24] wire out_womask_740 = &_out_womask_T_740; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_740 = out_rivalid_1_594 & out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7337 = out_f_rivalid_740; // @[RegisterRouter.scala:87:24] wire out_f_roready_740 = out_roready_1_594 & out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7338 = out_f_roready_740; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_740 = out_wivalid_1_594 & out_wimask_740; // @[RegisterRouter.scala:87:24] wire out_f_woready_740 = out_woready_1_594 & out_womask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7339 = ~out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7340 = ~out_wimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7341 = ~out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7342 = ~out_womask_740; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_628 = {hi_610, flags_0_go, _out_prepend_T_628}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7343 = out_prepend_628; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7344 = _out_T_7343; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_629 = _out_T_7344; // @[RegisterRouter.scala:87:24] wire out_rimask_741 = \|_out_rimask_T_741; // @[RegisterRouter.scala:87:24] wire out_wimask_741 = &_out_wimask_T_741; // @[RegisterRouter.scala:87:24] wire out_romask_741 = \|_out_romask_T_741; // @[RegisterRouter.scala:87:24] wire out_womask_741 = &_out_womask_T_741; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_741 = out_rivalid_1_595 & out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7346 = out_f_rivalid_741; // @[RegisterRouter.scala:87:24] wire out_f_roready_741 = out_roready_1_595 & out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7347 = out_f_roready_741; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_741 = out_wivalid_1_595 & out_wimask_741; // @[RegisterRouter.scala:87:24] wire out_f_woready_741 = out_woready_1_595 & out_womask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7348 = ~out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7349 = ~out_wimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7350 = ~out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7351 = ~out_womask_741; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_629 = {hi_611, flags_0_go, _out_prepend_T_629}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7352 = out_prepend_629; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7353 = _out_T_7352; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_630 = _out_T_7353; // @[RegisterRouter.scala:87:24] wire out_rimask_742 = \|_out_rimask_T_742; // @[RegisterRouter.scala:87:24] wire out_wimask_742 = &_out_wimask_T_742; // @[RegisterRouter.scala:87:24] wire out_romask_742 = \|_out_romask_T_742; // @[RegisterRouter.scala:87:24] wire out_womask_742 = &_out_womask_T_742; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_742 = out_rivalid_1_596 & out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7355 = out_f_rivalid_742; // @[RegisterRouter.scala:87:24] wire out_f_roready_742 = out_roready_1_596 & out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7356 = out_f_roready_742; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_742 = out_wivalid_1_596 & out_wimask_742; // @[RegisterRouter.scala:87:24] wire out_f_woready_742 = out_woready_1_596 & out_womask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7357 = ~out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7358 = ~out_wimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7359 = ~out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7360 = ~out_womask_742; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_630 = {hi_612, flags_0_go, _out_prepend_T_630}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7361 = out_prepend_630; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7362 = _out_T_7361; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_631 = _out_T_7362; // @[RegisterRouter.scala:87:24] wire out_rimask_743 = \|_out_rimask_T_743; // @[RegisterRouter.scala:87:24] wire out_wimask_743 = &_out_wimask_T_743; // @[RegisterRouter.scala:87:24] wire out_romask_743 = \|_out_romask_T_743; // @[RegisterRouter.scala:87:24] wire out_womask_743 = &_out_womask_T_743; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_743 = out_rivalid_1_597 & out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7364 = out_f_rivalid_743; // @[RegisterRouter.scala:87:24] wire out_f_roready_743 = out_roready_1_597 & out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7365 = out_f_roready_743; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_743 = out_wivalid_1_597 & out_wimask_743; // @[RegisterRouter.scala:87:24] wire out_f_woready_743 = out_woready_1_597 & out_womask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7366 = ~out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7367 = ~out_wimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7368 = ~out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7369 = ~out_womask_743; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_631 = {hi_613, flags_0_go, _out_prepend_T_631}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7370 = out_prepend_631; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7371 = _out_T_7370; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_632 = _out_T_7371; // @[RegisterRouter.scala:87:24] wire out_rimask_744 = \|_out_rimask_T_744; // @[RegisterRouter.scala:87:24] wire out_wimask_744 = &_out_wimask_T_744; // @[RegisterRouter.scala:87:24] wire out_romask_744 = \|_out_romask_T_744; // @[RegisterRouter.scala:87:24] wire out_womask_744 = &_out_womask_T_744; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_744 = out_rivalid_1_598 & out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7373 = out_f_rivalid_744; // @[RegisterRouter.scala:87:24] wire out_f_roready_744 = out_roready_1_598 & out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7374 = out_f_roready_744; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_744 = out_wivalid_1_598 & out_wimask_744; // @[RegisterRouter.scala:87:24] wire out_f_woready_744 = out_woready_1_598 & out_womask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7375 = ~out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7376 = ~out_wimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7377 = ~out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7378 = ~out_womask_744; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_632 = {hi_614, flags_0_go, _out_prepend_T_632}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7379 = out_prepend_632; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7380 = _out_T_7379; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_633 = _out_T_7380; // @[RegisterRouter.scala:87:24] wire out_rimask_745 = \|_out_rimask_T_745; // @[RegisterRouter.scala:87:24] wire out_wimask_745 = &_out_wimask_T_745; // @[RegisterRouter.scala:87:24] wire out_romask_745 = \|_out_romask_T_745; // @[RegisterRouter.scala:87:24] wire out_womask_745 = &_out_womask_T_745; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_745 = out_rivalid_1_599 & out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7382 = out_f_rivalid_745; // @[RegisterRouter.scala:87:24] wire out_f_roready_745 = out_roready_1_599 & out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7383 = out_f_roready_745; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_745 = out_wivalid_1_599 & out_wimask_745; // @[RegisterRouter.scala:87:24] wire out_f_woready_745 = out_woready_1_599 & out_womask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7384 = ~out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7385 = ~out_wimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7386 = ~out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7387 = ~out_womask_745; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_633 = {hi_615, flags_0_go, _out_prepend_T_633}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7388 = out_prepend_633; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7389 = _out_T_7388; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_634 = _out_T_7389; // @[RegisterRouter.scala:87:24] wire out_rimask_746 = \|_out_rimask_T_746; // @[RegisterRouter.scala:87:24] wire out_wimask_746 = &_out_wimask_T_746; // @[RegisterRouter.scala:87:24] wire out_romask_746 = \|_out_romask_T_746; // @[RegisterRouter.scala:87:24] wire out_womask_746 = &_out_womask_T_746; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_746 = out_rivalid_1_600 & out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7391 = out_f_rivalid_746; // @[RegisterRouter.scala:87:24] wire out_f_roready_746 = out_roready_1_600 & out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7392 = out_f_roready_746; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_746 = out_wivalid_1_600 & out_wimask_746; // @[RegisterRouter.scala:87:24] wire out_f_woready_746 = out_woready_1_600 & out_womask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7393 = ~out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7394 = ~out_wimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7395 = ~out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7396 = ~out_womask_746; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_634 = {hi_616, flags_0_go, _out_prepend_T_634}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7397 = out_prepend_634; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7398 = _out_T_7397; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_204 = _out_T_7398; // @[MuxLiteral.scala:49:48] wire out_rimask_747 = \|_out_rimask_T_747; // @[RegisterRouter.scala:87:24] wire out_wimask_747 = &_out_wimask_T_747; // @[RegisterRouter.scala:87:24] wire out_romask_747 = \|_out_romask_T_747; // @[RegisterRouter.scala:87:24] wire out_womask_747 = &_out_womask_T_747; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_747 = out_rivalid_1_601 & out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7400 = out_f_rivalid_747; // @[RegisterRouter.scala:87:24] wire out_f_roready_747 = out_roready_1_601 & out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7401 = out_f_roready_747; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_747 = out_wivalid_1_601 & out_wimask_747; // @[RegisterRouter.scala:87:24] wire out_f_woready_747 = out_woready_1_601 & out_womask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7402 = ~out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7403 = ~out_wimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7404 = ~out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7405 = ~out_womask_747; // @[RegisterRouter.scala:87:24] wire out_rimask_748 = \|_out_rimask_T_748; // @[RegisterRouter.scala:87:24] wire out_wimask_748 = &_out_wimask_T_748; // @[RegisterRouter.scala:87:24] wire out_romask_748 = \|_out_romask_T_748; // @[RegisterRouter.scala:87:24] wire out_womask_748 = &_out_womask_T_748; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_748 = out_rivalid_1_602 & out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7409 = out_f_rivalid_748; // @[RegisterRouter.scala:87:24] wire out_f_roready_748 = out_roready_1_602 & out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7410 = out_f_roready_748; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_748 = out_wivalid_1_602 & out_wimask_748; // @[RegisterRouter.scala:87:24] wire out_f_woready_748 = out_woready_1_602 & out_womask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7411 = ~out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7412 = ~out_wimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7413 = ~out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7414 = ~out_womask_748; // @[RegisterRouter.scala:87:24] wire out_rimask_749 = \|_out_rimask_T_749; // @[RegisterRouter.scala:87:24] wire out_wimask_749 = &_out_wimask_T_749; // @[RegisterRouter.scala:87:24] wire out_romask_749 = \|_out_romask_T_749; // @[RegisterRouter.scala:87:24] wire out_womask_749 = &_out_womask_T_749; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_749 = out_rivalid_1_603 & out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7418 = out_f_rivalid_749; // @[RegisterRouter.scala:87:24] wire out_f_roready_749 = out_roready_1_603 & out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7419 = out_f_roready_749; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_749 = out_wivalid_1_603 & out_wimask_749; // @[RegisterRouter.scala:87:24] wire out_f_woready_749 = out_woready_1_603 & out_womask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7420 = ~out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7421 = ~out_wimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7422 = ~out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7423 = ~out_womask_749; // @[RegisterRouter.scala:87:24] wire out_rimask_750 = \|_out_rimask_T_750; // @[RegisterRouter.scala:87:24] wire out_wimask_750 = &_out_wimask_T_750; // @[RegisterRouter.scala:87:24] wire out_romask_750 = \|_out_romask_T_750; // @[RegisterRouter.scala:87:24] wire out_womask_750 = &_out_womask_T_750; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_750 = out_rivalid_1_604 & out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7427 = out_f_rivalid_750; // @[RegisterRouter.scala:87:24] wire out_f_roready_750 = out_roready_1_604 & out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7428 = out_f_roready_750; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_750 = out_wivalid_1_604 & out_wimask_750; // @[RegisterRouter.scala:87:24] wire out_f_woready_750 = out_woready_1_604 & out_womask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7429 = ~out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7430 = ~out_wimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7431 = ~out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7432 = ~out_womask_750; // @[RegisterRouter.scala:87:24] wire out_rimask_751 = \|_out_rimask_T_751; // @[RegisterRouter.scala:87:24] wire out_wimask_751 = &_out_wimask_T_751; // @[RegisterRouter.scala:87:24] wire out_romask_751 = \|_out_romask_T_751; // @[RegisterRouter.scala:87:24] wire out_womask_751 = &_out_womask_T_751; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_751 = out_rivalid_1_605 & out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7436 = out_f_rivalid_751; // @[RegisterRouter.scala:87:24] wire out_f_roready_751 = out_roready_1_605 & out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7437 = out_f_roready_751; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_751 = out_wivalid_1_605 & out_wimask_751; // @[RegisterRouter.scala:87:24] wire out_f_woready_751 = out_woready_1_605 & out_womask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7438 = ~out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7439 = ~out_wimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7440 = ~out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7441 = ~out_womask_751; // @[RegisterRouter.scala:87:24] wire out_rimask_752 = \|_out_rimask_T_752; // @[RegisterRouter.scala:87:24] wire out_wimask_752 = &_out_wimask_T_752; // @[RegisterRouter.scala:87:24] wire out_romask_752 = \|_out_romask_T_752; // @[RegisterRouter.scala:87:24] wire out_womask_752 = &_out_womask_T_752; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_752 = out_rivalid_1_606 & out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7445 = out_f_rivalid_752; // @[RegisterRouter.scala:87:24] wire out_f_roready_752 = out_roready_1_606 & out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7446 = out_f_roready_752; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_752 = out_wivalid_1_606 & out_wimask_752; // @[RegisterRouter.scala:87:24] wire out_f_woready_752 = out_woready_1_606 & out_womask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7447 = ~out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7448 = ~out_wimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7449 = ~out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7450 = ~out_womask_752; // @[RegisterRouter.scala:87:24] wire out_rimask_753 = \|_out_rimask_T_753; // @[RegisterRouter.scala:87:24] wire out_wimask_753 = &_out_wimask_T_753; // @[RegisterRouter.scala:87:24] wire out_romask_753 = \|_out_romask_T_753; // @[RegisterRouter.scala:87:24] wire out_womask_753 = &_out_womask_T_753; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_753 = out_rivalid_1_607 & out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7454 = out_f_rivalid_753; // @[RegisterRouter.scala:87:24] wire out_f_roready_753 = out_roready_1_607 & out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7455 = out_f_roready_753; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_753 = out_wivalid_1_607 & out_wimask_753; // @[RegisterRouter.scala:87:24] wire out_f_woready_753 = out_woready_1_607 & out_womask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7456 = ~out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7457 = ~out_wimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7458 = ~out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7459 = ~out_womask_753; // @[RegisterRouter.scala:87:24] wire out_rimask_754 = \|_out_rimask_T_754; // @[RegisterRouter.scala:87:24] wire out_wimask_754 = &_out_wimask_T_754; // @[RegisterRouter.scala:87:24] wire out_romask_754 = \|_out_romask_T_754; // @[RegisterRouter.scala:87:24] wire out_womask_754 = &_out_womask_T_754; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_754 = out_rivalid_1_608 & out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7463 = out_f_rivalid_754; // @[RegisterRouter.scala:87:24] wire out_f_roready_754 = out_roready_1_608 & out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7464 = out_f_roready_754; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_754 = out_wivalid_1_608 & out_wimask_754; // @[RegisterRouter.scala:87:24] wire out_f_woready_754 = out_woready_1_608 & out_womask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7465 = ~out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7466 = ~out_wimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7467 = ~out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7468 = ~out_womask_754; // @[RegisterRouter.scala:87:24] wire out_rimask_755 = \|_out_rimask_T_755; // @[RegisterRouter.scala:87:24] wire out_wimask_755 = &_out_wimask_T_755; // @[RegisterRouter.scala:87:24] wire out_romask_755 = \|_out_romask_T_755; // @[RegisterRouter.scala:87:24] wire out_womask_755 = &_out_womask_T_755; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_755 = out_rivalid_1_609 & out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7472 = out_f_rivalid_755; // @[RegisterRouter.scala:87:24] wire out_f_roready_755 = out_roready_1_609 & out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7473 = out_f_roready_755; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_755 = out_wivalid_1_609 & out_wimask_755; // @[RegisterRouter.scala:87:24] wire out_f_woready_755 = out_woready_1_609 & out_womask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7474 = ~out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7475 = ~out_wimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7476 = ~out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7477 = ~out_womask_755; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7479 = _out_T_7478; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_642 = _out_T_7479; // @[RegisterRouter.scala:87:24] wire out_rimask_756 = \|_out_rimask_T_756; // @[RegisterRouter.scala:87:24] wire out_wimask_756 = &_out_wimask_T_756; // @[RegisterRouter.scala:87:24] wire out_romask_756 = \|_out_romask_T_756; // @[RegisterRouter.scala:87:24] wire out_womask_756 = &_out_womask_T_756; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_756 = out_rivalid_1_610 & out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7481 = out_f_rivalid_756; // @[RegisterRouter.scala:87:24] wire out_f_roready_756 = out_roready_1_610 & out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7482 = out_f_roready_756; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_756 = out_wivalid_1_610 & out_wimask_756; // @[RegisterRouter.scala:87:24] wire out_f_woready_756 = out_woready_1_610 & out_womask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7483 = ~out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7484 = ~out_wimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7485 = ~out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7486 = ~out_womask_756; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_642 = {hi_130, flags_0_go, _out_prepend_T_642}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7487 = out_prepend_642; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7488 = _out_T_7487; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_643 = _out_T_7488; // @[RegisterRouter.scala:87:24] wire out_rimask_757 = \|_out_rimask_T_757; // @[RegisterRouter.scala:87:24] wire out_wimask_757 = &_out_wimask_T_757; // @[RegisterRouter.scala:87:24] wire out_romask_757 = \|_out_romask_T_757; // @[RegisterRouter.scala:87:24] wire out_womask_757 = &_out_womask_T_757; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_757 = out_rivalid_1_611 & out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7490 = out_f_rivalid_757; // @[RegisterRouter.scala:87:24] wire out_f_roready_757 = out_roready_1_611 & out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7491 = out_f_roready_757; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_757 = out_wivalid_1_611 & out_wimask_757; // @[RegisterRouter.scala:87:24] wire out_f_woready_757 = out_woready_1_611 & out_womask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7492 = ~out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7493 = ~out_wimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7494 = ~out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7495 = ~out_womask_757; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_643 = {hi_131, flags_0_go, _out_prepend_T_643}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7496 = out_prepend_643; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7497 = _out_T_7496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_644 = _out_T_7497; // @[RegisterRouter.scala:87:24] wire out_rimask_758 = \|_out_rimask_T_758; // @[RegisterRouter.scala:87:24] wire out_wimask_758 = &_out_wimask_T_758; // @[RegisterRouter.scala:87:24] wire out_romask_758 = \|_out_romask_T_758; // @[RegisterRouter.scala:87:24] wire out_womask_758 = &_out_womask_T_758; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_758 = out_rivalid_1_612 & out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7499 = out_f_rivalid_758; // @[RegisterRouter.scala:87:24] wire out_f_roready_758 = out_roready_1_612 & out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7500 = out_f_roready_758; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_758 = out_wivalid_1_612 & out_wimask_758; // @[RegisterRouter.scala:87:24] wire out_f_woready_758 = out_woready_1_612 & out_womask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7501 = ~out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7502 = ~out_wimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7503 = ~out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7504 = ~out_womask_758; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_644 = {hi_132, flags_0_go, _out_prepend_T_644}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7505 = out_prepend_644; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7506 = _out_T_7505; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_645 = _out_T_7506; // @[RegisterRouter.scala:87:24] wire out_rimask_759 = \|_out_rimask_T_759; // @[RegisterRouter.scala:87:24] wire out_wimask_759 = &_out_wimask_T_759; // @[RegisterRouter.scala:87:24] wire out_romask_759 = \|_out_romask_T_759; // @[RegisterRouter.scala:87:24] wire out_womask_759 = &_out_womask_T_759; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_759 = out_rivalid_1_613 & out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7508 = out_f_rivalid_759; // @[RegisterRouter.scala:87:24] wire out_f_roready_759 = out_roready_1_613 & out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7509 = out_f_roready_759; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_759 = out_wivalid_1_613 & out_wimask_759; // @[RegisterRouter.scala:87:24] wire out_f_woready_759 = out_woready_1_613 & out_womask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7510 = ~out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7511 = ~out_wimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7512 = ~out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7513 = ~out_womask_759; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_645 = {hi_133, flags_0_go, _out_prepend_T_645}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7514 = out_prepend_645; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7515 = _out_T_7514; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_646 = _out_T_7515; // @[RegisterRouter.scala:87:24] wire out_rimask_760 = \|_out_rimask_T_760; // @[RegisterRouter.scala:87:24] wire out_wimask_760 = &_out_wimask_T_760; // @[RegisterRouter.scala:87:24] wire out_romask_760 = \|_out_romask_T_760; // @[RegisterRouter.scala:87:24] wire out_womask_760 = &_out_womask_T_760; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_760 = out_rivalid_1_614 & out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7517 = out_f_rivalid_760; // @[RegisterRouter.scala:87:24] wire out_f_roready_760 = out_roready_1_614 & out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7518 = out_f_roready_760; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_760 = out_wivalid_1_614 & out_wimask_760; // @[RegisterRouter.scala:87:24] wire out_f_woready_760 = out_woready_1_614 & out_womask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7519 = ~out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7520 = ~out_wimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7521 = ~out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7522 = ~out_womask_760; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_646 = {hi_134, flags_0_go, _out_prepend_T_646}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7523 = out_prepend_646; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7524 = _out_T_7523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_647 = _out_T_7524; // @[RegisterRouter.scala:87:24] wire out_rimask_761 = \|_out_rimask_T_761; // @[RegisterRouter.scala:87:24] wire out_wimask_761 = &_out_wimask_T_761; // @[RegisterRouter.scala:87:24] wire out_romask_761 = \|_out_romask_T_761; // @[RegisterRouter.scala:87:24] wire out_womask_761 = &_out_womask_T_761; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_761 = out_rivalid_1_615 & out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7526 = out_f_rivalid_761; // @[RegisterRouter.scala:87:24] wire out_f_roready_761 = out_roready_1_615 & out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7527 = out_f_roready_761; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_761 = out_wivalid_1_615 & out_wimask_761; // @[RegisterRouter.scala:87:24] wire out_f_woready_761 = out_woready_1_615 & out_womask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7528 = ~out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7529 = ~out_wimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7530 = ~out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7531 = ~out_womask_761; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_647 = {hi_135, flags_0_go, _out_prepend_T_647}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7532 = out_prepend_647; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7533 = _out_T_7532; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_648 = _out_T_7533; // @[RegisterRouter.scala:87:24] wire out_rimask_762 = \|_out_rimask_T_762; // @[RegisterRouter.scala:87:24] wire out_wimask_762 = &_out_wimask_T_762; // @[RegisterRouter.scala:87:24] wire out_romask_762 = \|_out_romask_T_762; // @[RegisterRouter.scala:87:24] wire out_womask_762 = &_out_womask_T_762; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_762 = out_rivalid_1_616 & out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7535 = out_f_rivalid_762; // @[RegisterRouter.scala:87:24] wire out_f_roready_762 = out_roready_1_616 & out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7536 = out_f_roready_762; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_762 = out_wivalid_1_616 & out_wimask_762; // @[RegisterRouter.scala:87:24] wire out_f_woready_762 = out_woready_1_616 & out_womask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7537 = ~out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7538 = ~out_wimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7539 = ~out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7540 = ~out_womask_762; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_648 = {hi_136, flags_0_go, _out_prepend_T_648}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7541 = out_prepend_648; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7542 = _out_T_7541; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_144 = _out_T_7542; // @[MuxLiteral.scala:49:48] wire out_rimask_763 = \|_out_rimask_T_763; // @[RegisterRouter.scala:87:24] wire out_wimask_763 = &_out_wimask_T_763; // @[RegisterRouter.scala:87:24] wire out_romask_763 = \|_out_romask_T_763; // @[RegisterRouter.scala:87:24] wire out_womask_763 = &_out_womask_T_763; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_763 = out_rivalid_1_617 & out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7544 = out_f_rivalid_763; // @[RegisterRouter.scala:87:24] wire out_f_roready_763 = out_roready_1_617 & out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7545 = out_f_roready_763; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_763 = out_wivalid_1_617 & out_wimask_763; // @[RegisterRouter.scala:87:24] wire out_f_woready_763 = out_woready_1_617 & out_womask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7546 = ~out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7547 = ~out_wimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7548 = ~out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7549 = ~out_womask_763; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7551 = _out_T_7550; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_649 = _out_T_7551; // @[RegisterRouter.scala:87:24] wire out_rimask_764 = \|_out_rimask_T_764; // @[RegisterRouter.scala:87:24] wire out_wimask_764 = &_out_wimask_T_764; // @[RegisterRouter.scala:87:24] wire out_romask_764 = \|_out_romask_T_764; // @[RegisterRouter.scala:87:24] wire out_womask_764 = &_out_womask_T_764; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_764 = out_rivalid_1_618 & out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7553 = out_f_rivalid_764; // @[RegisterRouter.scala:87:24] wire out_f_roready_764 = out_roready_1_618 & out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7554 = out_f_roready_764; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_764 = out_wivalid_1_618 & out_wimask_764; // @[RegisterRouter.scala:87:24] wire out_f_woready_764 = out_woready_1_618 & out_womask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7555 = ~out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7556 = ~out_wimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7557 = ~out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7558 = ~out_womask_764; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_649 = {hi_866, flags_0_go, _out_prepend_T_649}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7559 = out_prepend_649; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7560 = _out_T_7559; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_650 = _out_T_7560; // @[RegisterRouter.scala:87:24] wire out_rimask_765 = \|_out_rimask_T_765; // @[RegisterRouter.scala:87:24] wire out_wimask_765 = &_out_wimask_T_765; // @[RegisterRouter.scala:87:24] wire out_romask_765 = \|_out_romask_T_765; // @[RegisterRouter.scala:87:24] wire out_womask_765 = &_out_womask_T_765; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_765 = out_rivalid_1_619 & out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7562 = out_f_rivalid_765; // @[RegisterRouter.scala:87:24] wire out_f_roready_765 = out_roready_1_619 & out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7563 = out_f_roready_765; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_765 = out_wivalid_1_619 & out_wimask_765; // @[RegisterRouter.scala:87:24] wire out_f_woready_765 = out_woready_1_619 & out_womask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7564 = ~out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7565 = ~out_wimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7566 = ~out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7567 = ~out_womask_765; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_650 = {hi_867, flags_0_go, _out_prepend_T_650}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7568 = out_prepend_650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7569 = _out_T_7568; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_651 = _out_T_7569; // @[RegisterRouter.scala:87:24] wire out_rimask_766 = \|_out_rimask_T_766; // @[RegisterRouter.scala:87:24] wire out_wimask_766 = &_out_wimask_T_766; // @[RegisterRouter.scala:87:24] wire out_romask_766 = \|_out_romask_T_766; // @[RegisterRouter.scala:87:24] wire out_womask_766 = &_out_womask_T_766; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_766 = out_rivalid_1_620 & out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7571 = out_f_rivalid_766; // @[RegisterRouter.scala:87:24] wire out_f_roready_766 = out_roready_1_620 & out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7572 = out_f_roready_766; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_766 = out_wivalid_1_620 & out_wimask_766; // @[RegisterRouter.scala:87:24] wire out_f_woready_766 = out_woready_1_620 & out_womask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7573 = ~out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7574 = ~out_wimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7575 = ~out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7576 = ~out_womask_766; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_651 = {hi_868, flags_0_go, _out_prepend_T_651}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7577 = out_prepend_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7578 = _out_T_7577; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_652 = _out_T_7578; // @[RegisterRouter.scala:87:24] wire out_rimask_767 = \|_out_rimask_T_767; // @[RegisterRouter.scala:87:24] wire out_wimask_767 = &_out_wimask_T_767; // @[RegisterRouter.scala:87:24] wire out_romask_767 = \|_out_romask_T_767; // @[RegisterRouter.scala:87:24] wire out_womask_767 = &_out_womask_T_767; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_767 = out_rivalid_1_621 & out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7580 = out_f_rivalid_767; // @[RegisterRouter.scala:87:24] wire out_f_roready_767 = out_roready_1_621 & out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7581 = out_f_roready_767; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_767 = out_wivalid_1_621 & out_wimask_767; // @[RegisterRouter.scala:87:24] wire out_f_woready_767 = out_woready_1_621 & out_womask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7582 = ~out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7583 = ~out_wimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7584 = ~out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7585 = ~out_womask_767; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_652 = {hi_869, flags_0_go, _out_prepend_T_652}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7586 = out_prepend_652; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7587 = _out_T_7586; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_653 = _out_T_7587; // @[RegisterRouter.scala:87:24] wire out_rimask_768 = \|_out_rimask_T_768; // @[RegisterRouter.scala:87:24] wire out_wimask_768 = &_out_wimask_T_768; // @[RegisterRouter.scala:87:24] wire out_romask_768 = \|_out_romask_T_768; // @[RegisterRouter.scala:87:24] wire out_womask_768 = &_out_womask_T_768; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_768 = out_rivalid_1_622 & out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7589 = out_f_rivalid_768; // @[RegisterRouter.scala:87:24] wire out_f_roready_768 = out_roready_1_622 & out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7590 = out_f_roready_768; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_768 = out_wivalid_1_622 & out_wimask_768; // @[RegisterRouter.scala:87:24] wire out_f_woready_768 = out_woready_1_622 & out_womask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7591 = ~out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7592 = ~out_wimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7593 = ~out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7594 = ~out_womask_768; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_653 = {hi_870, flags_0_go, _out_prepend_T_653}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7595 = out_prepend_653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7596 = _out_T_7595; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_654 = _out_T_7596; // @[RegisterRouter.scala:87:24] wire out_rimask_769 = \|_out_rimask_T_769; // @[RegisterRouter.scala:87:24] wire out_wimask_769 = &_out_wimask_T_769; // @[RegisterRouter.scala:87:24] wire out_romask_769 = \|_out_romask_T_769; // @[RegisterRouter.scala:87:24] wire out_womask_769 = &_out_womask_T_769; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_769 = out_rivalid_1_623 & out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7598 = out_f_rivalid_769; // @[RegisterRouter.scala:87:24] wire out_f_roready_769 = out_roready_1_623 & out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7599 = out_f_roready_769; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_769 = out_wivalid_1_623 & out_wimask_769; // @[RegisterRouter.scala:87:24] wire out_f_woready_769 = out_woready_1_623 & out_womask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7600 = ~out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7601 = ~out_wimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7602 = ~out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7603 = ~out_womask_769; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_654 = {hi_871, flags_0_go, _out_prepend_T_654}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7604 = out_prepend_654; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7605 = _out_T_7604; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_655 = _out_T_7605; // @[RegisterRouter.scala:87:24] wire out_rimask_770 = \|_out_rimask_T_770; // @[RegisterRouter.scala:87:24] wire out_wimask_770 = &_out_wimask_T_770; // @[RegisterRouter.scala:87:24] wire out_romask_770 = \|_out_romask_T_770; // @[RegisterRouter.scala:87:24] wire out_womask_770 = &_out_womask_T_770; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_770 = out_rivalid_1_624 & out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7607 = out_f_rivalid_770; // @[RegisterRouter.scala:87:24] wire out_f_roready_770 = out_roready_1_624 & out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7608 = out_f_roready_770; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_770 = out_wivalid_1_624 & out_wimask_770; // @[RegisterRouter.scala:87:24] wire out_f_woready_770 = out_woready_1_624 & out_womask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7609 = ~out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7610 = ~out_wimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7611 = ~out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7612 = ~out_womask_770; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_655 = {hi_872, flags_0_go, _out_prepend_T_655}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7613 = out_prepend_655; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7614 = _out_T_7613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_236 = _out_T_7614; // @[MuxLiteral.scala:49:48] wire out_rimask_771 = \|_out_rimask_T_771; // @[RegisterRouter.scala:87:24] wire out_wimask_771 = &_out_wimask_T_771; // @[RegisterRouter.scala:87:24] wire out_romask_771 = \|_out_romask_T_771; // @[RegisterRouter.scala:87:24] wire out_womask_771 = &_out_womask_T_771; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_771 = out_rivalid_1_625 & out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7616 = out_f_rivalid_771; // @[RegisterRouter.scala:87:24] wire out_f_roready_771 = out_roready_1_625 & out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7617 = out_f_roready_771; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_771 = out_wivalid_1_625 & out_wimask_771; // @[RegisterRouter.scala:87:24] wire out_f_woready_771 = out_woready_1_625 & out_womask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7618 = ~out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7619 = ~out_wimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7620 = ~out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7621 = ~out_womask_771; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7623 = _out_T_7622; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_656 = _out_T_7623; // @[RegisterRouter.scala:87:24] wire out_rimask_772 = \|_out_rimask_T_772; // @[RegisterRouter.scala:87:24] wire out_wimask_772 = &_out_wimask_T_772; // @[RegisterRouter.scala:87:24] wire out_romask_772 = \|_out_romask_T_772; // @[RegisterRouter.scala:87:24] wire out_womask_772 = &_out_womask_T_772; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_772 = out_rivalid_1_626 & out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7625 = out_f_rivalid_772; // @[RegisterRouter.scala:87:24] wire out_f_roready_772 = out_roready_1_626 & out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7626 = out_f_roready_772; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_772 = out_wivalid_1_626 & out_wimask_772; // @[RegisterRouter.scala:87:24] wire out_f_woready_772 = out_woready_1_626 & out_womask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7627 = ~out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7628 = ~out_wimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7629 = ~out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7630 = ~out_womask_772; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_656 = {hi_426, flags_0_go, _out_prepend_T_656}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7631 = out_prepend_656; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7632 = _out_T_7631; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_657 = _out_T_7632; // @[RegisterRouter.scala:87:24] wire out_rimask_773 = \|_out_rimask_T_773; // @[RegisterRouter.scala:87:24] wire out_wimask_773 = &_out_wimask_T_773; // @[RegisterRouter.scala:87:24] wire out_romask_773 = \|_out_romask_T_773; // @[RegisterRouter.scala:87:24] wire out_womask_773 = &_out_womask_T_773; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_773 = out_rivalid_1_627 & out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7634 = out_f_rivalid_773; // @[RegisterRouter.scala:87:24] wire out_f_roready_773 = out_roready_1_627 & out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7635 = out_f_roready_773; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_773 = out_wivalid_1_627 & out_wimask_773; // @[RegisterRouter.scala:87:24] wire out_f_woready_773 = out_woready_1_627 & out_womask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7636 = ~out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7637 = ~out_wimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7638 = ~out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7639 = ~out_womask_773; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_657 = {hi_427, flags_0_go, _out_prepend_T_657}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7640 = out_prepend_657; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7641 = _out_T_7640; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_658 = _out_T_7641; // @[RegisterRouter.scala:87:24] wire out_rimask_774 = \|_out_rimask_T_774; // @[RegisterRouter.scala:87:24] wire out_wimask_774 = &_out_wimask_T_774; // @[RegisterRouter.scala:87:24] wire out_romask_774 = \|_out_romask_T_774; // @[RegisterRouter.scala:87:24] wire out_womask_774 = &_out_womask_T_774; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_774 = out_rivalid_1_628 & out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7643 = out_f_rivalid_774; // @[RegisterRouter.scala:87:24] wire out_f_roready_774 = out_roready_1_628 & out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7644 = out_f_roready_774; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_774 = out_wivalid_1_628 & out_wimask_774; // @[RegisterRouter.scala:87:24] wire out_f_woready_774 = out_woready_1_628 & out_womask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7645 = ~out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7646 = ~out_wimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7647 = ~out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7648 = ~out_womask_774; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_658 = {hi_428, flags_0_go, _out_prepend_T_658}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7649 = out_prepend_658; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7650 = _out_T_7649; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_659 = _out_T_7650; // @[RegisterRouter.scala:87:24] wire out_rimask_775 = \|_out_rimask_T_775; // @[RegisterRouter.scala:87:24] wire out_wimask_775 = &_out_wimask_T_775; // @[RegisterRouter.scala:87:24] wire out_romask_775 = \|_out_romask_T_775; // @[RegisterRouter.scala:87:24] wire out_womask_775 = &_out_womask_T_775; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_775 = out_rivalid_1_629 & out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7652 = out_f_rivalid_775; // @[RegisterRouter.scala:87:24] wire out_f_roready_775 = out_roready_1_629 & out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7653 = out_f_roready_775; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_775 = out_wivalid_1_629 & out_wimask_775; // @[RegisterRouter.scala:87:24] wire out_f_woready_775 = out_woready_1_629 & out_womask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7654 = ~out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7655 = ~out_wimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7656 = ~out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7657 = ~out_womask_775; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_659 = {hi_429, flags_0_go, _out_prepend_T_659}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7658 = out_prepend_659; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7659 = _out_T_7658; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_660 = _out_T_7659; // @[RegisterRouter.scala:87:24] wire out_rimask_776 = \|_out_rimask_T_776; // @[RegisterRouter.scala:87:24] wire out_wimask_776 = &_out_wimask_T_776; // @[RegisterRouter.scala:87:24] wire out_romask_776 = \|_out_romask_T_776; // @[RegisterRouter.scala:87:24] wire out_womask_776 = &_out_womask_T_776; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_776 = out_rivalid_1_630 & out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7661 = out_f_rivalid_776; // @[RegisterRouter.scala:87:24] wire out_f_roready_776 = out_roready_1_630 & out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7662 = out_f_roready_776; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_776 = out_wivalid_1_630 & out_wimask_776; // @[RegisterRouter.scala:87:24] wire out_f_woready_776 = out_woready_1_630 & out_womask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7663 = ~out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7664 = ~out_wimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7665 = ~out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7666 = ~out_womask_776; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_660 = {hi_430, flags_0_go, _out_prepend_T_660}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7667 = out_prepend_660; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7668 = _out_T_7667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_661 = _out_T_7668; // @[RegisterRouter.scala:87:24] wire out_rimask_777 = \|_out_rimask_T_777; // @[RegisterRouter.scala:87:24] wire out_wimask_777 = &_out_wimask_T_777; // @[RegisterRouter.scala:87:24] wire out_romask_777 = \|_out_romask_T_777; // @[RegisterRouter.scala:87:24] wire out_womask_777 = &_out_womask_T_777; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_777 = out_rivalid_1_631 & out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7670 = out_f_rivalid_777; // @[RegisterRouter.scala:87:24] wire out_f_roready_777 = out_roready_1_631 & out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7671 = out_f_roready_777; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_777 = out_wivalid_1_631 & out_wimask_777; // @[RegisterRouter.scala:87:24] wire out_f_woready_777 = out_woready_1_631 & out_womask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7672 = ~out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7673 = ~out_wimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7674 = ~out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7675 = ~out_womask_777; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_661 = {hi_431, flags_0_go, _out_prepend_T_661}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7676 = out_prepend_661; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7677 = _out_T_7676; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_662 = _out_T_7677; // @[RegisterRouter.scala:87:24] wire out_rimask_778 = \|_out_rimask_T_778; // @[RegisterRouter.scala:87:24] wire out_wimask_778 = &_out_wimask_T_778; // @[RegisterRouter.scala:87:24] wire out_romask_778 = \|_out_romask_T_778; // @[RegisterRouter.scala:87:24] wire out_womask_778 = &_out_womask_T_778; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_778 = out_rivalid_1_632 & out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7679 = out_f_rivalid_778; // @[RegisterRouter.scala:87:24] wire out_f_roready_778 = out_roready_1_632 & out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7680 = out_f_roready_778; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_778 = out_wivalid_1_632 & out_wimask_778; // @[RegisterRouter.scala:87:24] wire out_f_woready_778 = out_woready_1_632 & out_womask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7681 = ~out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7682 = ~out_wimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7683 = ~out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7684 = ~out_womask_778; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_662 = {hi_432, flags_0_go, _out_prepend_T_662}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7685 = out_prepend_662; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7686 = _out_T_7685; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_181 = _out_T_7686; // @[MuxLiteral.scala:49:48] wire out_rimask_779 = \|_out_rimask_T_779; // @[RegisterRouter.scala:87:24] wire out_wimask_779 = &_out_wimask_T_779; // @[RegisterRouter.scala:87:24] wire out_romask_779 = \|_out_romask_T_779; // @[RegisterRouter.scala:87:24] wire out_womask_779 = &_out_womask_T_779; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_779 = out_rivalid_1_633 & out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7688 = out_f_rivalid_779; // @[RegisterRouter.scala:87:24] wire out_f_roready_779 = out_roready_1_633 & out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7689 = out_f_roready_779; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_779 = out_wivalid_1_633 & out_wimask_779; // @[RegisterRouter.scala:87:24] wire out_f_woready_779 = out_woready_1_633 & out_womask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7690 = ~out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7691 = ~out_wimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7692 = ~out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7693 = ~out_womask_779; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7695 = _out_T_7694; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_663 = _out_T_7695; // @[RegisterRouter.scala:87:24] wire out_rimask_780 = \|_out_rimask_T_780; // @[RegisterRouter.scala:87:24] wire out_wimask_780 = &_out_wimask_T_780; // @[RegisterRouter.scala:87:24] wire out_romask_780 = \|_out_romask_T_780; // @[RegisterRouter.scala:87:24] wire out_womask_780 = &_out_womask_T_780; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_780 = out_rivalid_1_634 & out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7697 = out_f_rivalid_780; // @[RegisterRouter.scala:87:24] wire out_f_roready_780 = out_roready_1_634 & out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7698 = out_f_roready_780; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_780 = out_wivalid_1_634 & out_wimask_780; // @[RegisterRouter.scala:87:24] wire out_f_woready_780 = out_woready_1_634 & out_womask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7699 = ~out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7700 = ~out_wimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7701 = ~out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7702 = ~out_womask_780; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_663 = {hi_250, flags_0_go, _out_prepend_T_663}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7703 = out_prepend_663; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7704 = _out_T_7703; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_664 = _out_T_7704; // @[RegisterRouter.scala:87:24] wire out_rimask_781 = \|_out_rimask_T_781; // @[RegisterRouter.scala:87:24] wire out_wimask_781 = &_out_wimask_T_781; // @[RegisterRouter.scala:87:24] wire out_romask_781 = \|_out_romask_T_781; // @[RegisterRouter.scala:87:24] wire out_womask_781 = &_out_womask_T_781; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_781 = out_rivalid_1_635 & out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7706 = out_f_rivalid_781; // @[RegisterRouter.scala:87:24] wire out_f_roready_781 = out_roready_1_635 & out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7707 = out_f_roready_781; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_781 = out_wivalid_1_635 & out_wimask_781; // @[RegisterRouter.scala:87:24] wire out_f_woready_781 = out_woready_1_635 & out_womask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7708 = ~out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7709 = ~out_wimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7710 = ~out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7711 = ~out_womask_781; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_664 = {hi_251, flags_0_go, _out_prepend_T_664}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7712 = out_prepend_664; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7713 = _out_T_7712; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_665 = _out_T_7713; // @[RegisterRouter.scala:87:24] wire out_rimask_782 = \|_out_rimask_T_782; // @[RegisterRouter.scala:87:24] wire out_wimask_782 = &_out_wimask_T_782; // @[RegisterRouter.scala:87:24] wire out_romask_782 = \|_out_romask_T_782; // @[RegisterRouter.scala:87:24] wire out_womask_782 = &_out_womask_T_782; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_782 = out_rivalid_1_636 & out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7715 = out_f_rivalid_782; // @[RegisterRouter.scala:87:24] wire out_f_roready_782 = out_roready_1_636 & out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7716 = out_f_roready_782; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_782 = out_wivalid_1_636 & out_wimask_782; // @[RegisterRouter.scala:87:24] wire out_f_woready_782 = out_woready_1_636 & out_womask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7717 = ~out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7718 = ~out_wimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7719 = ~out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7720 = ~out_womask_782; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_665 = {hi_252, flags_0_go, _out_prepend_T_665}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7721 = out_prepend_665; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7722 = _out_T_7721; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_666 = _out_T_7722; // @[RegisterRouter.scala:87:24] wire out_rimask_783 = \|_out_rimask_T_783; // @[RegisterRouter.scala:87:24] wire out_wimask_783 = &_out_wimask_T_783; // @[RegisterRouter.scala:87:24] wire out_romask_783 = \|_out_romask_T_783; // @[RegisterRouter.scala:87:24] wire out_womask_783 = &_out_womask_T_783; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_783 = out_rivalid_1_637 & out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7724 = out_f_rivalid_783; // @[RegisterRouter.scala:87:24] wire out_f_roready_783 = out_roready_1_637 & out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7725 = out_f_roready_783; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_783 = out_wivalid_1_637 & out_wimask_783; // @[RegisterRouter.scala:87:24] wire out_f_woready_783 = out_woready_1_637 & out_womask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7726 = ~out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7727 = ~out_wimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7728 = ~out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7729 = ~out_womask_783; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_666 = {hi_253, flags_0_go, _out_prepend_T_666}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7730 = out_prepend_666; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7731 = _out_T_7730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_667 = _out_T_7731; // @[RegisterRouter.scala:87:24] wire out_rimask_784 = \|_out_rimask_T_784; // @[RegisterRouter.scala:87:24] wire out_wimask_784 = &_out_wimask_T_784; // @[RegisterRouter.scala:87:24] wire out_romask_784 = \|_out_romask_T_784; // @[RegisterRouter.scala:87:24] wire out_womask_784 = &_out_womask_T_784; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_784 = out_rivalid_1_638 & out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7733 = out_f_rivalid_784; // @[RegisterRouter.scala:87:24] wire out_f_roready_784 = out_roready_1_638 & out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7734 = out_f_roready_784; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_784 = out_wivalid_1_638 & out_wimask_784; // @[RegisterRouter.scala:87:24] wire out_f_woready_784 = out_woready_1_638 & out_womask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7735 = ~out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7736 = ~out_wimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7737 = ~out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7738 = ~out_womask_784; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_667 = {hi_254, flags_0_go, _out_prepend_T_667}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7739 = out_prepend_667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7740 = _out_T_7739; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_668 = _out_T_7740; // @[RegisterRouter.scala:87:24] wire out_rimask_785 = \|_out_rimask_T_785; // @[RegisterRouter.scala:87:24] wire out_wimask_785 = &_out_wimask_T_785; // @[RegisterRouter.scala:87:24] wire out_romask_785 = \|_out_romask_T_785; // @[RegisterRouter.scala:87:24] wire out_womask_785 = &_out_womask_T_785; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_785 = out_rivalid_1_639 & out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7742 = out_f_rivalid_785; // @[RegisterRouter.scala:87:24] wire out_f_roready_785 = out_roready_1_639 & out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7743 = out_f_roready_785; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_785 = out_wivalid_1_639 & out_wimask_785; // @[RegisterRouter.scala:87:24] wire out_f_woready_785 = out_woready_1_639 & out_womask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7744 = ~out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7745 = ~out_wimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7746 = ~out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7747 = ~out_womask_785; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_668 = {hi_255, flags_0_go, _out_prepend_T_668}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7748 = out_prepend_668; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7749 = _out_T_7748; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_669 = _out_T_7749; // @[RegisterRouter.scala:87:24] wire out_rimask_786 = \|_out_rimask_T_786; // @[RegisterRouter.scala:87:24] wire out_wimask_786 = &_out_wimask_T_786; // @[RegisterRouter.scala:87:24] wire out_romask_786 = \|_out_romask_T_786; // @[RegisterRouter.scala:87:24] wire out_womask_786 = &_out_womask_T_786; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_786 = out_rivalid_1_640 & out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7751 = out_f_rivalid_786; // @[RegisterRouter.scala:87:24] wire out_f_roready_786 = out_roready_1_640 & out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7752 = out_f_roready_786; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_786 = out_wivalid_1_640 & out_wimask_786; // @[RegisterRouter.scala:87:24] wire out_f_woready_786 = out_woready_1_640 & out_womask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7753 = ~out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7754 = ~out_wimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7755 = ~out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7756 = ~out_womask_786; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_669 = {hi_256, flags_0_go, _out_prepend_T_669}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7757 = out_prepend_669; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7758 = _out_T_7757; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_159 = _out_T_7758; // @[MuxLiteral.scala:49:48] wire out_rimask_787 = \|_out_rimask_T_787; // @[RegisterRouter.scala:87:24] wire out_wimask_787 = &_out_wimask_T_787; // @[RegisterRouter.scala:87:24] wire out_romask_787 = \|_out_romask_T_787; // @[RegisterRouter.scala:87:24] wire out_womask_787 = &_out_womask_T_787; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_787 = out_rivalid_1_641 & out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7760 = out_f_rivalid_787; // @[RegisterRouter.scala:87:24] wire out_f_roready_787 = out_roready_1_641 & out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7761 = out_f_roready_787; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_787 = out_wivalid_1_641 & out_wimask_787; // @[RegisterRouter.scala:87:24] wire out_f_woready_787 = out_woready_1_641 & out_womask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7762 = ~out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7763 = ~out_wimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7764 = ~out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7765 = ~out_womask_787; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7767 = _out_T_7766; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_670 = _out_T_7767; // @[RegisterRouter.scala:87:24] wire out_rimask_788 = \|_out_rimask_T_788; // @[RegisterRouter.scala:87:24] wire out_wimask_788 = &_out_wimask_T_788; // @[RegisterRouter.scala:87:24] wire out_romask_788 = \|_out_romask_T_788; // @[RegisterRouter.scala:87:24] wire out_womask_788 = &_out_womask_T_788; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_788 = out_rivalid_1_642 & out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7769 = out_f_rivalid_788; // @[RegisterRouter.scala:87:24] wire out_f_roready_788 = out_roready_1_642 & out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7770 = out_f_roready_788; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_788 = out_wivalid_1_642 & out_wimask_788; // @[RegisterRouter.scala:87:24] wire out_f_woready_788 = out_woready_1_642 & out_womask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7771 = ~out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7772 = ~out_wimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7773 = ~out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7774 = ~out_womask_788; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_670 = {hi_474, flags_0_go, _out_prepend_T_670}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7775 = out_prepend_670; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7776 = _out_T_7775; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_671 = _out_T_7776; // @[RegisterRouter.scala:87:24] wire out_rimask_789 = \|_out_rimask_T_789; // @[RegisterRouter.scala:87:24] wire out_wimask_789 = &_out_wimask_T_789; // @[RegisterRouter.scala:87:24] wire out_romask_789 = \|_out_romask_T_789; // @[RegisterRouter.scala:87:24] wire out_womask_789 = &_out_womask_T_789; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_789 = out_rivalid_1_643 & out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7778 = out_f_rivalid_789; // @[RegisterRouter.scala:87:24] wire out_f_roready_789 = out_roready_1_643 & out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7779 = out_f_roready_789; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_789 = out_wivalid_1_643 & out_wimask_789; // @[RegisterRouter.scala:87:24] wire out_f_woready_789 = out_woready_1_643 & out_womask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7780 = ~out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7781 = ~out_wimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7782 = ~out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7783 = ~out_womask_789; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_671 = {hi_475, flags_0_go, _out_prepend_T_671}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7784 = out_prepend_671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7785 = _out_T_7784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_672 = _out_T_7785; // @[RegisterRouter.scala:87:24] wire out_rimask_790 = \|_out_rimask_T_790; // @[RegisterRouter.scala:87:24] wire out_wimask_790 = &_out_wimask_T_790; // @[RegisterRouter.scala:87:24] wire out_romask_790 = \|_out_romask_T_790; // @[RegisterRouter.scala:87:24] wire out_womask_790 = &_out_womask_T_790; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_790 = out_rivalid_1_644 & out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7787 = out_f_rivalid_790; // @[RegisterRouter.scala:87:24] wire out_f_roready_790 = out_roready_1_644 & out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7788 = out_f_roready_790; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_790 = out_wivalid_1_644 & out_wimask_790; // @[RegisterRouter.scala:87:24] wire out_f_woready_790 = out_woready_1_644 & out_womask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7789 = ~out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7790 = ~out_wimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7791 = ~out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7792 = ~out_womask_790; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_672 = {hi_476, flags_0_go, _out_prepend_T_672}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7793 = out_prepend_672; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7794 = _out_T_7793; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_673 = _out_T_7794; // @[RegisterRouter.scala:87:24] wire out_rimask_791 = \|_out_rimask_T_791; // @[RegisterRouter.scala:87:24] wire out_wimask_791 = &_out_wimask_T_791; // @[RegisterRouter.scala:87:24] wire out_romask_791 = \|_out_romask_T_791; // @[RegisterRouter.scala:87:24] wire out_womask_791 = &_out_womask_T_791; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_791 = out_rivalid_1_645 & out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7796 = out_f_rivalid_791; // @[RegisterRouter.scala:87:24] wire out_f_roready_791 = out_roready_1_645 & out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7797 = out_f_roready_791; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_791 = out_wivalid_1_645 & out_wimask_791; // @[RegisterRouter.scala:87:24] wire out_f_woready_791 = out_woready_1_645 & out_womask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7798 = ~out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7799 = ~out_wimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7800 = ~out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7801 = ~out_womask_791; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_673 = {hi_477, flags_0_go, _out_prepend_T_673}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7802 = out_prepend_673; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7803 = _out_T_7802; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_674 = _out_T_7803; // @[RegisterRouter.scala:87:24] wire out_rimask_792 = \|_out_rimask_T_792; // @[RegisterRouter.scala:87:24] wire out_wimask_792 = &_out_wimask_T_792; // @[RegisterRouter.scala:87:24] wire out_romask_792 = \|_out_romask_T_792; // @[RegisterRouter.scala:87:24] wire out_womask_792 = &_out_womask_T_792; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_792 = out_rivalid_1_646 & out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7805 = out_f_rivalid_792; // @[RegisterRouter.scala:87:24] wire out_f_roready_792 = out_roready_1_646 & out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7806 = out_f_roready_792; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_792 = out_wivalid_1_646 & out_wimask_792; // @[RegisterRouter.scala:87:24] wire out_f_woready_792 = out_woready_1_646 & out_womask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7807 = ~out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7808 = ~out_wimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7809 = ~out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7810 = ~out_womask_792; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_674 = {hi_478, flags_0_go, _out_prepend_T_674}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7811 = out_prepend_674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7812 = _out_T_7811; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_675 = _out_T_7812; // @[RegisterRouter.scala:87:24] wire out_rimask_793 = \|_out_rimask_T_793; // @[RegisterRouter.scala:87:24] wire out_wimask_793 = &_out_wimask_T_793; // @[RegisterRouter.scala:87:24] wire out_romask_793 = \|_out_romask_T_793; // @[RegisterRouter.scala:87:24] wire out_womask_793 = &_out_womask_T_793; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_793 = out_rivalid_1_647 & out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7814 = out_f_rivalid_793; // @[RegisterRouter.scala:87:24] wire out_f_roready_793 = out_roready_1_647 & out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7815 = out_f_roready_793; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_793 = out_wivalid_1_647 & out_wimask_793; // @[RegisterRouter.scala:87:24] wire out_f_woready_793 = out_woready_1_647 & out_womask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7816 = ~out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7817 = ~out_wimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7818 = ~out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7819 = ~out_womask_793; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_675 = {hi_479, flags_0_go, _out_prepend_T_675}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7820 = out_prepend_675; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7821 = _out_T_7820; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_676 = _out_T_7821; // @[RegisterRouter.scala:87:24] wire out_rimask_794 = \|_out_rimask_T_794; // @[RegisterRouter.scala:87:24] wire out_wimask_794 = &_out_wimask_T_794; // @[RegisterRouter.scala:87:24] wire out_romask_794 = \|_out_romask_T_794; // @[RegisterRouter.scala:87:24] wire out_womask_794 = &_out_womask_T_794; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_794 = out_rivalid_1_648 & out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7823 = out_f_rivalid_794; // @[RegisterRouter.scala:87:24] wire out_f_roready_794 = out_roready_1_648 & out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7824 = out_f_roready_794; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_794 = out_wivalid_1_648 & out_wimask_794; // @[RegisterRouter.scala:87:24] wire out_f_woready_794 = out_woready_1_648 & out_womask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7825 = ~out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7826 = ~out_wimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7827 = ~out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7828 = ~out_womask_794; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_676 = {hi_480, flags_0_go, _out_prepend_T_676}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7829 = out_prepend_676; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7830 = _out_T_7829; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_187 = _out_T_7830; // @[MuxLiteral.scala:49:48] wire out_rimask_795 = \|_out_rimask_T_795; // @[RegisterRouter.scala:87:24] wire out_wimask_795 = &_out_wimask_T_795; // @[RegisterRouter.scala:87:24] wire out_romask_795 = \|_out_romask_T_795; // @[RegisterRouter.scala:87:24] wire out_womask_795 = &_out_womask_T_795; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_795 = out_rivalid_1_649 & out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7832 = out_f_rivalid_795; // @[RegisterRouter.scala:87:24] wire out_f_roready_795 = out_roready_1_649 & out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7833 = out_f_roready_795; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_795 = out_wivalid_1_649 & out_wimask_795; // @[RegisterRouter.scala:87:24] wire out_f_woready_795 = out_woready_1_649 & out_womask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7834 = ~out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7835 = ~out_wimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7836 = ~out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7837 = ~out_womask_795; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7839 = _out_T_7838; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_677 = _out_T_7839; // @[RegisterRouter.scala:87:24] wire out_rimask_796 = \|_out_rimask_T_796; // @[RegisterRouter.scala:87:24] wire out_wimask_796 = &_out_wimask_T_796; // @[RegisterRouter.scala:87:24] wire out_romask_796 = \|_out_romask_T_796; // @[RegisterRouter.scala:87:24] wire out_womask_796 = &_out_womask_T_796; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_796 = out_rivalid_1_650 & out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7841 = out_f_rivalid_796; // @[RegisterRouter.scala:87:24] wire out_f_roready_796 = out_roready_1_650 & out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7842 = out_f_roready_796; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_796 = out_wivalid_1_650 & out_wimask_796; // @[RegisterRouter.scala:87:24] wire out_f_woready_796 = out_woready_1_650 & out_womask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7843 = ~out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7844 = ~out_wimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7845 = ~out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7846 = ~out_womask_796; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_677 = {hi_354, flags_0_go, _out_prepend_T_677}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7847 = out_prepend_677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7848 = _out_T_7847; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_678 = _out_T_7848; // @[RegisterRouter.scala:87:24] wire out_rimask_797 = \|_out_rimask_T_797; // @[RegisterRouter.scala:87:24] wire out_wimask_797 = &_out_wimask_T_797; // @[RegisterRouter.scala:87:24] wire out_romask_797 = \|_out_romask_T_797; // @[RegisterRouter.scala:87:24] wire out_womask_797 = &_out_womask_T_797; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_797 = out_rivalid_1_651 & out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7850 = out_f_rivalid_797; // @[RegisterRouter.scala:87:24] wire out_f_roready_797 = out_roready_1_651 & out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7851 = out_f_roready_797; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_797 = out_wivalid_1_651 & out_wimask_797; // @[RegisterRouter.scala:87:24] wire out_f_woready_797 = out_woready_1_651 & out_womask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7852 = ~out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7853 = ~out_wimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7854 = ~out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7855 = ~out_womask_797; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_678 = {hi_355, flags_0_go, _out_prepend_T_678}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7856 = out_prepend_678; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7857 = _out_T_7856; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_679 = _out_T_7857; // @[RegisterRouter.scala:87:24] wire out_rimask_798 = \|_out_rimask_T_798; // @[RegisterRouter.scala:87:24] wire out_wimask_798 = &_out_wimask_T_798; // @[RegisterRouter.scala:87:24] wire out_romask_798 = \|_out_romask_T_798; // @[RegisterRouter.scala:87:24] wire out_womask_798 = &_out_womask_T_798; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_798 = out_rivalid_1_652 & out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7859 = out_f_rivalid_798; // @[RegisterRouter.scala:87:24] wire out_f_roready_798 = out_roready_1_652 & out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7860 = out_f_roready_798; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_798 = out_wivalid_1_652 & out_wimask_798; // @[RegisterRouter.scala:87:24] wire out_f_woready_798 = out_woready_1_652 & out_womask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7861 = ~out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7862 = ~out_wimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7863 = ~out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7864 = ~out_womask_798; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_679 = {hi_356, flags_0_go, _out_prepend_T_679}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7865 = out_prepend_679; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7866 = _out_T_7865; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_680 = _out_T_7866; // @[RegisterRouter.scala:87:24] wire out_rimask_799 = \|_out_rimask_T_799; // @[RegisterRouter.scala:87:24] wire out_wimask_799 = &_out_wimask_T_799; // @[RegisterRouter.scala:87:24] wire out_romask_799 = \|_out_romask_T_799; // @[RegisterRouter.scala:87:24] wire out_womask_799 = &_out_womask_T_799; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_799 = out_rivalid_1_653 & out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7868 = out_f_rivalid_799; // @[RegisterRouter.scala:87:24] wire out_f_roready_799 = out_roready_1_653 & out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7869 = out_f_roready_799; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_799 = out_wivalid_1_653 & out_wimask_799; // @[RegisterRouter.scala:87:24] wire out_f_woready_799 = out_woready_1_653 & out_womask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7870 = ~out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7871 = ~out_wimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7872 = ~out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7873 = ~out_womask_799; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_680 = {hi_357, flags_0_go, _out_prepend_T_680}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7874 = out_prepend_680; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7875 = _out_T_7874; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_681 = _out_T_7875; // @[RegisterRouter.scala:87:24] wire out_rimask_800 = \|_out_rimask_T_800; // @[RegisterRouter.scala:87:24] wire out_wimask_800 = &_out_wimask_T_800; // @[RegisterRouter.scala:87:24] wire out_romask_800 = \|_out_romask_T_800; // @[RegisterRouter.scala:87:24] wire out_womask_800 = &_out_womask_T_800; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_800 = out_rivalid_1_654 & out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7877 = out_f_rivalid_800; // @[RegisterRouter.scala:87:24] wire out_f_roready_800 = out_roready_1_654 & out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7878 = out_f_roready_800; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_800 = out_wivalid_1_654 & out_wimask_800; // @[RegisterRouter.scala:87:24] wire out_f_woready_800 = out_woready_1_654 & out_womask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7879 = ~out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7880 = ~out_wimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7881 = ~out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7882 = ~out_womask_800; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_681 = {hi_358, flags_0_go, _out_prepend_T_681}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7883 = out_prepend_681; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7884 = _out_T_7883; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_682 = _out_T_7884; // @[RegisterRouter.scala:87:24] wire out_rimask_801 = \|_out_rimask_T_801; // @[RegisterRouter.scala:87:24] wire out_wimask_801 = &_out_wimask_T_801; // @[RegisterRouter.scala:87:24] wire out_romask_801 = \|_out_romask_T_801; // @[RegisterRouter.scala:87:24] wire out_womask_801 = &_out_womask_T_801; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_801 = out_rivalid_1_655 & out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7886 = out_f_rivalid_801; // @[RegisterRouter.scala:87:24] wire out_f_roready_801 = out_roready_1_655 & out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7887 = out_f_roready_801; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_801 = out_wivalid_1_655 & out_wimask_801; // @[RegisterRouter.scala:87:24] wire out_f_woready_801 = out_woready_1_655 & out_womask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7888 = ~out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7889 = ~out_wimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7890 = ~out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7891 = ~out_womask_801; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_682 = {hi_359, flags_0_go, _out_prepend_T_682}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7892 = out_prepend_682; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7893 = _out_T_7892; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_683 = _out_T_7893; // @[RegisterRouter.scala:87:24] wire out_rimask_802 = \|_out_rimask_T_802; // @[RegisterRouter.scala:87:24] wire out_wimask_802 = &_out_wimask_T_802; // @[RegisterRouter.scala:87:24] wire out_romask_802 = \|_out_romask_T_802; // @[RegisterRouter.scala:87:24] wire out_womask_802 = &_out_womask_T_802; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_802 = out_rivalid_1_656 & out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7895 = out_f_rivalid_802; // @[RegisterRouter.scala:87:24] wire out_f_roready_802 = out_roready_1_656 & out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7896 = out_f_roready_802; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_802 = out_wivalid_1_656 & out_wimask_802; // @[RegisterRouter.scala:87:24] wire out_f_woready_802 = out_woready_1_656 & out_womask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7897 = ~out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7898 = ~out_wimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7899 = ~out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7900 = ~out_womask_802; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_683 = {hi_360, flags_0_go, _out_prepend_T_683}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7901 = out_prepend_683; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7902 = _out_T_7901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_172 = _out_T_7902; // @[MuxLiteral.scala:49:48] wire out_rimask_803 = \|_out_rimask_T_803; // @[RegisterRouter.scala:87:24] wire out_wimask_803 = &_out_wimask_T_803; // @[RegisterRouter.scala:87:24] wire out_romask_803 = \|_out_romask_T_803; // @[RegisterRouter.scala:87:24] wire out_womask_803 = &_out_womask_T_803; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_803 = out_rivalid_1_657 & out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7904 = out_f_rivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_roready_803 = out_roready_1_657 & out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7905 = out_f_roready_803; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_803 = out_wivalid_1_657 & out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7906 = out_f_wivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_woready_803 = out_woready_1_657 & out_womask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7907 = out_f_woready_803; // @[RegisterRouter.scala:87:24] wire _out_T_7908 = ~out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7909 = ~out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7910 = ~out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7911 = ~out_womask_803; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7913 = _out_T_7912; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_684 = _out_T_7913; // @[RegisterRouter.scala:87:24] wire out_rimask_804 = \|_out_rimask_T_804; // @[RegisterRouter.scala:87:24] wire out_wimask_804 = &_out_wimask_T_804; // @[RegisterRouter.scala:87:24] wire out_romask_804 = \|_out_romask_T_804; // @[RegisterRouter.scala:87:24] wire out_womask_804 = &_out_womask_T_804; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_804 = out_rivalid_1_658 & out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7915 = out_f_rivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_roready_804 = out_roready_1_658 & out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7916 = out_f_roready_804; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_804 = out_wivalid_1_658 & out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7917 = out_f_wivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_woready_804 = out_woready_1_658 & out_womask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7918 = out_f_woready_804; // @[RegisterRouter.scala:87:24] wire _out_T_7919 = ~out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7920 = ~out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7921 = ~out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7922 = ~out_womask_804; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_684 = {abstractDataMem_9, _out_prepend_T_684}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7923 = out_prepend_684; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7924 = _out_T_7923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_685 = _out_T_7924; // @[RegisterRouter.scala:87:24] wire out_rimask_805 = \|_out_rimask_T_805; // @[RegisterRouter.scala:87:24] wire out_wimask_805 = &_out_wimask_T_805; // @[RegisterRouter.scala:87:24] wire out_romask_805 = \|_out_romask_T_805; // @[RegisterRouter.scala:87:24] wire out_womask_805 = &_out_womask_T_805; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_805 = out_rivalid_1_659 & out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7926 = out_f_rivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_roready_805 = out_roready_1_659 & out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7927 = out_f_roready_805; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_805 = out_wivalid_1_659 & out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7928 = out_f_wivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_woready_805 = out_woready_1_659 & out_womask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7929 = out_f_woready_805; // @[RegisterRouter.scala:87:24] wire _out_T_7930 = ~out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7931 = ~out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7932 = ~out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7933 = ~out_womask_805; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_685 = {abstractDataMem_10, _out_prepend_T_685}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7934 = out_prepend_685; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7935 = _out_T_7934; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_686 = _out_T_7935; // @[RegisterRouter.scala:87:24] wire out_rimask_806 = \|_out_rimask_T_806; // @[RegisterRouter.scala:87:24] wire out_wimask_806 = &_out_wimask_T_806; // @[RegisterRouter.scala:87:24] wire out_romask_806 = \|_out_romask_T_806; // @[RegisterRouter.scala:87:24] wire out_womask_806 = &_out_womask_T_806; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_806 = out_rivalid_1_660 & out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7937 = out_f_rivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_roready_806 = out_roready_1_660 & out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7938 = out_f_roready_806; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_806 = out_wivalid_1_660 & out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7939 = out_f_wivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_woready_806 = out_woready_1_660 & out_womask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7940 = out_f_woready_806; // @[RegisterRouter.scala:87:24] wire _out_T_7941 = ~out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7942 = ~out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7943 = ~out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7944 = ~out_womask_806; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_686 = {abstractDataMem_11, _out_prepend_T_686}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7945 = out_prepend_686; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7946 = _out_T_7945; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_687 = _out_T_7946; // @[RegisterRouter.scala:87:24] wire out_rimask_807 = \|_out_rimask_T_807; // @[RegisterRouter.scala:87:24] wire out_wimask_807 = &_out_wimask_T_807; // @[RegisterRouter.scala:87:24] wire out_romask_807 = \|_out_romask_T_807; // @[RegisterRouter.scala:87:24] wire out_womask_807 = &_out_womask_T_807; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_807 = out_rivalid_1_661 & out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7948 = out_f_rivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_roready_807 = out_roready_1_661 & out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7949 = out_f_roready_807; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_807 = out_wivalid_1_661 & out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7950 = out_f_wivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_woready_807 = out_woready_1_661 & out_womask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7951 = out_f_woready_807; // @[RegisterRouter.scala:87:24] wire _out_T_7952 = ~out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7953 = ~out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7954 = ~out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7955 = ~out_womask_807; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_687 = {abstractDataMem_12, _out_prepend_T_687}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7956 = out_prepend_687; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7957 = _out_T_7956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_688 = _out_T_7957; // @[RegisterRouter.scala:87:24] wire out_rimask_808 = \|_out_rimask_T_808; // @[RegisterRouter.scala:87:24] wire out_wimask_808 = &_out_wimask_T_808; // @[RegisterRouter.scala:87:24] wire out_romask_808 = \|_out_romask_T_808; // @[RegisterRouter.scala:87:24] wire out_womask_808 = &_out_womask_T_808; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_808 = out_rivalid_1_662 & out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7959 = out_f_rivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_roready_808 = out_roready_1_662 & out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7960 = out_f_roready_808; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_808 = out_wivalid_1_662 & out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7961 = out_f_wivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_woready_808 = out_woready_1_662 & out_womask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7962 = out_f_woready_808; // @[RegisterRouter.scala:87:24] wire _out_T_7963 = ~out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7964 = ~out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7965 = ~out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7966 = ~out_womask_808; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_688 = {abstractDataMem_13, _out_prepend_T_688}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7967 = out_prepend_688; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7968 = _out_T_7967; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_689 = _out_T_7968; // @[RegisterRouter.scala:87:24] wire out_rimask_809 = \|_out_rimask_T_809; // @[RegisterRouter.scala:87:24] wire out_wimask_809 = &_out_wimask_T_809; // @[RegisterRouter.scala:87:24] wire out_romask_809 = \|_out_romask_T_809; // @[RegisterRouter.scala:87:24] wire out_womask_809 = &_out_womask_T_809; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_809 = out_rivalid_1_663 & out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7970 = out_f_rivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_roready_809 = out_roready_1_663 & out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7971 = out_f_roready_809; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_809 = out_wivalid_1_663 & out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7972 = out_f_wivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_woready_809 = out_woready_1_663 & out_womask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7973 = out_f_woready_809; // @[RegisterRouter.scala:87:24] wire _out_T_7974 = ~out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7975 = ~out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7976 = ~out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7977 = ~out_womask_809; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_689 = {abstractDataMem_14, _out_prepend_T_689}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7978 = out_prepend_689; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7979 = _out_T_7978; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_690 = _out_T_7979; // @[RegisterRouter.scala:87:24] wire out_rimask_810 = \|_out_rimask_T_810; // @[RegisterRouter.scala:87:24] wire out_wimask_810 = &_out_wimask_T_810; // @[RegisterRouter.scala:87:24] wire out_romask_810 = \|_out_romask_T_810; // @[RegisterRouter.scala:87:24] wire out_womask_810 = &_out_womask_T_810; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_810 = out_rivalid_1_664 & out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7981 = out_f_rivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_roready_810 = out_roready_1_664 & out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7982 = out_f_roready_810; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_810 = out_wivalid_1_664 & out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7983 = out_f_wivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_woready_810 = out_woready_1_664 & out_womask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7984 = out_f_woready_810; // @[RegisterRouter.scala:87:24] wire _out_T_7985 = ~out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7986 = ~out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7987 = ~out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7988 = ~out_womask_810; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_690 = {abstractDataMem_15, _out_prepend_T_690}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7989 = out_prepend_690; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7990 = _out_T_7989; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_113 = _out_T_7990; // @[MuxLiteral.scala:49:48] wire out_rimask_811 = \|_out_rimask_T_811; // @[RegisterRouter.scala:87:24] wire out_wimask_811 = &_out_wimask_T_811; // @[RegisterRouter.scala:87:24] wire out_romask_811 = \|_out_romask_T_811; // @[RegisterRouter.scala:87:24] wire out_womask_811 = &_out_womask_T_811; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_811 = out_rivalid_1_665 & out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7992 = out_f_rivalid_811; // @[RegisterRouter.scala:87:24] wire out_f_roready_811 = out_roready_1_665 & out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7993 = out_f_roready_811; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_811 = out_wivalid_1_665 & out_wimask_811; // @[RegisterRouter.scala:87:24] wire out_f_woready_811 = out_woready_1_665 & out_womask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7994 = ~out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7995 = ~out_wimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7996 = ~out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7997 = ~out_womask_811; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7999 = _out_T_7998; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_691 = _out_T_7999; // @[RegisterRouter.scala:87:24] wire out_rimask_812 = \|_out_rimask_T_812; // @[RegisterRouter.scala:87:24] wire out_wimask_812 = &_out_wimask_T_812; // @[RegisterRouter.scala:87:24] wire out_romask_812 = \|_out_romask_T_812; // @[RegisterRouter.scala:87:24] wire out_womask_812 = &_out_womask_T_812; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_812 = out_rivalid_1_666 & out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8001 = out_f_rivalid_812; // @[RegisterRouter.scala:87:24] wire out_f_roready_812 = out_roready_1_666 & out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8002 = out_f_roready_812; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_812 = out_wivalid_1_666 & out_wimask_812; // @[RegisterRouter.scala:87:24] wire out_f_woready_812 = out_woready_1_666 & out_womask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8003 = ~out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8004 = ~out_wimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8005 = ~out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8006 = ~out_womask_812; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_691 = {hi_730, flags_0_go, _out_prepend_T_691}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8007 = out_prepend_691; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8008 = _out_T_8007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_692 = _out_T_8008; // @[RegisterRouter.scala:87:24] wire out_rimask_813 = \|_out_rimask_T_813; // @[RegisterRouter.scala:87:24] wire out_wimask_813 = &_out_wimask_T_813; // @[RegisterRouter.scala:87:24] wire out_romask_813 = \|_out_romask_T_813; // @[RegisterRouter.scala:87:24] wire out_womask_813 = &_out_womask_T_813; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_813 = out_rivalid_1_667 & out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8010 = out_f_rivalid_813; // @[RegisterRouter.scala:87:24] wire out_f_roready_813 = out_roready_1_667 & out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8011 = out_f_roready_813; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_813 = out_wivalid_1_667 & out_wimask_813; // @[RegisterRouter.scala:87:24] wire out_f_woready_813 = out_woready_1_667 & out_womask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8012 = ~out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8013 = ~out_wimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8014 = ~out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8015 = ~out_womask_813; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_692 = {hi_731, flags_0_go, _out_prepend_T_692}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8016 = out_prepend_692; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8017 = _out_T_8016; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_693 = _out_T_8017; // @[RegisterRouter.scala:87:24] wire out_rimask_814 = \|_out_rimask_T_814; // @[RegisterRouter.scala:87:24] wire out_wimask_814 = &_out_wimask_T_814; // @[RegisterRouter.scala:87:24] wire out_romask_814 = \|_out_romask_T_814; // @[RegisterRouter.scala:87:24] wire out_womask_814 = &_out_womask_T_814; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_814 = out_rivalid_1_668 & out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8019 = out_f_rivalid_814; // @[RegisterRouter.scala:87:24] wire out_f_roready_814 = out_roready_1_668 & out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8020 = out_f_roready_814; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_814 = out_wivalid_1_668 & out_wimask_814; // @[RegisterRouter.scala:87:24] wire out_f_woready_814 = out_woready_1_668 & out_womask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8021 = ~out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8022 = ~out_wimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8023 = ~out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8024 = ~out_womask_814; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_693 = {hi_732, flags_0_go, _out_prepend_T_693}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8025 = out_prepend_693; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8026 = _out_T_8025; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_694 = _out_T_8026; // @[RegisterRouter.scala:87:24] wire out_rimask_815 = \|_out_rimask_T_815; // @[RegisterRouter.scala:87:24] wire out_wimask_815 = &_out_wimask_T_815; // @[RegisterRouter.scala:87:24] wire out_romask_815 = \|_out_romask_T_815; // @[RegisterRouter.scala:87:24] wire out_womask_815 = &_out_womask_T_815; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_815 = out_rivalid_1_669 & out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8028 = out_f_rivalid_815; // @[RegisterRouter.scala:87:24] wire out_f_roready_815 = out_roready_1_669 & out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8029 = out_f_roready_815; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_815 = out_wivalid_1_669 & out_wimask_815; // @[RegisterRouter.scala:87:24] wire out_f_woready_815 = out_woready_1_669 & out_womask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8030 = ~out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8031 = ~out_wimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8032 = ~out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8033 = ~out_womask_815; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_694 = {hi_733, flags_0_go, _out_prepend_T_694}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8034 = out_prepend_694; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8035 = _out_T_8034; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_695 = _out_T_8035; // @[RegisterRouter.scala:87:24] wire out_rimask_816 = \|_out_rimask_T_816; // @[RegisterRouter.scala:87:24] wire out_wimask_816 = &_out_wimask_T_816; // @[RegisterRouter.scala:87:24] wire out_romask_816 = \|_out_romask_T_816; // @[RegisterRouter.scala:87:24] wire out_womask_816 = &_out_womask_T_816; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_816 = out_rivalid_1_670 & out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8037 = out_f_rivalid_816; // @[RegisterRouter.scala:87:24] wire out_f_roready_816 = out_roready_1_670 & out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8038 = out_f_roready_816; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_816 = out_wivalid_1_670 & out_wimask_816; // @[RegisterRouter.scala:87:24] wire out_f_woready_816 = out_woready_1_670 & out_womask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8039 = ~out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8040 = ~out_wimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8041 = ~out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8042 = ~out_womask_816; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_695 = {hi_734, flags_0_go, _out_prepend_T_695}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8043 = out_prepend_695; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8044 = _out_T_8043; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_696 = _out_T_8044; // @[RegisterRouter.scala:87:24] wire out_rimask_817 = \|_out_rimask_T_817; // @[RegisterRouter.scala:87:24] wire out_wimask_817 = &_out_wimask_T_817; // @[RegisterRouter.scala:87:24] wire out_romask_817 = \|_out_romask_T_817; // @[RegisterRouter.scala:87:24] wire out_womask_817 = &_out_womask_T_817; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_817 = out_rivalid_1_671 & out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8046 = out_f_rivalid_817; // @[RegisterRouter.scala:87:24] wire out_f_roready_817 = out_roready_1_671 & out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8047 = out_f_roready_817; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_817 = out_wivalid_1_671 & out_wimask_817; // @[RegisterRouter.scala:87:24] wire out_f_woready_817 = out_woready_1_671 & out_womask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8048 = ~out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8049 = ~out_wimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8050 = ~out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8051 = ~out_womask_817; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_696 = {hi_735, flags_0_go, _out_prepend_T_696}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8052 = out_prepend_696; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8053 = _out_T_8052; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_697 = _out_T_8053; // @[RegisterRouter.scala:87:24] wire out_rimask_818 = \|_out_rimask_T_818; // @[RegisterRouter.scala:87:24] wire out_wimask_818 = &_out_wimask_T_818; // @[RegisterRouter.scala:87:24] wire out_romask_818 = \|_out_romask_T_818; // @[RegisterRouter.scala:87:24] wire out_womask_818 = &_out_womask_T_818; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_818 = out_rivalid_1_672 & out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8055 = out_f_rivalid_818; // @[RegisterRouter.scala:87:24] wire out_f_roready_818 = out_roready_1_672 & out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8056 = out_f_roready_818; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_818 = out_wivalid_1_672 & out_wimask_818; // @[RegisterRouter.scala:87:24] wire out_f_woready_818 = out_woready_1_672 & out_womask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8057 = ~out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8058 = ~out_wimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8059 = ~out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8060 = ~out_womask_818; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_697 = {hi_736, flags_0_go, _out_prepend_T_697}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8061 = out_prepend_697; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8062 = _out_T_8061; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_219 = _out_T_8062; // @[MuxLiteral.scala:49:48] wire out_rimask_819 = \|_out_rimask_T_819; // @[RegisterRouter.scala:87:24] wire out_wimask_819 = &_out_wimask_T_819; // @[RegisterRouter.scala:87:24] wire out_romask_819 = \|_out_romask_T_819; // @[RegisterRouter.scala:87:24] wire out_womask_819 = &_out_womask_T_819; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_819 = out_rivalid_1_673 & out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8064 = out_f_rivalid_819; // @[RegisterRouter.scala:87:24] wire out_f_roready_819 = out_roready_1_673 & out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8065 = out_f_roready_819; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_819 = out_wivalid_1_673 & out_wimask_819; // @[RegisterRouter.scala:87:24] wire out_f_woready_819 = out_woready_1_673 & out_womask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8066 = ~out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8067 = ~out_wimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8068 = ~out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8069 = ~out_womask_819; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8071 = _out_T_8070; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_698 = _out_T_8071; // @[RegisterRouter.scala:87:24] wire out_rimask_820 = \|_out_rimask_T_820; // @[RegisterRouter.scala:87:24] wire out_wimask_820 = &_out_wimask_T_820; // @[RegisterRouter.scala:87:24] wire out_romask_820 = \|_out_romask_T_820; // @[RegisterRouter.scala:87:24] wire out_womask_820 = &_out_womask_T_820; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_820 = out_rivalid_1_674 & out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8073 = out_f_rivalid_820; // @[RegisterRouter.scala:87:24] wire out_f_roready_820 = out_roready_1_674 & out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8074 = out_f_roready_820; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_820 = out_wivalid_1_674 & out_wimask_820; // @[RegisterRouter.scala:87:24] wire out_f_woready_820 = out_woready_1_674 & out_womask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8075 = ~out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8076 = ~out_wimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8077 = ~out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8078 = ~out_womask_820; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_698 = {hi_818, flags_0_go, _out_prepend_T_698}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8079 = out_prepend_698; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8080 = _out_T_8079; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_699 = _out_T_8080; // @[RegisterRouter.scala:87:24] wire out_rimask_821 = \|_out_rimask_T_821; // @[RegisterRouter.scala:87:24] wire out_wimask_821 = &_out_wimask_T_821; // @[RegisterRouter.scala:87:24] wire out_romask_821 = \|_out_romask_T_821; // @[RegisterRouter.scala:87:24] wire out_womask_821 = &_out_womask_T_821; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_821 = out_rivalid_1_675 & out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8082 = out_f_rivalid_821; // @[RegisterRouter.scala:87:24] wire out_f_roready_821 = out_roready_1_675 & out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8083 = out_f_roready_821; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_821 = out_wivalid_1_675 & out_wimask_821; // @[RegisterRouter.scala:87:24] wire out_f_woready_821 = out_woready_1_675 & out_womask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8084 = ~out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8085 = ~out_wimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8086 = ~out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8087 = ~out_womask_821; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_699 = {hi_819, flags_0_go, _out_prepend_T_699}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8088 = out_prepend_699; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8089 = _out_T_8088; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_700 = _out_T_8089; // @[RegisterRouter.scala:87:24] wire out_rimask_822 = \|_out_rimask_T_822; // @[RegisterRouter.scala:87:24] wire out_wimask_822 = &_out_wimask_T_822; // @[RegisterRouter.scala:87:24] wire out_romask_822 = \|_out_romask_T_822; // @[RegisterRouter.scala:87:24] wire out_womask_822 = &_out_womask_T_822; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_822 = out_rivalid_1_676 & out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8091 = out_f_rivalid_822; // @[RegisterRouter.scala:87:24] wire out_f_roready_822 = out_roready_1_676 & out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8092 = out_f_roready_822; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_822 = out_wivalid_1_676 & out_wimask_822; // @[RegisterRouter.scala:87:24] wire out_f_woready_822 = out_woready_1_676 & out_womask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8093 = ~out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8094 = ~out_wimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8095 = ~out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8096 = ~out_womask_822; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_700 = {hi_820, flags_0_go, _out_prepend_T_700}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8097 = out_prepend_700; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8098 = _out_T_8097; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_701 = _out_T_8098; // @[RegisterRouter.scala:87:24] wire out_rimask_823 = \|_out_rimask_T_823; // @[RegisterRouter.scala:87:24] wire out_wimask_823 = &_out_wimask_T_823; // @[RegisterRouter.scala:87:24] wire out_romask_823 = \|_out_romask_T_823; // @[RegisterRouter.scala:87:24] wire out_womask_823 = &_out_womask_T_823; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_823 = out_rivalid_1_677 & out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8100 = out_f_rivalid_823; // @[RegisterRouter.scala:87:24] wire out_f_roready_823 = out_roready_1_677 & out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8101 = out_f_roready_823; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_823 = out_wivalid_1_677 & out_wimask_823; // @[RegisterRouter.scala:87:24] wire out_f_woready_823 = out_woready_1_677 & out_womask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8102 = ~out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8103 = ~out_wimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8104 = ~out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8105 = ~out_womask_823; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_701 = {hi_821, flags_0_go, _out_prepend_T_701}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8106 = out_prepend_701; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8107 = _out_T_8106; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_702 = _out_T_8107; // @[RegisterRouter.scala:87:24] wire out_rimask_824 = \|_out_rimask_T_824; // @[RegisterRouter.scala:87:24] wire out_wimask_824 = &_out_wimask_T_824; // @[RegisterRouter.scala:87:24] wire out_romask_824 = \|_out_romask_T_824; // @[RegisterRouter.scala:87:24] wire out_womask_824 = &_out_womask_T_824; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_824 = out_rivalid_1_678 & out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8109 = out_f_rivalid_824; // @[RegisterRouter.scala:87:24] wire out_f_roready_824 = out_roready_1_678 & out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8110 = out_f_roready_824; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_824 = out_wivalid_1_678 & out_wimask_824; // @[RegisterRouter.scala:87:24] wire out_f_woready_824 = out_woready_1_678 & out_womask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8111 = ~out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8112 = ~out_wimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8113 = ~out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8114 = ~out_womask_824; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_702 = {hi_822, flags_0_go, _out_prepend_T_702}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8115 = out_prepend_702; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8116 = _out_T_8115; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_703 = _out_T_8116; // @[RegisterRouter.scala:87:24] wire out_rimask_825 = \|_out_rimask_T_825; // @[RegisterRouter.scala:87:24] wire out_wimask_825 = &_out_wimask_T_825; // @[RegisterRouter.scala:87:24] wire out_romask_825 = \|_out_romask_T_825; // @[RegisterRouter.scala:87:24] wire out_womask_825 = &_out_womask_T_825; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_825 = out_rivalid_1_679 & out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8118 = out_f_rivalid_825; // @[RegisterRouter.scala:87:24] wire out_f_roready_825 = out_roready_1_679 & out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8119 = out_f_roready_825; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_825 = out_wivalid_1_679 & out_wimask_825; // @[RegisterRouter.scala:87:24] wire out_f_woready_825 = out_woready_1_679 & out_womask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8120 = ~out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8121 = ~out_wimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8122 = ~out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8123 = ~out_womask_825; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_703 = {hi_823, flags_0_go, _out_prepend_T_703}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8124 = out_prepend_703; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8125 = _out_T_8124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_704 = _out_T_8125; // @[RegisterRouter.scala:87:24] wire out_rimask_826 = \|_out_rimask_T_826; // @[RegisterRouter.scala:87:24] wire out_wimask_826 = &_out_wimask_T_826; // @[RegisterRouter.scala:87:24] wire out_romask_826 = \|_out_romask_T_826; // @[RegisterRouter.scala:87:24] wire out_womask_826 = &_out_womask_T_826; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_826 = out_rivalid_1_680 & out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8127 = out_f_rivalid_826; // @[RegisterRouter.scala:87:24] wire out_f_roready_826 = out_roready_1_680 & out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8128 = out_f_roready_826; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_826 = out_wivalid_1_680 & out_wimask_826; // @[RegisterRouter.scala:87:24] wire out_f_woready_826 = out_woready_1_680 & out_womask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8129 = ~out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8130 = ~out_wimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8131 = ~out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8132 = ~out_womask_826; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_704 = {hi_824, flags_0_go, _out_prepend_T_704}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8133 = out_prepend_704; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8134 = _out_T_8133; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_230 = _out_T_8134; // @[MuxLiteral.scala:49:48] wire out_rimask_827 = \|_out_rimask_T_827; // @[RegisterRouter.scala:87:24] wire out_wimask_827 = &_out_wimask_T_827; // @[RegisterRouter.scala:87:24] wire out_romask_827 = \|_out_romask_T_827; // @[RegisterRouter.scala:87:24] wire out_womask_827 = &_out_womask_T_827; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_827 = out_rivalid_1_681 & out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8136 = out_f_rivalid_827; // @[RegisterRouter.scala:87:24] wire out_f_roready_827 = out_roready_1_681 & out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8137 = out_f_roready_827; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_827 = out_wivalid_1_681 & out_wimask_827; // @[RegisterRouter.scala:87:24] wire out_f_woready_827 = out_woready_1_681 & out_womask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8138 = ~out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8139 = ~out_wimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8140 = ~out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8141 = ~out_womask_827; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8143 = _out_T_8142; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_705 = _out_T_8143; // @[RegisterRouter.scala:87:24] wire out_rimask_828 = \|_out_rimask_T_828; // @[RegisterRouter.scala:87:24] wire out_wimask_828 = &_out_wimask_T_828; // @[RegisterRouter.scala:87:24] wire out_romask_828 = \|_out_romask_T_828; // @[RegisterRouter.scala:87:24] wire out_womask_828 = &_out_womask_T_828; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_828 = out_rivalid_1_682 & out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8145 = out_f_rivalid_828; // @[RegisterRouter.scala:87:24] wire out_f_roready_828 = out_roready_1_682 & out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8146 = out_f_roready_828; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_828 = out_wivalid_1_682 & out_wimask_828; // @[RegisterRouter.scala:87:24] wire out_f_woready_828 = out_woready_1_682 & out_womask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8147 = ~out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8148 = ~out_wimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8149 = ~out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8150 = ~out_womask_828; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_705 = {hi_938, flags_0_go, _out_prepend_T_705}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8151 = out_prepend_705; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8152 = _out_T_8151; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_706 = _out_T_8152; // @[RegisterRouter.scala:87:24] wire out_rimask_829 = \|_out_rimask_T_829; // @[RegisterRouter.scala:87:24] wire out_wimask_829 = &_out_wimask_T_829; // @[RegisterRouter.scala:87:24] wire out_romask_829 = \|_out_romask_T_829; // @[RegisterRouter.scala:87:24] wire out_womask_829 = &_out_womask_T_829; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_829 = out_rivalid_1_683 & out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8154 = out_f_rivalid_829; // @[RegisterRouter.scala:87:24] wire out_f_roready_829 = out_roready_1_683 & out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8155 = out_f_roready_829; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_829 = out_wivalid_1_683 & out_wimask_829; // @[RegisterRouter.scala:87:24] wire out_f_woready_829 = out_woready_1_683 & out_womask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8156 = ~out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8157 = ~out_wimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8158 = ~out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8159 = ~out_womask_829; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_706 = {hi_939, flags_0_go, _out_prepend_T_706}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8160 = out_prepend_706; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8161 = _out_T_8160; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_707 = _out_T_8161; // @[RegisterRouter.scala:87:24] wire out_rimask_830 = \|_out_rimask_T_830; // @[RegisterRouter.scala:87:24] wire out_wimask_830 = &_out_wimask_T_830; // @[RegisterRouter.scala:87:24] wire out_romask_830 = \|_out_romask_T_830; // @[RegisterRouter.scala:87:24] wire out_womask_830 = &_out_womask_T_830; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_830 = out_rivalid_1_684 & out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8163 = out_f_rivalid_830; // @[RegisterRouter.scala:87:24] wire out_f_roready_830 = out_roready_1_684 & out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8164 = out_f_roready_830; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_830 = out_wivalid_1_684 & out_wimask_830; // @[RegisterRouter.scala:87:24] wire out_f_woready_830 = out_woready_1_684 & out_womask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8165 = ~out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8166 = ~out_wimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8167 = ~out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8168 = ~out_womask_830; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_707 = {hi_940, flags_0_go, _out_prepend_T_707}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8169 = out_prepend_707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8170 = _out_T_8169; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_708 = _out_T_8170; // @[RegisterRouter.scala:87:24] wire out_rimask_831 = \|_out_rimask_T_831; // @[RegisterRouter.scala:87:24] wire out_wimask_831 = &_out_wimask_T_831; // @[RegisterRouter.scala:87:24] wire out_romask_831 = \|_out_romask_T_831; // @[RegisterRouter.scala:87:24] wire out_womask_831 = &_out_womask_T_831; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_831 = out_rivalid_1_685 & out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8172 = out_f_rivalid_831; // @[RegisterRouter.scala:87:24] wire out_f_roready_831 = out_roready_1_685 & out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8173 = out_f_roready_831; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_831 = out_wivalid_1_685 & out_wimask_831; // @[RegisterRouter.scala:87:24] wire out_f_woready_831 = out_woready_1_685 & out_womask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8174 = ~out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8175 = ~out_wimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8176 = ~out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8177 = ~out_womask_831; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_708 = {hi_941, flags_0_go, _out_prepend_T_708}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8178 = out_prepend_708; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8179 = _out_T_8178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_709 = _out_T_8179; // @[RegisterRouter.scala:87:24] wire out_rimask_832 = \|_out_rimask_T_832; // @[RegisterRouter.scala:87:24] wire out_wimask_832 = &_out_wimask_T_832; // @[RegisterRouter.scala:87:24] wire out_romask_832 = \|_out_romask_T_832; // @[RegisterRouter.scala:87:24] wire out_womask_832 = &_out_womask_T_832; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_832 = out_rivalid_1_686 & out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8181 = out_f_rivalid_832; // @[RegisterRouter.scala:87:24] wire out_f_roready_832 = out_roready_1_686 & out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8182 = out_f_roready_832; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_832 = out_wivalid_1_686 & out_wimask_832; // @[RegisterRouter.scala:87:24] wire out_f_woready_832 = out_woready_1_686 & out_womask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8183 = ~out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8184 = ~out_wimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8185 = ~out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8186 = ~out_womask_832; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_709 = {hi_942, flags_0_go, _out_prepend_T_709}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8187 = out_prepend_709; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8188 = _out_T_8187; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_710 = _out_T_8188; // @[RegisterRouter.scala:87:24] wire out_rimask_833 = \|_out_rimask_T_833; // @[RegisterRouter.scala:87:24] wire out_wimask_833 = &_out_wimask_T_833; // @[RegisterRouter.scala:87:24] wire out_romask_833 = \|_out_romask_T_833; // @[RegisterRouter.scala:87:24] wire out_womask_833 = &_out_womask_T_833; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_833 = out_rivalid_1_687 & out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8190 = out_f_rivalid_833; // @[RegisterRouter.scala:87:24] wire out_f_roready_833 = out_roready_1_687 & out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8191 = out_f_roready_833; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_833 = out_wivalid_1_687 & out_wimask_833; // @[RegisterRouter.scala:87:24] wire out_f_woready_833 = out_woready_1_687 & out_womask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8192 = ~out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8193 = ~out_wimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8194 = ~out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8195 = ~out_womask_833; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_710 = {hi_943, flags_0_go, _out_prepend_T_710}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8196 = out_prepend_710; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8197 = _out_T_8196; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_711 = _out_T_8197; // @[RegisterRouter.scala:87:24] wire out_rimask_834 = \|_out_rimask_T_834; // @[RegisterRouter.scala:87:24] wire out_wimask_834 = &_out_wimask_T_834; // @[RegisterRouter.scala:87:24] wire out_romask_834 = \|_out_romask_T_834; // @[RegisterRouter.scala:87:24] wire out_womask_834 = &_out_womask_T_834; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_834 = out_rivalid_1_688 & out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8199 = out_f_rivalid_834; // @[RegisterRouter.scala:87:24] wire out_f_roready_834 = out_roready_1_688 & out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8200 = out_f_roready_834; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_834 = out_wivalid_1_688 & out_wimask_834; // @[RegisterRouter.scala:87:24] wire out_f_woready_834 = out_woready_1_688 & out_womask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8201 = ~out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8202 = ~out_wimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8203 = ~out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8204 = ~out_womask_834; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_711 = {hi_944, flags_0_go, _out_prepend_T_711}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8205 = out_prepend_711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8206 = _out_T_8205; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_245 = _out_T_8206; // @[MuxLiteral.scala:49:48] wire out_rimask_835 = \|_out_rimask_T_835; // @[RegisterRouter.scala:87:24] wire out_wimask_835 = &_out_wimask_T_835; // @[RegisterRouter.scala:87:24] wire out_romask_835 = \|_out_romask_T_835; // @[RegisterRouter.scala:87:24] wire out_womask_835 = &_out_womask_T_835; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_835 = out_rivalid_1_689 & out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8208 = out_f_rivalid_835; // @[RegisterRouter.scala:87:24] wire out_f_roready_835 = out_roready_1_689 & out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8209 = out_f_roready_835; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_835 = out_wivalid_1_689 & out_wimask_835; // @[RegisterRouter.scala:87:24] wire out_f_woready_835 = out_woready_1_689 & out_womask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8210 = ~out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8211 = ~out_wimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8212 = ~out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8213 = ~out_womask_835; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8215 = _out_T_8214; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_712 = _out_T_8215; // @[RegisterRouter.scala:87:24] wire out_rimask_836 = \|_out_rimask_T_836; // @[RegisterRouter.scala:87:24] wire out_wimask_836 = &_out_wimask_T_836; // @[RegisterRouter.scala:87:24] wire out_romask_836 = \|_out_romask_T_836; // @[RegisterRouter.scala:87:24] wire out_womask_836 = &_out_womask_T_836; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_836 = out_rivalid_1_690 & out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8217 = out_f_rivalid_836; // @[RegisterRouter.scala:87:24] wire out_f_roready_836 = out_roready_1_690 & out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8218 = out_f_roready_836; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_836 = out_wivalid_1_690 & out_wimask_836; // @[RegisterRouter.scala:87:24] wire out_f_woready_836 = out_woready_1_690 & out_womask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8219 = ~out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8220 = ~out_wimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8221 = ~out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8222 = ~out_womask_836; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_712 = {hi_642, flags_0_go, _out_prepend_T_712}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8223 = out_prepend_712; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8224 = _out_T_8223; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_713 = _out_T_8224; // @[RegisterRouter.scala:87:24] wire out_rimask_837 = \|_out_rimask_T_837; // @[RegisterRouter.scala:87:24] wire out_wimask_837 = &_out_wimask_T_837; // @[RegisterRouter.scala:87:24] wire out_romask_837 = \|_out_romask_T_837; // @[RegisterRouter.scala:87:24] wire out_womask_837 = &_out_womask_T_837; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_837 = out_rivalid_1_691 & out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8226 = out_f_rivalid_837; // @[RegisterRouter.scala:87:24] wire out_f_roready_837 = out_roready_1_691 & out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8227 = out_f_roready_837; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_837 = out_wivalid_1_691 & out_wimask_837; // @[RegisterRouter.scala:87:24] wire out_f_woready_837 = out_woready_1_691 & out_womask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8228 = ~out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8229 = ~out_wimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8230 = ~out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8231 = ~out_womask_837; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_713 = {hi_643, flags_0_go, _out_prepend_T_713}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8232 = out_prepend_713; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8233 = _out_T_8232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_714 = _out_T_8233; // @[RegisterRouter.scala:87:24] wire out_rimask_838 = \|_out_rimask_T_838; // @[RegisterRouter.scala:87:24] wire out_wimask_838 = &_out_wimask_T_838; // @[RegisterRouter.scala:87:24] wire out_romask_838 = \|_out_romask_T_838; // @[RegisterRouter.scala:87:24] wire out_womask_838 = &_out_womask_T_838; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_838 = out_rivalid_1_692 & out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8235 = out_f_rivalid_838; // @[RegisterRouter.scala:87:24] wire out_f_roready_838 = out_roready_1_692 & out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8236 = out_f_roready_838; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_838 = out_wivalid_1_692 & out_wimask_838; // @[RegisterRouter.scala:87:24] wire out_f_woready_838 = out_woready_1_692 & out_womask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8237 = ~out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8238 = ~out_wimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8239 = ~out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8240 = ~out_womask_838; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_714 = {hi_644, flags_0_go, _out_prepend_T_714}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8241 = out_prepend_714; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8242 = _out_T_8241; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_715 = _out_T_8242; // @[RegisterRouter.scala:87:24] wire out_rimask_839 = \|_out_rimask_T_839; // @[RegisterRouter.scala:87:24] wire out_wimask_839 = &_out_wimask_T_839; // @[RegisterRouter.scala:87:24] wire out_romask_839 = \|_out_romask_T_839; // @[RegisterRouter.scala:87:24] wire out_womask_839 = &_out_womask_T_839; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_839 = out_rivalid_1_693 & out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8244 = out_f_rivalid_839; // @[RegisterRouter.scala:87:24] wire out_f_roready_839 = out_roready_1_693 & out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8245 = out_f_roready_839; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_839 = out_wivalid_1_693 & out_wimask_839; // @[RegisterRouter.scala:87:24] wire out_f_woready_839 = out_woready_1_693 & out_womask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8246 = ~out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8247 = ~out_wimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8248 = ~out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8249 = ~out_womask_839; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_715 = {hi_645, flags_0_go, _out_prepend_T_715}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8250 = out_prepend_715; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8251 = _out_T_8250; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_716 = _out_T_8251; // @[RegisterRouter.scala:87:24] wire out_rimask_840 = \|_out_rimask_T_840; // @[RegisterRouter.scala:87:24] wire out_wimask_840 = &_out_wimask_T_840; // @[RegisterRouter.scala:87:24] wire out_romask_840 = \|_out_romask_T_840; // @[RegisterRouter.scala:87:24] wire out_womask_840 = &_out_womask_T_840; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_840 = out_rivalid_1_694 & out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8253 = out_f_rivalid_840; // @[RegisterRouter.scala:87:24] wire out_f_roready_840 = out_roready_1_694 & out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8254 = out_f_roready_840; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_840 = out_wivalid_1_694 & out_wimask_840; // @[RegisterRouter.scala:87:24] wire out_f_woready_840 = out_woready_1_694 & out_womask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8255 = ~out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8256 = ~out_wimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8257 = ~out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8258 = ~out_womask_840; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_716 = {hi_646, flags_0_go, _out_prepend_T_716}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8259 = out_prepend_716; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8260 = _out_T_8259; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_717 = _out_T_8260; // @[RegisterRouter.scala:87:24] wire out_rimask_841 = \|_out_rimask_T_841; // @[RegisterRouter.scala:87:24] wire out_wimask_841 = &_out_wimask_T_841; // @[RegisterRouter.scala:87:24] wire out_romask_841 = \|_out_romask_T_841; // @[RegisterRouter.scala:87:24] wire out_womask_841 = &_out_womask_T_841; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_841 = out_rivalid_1_695 & out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8262 = out_f_rivalid_841; // @[RegisterRouter.scala:87:24] wire out_f_roready_841 = out_roready_1_695 & out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8263 = out_f_roready_841; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_841 = out_wivalid_1_695 & out_wimask_841; // @[RegisterRouter.scala:87:24] wire out_f_woready_841 = out_woready_1_695 & out_womask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8264 = ~out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8265 = ~out_wimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8266 = ~out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8267 = ~out_womask_841; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_717 = {hi_647, flags_0_go, _out_prepend_T_717}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8268 = out_prepend_717; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8269 = _out_T_8268; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_718 = _out_T_8269; // @[RegisterRouter.scala:87:24] wire out_rimask_842 = \|_out_rimask_T_842; // @[RegisterRouter.scala:87:24] wire out_wimask_842 = &_out_wimask_T_842; // @[RegisterRouter.scala:87:24] wire out_romask_842 = \|_out_romask_T_842; // @[RegisterRouter.scala:87:24] wire out_womask_842 = &_out_womask_T_842; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_842 = out_rivalid_1_696 & out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8271 = out_f_rivalid_842; // @[RegisterRouter.scala:87:24] wire out_f_roready_842 = out_roready_1_696 & out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8272 = out_f_roready_842; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_842 = out_wivalid_1_696 & out_wimask_842; // @[RegisterRouter.scala:87:24] wire out_f_woready_842 = out_woready_1_696 & out_womask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8273 = ~out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8274 = ~out_wimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8275 = ~out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8276 = ~out_womask_842; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_718 = {hi_648, flags_0_go, _out_prepend_T_718}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8277 = out_prepend_718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8278 = _out_T_8277; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_208 = _out_T_8278; // @[MuxLiteral.scala:49:48] wire out_rimask_843 = \|_out_rimask_T_843; // @[RegisterRouter.scala:87:24] wire out_wimask_843 = &_out_wimask_T_843; // @[RegisterRouter.scala:87:24] wire out_romask_843 = \|_out_romask_T_843; // @[RegisterRouter.scala:87:24] wire out_womask_843 = &_out_womask_T_843; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_843 = out_rivalid_1_697 & out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8280 = out_f_rivalid_843; // @[RegisterRouter.scala:87:24] wire out_f_roready_843 = out_roready_1_697 & out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8281 = out_f_roready_843; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_843 = out_wivalid_1_697 & out_wimask_843; // @[RegisterRouter.scala:87:24] wire out_f_woready_843 = out_woready_1_697 & out_womask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8282 = ~out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8283 = ~out_wimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8284 = ~out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8285 = ~out_womask_843; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8287 = _out_T_8286; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_719 = _out_T_8287; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_844 = \|_out_rimask_T_844; // @[RegisterRouter.scala:87:24] wire out_wimask_844 = &_out_wimask_T_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_844 = \|_out_romask_T_844; // @[RegisterRouter.scala:87:24] wire out_womask_844 = &_out_womask_T_844; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_844 = out_rivalid_1_698 & out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8289 = out_f_rivalid_844; // @[RegisterRouter.scala:87:24] wire out_f_roready_844 = out_roready_1_698 & out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8290 = out_f_roready_844; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_844 = out_wivalid_1_698 & out_wimask_844; // @[RegisterRouter.scala:87:24] wire out_f_woready_844 = out_woready_1_698 & out_womask_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8288 = out_front_1_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_8291 = ~out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8292 = ~out_wimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8293 = ~out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8294 = ~out_womask_844; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_719 = {abstractGeneratedMem_1, _out_prepend_T_719}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8295 = out_prepend_719; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8296 = _out_T_8295; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_103 = _out_T_8296; // @[MuxLiteral.scala:49:48] wire out_rimask_845 = \|_out_rimask_T_845; // @[RegisterRouter.scala:87:24] wire out_wimask_845 = &_out_wimask_T_845; // @[RegisterRouter.scala:87:24] wire out_romask_845 = \|_out_romask_T_845; // @[RegisterRouter.scala:87:24] wire out_womask_845 = &_out_womask_T_845; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_845 = out_rivalid_1_699 & out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8298 = out_f_rivalid_845; // @[RegisterRouter.scala:87:24] wire out_f_roready_845 = out_roready_1_699 & out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8299 = out_f_roready_845; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_845 = out_wivalid_1_699 & out_wimask_845; // @[RegisterRouter.scala:87:24] wire out_f_woready_845 = out_woready_1_699 & out_womask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8300 = ~out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8301 = ~out_wimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8302 = ~out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8303 = ~out_womask_845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8305 = _out_T_8304; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_720 = _out_T_8305; // @[RegisterRouter.scala:87:24] wire out_rimask_846 = \|_out_rimask_T_846; // @[RegisterRouter.scala:87:24] wire out_wimask_846 = &_out_wimask_T_846; // @[RegisterRouter.scala:87:24] wire out_romask_846 = \|_out_romask_T_846; // @[RegisterRouter.scala:87:24] wire out_womask_846 = &_out_womask_T_846; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_846 = out_rivalid_1_700 & out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8307 = out_f_rivalid_846; // @[RegisterRouter.scala:87:24] wire out_f_roready_846 = out_roready_1_700 & out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8308 = out_f_roready_846; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_846 = out_wivalid_1_700 & out_wimask_846; // @[RegisterRouter.scala:87:24] wire out_f_woready_846 = out_woready_1_700 & out_womask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8309 = ~out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8310 = ~out_wimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8311 = ~out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8312 = ~out_womask_846; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_720 = {hi_98, flags_0_go, _out_prepend_T_720}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8313 = out_prepend_720; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8314 = _out_T_8313; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_721 = _out_T_8314; // @[RegisterRouter.scala:87:24] wire out_rimask_847 = \|_out_rimask_T_847; // @[RegisterRouter.scala:87:24] wire out_wimask_847 = &_out_wimask_T_847; // @[RegisterRouter.scala:87:24] wire out_romask_847 = \|_out_romask_T_847; // @[RegisterRouter.scala:87:24] wire out_womask_847 = &_out_womask_T_847; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_847 = out_rivalid_1_701 & out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8316 = out_f_rivalid_847; // @[RegisterRouter.scala:87:24] wire out_f_roready_847 = out_roready_1_701 & out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8317 = out_f_roready_847; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_847 = out_wivalid_1_701 & out_wimask_847; // @[RegisterRouter.scala:87:24] wire out_f_woready_847 = out_woready_1_701 & out_womask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8318 = ~out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8319 = ~out_wimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8320 = ~out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8321 = ~out_womask_847; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_721 = {hi_99, flags_0_go, _out_prepend_T_721}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8322 = out_prepend_721; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8323 = _out_T_8322; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_722 = _out_T_8323; // @[RegisterRouter.scala:87:24] wire out_rimask_848 = \|_out_rimask_T_848; // @[RegisterRouter.scala:87:24] wire out_wimask_848 = &_out_wimask_T_848; // @[RegisterRouter.scala:87:24] wire out_romask_848 = \|_out_romask_T_848; // @[RegisterRouter.scala:87:24] wire out_womask_848 = &_out_womask_T_848; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_848 = out_rivalid_1_702 & out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8325 = out_f_rivalid_848; // @[RegisterRouter.scala:87:24] wire out_f_roready_848 = out_roready_1_702 & out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8326 = out_f_roready_848; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_848 = out_wivalid_1_702 & out_wimask_848; // @[RegisterRouter.scala:87:24] wire out_f_woready_848 = out_woready_1_702 & out_womask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8327 = ~out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8328 = ~out_wimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8329 = ~out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8330 = ~out_womask_848; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_722 = {hi_100, flags_0_go, _out_prepend_T_722}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8331 = out_prepend_722; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8332 = _out_T_8331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_723 = _out_T_8332; // @[RegisterRouter.scala:87:24] wire out_rimask_849 = \|_out_rimask_T_849; // @[RegisterRouter.scala:87:24] wire out_wimask_849 = &_out_wimask_T_849; // @[RegisterRouter.scala:87:24] wire out_romask_849 = \|_out_romask_T_849; // @[RegisterRouter.scala:87:24] wire out_womask_849 = &_out_womask_T_849; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_849 = out_rivalid_1_703 & out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8334 = out_f_rivalid_849; // @[RegisterRouter.scala:87:24] wire out_f_roready_849 = out_roready_1_703 & out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8335 = out_f_roready_849; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_849 = out_wivalid_1_703 & out_wimask_849; // @[RegisterRouter.scala:87:24] wire out_f_woready_849 = out_woready_1_703 & out_womask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8336 = ~out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8337 = ~out_wimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8338 = ~out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8339 = ~out_womask_849; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_723 = {hi_101, flags_0_go, _out_prepend_T_723}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8340 = out_prepend_723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8341 = _out_T_8340; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_724 = _out_T_8341; // @[RegisterRouter.scala:87:24] wire out_rimask_850 = \|_out_rimask_T_850; // @[RegisterRouter.scala:87:24] wire out_wimask_850 = &_out_wimask_T_850; // @[RegisterRouter.scala:87:24] wire out_romask_850 = \|_out_romask_T_850; // @[RegisterRouter.scala:87:24] wire out_womask_850 = &_out_womask_T_850; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_850 = out_rivalid_1_704 & out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8343 = out_f_rivalid_850; // @[RegisterRouter.scala:87:24] wire out_f_roready_850 = out_roready_1_704 & out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8344 = out_f_roready_850; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_850 = out_wivalid_1_704 & out_wimask_850; // @[RegisterRouter.scala:87:24] wire out_f_woready_850 = out_woready_1_704 & out_womask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8345 = ~out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8346 = ~out_wimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8347 = ~out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8348 = ~out_womask_850; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_724 = {hi_102, flags_0_go, _out_prepend_T_724}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8349 = out_prepend_724; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8350 = _out_T_8349; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_725 = _out_T_8350; // @[RegisterRouter.scala:87:24] wire out_rimask_851 = \|_out_rimask_T_851; // @[RegisterRouter.scala:87:24] wire out_wimask_851 = &_out_wimask_T_851; // @[RegisterRouter.scala:87:24] wire out_romask_851 = \|_out_romask_T_851; // @[RegisterRouter.scala:87:24] wire out_womask_851 = &_out_womask_T_851; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_851 = out_rivalid_1_705 & out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8352 = out_f_rivalid_851; // @[RegisterRouter.scala:87:24] wire out_f_roready_851 = out_roready_1_705 & out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8353 = out_f_roready_851; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_851 = out_wivalid_1_705 & out_wimask_851; // @[RegisterRouter.scala:87:24] wire out_f_woready_851 = out_woready_1_705 & out_womask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8354 = ~out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8355 = ~out_wimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8356 = ~out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8357 = ~out_womask_851; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_725 = {hi_103, flags_0_go, _out_prepend_T_725}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8358 = out_prepend_725; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8359 = _out_T_8358; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_726 = _out_T_8359; // @[RegisterRouter.scala:87:24] wire out_rimask_852 = \|_out_rimask_T_852; // @[RegisterRouter.scala:87:24] wire out_wimask_852 = &_out_wimask_T_852; // @[RegisterRouter.scala:87:24] wire out_romask_852 = \|_out_romask_T_852; // @[RegisterRouter.scala:87:24] wire out_womask_852 = &_out_womask_T_852; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_852 = out_rivalid_1_706 & out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8361 = out_f_rivalid_852; // @[RegisterRouter.scala:87:24] wire out_f_roready_852 = out_roready_1_706 & out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8362 = out_f_roready_852; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_852 = out_wivalid_1_706 & out_wimask_852; // @[RegisterRouter.scala:87:24] wire out_f_woready_852 = out_woready_1_706 & out_womask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8363 = ~out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8364 = ~out_wimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8365 = ~out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8366 = ~out_womask_852; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_726 = {hi_104, flags_0_go, _out_prepend_T_726}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8367 = out_prepend_726; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8368 = _out_T_8367; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_140 = _out_T_8368; // @[MuxLiteral.scala:49:48] wire out_rimask_853 = \|_out_rimask_T_853; // @[RegisterRouter.scala:87:24] wire out_wimask_853 = &_out_wimask_T_853; // @[RegisterRouter.scala:87:24] wire out_romask_853 = \|_out_romask_T_853; // @[RegisterRouter.scala:87:24] wire out_womask_853 = &_out_womask_T_853; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_853 = out_rivalid_1_707 & out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8370 = out_f_rivalid_853; // @[RegisterRouter.scala:87:24] wire out_f_roready_853 = out_roready_1_707 & out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8371 = out_f_roready_853; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_853 = out_wivalid_1_707 & out_wimask_853; // @[RegisterRouter.scala:87:24] wire out_f_woready_853 = out_woready_1_707 & out_womask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8372 = ~out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8373 = ~out_wimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8374 = ~out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8375 = ~out_womask_853; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8377 = _out_T_8376; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_727 = _out_T_8377; // @[RegisterRouter.scala:87:24] wire out_rimask_854 = \|_out_rimask_T_854; // @[RegisterRouter.scala:87:24] wire out_wimask_854 = &_out_wimask_T_854; // @[RegisterRouter.scala:87:24] wire out_romask_854 = \|_out_romask_T_854; // @[RegisterRouter.scala:87:24] wire out_womask_854 = &_out_womask_T_854; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_854 = out_rivalid_1_708 & out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8379 = out_f_rivalid_854; // @[RegisterRouter.scala:87:24] wire out_f_roready_854 = out_roready_1_708 & out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8380 = out_f_roready_854; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_854 = out_wivalid_1_708 & out_wimask_854; // @[RegisterRouter.scala:87:24] wire out_f_woready_854 = out_woready_1_708 & out_womask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8381 = ~out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8382 = ~out_wimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8383 = ~out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8384 = ~out_womask_854; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_727 = {hi_682, flags_0_go, _out_prepend_T_727}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8385 = out_prepend_727; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8386 = _out_T_8385; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_728 = _out_T_8386; // @[RegisterRouter.scala:87:24] wire out_rimask_855 = \|_out_rimask_T_855; // @[RegisterRouter.scala:87:24] wire out_wimask_855 = &_out_wimask_T_855; // @[RegisterRouter.scala:87:24] wire out_romask_855 = \|_out_romask_T_855; // @[RegisterRouter.scala:87:24] wire out_womask_855 = &_out_womask_T_855; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_855 = out_rivalid_1_709 & out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8388 = out_f_rivalid_855; // @[RegisterRouter.scala:87:24] wire out_f_roready_855 = out_roready_1_709 & out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8389 = out_f_roready_855; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_855 = out_wivalid_1_709 & out_wimask_855; // @[RegisterRouter.scala:87:24] wire out_f_woready_855 = out_woready_1_709 & out_womask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8390 = ~out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8391 = ~out_wimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8392 = ~out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8393 = ~out_womask_855; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_728 = {hi_683, flags_0_go, _out_prepend_T_728}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8394 = out_prepend_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8395 = _out_T_8394; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_729 = _out_T_8395; // @[RegisterRouter.scala:87:24] wire out_rimask_856 = \|_out_rimask_T_856; // @[RegisterRouter.scala:87:24] wire out_wimask_856 = &_out_wimask_T_856; // @[RegisterRouter.scala:87:24] wire out_romask_856 = \|_out_romask_T_856; // @[RegisterRouter.scala:87:24] wire out_womask_856 = &_out_womask_T_856; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_856 = out_rivalid_1_710 & out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8397 = out_f_rivalid_856; // @[RegisterRouter.scala:87:24] wire out_f_roready_856 = out_roready_1_710 & out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8398 = out_f_roready_856; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_856 = out_wivalid_1_710 & out_wimask_856; // @[RegisterRouter.scala:87:24] wire out_f_woready_856 = out_woready_1_710 & out_womask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8399 = ~out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8400 = ~out_wimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8401 = ~out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8402 = ~out_womask_856; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_729 = {hi_684, flags_0_go, _out_prepend_T_729}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8403 = out_prepend_729; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8404 = _out_T_8403; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_730 = _out_T_8404; // @[RegisterRouter.scala:87:24] wire out_rimask_857 = \|_out_rimask_T_857; // @[RegisterRouter.scala:87:24] wire out_wimask_857 = &_out_wimask_T_857; // @[RegisterRouter.scala:87:24] wire out_romask_857 = \|_out_romask_T_857; // @[RegisterRouter.scala:87:24] wire out_womask_857 = &_out_womask_T_857; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_857 = out_rivalid_1_711 & out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8406 = out_f_rivalid_857; // @[RegisterRouter.scala:87:24] wire out_f_roready_857 = out_roready_1_711 & out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8407 = out_f_roready_857; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_857 = out_wivalid_1_711 & out_wimask_857; // @[RegisterRouter.scala:87:24] wire out_f_woready_857 = out_woready_1_711 & out_womask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8408 = ~out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8409 = ~out_wimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8410 = ~out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8411 = ~out_womask_857; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_730 = {hi_685, flags_0_go, _out_prepend_T_730}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8412 = out_prepend_730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8413 = _out_T_8412; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_731 = _out_T_8413; // @[RegisterRouter.scala:87:24] wire out_rimask_858 = \|_out_rimask_T_858; // @[RegisterRouter.scala:87:24] wire out_wimask_858 = &_out_wimask_T_858; // @[RegisterRouter.scala:87:24] wire out_romask_858 = \|_out_romask_T_858; // @[RegisterRouter.scala:87:24] wire out_womask_858 = &_out_womask_T_858; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_858 = out_rivalid_1_712 & out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8415 = out_f_rivalid_858; // @[RegisterRouter.scala:87:24] wire out_f_roready_858 = out_roready_1_712 & out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8416 = out_f_roready_858; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_858 = out_wivalid_1_712 & out_wimask_858; // @[RegisterRouter.scala:87:24] wire out_f_woready_858 = out_woready_1_712 & out_womask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8417 = ~out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8418 = ~out_wimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8419 = ~out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8420 = ~out_womask_858; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_731 = {hi_686, flags_0_go, _out_prepend_T_731}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8421 = out_prepend_731; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8422 = _out_T_8421; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_732 = _out_T_8422; // @[RegisterRouter.scala:87:24] wire out_rimask_859 = \|_out_rimask_T_859; // @[RegisterRouter.scala:87:24] wire out_wimask_859 = &_out_wimask_T_859; // @[RegisterRouter.scala:87:24] wire out_romask_859 = \|_out_romask_T_859; // @[RegisterRouter.scala:87:24] wire out_womask_859 = &_out_womask_T_859; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_859 = out_rivalid_1_713 & out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8424 = out_f_rivalid_859; // @[RegisterRouter.scala:87:24] wire out_f_roready_859 = out_roready_1_713 & out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8425 = out_f_roready_859; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_859 = out_wivalid_1_713 & out_wimask_859; // @[RegisterRouter.scala:87:24] wire out_f_woready_859 = out_woready_1_713 & out_womask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8426 = ~out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8427 = ~out_wimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8428 = ~out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8429 = ~out_womask_859; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_732 = {hi_687, flags_0_go, _out_prepend_T_732}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8430 = out_prepend_732; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8431 = _out_T_8430; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_733 = _out_T_8431; // @[RegisterRouter.scala:87:24] wire out_rimask_860 = \|_out_rimask_T_860; // @[RegisterRouter.scala:87:24] wire out_wimask_860 = &_out_wimask_T_860; // @[RegisterRouter.scala:87:24] wire out_romask_860 = \|_out_romask_T_860; // @[RegisterRouter.scala:87:24] wire out_womask_860 = &_out_womask_T_860; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_860 = out_rivalid_1_714 & out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8433 = out_f_rivalid_860; // @[RegisterRouter.scala:87:24] wire out_f_roready_860 = out_roready_1_714 & out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8434 = out_f_roready_860; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_860 = out_wivalid_1_714 & out_wimask_860; // @[RegisterRouter.scala:87:24] wire out_f_woready_860 = out_woready_1_714 & out_womask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8435 = ~out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8436 = ~out_wimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8437 = ~out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8438 = ~out_womask_860; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_733 = {hi_688, flags_0_go, _out_prepend_T_733}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8439 = out_prepend_733; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8440 = _out_T_8439; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_213 = _out_T_8440; // @[MuxLiteral.scala:49:48] wire out_rimask_861 = \|_out_rimask_T_861; // @[RegisterRouter.scala:87:24] wire out_wimask_861 = &_out_wimask_T_861; // @[RegisterRouter.scala:87:24] wire out_romask_861 = \|_out_romask_T_861; // @[RegisterRouter.scala:87:24] wire out_womask_861 = &_out_womask_T_861; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_861 = out_rivalid_1_715 & out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8442 = out_f_rivalid_861; // @[RegisterRouter.scala:87:24] wire out_f_roready_861 = out_roready_1_715 & out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8443 = out_f_roready_861; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_861 = out_wivalid_1_715 & out_wimask_861; // @[RegisterRouter.scala:87:24] wire out_f_woready_861 = out_woready_1_715 & out_womask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8444 = ~out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8445 = ~out_wimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8446 = ~out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8447 = ~out_womask_861; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8449 = _out_T_8448; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_734 = _out_T_8449; // @[RegisterRouter.scala:87:24] wire out_rimask_862 = \|_out_rimask_T_862; // @[RegisterRouter.scala:87:24] wire out_wimask_862 = &_out_wimask_T_862; // @[RegisterRouter.scala:87:24] wire out_romask_862 = \|_out_romask_T_862; // @[RegisterRouter.scala:87:24] wire out_womask_862 = &_out_womask_T_862; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_862 = out_rivalid_1_716 & out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8451 = out_f_rivalid_862; // @[RegisterRouter.scala:87:24] wire out_f_roready_862 = out_roready_1_716 & out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8452 = out_f_roready_862; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_862 = out_wivalid_1_716 & out_wimask_862; // @[RegisterRouter.scala:87:24] wire out_f_woready_862 = out_woready_1_716 & out_womask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8453 = ~out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8454 = ~out_wimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8455 = ~out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8456 = ~out_womask_862; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_734 = {hi_218, flags_0_go, _out_prepend_T_734}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8457 = out_prepend_734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8458 = _out_T_8457; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_735 = _out_T_8458; // @[RegisterRouter.scala:87:24] wire out_rimask_863 = \|_out_rimask_T_863; // @[RegisterRouter.scala:87:24] wire out_wimask_863 = &_out_wimask_T_863; // @[RegisterRouter.scala:87:24] wire out_romask_863 = \|_out_romask_T_863; // @[RegisterRouter.scala:87:24] wire out_womask_863 = &_out_womask_T_863; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_863 = out_rivalid_1_717 & out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8460 = out_f_rivalid_863; // @[RegisterRouter.scala:87:24] wire out_f_roready_863 = out_roready_1_717 & out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8461 = out_f_roready_863; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_863 = out_wivalid_1_717 & out_wimask_863; // @[RegisterRouter.scala:87:24] wire out_f_woready_863 = out_woready_1_717 & out_womask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8462 = ~out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8463 = ~out_wimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8464 = ~out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8465 = ~out_womask_863; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_735 = {hi_219, flags_0_go, _out_prepend_T_735}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8466 = out_prepend_735; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8467 = _out_T_8466; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_736 = _out_T_8467; // @[RegisterRouter.scala:87:24] wire out_rimask_864 = \|_out_rimask_T_864; // @[RegisterRouter.scala:87:24] wire out_wimask_864 = &_out_wimask_T_864; // @[RegisterRouter.scala:87:24] wire out_romask_864 = \|_out_romask_T_864; // @[RegisterRouter.scala:87:24] wire out_womask_864 = &_out_womask_T_864; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_864 = out_rivalid_1_718 & out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8469 = out_f_rivalid_864; // @[RegisterRouter.scala:87:24] wire out_f_roready_864 = out_roready_1_718 & out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8470 = out_f_roready_864; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_864 = out_wivalid_1_718 & out_wimask_864; // @[RegisterRouter.scala:87:24] wire out_f_woready_864 = out_woready_1_718 & out_womask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8471 = ~out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8472 = ~out_wimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8473 = ~out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8474 = ~out_womask_864; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_736 = {hi_220, flags_0_go, _out_prepend_T_736}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8475 = out_prepend_736; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8476 = _out_T_8475; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_737 = _out_T_8476; // @[RegisterRouter.scala:87:24] wire out_rimask_865 = \|_out_rimask_T_865; // @[RegisterRouter.scala:87:24] wire out_wimask_865 = &_out_wimask_T_865; // @[RegisterRouter.scala:87:24] wire out_romask_865 = \|_out_romask_T_865; // @[RegisterRouter.scala:87:24] wire out_womask_865 = &_out_womask_T_865; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_865 = out_rivalid_1_719 & out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8478 = out_f_rivalid_865; // @[RegisterRouter.scala:87:24] wire out_f_roready_865 = out_roready_1_719 & out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8479 = out_f_roready_865; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_865 = out_wivalid_1_719 & out_wimask_865; // @[RegisterRouter.scala:87:24] wire out_f_woready_865 = out_woready_1_719 & out_womask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8480 = ~out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8481 = ~out_wimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8482 = ~out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8483 = ~out_womask_865; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_737 = {hi_221, flags_0_go, _out_prepend_T_737}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8484 = out_prepend_737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8485 = _out_T_8484; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_738 = _out_T_8485; // @[RegisterRouter.scala:87:24] wire out_rimask_866 = \|_out_rimask_T_866; // @[RegisterRouter.scala:87:24] wire out_wimask_866 = &_out_wimask_T_866; // @[RegisterRouter.scala:87:24] wire out_romask_866 = \|_out_romask_T_866; // @[RegisterRouter.scala:87:24] wire out_womask_866 = &_out_womask_T_866; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_866 = out_rivalid_1_720 & out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8487 = out_f_rivalid_866; // @[RegisterRouter.scala:87:24] wire out_f_roready_866 = out_roready_1_720 & out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8488 = out_f_roready_866; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_866 = out_wivalid_1_720 & out_wimask_866; // @[RegisterRouter.scala:87:24] wire out_f_woready_866 = out_woready_1_720 & out_womask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8489 = ~out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8490 = ~out_wimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8491 = ~out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8492 = ~out_womask_866; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_738 = {hi_222, flags_0_go, _out_prepend_T_738}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8493 = out_prepend_738; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8494 = _out_T_8493; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_739 = _out_T_8494; // @[RegisterRouter.scala:87:24] wire out_rimask_867 = \|_out_rimask_T_867; // @[RegisterRouter.scala:87:24] wire out_wimask_867 = &_out_wimask_T_867; // @[RegisterRouter.scala:87:24] wire out_romask_867 = \|_out_romask_T_867; // @[RegisterRouter.scala:87:24] wire out_womask_867 = &_out_womask_T_867; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_867 = out_rivalid_1_721 & out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8496 = out_f_rivalid_867; // @[RegisterRouter.scala:87:24] wire out_f_roready_867 = out_roready_1_721 & out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8497 = out_f_roready_867; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_867 = out_wivalid_1_721 & out_wimask_867; // @[RegisterRouter.scala:87:24] wire out_f_woready_867 = out_woready_1_721 & out_womask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8498 = ~out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8499 = ~out_wimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8500 = ~out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8501 = ~out_womask_867; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_739 = {hi_223, flags_0_go, _out_prepend_T_739}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8502 = out_prepend_739; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8503 = _out_T_8502; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_740 = _out_T_8503; // @[RegisterRouter.scala:87:24] wire out_rimask_868 = \|_out_rimask_T_868; // @[RegisterRouter.scala:87:24] wire out_wimask_868 = &_out_wimask_T_868; // @[RegisterRouter.scala:87:24] wire out_romask_868 = \|_out_romask_T_868; // @[RegisterRouter.scala:87:24] wire out_womask_868 = &_out_womask_T_868; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_868 = out_rivalid_1_722 & out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8505 = out_f_rivalid_868; // @[RegisterRouter.scala:87:24] wire out_f_roready_868 = out_roready_1_722 & out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8506 = out_f_roready_868; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_868 = out_wivalid_1_722 & out_wimask_868; // @[RegisterRouter.scala:87:24] wire out_f_woready_868 = out_woready_1_722 & out_womask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8507 = ~out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8508 = ~out_wimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8509 = ~out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8510 = ~out_womask_868; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_740 = {hi_224, flags_0_go, _out_prepend_T_740}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8511 = out_prepend_740; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8512 = _out_T_8511; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_155 = _out_T_8512; // @[MuxLiteral.scala:49:48] wire out_rimask_869 = \|_out_rimask_T_869; // @[RegisterRouter.scala:87:24] wire out_wimask_869 = &_out_wimask_T_869; // @[RegisterRouter.scala:87:24] wire out_romask_869 = \|_out_romask_T_869; // @[RegisterRouter.scala:87:24] wire out_womask_869 = &_out_womask_T_869; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_869 = out_rivalid_1_723 & out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8514 = out_f_rivalid_869; // @[RegisterRouter.scala:87:24] wire out_f_roready_869 = out_roready_1_723 & out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8515 = out_f_roready_869; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_869 = out_wivalid_1_723 & out_wimask_869; // @[RegisterRouter.scala:87:24] wire out_f_woready_869 = out_woready_1_723 & out_womask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8516 = ~out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8517 = ~out_wimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8518 = ~out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8519 = ~out_womask_869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8521 = _out_T_8520; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_741 = _out_T_8521; // @[RegisterRouter.scala:87:24] wire out_rimask_870 = \|_out_rimask_T_870; // @[RegisterRouter.scala:87:24] wire out_wimask_870 = &_out_wimask_T_870; // @[RegisterRouter.scala:87:24] wire out_romask_870 = \|_out_romask_T_870; // @[RegisterRouter.scala:87:24] wire out_womask_870 = &_out_womask_T_870; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_870 = out_rivalid_1_724 & out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8523 = out_f_rivalid_870; // @[RegisterRouter.scala:87:24] wire out_f_roready_870 = out_roready_1_724 & out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8524 = out_f_roready_870; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_870 = out_wivalid_1_724 & out_wimask_870; // @[RegisterRouter.scala:87:24] wire out_f_woready_870 = out_woready_1_724 & out_womask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8525 = ~out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8526 = ~out_wimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8527 = ~out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8528 = ~out_womask_870; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_741 = {hi_562, flags_0_go, _out_prepend_T_741}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8529 = out_prepend_741; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8530 = _out_T_8529; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_742 = _out_T_8530; // @[RegisterRouter.scala:87:24] wire out_rimask_871 = \|_out_rimask_T_871; // @[RegisterRouter.scala:87:24] wire out_wimask_871 = &_out_wimask_T_871; // @[RegisterRouter.scala:87:24] wire out_romask_871 = \|_out_romask_T_871; // @[RegisterRouter.scala:87:24] wire out_womask_871 = &_out_womask_T_871; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_871 = out_rivalid_1_725 & out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8532 = out_f_rivalid_871; // @[RegisterRouter.scala:87:24] wire out_f_roready_871 = out_roready_1_725 & out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8533 = out_f_roready_871; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_871 = out_wivalid_1_725 & out_wimask_871; // @[RegisterRouter.scala:87:24] wire out_f_woready_871 = out_woready_1_725 & out_womask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8534 = ~out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8535 = ~out_wimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8536 = ~out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8537 = ~out_womask_871; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_742 = {hi_563, flags_0_go, _out_prepend_T_742}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8538 = out_prepend_742; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8539 = _out_T_8538; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_743 = _out_T_8539; // @[RegisterRouter.scala:87:24] wire out_rimask_872 = \|_out_rimask_T_872; // @[RegisterRouter.scala:87:24] wire out_wimask_872 = &_out_wimask_T_872; // @[RegisterRouter.scala:87:24] wire out_romask_872 = \|_out_romask_T_872; // @[RegisterRouter.scala:87:24] wire out_womask_872 = &_out_womask_T_872; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_872 = out_rivalid_1_726 & out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8541 = out_f_rivalid_872; // @[RegisterRouter.scala:87:24] wire out_f_roready_872 = out_roready_1_726 & out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8542 = out_f_roready_872; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_872 = out_wivalid_1_726 & out_wimask_872; // @[RegisterRouter.scala:87:24] wire out_f_woready_872 = out_woready_1_726 & out_womask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8543 = ~out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8544 = ~out_wimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8545 = ~out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8546 = ~out_womask_872; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_743 = {hi_564, flags_0_go, _out_prepend_T_743}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8547 = out_prepend_743; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8548 = _out_T_8547; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_744 = _out_T_8548; // @[RegisterRouter.scala:87:24] wire out_rimask_873 = \|_out_rimask_T_873; // @[RegisterRouter.scala:87:24] wire out_wimask_873 = &_out_wimask_T_873; // @[RegisterRouter.scala:87:24] wire out_romask_873 = \|_out_romask_T_873; // @[RegisterRouter.scala:87:24] wire out_womask_873 = &_out_womask_T_873; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_873 = out_rivalid_1_727 & out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8550 = out_f_rivalid_873; // @[RegisterRouter.scala:87:24] wire out_f_roready_873 = out_roready_1_727 & out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8551 = out_f_roready_873; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_873 = out_wivalid_1_727 & out_wimask_873; // @[RegisterRouter.scala:87:24] wire out_f_woready_873 = out_woready_1_727 & out_womask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8552 = ~out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8553 = ~out_wimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8554 = ~out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8555 = ~out_womask_873; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_744 = {hi_565, flags_0_go, _out_prepend_T_744}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8556 = out_prepend_744; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8557 = _out_T_8556; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_745 = _out_T_8557; // @[RegisterRouter.scala:87:24] wire out_rimask_874 = \|_out_rimask_T_874; // @[RegisterRouter.scala:87:24] wire out_wimask_874 = &_out_wimask_T_874; // @[RegisterRouter.scala:87:24] wire out_romask_874 = \|_out_romask_T_874; // @[RegisterRouter.scala:87:24] wire out_womask_874 = &_out_womask_T_874; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_874 = out_rivalid_1_728 & out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8559 = out_f_rivalid_874; // @[RegisterRouter.scala:87:24] wire out_f_roready_874 = out_roready_1_728 & out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8560 = out_f_roready_874; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_874 = out_wivalid_1_728 & out_wimask_874; // @[RegisterRouter.scala:87:24] wire out_f_woready_874 = out_woready_1_728 & out_womask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8561 = ~out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8562 = ~out_wimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8563 = ~out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8564 = ~out_womask_874; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_745 = {hi_566, flags_0_go, _out_prepend_T_745}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8565 = out_prepend_745; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8566 = _out_T_8565; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_746 = _out_T_8566; // @[RegisterRouter.scala:87:24] wire out_rimask_875 = \|_out_rimask_T_875; // @[RegisterRouter.scala:87:24] wire out_wimask_875 = &_out_wimask_T_875; // @[RegisterRouter.scala:87:24] wire out_romask_875 = \|_out_romask_T_875; // @[RegisterRouter.scala:87:24] wire out_womask_875 = &_out_womask_T_875; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_875 = out_rivalid_1_729 & out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8568 = out_f_rivalid_875; // @[RegisterRouter.scala:87:24] wire out_f_roready_875 = out_roready_1_729 & out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8569 = out_f_roready_875; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_875 = out_wivalid_1_729 & out_wimask_875; // @[RegisterRouter.scala:87:24] wire out_f_woready_875 = out_woready_1_729 & out_womask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8570 = ~out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8571 = ~out_wimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8572 = ~out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8573 = ~out_womask_875; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_746 = {hi_567, flags_0_go, _out_prepend_T_746}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8574 = out_prepend_746; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8575 = _out_T_8574; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_747 = _out_T_8575; // @[RegisterRouter.scala:87:24] wire out_rimask_876 = \|_out_rimask_T_876; // @[RegisterRouter.scala:87:24] wire out_wimask_876 = &_out_wimask_T_876; // @[RegisterRouter.scala:87:24] wire out_romask_876 = \|_out_romask_T_876; // @[RegisterRouter.scala:87:24] wire out_womask_876 = &_out_womask_T_876; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_876 = out_rivalid_1_730 & out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8577 = out_f_rivalid_876; // @[RegisterRouter.scala:87:24] wire out_f_roready_876 = out_roready_1_730 & out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8578 = out_f_roready_876; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_876 = out_wivalid_1_730 & out_wimask_876; // @[RegisterRouter.scala:87:24] wire out_f_woready_876 = out_woready_1_730 & out_womask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8579 = ~out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8580 = ~out_wimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8581 = ~out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8582 = ~out_womask_876; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_747 = {hi_568, flags_0_go, _out_prepend_T_747}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8583 = out_prepend_747; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8584 = _out_T_8583; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_198 = _out_T_8584; // @[MuxLiteral.scala:49:48] wire out_rimask_877 = \|_out_rimask_T_877; // @[RegisterRouter.scala:87:24] wire out_wimask_877 = &_out_wimask_T_877; // @[RegisterRouter.scala:87:24] wire out_romask_877 = \|_out_romask_T_877; // @[RegisterRouter.scala:87:24] wire out_womask_877 = &_out_womask_T_877; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_877 = out_rivalid_1_731 & out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8586 = out_f_rivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_roready_877 = out_roready_1_731 & out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8587 = out_f_roready_877; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_877 = out_wivalid_1_731 & out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8588 = out_f_wivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_woready_877 = out_woready_1_731 & out_womask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8589 = out_f_woready_877; // @[RegisterRouter.scala:87:24] wire _out_T_8590 = ~out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8591 = ~out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8592 = ~out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8593 = ~out_womask_877; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8595 = _out_T_8594; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_748 = _out_T_8595; // @[RegisterRouter.scala:87:24] wire out_rimask_878 = \|_out_rimask_T_878; // @[RegisterRouter.scala:87:24] wire out_wimask_878 = &_out_wimask_T_878; // @[RegisterRouter.scala:87:24] wire out_romask_878 = \|_out_romask_T_878; // @[RegisterRouter.scala:87:24] wire out_womask_878 = &_out_womask_T_878; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_878 = out_rivalid_1_732 & out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8597 = out_f_rivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_roready_878 = out_roready_1_732 & out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8598 = out_f_roready_878; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_878 = out_wivalid_1_732 & out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8599 = out_f_wivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_woready_878 = out_woready_1_732 & out_womask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8600 = out_f_woready_878; // @[RegisterRouter.scala:87:24] wire _out_T_8601 = ~out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8602 = ~out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8603 = ~out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8604 = ~out_womask_878; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_748 = {programBufferMem_33, _out_prepend_T_748}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8605 = out_prepend_748; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8606 = _out_T_8605; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_749 = _out_T_8606; // @[RegisterRouter.scala:87:24] wire out_rimask_879 = \|_out_rimask_T_879; // @[RegisterRouter.scala:87:24] wire out_wimask_879 = &_out_wimask_T_879; // @[RegisterRouter.scala:87:24] wire out_romask_879 = \|_out_romask_T_879; // @[RegisterRouter.scala:87:24] wire out_womask_879 = &_out_womask_T_879; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_879 = out_rivalid_1_733 & out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8608 = out_f_rivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_roready_879 = out_roready_1_733 & out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8609 = out_f_roready_879; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_879 = out_wivalid_1_733 & out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8610 = out_f_wivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_woready_879 = out_woready_1_733 & out_womask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8611 = out_f_woready_879; // @[RegisterRouter.scala:87:24] wire _out_T_8612 = ~out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8613 = ~out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8614 = ~out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8615 = ~out_womask_879; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_749 = {programBufferMem_34, _out_prepend_T_749}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8616 = out_prepend_749; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8617 = _out_T_8616; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_750 = _out_T_8617; // @[RegisterRouter.scala:87:24] wire out_rimask_880 = \|_out_rimask_T_880; // @[RegisterRouter.scala:87:24] wire out_wimask_880 = &_out_wimask_T_880; // @[RegisterRouter.scala:87:24] wire out_romask_880 = \|_out_romask_T_880; // @[RegisterRouter.scala:87:24] wire out_womask_880 = &_out_womask_T_880; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_880 = out_rivalid_1_734 & out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8619 = out_f_rivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_roready_880 = out_roready_1_734 & out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8620 = out_f_roready_880; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_880 = out_wivalid_1_734 & out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8621 = out_f_wivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_woready_880 = out_woready_1_734 & out_womask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8622 = out_f_woready_880; // @[RegisterRouter.scala:87:24] wire _out_T_8623 = ~out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8624 = ~out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8625 = ~out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8626 = ~out_womask_880; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_750 = {programBufferMem_35, _out_prepend_T_750}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8627 = out_prepend_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8628 = _out_T_8627; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_751 = _out_T_8628; // @[RegisterRouter.scala:87:24] wire out_rimask_881 = \|_out_rimask_T_881; // @[RegisterRouter.scala:87:24] wire out_wimask_881 = &_out_wimask_T_881; // @[RegisterRouter.scala:87:24] wire out_romask_881 = \|_out_romask_T_881; // @[RegisterRouter.scala:87:24] wire out_womask_881 = &_out_womask_T_881; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_881 = out_rivalid_1_735 & out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8630 = out_f_rivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_roready_881 = out_roready_1_735 & out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8631 = out_f_roready_881; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_881 = out_wivalid_1_735 & out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8632 = out_f_wivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_woready_881 = out_woready_1_735 & out_womask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8633 = out_f_woready_881; // @[RegisterRouter.scala:87:24] wire _out_T_8634 = ~out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8635 = ~out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8636 = ~out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8637 = ~out_womask_881; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_751 = {programBufferMem_36, _out_prepend_T_751}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8638 = out_prepend_751; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8639 = _out_T_8638; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_752 = _out_T_8639; // @[RegisterRouter.scala:87:24] wire out_rimask_882 = \|_out_rimask_T_882; // @[RegisterRouter.scala:87:24] wire out_wimask_882 = &_out_wimask_T_882; // @[RegisterRouter.scala:87:24] wire out_romask_882 = \|_out_romask_T_882; // @[RegisterRouter.scala:87:24] wire out_womask_882 = &_out_womask_T_882; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_882 = out_rivalid_1_736 & out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8641 = out_f_rivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_roready_882 = out_roready_1_736 & out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8642 = out_f_roready_882; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_882 = out_wivalid_1_736 & out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8643 = out_f_wivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_woready_882 = out_woready_1_736 & out_womask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8644 = out_f_woready_882; // @[RegisterRouter.scala:87:24] wire _out_T_8645 = ~out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8646 = ~out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8647 = ~out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8648 = ~out_womask_882; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_752 = {programBufferMem_37, _out_prepend_T_752}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8649 = out_prepend_752; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8650 = _out_T_8649; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_753 = _out_T_8650; // @[RegisterRouter.scala:87:24] wire out_rimask_883 = \|_out_rimask_T_883; // @[RegisterRouter.scala:87:24] wire out_wimask_883 = &_out_wimask_T_883; // @[RegisterRouter.scala:87:24] wire out_romask_883 = \|_out_romask_T_883; // @[RegisterRouter.scala:87:24] wire out_womask_883 = &_out_womask_T_883; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_883 = out_rivalid_1_737 & out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8652 = out_f_rivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_roready_883 = out_roready_1_737 & out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8653 = out_f_roready_883; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_883 = out_wivalid_1_737 & out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8654 = out_f_wivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_woready_883 = out_woready_1_737 & out_womask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8655 = out_f_woready_883; // @[RegisterRouter.scala:87:24] wire _out_T_8656 = ~out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8657 = ~out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8658 = ~out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8659 = ~out_womask_883; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_753 = {programBufferMem_38, _out_prepend_T_753}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8660 = out_prepend_753; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8661 = _out_T_8660; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_754 = _out_T_8661; // @[RegisterRouter.scala:87:24] wire out_rimask_884 = \|_out_rimask_T_884; // @[RegisterRouter.scala:87:24] wire out_wimask_884 = &_out_wimask_T_884; // @[RegisterRouter.scala:87:24] wire out_romask_884 = \|_out_romask_T_884; // @[RegisterRouter.scala:87:24] wire out_womask_884 = &_out_womask_T_884; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_884 = out_rivalid_1_738 & out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8663 = out_f_rivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_roready_884 = out_roready_1_738 & out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8664 = out_f_roready_884; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_884 = out_wivalid_1_738 & out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8665 = out_f_wivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_woready_884 = out_woready_1_738 & out_womask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8666 = out_f_woready_884; // @[RegisterRouter.scala:87:24] wire _out_T_8667 = ~out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8668 = ~out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8669 = ~out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8670 = ~out_womask_884; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_754 = {programBufferMem_39, _out_prepend_T_754}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8671 = out_prepend_754; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8672 = _out_T_8671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_108 = _out_T_8672; // @[MuxLiteral.scala:49:48] wire out_rimask_885 = \|_out_rimask_T_885; // @[RegisterRouter.scala:87:24] wire out_wimask_885 = &_out_wimask_T_885; // @[RegisterRouter.scala:87:24] wire out_romask_885 = \|_out_romask_T_885; // @[RegisterRouter.scala:87:24] wire out_womask_885 = &_out_womask_T_885; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_885 = out_rivalid_1_739 & out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8674 = out_f_rivalid_885; // @[RegisterRouter.scala:87:24] wire out_f_roready_885 = out_roready_1_739 & out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8675 = out_f_roready_885; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_885 = out_wivalid_1_739 & out_wimask_885; // @[RegisterRouter.scala:87:24] wire out_f_woready_885 = out_woready_1_739 & out_womask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8676 = ~out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8677 = ~out_wimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8678 = ~out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8679 = ~out_womask_885; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8681 = _out_T_8680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_755 = _out_T_8681; // @[RegisterRouter.scala:87:24] wire out_rimask_886 = \|_out_rimask_T_886; // @[RegisterRouter.scala:87:24] wire out_wimask_886 = &_out_wimask_T_886; // @[RegisterRouter.scala:87:24] wire out_romask_886 = \|_out_romask_T_886; // @[RegisterRouter.scala:87:24] wire out_womask_886 = &_out_womask_T_886; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_886 = out_rivalid_1_740 & out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8683 = out_f_rivalid_886; // @[RegisterRouter.scala:87:24] wire out_f_roready_886 = out_roready_1_740 & out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8684 = out_f_roready_886; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_886 = out_wivalid_1_740 & out_wimask_886; // @[RegisterRouter.scala:87:24] wire out_f_woready_886 = out_woready_1_740 & out_womask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8685 = ~out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8686 = ~out_wimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8687 = ~out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8688 = ~out_womask_886; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_755 = {hi_898, flags_0_go, _out_prepend_T_755}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8689 = out_prepend_755; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8690 = _out_T_8689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_756 = _out_T_8690; // @[RegisterRouter.scala:87:24] wire out_rimask_887 = \|_out_rimask_T_887; // @[RegisterRouter.scala:87:24] wire out_wimask_887 = &_out_wimask_T_887; // @[RegisterRouter.scala:87:24] wire out_romask_887 = \|_out_romask_T_887; // @[RegisterRouter.scala:87:24] wire out_womask_887 = &_out_womask_T_887; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_887 = out_rivalid_1_741 & out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8692 = out_f_rivalid_887; // @[RegisterRouter.scala:87:24] wire out_f_roready_887 = out_roready_1_741 & out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8693 = out_f_roready_887; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_887 = out_wivalid_1_741 & out_wimask_887; // @[RegisterRouter.scala:87:24] wire out_f_woready_887 = out_woready_1_741 & out_womask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8694 = ~out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8695 = ~out_wimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8696 = ~out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8697 = ~out_womask_887; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_756 = {hi_899, flags_0_go, _out_prepend_T_756}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8698 = out_prepend_756; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8699 = _out_T_8698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_757 = _out_T_8699; // @[RegisterRouter.scala:87:24] wire out_rimask_888 = \|_out_rimask_T_888; // @[RegisterRouter.scala:87:24] wire out_wimask_888 = &_out_wimask_T_888; // @[RegisterRouter.scala:87:24] wire out_romask_888 = \|_out_romask_T_888; // @[RegisterRouter.scala:87:24] wire out_womask_888 = &_out_womask_T_888; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_888 = out_rivalid_1_742 & out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8701 = out_f_rivalid_888; // @[RegisterRouter.scala:87:24] wire out_f_roready_888 = out_roready_1_742 & out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8702 = out_f_roready_888; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_888 = out_wivalid_1_742 & out_wimask_888; // @[RegisterRouter.scala:87:24] wire out_f_woready_888 = out_woready_1_742 & out_womask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8703 = ~out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8704 = ~out_wimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8705 = ~out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8706 = ~out_womask_888; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_757 = {hi_900, flags_0_go, _out_prepend_T_757}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8707 = out_prepend_757; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8708 = _out_T_8707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_758 = _out_T_8708; // @[RegisterRouter.scala:87:24] wire out_rimask_889 = \|_out_rimask_T_889; // @[RegisterRouter.scala:87:24] wire out_wimask_889 = &_out_wimask_T_889; // @[RegisterRouter.scala:87:24] wire out_romask_889 = \|_out_romask_T_889; // @[RegisterRouter.scala:87:24] wire out_womask_889 = &_out_womask_T_889; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_889 = out_rivalid_1_743 & out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8710 = out_f_rivalid_889; // @[RegisterRouter.scala:87:24] wire out_f_roready_889 = out_roready_1_743 & out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8711 = out_f_roready_889; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_889 = out_wivalid_1_743 & out_wimask_889; // @[RegisterRouter.scala:87:24] wire out_f_woready_889 = out_woready_1_743 & out_womask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8712 = ~out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8713 = ~out_wimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8714 = ~out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8715 = ~out_womask_889; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_758 = {hi_901, flags_0_go, _out_prepend_T_758}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8716 = out_prepend_758; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8717 = _out_T_8716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_759 = _out_T_8717; // @[RegisterRouter.scala:87:24] wire out_rimask_890 = \|_out_rimask_T_890; // @[RegisterRouter.scala:87:24] wire out_wimask_890 = &_out_wimask_T_890; // @[RegisterRouter.scala:87:24] wire out_romask_890 = \|_out_romask_T_890; // @[RegisterRouter.scala:87:24] wire out_womask_890 = &_out_womask_T_890; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_890 = out_rivalid_1_744 & out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8719 = out_f_rivalid_890; // @[RegisterRouter.scala:87:24] wire out_f_roready_890 = out_roready_1_744 & out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8720 = out_f_roready_890; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_890 = out_wivalid_1_744 & out_wimask_890; // @[RegisterRouter.scala:87:24] wire out_f_woready_890 = out_woready_1_744 & out_womask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8721 = ~out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8722 = ~out_wimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8723 = ~out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8724 = ~out_womask_890; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_759 = {hi_902, flags_0_go, _out_prepend_T_759}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8725 = out_prepend_759; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8726 = _out_T_8725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_760 = _out_T_8726; // @[RegisterRouter.scala:87:24] wire out_rimask_891 = \|_out_rimask_T_891; // @[RegisterRouter.scala:87:24] wire out_wimask_891 = &_out_wimask_T_891; // @[RegisterRouter.scala:87:24] wire out_romask_891 = \|_out_romask_T_891; // @[RegisterRouter.scala:87:24] wire out_womask_891 = &_out_womask_T_891; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_891 = out_rivalid_1_745 & out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8728 = out_f_rivalid_891; // @[RegisterRouter.scala:87:24] wire out_f_roready_891 = out_roready_1_745 & out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8729 = out_f_roready_891; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_891 = out_wivalid_1_745 & out_wimask_891; // @[RegisterRouter.scala:87:24] wire out_f_woready_891 = out_woready_1_745 & out_womask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8730 = ~out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8731 = ~out_wimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8732 = ~out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8733 = ~out_womask_891; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_760 = {hi_903, flags_0_go, _out_prepend_T_760}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8734 = out_prepend_760; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8735 = _out_T_8734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_761 = _out_T_8735; // @[RegisterRouter.scala:87:24] wire out_rimask_892 = \|_out_rimask_T_892; // @[RegisterRouter.scala:87:24] wire out_wimask_892 = &_out_wimask_T_892; // @[RegisterRouter.scala:87:24] wire out_romask_892 = \|_out_romask_T_892; // @[RegisterRouter.scala:87:24] wire out_womask_892 = &_out_womask_T_892; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_892 = out_rivalid_1_746 & out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8737 = out_f_rivalid_892; // @[RegisterRouter.scala:87:24] wire out_f_roready_892 = out_roready_1_746 & out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8738 = out_f_roready_892; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_892 = out_wivalid_1_746 & out_wimask_892; // @[RegisterRouter.scala:87:24] wire out_f_woready_892 = out_woready_1_746 & out_womask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8739 = ~out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8740 = ~out_wimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8741 = ~out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8742 = ~out_womask_892; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_761 = {hi_904, flags_0_go, _out_prepend_T_761}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8743 = out_prepend_761; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8744 = _out_T_8743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_240 = _out_T_8744; // @[MuxLiteral.scala:49:48] wire out_rimask_893 = \|_out_rimask_T_893; // @[RegisterRouter.scala:87:24] wire out_wimask_893 = &_out_wimask_T_893; // @[RegisterRouter.scala:87:24] wire out_romask_893 = \|_out_romask_T_893; // @[RegisterRouter.scala:87:24] wire out_womask_893 = &_out_womask_T_893; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_893 = out_rivalid_1_747 & out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8746 = out_f_rivalid_893; // @[RegisterRouter.scala:87:24] wire out_f_roready_893 = out_roready_1_747 & out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8747 = out_f_roready_893; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_893 = out_wivalid_1_747 & out_wimask_893; // @[RegisterRouter.scala:87:24] wire out_f_woready_893 = out_woready_1_747 & out_womask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8748 = ~out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8749 = ~out_wimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8750 = ~out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8751 = ~out_womask_893; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8753 = _out_T_8752; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_762 = _out_T_8753; // @[RegisterRouter.scala:87:24] wire out_rimask_894 = \|_out_rimask_T_894; // @[RegisterRouter.scala:87:24] wire out_wimask_894 = &_out_wimask_T_894; // @[RegisterRouter.scala:87:24] wire out_romask_894 = \|_out_romask_T_894; // @[RegisterRouter.scala:87:24] wire out_womask_894 = &_out_womask_T_894; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_894 = out_rivalid_1_748 & out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8755 = out_f_rivalid_894; // @[RegisterRouter.scala:87:24] wire out_f_roready_894 = out_roready_1_748 & out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8756 = out_f_roready_894; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_894 = out_wivalid_1_748 & out_wimask_894; // @[RegisterRouter.scala:87:24] wire out_f_woready_894 = out_woready_1_748 & out_womask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8757 = ~out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8758 = ~out_wimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8759 = ~out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8760 = ~out_womask_894; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_762 = {hi_986, flags_0_go, _out_prepend_T_762}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8761 = out_prepend_762; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8762 = _out_T_8761; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_763 = _out_T_8762; // @[RegisterRouter.scala:87:24] wire out_rimask_895 = \|_out_rimask_T_895; // @[RegisterRouter.scala:87:24] wire out_wimask_895 = &_out_wimask_T_895; // @[RegisterRouter.scala:87:24] wire out_romask_895 = \|_out_romask_T_895; // @[RegisterRouter.scala:87:24] wire out_womask_895 = &_out_womask_T_895; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_895 = out_rivalid_1_749 & out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8764 = out_f_rivalid_895; // @[RegisterRouter.scala:87:24] wire out_f_roready_895 = out_roready_1_749 & out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8765 = out_f_roready_895; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_895 = out_wivalid_1_749 & out_wimask_895; // @[RegisterRouter.scala:87:24] wire out_f_woready_895 = out_woready_1_749 & out_womask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8766 = ~out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8767 = ~out_wimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8768 = ~out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8769 = ~out_womask_895; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_763 = {hi_987, flags_0_go, _out_prepend_T_763}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8770 = out_prepend_763; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8771 = _out_T_8770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_764 = _out_T_8771; // @[RegisterRouter.scala:87:24] wire out_rimask_896 = \|_out_rimask_T_896; // @[RegisterRouter.scala:87:24] wire out_wimask_896 = &_out_wimask_T_896; // @[RegisterRouter.scala:87:24] wire out_romask_896 = \|_out_romask_T_896; // @[RegisterRouter.scala:87:24] wire out_womask_896 = &_out_womask_T_896; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_896 = out_rivalid_1_750 & out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8773 = out_f_rivalid_896; // @[RegisterRouter.scala:87:24] wire out_f_roready_896 = out_roready_1_750 & out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8774 = out_f_roready_896; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_896 = out_wivalid_1_750 & out_wimask_896; // @[RegisterRouter.scala:87:24] wire out_f_woready_896 = out_woready_1_750 & out_womask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8775 = ~out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8776 = ~out_wimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8777 = ~out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8778 = ~out_womask_896; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_764 = {hi_988, flags_0_go, _out_prepend_T_764}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8779 = out_prepend_764; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8780 = _out_T_8779; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_765 = _out_T_8780; // @[RegisterRouter.scala:87:24] wire out_rimask_897 = \|_out_rimask_T_897; // @[RegisterRouter.scala:87:24] wire out_wimask_897 = &_out_wimask_T_897; // @[RegisterRouter.scala:87:24] wire out_romask_897 = \|_out_romask_T_897; // @[RegisterRouter.scala:87:24] wire out_womask_897 = &_out_womask_T_897; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_897 = out_rivalid_1_751 & out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8782 = out_f_rivalid_897; // @[RegisterRouter.scala:87:24] wire out_f_roready_897 = out_roready_1_751 & out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8783 = out_f_roready_897; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_897 = out_wivalid_1_751 & out_wimask_897; // @[RegisterRouter.scala:87:24] wire out_f_woready_897 = out_woready_1_751 & out_womask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8784 = ~out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8785 = ~out_wimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8786 = ~out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8787 = ~out_womask_897; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_765 = {hi_989, flags_0_go, _out_prepend_T_765}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8788 = out_prepend_765; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8789 = _out_T_8788; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_766 = _out_T_8789; // @[RegisterRouter.scala:87:24] wire out_rimask_898 = \|_out_rimask_T_898; // @[RegisterRouter.scala:87:24] wire out_wimask_898 = &_out_wimask_T_898; // @[RegisterRouter.scala:87:24] wire out_romask_898 = \|_out_romask_T_898; // @[RegisterRouter.scala:87:24] wire out_womask_898 = &_out_womask_T_898; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_898 = out_rivalid_1_752 & out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8791 = out_f_rivalid_898; // @[RegisterRouter.scala:87:24] wire out_f_roready_898 = out_roready_1_752 & out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8792 = out_f_roready_898; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_898 = out_wivalid_1_752 & out_wimask_898; // @[RegisterRouter.scala:87:24] wire out_f_woready_898 = out_woready_1_752 & out_womask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8793 = ~out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8794 = ~out_wimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8795 = ~out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8796 = ~out_womask_898; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_766 = {hi_990, flags_0_go, _out_prepend_T_766}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8797 = out_prepend_766; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8798 = _out_T_8797; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_767 = _out_T_8798; // @[RegisterRouter.scala:87:24] wire out_rimask_899 = \|_out_rimask_T_899; // @[RegisterRouter.scala:87:24] wire out_wimask_899 = &_out_wimask_T_899; // @[RegisterRouter.scala:87:24] wire out_romask_899 = \|_out_romask_T_899; // @[RegisterRouter.scala:87:24] wire out_womask_899 = &_out_womask_T_899; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_899 = out_rivalid_1_753 & out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8800 = out_f_rivalid_899; // @[RegisterRouter.scala:87:24] wire out_f_roready_899 = out_roready_1_753 & out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8801 = out_f_roready_899; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_899 = out_wivalid_1_753 & out_wimask_899; // @[RegisterRouter.scala:87:24] wire out_f_woready_899 = out_woready_1_753 & out_womask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8802 = ~out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8803 = ~out_wimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8804 = ~out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8805 = ~out_womask_899; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_767 = {hi_991, flags_0_go, _out_prepend_T_767}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8806 = out_prepend_767; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8807 = _out_T_8806; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_768 = _out_T_8807; // @[RegisterRouter.scala:87:24] wire out_rimask_900 = \|_out_rimask_T_900; // @[RegisterRouter.scala:87:24] wire out_wimask_900 = &_out_wimask_T_900; // @[RegisterRouter.scala:87:24] wire out_romask_900 = \|_out_romask_T_900; // @[RegisterRouter.scala:87:24] wire out_womask_900 = &_out_womask_T_900; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_900 = out_rivalid_1_754 & out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8809 = out_f_rivalid_900; // @[RegisterRouter.scala:87:24] wire out_f_roready_900 = out_roready_1_754 & out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8810 = out_f_roready_900; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_900 = out_wivalid_1_754 & out_wimask_900; // @[RegisterRouter.scala:87:24] wire out_f_woready_900 = out_woready_1_754 & out_womask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8811 = ~out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8812 = ~out_wimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8813 = ~out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8814 = ~out_womask_900; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_768 = {hi_992, flags_0_go, _out_prepend_T_768}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8815 = out_prepend_768; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8816 = _out_T_8815; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_251 = _out_T_8816; // @[MuxLiteral.scala:49:48] wire out_rimask_901 = \|_out_rimask_T_901; // @[RegisterRouter.scala:87:24] wire out_wimask_901 = &_out_wimask_T_901; // @[RegisterRouter.scala:87:24] wire out_romask_901 = \|_out_romask_T_901; // @[RegisterRouter.scala:87:24] wire out_womask_901 = &_out_womask_T_901; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_901 = out_rivalid_1_755 & out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8818 = out_f_rivalid_901; // @[RegisterRouter.scala:87:24] wire out_f_roready_901 = out_roready_1_755 & out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8819 = out_f_roready_901; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_901 = out_wivalid_1_755 & out_wimask_901; // @[RegisterRouter.scala:87:24] wire out_f_woready_901 = out_woready_1_755 & out_womask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8820 = ~out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8821 = ~out_wimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8822 = ~out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8823 = ~out_womask_901; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8825 = _out_T_8824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_769 = _out_T_8825; // @[RegisterRouter.scala:87:24] wire out_rimask_902 = \|_out_rimask_T_902; // @[RegisterRouter.scala:87:24] wire out_wimask_902 = &_out_wimask_T_902; // @[RegisterRouter.scala:87:24] wire out_romask_902 = \|_out_romask_T_902; // @[RegisterRouter.scala:87:24] wire out_womask_902 = &_out_womask_T_902; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_902 = out_rivalid_1_756 & out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8827 = out_f_rivalid_902; // @[RegisterRouter.scala:87:24] wire out_f_roready_902 = out_roready_1_756 & out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8828 = out_f_roready_902; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_902 = out_wivalid_1_756 & out_wimask_902; // @[RegisterRouter.scala:87:24] wire out_f_woready_902 = out_woready_1_756 & out_womask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8829 = ~out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8830 = ~out_wimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8831 = ~out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8832 = ~out_womask_902; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_769 = {hi_18, flags_0_go, _out_prepend_T_769}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8833 = out_prepend_769; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8834 = _out_T_8833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_770 = _out_T_8834; // @[RegisterRouter.scala:87:24] wire out_rimask_903 = \|_out_rimask_T_903; // @[RegisterRouter.scala:87:24] wire out_wimask_903 = &_out_wimask_T_903; // @[RegisterRouter.scala:87:24] wire out_romask_903 = \|_out_romask_T_903; // @[RegisterRouter.scala:87:24] wire out_womask_903 = &_out_womask_T_903; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_903 = out_rivalid_1_757 & out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8836 = out_f_rivalid_903; // @[RegisterRouter.scala:87:24] wire out_f_roready_903 = out_roready_1_757 & out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8837 = out_f_roready_903; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_903 = out_wivalid_1_757 & out_wimask_903; // @[RegisterRouter.scala:87:24] wire out_f_woready_903 = out_woready_1_757 & out_womask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8838 = ~out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8839 = ~out_wimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8840 = ~out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8841 = ~out_womask_903; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_770 = {hi_19, flags_0_go, _out_prepend_T_770}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8842 = out_prepend_770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8843 = _out_T_8842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_771 = _out_T_8843; // @[RegisterRouter.scala:87:24] wire out_rimask_904 = \|_out_rimask_T_904; // @[RegisterRouter.scala:87:24] wire out_wimask_904 = &_out_wimask_T_904; // @[RegisterRouter.scala:87:24] wire out_romask_904 = \|_out_romask_T_904; // @[RegisterRouter.scala:87:24] wire out_womask_904 = &_out_womask_T_904; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_904 = out_rivalid_1_758 & out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8845 = out_f_rivalid_904; // @[RegisterRouter.scala:87:24] wire out_f_roready_904 = out_roready_1_758 & out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8846 = out_f_roready_904; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_904 = out_wivalid_1_758 & out_wimask_904; // @[RegisterRouter.scala:87:24] wire out_f_woready_904 = out_woready_1_758 & out_womask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8847 = ~out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8848 = ~out_wimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8849 = ~out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8850 = ~out_womask_904; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_771 = {hi_20, flags_0_go, _out_prepend_T_771}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8851 = out_prepend_771; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8852 = _out_T_8851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_772 = _out_T_8852; // @[RegisterRouter.scala:87:24] wire out_rimask_905 = \|_out_rimask_T_905; // @[RegisterRouter.scala:87:24] wire out_wimask_905 = &_out_wimask_T_905; // @[RegisterRouter.scala:87:24] wire out_romask_905 = \|_out_romask_T_905; // @[RegisterRouter.scala:87:24] wire out_womask_905 = &_out_womask_T_905; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_905 = out_rivalid_1_759 & out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8854 = out_f_rivalid_905; // @[RegisterRouter.scala:87:24] wire out_f_roready_905 = out_roready_1_759 & out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8855 = out_f_roready_905; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_905 = out_wivalid_1_759 & out_wimask_905; // @[RegisterRouter.scala:87:24] wire out_f_woready_905 = out_woready_1_759 & out_womask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8856 = ~out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8857 = ~out_wimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8858 = ~out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8859 = ~out_womask_905; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_772 = {hi_21, flags_0_go, _out_prepend_T_772}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8860 = out_prepend_772; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8861 = _out_T_8860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_773 = _out_T_8861; // @[RegisterRouter.scala:87:24] wire out_rimask_906 = \|_out_rimask_T_906; // @[RegisterRouter.scala:87:24] wire out_wimask_906 = &_out_wimask_T_906; // @[RegisterRouter.scala:87:24] wire out_romask_906 = \|_out_romask_T_906; // @[RegisterRouter.scala:87:24] wire out_womask_906 = &_out_womask_T_906; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_906 = out_rivalid_1_760 & out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8863 = out_f_rivalid_906; // @[RegisterRouter.scala:87:24] wire out_f_roready_906 = out_roready_1_760 & out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8864 = out_f_roready_906; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_906 = out_wivalid_1_760 & out_wimask_906; // @[RegisterRouter.scala:87:24] wire out_f_woready_906 = out_woready_1_760 & out_womask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8865 = ~out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8866 = ~out_wimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8867 = ~out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8868 = ~out_womask_906; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_773 = {hi_22, flags_0_go, _out_prepend_T_773}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8869 = out_prepend_773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8870 = _out_T_8869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_774 = _out_T_8870; // @[RegisterRouter.scala:87:24] wire out_rimask_907 = \|_out_rimask_T_907; // @[RegisterRouter.scala:87:24] wire out_wimask_907 = &_out_wimask_T_907; // @[RegisterRouter.scala:87:24] wire out_romask_907 = \|_out_romask_T_907; // @[RegisterRouter.scala:87:24] wire out_womask_907 = &_out_womask_T_907; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_907 = out_rivalid_1_761 & out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8872 = out_f_rivalid_907; // @[RegisterRouter.scala:87:24] wire out_f_roready_907 = out_roready_1_761 & out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8873 = out_f_roready_907; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_907 = out_wivalid_1_761 & out_wimask_907; // @[RegisterRouter.scala:87:24] wire out_f_woready_907 = out_woready_1_761 & out_womask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8874 = ~out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8875 = ~out_wimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8876 = ~out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8877 = ~out_womask_907; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_774 = {hi_23, flags_0_go, _out_prepend_T_774}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8878 = out_prepend_774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8879 = _out_T_8878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_775 = _out_T_8879; // @[RegisterRouter.scala:87:24] wire out_rimask_908 = \|_out_rimask_T_908; // @[RegisterRouter.scala:87:24] wire out_wimask_908 = &_out_wimask_T_908; // @[RegisterRouter.scala:87:24] wire out_romask_908 = \|_out_romask_T_908; // @[RegisterRouter.scala:87:24] wire out_womask_908 = &_out_womask_T_908; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_908 = out_rivalid_1_762 & out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8881 = out_f_rivalid_908; // @[RegisterRouter.scala:87:24] wire out_f_roready_908 = out_roready_1_762 & out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8882 = out_f_roready_908; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_908 = out_wivalid_1_762 & out_wimask_908; // @[RegisterRouter.scala:87:24] wire out_f_woready_908 = out_woready_1_762 & out_womask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8883 = ~out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8884 = ~out_wimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8885 = ~out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8886 = ~out_womask_908; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_775 = {hi_24, flags_0_go, _out_prepend_T_775}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8887 = out_prepend_775; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8888 = _out_T_8887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_130 = _out_T_8888; // @[MuxLiteral.scala:49:48] wire out_rimask_909 = \|_out_rimask_T_909; // @[RegisterRouter.scala:87:24] wire out_wimask_909 = &_out_wimask_T_909; // @[RegisterRouter.scala:87:24] wire out_romask_909 = \|_out_romask_T_909; // @[RegisterRouter.scala:87:24] wire out_womask_909 = &_out_womask_T_909; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_909 = out_rivalid_1_763 & out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8890 = out_f_rivalid_909; // @[RegisterRouter.scala:87:24] wire out_f_roready_909 = out_roready_1_763 & out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8891 = out_f_roready_909; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_909 = out_wivalid_1_763 & out_wimask_909; // @[RegisterRouter.scala:87:24] wire out_f_woready_909 = out_woready_1_763 & out_womask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8892 = ~out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8893 = ~out_wimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8894 = ~out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8895 = ~out_womask_909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8897 = _out_T_8896; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_776 = _out_T_8897; // @[RegisterRouter.scala:87:24] wire out_rimask_910 = \|_out_rimask_T_910; // @[RegisterRouter.scala:87:24] wire out_wimask_910 = &_out_wimask_T_910; // @[RegisterRouter.scala:87:24] wire out_romask_910 = \|_out_romask_T_910; // @[RegisterRouter.scala:87:24] wire out_womask_910 = &_out_womask_T_910; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_910 = out_rivalid_1_764 & out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8899 = out_f_rivalid_910; // @[RegisterRouter.scala:87:24] wire out_f_roready_910 = out_roready_1_764 & out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8900 = out_f_roready_910; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_910 = out_wivalid_1_764 & out_wimask_910; // @[RegisterRouter.scala:87:24] wire out_f_woready_910 = out_woready_1_764 & out_womask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8901 = ~out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8902 = ~out_wimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8903 = ~out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8904 = ~out_womask_910; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_776 = {hi_762, flags_0_go, _out_prepend_T_776}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8905 = out_prepend_776; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8906 = _out_T_8905; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_777 = _out_T_8906; // @[RegisterRouter.scala:87:24] wire out_rimask_911 = \|_out_rimask_T_911; // @[RegisterRouter.scala:87:24] wire out_wimask_911 = &_out_wimask_T_911; // @[RegisterRouter.scala:87:24] wire out_romask_911 = \|_out_romask_T_911; // @[RegisterRouter.scala:87:24] wire out_womask_911 = &_out_womask_T_911; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_911 = out_rivalid_1_765 & out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8908 = out_f_rivalid_911; // @[RegisterRouter.scala:87:24] wire out_f_roready_911 = out_roready_1_765 & out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8909 = out_f_roready_911; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_911 = out_wivalid_1_765 & out_wimask_911; // @[RegisterRouter.scala:87:24] wire out_f_woready_911 = out_woready_1_765 & out_womask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8910 = ~out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8911 = ~out_wimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8912 = ~out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8913 = ~out_womask_911; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_777 = {hi_763, flags_0_go, _out_prepend_T_777}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8914 = out_prepend_777; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8915 = _out_T_8914; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_778 = _out_T_8915; // @[RegisterRouter.scala:87:24] wire out_rimask_912 = \|_out_rimask_T_912; // @[RegisterRouter.scala:87:24] wire out_wimask_912 = &_out_wimask_T_912; // @[RegisterRouter.scala:87:24] wire out_romask_912 = \|_out_romask_T_912; // @[RegisterRouter.scala:87:24] wire out_womask_912 = &_out_womask_T_912; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_912 = out_rivalid_1_766 & out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8917 = out_f_rivalid_912; // @[RegisterRouter.scala:87:24] wire out_f_roready_912 = out_roready_1_766 & out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8918 = out_f_roready_912; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_912 = out_wivalid_1_766 & out_wimask_912; // @[RegisterRouter.scala:87:24] wire out_f_woready_912 = out_woready_1_766 & out_womask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8919 = ~out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8920 = ~out_wimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8921 = ~out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8922 = ~out_womask_912; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_778 = {hi_764, flags_0_go, _out_prepend_T_778}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8923 = out_prepend_778; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8924 = _out_T_8923; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_779 = _out_T_8924; // @[RegisterRouter.scala:87:24] wire out_rimask_913 = \|_out_rimask_T_913; // @[RegisterRouter.scala:87:24] wire out_wimask_913 = &_out_wimask_T_913; // @[RegisterRouter.scala:87:24] wire out_romask_913 = \|_out_romask_T_913; // @[RegisterRouter.scala:87:24] wire out_womask_913 = &_out_womask_T_913; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_913 = out_rivalid_1_767 & out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8926 = out_f_rivalid_913; // @[RegisterRouter.scala:87:24] wire out_f_roready_913 = out_roready_1_767 & out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8927 = out_f_roready_913; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_913 = out_wivalid_1_767 & out_wimask_913; // @[RegisterRouter.scala:87:24] wire out_f_woready_913 = out_woready_1_767 & out_womask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8928 = ~out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8929 = ~out_wimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8930 = ~out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8931 = ~out_womask_913; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_779 = {hi_765, flags_0_go, _out_prepend_T_779}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8932 = out_prepend_779; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8933 = _out_T_8932; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_780 = _out_T_8933; // @[RegisterRouter.scala:87:24] wire out_rimask_914 = \|_out_rimask_T_914; // @[RegisterRouter.scala:87:24] wire out_wimask_914 = &_out_wimask_T_914; // @[RegisterRouter.scala:87:24] wire out_romask_914 = \|_out_romask_T_914; // @[RegisterRouter.scala:87:24] wire out_womask_914 = &_out_womask_T_914; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_914 = out_rivalid_1_768 & out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8935 = out_f_rivalid_914; // @[RegisterRouter.scala:87:24] wire out_f_roready_914 = out_roready_1_768 & out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8936 = out_f_roready_914; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_914 = out_wivalid_1_768 & out_wimask_914; // @[RegisterRouter.scala:87:24] wire out_f_woready_914 = out_woready_1_768 & out_womask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8937 = ~out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8938 = ~out_wimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8939 = ~out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8940 = ~out_womask_914; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_780 = {hi_766, flags_0_go, _out_prepend_T_780}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8941 = out_prepend_780; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8942 = _out_T_8941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_781 = _out_T_8942; // @[RegisterRouter.scala:87:24] wire out_rimask_915 = \|_out_rimask_T_915; // @[RegisterRouter.scala:87:24] wire out_wimask_915 = &_out_wimask_T_915; // @[RegisterRouter.scala:87:24] wire out_romask_915 = \|_out_romask_T_915; // @[RegisterRouter.scala:87:24] wire out_womask_915 = &_out_womask_T_915; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_915 = out_rivalid_1_769 & out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8944 = out_f_rivalid_915; // @[RegisterRouter.scala:87:24] wire out_f_roready_915 = out_roready_1_769 & out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8945 = out_f_roready_915; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_915 = out_wivalid_1_769 & out_wimask_915; // @[RegisterRouter.scala:87:24] wire out_f_woready_915 = out_woready_1_769 & out_womask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8946 = ~out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8947 = ~out_wimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8948 = ~out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8949 = ~out_womask_915; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_781 = {hi_767, flags_0_go, _out_prepend_T_781}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8950 = out_prepend_781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8951 = _out_T_8950; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_782 = _out_T_8951; // @[RegisterRouter.scala:87:24] wire out_rimask_916 = \|_out_rimask_T_916; // @[RegisterRouter.scala:87:24] wire out_wimask_916 = &_out_wimask_T_916; // @[RegisterRouter.scala:87:24] wire out_romask_916 = \|_out_romask_T_916; // @[RegisterRouter.scala:87:24] wire out_womask_916 = &_out_womask_T_916; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_916 = out_rivalid_1_770 & out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8953 = out_f_rivalid_916; // @[RegisterRouter.scala:87:24] wire out_f_roready_916 = out_roready_1_770 & out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8954 = out_f_roready_916; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_916 = out_wivalid_1_770 & out_wimask_916; // @[RegisterRouter.scala:87:24] wire out_f_woready_916 = out_woready_1_770 & out_womask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8955 = ~out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8956 = ~out_wimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8957 = ~out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8958 = ~out_womask_916; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_782 = {hi_768, flags_0_go, _out_prepend_T_782}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8959 = out_prepend_782; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8960 = _out_T_8959; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_223 = _out_T_8960; // @[MuxLiteral.scala:49:48] wire out_rimask_917 = \|_out_rimask_T_917; // @[RegisterRouter.scala:87:24] wire out_wimask_917 = &_out_wimask_T_917; // @[RegisterRouter.scala:87:24] wire out_romask_917 = \|_out_romask_T_917; // @[RegisterRouter.scala:87:24] wire out_womask_917 = &_out_womask_T_917; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_917 = out_rivalid_1_771 & out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8962 = out_f_rivalid_917; // @[RegisterRouter.scala:87:24] wire out_f_roready_917 = out_roready_1_771 & out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8963 = out_f_roready_917; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_917 = out_wivalid_1_771 & out_wimask_917; // @[RegisterRouter.scala:87:24] wire out_f_woready_917 = out_woready_1_771 & out_womask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8964 = ~out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8965 = ~out_wimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8966 = ~out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8967 = ~out_womask_917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8969 = _out_T_8968; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_783 = _out_T_8969; // @[RegisterRouter.scala:87:24] wire out_rimask_918 = \|_out_rimask_T_918; // @[RegisterRouter.scala:87:24] wire out_wimask_918 = &_out_wimask_T_918; // @[RegisterRouter.scala:87:24] wire out_romask_918 = \|_out_romask_T_918; // @[RegisterRouter.scala:87:24] wire out_womask_918 = &_out_womask_T_918; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_918 = out_rivalid_1_772 & out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8971 = out_f_rivalid_918; // @[RegisterRouter.scala:87:24] wire out_f_roready_918 = out_roready_1_772 & out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8972 = out_f_roready_918; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_918 = out_wivalid_1_772 & out_wimask_918; // @[RegisterRouter.scala:87:24] wire out_f_woready_918 = out_woready_1_772 & out_womask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8973 = ~out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8974 = ~out_wimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8975 = ~out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8976 = ~out_womask_918; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_783 = {hi_58, flags_0_go, _out_prepend_T_783}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8977 = out_prepend_783; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8978 = _out_T_8977; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_784 = _out_T_8978; // @[RegisterRouter.scala:87:24] wire out_rimask_919 = \|_out_rimask_T_919; // @[RegisterRouter.scala:87:24] wire out_wimask_919 = &_out_wimask_T_919; // @[RegisterRouter.scala:87:24] wire out_romask_919 = \|_out_romask_T_919; // @[RegisterRouter.scala:87:24] wire out_womask_919 = &_out_womask_T_919; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_919 = out_rivalid_1_773 & out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8980 = out_f_rivalid_919; // @[RegisterRouter.scala:87:24] wire out_f_roready_919 = out_roready_1_773 & out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8981 = out_f_roready_919; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_919 = out_wivalid_1_773 & out_wimask_919; // @[RegisterRouter.scala:87:24] wire out_f_woready_919 = out_woready_1_773 & out_womask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8982 = ~out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8983 = ~out_wimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8984 = ~out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8985 = ~out_womask_919; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_784 = {hi_59, flags_0_go, _out_prepend_T_784}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8986 = out_prepend_784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8987 = _out_T_8986; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_785 = _out_T_8987; // @[RegisterRouter.scala:87:24] wire out_rimask_920 = \|_out_rimask_T_920; // @[RegisterRouter.scala:87:24] wire out_wimask_920 = &_out_wimask_T_920; // @[RegisterRouter.scala:87:24] wire out_romask_920 = \|_out_romask_T_920; // @[RegisterRouter.scala:87:24] wire out_womask_920 = &_out_womask_T_920; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_920 = out_rivalid_1_774 & out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8989 = out_f_rivalid_920; // @[RegisterRouter.scala:87:24] wire out_f_roready_920 = out_roready_1_774 & out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8990 = out_f_roready_920; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_920 = out_wivalid_1_774 & out_wimask_920; // @[RegisterRouter.scala:87:24] wire out_f_woready_920 = out_woready_1_774 & out_womask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8991 = ~out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8992 = ~out_wimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8993 = ~out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8994 = ~out_womask_920; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_785 = {hi_60, flags_0_go, _out_prepend_T_785}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8995 = out_prepend_785; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8996 = _out_T_8995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_786 = _out_T_8996; // @[RegisterRouter.scala:87:24] wire out_rimask_921 = \|_out_rimask_T_921; // @[RegisterRouter.scala:87:24] wire out_wimask_921 = &_out_wimask_T_921; // @[RegisterRouter.scala:87:24] wire out_romask_921 = \|_out_romask_T_921; // @[RegisterRouter.scala:87:24] wire out_womask_921 = &_out_womask_T_921; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_921 = out_rivalid_1_775 & out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8998 = out_f_rivalid_921; // @[RegisterRouter.scala:87:24] wire out_f_roready_921 = out_roready_1_775 & out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8999 = out_f_roready_921; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_921 = out_wivalid_1_775 & out_wimask_921; // @[RegisterRouter.scala:87:24] wire out_f_woready_921 = out_woready_1_775 & out_womask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9000 = ~out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9001 = ~out_wimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9002 = ~out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9003 = ~out_womask_921; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_786 = {hi_61, flags_0_go, _out_prepend_T_786}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9004 = out_prepend_786; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9005 = _out_T_9004; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_787 = _out_T_9005; // @[RegisterRouter.scala:87:24] wire out_rimask_922 = \|_out_rimask_T_922; // @[RegisterRouter.scala:87:24] wire out_wimask_922 = &_out_wimask_T_922; // @[RegisterRouter.scala:87:24] wire out_romask_922 = \|_out_romask_T_922; // @[RegisterRouter.scala:87:24] wire out_womask_922 = &_out_womask_T_922; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_922 = out_rivalid_1_776 & out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9007 = out_f_rivalid_922; // @[RegisterRouter.scala:87:24] wire out_f_roready_922 = out_roready_1_776 & out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9008 = out_f_roready_922; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_922 = out_wivalid_1_776 & out_wimask_922; // @[RegisterRouter.scala:87:24] wire out_f_woready_922 = out_woready_1_776 & out_womask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9009 = ~out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9010 = ~out_wimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9011 = ~out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9012 = ~out_womask_922; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_787 = {hi_62, flags_0_go, _out_prepend_T_787}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9013 = out_prepend_787; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9014 = _out_T_9013; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_788 = _out_T_9014; // @[RegisterRouter.scala:87:24] wire out_rimask_923 = \|_out_rimask_T_923; // @[RegisterRouter.scala:87:24] wire out_wimask_923 = &_out_wimask_T_923; // @[RegisterRouter.scala:87:24] wire out_romask_923 = \|_out_romask_T_923; // @[RegisterRouter.scala:87:24] wire out_womask_923 = &_out_womask_T_923; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_923 = out_rivalid_1_777 & out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9016 = out_f_rivalid_923; // @[RegisterRouter.scala:87:24] wire out_f_roready_923 = out_roready_1_777 & out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9017 = out_f_roready_923; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_923 = out_wivalid_1_777 & out_wimask_923; // @[RegisterRouter.scala:87:24] wire out_f_woready_923 = out_woready_1_777 & out_womask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9018 = ~out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9019 = ~out_wimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9020 = ~out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9021 = ~out_womask_923; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_788 = {hi_63, flags_0_go, _out_prepend_T_788}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9022 = out_prepend_788; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9023 = _out_T_9022; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_789 = _out_T_9023; // @[RegisterRouter.scala:87:24] wire out_rimask_924 = \|_out_rimask_T_924; // @[RegisterRouter.scala:87:24] wire out_wimask_924 = &_out_wimask_T_924; // @[RegisterRouter.scala:87:24] wire out_romask_924 = \|_out_romask_T_924; // @[RegisterRouter.scala:87:24] wire out_womask_924 = &_out_womask_T_924; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_924 = out_rivalid_1_778 & out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9025 = out_f_rivalid_924; // @[RegisterRouter.scala:87:24] wire out_f_roready_924 = out_roready_1_778 & out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9026 = out_f_roready_924; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_924 = out_wivalid_1_778 & out_wimask_924; // @[RegisterRouter.scala:87:24] wire out_f_woready_924 = out_woready_1_778 & out_womask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9027 = ~out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9028 = ~out_wimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9029 = ~out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9030 = ~out_womask_924; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_789 = {hi_64, flags_0_go, _out_prepend_T_789}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9031 = out_prepend_789; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9032 = _out_T_9031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_135 = _out_T_9032; // @[MuxLiteral.scala:49:48] wire out_rimask_925 = \|_out_rimask_T_925; // @[RegisterRouter.scala:87:24] wire out_wimask_925 = &_out_wimask_T_925; // @[RegisterRouter.scala:87:24] wire out_romask_925 = \|_out_romask_T_925; // @[RegisterRouter.scala:87:24] wire out_womask_925 = &_out_womask_T_925; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_925 = out_rivalid_1_779 & out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9034 = out_f_rivalid_925; // @[RegisterRouter.scala:87:24] wire out_f_roready_925 = out_roready_1_779 & out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9035 = out_f_roready_925; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_925 = out_wivalid_1_779 & out_wimask_925; // @[RegisterRouter.scala:87:24] wire out_f_woready_925 = out_woready_1_779 & out_womask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9036 = ~out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9037 = ~out_wimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9038 = ~out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9039 = ~out_womask_925; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9041 = _out_T_9040; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_790 = _out_T_9041; // @[RegisterRouter.scala:87:24] wire out_rimask_926 = \|_out_rimask_T_926; // @[RegisterRouter.scala:87:24] wire out_wimask_926 = &_out_wimask_T_926; // @[RegisterRouter.scala:87:24] wire out_romask_926 = \|_out_romask_T_926; // @[RegisterRouter.scala:87:24] wire out_womask_926 = &_out_womask_T_926; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_926 = out_rivalid_1_780 & out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9043 = out_f_rivalid_926; // @[RegisterRouter.scala:87:24] wire out_f_roready_926 = out_roready_1_780 & out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9044 = out_f_roready_926; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_926 = out_wivalid_1_780 & out_wimask_926; // @[RegisterRouter.scala:87:24] wire out_f_woready_926 = out_woready_1_780 & out_womask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9045 = ~out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9046 = ~out_wimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9047 = ~out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9048 = ~out_womask_926; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_790 = {hi_786, flags_0_go, _out_prepend_T_790}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9049 = out_prepend_790; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9050 = _out_T_9049; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_791 = _out_T_9050; // @[RegisterRouter.scala:87:24] wire out_rimask_927 = \|_out_rimask_T_927; // @[RegisterRouter.scala:87:24] wire out_wimask_927 = &_out_wimask_T_927; // @[RegisterRouter.scala:87:24] wire out_romask_927 = \|_out_romask_T_927; // @[RegisterRouter.scala:87:24] wire out_womask_927 = &_out_womask_T_927; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_927 = out_rivalid_1_781 & out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9052 = out_f_rivalid_927; // @[RegisterRouter.scala:87:24] wire out_f_roready_927 = out_roready_1_781 & out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9053 = out_f_roready_927; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_927 = out_wivalid_1_781 & out_wimask_927; // @[RegisterRouter.scala:87:24] wire out_f_woready_927 = out_woready_1_781 & out_womask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9054 = ~out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9055 = ~out_wimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9056 = ~out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9057 = ~out_womask_927; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_791 = {hi_787, flags_0_go, _out_prepend_T_791}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9058 = out_prepend_791; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9059 = _out_T_9058; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_792 = _out_T_9059; // @[RegisterRouter.scala:87:24] wire out_rimask_928 = \|_out_rimask_T_928; // @[RegisterRouter.scala:87:24] wire out_wimask_928 = &_out_wimask_T_928; // @[RegisterRouter.scala:87:24] wire out_romask_928 = \|_out_romask_T_928; // @[RegisterRouter.scala:87:24] wire out_womask_928 = &_out_womask_T_928; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_928 = out_rivalid_1_782 & out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9061 = out_f_rivalid_928; // @[RegisterRouter.scala:87:24] wire out_f_roready_928 = out_roready_1_782 & out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9062 = out_f_roready_928; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_928 = out_wivalid_1_782 & out_wimask_928; // @[RegisterRouter.scala:87:24] wire out_f_woready_928 = out_woready_1_782 & out_womask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9063 = ~out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9064 = ~out_wimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9065 = ~out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9066 = ~out_womask_928; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_792 = {hi_788, flags_0_go, _out_prepend_T_792}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9067 = out_prepend_792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9068 = _out_T_9067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_793 = _out_T_9068; // @[RegisterRouter.scala:87:24] wire out_rimask_929 = \|_out_rimask_T_929; // @[RegisterRouter.scala:87:24] wire out_wimask_929 = &_out_wimask_T_929; // @[RegisterRouter.scala:87:24] wire out_romask_929 = \|_out_romask_T_929; // @[RegisterRouter.scala:87:24] wire out_womask_929 = &_out_womask_T_929; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_929 = out_rivalid_1_783 & out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9070 = out_f_rivalid_929; // @[RegisterRouter.scala:87:24] wire out_f_roready_929 = out_roready_1_783 & out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9071 = out_f_roready_929; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_929 = out_wivalid_1_783 & out_wimask_929; // @[RegisterRouter.scala:87:24] wire out_f_woready_929 = out_woready_1_783 & out_womask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9072 = ~out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9073 = ~out_wimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9074 = ~out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9075 = ~out_womask_929; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_793 = {hi_789, flags_0_go, _out_prepend_T_793}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9076 = out_prepend_793; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9077 = _out_T_9076; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_794 = _out_T_9077; // @[RegisterRouter.scala:87:24] wire out_rimask_930 = \|_out_rimask_T_930; // @[RegisterRouter.scala:87:24] wire out_wimask_930 = &_out_wimask_T_930; // @[RegisterRouter.scala:87:24] wire out_romask_930 = \|_out_romask_T_930; // @[RegisterRouter.scala:87:24] wire out_womask_930 = &_out_womask_T_930; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_930 = out_rivalid_1_784 & out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9079 = out_f_rivalid_930; // @[RegisterRouter.scala:87:24] wire out_f_roready_930 = out_roready_1_784 & out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9080 = out_f_roready_930; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_930 = out_wivalid_1_784 & out_wimask_930; // @[RegisterRouter.scala:87:24] wire out_f_woready_930 = out_woready_1_784 & out_womask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9081 = ~out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9082 = ~out_wimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9083 = ~out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9084 = ~out_womask_930; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_794 = {hi_790, flags_0_go, _out_prepend_T_794}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9085 = out_prepend_794; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9086 = _out_T_9085; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_795 = _out_T_9086; // @[RegisterRouter.scala:87:24] wire out_rimask_931 = \|_out_rimask_T_931; // @[RegisterRouter.scala:87:24] wire out_wimask_931 = &_out_wimask_T_931; // @[RegisterRouter.scala:87:24] wire out_romask_931 = \|_out_romask_T_931; // @[RegisterRouter.scala:87:24] wire out_womask_931 = &_out_womask_T_931; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_931 = out_rivalid_1_785 & out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9088 = out_f_rivalid_931; // @[RegisterRouter.scala:87:24] wire out_f_roready_931 = out_roready_1_785 & out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9089 = out_f_roready_931; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_931 = out_wivalid_1_785 & out_wimask_931; // @[RegisterRouter.scala:87:24] wire out_f_woready_931 = out_woready_1_785 & out_womask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9090 = ~out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9091 = ~out_wimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9092 = ~out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9093 = ~out_womask_931; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_795 = {hi_791, flags_0_go, _out_prepend_T_795}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9094 = out_prepend_795; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9095 = _out_T_9094; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_796 = _out_T_9095; // @[RegisterRouter.scala:87:24] wire out_rimask_932 = \|_out_rimask_T_932; // @[RegisterRouter.scala:87:24] wire out_wimask_932 = &_out_wimask_T_932; // @[RegisterRouter.scala:87:24] wire out_romask_932 = \|_out_romask_T_932; // @[RegisterRouter.scala:87:24] wire out_womask_932 = &_out_womask_T_932; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_932 = out_rivalid_1_786 & out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9097 = out_f_rivalid_932; // @[RegisterRouter.scala:87:24] wire out_f_roready_932 = out_roready_1_786 & out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9098 = out_f_roready_932; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_932 = out_wivalid_1_786 & out_wimask_932; // @[RegisterRouter.scala:87:24] wire out_f_woready_932 = out_woready_1_786 & out_womask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9099 = ~out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9100 = ~out_wimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9101 = ~out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9102 = ~out_womask_932; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_796 = {hi_792, flags_0_go, _out_prepend_T_796}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9103 = out_prepend_796; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9104 = _out_T_9103; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_226 = _out_T_9104; // @[MuxLiteral.scala:49:48] wire out_rimask_933 = \|_out_rimask_T_933; // @[RegisterRouter.scala:87:24] wire out_wimask_933 = &_out_wimask_T_933; // @[RegisterRouter.scala:87:24] wire out_romask_933 = \|_out_romask_T_933; // @[RegisterRouter.scala:87:24] wire out_womask_933 = &_out_womask_T_933; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_933 = out_rivalid_1_787 & out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9106 = out_f_rivalid_933; // @[RegisterRouter.scala:87:24] wire out_f_roready_933 = out_roready_1_787 & out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9107 = out_f_roready_933; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_933 = out_wivalid_1_787 & out_wimask_933; // @[RegisterRouter.scala:87:24] wire out_f_woready_933 = out_woready_1_787 & out_womask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9108 = ~out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9109 = ~out_wimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9110 = ~out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9111 = ~out_womask_933; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9113 = _out_T_9112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_797 = _out_T_9113; // @[RegisterRouter.scala:87:24] wire out_rimask_934 = \|_out_rimask_T_934; // @[RegisterRouter.scala:87:24] wire out_wimask_934 = &_out_wimask_T_934; // @[RegisterRouter.scala:87:24] wire out_romask_934 = \|_out_romask_T_934; // @[RegisterRouter.scala:87:24] wire out_womask_934 = &_out_womask_T_934; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_934 = out_rivalid_1_788 & out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9115 = out_f_rivalid_934; // @[RegisterRouter.scala:87:24] wire out_f_roready_934 = out_roready_1_788 & out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9116 = out_f_roready_934; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_934 = out_wivalid_1_788 & out_wimask_934; // @[RegisterRouter.scala:87:24] wire out_f_woready_934 = out_woready_1_788 & out_womask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9117 = ~out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9118 = ~out_wimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9119 = ~out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9120 = ~out_womask_934; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_797 = {hi_906, flags_0_go, _out_prepend_T_797}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9121 = out_prepend_797; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9122 = _out_T_9121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_798 = _out_T_9122; // @[RegisterRouter.scala:87:24] wire out_rimask_935 = \|_out_rimask_T_935; // @[RegisterRouter.scala:87:24] wire out_wimask_935 = &_out_wimask_T_935; // @[RegisterRouter.scala:87:24] wire out_romask_935 = \|_out_romask_T_935; // @[RegisterRouter.scala:87:24] wire out_womask_935 = &_out_womask_T_935; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_935 = out_rivalid_1_789 & out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9124 = out_f_rivalid_935; // @[RegisterRouter.scala:87:24] wire out_f_roready_935 = out_roready_1_789 & out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9125 = out_f_roready_935; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_935 = out_wivalid_1_789 & out_wimask_935; // @[RegisterRouter.scala:87:24] wire out_f_woready_935 = out_woready_1_789 & out_womask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9126 = ~out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9127 = ~out_wimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9128 = ~out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9129 = ~out_womask_935; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_798 = {hi_907, flags_0_go, _out_prepend_T_798}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9130 = out_prepend_798; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9131 = _out_T_9130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_799 = _out_T_9131; // @[RegisterRouter.scala:87:24] wire out_rimask_936 = \|_out_rimask_T_936; // @[RegisterRouter.scala:87:24] wire out_wimask_936 = &_out_wimask_T_936; // @[RegisterRouter.scala:87:24] wire out_romask_936 = \|_out_romask_T_936; // @[RegisterRouter.scala:87:24] wire out_womask_936 = &_out_womask_T_936; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_936 = out_rivalid_1_790 & out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9133 = out_f_rivalid_936; // @[RegisterRouter.scala:87:24] wire out_f_roready_936 = out_roready_1_790 & out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9134 = out_f_roready_936; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_936 = out_wivalid_1_790 & out_wimask_936; // @[RegisterRouter.scala:87:24] wire out_f_woready_936 = out_woready_1_790 & out_womask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9135 = ~out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9136 = ~out_wimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9137 = ~out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9138 = ~out_womask_936; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_799 = {hi_908, flags_0_go, _out_prepend_T_799}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9139 = out_prepend_799; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9140 = _out_T_9139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_800 = _out_T_9140; // @[RegisterRouter.scala:87:24] wire out_rimask_937 = \|_out_rimask_T_937; // @[RegisterRouter.scala:87:24] wire out_wimask_937 = &_out_wimask_T_937; // @[RegisterRouter.scala:87:24] wire out_romask_937 = \|_out_romask_T_937; // @[RegisterRouter.scala:87:24] wire out_womask_937 = &_out_womask_T_937; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_937 = out_rivalid_1_791 & out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9142 = out_f_rivalid_937; // @[RegisterRouter.scala:87:24] wire out_f_roready_937 = out_roready_1_791 & out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9143 = out_f_roready_937; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_937 = out_wivalid_1_791 & out_wimask_937; // @[RegisterRouter.scala:87:24] wire out_f_woready_937 = out_woready_1_791 & out_womask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9144 = ~out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9145 = ~out_wimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9146 = ~out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9147 = ~out_womask_937; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_800 = {hi_909, flags_0_go, _out_prepend_T_800}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9148 = out_prepend_800; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9149 = _out_T_9148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_801 = _out_T_9149; // @[RegisterRouter.scala:87:24] wire out_rimask_938 = \|_out_rimask_T_938; // @[RegisterRouter.scala:87:24] wire out_wimask_938 = &_out_wimask_T_938; // @[RegisterRouter.scala:87:24] wire out_romask_938 = \|_out_romask_T_938; // @[RegisterRouter.scala:87:24] wire out_womask_938 = &_out_womask_T_938; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_938 = out_rivalid_1_792 & out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9151 = out_f_rivalid_938; // @[RegisterRouter.scala:87:24] wire out_f_roready_938 = out_roready_1_792 & out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9152 = out_f_roready_938; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_938 = out_wivalid_1_792 & out_wimask_938; // @[RegisterRouter.scala:87:24] wire out_f_woready_938 = out_woready_1_792 & out_womask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9153 = ~out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9154 = ~out_wimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9155 = ~out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9156 = ~out_womask_938; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_801 = {hi_910, flags_0_go, _out_prepend_T_801}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9157 = out_prepend_801; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9158 = _out_T_9157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_802 = _out_T_9158; // @[RegisterRouter.scala:87:24] wire out_rimask_939 = \|_out_rimask_T_939; // @[RegisterRouter.scala:87:24] wire out_wimask_939 = &_out_wimask_T_939; // @[RegisterRouter.scala:87:24] wire out_romask_939 = \|_out_romask_T_939; // @[RegisterRouter.scala:87:24] wire out_womask_939 = &_out_womask_T_939; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_939 = out_rivalid_1_793 & out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9160 = out_f_rivalid_939; // @[RegisterRouter.scala:87:24] wire out_f_roready_939 = out_roready_1_793 & out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9161 = out_f_roready_939; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_939 = out_wivalid_1_793 & out_wimask_939; // @[RegisterRouter.scala:87:24] wire out_f_woready_939 = out_woready_1_793 & out_womask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9162 = ~out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9163 = ~out_wimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9164 = ~out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9165 = ~out_womask_939; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_802 = {hi_911, flags_0_go, _out_prepend_T_802}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9166 = out_prepend_802; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9167 = _out_T_9166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_803 = _out_T_9167; // @[RegisterRouter.scala:87:24] wire out_rimask_940 = \|_out_rimask_T_940; // @[RegisterRouter.scala:87:24] wire out_wimask_940 = &_out_wimask_T_940; // @[RegisterRouter.scala:87:24] wire out_romask_940 = \|_out_romask_T_940; // @[RegisterRouter.scala:87:24] wire out_womask_940 = &_out_womask_T_940; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_940 = out_rivalid_1_794 & out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9169 = out_f_rivalid_940; // @[RegisterRouter.scala:87:24] wire out_f_roready_940 = out_roready_1_794 & out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9170 = out_f_roready_940; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_940 = out_wivalid_1_794 & out_wimask_940; // @[RegisterRouter.scala:87:24] wire out_f_woready_940 = out_woready_1_794 & out_womask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9171 = ~out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9172 = ~out_wimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9173 = ~out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9174 = ~out_womask_940; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_803 = {hi_912, flags_0_go, _out_prepend_T_803}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9175 = out_prepend_803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9176 = _out_T_9175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_241 = _out_T_9176; // @[MuxLiteral.scala:49:48] wire out_rimask_941 = \|_out_rimask_T_941; // @[RegisterRouter.scala:87:24] wire out_wimask_941 = &_out_wimask_T_941; // @[RegisterRouter.scala:87:24] wire out_romask_941 = \|_out_romask_T_941; // @[RegisterRouter.scala:87:24] wire out_womask_941 = &_out_womask_T_941; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_941 = out_rivalid_1_795 & out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9178 = out_f_rivalid_941; // @[RegisterRouter.scala:87:24] wire out_f_roready_941 = out_roready_1_795 & out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9179 = out_f_roready_941; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_941 = out_wivalid_1_795 & out_wimask_941; // @[RegisterRouter.scala:87:24] wire out_f_woready_941 = out_woready_1_795 & out_womask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9180 = ~out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9181 = ~out_wimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9182 = ~out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9183 = ~out_womask_941; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9185 = _out_T_9184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_804 = _out_T_9185; // @[RegisterRouter.scala:87:24] wire out_rimask_942 = \|_out_rimask_T_942; // @[RegisterRouter.scala:87:24] wire out_wimask_942 = &_out_wimask_T_942; // @[RegisterRouter.scala:87:24] wire out_romask_942 = \|_out_romask_T_942; // @[RegisterRouter.scala:87:24] wire out_womask_942 = &_out_womask_T_942; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_942 = out_rivalid_1_796 & out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9187 = out_f_rivalid_942; // @[RegisterRouter.scala:87:24] wire out_f_roready_942 = out_roready_1_796 & out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9188 = out_f_roready_942; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_942 = out_wivalid_1_796 & out_wimask_942; // @[RegisterRouter.scala:87:24] wire out_f_woready_942 = out_woready_1_796 & out_womask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9189 = ~out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9190 = ~out_wimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9191 = ~out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9192 = ~out_womask_942; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_804 = {hi_314, flags_0_go, _out_prepend_T_804}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9193 = out_prepend_804; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9194 = _out_T_9193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_805 = _out_T_9194; // @[RegisterRouter.scala:87:24] wire out_rimask_943 = \|_out_rimask_T_943; // @[RegisterRouter.scala:87:24] wire out_wimask_943 = &_out_wimask_T_943; // @[RegisterRouter.scala:87:24] wire out_romask_943 = \|_out_romask_T_943; // @[RegisterRouter.scala:87:24] wire out_womask_943 = &_out_womask_T_943; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_943 = out_rivalid_1_797 & out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9196 = out_f_rivalid_943; // @[RegisterRouter.scala:87:24] wire out_f_roready_943 = out_roready_1_797 & out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9197 = out_f_roready_943; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_943 = out_wivalid_1_797 & out_wimask_943; // @[RegisterRouter.scala:87:24] wire out_f_woready_943 = out_woready_1_797 & out_womask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9198 = ~out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9199 = ~out_wimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9200 = ~out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9201 = ~out_womask_943; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_805 = {hi_315, flags_0_go, _out_prepend_T_805}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9202 = out_prepend_805; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9203 = _out_T_9202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_806 = _out_T_9203; // @[RegisterRouter.scala:87:24] wire out_rimask_944 = \|_out_rimask_T_944; // @[RegisterRouter.scala:87:24] wire out_wimask_944 = &_out_wimask_T_944; // @[RegisterRouter.scala:87:24] wire out_romask_944 = \|_out_romask_T_944; // @[RegisterRouter.scala:87:24] wire out_womask_944 = &_out_womask_T_944; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_944 = out_rivalid_1_798 & out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9205 = out_f_rivalid_944; // @[RegisterRouter.scala:87:24] wire out_f_roready_944 = out_roready_1_798 & out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9206 = out_f_roready_944; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_944 = out_wivalid_1_798 & out_wimask_944; // @[RegisterRouter.scala:87:24] wire out_f_woready_944 = out_woready_1_798 & out_womask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9207 = ~out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9208 = ~out_wimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9209 = ~out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9210 = ~out_womask_944; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_806 = {hi_316, flags_0_go, _out_prepend_T_806}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9211 = out_prepend_806; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9212 = _out_T_9211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_807 = _out_T_9212; // @[RegisterRouter.scala:87:24] wire out_rimask_945 = \|_out_rimask_T_945; // @[RegisterRouter.scala:87:24] wire out_wimask_945 = &_out_wimask_T_945; // @[RegisterRouter.scala:87:24] wire out_romask_945 = \|_out_romask_T_945; // @[RegisterRouter.scala:87:24] wire out_womask_945 = &_out_womask_T_945; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_945 = out_rivalid_1_799 & out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9214 = out_f_rivalid_945; // @[RegisterRouter.scala:87:24] wire out_f_roready_945 = out_roready_1_799 & out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9215 = out_f_roready_945; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_945 = out_wivalid_1_799 & out_wimask_945; // @[RegisterRouter.scala:87:24] wire out_f_woready_945 = out_woready_1_799 & out_womask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9216 = ~out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9217 = ~out_wimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9218 = ~out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9219 = ~out_womask_945; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_807 = {hi_317, flags_0_go, _out_prepend_T_807}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9220 = out_prepend_807; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9221 = _out_T_9220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_808 = _out_T_9221; // @[RegisterRouter.scala:87:24] wire out_rimask_946 = \|_out_rimask_T_946; // @[RegisterRouter.scala:87:24] wire out_wimask_946 = &_out_wimask_T_946; // @[RegisterRouter.scala:87:24] wire out_romask_946 = \|_out_romask_T_946; // @[RegisterRouter.scala:87:24] wire out_womask_946 = &_out_womask_T_946; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_946 = out_rivalid_1_800 & out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9223 = out_f_rivalid_946; // @[RegisterRouter.scala:87:24] wire out_f_roready_946 = out_roready_1_800 & out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9224 = out_f_roready_946; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_946 = out_wivalid_1_800 & out_wimask_946; // @[RegisterRouter.scala:87:24] wire out_f_woready_946 = out_woready_1_800 & out_womask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9225 = ~out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9226 = ~out_wimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9227 = ~out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9228 = ~out_womask_946; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_808 = {hi_318, flags_0_go, _out_prepend_T_808}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9229 = out_prepend_808; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9230 = _out_T_9229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_809 = _out_T_9230; // @[RegisterRouter.scala:87:24] wire out_rimask_947 = \|_out_rimask_T_947; // @[RegisterRouter.scala:87:24] wire out_wimask_947 = &_out_wimask_T_947; // @[RegisterRouter.scala:87:24] wire out_romask_947 = \|_out_romask_T_947; // @[RegisterRouter.scala:87:24] wire out_womask_947 = &_out_womask_T_947; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_947 = out_rivalid_1_801 & out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9232 = out_f_rivalid_947; // @[RegisterRouter.scala:87:24] wire out_f_roready_947 = out_roready_1_801 & out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9233 = out_f_roready_947; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_947 = out_wivalid_1_801 & out_wimask_947; // @[RegisterRouter.scala:87:24] wire out_f_woready_947 = out_woready_1_801 & out_womask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9234 = ~out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9235 = ~out_wimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9236 = ~out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9237 = ~out_womask_947; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_809 = {hi_319, flags_0_go, _out_prepend_T_809}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9238 = out_prepend_809; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9239 = _out_T_9238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_810 = _out_T_9239; // @[RegisterRouter.scala:87:24] wire out_rimask_948 = \|_out_rimask_T_948; // @[RegisterRouter.scala:87:24] wire out_wimask_948 = &_out_wimask_T_948; // @[RegisterRouter.scala:87:24] wire out_romask_948 = \|_out_romask_T_948; // @[RegisterRouter.scala:87:24] wire out_womask_948 = &_out_womask_T_948; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_948 = out_rivalid_1_802 & out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9241 = out_f_rivalid_948; // @[RegisterRouter.scala:87:24] wire out_f_roready_948 = out_roready_1_802 & out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9242 = out_f_roready_948; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_948 = out_wivalid_1_802 & out_wimask_948; // @[RegisterRouter.scala:87:24] wire out_f_woready_948 = out_woready_1_802 & out_womask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9243 = ~out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9244 = ~out_wimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9245 = ~out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9246 = ~out_womask_948; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_810 = {hi_320, flags_0_go, _out_prepend_T_810}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9247 = out_prepend_810; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9248 = _out_T_9247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_167 = _out_T_9248; // @[MuxLiteral.scala:49:48] wire out_rimask_949 = \|_out_rimask_T_949; // @[RegisterRouter.scala:87:24] wire out_wimask_949 = &_out_wimask_T_949; // @[RegisterRouter.scala:87:24] wire out_romask_949 = \|_out_romask_T_949; // @[RegisterRouter.scala:87:24] wire out_womask_949 = &_out_womask_T_949; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_949 = out_rivalid_1_803 & out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9250 = out_f_rivalid_949; // @[RegisterRouter.scala:87:24] wire out_f_roready_949 = out_roready_1_803 & out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9251 = out_f_roready_949; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_949 = out_wivalid_1_803 & out_wimask_949; // @[RegisterRouter.scala:87:24] wire out_f_woready_949 = out_woready_1_803 & out_womask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9252 = ~out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9253 = ~out_wimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9254 = ~out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9255 = ~out_womask_949; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9257 = _out_T_9256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_811 = _out_T_9257; // @[RegisterRouter.scala:87:24] wire out_rimask_950 = \|_out_rimask_T_950; // @[RegisterRouter.scala:87:24] wire out_wimask_950 = &_out_wimask_T_950; // @[RegisterRouter.scala:87:24] wire out_romask_950 = \|_out_romask_T_950; // @[RegisterRouter.scala:87:24] wire out_womask_950 = &_out_womask_T_950; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_950 = out_rivalid_1_804 & out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9259 = out_f_rivalid_950; // @[RegisterRouter.scala:87:24] wire out_f_roready_950 = out_roready_1_804 & out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9260 = out_f_roready_950; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_950 = out_wivalid_1_804 & out_wimask_950; // @[RegisterRouter.scala:87:24] wire out_f_woready_950 = out_woready_1_804 & out_womask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9261 = ~out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9262 = ~out_wimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9263 = ~out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9264 = ~out_womask_950; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_811 = {hi_274, flags_0_go, _out_prepend_T_811}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9265 = out_prepend_811; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9266 = _out_T_9265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_812 = _out_T_9266; // @[RegisterRouter.scala:87:24] wire out_rimask_951 = \|_out_rimask_T_951; // @[RegisterRouter.scala:87:24] wire out_wimask_951 = &_out_wimask_T_951; // @[RegisterRouter.scala:87:24] wire out_romask_951 = \|_out_romask_T_951; // @[RegisterRouter.scala:87:24] wire out_womask_951 = &_out_womask_T_951; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_951 = out_rivalid_1_805 & out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9268 = out_f_rivalid_951; // @[RegisterRouter.scala:87:24] wire out_f_roready_951 = out_roready_1_805 & out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9269 = out_f_roready_951; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_951 = out_wivalid_1_805 & out_wimask_951; // @[RegisterRouter.scala:87:24] wire out_f_woready_951 = out_woready_1_805 & out_womask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9270 = ~out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9271 = ~out_wimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9272 = ~out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9273 = ~out_womask_951; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_812 = {hi_275, flags_0_go, _out_prepend_T_812}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9274 = out_prepend_812; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9275 = _out_T_9274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_813 = _out_T_9275; // @[RegisterRouter.scala:87:24] wire out_rimask_952 = \|_out_rimask_T_952; // @[RegisterRouter.scala:87:24] wire out_wimask_952 = &_out_wimask_T_952; // @[RegisterRouter.scala:87:24] wire out_romask_952 = \|_out_romask_T_952; // @[RegisterRouter.scala:87:24] wire out_womask_952 = &_out_womask_T_952; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_952 = out_rivalid_1_806 & out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9277 = out_f_rivalid_952; // @[RegisterRouter.scala:87:24] wire out_f_roready_952 = out_roready_1_806 & out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9278 = out_f_roready_952; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_952 = out_wivalid_1_806 & out_wimask_952; // @[RegisterRouter.scala:87:24] wire out_f_woready_952 = out_woready_1_806 & out_womask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9279 = ~out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9280 = ~out_wimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9281 = ~out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9282 = ~out_womask_952; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_813 = {hi_276, flags_0_go, _out_prepend_T_813}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9283 = out_prepend_813; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9284 = _out_T_9283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_814 = _out_T_9284; // @[RegisterRouter.scala:87:24] wire out_rimask_953 = \|_out_rimask_T_953; // @[RegisterRouter.scala:87:24] wire out_wimask_953 = &_out_wimask_T_953; // @[RegisterRouter.scala:87:24] wire out_romask_953 = \|_out_romask_T_953; // @[RegisterRouter.scala:87:24] wire out_womask_953 = &_out_womask_T_953; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_953 = out_rivalid_1_807 & out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9286 = out_f_rivalid_953; // @[RegisterRouter.scala:87:24] wire out_f_roready_953 = out_roready_1_807 & out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9287 = out_f_roready_953; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_953 = out_wivalid_1_807 & out_wimask_953; // @[RegisterRouter.scala:87:24] wire out_f_woready_953 = out_woready_1_807 & out_womask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9288 = ~out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9289 = ~out_wimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9290 = ~out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9291 = ~out_womask_953; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_814 = {hi_277, flags_0_go, _out_prepend_T_814}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9292 = out_prepend_814; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9293 = _out_T_9292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_815 = _out_T_9293; // @[RegisterRouter.scala:87:24] wire out_rimask_954 = \|_out_rimask_T_954; // @[RegisterRouter.scala:87:24] wire out_wimask_954 = &_out_wimask_T_954; // @[RegisterRouter.scala:87:24] wire out_romask_954 = \|_out_romask_T_954; // @[RegisterRouter.scala:87:24] wire out_womask_954 = &_out_womask_T_954; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_954 = out_rivalid_1_808 & out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9295 = out_f_rivalid_954; // @[RegisterRouter.scala:87:24] wire out_f_roready_954 = out_roready_1_808 & out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9296 = out_f_roready_954; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_954 = out_wivalid_1_808 & out_wimask_954; // @[RegisterRouter.scala:87:24] wire out_f_woready_954 = out_woready_1_808 & out_womask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9297 = ~out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9298 = ~out_wimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9299 = ~out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9300 = ~out_womask_954; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_815 = {hi_278, flags_0_go, _out_prepend_T_815}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9301 = out_prepend_815; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9302 = _out_T_9301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_816 = _out_T_9302; // @[RegisterRouter.scala:87:24] wire out_rimask_955 = \|_out_rimask_T_955; // @[RegisterRouter.scala:87:24] wire out_wimask_955 = &_out_wimask_T_955; // @[RegisterRouter.scala:87:24] wire out_romask_955 = \|_out_romask_T_955; // @[RegisterRouter.scala:87:24] wire out_womask_955 = &_out_womask_T_955; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_955 = out_rivalid_1_809 & out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9304 = out_f_rivalid_955; // @[RegisterRouter.scala:87:24] wire out_f_roready_955 = out_roready_1_809 & out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9305 = out_f_roready_955; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_955 = out_wivalid_1_809 & out_wimask_955; // @[RegisterRouter.scala:87:24] wire out_f_woready_955 = out_woready_1_809 & out_womask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9306 = ~out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9307 = ~out_wimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9308 = ~out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9309 = ~out_womask_955; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_816 = {hi_279, flags_0_go, _out_prepend_T_816}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9310 = out_prepend_816; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9311 = _out_T_9310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_817 = _out_T_9311; // @[RegisterRouter.scala:87:24] wire out_rimask_956 = \|_out_rimask_T_956; // @[RegisterRouter.scala:87:24] wire out_wimask_956 = &_out_wimask_T_956; // @[RegisterRouter.scala:87:24] wire out_romask_956 = \|_out_romask_T_956; // @[RegisterRouter.scala:87:24] wire out_womask_956 = &_out_womask_T_956; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_956 = out_rivalid_1_810 & out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9313 = out_f_rivalid_956; // @[RegisterRouter.scala:87:24] wire out_f_roready_956 = out_roready_1_810 & out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9314 = out_f_roready_956; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_956 = out_wivalid_1_810 & out_wimask_956; // @[RegisterRouter.scala:87:24] wire out_f_woready_956 = out_woready_1_810 & out_womask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9315 = ~out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9316 = ~out_wimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9317 = ~out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9318 = ~out_womask_956; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_817 = {hi_280, flags_0_go, _out_prepend_T_817}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9319 = out_prepend_817; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9320 = _out_T_9319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_162 = _out_T_9320; // @[MuxLiteral.scala:49:48] wire out_rimask_957 = \|_out_rimask_T_957; // @[RegisterRouter.scala:87:24] wire out_wimask_957 = &_out_wimask_T_957; // @[RegisterRouter.scala:87:24] wire out_romask_957 = \|_out_romask_T_957; // @[RegisterRouter.scala:87:24] wire out_womask_957 = &_out_womask_T_957; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_957 = out_rivalid_1_811 & out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9322 = out_f_rivalid_957; // @[RegisterRouter.scala:87:24] wire out_f_roready_957 = out_roready_1_811 & out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9323 = out_f_roready_957; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_957 = out_wivalid_1_811 & out_wimask_957; // @[RegisterRouter.scala:87:24] wire out_f_woready_957 = out_woready_1_811 & out_womask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9324 = ~out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9325 = ~out_wimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9326 = ~out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9327 = ~out_womask_957; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9329 = _out_T_9328; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_818 = _out_T_9329; // @[RegisterRouter.scala:87:24] wire out_rimask_958 = \|_out_rimask_T_958; // @[RegisterRouter.scala:87:24] wire out_wimask_958 = &_out_wimask_T_958; // @[RegisterRouter.scala:87:24] wire out_romask_958 = \|_out_romask_T_958; // @[RegisterRouter.scala:87:24] wire out_womask_958 = &_out_womask_T_958; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_958 = out_rivalid_1_812 & out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9331 = out_f_rivalid_958; // @[RegisterRouter.scala:87:24] wire out_f_roready_958 = out_roready_1_812 & out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9332 = out_f_roready_958; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_958 = out_wivalid_1_812 & out_wimask_958; // @[RegisterRouter.scala:87:24] wire out_f_woready_958 = out_woready_1_812 & out_womask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9333 = ~out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9334 = ~out_wimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9335 = ~out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9336 = ~out_womask_958; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_818 = {hi_1018, flags_0_go, _out_prepend_T_818}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9337 = out_prepend_818; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9338 = _out_T_9337; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_819 = _out_T_9338; // @[RegisterRouter.scala:87:24] wire out_rimask_959 = \|_out_rimask_T_959; // @[RegisterRouter.scala:87:24] wire out_wimask_959 = &_out_wimask_T_959; // @[RegisterRouter.scala:87:24] wire out_romask_959 = \|_out_romask_T_959; // @[RegisterRouter.scala:87:24] wire out_womask_959 = &_out_womask_T_959; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_959 = out_rivalid_1_813 & out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9340 = out_f_rivalid_959; // @[RegisterRouter.scala:87:24] wire out_f_roready_959 = out_roready_1_813 & out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9341 = out_f_roready_959; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_959 = out_wivalid_1_813 & out_wimask_959; // @[RegisterRouter.scala:87:24] wire out_f_woready_959 = out_woready_1_813 & out_womask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9342 = ~out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9343 = ~out_wimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9344 = ~out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9345 = ~out_womask_959; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_819 = {hi_1019, flags_0_go, _out_prepend_T_819}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9346 = out_prepend_819; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9347 = _out_T_9346; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_820 = _out_T_9347; // @[RegisterRouter.scala:87:24] wire out_rimask_960 = \|_out_rimask_T_960; // @[RegisterRouter.scala:87:24] wire out_wimask_960 = &_out_wimask_T_960; // @[RegisterRouter.scala:87:24] wire out_romask_960 = \|_out_romask_T_960; // @[RegisterRouter.scala:87:24] wire out_womask_960 = &_out_womask_T_960; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_960 = out_rivalid_1_814 & out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9349 = out_f_rivalid_960; // @[RegisterRouter.scala:87:24] wire out_f_roready_960 = out_roready_1_814 & out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9350 = out_f_roready_960; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_960 = out_wivalid_1_814 & out_wimask_960; // @[RegisterRouter.scala:87:24] wire out_f_woready_960 = out_woready_1_814 & out_womask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9351 = ~out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9352 = ~out_wimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9353 = ~out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9354 = ~out_womask_960; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_820 = {hi_1020, flags_0_go, _out_prepend_T_820}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9355 = out_prepend_820; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9356 = _out_T_9355; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_821 = _out_T_9356; // @[RegisterRouter.scala:87:24] wire out_rimask_961 = \|_out_rimask_T_961; // @[RegisterRouter.scala:87:24] wire out_wimask_961 = &_out_wimask_T_961; // @[RegisterRouter.scala:87:24] wire out_romask_961 = \|_out_romask_T_961; // @[RegisterRouter.scala:87:24] wire out_womask_961 = &_out_womask_T_961; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_961 = out_rivalid_1_815 & out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9358 = out_f_rivalid_961; // @[RegisterRouter.scala:87:24] wire out_f_roready_961 = out_roready_1_815 & out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9359 = out_f_roready_961; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_961 = out_wivalid_1_815 & out_wimask_961; // @[RegisterRouter.scala:87:24] wire out_f_woready_961 = out_woready_1_815 & out_womask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9360 = ~out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9361 = ~out_wimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9362 = ~out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9363 = ~out_womask_961; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_821 = {hi_1021, flags_0_go, _out_prepend_T_821}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9364 = out_prepend_821; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9365 = _out_T_9364; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_822 = _out_T_9365; // @[RegisterRouter.scala:87:24] wire out_rimask_962 = \|_out_rimask_T_962; // @[RegisterRouter.scala:87:24] wire out_wimask_962 = &_out_wimask_T_962; // @[RegisterRouter.scala:87:24] wire out_romask_962 = \|_out_romask_T_962; // @[RegisterRouter.scala:87:24] wire out_womask_962 = &_out_womask_T_962; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_962 = out_rivalid_1_816 & out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9367 = out_f_rivalid_962; // @[RegisterRouter.scala:87:24] wire out_f_roready_962 = out_roready_1_816 & out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9368 = out_f_roready_962; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_962 = out_wivalid_1_816 & out_wimask_962; // @[RegisterRouter.scala:87:24] wire out_f_woready_962 = out_woready_1_816 & out_womask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9369 = ~out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9370 = ~out_wimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9371 = ~out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9372 = ~out_womask_962; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_822 = {hi_1022, flags_0_go, _out_prepend_T_822}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9373 = out_prepend_822; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9374 = _out_T_9373; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_823 = _out_T_9374; // @[RegisterRouter.scala:87:24] wire out_rimask_963 = \|_out_rimask_T_963; // @[RegisterRouter.scala:87:24] wire out_wimask_963 = &_out_wimask_T_963; // @[RegisterRouter.scala:87:24] wire out_romask_963 = \|_out_romask_T_963; // @[RegisterRouter.scala:87:24] wire out_womask_963 = &_out_womask_T_963; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_963 = out_rivalid_1_817 & out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9376 = out_f_rivalid_963; // @[RegisterRouter.scala:87:24] wire out_f_roready_963 = out_roready_1_817 & out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9377 = out_f_roready_963; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_963 = out_wivalid_1_817 & out_wimask_963; // @[RegisterRouter.scala:87:24] wire out_f_woready_963 = out_woready_1_817 & out_womask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9378 = ~out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9379 = ~out_wimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9380 = ~out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9381 = ~out_womask_963; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_823 = {hi_1023, flags_0_go, _out_prepend_T_823}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9382 = out_prepend_823; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9383 = _out_T_9382; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_824 = _out_T_9383; // @[RegisterRouter.scala:87:24] wire out_rimask_964 = \|_out_rimask_T_964; // @[RegisterRouter.scala:87:24] wire out_wimask_964 = &_out_wimask_T_964; // @[RegisterRouter.scala:87:24] wire out_romask_964 = \|_out_romask_T_964; // @[RegisterRouter.scala:87:24] wire out_womask_964 = &_out_womask_T_964; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_964 = out_rivalid_1_818 & out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9385 = out_f_rivalid_964; // @[RegisterRouter.scala:87:24] wire out_f_roready_964 = out_roready_1_818 & out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9386 = out_f_roready_964; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_964 = out_wivalid_1_818 & out_wimask_964; // @[RegisterRouter.scala:87:24] wire out_f_woready_964 = out_woready_1_818 & out_womask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9387 = ~out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9388 = ~out_wimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9389 = ~out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9390 = ~out_womask_964; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_824 = {hi_1024, flags_0_go, _out_prepend_T_824}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9391 = out_prepend_824; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9392 = _out_T_9391; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_255 = _out_T_9392; // @[MuxLiteral.scala:49:48] wire out_rimask_965 = \|_out_rimask_T_965; // @[RegisterRouter.scala:87:24] wire out_wimask_965 = &_out_wimask_T_965; // @[RegisterRouter.scala:87:24] wire out_romask_965 = \|_out_romask_T_965; // @[RegisterRouter.scala:87:24] wire out_womask_965 = &_out_womask_T_965; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_965 = out_rivalid_1_819 & out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9394 = out_f_rivalid_965; // @[RegisterRouter.scala:87:24] wire out_f_roready_965 = out_roready_1_819 & out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9395 = out_f_roready_965; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_965 = out_wivalid_1_819 & out_wimask_965; // @[RegisterRouter.scala:87:24] wire out_f_woready_965 = out_woready_1_819 & out_womask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9396 = ~out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9397 = ~out_wimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9398 = ~out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9399 = ~out_womask_965; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9401 = _out_T_9400; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_825 = _out_T_9401; // @[RegisterRouter.scala:87:24] wire out_rimask_966 = \|_out_rimask_T_966; // @[RegisterRouter.scala:87:24] wire out_wimask_966 = &_out_wimask_T_966; // @[RegisterRouter.scala:87:24] wire out_romask_966 = \|_out_romask_T_966; // @[RegisterRouter.scala:87:24] wire out_womask_966 = &_out_womask_T_966; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_966 = out_rivalid_1_820 & out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9403 = out_f_rivalid_966; // @[RegisterRouter.scala:87:24] wire out_f_roready_966 = out_roready_1_820 & out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9404 = out_f_roready_966; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_966 = out_wivalid_1_820 & out_wimask_966; // @[RegisterRouter.scala:87:24] wire out_f_woready_966 = out_woready_1_820 & out_womask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9405 = ~out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9406 = ~out_wimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9407 = ~out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9408 = ~out_womask_966; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_825 = {hi_650, flags_0_go, _out_prepend_T_825}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9409 = out_prepend_825; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9410 = _out_T_9409; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_826 = _out_T_9410; // @[RegisterRouter.scala:87:24] wire out_rimask_967 = \|_out_rimask_T_967; // @[RegisterRouter.scala:87:24] wire out_wimask_967 = &_out_wimask_T_967; // @[RegisterRouter.scala:87:24] wire out_romask_967 = \|_out_romask_T_967; // @[RegisterRouter.scala:87:24] wire out_womask_967 = &_out_womask_T_967; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_967 = out_rivalid_1_821 & out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9412 = out_f_rivalid_967; // @[RegisterRouter.scala:87:24] wire out_f_roready_967 = out_roready_1_821 & out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9413 = out_f_roready_967; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_967 = out_wivalid_1_821 & out_wimask_967; // @[RegisterRouter.scala:87:24] wire out_f_woready_967 = out_woready_1_821 & out_womask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9414 = ~out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9415 = ~out_wimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9416 = ~out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9417 = ~out_womask_967; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_826 = {hi_651, flags_0_go, _out_prepend_T_826}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9418 = out_prepend_826; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9419 = _out_T_9418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_827 = _out_T_9419; // @[RegisterRouter.scala:87:24] wire out_rimask_968 = \|_out_rimask_T_968; // @[RegisterRouter.scala:87:24] wire out_wimask_968 = &_out_wimask_T_968; // @[RegisterRouter.scala:87:24] wire out_romask_968 = \|_out_romask_T_968; // @[RegisterRouter.scala:87:24] wire out_womask_968 = &_out_womask_T_968; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_968 = out_rivalid_1_822 & out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9421 = out_f_rivalid_968; // @[RegisterRouter.scala:87:24] wire out_f_roready_968 = out_roready_1_822 & out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9422 = out_f_roready_968; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_968 = out_wivalid_1_822 & out_wimask_968; // @[RegisterRouter.scala:87:24] wire out_f_woready_968 = out_woready_1_822 & out_womask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9423 = ~out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9424 = ~out_wimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9425 = ~out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9426 = ~out_womask_968; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_827 = {hi_652, flags_0_go, _out_prepend_T_827}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9427 = out_prepend_827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9428 = _out_T_9427; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_828 = _out_T_9428; // @[RegisterRouter.scala:87:24] wire out_rimask_969 = \|_out_rimask_T_969; // @[RegisterRouter.scala:87:24] wire out_wimask_969 = &_out_wimask_T_969; // @[RegisterRouter.scala:87:24] wire out_romask_969 = \|_out_romask_T_969; // @[RegisterRouter.scala:87:24] wire out_womask_969 = &_out_womask_T_969; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_969 = out_rivalid_1_823 & out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9430 = out_f_rivalid_969; // @[RegisterRouter.scala:87:24] wire out_f_roready_969 = out_roready_1_823 & out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9431 = out_f_roready_969; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_969 = out_wivalid_1_823 & out_wimask_969; // @[RegisterRouter.scala:87:24] wire out_f_woready_969 = out_woready_1_823 & out_womask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9432 = ~out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9433 = ~out_wimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9434 = ~out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9435 = ~out_womask_969; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_828 = {hi_653, flags_0_go, _out_prepend_T_828}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9436 = out_prepend_828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9437 = _out_T_9436; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_829 = _out_T_9437; // @[RegisterRouter.scala:87:24] wire out_rimask_970 = \|_out_rimask_T_970; // @[RegisterRouter.scala:87:24] wire out_wimask_970 = &_out_wimask_T_970; // @[RegisterRouter.scala:87:24] wire out_romask_970 = \|_out_romask_T_970; // @[RegisterRouter.scala:87:24] wire out_womask_970 = &_out_womask_T_970; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_970 = out_rivalid_1_824 & out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9439 = out_f_rivalid_970; // @[RegisterRouter.scala:87:24] wire out_f_roready_970 = out_roready_1_824 & out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9440 = out_f_roready_970; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_970 = out_wivalid_1_824 & out_wimask_970; // @[RegisterRouter.scala:87:24] wire out_f_woready_970 = out_woready_1_824 & out_womask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9441 = ~out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9442 = ~out_wimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9443 = ~out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9444 = ~out_womask_970; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_829 = {hi_654, flags_0_go, _out_prepend_T_829}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9445 = out_prepend_829; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9446 = _out_T_9445; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_830 = _out_T_9446; // @[RegisterRouter.scala:87:24] wire out_rimask_971 = \|_out_rimask_T_971; // @[RegisterRouter.scala:87:24] wire out_wimask_971 = &_out_wimask_T_971; // @[RegisterRouter.scala:87:24] wire out_romask_971 = \|_out_romask_T_971; // @[RegisterRouter.scala:87:24] wire out_womask_971 = &_out_womask_T_971; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_971 = out_rivalid_1_825 & out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9448 = out_f_rivalid_971; // @[RegisterRouter.scala:87:24] wire out_f_roready_971 = out_roready_1_825 & out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9449 = out_f_roready_971; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_971 = out_wivalid_1_825 & out_wimask_971; // @[RegisterRouter.scala:87:24] wire out_f_woready_971 = out_woready_1_825 & out_womask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9450 = ~out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9451 = ~out_wimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9452 = ~out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9453 = ~out_womask_971; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_830 = {hi_655, flags_0_go, _out_prepend_T_830}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9454 = out_prepend_830; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9455 = _out_T_9454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_831 = _out_T_9455; // @[RegisterRouter.scala:87:24] wire out_rimask_972 = \|_out_rimask_T_972; // @[RegisterRouter.scala:87:24] wire out_wimask_972 = &_out_wimask_T_972; // @[RegisterRouter.scala:87:24] wire out_romask_972 = \|_out_romask_T_972; // @[RegisterRouter.scala:87:24] wire out_womask_972 = &_out_womask_T_972; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_972 = out_rivalid_1_826 & out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9457 = out_f_rivalid_972; // @[RegisterRouter.scala:87:24] wire out_f_roready_972 = out_roready_1_826 & out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9458 = out_f_roready_972; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_972 = out_wivalid_1_826 & out_wimask_972; // @[RegisterRouter.scala:87:24] wire out_f_woready_972 = out_woready_1_826 & out_womask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9459 = ~out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9460 = ~out_wimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9461 = ~out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9462 = ~out_womask_972; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_831 = {hi_656, flags_0_go, _out_prepend_T_831}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9463 = out_prepend_831; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9464 = _out_T_9463; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_209 = _out_T_9464; // @[MuxLiteral.scala:49:48] wire out_rimask_973 = \|_out_rimask_T_973; // @[RegisterRouter.scala:87:24] wire out_wimask_973 = &_out_wimask_T_973; // @[RegisterRouter.scala:87:24] wire out_romask_973 = \|_out_romask_T_973; // @[RegisterRouter.scala:87:24] wire out_womask_973 = &_out_womask_T_973; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_973 = out_rivalid_1_827 & out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9466 = out_f_rivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_roready_973 = out_roready_1_827 & out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9467 = out_f_roready_973; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_973 = out_wivalid_1_827 & out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9468 = out_f_wivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_woready_973 = out_woready_1_827 & out_womask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9469 = out_f_woready_973; // @[RegisterRouter.scala:87:24] wire _out_T_9470 = ~out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9471 = ~out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9472 = ~out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9473 = ~out_womask_973; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9475 = _out_T_9474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_832 = _out_T_9475; // @[RegisterRouter.scala:87:24] wire out_rimask_974 = \|_out_rimask_T_974; // @[RegisterRouter.scala:87:24] wire out_wimask_974 = &_out_wimask_T_974; // @[RegisterRouter.scala:87:24] wire out_romask_974 = \|_out_romask_T_974; // @[RegisterRouter.scala:87:24] wire out_womask_974 = &_out_womask_T_974; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_974 = out_rivalid_1_828 & out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9477 = out_f_rivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_roready_974 = out_roready_1_828 & out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9478 = out_f_roready_974; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_974 = out_wivalid_1_828 & out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9479 = out_f_wivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_woready_974 = out_woready_1_828 & out_womask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9480 = out_f_woready_974; // @[RegisterRouter.scala:87:24] wire _out_T_9481 = ~out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9482 = ~out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9483 = ~out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9484 = ~out_womask_974; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_832 = {abstractDataMem_1, _out_prepend_T_832}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9485 = out_prepend_832; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9486 = _out_T_9485; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_833 = _out_T_9486; // @[RegisterRouter.scala:87:24] wire out_rimask_975 = \|_out_rimask_T_975; // @[RegisterRouter.scala:87:24] wire out_wimask_975 = &_out_wimask_T_975; // @[RegisterRouter.scala:87:24] wire out_romask_975 = \|_out_romask_T_975; // @[RegisterRouter.scala:87:24] wire out_womask_975 = &_out_womask_T_975; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_975 = out_rivalid_1_829 & out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9488 = out_f_rivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_roready_975 = out_roready_1_829 & out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9489 = out_f_roready_975; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_975 = out_wivalid_1_829 & out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9490 = out_f_wivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_woready_975 = out_woready_1_829 & out_womask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9491 = out_f_woready_975; // @[RegisterRouter.scala:87:24] wire _out_T_9492 = ~out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9493 = ~out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9494 = ~out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9495 = ~out_womask_975; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_833 = {abstractDataMem_2, _out_prepend_T_833}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9496 = out_prepend_833; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9497 = _out_T_9496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_834 = _out_T_9497; // @[RegisterRouter.scala:87:24] wire out_rimask_976 = \|_out_rimask_T_976; // @[RegisterRouter.scala:87:24] wire out_wimask_976 = &_out_wimask_T_976; // @[RegisterRouter.scala:87:24] wire out_romask_976 = \|_out_romask_T_976; // @[RegisterRouter.scala:87:24] wire out_womask_976 = &_out_womask_T_976; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_976 = out_rivalid_1_830 & out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9499 = out_f_rivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_roready_976 = out_roready_1_830 & out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9500 = out_f_roready_976; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_976 = out_wivalid_1_830 & out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9501 = out_f_wivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_woready_976 = out_woready_1_830 & out_womask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9502 = out_f_woready_976; // @[RegisterRouter.scala:87:24] wire _out_T_9503 = ~out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9504 = ~out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9505 = ~out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9506 = ~out_womask_976; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_834 = {abstractDataMem_3, _out_prepend_T_834}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9507 = out_prepend_834; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9508 = _out_T_9507; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_835 = _out_T_9508; // @[RegisterRouter.scala:87:24] wire out_rimask_977 = \|_out_rimask_T_977; // @[RegisterRouter.scala:87:24] wire out_wimask_977 = &_out_wimask_T_977; // @[RegisterRouter.scala:87:24] wire out_romask_977 = \|_out_romask_T_977; // @[RegisterRouter.scala:87:24] wire out_womask_977 = &_out_womask_T_977; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_977 = out_rivalid_1_831 & out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9510 = out_f_rivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_roready_977 = out_roready_1_831 & out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9511 = out_f_roready_977; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_977 = out_wivalid_1_831 & out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9512 = out_f_wivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_woready_977 = out_woready_1_831 & out_womask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9513 = out_f_woready_977; // @[RegisterRouter.scala:87:24] wire _out_T_9514 = ~out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9515 = ~out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9516 = ~out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9517 = ~out_womask_977; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_835 = {abstractDataMem_4, _out_prepend_T_835}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9518 = out_prepend_835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9519 = _out_T_9518; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_836 = _out_T_9519; // @[RegisterRouter.scala:87:24] wire out_rimask_978 = \|_out_rimask_T_978; // @[RegisterRouter.scala:87:24] wire out_wimask_978 = &_out_wimask_T_978; // @[RegisterRouter.scala:87:24] wire out_romask_978 = \|_out_romask_T_978; // @[RegisterRouter.scala:87:24] wire out_womask_978 = &_out_womask_T_978; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_978 = out_rivalid_1_832 & out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9521 = out_f_rivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_roready_978 = out_roready_1_832 & out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9522 = out_f_roready_978; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_978 = out_wivalid_1_832 & out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9523 = out_f_wivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_woready_978 = out_woready_1_832 & out_womask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9524 = out_f_woready_978; // @[RegisterRouter.scala:87:24] wire _out_T_9525 = ~out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9526 = ~out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9527 = ~out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9528 = ~out_womask_978; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_836 = {abstractDataMem_5, _out_prepend_T_836}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9529 = out_prepend_836; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9530 = _out_T_9529; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_837 = _out_T_9530; // @[RegisterRouter.scala:87:24] wire out_rimask_979 = \|_out_rimask_T_979; // @[RegisterRouter.scala:87:24] wire out_wimask_979 = &_out_wimask_T_979; // @[RegisterRouter.scala:87:24] wire out_romask_979 = \|_out_romask_T_979; // @[RegisterRouter.scala:87:24] wire out_womask_979 = &_out_womask_T_979; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_979 = out_rivalid_1_833 & out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9532 = out_f_rivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_roready_979 = out_roready_1_833 & out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9533 = out_f_roready_979; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_979 = out_wivalid_1_833 & out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9534 = out_f_wivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_woready_979 = out_woready_1_833 & out_womask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9535 = out_f_woready_979; // @[RegisterRouter.scala:87:24] wire _out_T_9536 = ~out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9537 = ~out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9538 = ~out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9539 = ~out_womask_979; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_837 = {abstractDataMem_6, _out_prepend_T_837}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9540 = out_prepend_837; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9541 = _out_T_9540; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_838 = _out_T_9541; // @[RegisterRouter.scala:87:24] wire out_rimask_980 = \|_out_rimask_T_980; // @[RegisterRouter.scala:87:24] wire out_wimask_980 = &_out_wimask_T_980; // @[RegisterRouter.scala:87:24] wire out_romask_980 = \|_out_romask_T_980; // @[RegisterRouter.scala:87:24] wire out_womask_980 = &_out_womask_T_980; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_980 = out_rivalid_1_834 & out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9543 = out_f_rivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_roready_980 = out_roready_1_834 & out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9544 = out_f_roready_980; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_980 = out_wivalid_1_834 & out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9545 = out_f_wivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_woready_980 = out_woready_1_834 & out_womask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9546 = out_f_woready_980; // @[RegisterRouter.scala:87:24] wire _out_T_9547 = ~out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9548 = ~out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9549 = ~out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9550 = ~out_womask_980; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_838 = {abstractDataMem_7, _out_prepend_T_838}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9551 = out_prepend_838; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9552 = _out_T_9551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_112 = _out_T_9552; // @[MuxLiteral.scala:49:48] wire out_rimask_981 = \|_out_rimask_T_981; // @[RegisterRouter.scala:87:24] wire out_wimask_981 = &_out_wimask_T_981; // @[RegisterRouter.scala:87:24] wire out_romask_981 = \|_out_romask_T_981; // @[RegisterRouter.scala:87:24] wire out_womask_981 = &_out_womask_T_981; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_981 = out_rivalid_1_835 & out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9554 = out_f_rivalid_981; // @[RegisterRouter.scala:87:24] wire out_f_roready_981 = out_roready_1_835 & out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9555 = out_f_roready_981; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_981 = out_wivalid_1_835 & out_wimask_981; // @[RegisterRouter.scala:87:24] wire out_f_woready_981 = out_woready_1_835 & out_womask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9556 = ~out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9557 = ~out_wimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9558 = ~out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9559 = ~out_womask_981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9561 = _out_T_9560; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_839 = _out_T_9561; // @[RegisterRouter.scala:87:24] wire out_rimask_982 = \|_out_rimask_T_982; // @[RegisterRouter.scala:87:24] wire out_wimask_982 = &_out_wimask_T_982; // @[RegisterRouter.scala:87:24] wire out_romask_982 = \|_out_romask_T_982; // @[RegisterRouter.scala:87:24] wire out_womask_982 = &_out_womask_T_982; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_982 = out_rivalid_1_836 & out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9563 = out_f_rivalid_982; // @[RegisterRouter.scala:87:24] wire out_f_roready_982 = out_roready_1_836 & out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9564 = out_f_roready_982; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_982 = out_wivalid_1_836 & out_wimask_982; // @[RegisterRouter.scala:87:24] wire out_f_woready_982 = out_woready_1_836 & out_womask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9565 = ~out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9566 = ~out_wimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9567 = ~out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9568 = ~out_womask_982; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_839 = {hi_530, flags_0_go, _out_prepend_T_839}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9569 = out_prepend_839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9570 = _out_T_9569; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_840 = _out_T_9570; // @[RegisterRouter.scala:87:24] wire out_rimask_983 = \|_out_rimask_T_983; // @[RegisterRouter.scala:87:24] wire out_wimask_983 = &_out_wimask_T_983; // @[RegisterRouter.scala:87:24] wire out_romask_983 = \|_out_romask_T_983; // @[RegisterRouter.scala:87:24] wire out_womask_983 = &_out_womask_T_983; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_983 = out_rivalid_1_837 & out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9572 = out_f_rivalid_983; // @[RegisterRouter.scala:87:24] wire out_f_roready_983 = out_roready_1_837 & out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9573 = out_f_roready_983; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_983 = out_wivalid_1_837 & out_wimask_983; // @[RegisterRouter.scala:87:24] wire out_f_woready_983 = out_woready_1_837 & out_womask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9574 = ~out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9575 = ~out_wimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9576 = ~out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9577 = ~out_womask_983; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_840 = {hi_531, flags_0_go, _out_prepend_T_840}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9578 = out_prepend_840; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9579 = _out_T_9578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_841 = _out_T_9579; // @[RegisterRouter.scala:87:24] wire out_rimask_984 = \|_out_rimask_T_984; // @[RegisterRouter.scala:87:24] wire out_wimask_984 = &_out_wimask_T_984; // @[RegisterRouter.scala:87:24] wire out_romask_984 = \|_out_romask_T_984; // @[RegisterRouter.scala:87:24] wire out_womask_984 = &_out_womask_T_984; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_984 = out_rivalid_1_838 & out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9581 = out_f_rivalid_984; // @[RegisterRouter.scala:87:24] wire out_f_roready_984 = out_roready_1_838 & out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9582 = out_f_roready_984; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_984 = out_wivalid_1_838 & out_wimask_984; // @[RegisterRouter.scala:87:24] wire out_f_woready_984 = out_woready_1_838 & out_womask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9583 = ~out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9584 = ~out_wimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9585 = ~out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9586 = ~out_womask_984; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_841 = {hi_532, flags_0_go, _out_prepend_T_841}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9587 = out_prepend_841; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9588 = _out_T_9587; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_842 = _out_T_9588; // @[RegisterRouter.scala:87:24] wire out_rimask_985 = \|_out_rimask_T_985; // @[RegisterRouter.scala:87:24] wire out_wimask_985 = &_out_wimask_T_985; // @[RegisterRouter.scala:87:24] wire out_romask_985 = \|_out_romask_T_985; // @[RegisterRouter.scala:87:24] wire out_womask_985 = &_out_womask_T_985; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_985 = out_rivalid_1_839 & out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9590 = out_f_rivalid_985; // @[RegisterRouter.scala:87:24] wire out_f_roready_985 = out_roready_1_839 & out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9591 = out_f_roready_985; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_985 = out_wivalid_1_839 & out_wimask_985; // @[RegisterRouter.scala:87:24] wire out_f_woready_985 = out_woready_1_839 & out_womask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9592 = ~out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9593 = ~out_wimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9594 = ~out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9595 = ~out_womask_985; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_842 = {hi_533, flags_0_go, _out_prepend_T_842}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9596 = out_prepend_842; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9597 = _out_T_9596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_843 = _out_T_9597; // @[RegisterRouter.scala:87:24] wire out_rimask_986 = \|_out_rimask_T_986; // @[RegisterRouter.scala:87:24] wire out_wimask_986 = &_out_wimask_T_986; // @[RegisterRouter.scala:87:24] wire out_romask_986 = \|_out_romask_T_986; // @[RegisterRouter.scala:87:24] wire out_womask_986 = &_out_womask_T_986; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_986 = out_rivalid_1_840 & out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9599 = out_f_rivalid_986; // @[RegisterRouter.scala:87:24] wire out_f_roready_986 = out_roready_1_840 & out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9600 = out_f_roready_986; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_986 = out_wivalid_1_840 & out_wimask_986; // @[RegisterRouter.scala:87:24] wire out_f_woready_986 = out_woready_1_840 & out_womask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9601 = ~out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9602 = ~out_wimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9603 = ~out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9604 = ~out_womask_986; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_843 = {hi_534, flags_0_go, _out_prepend_T_843}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9605 = out_prepend_843; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9606 = _out_T_9605; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_844 = _out_T_9606; // @[RegisterRouter.scala:87:24] wire out_rimask_987 = \|_out_rimask_T_987; // @[RegisterRouter.scala:87:24] wire out_wimask_987 = &_out_wimask_T_987; // @[RegisterRouter.scala:87:24] wire out_romask_987 = \|_out_romask_T_987; // @[RegisterRouter.scala:87:24] wire out_womask_987 = &_out_womask_T_987; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_987 = out_rivalid_1_841 & out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9608 = out_f_rivalid_987; // @[RegisterRouter.scala:87:24] wire out_f_roready_987 = out_roready_1_841 & out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9609 = out_f_roready_987; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_987 = out_wivalid_1_841 & out_wimask_987; // @[RegisterRouter.scala:87:24] wire out_f_woready_987 = out_woready_1_841 & out_womask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9610 = ~out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9611 = ~out_wimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9612 = ~out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9613 = ~out_womask_987; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_844 = {hi_535, flags_0_go, _out_prepend_T_844}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9614 = out_prepend_844; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9615 = _out_T_9614; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_845 = _out_T_9615; // @[RegisterRouter.scala:87:24] wire out_rimask_988 = \|_out_rimask_T_988; // @[RegisterRouter.scala:87:24] wire out_wimask_988 = &_out_wimask_T_988; // @[RegisterRouter.scala:87:24] wire out_romask_988 = \|_out_romask_T_988; // @[RegisterRouter.scala:87:24] wire out_womask_988 = &_out_womask_T_988; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_988 = out_rivalid_1_842 & out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9617 = out_f_rivalid_988; // @[RegisterRouter.scala:87:24] wire out_f_roready_988 = out_roready_1_842 & out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9618 = out_f_roready_988; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_988 = out_wivalid_1_842 & out_wimask_988; // @[RegisterRouter.scala:87:24] wire out_f_woready_988 = out_woready_1_842 & out_womask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9619 = ~out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9620 = ~out_wimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9621 = ~out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9622 = ~out_womask_988; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_845 = {hi_536, flags_0_go, _out_prepend_T_845}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9623 = out_prepend_845; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9624 = _out_T_9623; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_194 = _out_T_9624; // @[MuxLiteral.scala:49:48] wire out_rimask_989 = \|_out_rimask_T_989; // @[RegisterRouter.scala:87:24] wire out_wimask_989 = &_out_wimask_T_989; // @[RegisterRouter.scala:87:24] wire out_romask_989 = \|_out_romask_T_989; // @[RegisterRouter.scala:87:24] wire out_womask_989 = &_out_womask_T_989; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_989 = out_rivalid_1_843 & out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9626 = out_f_rivalid_989; // @[RegisterRouter.scala:87:24] wire out_f_roready_989 = out_roready_1_843 & out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9627 = out_f_roready_989; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_989 = out_wivalid_1_843 & out_wimask_989; // @[RegisterRouter.scala:87:24] wire out_f_woready_989 = out_woready_1_843 & out_womask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9628 = ~out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9629 = ~out_wimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9630 = ~out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9631 = ~out_womask_989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9633 = _out_T_9632; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_846 = _out_T_9633; // @[RegisterRouter.scala:87:24] wire out_rimask_990 = \|_out_rimask_T_990; // @[RegisterRouter.scala:87:24] wire out_wimask_990 = &_out_wimask_T_990; // @[RegisterRouter.scala:87:24] wire out_romask_990 = \|_out_romask_T_990; // @[RegisterRouter.scala:87:24] wire out_womask_990 = &_out_womask_T_990; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_990 = out_rivalid_1_844 & out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9635 = out_f_rivalid_990; // @[RegisterRouter.scala:87:24] wire out_f_roready_990 = out_roready_1_844 & out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9636 = out_f_roready_990; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_990 = out_wivalid_1_844 & out_wimask_990; // @[RegisterRouter.scala:87:24] wire out_f_woready_990 = out_woready_1_844 & out_womask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9637 = ~out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9638 = ~out_wimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9639 = ~out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9640 = ~out_womask_990; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_846 = {hi_138, flags_0_go, _out_prepend_T_846}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9641 = out_prepend_846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9642 = _out_T_9641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_847 = _out_T_9642; // @[RegisterRouter.scala:87:24] wire out_rimask_991 = \|_out_rimask_T_991; // @[RegisterRouter.scala:87:24] wire out_wimask_991 = &_out_wimask_T_991; // @[RegisterRouter.scala:87:24] wire out_romask_991 = \|_out_romask_T_991; // @[RegisterRouter.scala:87:24] wire out_womask_991 = &_out_womask_T_991; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_991 = out_rivalid_1_845 & out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9644 = out_f_rivalid_991; // @[RegisterRouter.scala:87:24] wire out_f_roready_991 = out_roready_1_845 & out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9645 = out_f_roready_991; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_991 = out_wivalid_1_845 & out_wimask_991; // @[RegisterRouter.scala:87:24] wire out_f_woready_991 = out_woready_1_845 & out_womask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9646 = ~out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9647 = ~out_wimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9648 = ~out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9649 = ~out_womask_991; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_847 = {hi_139, flags_0_go, _out_prepend_T_847}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9650 = out_prepend_847; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9651 = _out_T_9650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_848 = _out_T_9651; // @[RegisterRouter.scala:87:24] wire out_rimask_992 = \|_out_rimask_T_992; // @[RegisterRouter.scala:87:24] wire out_wimask_992 = &_out_wimask_T_992; // @[RegisterRouter.scala:87:24] wire out_romask_992 = \|_out_romask_T_992; // @[RegisterRouter.scala:87:24] wire out_womask_992 = &_out_womask_T_992; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_992 = out_rivalid_1_846 & out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9653 = out_f_rivalid_992; // @[RegisterRouter.scala:87:24] wire out_f_roready_992 = out_roready_1_846 & out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9654 = out_f_roready_992; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_992 = out_wivalid_1_846 & out_wimask_992; // @[RegisterRouter.scala:87:24] wire out_f_woready_992 = out_woready_1_846 & out_womask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9655 = ~out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9656 = ~out_wimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9657 = ~out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9658 = ~out_womask_992; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_848 = {hi_140, flags_0_go, _out_prepend_T_848}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9659 = out_prepend_848; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9660 = _out_T_9659; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_849 = _out_T_9660; // @[RegisterRouter.scala:87:24] wire out_rimask_993 = \|_out_rimask_T_993; // @[RegisterRouter.scala:87:24] wire out_wimask_993 = &_out_wimask_T_993; // @[RegisterRouter.scala:87:24] wire out_romask_993 = \|_out_romask_T_993; // @[RegisterRouter.scala:87:24] wire out_womask_993 = &_out_womask_T_993; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_993 = out_rivalid_1_847 & out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9662 = out_f_rivalid_993; // @[RegisterRouter.scala:87:24] wire out_f_roready_993 = out_roready_1_847 & out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9663 = out_f_roready_993; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_993 = out_wivalid_1_847 & out_wimask_993; // @[RegisterRouter.scala:87:24] wire out_f_woready_993 = out_woready_1_847 & out_womask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9664 = ~out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9665 = ~out_wimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9666 = ~out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9667 = ~out_womask_993; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_849 = {hi_141, flags_0_go, _out_prepend_T_849}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9668 = out_prepend_849; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9669 = _out_T_9668; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_850 = _out_T_9669; // @[RegisterRouter.scala:87:24] wire out_rimask_994 = \|_out_rimask_T_994; // @[RegisterRouter.scala:87:24] wire out_wimask_994 = &_out_wimask_T_994; // @[RegisterRouter.scala:87:24] wire out_romask_994 = \|_out_romask_T_994; // @[RegisterRouter.scala:87:24] wire out_womask_994 = &_out_womask_T_994; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_994 = out_rivalid_1_848 & out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9671 = out_f_rivalid_994; // @[RegisterRouter.scala:87:24] wire out_f_roready_994 = out_roready_1_848 & out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9672 = out_f_roready_994; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_994 = out_wivalid_1_848 & out_wimask_994; // @[RegisterRouter.scala:87:24] wire out_f_woready_994 = out_woready_1_848 & out_womask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9673 = ~out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9674 = ~out_wimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9675 = ~out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9676 = ~out_womask_994; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_850 = {hi_142, flags_0_go, _out_prepend_T_850}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9677 = out_prepend_850; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9678 = _out_T_9677; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_851 = _out_T_9678; // @[RegisterRouter.scala:87:24] wire out_rimask_995 = \|_out_rimask_T_995; // @[RegisterRouter.scala:87:24] wire out_wimask_995 = &_out_wimask_T_995; // @[RegisterRouter.scala:87:24] wire out_romask_995 = \|_out_romask_T_995; // @[RegisterRouter.scala:87:24] wire out_womask_995 = &_out_womask_T_995; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_995 = out_rivalid_1_849 & out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9680 = out_f_rivalid_995; // @[RegisterRouter.scala:87:24] wire out_f_roready_995 = out_roready_1_849 & out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9681 = out_f_roready_995; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_995 = out_wivalid_1_849 & out_wimask_995; // @[RegisterRouter.scala:87:24] wire out_f_woready_995 = out_woready_1_849 & out_womask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9682 = ~out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9683 = ~out_wimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9684 = ~out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9685 = ~out_womask_995; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_851 = {hi_143, flags_0_go, _out_prepend_T_851}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9686 = out_prepend_851; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9687 = _out_T_9686; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_852 = _out_T_9687; // @[RegisterRouter.scala:87:24] wire out_rimask_996 = \|_out_rimask_T_996; // @[RegisterRouter.scala:87:24] wire out_wimask_996 = &_out_wimask_T_996; // @[RegisterRouter.scala:87:24] wire out_romask_996 = \|_out_romask_T_996; // @[RegisterRouter.scala:87:24] wire out_womask_996 = &_out_womask_T_996; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_996 = out_rivalid_1_850 & out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9689 = out_f_rivalid_996; // @[RegisterRouter.scala:87:24] wire out_f_roready_996 = out_roready_1_850 & out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9690 = out_f_roready_996; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_996 = out_wivalid_1_850 & out_wimask_996; // @[RegisterRouter.scala:87:24] wire out_f_woready_996 = out_woready_1_850 & out_womask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9691 = ~out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9692 = ~out_wimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9693 = ~out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9694 = ~out_womask_996; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_852 = {hi_144, flags_0_go, _out_prepend_T_852}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9695 = out_prepend_852; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9696 = _out_T_9695; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_145 = _out_T_9696; // @[MuxLiteral.scala:49:48] wire out_rimask_997 = \|_out_rimask_T_997; // @[RegisterRouter.scala:87:24] wire out_wimask_997 = &_out_wimask_T_997; // @[RegisterRouter.scala:87:24] wire out_romask_997 = \|_out_romask_T_997; // @[RegisterRouter.scala:87:24] wire out_womask_997 = &_out_womask_T_997; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_997 = out_rivalid_1_851 & out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9698 = out_f_rivalid_997; // @[RegisterRouter.scala:87:24] wire out_f_roready_997 = out_roready_1_851 & out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9699 = out_f_roready_997; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_997 = out_wivalid_1_851 & out_wimask_997; // @[RegisterRouter.scala:87:24] wire out_f_woready_997 = out_woready_1_851 & out_womask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9700 = ~out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9701 = ~out_wimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9702 = ~out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9703 = ~out_womask_997; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9705 = _out_T_9704; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_853 = _out_T_9705; // @[RegisterRouter.scala:87:24] wire out_rimask_998 = \|_out_rimask_T_998; // @[RegisterRouter.scala:87:24] wire out_wimask_998 = &_out_wimask_T_998; // @[RegisterRouter.scala:87:24] wire out_romask_998 = \|_out_romask_T_998; // @[RegisterRouter.scala:87:24] wire out_womask_998 = &_out_womask_T_998; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_998 = out_rivalid_1_852 & out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9707 = out_f_rivalid_998; // @[RegisterRouter.scala:87:24] wire out_f_roready_998 = out_roready_1_852 & out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9708 = out_f_roready_998; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_998 = out_wivalid_1_852 & out_wimask_998; // @[RegisterRouter.scala:87:24] wire out_f_woready_998 = out_woready_1_852 & out_womask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9709 = ~out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9710 = ~out_wimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9711 = ~out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9712 = ~out_womask_998; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_853 = {hi_178, flags_0_go, _out_prepend_T_853}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9713 = out_prepend_853; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9714 = _out_T_9713; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_854 = _out_T_9714; // @[RegisterRouter.scala:87:24] wire out_rimask_999 = \|_out_rimask_T_999; // @[RegisterRouter.scala:87:24] wire out_wimask_999 = &_out_wimask_T_999; // @[RegisterRouter.scala:87:24] wire out_romask_999 = \|_out_romask_T_999; // @[RegisterRouter.scala:87:24] wire out_womask_999 = &_out_womask_T_999; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_999 = out_rivalid_1_853 & out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9716 = out_f_rivalid_999; // @[RegisterRouter.scala:87:24] wire out_f_roready_999 = out_roready_1_853 & out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9717 = out_f_roready_999; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_999 = out_wivalid_1_853 & out_wimask_999; // @[RegisterRouter.scala:87:24] wire out_f_woready_999 = out_woready_1_853 & out_womask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9718 = ~out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9719 = ~out_wimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9720 = ~out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9721 = ~out_womask_999; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_854 = {hi_179, flags_0_go, _out_prepend_T_854}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9722 = out_prepend_854; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9723 = _out_T_9722; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_855 = _out_T_9723; // @[RegisterRouter.scala:87:24] wire out_rimask_1000 = \|_out_rimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_wimask_1000 = &_out_wimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_romask_1000 = \|_out_romask_T_1000; // @[RegisterRouter.scala:87:24] wire out_womask_1000 = &_out_womask_T_1000; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1000 = out_rivalid_1_854 & out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9725 = out_f_rivalid_1000; // @[RegisterRouter.scala:87:24] wire out_f_roready_1000 = out_roready_1_854 & out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9726 = out_f_roready_1000; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1000 = out_wivalid_1_854 & out_wimask_1000; // @[RegisterRouter.scala:87:24] wire out_f_woready_1000 = out_woready_1_854 & out_womask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9727 = ~out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9728 = ~out_wimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9729 = ~out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9730 = ~out_womask_1000; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_855 = {hi_180, flags_0_go, _out_prepend_T_855}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9731 = out_prepend_855; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9732 = _out_T_9731; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_856 = _out_T_9732; // @[RegisterRouter.scala:87:24] wire out_rimask_1001 = \|_out_rimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_wimask_1001 = &_out_wimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_romask_1001 = \|_out_romask_T_1001; // @[RegisterRouter.scala:87:24] wire out_womask_1001 = &_out_womask_T_1001; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1001 = out_rivalid_1_855 & out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9734 = out_f_rivalid_1001; // @[RegisterRouter.scala:87:24] wire out_f_roready_1001 = out_roready_1_855 & out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9735 = out_f_roready_1001; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1001 = out_wivalid_1_855 & out_wimask_1001; // @[RegisterRouter.scala:87:24] wire out_f_woready_1001 = out_woready_1_855 & out_womask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9736 = ~out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9737 = ~out_wimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9738 = ~out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9739 = ~out_womask_1001; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_856 = {hi_181, flags_0_go, _out_prepend_T_856}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9740 = out_prepend_856; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9741 = _out_T_9740; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_857 = _out_T_9741; // @[RegisterRouter.scala:87:24] wire out_rimask_1002 = \|_out_rimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_wimask_1002 = &_out_wimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_romask_1002 = \|_out_romask_T_1002; // @[RegisterRouter.scala:87:24] wire out_womask_1002 = &_out_womask_T_1002; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1002 = out_rivalid_1_856 & out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9743 = out_f_rivalid_1002; // @[RegisterRouter.scala:87:24] wire out_f_roready_1002 = out_roready_1_856 & out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9744 = out_f_roready_1002; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1002 = out_wivalid_1_856 & out_wimask_1002; // @[RegisterRouter.scala:87:24] wire out_f_woready_1002 = out_woready_1_856 & out_womask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9745 = ~out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9746 = ~out_wimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9747 = ~out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9748 = ~out_womask_1002; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_857 = {hi_182, flags_0_go, _out_prepend_T_857}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9749 = out_prepend_857; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9750 = _out_T_9749; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_858 = _out_T_9750; // @[RegisterRouter.scala:87:24] wire out_rimask_1003 = \|_out_rimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_wimask_1003 = &_out_wimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_romask_1003 = \|_out_romask_T_1003; // @[RegisterRouter.scala:87:24] wire out_womask_1003 = &_out_womask_T_1003; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1003 = out_rivalid_1_857 & out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9752 = out_f_rivalid_1003; // @[RegisterRouter.scala:87:24] wire out_f_roready_1003 = out_roready_1_857 & out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9753 = out_f_roready_1003; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1003 = out_wivalid_1_857 & out_wimask_1003; // @[RegisterRouter.scala:87:24] wire out_f_woready_1003 = out_woready_1_857 & out_womask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9754 = ~out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9755 = ~out_wimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9756 = ~out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9757 = ~out_womask_1003; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_858 = {hi_183, flags_0_go, _out_prepend_T_858}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9758 = out_prepend_858; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9759 = _out_T_9758; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_859 = _out_T_9759; // @[RegisterRouter.scala:87:24] wire out_rimask_1004 = \|_out_rimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_wimask_1004 = &_out_wimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_romask_1004 = \|_out_romask_T_1004; // @[RegisterRouter.scala:87:24] wire out_womask_1004 = &_out_womask_T_1004; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1004 = out_rivalid_1_858 & out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9761 = out_f_rivalid_1004; // @[RegisterRouter.scala:87:24] wire out_f_roready_1004 = out_roready_1_858 & out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9762 = out_f_roready_1004; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1004 = out_wivalid_1_858 & out_wimask_1004; // @[RegisterRouter.scala:87:24] wire out_f_woready_1004 = out_woready_1_858 & out_womask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9763 = ~out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9764 = ~out_wimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9765 = ~out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9766 = ~out_womask_1004; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_859 = {hi_184, flags_0_go, _out_prepend_T_859}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9767 = out_prepend_859; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9768 = _out_T_9767; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_150 = _out_T_9768; // @[MuxLiteral.scala:49:48] wire out_rimask_1005 = \|_out_rimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_wimask_1005 = &_out_wimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_romask_1005 = \|_out_romask_T_1005; // @[RegisterRouter.scala:87:24] wire out_womask_1005 = &_out_womask_T_1005; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1005 = out_rivalid_1_859 & out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9770 = out_f_rivalid_1005; // @[RegisterRouter.scala:87:24] wire out_f_roready_1005 = out_roready_1_859 & out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9771 = out_f_roready_1005; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1005 = out_wivalid_1_859 & out_wimask_1005; // @[RegisterRouter.scala:87:24] wire out_f_woready_1005 = out_woready_1_859 & out_womask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9772 = ~out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9773 = ~out_wimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9774 = ~out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9775 = ~out_womask_1005; // @[RegisterRouter.scala:87:24] wire out_rimask_1006 = \|_out_rimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_wimask_1006 = &_out_wimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_romask_1006 = \|_out_romask_T_1006; // @[RegisterRouter.scala:87:24] wire out_womask_1006 = &_out_womask_T_1006; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1006 = out_rivalid_1_860 & out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9779 = out_f_rivalid_1006; // @[RegisterRouter.scala:87:24] wire out_f_roready_1006 = out_roready_1_860 & out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9780 = out_f_roready_1006; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1006 = out_wivalid_1_860 & out_wimask_1006; // @[RegisterRouter.scala:87:24] wire out_f_woready_1006 = out_woready_1_860 & out_womask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9781 = ~out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9782 = ~out_wimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9783 = ~out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9784 = ~out_womask_1006; // @[RegisterRouter.scala:87:24] wire out_rimask_1007 = \|_out_rimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_wimask_1007 = &_out_wimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_romask_1007 = \|_out_romask_T_1007; // @[RegisterRouter.scala:87:24] wire out_womask_1007 = &_out_womask_T_1007; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1007 = out_rivalid_1_861 & out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9788 = out_f_rivalid_1007; // @[RegisterRouter.scala:87:24] wire out_f_roready_1007 = out_roready_1_861 & out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9789 = out_f_roready_1007; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1007 = out_wivalid_1_861 & out_wimask_1007; // @[RegisterRouter.scala:87:24] wire out_f_woready_1007 = out_woready_1_861 & out_womask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9790 = ~out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9791 = ~out_wimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9792 = ~out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9793 = ~out_womask_1007; // @[RegisterRouter.scala:87:24] wire out_rimask_1008 = \|_out_rimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_wimask_1008 = &_out_wimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_romask_1008 = \|_out_romask_T_1008; // @[RegisterRouter.scala:87:24] wire out_womask_1008 = &_out_womask_T_1008; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1008 = out_rivalid_1_862 & out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9797 = out_f_rivalid_1008; // @[RegisterRouter.scala:87:24] wire out_f_roready_1008 = out_roready_1_862 & out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9798 = out_f_roready_1008; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1008 = out_wivalid_1_862 & out_wimask_1008; // @[RegisterRouter.scala:87:24] wire out_f_woready_1008 = out_woready_1_862 & out_womask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9799 = ~out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9800 = ~out_wimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9801 = ~out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9802 = ~out_womask_1008; // @[RegisterRouter.scala:87:24] wire out_rimask_1009 = \|_out_rimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_wimask_1009 = &_out_wimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_romask_1009 = \|_out_romask_T_1009; // @[RegisterRouter.scala:87:24] wire out_womask_1009 = &_out_womask_T_1009; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1009 = out_rivalid_1_863 & out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9806 = out_f_rivalid_1009; // @[RegisterRouter.scala:87:24] wire out_f_roready_1009 = out_roready_1_863 & out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9807 = out_f_roready_1009; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1009 = out_wivalid_1_863 & out_wimask_1009; // @[RegisterRouter.scala:87:24] wire out_f_woready_1009 = out_woready_1_863 & out_womask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9808 = ~out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9809 = ~out_wimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9810 = ~out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9811 = ~out_womask_1009; // @[RegisterRouter.scala:87:24] wire out_rimask_1010 = \|_out_rimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_wimask_1010 = &_out_wimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_romask_1010 = \|_out_romask_T_1010; // @[RegisterRouter.scala:87:24] wire out_womask_1010 = &_out_womask_T_1010; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1010 = out_rivalid_1_864 & out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9815 = out_f_rivalid_1010; // @[RegisterRouter.scala:87:24] wire out_f_roready_1010 = out_roready_1_864 & out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9816 = out_f_roready_1010; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1010 = out_wivalid_1_864 & out_wimask_1010; // @[RegisterRouter.scala:87:24] wire out_f_woready_1010 = out_woready_1_864 & out_womask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9817 = ~out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9818 = ~out_wimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9819 = ~out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9820 = ~out_womask_1010; // @[RegisterRouter.scala:87:24] wire out_rimask_1011 = \|_out_rimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_wimask_1011 = &_out_wimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_romask_1011 = \|_out_romask_T_1011; // @[RegisterRouter.scala:87:24] wire out_womask_1011 = &_out_womask_T_1011; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1011 = out_rivalid_1_865 & out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9824 = out_f_rivalid_1011; // @[RegisterRouter.scala:87:24] wire out_f_roready_1011 = out_roready_1_865 & out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9825 = out_f_roready_1011; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1011 = out_wivalid_1_865 & out_wimask_1011; // @[RegisterRouter.scala:87:24] wire out_f_woready_1011 = out_woready_1_865 & out_womask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9826 = ~out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9827 = ~out_wimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9828 = ~out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9829 = ~out_womask_1011; // @[RegisterRouter.scala:87:24] wire out_rimask_1012 = \|_out_rimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_wimask_1012 = &_out_wimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_romask_1012 = \|_out_romask_T_1012; // @[RegisterRouter.scala:87:24] wire out_womask_1012 = &_out_womask_T_1012; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1012 = out_rivalid_1_866 & out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9833 = out_f_rivalid_1012; // @[RegisterRouter.scala:87:24] wire out_f_roready_1012 = out_roready_1_866 & out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9834 = out_f_roready_1012; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1012 = out_wivalid_1_866 & out_wimask_1012; // @[RegisterRouter.scala:87:24] wire out_f_woready_1012 = out_woready_1_866 & out_womask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9835 = ~out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9836 = ~out_wimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9837 = ~out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9838 = ~out_womask_1012; // @[RegisterRouter.scala:87:24] wire out_rimask_1013 = \|_out_rimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_wimask_1013 = &_out_wimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_romask_1013 = \|_out_romask_T_1013; // @[RegisterRouter.scala:87:24] wire out_womask_1013 = &_out_womask_T_1013; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1013 = out_rivalid_1_867 & out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9842 = out_f_rivalid_1013; // @[RegisterRouter.scala:87:24] wire out_f_roready_1013 = out_roready_1_867 & out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9843 = out_f_roready_1013; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1013 = out_wivalid_1_867 & out_wimask_1013; // @[RegisterRouter.scala:87:24] wire out_f_woready_1013 = out_woready_1_867 & out_womask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9844 = ~out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9845 = ~out_wimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9846 = ~out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9847 = ~out_womask_1013; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9849 = _out_T_9848; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_867 = _out_T_9849; // @[RegisterRouter.scala:87:24] wire out_rimask_1014 = \|_out_rimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_wimask_1014 = &_out_wimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_romask_1014 = \|_out_romask_T_1014; // @[RegisterRouter.scala:87:24] wire out_womask_1014 = &_out_womask_T_1014; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1014 = out_rivalid_1_868 & out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9851 = out_f_rivalid_1014; // @[RegisterRouter.scala:87:24] wire out_f_roready_1014 = out_roready_1_868 & out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9852 = out_f_roready_1014; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1014 = out_wivalid_1_868 & out_wimask_1014; // @[RegisterRouter.scala:87:24] wire out_f_woready_1014 = out_woready_1_868 & out_womask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9853 = ~out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9854 = ~out_wimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9855 = ~out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9856 = ~out_womask_1014; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_867 = {hi_570, flags_0_go, _out_prepend_T_867}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9857 = out_prepend_867; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9858 = _out_T_9857; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_868 = _out_T_9858; // @[RegisterRouter.scala:87:24] wire out_rimask_1015 = \|_out_rimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_wimask_1015 = &_out_wimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_romask_1015 = \|_out_romask_T_1015; // @[RegisterRouter.scala:87:24] wire out_womask_1015 = &_out_womask_T_1015; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1015 = out_rivalid_1_869 & out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9860 = out_f_rivalid_1015; // @[RegisterRouter.scala:87:24] wire out_f_roready_1015 = out_roready_1_869 & out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9861 = out_f_roready_1015; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1015 = out_wivalid_1_869 & out_wimask_1015; // @[RegisterRouter.scala:87:24] wire out_f_woready_1015 = out_woready_1_869 & out_womask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9862 = ~out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9863 = ~out_wimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9864 = ~out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9865 = ~out_womask_1015; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_868 = {hi_571, flags_0_go, _out_prepend_T_868}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9866 = out_prepend_868; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9867 = _out_T_9866; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_869 = _out_T_9867; // @[RegisterRouter.scala:87:24] wire out_rimask_1016 = \|_out_rimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_wimask_1016 = &_out_wimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_romask_1016 = \|_out_romask_T_1016; // @[RegisterRouter.scala:87:24] wire out_womask_1016 = &_out_womask_T_1016; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1016 = out_rivalid_1_870 & out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9869 = out_f_rivalid_1016; // @[RegisterRouter.scala:87:24] wire out_f_roready_1016 = out_roready_1_870 & out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9870 = out_f_roready_1016; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1016 = out_wivalid_1_870 & out_wimask_1016; // @[RegisterRouter.scala:87:24] wire out_f_woready_1016 = out_woready_1_870 & out_womask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9871 = ~out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9872 = ~out_wimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9873 = ~out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9874 = ~out_womask_1016; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_869 = {hi_572, flags_0_go, _out_prepend_T_869}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9875 = out_prepend_869; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9876 = _out_T_9875; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_870 = _out_T_9876; // @[RegisterRouter.scala:87:24] wire out_rimask_1017 = \|_out_rimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_wimask_1017 = &_out_wimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_romask_1017 = \|_out_romask_T_1017; // @[RegisterRouter.scala:87:24] wire out_womask_1017 = &_out_womask_T_1017; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1017 = out_rivalid_1_871 & out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9878 = out_f_rivalid_1017; // @[RegisterRouter.scala:87:24] wire out_f_roready_1017 = out_roready_1_871 & out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9879 = out_f_roready_1017; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1017 = out_wivalid_1_871 & out_wimask_1017; // @[RegisterRouter.scala:87:24] wire out_f_woready_1017 = out_woready_1_871 & out_womask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9880 = ~out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9881 = ~out_wimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9882 = ~out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9883 = ~out_womask_1017; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_870 = {hi_573, flags_0_go, _out_prepend_T_870}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9884 = out_prepend_870; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9885 = _out_T_9884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_871 = _out_T_9885; // @[RegisterRouter.scala:87:24] wire out_rimask_1018 = \|_out_rimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_wimask_1018 = &_out_wimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_romask_1018 = \|_out_romask_T_1018; // @[RegisterRouter.scala:87:24] wire out_womask_1018 = &_out_womask_T_1018; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1018 = out_rivalid_1_872 & out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9887 = out_f_rivalid_1018; // @[RegisterRouter.scala:87:24] wire out_f_roready_1018 = out_roready_1_872 & out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9888 = out_f_roready_1018; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1018 = out_wivalid_1_872 & out_wimask_1018; // @[RegisterRouter.scala:87:24] wire out_f_woready_1018 = out_woready_1_872 & out_womask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9889 = ~out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9890 = ~out_wimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9891 = ~out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9892 = ~out_womask_1018; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_871 = {hi_574, flags_0_go, _out_prepend_T_871}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9893 = out_prepend_871; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9894 = _out_T_9893; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_872 = _out_T_9894; // @[RegisterRouter.scala:87:24] wire out_rimask_1019 = \|_out_rimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_wimask_1019 = &_out_wimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_romask_1019 = \|_out_romask_T_1019; // @[RegisterRouter.scala:87:24] wire out_womask_1019 = &_out_womask_T_1019; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1019 = out_rivalid_1_873 & out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9896 = out_f_rivalid_1019; // @[RegisterRouter.scala:87:24] wire out_f_roready_1019 = out_roready_1_873 & out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9897 = out_f_roready_1019; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1019 = out_wivalid_1_873 & out_wimask_1019; // @[RegisterRouter.scala:87:24] wire out_f_woready_1019 = out_woready_1_873 & out_womask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9898 = ~out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9899 = ~out_wimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9900 = ~out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9901 = ~out_womask_1019; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_872 = {hi_575, flags_0_go, _out_prepend_T_872}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9902 = out_prepend_872; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9903 = _out_T_9902; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_873 = _out_T_9903; // @[RegisterRouter.scala:87:24] wire out_rimask_1020 = \|_out_rimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_wimask_1020 = &_out_wimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_romask_1020 = \|_out_romask_T_1020; // @[RegisterRouter.scala:87:24] wire out_womask_1020 = &_out_womask_T_1020; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1020 = out_rivalid_1_874 & out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9905 = out_f_rivalid_1020; // @[RegisterRouter.scala:87:24] wire out_f_roready_1020 = out_roready_1_874 & out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9906 = out_f_roready_1020; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1020 = out_wivalid_1_874 & out_wimask_1020; // @[RegisterRouter.scala:87:24] wire out_f_woready_1020 = out_woready_1_874 & out_womask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9907 = ~out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9908 = ~out_wimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9909 = ~out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9910 = ~out_womask_1020; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_873 = {hi_576, flags_0_go, _out_prepend_T_873}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9911 = out_prepend_873; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9912 = _out_T_9911; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_199 = _out_T_9912; // @[MuxLiteral.scala:49:48] wire out_rimask_1021 = \|_out_rimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_wimask_1021 = &_out_wimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_romask_1021 = \|_out_romask_T_1021; // @[RegisterRouter.scala:87:24] wire out_womask_1021 = &_out_womask_T_1021; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1021 = out_rivalid_1_875 & out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9914 = out_f_rivalid_1021; // @[RegisterRouter.scala:87:24] wire out_f_roready_1021 = out_roready_1_875 & out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9915 = out_f_roready_1021; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1021 = out_wivalid_1_875 & out_wimask_1021; // @[RegisterRouter.scala:87:24] wire out_f_woready_1021 = out_woready_1_875 & out_womask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9916 = ~out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9917 = ~out_wimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9918 = ~out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9919 = ~out_womask_1021; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9921 = _out_T_9920; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_874 = _out_T_9921; // @[RegisterRouter.scala:87:24] wire out_rimask_1022 = \|_out_rimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_wimask_1022 = &_out_wimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_romask_1022 = \|_out_romask_T_1022; // @[RegisterRouter.scala:87:24] wire out_womask_1022 = &_out_womask_T_1022; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1022 = out_rivalid_1_876 & out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9923 = out_f_rivalid_1022; // @[RegisterRouter.scala:87:24] wire out_f_roready_1022 = out_roready_1_876 & out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9924 = out_f_roready_1022; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1022 = out_wivalid_1_876 & out_wimask_1022; // @[RegisterRouter.scala:87:24] wire out_f_woready_1022 = out_woready_1_876 & out_womask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9925 = ~out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9926 = ~out_wimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9927 = ~out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9928 = ~out_womask_1022; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_874 = {hi_394, flags_0_go, _out_prepend_T_874}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9929 = out_prepend_874; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9930 = _out_T_9929; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_875 = _out_T_9930; // @[RegisterRouter.scala:87:24] wire out_rimask_1023 = \|_out_rimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_wimask_1023 = &_out_wimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_romask_1023 = \|_out_romask_T_1023; // @[RegisterRouter.scala:87:24] wire out_womask_1023 = &_out_womask_T_1023; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1023 = out_rivalid_1_877 & out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9932 = out_f_rivalid_1023; // @[RegisterRouter.scala:87:24] wire out_f_roready_1023 = out_roready_1_877 & out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9933 = out_f_roready_1023; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1023 = out_wivalid_1_877 & out_wimask_1023; // @[RegisterRouter.scala:87:24] wire out_f_woready_1023 = out_woready_1_877 & out_womask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9934 = ~out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9935 = ~out_wimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9936 = ~out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9937 = ~out_womask_1023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_875 = {hi_395, flags_0_go, _out_prepend_T_875}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9938 = out_prepend_875; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9939 = _out_T_9938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_876 = _out_T_9939; // @[RegisterRouter.scala:87:24] wire out_rimask_1024 = \|_out_rimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_wimask_1024 = &_out_wimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_romask_1024 = \|_out_romask_T_1024; // @[RegisterRouter.scala:87:24] wire out_womask_1024 = &_out_womask_T_1024; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1024 = out_rivalid_1_878 & out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9941 = out_f_rivalid_1024; // @[RegisterRouter.scala:87:24] wire out_f_roready_1024 = out_roready_1_878 & out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9942 = out_f_roready_1024; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1024 = out_wivalid_1_878 & out_wimask_1024; // @[RegisterRouter.scala:87:24] wire out_f_woready_1024 = out_woready_1_878 & out_womask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9943 = ~out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9944 = ~out_wimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9945 = ~out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9946 = ~out_womask_1024; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_876 = {hi_396, flags_0_go, _out_prepend_T_876}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9947 = out_prepend_876; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9948 = _out_T_9947; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_877 = _out_T_9948; // @[RegisterRouter.scala:87:24] wire out_rimask_1025 = \|_out_rimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_wimask_1025 = &_out_wimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_romask_1025 = \|_out_romask_T_1025; // @[RegisterRouter.scala:87:24] wire out_womask_1025 = &_out_womask_T_1025; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1025 = out_rivalid_1_879 & out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9950 = out_f_rivalid_1025; // @[RegisterRouter.scala:87:24] wire out_f_roready_1025 = out_roready_1_879 & out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9951 = out_f_roready_1025; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1025 = out_wivalid_1_879 & out_wimask_1025; // @[RegisterRouter.scala:87:24] wire out_f_woready_1025 = out_woready_1_879 & out_womask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9952 = ~out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9953 = ~out_wimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9954 = ~out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9955 = ~out_womask_1025; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_877 = {hi_397, flags_0_go, _out_prepend_T_877}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9956 = out_prepend_877; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9957 = _out_T_9956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_878 = _out_T_9957; // @[RegisterRouter.scala:87:24] wire out_rimask_1026 = \|_out_rimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_wimask_1026 = &_out_wimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_romask_1026 = \|_out_romask_T_1026; // @[RegisterRouter.scala:87:24] wire out_womask_1026 = &_out_womask_T_1026; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1026 = out_rivalid_1_880 & out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9959 = out_f_rivalid_1026; // @[RegisterRouter.scala:87:24] wire out_f_roready_1026 = out_roready_1_880 & out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9960 = out_f_roready_1026; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1026 = out_wivalid_1_880 & out_wimask_1026; // @[RegisterRouter.scala:87:24] wire out_f_woready_1026 = out_woready_1_880 & out_womask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9961 = ~out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9962 = ~out_wimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9963 = ~out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9964 = ~out_womask_1026; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_878 = {hi_398, flags_0_go, _out_prepend_T_878}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9965 = out_prepend_878; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9966 = _out_T_9965; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_879 = _out_T_9966; // @[RegisterRouter.scala:87:24] wire out_rimask_1027 = \|_out_rimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_wimask_1027 = &_out_wimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_romask_1027 = \|_out_romask_T_1027; // @[RegisterRouter.scala:87:24] wire out_womask_1027 = &_out_womask_T_1027; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1027 = out_rivalid_1_881 & out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9968 = out_f_rivalid_1027; // @[RegisterRouter.scala:87:24] wire out_f_roready_1027 = out_roready_1_881 & out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9969 = out_f_roready_1027; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1027 = out_wivalid_1_881 & out_wimask_1027; // @[RegisterRouter.scala:87:24] wire out_f_woready_1027 = out_woready_1_881 & out_womask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9970 = ~out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9971 = ~out_wimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9972 = ~out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9973 = ~out_womask_1027; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_879 = {hi_399, flags_0_go, _out_prepend_T_879}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9974 = out_prepend_879; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9975 = _out_T_9974; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_880 = _out_T_9975; // @[RegisterRouter.scala:87:24] wire out_rimask_1028 = \|_out_rimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_wimask_1028 = &_out_wimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_romask_1028 = \|_out_romask_T_1028; // @[RegisterRouter.scala:87:24] wire out_womask_1028 = &_out_womask_T_1028; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1028 = out_rivalid_1_882 & out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9977 = out_f_rivalid_1028; // @[RegisterRouter.scala:87:24] wire out_f_roready_1028 = out_roready_1_882 & out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9978 = out_f_roready_1028; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1028 = out_wivalid_1_882 & out_wimask_1028; // @[RegisterRouter.scala:87:24] wire out_f_woready_1028 = out_woready_1_882 & out_womask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9979 = ~out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9980 = ~out_wimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9981 = ~out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9982 = ~out_womask_1028; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_880 = {hi_400, flags_0_go, _out_prepend_T_880}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9983 = out_prepend_880; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9984 = _out_T_9983; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_177 = _out_T_9984; // @[MuxLiteral.scala:49:48] wire out_rimask_1029 = \|_out_rimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_wimask_1029 = &_out_wimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_romask_1029 = \|_out_romask_T_1029; // @[RegisterRouter.scala:87:24] wire out_womask_1029 = &_out_womask_T_1029; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1029 = out_rivalid_1_883 & out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9986 = out_f_rivalid_1029; // @[RegisterRouter.scala:87:24] wire out_f_roready_1029 = out_roready_1_883 & out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9987 = out_f_roready_1029; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1029 = out_wivalid_1_883 & out_wimask_1029; // @[RegisterRouter.scala:87:24] wire out_f_woready_1029 = out_woready_1_883 & out_womask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9988 = ~out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9989 = ~out_wimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9990 = ~out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9991 = ~out_womask_1029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9993 = _out_T_9992; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_881 = _out_T_9993; // @[RegisterRouter.scala:87:24] wire out_rimask_1030 = \|_out_rimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_wimask_1030 = &_out_wimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_romask_1030 = \|_out_romask_T_1030; // @[RegisterRouter.scala:87:24] wire out_womask_1030 = &_out_womask_T_1030; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1030 = out_rivalid_1_884 & out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9995 = out_f_rivalid_1030; // @[RegisterRouter.scala:87:24] wire out_f_roready_1030 = out_roready_1_884 & out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9996 = out_f_roready_1030; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1030 = out_wivalid_1_884 & out_wimask_1030; // @[RegisterRouter.scala:87:24] wire out_f_woready_1030 = out_woready_1_884 & out_womask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9997 = ~out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9998 = ~out_wimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9999 = ~out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_10000 = ~out_womask_1030; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_881 = {hi_434, flags_0_go, _out_prepend_T_881}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10001 = out_prepend_881; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10002 = _out_T_10001; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_882 = _out_T_10002; // @[RegisterRouter.scala:87:24] wire out_rimask_1031 = \|_out_rimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_wimask_1031 = &_out_wimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_romask_1031 = \|_out_romask_T_1031; // @[RegisterRouter.scala:87:24] wire out_womask_1031 = &_out_womask_T_1031; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1031 = out_rivalid_1_885 & out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10004 = out_f_rivalid_1031; // @[RegisterRouter.scala:87:24] wire out_f_roready_1031 = out_roready_1_885 & out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10005 = out_f_roready_1031; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1031 = out_wivalid_1_885 & out_wimask_1031; // @[RegisterRouter.scala:87:24] wire out_f_woready_1031 = out_woready_1_885 & out_womask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10006 = ~out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10007 = ~out_wimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10008 = ~out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10009 = ~out_womask_1031; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_882 = {hi_435, flags_0_go, _out_prepend_T_882}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10010 = out_prepend_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10011 = _out_T_10010; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_883 = _out_T_10011; // @[RegisterRouter.scala:87:24] wire out_rimask_1032 = \|_out_rimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_wimask_1032 = &_out_wimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_romask_1032 = \|_out_romask_T_1032; // @[RegisterRouter.scala:87:24] wire out_womask_1032 = &_out_womask_T_1032; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1032 = out_rivalid_1_886 & out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10013 = out_f_rivalid_1032; // @[RegisterRouter.scala:87:24] wire out_f_roready_1032 = out_roready_1_886 & out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10014 = out_f_roready_1032; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1032 = out_wivalid_1_886 & out_wimask_1032; // @[RegisterRouter.scala:87:24] wire out_f_woready_1032 = out_woready_1_886 & out_womask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10015 = ~out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10016 = ~out_wimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10017 = ~out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10018 = ~out_womask_1032; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_883 = {hi_436, flags_0_go, _out_prepend_T_883}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10019 = out_prepend_883; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10020 = _out_T_10019; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_884 = _out_T_10020; // @[RegisterRouter.scala:87:24] wire out_rimask_1033 = \|_out_rimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_wimask_1033 = &_out_wimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_romask_1033 = \|_out_romask_T_1033; // @[RegisterRouter.scala:87:24] wire out_womask_1033 = &_out_womask_T_1033; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1033 = out_rivalid_1_887 & out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10022 = out_f_rivalid_1033; // @[RegisterRouter.scala:87:24] wire out_f_roready_1033 = out_roready_1_887 & out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10023 = out_f_roready_1033; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1033 = out_wivalid_1_887 & out_wimask_1033; // @[RegisterRouter.scala:87:24] wire out_f_woready_1033 = out_woready_1_887 & out_womask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10024 = ~out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10025 = ~out_wimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10026 = ~out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10027 = ~out_womask_1033; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_884 = {hi_437, flags_0_go, _out_prepend_T_884}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10028 = out_prepend_884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10029 = _out_T_10028; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_885 = _out_T_10029; // @[RegisterRouter.scala:87:24] wire out_rimask_1034 = \|_out_rimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_wimask_1034 = &_out_wimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_romask_1034 = \|_out_romask_T_1034; // @[RegisterRouter.scala:87:24] wire out_womask_1034 = &_out_womask_T_1034; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1034 = out_rivalid_1_888 & out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10031 = out_f_rivalid_1034; // @[RegisterRouter.scala:87:24] wire out_f_roready_1034 = out_roready_1_888 & out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10032 = out_f_roready_1034; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1034 = out_wivalid_1_888 & out_wimask_1034; // @[RegisterRouter.scala:87:24] wire out_f_woready_1034 = out_woready_1_888 & out_womask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10033 = ~out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10034 = ~out_wimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10035 = ~out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10036 = ~out_womask_1034; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_885 = {hi_438, flags_0_go, _out_prepend_T_885}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10037 = out_prepend_885; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10038 = _out_T_10037; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_886 = _out_T_10038; // @[RegisterRouter.scala:87:24] wire out_rimask_1035 = \|_out_rimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_wimask_1035 = &_out_wimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_romask_1035 = \|_out_romask_T_1035; // @[RegisterRouter.scala:87:24] wire out_womask_1035 = &_out_womask_T_1035; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1035 = out_rivalid_1_889 & out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10040 = out_f_rivalid_1035; // @[RegisterRouter.scala:87:24] wire out_f_roready_1035 = out_roready_1_889 & out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10041 = out_f_roready_1035; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1035 = out_wivalid_1_889 & out_wimask_1035; // @[RegisterRouter.scala:87:24] wire out_f_woready_1035 = out_woready_1_889 & out_womask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10042 = ~out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10043 = ~out_wimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10044 = ~out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10045 = ~out_womask_1035; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_886 = {hi_439, flags_0_go, _out_prepend_T_886}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10046 = out_prepend_886; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10047 = _out_T_10046; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_887 = _out_T_10047; // @[RegisterRouter.scala:87:24] wire out_rimask_1036 = \|_out_rimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_wimask_1036 = &_out_wimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_romask_1036 = \|_out_romask_T_1036; // @[RegisterRouter.scala:87:24] wire out_womask_1036 = &_out_womask_T_1036; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1036 = out_rivalid_1_890 & out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10049 = out_f_rivalid_1036; // @[RegisterRouter.scala:87:24] wire out_f_roready_1036 = out_roready_1_890 & out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10050 = out_f_roready_1036; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1036 = out_wivalid_1_890 & out_wimask_1036; // @[RegisterRouter.scala:87:24] wire out_f_woready_1036 = out_woready_1_890 & out_womask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10051 = ~out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10052 = ~out_wimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10053 = ~out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10054 = ~out_womask_1036; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_887 = {hi_440, flags_0_go, _out_prepend_T_887}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10055 = out_prepend_887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10056 = _out_T_10055; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_182 = _out_T_10056; // @[MuxLiteral.scala:49:48] wire out_rimask_1037 = \|_out_rimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_wimask_1037 = &_out_wimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_romask_1037 = \|_out_romask_T_1037; // @[RegisterRouter.scala:87:24] wire out_womask_1037 = &_out_womask_T_1037; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1037 = out_rivalid_1_891 & out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10058 = out_f_rivalid_1037; // @[RegisterRouter.scala:87:24] wire out_f_roready_1037 = out_roready_1_891 & out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10059 = out_f_roready_1037; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1037 = out_wivalid_1_891 & out_wimask_1037; // @[RegisterRouter.scala:87:24] wire out_f_woready_1037 = out_woready_1_891 & out_womask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10060 = ~out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10061 = ~out_wimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10062 = ~out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10063 = ~out_womask_1037; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10065 = _out_T_10064; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_888 = _out_T_10065; // @[RegisterRouter.scala:87:24] wire out_rimask_1038 = \|_out_rimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_wimask_1038 = &_out_wimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_romask_1038 = \|_out_romask_T_1038; // @[RegisterRouter.scala:87:24] wire out_womask_1038 = &_out_womask_T_1038; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1038 = out_rivalid_1_892 & out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10067 = out_f_rivalid_1038; // @[RegisterRouter.scala:87:24] wire out_f_roready_1038 = out_roready_1_892 & out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10068 = out_f_roready_1038; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1038 = out_wivalid_1_892 & out_wimask_1038; // @[RegisterRouter.scala:87:24] wire out_f_woready_1038 = out_woready_1_892 & out_womask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10069 = ~out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10070 = ~out_wimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10071 = ~out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10072 = ~out_womask_1038; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_888 = {hi_210, flags_0_go, _out_prepend_T_888}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10073 = out_prepend_888; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10074 = _out_T_10073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_889 = _out_T_10074; // @[RegisterRouter.scala:87:24] wire out_rimask_1039 = \|_out_rimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_wimask_1039 = &_out_wimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_romask_1039 = \|_out_romask_T_1039; // @[RegisterRouter.scala:87:24] wire out_womask_1039 = &_out_womask_T_1039; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1039 = out_rivalid_1_893 & out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10076 = out_f_rivalid_1039; // @[RegisterRouter.scala:87:24] wire out_f_roready_1039 = out_roready_1_893 & out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10077 = out_f_roready_1039; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1039 = out_wivalid_1_893 & out_wimask_1039; // @[RegisterRouter.scala:87:24] wire out_f_woready_1039 = out_woready_1_893 & out_womask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10078 = ~out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10079 = ~out_wimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10080 = ~out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10081 = ~out_womask_1039; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_889 = {hi_211, flags_0_go, _out_prepend_T_889}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10082 = out_prepend_889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10083 = _out_T_10082; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_890 = _out_T_10083; // @[RegisterRouter.scala:87:24] wire out_rimask_1040 = \|_out_rimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_wimask_1040 = &_out_wimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_romask_1040 = \|_out_romask_T_1040; // @[RegisterRouter.scala:87:24] wire out_womask_1040 = &_out_womask_T_1040; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1040 = out_rivalid_1_894 & out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10085 = out_f_rivalid_1040; // @[RegisterRouter.scala:87:24] wire out_f_roready_1040 = out_roready_1_894 & out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10086 = out_f_roready_1040; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1040 = out_wivalid_1_894 & out_wimask_1040; // @[RegisterRouter.scala:87:24] wire out_f_woready_1040 = out_woready_1_894 & out_womask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10087 = ~out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10088 = ~out_wimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10089 = ~out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10090 = ~out_womask_1040; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_890 = {hi_212, flags_0_go, _out_prepend_T_890}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10091 = out_prepend_890; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10092 = _out_T_10091; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_891 = _out_T_10092; // @[RegisterRouter.scala:87:24] wire out_rimask_1041 = \|_out_rimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_wimask_1041 = &_out_wimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_romask_1041 = \|_out_romask_T_1041; // @[RegisterRouter.scala:87:24] wire out_womask_1041 = &_out_womask_T_1041; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1041 = out_rivalid_1_895 & out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10094 = out_f_rivalid_1041; // @[RegisterRouter.scala:87:24] wire out_f_roready_1041 = out_roready_1_895 & out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10095 = out_f_roready_1041; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1041 = out_wivalid_1_895 & out_wimask_1041; // @[RegisterRouter.scala:87:24] wire out_f_woready_1041 = out_woready_1_895 & out_womask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10096 = ~out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10097 = ~out_wimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10098 = ~out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10099 = ~out_womask_1041; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_891 = {hi_213, flags_0_go, _out_prepend_T_891}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10100 = out_prepend_891; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10101 = _out_T_10100; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_892 = _out_T_10101; // @[RegisterRouter.scala:87:24] wire out_rimask_1042 = \|_out_rimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_wimask_1042 = &_out_wimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_romask_1042 = \|_out_romask_T_1042; // @[RegisterRouter.scala:87:24] wire out_womask_1042 = &_out_womask_T_1042; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1042 = out_rivalid_1_896 & out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10103 = out_f_rivalid_1042; // @[RegisterRouter.scala:87:24] wire out_f_roready_1042 = out_roready_1_896 & out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10104 = out_f_roready_1042; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1042 = out_wivalid_1_896 & out_wimask_1042; // @[RegisterRouter.scala:87:24] wire out_f_woready_1042 = out_woready_1_896 & out_womask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10105 = ~out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10106 = ~out_wimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10107 = ~out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10108 = ~out_womask_1042; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_892 = {hi_214, flags_0_go, _out_prepend_T_892}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10109 = out_prepend_892; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10110 = _out_T_10109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_893 = _out_T_10110; // @[RegisterRouter.scala:87:24] wire out_rimask_1043 = \|_out_rimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_wimask_1043 = &_out_wimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_romask_1043 = \|_out_romask_T_1043; // @[RegisterRouter.scala:87:24] wire out_womask_1043 = &_out_womask_T_1043; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1043 = out_rivalid_1_897 & out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10112 = out_f_rivalid_1043; // @[RegisterRouter.scala:87:24] wire out_f_roready_1043 = out_roready_1_897 & out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10113 = out_f_roready_1043; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1043 = out_wivalid_1_897 & out_wimask_1043; // @[RegisterRouter.scala:87:24] wire out_f_woready_1043 = out_woready_1_897 & out_womask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10114 = ~out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10115 = ~out_wimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10116 = ~out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10117 = ~out_womask_1043; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_893 = {hi_215, flags_0_go, _out_prepend_T_893}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10118 = out_prepend_893; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10119 = _out_T_10118; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_894 = _out_T_10119; // @[RegisterRouter.scala:87:24] wire out_rimask_1044 = \|_out_rimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_wimask_1044 = &_out_wimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_romask_1044 = \|_out_romask_T_1044; // @[RegisterRouter.scala:87:24] wire out_womask_1044 = &_out_womask_T_1044; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1044 = out_rivalid_1_898 & out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10121 = out_f_rivalid_1044; // @[RegisterRouter.scala:87:24] wire out_f_roready_1044 = out_roready_1_898 & out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10122 = out_f_roready_1044; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1044 = out_wivalid_1_898 & out_wimask_1044; // @[RegisterRouter.scala:87:24] wire out_f_woready_1044 = out_woready_1_898 & out_womask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10123 = ~out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10124 = ~out_wimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10125 = ~out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10126 = ~out_womask_1044; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_894 = {hi_216, flags_0_go, _out_prepend_T_894}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10127 = out_prepend_894; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10128 = _out_T_10127; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_154 = _out_T_10128; // @[MuxLiteral.scala:49:48] wire out_rimask_1045 = \|_out_rimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_wimask_1045 = &_out_wimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_romask_1045 = \|_out_romask_T_1045; // @[RegisterRouter.scala:87:24] wire out_womask_1045 = &_out_womask_T_1045; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1045 = out_rivalid_1_899 & out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10130 = out_f_rivalid_1045; // @[RegisterRouter.scala:87:24] wire out_f_roready_1045 = out_roready_1_899 & out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10131 = out_f_roready_1045; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1045 = out_wivalid_1_899 & out_wimask_1045; // @[RegisterRouter.scala:87:24] wire out_f_woready_1045 = out_woready_1_899 & out_womask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10132 = ~out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10133 = ~out_wimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10134 = ~out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10135 = ~out_womask_1045; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10137 = _out_T_10136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_895 = _out_T_10137; // @[RegisterRouter.scala:87:24] wire out_rimask_1046 = \|_out_rimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_wimask_1046 = &_out_wimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_romask_1046 = \|_out_romask_T_1046; // @[RegisterRouter.scala:87:24] wire out_womask_1046 = &_out_womask_T_1046; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1046 = out_rivalid_1_900 & out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10139 = out_f_rivalid_1046; // @[RegisterRouter.scala:87:24] wire out_f_roready_1046 = out_roready_1_900 & out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10140 = out_f_roready_1046; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1046 = out_wivalid_1_900 & out_wimask_1046; // @[RegisterRouter.scala:87:24] wire out_f_woready_1046 = out_woready_1_900 & out_womask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10141 = ~out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10142 = ~out_wimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10143 = ~out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10144 = ~out_womask_1046; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_895 = {hi_378, flags_0_go, _out_prepend_T_895}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10145 = out_prepend_895; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10146 = _out_T_10145; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_896 = _out_T_10146; // @[RegisterRouter.scala:87:24] wire out_rimask_1047 = \|_out_rimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_wimask_1047 = &_out_wimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_romask_1047 = \|_out_romask_T_1047; // @[RegisterRouter.scala:87:24] wire out_womask_1047 = &_out_womask_T_1047; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1047 = out_rivalid_1_901 & out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10148 = out_f_rivalid_1047; // @[RegisterRouter.scala:87:24] wire out_f_roready_1047 = out_roready_1_901 & out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10149 = out_f_roready_1047; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1047 = out_wivalid_1_901 & out_wimask_1047; // @[RegisterRouter.scala:87:24] wire out_f_woready_1047 = out_woready_1_901 & out_womask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10150 = ~out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10151 = ~out_wimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10152 = ~out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10153 = ~out_womask_1047; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_896 = {hi_379, flags_0_go, _out_prepend_T_896}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10154 = out_prepend_896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10155 = _out_T_10154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_897 = _out_T_10155; // @[RegisterRouter.scala:87:24] wire out_rimask_1048 = \|_out_rimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_wimask_1048 = &_out_wimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_romask_1048 = \|_out_romask_T_1048; // @[RegisterRouter.scala:87:24] wire out_womask_1048 = &_out_womask_T_1048; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1048 = out_rivalid_1_902 & out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10157 = out_f_rivalid_1048; // @[RegisterRouter.scala:87:24] wire out_f_roready_1048 = out_roready_1_902 & out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10158 = out_f_roready_1048; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1048 = out_wivalid_1_902 & out_wimask_1048; // @[RegisterRouter.scala:87:24] wire out_f_woready_1048 = out_woready_1_902 & out_womask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10159 = ~out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10160 = ~out_wimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10161 = ~out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10162 = ~out_womask_1048; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_897 = {hi_380, flags_0_go, _out_prepend_T_897}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10163 = out_prepend_897; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10164 = _out_T_10163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_898 = _out_T_10164; // @[RegisterRouter.scala:87:24] wire out_rimask_1049 = \|_out_rimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_wimask_1049 = &_out_wimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_romask_1049 = \|_out_romask_T_1049; // @[RegisterRouter.scala:87:24] wire out_womask_1049 = &_out_womask_T_1049; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1049 = out_rivalid_1_903 & out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10166 = out_f_rivalid_1049; // @[RegisterRouter.scala:87:24] wire out_f_roready_1049 = out_roready_1_903 & out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10167 = out_f_roready_1049; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1049 = out_wivalid_1_903 & out_wimask_1049; // @[RegisterRouter.scala:87:24] wire out_f_woready_1049 = out_woready_1_903 & out_womask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10168 = ~out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10169 = ~out_wimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10170 = ~out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10171 = ~out_womask_1049; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_898 = {hi_381, flags_0_go, _out_prepend_T_898}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10172 = out_prepend_898; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10173 = _out_T_10172; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_899 = _out_T_10173; // @[RegisterRouter.scala:87:24] wire out_rimask_1050 = \|_out_rimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_wimask_1050 = &_out_wimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_romask_1050 = \|_out_romask_T_1050; // @[RegisterRouter.scala:87:24] wire out_womask_1050 = &_out_womask_T_1050; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1050 = out_rivalid_1_904 & out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10175 = out_f_rivalid_1050; // @[RegisterRouter.scala:87:24] wire out_f_roready_1050 = out_roready_1_904 & out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10176 = out_f_roready_1050; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1050 = out_wivalid_1_904 & out_wimask_1050; // @[RegisterRouter.scala:87:24] wire out_f_woready_1050 = out_woready_1_904 & out_womask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10177 = ~out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10178 = ~out_wimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10179 = ~out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10180 = ~out_womask_1050; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_899 = {hi_382, flags_0_go, _out_prepend_T_899}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10181 = out_prepend_899; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10182 = _out_T_10181; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_900 = _out_T_10182; // @[RegisterRouter.scala:87:24] wire out_rimask_1051 = \|_out_rimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_wimask_1051 = &_out_wimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_romask_1051 = \|_out_romask_T_1051; // @[RegisterRouter.scala:87:24] wire out_womask_1051 = &_out_womask_T_1051; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1051 = out_rivalid_1_905 & out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10184 = out_f_rivalid_1051; // @[RegisterRouter.scala:87:24] wire out_f_roready_1051 = out_roready_1_905 & out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10185 = out_f_roready_1051; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1051 = out_wivalid_1_905 & out_wimask_1051; // @[RegisterRouter.scala:87:24] wire out_f_woready_1051 = out_woready_1_905 & out_womask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10186 = ~out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10187 = ~out_wimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10188 = ~out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10189 = ~out_womask_1051; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_900 = {hi_383, flags_0_go, _out_prepend_T_900}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10190 = out_prepend_900; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10191 = _out_T_10190; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_901 = _out_T_10191; // @[RegisterRouter.scala:87:24] wire out_rimask_1052 = \|_out_rimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_wimask_1052 = &_out_wimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_romask_1052 = \|_out_romask_T_1052; // @[RegisterRouter.scala:87:24] wire out_womask_1052 = &_out_womask_T_1052; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1052 = out_rivalid_1_906 & out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10193 = out_f_rivalid_1052; // @[RegisterRouter.scala:87:24] wire out_f_roready_1052 = out_roready_1_906 & out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10194 = out_f_roready_1052; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1052 = out_wivalid_1_906 & out_wimask_1052; // @[RegisterRouter.scala:87:24] wire out_f_woready_1052 = out_woready_1_906 & out_womask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10195 = ~out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10196 = ~out_wimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10197 = ~out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10198 = ~out_womask_1052; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_901 = {hi_384, flags_0_go, _out_prepend_T_901}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10199 = out_prepend_901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10200 = _out_T_10199; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_175 = _out_T_10200; // @[MuxLiteral.scala:49:48] wire out_rimask_1053 = \|_out_rimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_wimask_1053 = &_out_wimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_romask_1053 = \|_out_romask_T_1053; // @[RegisterRouter.scala:87:24] wire out_womask_1053 = &_out_womask_T_1053; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1053 = out_rivalid_1_907 & out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10202 = out_f_rivalid_1053; // @[RegisterRouter.scala:87:24] wire out_f_roready_1053 = out_roready_1_907 & out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10203 = out_f_roready_1053; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1053 = out_wivalid_1_907 & out_wimask_1053; // @[RegisterRouter.scala:87:24] wire out_f_woready_1053 = out_woready_1_907 & out_womask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10204 = ~out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10205 = ~out_wimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10206 = ~out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10207 = ~out_womask_1053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10209 = _out_T_10208; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_902 = _out_T_10209; // @[RegisterRouter.scala:87:24] wire out_rimask_1054 = \|_out_rimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_wimask_1054 = &_out_wimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_romask_1054 = \|_out_romask_T_1054; // @[RegisterRouter.scala:87:24] wire out_womask_1054 = &_out_womask_T_1054; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1054 = out_rivalid_1_908 & out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10211 = out_f_rivalid_1054; // @[RegisterRouter.scala:87:24] wire out_f_roready_1054 = out_roready_1_908 & out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10212 = out_f_roready_1054; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1054 = out_wivalid_1_908 & out_wimask_1054; // @[RegisterRouter.scala:87:24] wire out_f_woready_1054 = out_woready_1_908 & out_womask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10213 = ~out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10214 = ~out_wimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10215 = ~out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10216 = ~out_womask_1054; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_902 = {hi_122, flags_0_go, _out_prepend_T_902}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10217 = out_prepend_902; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10218 = _out_T_10217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_903 = _out_T_10218; // @[RegisterRouter.scala:87:24] wire out_rimask_1055 = \|_out_rimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_wimask_1055 = &_out_wimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_romask_1055 = \|_out_romask_T_1055; // @[RegisterRouter.scala:87:24] wire out_womask_1055 = &_out_womask_T_1055; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1055 = out_rivalid_1_909 & out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10220 = out_f_rivalid_1055; // @[RegisterRouter.scala:87:24] wire out_f_roready_1055 = out_roready_1_909 & out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10221 = out_f_roready_1055; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1055 = out_wivalid_1_909 & out_wimask_1055; // @[RegisterRouter.scala:87:24] wire out_f_woready_1055 = out_woready_1_909 & out_womask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10222 = ~out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10223 = ~out_wimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10224 = ~out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10225 = ~out_womask_1055; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_903 = {hi_123, flags_0_go, _out_prepend_T_903}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10226 = out_prepend_903; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10227 = _out_T_10226; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_904 = _out_T_10227; // @[RegisterRouter.scala:87:24] wire out_rimask_1056 = \|_out_rimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_wimask_1056 = &_out_wimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_romask_1056 = \|_out_romask_T_1056; // @[RegisterRouter.scala:87:24] wire out_womask_1056 = &_out_womask_T_1056; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1056 = out_rivalid_1_910 & out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10229 = out_f_rivalid_1056; // @[RegisterRouter.scala:87:24] wire out_f_roready_1056 = out_roready_1_910 & out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10230 = out_f_roready_1056; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1056 = out_wivalid_1_910 & out_wimask_1056; // @[RegisterRouter.scala:87:24] wire out_f_woready_1056 = out_woready_1_910 & out_womask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10231 = ~out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10232 = ~out_wimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10233 = ~out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10234 = ~out_womask_1056; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_904 = {hi_124, flags_0_go, _out_prepend_T_904}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10235 = out_prepend_904; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10236 = _out_T_10235; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_905 = _out_T_10236; // @[RegisterRouter.scala:87:24] wire out_rimask_1057 = \|_out_rimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_wimask_1057 = &_out_wimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_romask_1057 = \|_out_romask_T_1057; // @[RegisterRouter.scala:87:24] wire out_womask_1057 = &_out_womask_T_1057; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1057 = out_rivalid_1_911 & out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10238 = out_f_rivalid_1057; // @[RegisterRouter.scala:87:24] wire out_f_roready_1057 = out_roready_1_911 & out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10239 = out_f_roready_1057; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1057 = out_wivalid_1_911 & out_wimask_1057; // @[RegisterRouter.scala:87:24] wire out_f_woready_1057 = out_woready_1_911 & out_womask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10240 = ~out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10241 = ~out_wimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10242 = ~out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10243 = ~out_womask_1057; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_905 = {hi_125, flags_0_go, _out_prepend_T_905}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10244 = out_prepend_905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10245 = _out_T_10244; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_906 = _out_T_10245; // @[RegisterRouter.scala:87:24] wire out_rimask_1058 = \|_out_rimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_wimask_1058 = &_out_wimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_romask_1058 = \|_out_romask_T_1058; // @[RegisterRouter.scala:87:24] wire out_womask_1058 = &_out_womask_T_1058; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1058 = out_rivalid_1_912 & out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10247 = out_f_rivalid_1058; // @[RegisterRouter.scala:87:24] wire out_f_roready_1058 = out_roready_1_912 & out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10248 = out_f_roready_1058; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1058 = out_wivalid_1_912 & out_wimask_1058; // @[RegisterRouter.scala:87:24] wire out_f_woready_1058 = out_woready_1_912 & out_womask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10249 = ~out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10250 = ~out_wimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10251 = ~out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10252 = ~out_womask_1058; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_906 = {hi_126, flags_0_go, _out_prepend_T_906}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10253 = out_prepend_906; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10254 = _out_T_10253; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_907 = _out_T_10254; // @[RegisterRouter.scala:87:24] wire out_rimask_1059 = \|_out_rimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_wimask_1059 = &_out_wimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_romask_1059 = \|_out_romask_T_1059; // @[RegisterRouter.scala:87:24] wire out_womask_1059 = &_out_womask_T_1059; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1059 = out_rivalid_1_913 & out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10256 = out_f_rivalid_1059; // @[RegisterRouter.scala:87:24] wire out_f_roready_1059 = out_roready_1_913 & out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10257 = out_f_roready_1059; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1059 = out_wivalid_1_913 & out_wimask_1059; // @[RegisterRouter.scala:87:24] wire out_f_woready_1059 = out_woready_1_913 & out_womask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10258 = ~out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10259 = ~out_wimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10260 = ~out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10261 = ~out_womask_1059; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_907 = {hi_127, flags_0_go, _out_prepend_T_907}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10262 = out_prepend_907; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10263 = _out_T_10262; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_908 = _out_T_10263; // @[RegisterRouter.scala:87:24] wire out_rimask_1060 = \|_out_rimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_wimask_1060 = &_out_wimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_romask_1060 = \|_out_romask_T_1060; // @[RegisterRouter.scala:87:24] wire out_womask_1060 = &_out_womask_T_1060; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1060 = out_rivalid_1_914 & out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10265 = out_f_rivalid_1060; // @[RegisterRouter.scala:87:24] wire out_f_roready_1060 = out_roready_1_914 & out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10266 = out_f_roready_1060; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1060 = out_wivalid_1_914 & out_wimask_1060; // @[RegisterRouter.scala:87:24] wire out_f_woready_1060 = out_woready_1_914 & out_womask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10267 = ~out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10268 = ~out_wimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10269 = ~out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10270 = ~out_womask_1060; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_908 = {hi_128, flags_0_go, _out_prepend_T_908}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10271 = out_prepend_908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10272 = _out_T_10271; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_143 = _out_T_10272; // @[MuxLiteral.scala:49:48] wire out_rimask_1061 = \|_out_rimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_wimask_1061 = &_out_wimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_romask_1061 = \|_out_romask_T_1061; // @[RegisterRouter.scala:87:24] wire out_womask_1061 = &_out_womask_T_1061; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1061 = out_rivalid_1_915 & out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10274 = out_f_rivalid_1061; // @[RegisterRouter.scala:87:24] wire out_f_roready_1061 = out_roready_1_915 & out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10275 = out_f_roready_1061; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1061 = out_wivalid_1_915 & out_wimask_1061; // @[RegisterRouter.scala:87:24] wire out_f_woready_1061 = out_woready_1_915 & out_womask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10276 = ~out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10277 = ~out_wimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10278 = ~out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10279 = ~out_womask_1061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10281 = _out_T_10280; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_909 = _out_T_10281; // @[RegisterRouter.scala:87:24] wire out_rimask_1062 = \|_out_rimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_wimask_1062 = &_out_wimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_romask_1062 = \|_out_romask_T_1062; // @[RegisterRouter.scala:87:24] wire out_womask_1062 = &_out_womask_T_1062; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1062 = out_rivalid_1_916 & out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10283 = out_f_rivalid_1062; // @[RegisterRouter.scala:87:24] wire out_f_roready_1062 = out_roready_1_916 & out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10284 = out_f_roready_1062; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1062 = out_wivalid_1_916 & out_wimask_1062; // @[RegisterRouter.scala:87:24] wire out_f_woready_1062 = out_woready_1_916 & out_womask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10285 = ~out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10286 = ~out_wimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10287 = ~out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10288 = ~out_womask_1062; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_909 = {hi_602, flags_0_go, _out_prepend_T_909}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10289 = out_prepend_909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10290 = _out_T_10289; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_910 = _out_T_10290; // @[RegisterRouter.scala:87:24] wire out_rimask_1063 = \|_out_rimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_wimask_1063 = &_out_wimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_romask_1063 = \|_out_romask_T_1063; // @[RegisterRouter.scala:87:24] wire out_womask_1063 = &_out_womask_T_1063; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1063 = out_rivalid_1_917 & out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10292 = out_f_rivalid_1063; // @[RegisterRouter.scala:87:24] wire out_f_roready_1063 = out_roready_1_917 & out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10293 = out_f_roready_1063; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1063 = out_wivalid_1_917 & out_wimask_1063; // @[RegisterRouter.scala:87:24] wire out_f_woready_1063 = out_woready_1_917 & out_womask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10294 = ~out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10295 = ~out_wimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10296 = ~out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10297 = ~out_womask_1063; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_910 = {hi_603, flags_0_go, _out_prepend_T_910}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10298 = out_prepend_910; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10299 = _out_T_10298; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_911 = _out_T_10299; // @[RegisterRouter.scala:87:24] wire out_rimask_1064 = \|_out_rimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_wimask_1064 = &_out_wimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_romask_1064 = \|_out_romask_T_1064; // @[RegisterRouter.scala:87:24] wire out_womask_1064 = &_out_womask_T_1064; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1064 = out_rivalid_1_918 & out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10301 = out_f_rivalid_1064; // @[RegisterRouter.scala:87:24] wire out_f_roready_1064 = out_roready_1_918 & out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10302 = out_f_roready_1064; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1064 = out_wivalid_1_918 & out_wimask_1064; // @[RegisterRouter.scala:87:24] wire out_f_woready_1064 = out_woready_1_918 & out_womask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10303 = ~out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10304 = ~out_wimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10305 = ~out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10306 = ~out_womask_1064; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_911 = {hi_604, flags_0_go, _out_prepend_T_911}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10307 = out_prepend_911; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10308 = _out_T_10307; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_912 = _out_T_10308; // @[RegisterRouter.scala:87:24] wire out_rimask_1065 = \|_out_rimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_wimask_1065 = &_out_wimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_romask_1065 = \|_out_romask_T_1065; // @[RegisterRouter.scala:87:24] wire out_womask_1065 = &_out_womask_T_1065; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1065 = out_rivalid_1_919 & out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10310 = out_f_rivalid_1065; // @[RegisterRouter.scala:87:24] wire out_f_roready_1065 = out_roready_1_919 & out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10311 = out_f_roready_1065; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1065 = out_wivalid_1_919 & out_wimask_1065; // @[RegisterRouter.scala:87:24] wire out_f_woready_1065 = out_woready_1_919 & out_womask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10312 = ~out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10313 = ~out_wimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10314 = ~out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10315 = ~out_womask_1065; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_912 = {hi_605, flags_0_go, _out_prepend_T_912}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10316 = out_prepend_912; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10317 = _out_T_10316; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_913 = _out_T_10317; // @[RegisterRouter.scala:87:24] wire out_rimask_1066 = \|_out_rimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_wimask_1066 = &_out_wimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_romask_1066 = \|_out_romask_T_1066; // @[RegisterRouter.scala:87:24] wire out_womask_1066 = &_out_womask_T_1066; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1066 = out_rivalid_1_920 & out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10319 = out_f_rivalid_1066; // @[RegisterRouter.scala:87:24] wire out_f_roready_1066 = out_roready_1_920 & out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10320 = out_f_roready_1066; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1066 = out_wivalid_1_920 & out_wimask_1066; // @[RegisterRouter.scala:87:24] wire out_f_woready_1066 = out_woready_1_920 & out_womask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10321 = ~out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10322 = ~out_wimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10323 = ~out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10324 = ~out_womask_1066; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_913 = {hi_606, flags_0_go, _out_prepend_T_913}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10325 = out_prepend_913; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10326 = _out_T_10325; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_914 = _out_T_10326; // @[RegisterRouter.scala:87:24] wire out_rimask_1067 = \|_out_rimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_wimask_1067 = &_out_wimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_romask_1067 = \|_out_romask_T_1067; // @[RegisterRouter.scala:87:24] wire out_womask_1067 = &_out_womask_T_1067; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1067 = out_rivalid_1_921 & out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10328 = out_f_rivalid_1067; // @[RegisterRouter.scala:87:24] wire out_f_roready_1067 = out_roready_1_921 & out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10329 = out_f_roready_1067; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1067 = out_wivalid_1_921 & out_wimask_1067; // @[RegisterRouter.scala:87:24] wire out_f_woready_1067 = out_woready_1_921 & out_womask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10330 = ~out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10331 = ~out_wimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10332 = ~out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10333 = ~out_womask_1067; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_914 = {hi_607, flags_0_go, _out_prepend_T_914}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10334 = out_prepend_914; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10335 = _out_T_10334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_915 = _out_T_10335; // @[RegisterRouter.scala:87:24] wire out_rimask_1068 = \|_out_rimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_wimask_1068 = &_out_wimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_romask_1068 = \|_out_romask_T_1068; // @[RegisterRouter.scala:87:24] wire out_womask_1068 = &_out_womask_T_1068; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1068 = out_rivalid_1_922 & out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10337 = out_f_rivalid_1068; // @[RegisterRouter.scala:87:24] wire out_f_roready_1068 = out_roready_1_922 & out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10338 = out_f_roready_1068; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1068 = out_wivalid_1_922 & out_wimask_1068; // @[RegisterRouter.scala:87:24] wire out_f_woready_1068 = out_woready_1_922 & out_womask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10339 = ~out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10340 = ~out_wimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10341 = ~out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10342 = ~out_womask_1068; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_915 = {hi_608, flags_0_go, _out_prepend_T_915}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10343 = out_prepend_915; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10344 = _out_T_10343; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_203 = _out_T_10344; // @[MuxLiteral.scala:49:48] wire out_rimask_1069 = \|_out_rimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_wimask_1069 = &_out_wimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_romask_1069 = \|_out_romask_T_1069; // @[RegisterRouter.scala:87:24] wire out_womask_1069 = &_out_womask_T_1069; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1069 = out_rivalid_1_923 & out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10346 = out_f_rivalid_1069; // @[RegisterRouter.scala:87:24] wire out_f_roready_1069 = out_roready_1_923 & out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10347 = out_f_roready_1069; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1069 = out_wivalid_1_923 & out_wimask_1069; // @[RegisterRouter.scala:87:24] wire out_f_woready_1069 = out_woready_1_923 & out_womask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10348 = ~out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10349 = ~out_wimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10350 = ~out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10351 = ~out_womask_1069; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10353 = _out_T_10352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_916 = _out_T_10353; // @[RegisterRouter.scala:87:24] wire out_rimask_1070 = \|_out_rimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_wimask_1070 = &_out_wimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_romask_1070 = \|_out_romask_T_1070; // @[RegisterRouter.scala:87:24] wire out_womask_1070 = &_out_womask_T_1070; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1070 = out_rivalid_1_924 & out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10355 = out_f_rivalid_1070; // @[RegisterRouter.scala:87:24] wire out_f_roready_1070 = out_roready_1_924 & out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10356 = out_f_roready_1070; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1070 = out_wivalid_1_924 & out_wimask_1070; // @[RegisterRouter.scala:87:24] wire out_f_woready_1070 = out_woready_1_924 & out_womask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10357 = ~out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10358 = ~out_wimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10359 = ~out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10360 = ~out_womask_1070; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_916 = {hi_722, flags_0_go, _out_prepend_T_916}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10361 = out_prepend_916; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10362 = _out_T_10361; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_917 = _out_T_10362; // @[RegisterRouter.scala:87:24] wire out_rimask_1071 = \|_out_rimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_wimask_1071 = &_out_wimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_romask_1071 = \|_out_romask_T_1071; // @[RegisterRouter.scala:87:24] wire out_womask_1071 = &_out_womask_T_1071; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1071 = out_rivalid_1_925 & out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10364 = out_f_rivalid_1071; // @[RegisterRouter.scala:87:24] wire out_f_roready_1071 = out_roready_1_925 & out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10365 = out_f_roready_1071; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1071 = out_wivalid_1_925 & out_wimask_1071; // @[RegisterRouter.scala:87:24] wire out_f_woready_1071 = out_woready_1_925 & out_womask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10366 = ~out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10367 = ~out_wimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10368 = ~out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10369 = ~out_womask_1071; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_917 = {hi_723, flags_0_go, _out_prepend_T_917}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10370 = out_prepend_917; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10371 = _out_T_10370; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_918 = _out_T_10371; // @[RegisterRouter.scala:87:24] wire out_rimask_1072 = \|_out_rimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_wimask_1072 = &_out_wimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_romask_1072 = \|_out_romask_T_1072; // @[RegisterRouter.scala:87:24] wire out_womask_1072 = &_out_womask_T_1072; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1072 = out_rivalid_1_926 & out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10373 = out_f_rivalid_1072; // @[RegisterRouter.scala:87:24] wire out_f_roready_1072 = out_roready_1_926 & out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10374 = out_f_roready_1072; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1072 = out_wivalid_1_926 & out_wimask_1072; // @[RegisterRouter.scala:87:24] wire out_f_woready_1072 = out_woready_1_926 & out_womask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10375 = ~out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10376 = ~out_wimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10377 = ~out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10378 = ~out_womask_1072; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_918 = {hi_724, flags_0_go, _out_prepend_T_918}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10379 = out_prepend_918; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10380 = _out_T_10379; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_919 = _out_T_10380; // @[RegisterRouter.scala:87:24] wire out_rimask_1073 = \|_out_rimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_wimask_1073 = &_out_wimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_romask_1073 = \|_out_romask_T_1073; // @[RegisterRouter.scala:87:24] wire out_womask_1073 = &_out_womask_T_1073; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1073 = out_rivalid_1_927 & out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10382 = out_f_rivalid_1073; // @[RegisterRouter.scala:87:24] wire out_f_roready_1073 = out_roready_1_927 & out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10383 = out_f_roready_1073; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1073 = out_wivalid_1_927 & out_wimask_1073; // @[RegisterRouter.scala:87:24] wire out_f_woready_1073 = out_woready_1_927 & out_womask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10384 = ~out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10385 = ~out_wimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10386 = ~out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10387 = ~out_womask_1073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_919 = {hi_725, flags_0_go, _out_prepend_T_919}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10388 = out_prepend_919; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10389 = _out_T_10388; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_920 = _out_T_10389; // @[RegisterRouter.scala:87:24] wire out_rimask_1074 = \|_out_rimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_wimask_1074 = &_out_wimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_romask_1074 = \|_out_romask_T_1074; // @[RegisterRouter.scala:87:24] wire out_womask_1074 = &_out_womask_T_1074; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1074 = out_rivalid_1_928 & out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10391 = out_f_rivalid_1074; // @[RegisterRouter.scala:87:24] wire out_f_roready_1074 = out_roready_1_928 & out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10392 = out_f_roready_1074; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1074 = out_wivalid_1_928 & out_wimask_1074; // @[RegisterRouter.scala:87:24] wire out_f_woready_1074 = out_woready_1_928 & out_womask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10393 = ~out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10394 = ~out_wimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10395 = ~out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10396 = ~out_womask_1074; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_920 = {hi_726, flags_0_go, _out_prepend_T_920}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10397 = out_prepend_920; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10398 = _out_T_10397; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_921 = _out_T_10398; // @[RegisterRouter.scala:87:24] wire out_rimask_1075 = \|_out_rimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_wimask_1075 = &_out_wimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_romask_1075 = \|_out_romask_T_1075; // @[RegisterRouter.scala:87:24] wire out_womask_1075 = &_out_womask_T_1075; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1075 = out_rivalid_1_929 & out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10400 = out_f_rivalid_1075; // @[RegisterRouter.scala:87:24] wire out_f_roready_1075 = out_roready_1_929 & out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10401 = out_f_roready_1075; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1075 = out_wivalid_1_929 & out_wimask_1075; // @[RegisterRouter.scala:87:24] wire out_f_woready_1075 = out_woready_1_929 & out_womask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10402 = ~out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10403 = ~out_wimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10404 = ~out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10405 = ~out_womask_1075; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_921 = {hi_727, flags_0_go, _out_prepend_T_921}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10406 = out_prepend_921; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10407 = _out_T_10406; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_922 = _out_T_10407; // @[RegisterRouter.scala:87:24] wire out_rimask_1076 = \|_out_rimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_wimask_1076 = &_out_wimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_romask_1076 = \|_out_romask_T_1076; // @[RegisterRouter.scala:87:24] wire out_womask_1076 = &_out_womask_T_1076; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1076 = out_rivalid_1_930 & out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10409 = out_f_rivalid_1076; // @[RegisterRouter.scala:87:24] wire out_f_roready_1076 = out_roready_1_930 & out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10410 = out_f_roready_1076; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1076 = out_wivalid_1_930 & out_wimask_1076; // @[RegisterRouter.scala:87:24] wire out_f_woready_1076 = out_woready_1_930 & out_womask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10411 = ~out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10412 = ~out_wimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10413 = ~out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10414 = ~out_womask_1076; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_922 = {hi_728, flags_0_go, _out_prepend_T_922}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10415 = out_prepend_922; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10416 = _out_T_10415; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_218 = _out_T_10416; // @[MuxLiteral.scala:49:48] wire out_rimask_1077 = \|_out_rimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_wimask_1077 = &_out_wimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_romask_1077 = \|_out_romask_T_1077; // @[RegisterRouter.scala:87:24] wire out_womask_1077 = &_out_womask_T_1077; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1077 = out_rivalid_1_931 & out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10418 = out_f_rivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_roready_1077 = out_roready_1_931 & out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10419 = out_f_roready_1077; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1077 = out_wivalid_1_931 & out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10420 = out_f_wivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_woready_1077 = out_woready_1_931 & out_womask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10421 = out_f_woready_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10422 = ~out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10423 = ~out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10424 = ~out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10425 = ~out_womask_1077; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10427 = _out_T_10426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_923 = _out_T_10427; // @[RegisterRouter.scala:87:24] wire out_rimask_1078 = \|_out_rimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_wimask_1078 = &_out_wimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_romask_1078 = \|_out_romask_T_1078; // @[RegisterRouter.scala:87:24] wire out_womask_1078 = &_out_womask_T_1078; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1078 = out_rivalid_1_932 & out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10429 = out_f_rivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_roready_1078 = out_roready_1_932 & out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10430 = out_f_roready_1078; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1078 = out_wivalid_1_932 & out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10431 = out_f_wivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_woready_1078 = out_woready_1_932 & out_womask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10432 = out_f_woready_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10433 = ~out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10434 = ~out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10435 = ~out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10436 = ~out_womask_1078; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_923 = {programBufferMem_1, _out_prepend_T_923}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10437 = out_prepend_923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10438 = _out_T_10437; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_924 = _out_T_10438; // @[RegisterRouter.scala:87:24] wire out_rimask_1079 = \|_out_rimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_wimask_1079 = &_out_wimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_romask_1079 = \|_out_romask_T_1079; // @[RegisterRouter.scala:87:24] wire out_womask_1079 = &_out_womask_T_1079; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1079 = out_rivalid_1_933 & out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10440 = out_f_rivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_roready_1079 = out_roready_1_933 & out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10441 = out_f_roready_1079; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1079 = out_wivalid_1_933 & out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10442 = out_f_wivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_woready_1079 = out_woready_1_933 & out_womask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10443 = out_f_woready_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10444 = ~out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10445 = ~out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10446 = ~out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10447 = ~out_womask_1079; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_924 = {programBufferMem_2, _out_prepend_T_924}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10448 = out_prepend_924; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10449 = _out_T_10448; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_925 = _out_T_10449; // @[RegisterRouter.scala:87:24] wire out_rimask_1080 = \|_out_rimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_wimask_1080 = &_out_wimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_romask_1080 = \|_out_romask_T_1080; // @[RegisterRouter.scala:87:24] wire out_womask_1080 = &_out_womask_T_1080; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1080 = out_rivalid_1_934 & out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10451 = out_f_rivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_roready_1080 = out_roready_1_934 & out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10452 = out_f_roready_1080; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1080 = out_wivalid_1_934 & out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10453 = out_f_wivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_woready_1080 = out_woready_1_934 & out_womask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10454 = out_f_woready_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10455 = ~out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10456 = ~out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10457 = ~out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10458 = ~out_womask_1080; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_925 = {programBufferMem_3, _out_prepend_T_925}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10459 = out_prepend_925; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10460 = _out_T_10459; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_926 = _out_T_10460; // @[RegisterRouter.scala:87:24] wire out_rimask_1081 = \|_out_rimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_wimask_1081 = &_out_wimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_romask_1081 = \|_out_romask_T_1081; // @[RegisterRouter.scala:87:24] wire out_womask_1081 = &_out_womask_T_1081; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1081 = out_rivalid_1_935 & out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10462 = out_f_rivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_roready_1081 = out_roready_1_935 & out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10463 = out_f_roready_1081; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1081 = out_wivalid_1_935 & out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10464 = out_f_wivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_woready_1081 = out_woready_1_935 & out_womask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10465 = out_f_woready_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10466 = ~out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10467 = ~out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10468 = ~out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10469 = ~out_womask_1081; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_926 = {programBufferMem_4, _out_prepend_T_926}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10470 = out_prepend_926; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10471 = _out_T_10470; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_927 = _out_T_10471; // @[RegisterRouter.scala:87:24] wire out_rimask_1082 = \|_out_rimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_wimask_1082 = &_out_wimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_romask_1082 = \|_out_romask_T_1082; // @[RegisterRouter.scala:87:24] wire out_womask_1082 = &_out_womask_T_1082; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1082 = out_rivalid_1_936 & out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10473 = out_f_rivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_roready_1082 = out_roready_1_936 & out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10474 = out_f_roready_1082; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1082 = out_wivalid_1_936 & out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10475 = out_f_wivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_woready_1082 = out_woready_1_936 & out_womask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10476 = out_f_woready_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10477 = ~out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10478 = ~out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10479 = ~out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10480 = ~out_womask_1082; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_927 = {programBufferMem_5, _out_prepend_T_927}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10481 = out_prepend_927; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10482 = _out_T_10481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_928 = _out_T_10482; // @[RegisterRouter.scala:87:24] wire out_rimask_1083 = \|_out_rimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_wimask_1083 = &_out_wimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_romask_1083 = \|_out_romask_T_1083; // @[RegisterRouter.scala:87:24] wire out_womask_1083 = &_out_womask_T_1083; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1083 = out_rivalid_1_937 & out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10484 = out_f_rivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_roready_1083 = out_roready_1_937 & out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10485 = out_f_roready_1083; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1083 = out_wivalid_1_937 & out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10486 = out_f_wivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_woready_1083 = out_woready_1_937 & out_womask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10487 = out_f_woready_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10488 = ~out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10489 = ~out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10490 = ~out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10491 = ~out_womask_1083; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_928 = {programBufferMem_6, _out_prepend_T_928}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10492 = out_prepend_928; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10493 = _out_T_10492; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_929 = _out_T_10493; // @[RegisterRouter.scala:87:24] wire out_rimask_1084 = \|_out_rimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_wimask_1084 = &_out_wimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_romask_1084 = \|_out_romask_T_1084; // @[RegisterRouter.scala:87:24] wire out_womask_1084 = &_out_womask_T_1084; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1084 = out_rivalid_1_938 & out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10495 = out_f_rivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_roready_1084 = out_roready_1_938 & out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10496 = out_f_roready_1084; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1084 = out_wivalid_1_938 & out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10497 = out_f_wivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_woready_1084 = out_woready_1_938 & out_womask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10498 = out_f_woready_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10499 = ~out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10500 = ~out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10501 = ~out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10502 = ~out_womask_1084; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_929 = {programBufferMem_7, _out_prepend_T_929}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10503 = out_prepend_929; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10504 = _out_T_10503; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_104 = _out_T_10504; // @[MuxLiteral.scala:49:48] wire out_rimask_1085 = \|_out_rimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_wimask_1085 = &_out_wimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_romask_1085 = \|_out_romask_T_1085; // @[RegisterRouter.scala:87:24] wire out_womask_1085 = &_out_womask_T_1085; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1085 = out_rivalid_1_939 & out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10506 = out_f_rivalid_1085; // @[RegisterRouter.scala:87:24] wire out_f_roready_1085 = out_roready_1_939 & out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10507 = out_f_roready_1085; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1085 = out_wivalid_1_939 & out_wimask_1085; // @[RegisterRouter.scala:87:24] wire out_f_woready_1085 = out_woready_1_939 & out_womask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10508 = ~out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10509 = ~out_wimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10510 = ~out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10511 = ~out_womask_1085; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10513 = _out_T_10512; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_930 = _out_T_10513; // @[RegisterRouter.scala:87:24] wire out_rimask_1086 = \|_out_rimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_wimask_1086 = &_out_wimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_romask_1086 = \|_out_romask_T_1086; // @[RegisterRouter.scala:87:24] wire out_womask_1086 = &_out_womask_T_1086; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1086 = out_rivalid_1_940 & out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10515 = out_f_rivalid_1086; // @[RegisterRouter.scala:87:24] wire out_f_roready_1086 = out_roready_1_940 & out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10516 = out_f_roready_1086; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1086 = out_wivalid_1_940 & out_wimask_1086; // @[RegisterRouter.scala:87:24] wire out_f_woready_1086 = out_woready_1_940 & out_womask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10517 = ~out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10518 = ~out_wimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10519 = ~out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10520 = ~out_womask_1086; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_930 = {hi_978, flags_0_go, _out_prepend_T_930}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10521 = out_prepend_930; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10522 = _out_T_10521; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_931 = _out_T_10522; // @[RegisterRouter.scala:87:24] wire out_rimask_1087 = \|_out_rimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_wimask_1087 = &_out_wimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_romask_1087 = \|_out_romask_T_1087; // @[RegisterRouter.scala:87:24] wire out_womask_1087 = &_out_womask_T_1087; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1087 = out_rivalid_1_941 & out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10524 = out_f_rivalid_1087; // @[RegisterRouter.scala:87:24] wire out_f_roready_1087 = out_roready_1_941 & out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10525 = out_f_roready_1087; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1087 = out_wivalid_1_941 & out_wimask_1087; // @[RegisterRouter.scala:87:24] wire out_f_woready_1087 = out_woready_1_941 & out_womask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10526 = ~out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10527 = ~out_wimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10528 = ~out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10529 = ~out_womask_1087; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_931 = {hi_979, flags_0_go, _out_prepend_T_931}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10530 = out_prepend_931; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10531 = _out_T_10530; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_932 = _out_T_10531; // @[RegisterRouter.scala:87:24] wire out_rimask_1088 = \|_out_rimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_wimask_1088 = &_out_wimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_romask_1088 = \|_out_romask_T_1088; // @[RegisterRouter.scala:87:24] wire out_womask_1088 = &_out_womask_T_1088; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1088 = out_rivalid_1_942 & out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10533 = out_f_rivalid_1088; // @[RegisterRouter.scala:87:24] wire out_f_roready_1088 = out_roready_1_942 & out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10534 = out_f_roready_1088; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1088 = out_wivalid_1_942 & out_wimask_1088; // @[RegisterRouter.scala:87:24] wire out_f_woready_1088 = out_woready_1_942 & out_womask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10535 = ~out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10536 = ~out_wimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10537 = ~out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10538 = ~out_womask_1088; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_932 = {hi_980, flags_0_go, _out_prepend_T_932}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10539 = out_prepend_932; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10540 = _out_T_10539; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_933 = _out_T_10540; // @[RegisterRouter.scala:87:24] wire out_rimask_1089 = \|_out_rimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_wimask_1089 = &_out_wimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_romask_1089 = \|_out_romask_T_1089; // @[RegisterRouter.scala:87:24] wire out_womask_1089 = &_out_womask_T_1089; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1089 = out_rivalid_1_943 & out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10542 = out_f_rivalid_1089; // @[RegisterRouter.scala:87:24] wire out_f_roready_1089 = out_roready_1_943 & out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10543 = out_f_roready_1089; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1089 = out_wivalid_1_943 & out_wimask_1089; // @[RegisterRouter.scala:87:24] wire out_f_woready_1089 = out_woready_1_943 & out_womask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10544 = ~out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10545 = ~out_wimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10546 = ~out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10547 = ~out_womask_1089; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_933 = {hi_981, flags_0_go, _out_prepend_T_933}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10548 = out_prepend_933; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10549 = _out_T_10548; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_934 = _out_T_10549; // @[RegisterRouter.scala:87:24] wire out_rimask_1090 = \|_out_rimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_wimask_1090 = &_out_wimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_romask_1090 = \|_out_romask_T_1090; // @[RegisterRouter.scala:87:24] wire out_womask_1090 = &_out_womask_T_1090; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1090 = out_rivalid_1_944 & out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10551 = out_f_rivalid_1090; // @[RegisterRouter.scala:87:24] wire out_f_roready_1090 = out_roready_1_944 & out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10552 = out_f_roready_1090; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1090 = out_wivalid_1_944 & out_wimask_1090; // @[RegisterRouter.scala:87:24] wire out_f_woready_1090 = out_woready_1_944 & out_womask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10553 = ~out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10554 = ~out_wimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10555 = ~out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10556 = ~out_womask_1090; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_934 = {hi_982, flags_0_go, _out_prepend_T_934}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10557 = out_prepend_934; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10558 = _out_T_10557; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_935 = _out_T_10558; // @[RegisterRouter.scala:87:24] wire out_rimask_1091 = \|_out_rimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_wimask_1091 = &_out_wimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_romask_1091 = \|_out_romask_T_1091; // @[RegisterRouter.scala:87:24] wire out_womask_1091 = &_out_womask_T_1091; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1091 = out_rivalid_1_945 & out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10560 = out_f_rivalid_1091; // @[RegisterRouter.scala:87:24] wire out_f_roready_1091 = out_roready_1_945 & out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10561 = out_f_roready_1091; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1091 = out_wivalid_1_945 & out_wimask_1091; // @[RegisterRouter.scala:87:24] wire out_f_woready_1091 = out_woready_1_945 & out_womask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10562 = ~out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10563 = ~out_wimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10564 = ~out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10565 = ~out_womask_1091; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_935 = {hi_983, flags_0_go, _out_prepend_T_935}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10566 = out_prepend_935; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10567 = _out_T_10566; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_936 = _out_T_10567; // @[RegisterRouter.scala:87:24] wire out_rimask_1092 = \|_out_rimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_wimask_1092 = &_out_wimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_romask_1092 = \|_out_romask_T_1092; // @[RegisterRouter.scala:87:24] wire out_womask_1092 = &_out_womask_T_1092; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1092 = out_rivalid_1_946 & out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10569 = out_f_rivalid_1092; // @[RegisterRouter.scala:87:24] wire out_f_roready_1092 = out_roready_1_946 & out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10570 = out_f_roready_1092; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1092 = out_wivalid_1_946 & out_wimask_1092; // @[RegisterRouter.scala:87:24] wire out_f_woready_1092 = out_woready_1_946 & out_womask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10571 = ~out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10572 = ~out_wimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10573 = ~out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10574 = ~out_womask_1092; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_936 = {hi_984, flags_0_go, _out_prepend_T_936}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10575 = out_prepend_936; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10576 = _out_T_10575; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_250 = _out_T_10576; // @[MuxLiteral.scala:49:48] wire out_rimask_1093 = \|_out_rimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_wimask_1093 = &_out_wimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_romask_1093 = \|_out_romask_T_1093; // @[RegisterRouter.scala:87:24] wire out_womask_1093 = &_out_womask_T_1093; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1093 = out_rivalid_1_947 & out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10578 = out_f_rivalid_1093; // @[RegisterRouter.scala:87:24] wire out_f_roready_1093 = out_roready_1_947 & out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10579 = out_f_roready_1093; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1093 = out_wivalid_1_947 & out_wimask_1093; // @[RegisterRouter.scala:87:24] wire out_f_woready_1093 = out_woready_1_947 & out_womask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10580 = ~out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10581 = ~out_wimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10582 = ~out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10583 = ~out_womask_1093; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10585 = _out_T_10584; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_937 = _out_T_10585; // @[RegisterRouter.scala:87:24] wire out_rimask_1094 = \|_out_rimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_wimask_1094 = &_out_wimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_romask_1094 = \|_out_romask_T_1094; // @[RegisterRouter.scala:87:24] wire out_womask_1094 = &_out_womask_T_1094; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1094 = out_rivalid_1_948 & out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10587 = out_f_rivalid_1094; // @[RegisterRouter.scala:87:24] wire out_f_roready_1094 = out_roready_1_948 & out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10588 = out_f_roready_1094; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1094 = out_wivalid_1_948 & out_wimask_1094; // @[RegisterRouter.scala:87:24] wire out_f_woready_1094 = out_woready_1_948 & out_womask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10589 = ~out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10590 = ~out_wimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10591 = ~out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10592 = ~out_womask_1094; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_937 = {hi_826, flags_0_go, _out_prepend_T_937}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10593 = out_prepend_937; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10594 = _out_T_10593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_938 = _out_T_10594; // @[RegisterRouter.scala:87:24] wire out_rimask_1095 = \|_out_rimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_wimask_1095 = &_out_wimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_romask_1095 = \|_out_romask_T_1095; // @[RegisterRouter.scala:87:24] wire out_womask_1095 = &_out_womask_T_1095; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1095 = out_rivalid_1_949 & out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10596 = out_f_rivalid_1095; // @[RegisterRouter.scala:87:24] wire out_f_roready_1095 = out_roready_1_949 & out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10597 = out_f_roready_1095; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1095 = out_wivalid_1_949 & out_wimask_1095; // @[RegisterRouter.scala:87:24] wire out_f_woready_1095 = out_woready_1_949 & out_womask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10598 = ~out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10599 = ~out_wimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10600 = ~out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10601 = ~out_womask_1095; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_938 = {hi_827, flags_0_go, _out_prepend_T_938}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10602 = out_prepend_938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10603 = _out_T_10602; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_939 = _out_T_10603; // @[RegisterRouter.scala:87:24] wire out_rimask_1096 = \|_out_rimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_wimask_1096 = &_out_wimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_romask_1096 = \|_out_romask_T_1096; // @[RegisterRouter.scala:87:24] wire out_womask_1096 = &_out_womask_T_1096; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1096 = out_rivalid_1_950 & out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10605 = out_f_rivalid_1096; // @[RegisterRouter.scala:87:24] wire out_f_roready_1096 = out_roready_1_950 & out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10606 = out_f_roready_1096; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1096 = out_wivalid_1_950 & out_wimask_1096; // @[RegisterRouter.scala:87:24] wire out_f_woready_1096 = out_woready_1_950 & out_womask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10607 = ~out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10608 = ~out_wimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10609 = ~out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10610 = ~out_womask_1096; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_939 = {hi_828, flags_0_go, _out_prepend_T_939}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10611 = out_prepend_939; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10612 = _out_T_10611; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_940 = _out_T_10612; // @[RegisterRouter.scala:87:24] wire out_rimask_1097 = \|_out_rimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_wimask_1097 = &_out_wimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_romask_1097 = \|_out_romask_T_1097; // @[RegisterRouter.scala:87:24] wire out_womask_1097 = &_out_womask_T_1097; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1097 = out_rivalid_1_951 & out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10614 = out_f_rivalid_1097; // @[RegisterRouter.scala:87:24] wire out_f_roready_1097 = out_roready_1_951 & out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10615 = out_f_roready_1097; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1097 = out_wivalid_1_951 & out_wimask_1097; // @[RegisterRouter.scala:87:24] wire out_f_woready_1097 = out_woready_1_951 & out_womask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10616 = ~out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10617 = ~out_wimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10618 = ~out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10619 = ~out_womask_1097; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_940 = {hi_829, flags_0_go, _out_prepend_T_940}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10620 = out_prepend_940; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10621 = _out_T_10620; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_941 = _out_T_10621; // @[RegisterRouter.scala:87:24] wire out_rimask_1098 = \|_out_rimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_wimask_1098 = &_out_wimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_romask_1098 = \|_out_romask_T_1098; // @[RegisterRouter.scala:87:24] wire out_womask_1098 = &_out_womask_T_1098; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1098 = out_rivalid_1_952 & out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10623 = out_f_rivalid_1098; // @[RegisterRouter.scala:87:24] wire out_f_roready_1098 = out_roready_1_952 & out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10624 = out_f_roready_1098; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1098 = out_wivalid_1_952 & out_wimask_1098; // @[RegisterRouter.scala:87:24] wire out_f_woready_1098 = out_woready_1_952 & out_womask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10625 = ~out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10626 = ~out_wimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10627 = ~out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10628 = ~out_womask_1098; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_941 = {hi_830, flags_0_go, _out_prepend_T_941}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10629 = out_prepend_941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10630 = _out_T_10629; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_942 = _out_T_10630; // @[RegisterRouter.scala:87:24] wire out_rimask_1099 = \|_out_rimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_wimask_1099 = &_out_wimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_romask_1099 = \|_out_romask_T_1099; // @[RegisterRouter.scala:87:24] wire out_womask_1099 = &_out_womask_T_1099; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1099 = out_rivalid_1_953 & out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10632 = out_f_rivalid_1099; // @[RegisterRouter.scala:87:24] wire out_f_roready_1099 = out_roready_1_953 & out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10633 = out_f_roready_1099; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1099 = out_wivalid_1_953 & out_wimask_1099; // @[RegisterRouter.scala:87:24] wire out_f_woready_1099 = out_woready_1_953 & out_womask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10634 = ~out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10635 = ~out_wimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10636 = ~out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10637 = ~out_womask_1099; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_942 = {hi_831, flags_0_go, _out_prepend_T_942}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10638 = out_prepend_942; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10639 = _out_T_10638; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_943 = _out_T_10639; // @[RegisterRouter.scala:87:24] wire out_rimask_1100 = \|_out_rimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_wimask_1100 = &_out_wimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_romask_1100 = \|_out_romask_T_1100; // @[RegisterRouter.scala:87:24] wire out_womask_1100 = &_out_womask_T_1100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1100 = out_rivalid_1_954 & out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10641 = out_f_rivalid_1100; // @[RegisterRouter.scala:87:24] wire out_f_roready_1100 = out_roready_1_954 & out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10642 = out_f_roready_1100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1100 = out_wivalid_1_954 & out_wimask_1100; // @[RegisterRouter.scala:87:24] wire out_f_woready_1100 = out_woready_1_954 & out_womask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10643 = ~out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10644 = ~out_wimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10645 = ~out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10646 = ~out_womask_1100; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_943 = {hi_832, flags_0_go, _out_prepend_T_943}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10647 = out_prepend_943; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10648 = _out_T_10647; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_231 = _out_T_10648; // @[MuxLiteral.scala:49:48] wire out_rimask_1101 = \|_out_rimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_wimask_1101 = &_out_wimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_romask_1101 = \|_out_romask_T_1101; // @[RegisterRouter.scala:87:24] wire out_womask_1101 = &_out_womask_T_1101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1101 = out_rivalid_1_955 & out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10650 = out_f_rivalid_1101; // @[RegisterRouter.scala:87:24] wire out_f_roready_1101 = out_roready_1_955 & out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10651 = out_f_roready_1101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1101 = out_wivalid_1_955 & out_wimask_1101; // @[RegisterRouter.scala:87:24] wire out_f_woready_1101 = out_woready_1_955 & out_womask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10652 = ~out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10653 = ~out_wimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10654 = ~out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10655 = ~out_womask_1101; // @[RegisterRouter.scala:87:24] wire out_rimask_1102 = \|_out_rimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_wimask_1102 = &_out_wimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_romask_1102 = \|_out_romask_T_1102; // @[RegisterRouter.scala:87:24] wire out_womask_1102 = &_out_womask_T_1102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1102 = out_rivalid_1_956 & out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10659 = out_f_rivalid_1102; // @[RegisterRouter.scala:87:24] wire out_f_roready_1102 = out_roready_1_956 & out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10660 = out_f_roready_1102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1102 = out_wivalid_1_956 & out_wimask_1102; // @[RegisterRouter.scala:87:24] wire out_f_woready_1102 = out_woready_1_956 & out_womask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10661 = ~out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10662 = ~out_wimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10663 = ~out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10664 = ~out_womask_1102; // @[RegisterRouter.scala:87:24] wire out_rimask_1103 = \|_out_rimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_wimask_1103 = &_out_wimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_romask_1103 = \|_out_romask_T_1103; // @[RegisterRouter.scala:87:24] wire out_womask_1103 = &_out_womask_T_1103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1103 = out_rivalid_1_957 & out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10668 = out_f_rivalid_1103; // @[RegisterRouter.scala:87:24] wire out_f_roready_1103 = out_roready_1_957 & out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10669 = out_f_roready_1103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1103 = out_wivalid_1_957 & out_wimask_1103; // @[RegisterRouter.scala:87:24] wire out_f_woready_1103 = out_woready_1_957 & out_womask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10670 = ~out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10671 = ~out_wimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10672 = ~out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10673 = ~out_womask_1103; // @[RegisterRouter.scala:87:24] wire out_rimask_1104 = \|_out_rimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_wimask_1104 = &_out_wimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_romask_1104 = \|_out_romask_T_1104; // @[RegisterRouter.scala:87:24] wire out_womask_1104 = &_out_womask_T_1104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1104 = out_rivalid_1_958 & out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10677 = out_f_rivalid_1104; // @[RegisterRouter.scala:87:24] wire out_f_roready_1104 = out_roready_1_958 & out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10678 = out_f_roready_1104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1104 = out_wivalid_1_958 & out_wimask_1104; // @[RegisterRouter.scala:87:24] wire out_f_woready_1104 = out_woready_1_958 & out_womask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10679 = ~out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10680 = ~out_wimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10681 = ~out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10682 = ~out_womask_1104; // @[RegisterRouter.scala:87:24] wire out_rimask_1105 = \|_out_rimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_wimask_1105 = &_out_wimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_romask_1105 = \|_out_romask_T_1105; // @[RegisterRouter.scala:87:24] wire out_womask_1105 = &_out_womask_T_1105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1105 = out_rivalid_1_959 & out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10686 = out_f_rivalid_1105; // @[RegisterRouter.scala:87:24] wire out_f_roready_1105 = out_roready_1_959 & out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10687 = out_f_roready_1105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1105 = out_wivalid_1_959 & out_wimask_1105; // @[RegisterRouter.scala:87:24] wire out_f_woready_1105 = out_woready_1_959 & out_womask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10688 = ~out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10689 = ~out_wimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10690 = ~out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10691 = ~out_womask_1105; // @[RegisterRouter.scala:87:24] wire out_rimask_1106 = \|_out_rimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_wimask_1106 = &_out_wimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_romask_1106 = \|_out_romask_T_1106; // @[RegisterRouter.scala:87:24] wire out_womask_1106 = &_out_womask_T_1106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1106 = out_rivalid_1_960 & out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10695 = out_f_rivalid_1106; // @[RegisterRouter.scala:87:24] wire out_f_roready_1106 = out_roready_1_960 & out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10696 = out_f_roready_1106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1106 = out_wivalid_1_960 & out_wimask_1106; // @[RegisterRouter.scala:87:24] wire out_f_woready_1106 = out_woready_1_960 & out_womask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10697 = ~out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10698 = ~out_wimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10699 = ~out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10700 = ~out_womask_1106; // @[RegisterRouter.scala:87:24] wire out_rimask_1107 = \|_out_rimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_wimask_1107 = &_out_wimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_romask_1107 = \|_out_romask_T_1107; // @[RegisterRouter.scala:87:24] wire out_womask_1107 = &_out_womask_T_1107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1107 = out_rivalid_1_961 & out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10704 = out_f_rivalid_1107; // @[RegisterRouter.scala:87:24] wire out_f_roready_1107 = out_roready_1_961 & out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10705 = out_f_roready_1107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1107 = out_wivalid_1_961 & out_wimask_1107; // @[RegisterRouter.scala:87:24] wire out_f_woready_1107 = out_woready_1_961 & out_womask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10706 = ~out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10707 = ~out_wimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10708 = ~out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10709 = ~out_womask_1107; // @[RegisterRouter.scala:87:24] wire out_rimask_1108 = \|_out_rimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_wimask_1108 = &_out_wimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_romask_1108 = \|_out_romask_T_1108; // @[RegisterRouter.scala:87:24] wire out_womask_1108 = &_out_womask_T_1108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1108 = out_rivalid_1_962 & out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10713 = out_f_rivalid_1108; // @[RegisterRouter.scala:87:24] wire out_f_roready_1108 = out_roready_1_962 & out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10714 = out_f_roready_1108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1108 = out_wivalid_1_962 & out_wimask_1108; // @[RegisterRouter.scala:87:24] wire out_f_woready_1108 = out_woready_1_962 & out_womask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10715 = ~out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10716 = ~out_wimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10717 = ~out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10718 = ~out_womask_1108; // @[RegisterRouter.scala:87:24] wire out_rimask_1109 = \|_out_rimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_wimask_1109 = &_out_wimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_romask_1109 = \|_out_romask_T_1109; // @[RegisterRouter.scala:87:24] wire out_womask_1109 = &_out_womask_T_1109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1109 = out_rivalid_1_963 & out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10722 = out_f_rivalid_1109; // @[RegisterRouter.scala:87:24] wire out_f_roready_1109 = out_roready_1_963 & out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10723 = out_f_roready_1109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1109 = out_wivalid_1_963 & out_wimask_1109; // @[RegisterRouter.scala:87:24] wire out_f_woready_1109 = out_woready_1_963 & out_womask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10724 = ~out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10725 = ~out_wimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10726 = ~out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10727 = ~out_womask_1109; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10729 = _out_T_10728; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_951 = _out_T_10729; // @[RegisterRouter.scala:87:24] wire out_rimask_1110 = \|_out_rimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_wimask_1110 = &_out_wimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_romask_1110 = \|_out_romask_T_1110; // @[RegisterRouter.scala:87:24] wire out_womask_1110 = &_out_womask_T_1110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1110 = out_rivalid_1_964 & out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10731 = out_f_rivalid_1110; // @[RegisterRouter.scala:87:24] wire out_f_roready_1110 = out_roready_1_964 & out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10732 = out_f_roready_1110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1110 = out_wivalid_1_964 & out_wimask_1110; // @[RegisterRouter.scala:87:24] wire out_f_woready_1110 = out_woready_1_964 & out_womask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10733 = ~out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10734 = ~out_wimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10735 = ~out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10736 = ~out_womask_1110; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_951 = {hi_242, flags_0_go, _out_prepend_T_951}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10737 = out_prepend_951; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10738 = _out_T_10737; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_952 = _out_T_10738; // @[RegisterRouter.scala:87:24] wire out_rimask_1111 = \|_out_rimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_wimask_1111 = &_out_wimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_romask_1111 = \|_out_romask_T_1111; // @[RegisterRouter.scala:87:24] wire out_womask_1111 = &_out_womask_T_1111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1111 = out_rivalid_1_965 & out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10740 = out_f_rivalid_1111; // @[RegisterRouter.scala:87:24] wire out_f_roready_1111 = out_roready_1_965 & out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10741 = out_f_roready_1111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1111 = out_wivalid_1_965 & out_wimask_1111; // @[RegisterRouter.scala:87:24] wire out_f_woready_1111 = out_woready_1_965 & out_womask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10742 = ~out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10743 = ~out_wimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10744 = ~out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10745 = ~out_womask_1111; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_952 = {hi_243, flags_0_go, _out_prepend_T_952}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10746 = out_prepend_952; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10747 = _out_T_10746; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_953 = _out_T_10747; // @[RegisterRouter.scala:87:24] wire out_rimask_1112 = \|_out_rimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_wimask_1112 = &_out_wimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_romask_1112 = \|_out_romask_T_1112; // @[RegisterRouter.scala:87:24] wire out_womask_1112 = &_out_womask_T_1112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1112 = out_rivalid_1_966 & out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10749 = out_f_rivalid_1112; // @[RegisterRouter.scala:87:24] wire out_f_roready_1112 = out_roready_1_966 & out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10750 = out_f_roready_1112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1112 = out_wivalid_1_966 & out_wimask_1112; // @[RegisterRouter.scala:87:24] wire out_f_woready_1112 = out_woready_1_966 & out_womask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10751 = ~out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10752 = ~out_wimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10753 = ~out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10754 = ~out_womask_1112; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_953 = {hi_244, flags_0_go, _out_prepend_T_953}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10755 = out_prepend_953; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10756 = _out_T_10755; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_954 = _out_T_10756; // @[RegisterRouter.scala:87:24] wire out_rimask_1113 = \|_out_rimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_wimask_1113 = &_out_wimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_romask_1113 = \|_out_romask_T_1113; // @[RegisterRouter.scala:87:24] wire out_womask_1113 = &_out_womask_T_1113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1113 = out_rivalid_1_967 & out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10758 = out_f_rivalid_1113; // @[RegisterRouter.scala:87:24] wire out_f_roready_1113 = out_roready_1_967 & out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10759 = out_f_roready_1113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1113 = out_wivalid_1_967 & out_wimask_1113; // @[RegisterRouter.scala:87:24] wire out_f_woready_1113 = out_woready_1_967 & out_womask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10760 = ~out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10761 = ~out_wimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10762 = ~out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10763 = ~out_womask_1113; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_954 = {hi_245, flags_0_go, _out_prepend_T_954}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10764 = out_prepend_954; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10765 = _out_T_10764; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_955 = _out_T_10765; // @[RegisterRouter.scala:87:24] wire out_rimask_1114 = \|_out_rimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_wimask_1114 = &_out_wimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_romask_1114 = \|_out_romask_T_1114; // @[RegisterRouter.scala:87:24] wire out_womask_1114 = &_out_womask_T_1114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1114 = out_rivalid_1_968 & out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10767 = out_f_rivalid_1114; // @[RegisterRouter.scala:87:24] wire out_f_roready_1114 = out_roready_1_968 & out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10768 = out_f_roready_1114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1114 = out_wivalid_1_968 & out_wimask_1114; // @[RegisterRouter.scala:87:24] wire out_f_woready_1114 = out_woready_1_968 & out_womask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10769 = ~out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10770 = ~out_wimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10771 = ~out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10772 = ~out_womask_1114; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_955 = {hi_246, flags_0_go, _out_prepend_T_955}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10773 = out_prepend_955; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10774 = _out_T_10773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_956 = _out_T_10774; // @[RegisterRouter.scala:87:24] wire out_rimask_1115 = \|_out_rimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_wimask_1115 = &_out_wimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_romask_1115 = \|_out_romask_T_1115; // @[RegisterRouter.scala:87:24] wire out_womask_1115 = &_out_womask_T_1115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1115 = out_rivalid_1_969 & out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10776 = out_f_rivalid_1115; // @[RegisterRouter.scala:87:24] wire out_f_roready_1115 = out_roready_1_969 & out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10777 = out_f_roready_1115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1115 = out_wivalid_1_969 & out_wimask_1115; // @[RegisterRouter.scala:87:24] wire out_f_woready_1115 = out_woready_1_969 & out_womask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10778 = ~out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10779 = ~out_wimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10780 = ~out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10781 = ~out_womask_1115; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_956 = {hi_247, flags_0_go, _out_prepend_T_956}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10782 = out_prepend_956; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10783 = _out_T_10782; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_957 = _out_T_10783; // @[RegisterRouter.scala:87:24] wire out_rimask_1116 = \|_out_rimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_wimask_1116 = &_out_wimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_romask_1116 = \|_out_romask_T_1116; // @[RegisterRouter.scala:87:24] wire out_womask_1116 = &_out_womask_T_1116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1116 = out_rivalid_1_970 & out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10785 = out_f_rivalid_1116; // @[RegisterRouter.scala:87:24] wire out_f_roready_1116 = out_roready_1_970 & out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10786 = out_f_roready_1116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1116 = out_wivalid_1_970 & out_wimask_1116; // @[RegisterRouter.scala:87:24] wire out_f_woready_1116 = out_woready_1_970 & out_womask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10787 = ~out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10788 = ~out_wimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10789 = ~out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10790 = ~out_womask_1116; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_957 = {hi_248, flags_0_go, _out_prepend_T_957}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10791 = out_prepend_957; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10792 = _out_T_10791; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_158 = _out_T_10792; // @[MuxLiteral.scala:49:48] wire out_rimask_1117 = \|_out_rimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_wimask_1117 = &_out_wimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_romask_1117 = \|_out_romask_T_1117; // @[RegisterRouter.scala:87:24] wire out_womask_1117 = &_out_womask_T_1117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1117 = out_rivalid_1_971 & out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10794 = out_f_rivalid_1117; // @[RegisterRouter.scala:87:24] wire out_f_roready_1117 = out_roready_1_971 & out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10795 = out_f_roready_1117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1117 = out_wivalid_1_971 & out_wimask_1117; // @[RegisterRouter.scala:87:24] wire out_f_woready_1117 = out_woready_1_971 & out_womask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10796 = ~out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10797 = ~out_wimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10798 = ~out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10799 = ~out_womask_1117; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10801 = _out_T_10800; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_958 = _out_T_10801; // @[RegisterRouter.scala:87:24] wire out_rimask_1118 = \|_out_rimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_wimask_1118 = &_out_wimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_romask_1118 = \|_out_romask_T_1118; // @[RegisterRouter.scala:87:24] wire out_womask_1118 = &_out_womask_T_1118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1118 = out_rivalid_1_972 & out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10803 = out_f_rivalid_1118; // @[RegisterRouter.scala:87:24] wire out_f_roready_1118 = out_roready_1_972 & out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10804 = out_f_roready_1118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1118 = out_wivalid_1_972 & out_wimask_1118; // @[RegisterRouter.scala:87:24] wire out_f_woready_1118 = out_woready_1_972 & out_womask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10805 = ~out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10806 = ~out_wimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10807 = ~out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10808 = ~out_womask_1118; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_958 = {hi_466, flags_0_go, _out_prepend_T_958}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10809 = out_prepend_958; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10810 = _out_T_10809; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_959 = _out_T_10810; // @[RegisterRouter.scala:87:24] wire out_rimask_1119 = \|_out_rimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_wimask_1119 = &_out_wimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_romask_1119 = \|_out_romask_T_1119; // @[RegisterRouter.scala:87:24] wire out_womask_1119 = &_out_womask_T_1119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1119 = out_rivalid_1_973 & out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10812 = out_f_rivalid_1119; // @[RegisterRouter.scala:87:24] wire out_f_roready_1119 = out_roready_1_973 & out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10813 = out_f_roready_1119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1119 = out_wivalid_1_973 & out_wimask_1119; // @[RegisterRouter.scala:87:24] wire out_f_woready_1119 = out_woready_1_973 & out_womask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10814 = ~out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10815 = ~out_wimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10816 = ~out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10817 = ~out_womask_1119; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_959 = {hi_467, flags_0_go, _out_prepend_T_959}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10818 = out_prepend_959; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10819 = _out_T_10818; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_960 = _out_T_10819; // @[RegisterRouter.scala:87:24] wire out_rimask_1120 = \|_out_rimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_wimask_1120 = &_out_wimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_romask_1120 = \|_out_romask_T_1120; // @[RegisterRouter.scala:87:24] wire out_womask_1120 = &_out_womask_T_1120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1120 = out_rivalid_1_974 & out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10821 = out_f_rivalid_1120; // @[RegisterRouter.scala:87:24] wire out_f_roready_1120 = out_roready_1_974 & out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10822 = out_f_roready_1120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1120 = out_wivalid_1_974 & out_wimask_1120; // @[RegisterRouter.scala:87:24] wire out_f_woready_1120 = out_woready_1_974 & out_womask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10823 = ~out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10824 = ~out_wimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10825 = ~out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10826 = ~out_womask_1120; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_960 = {hi_468, flags_0_go, _out_prepend_T_960}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10827 = out_prepend_960; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10828 = _out_T_10827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_961 = _out_T_10828; // @[RegisterRouter.scala:87:24] wire out_rimask_1121 = \|_out_rimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_wimask_1121 = &_out_wimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_romask_1121 = \|_out_romask_T_1121; // @[RegisterRouter.scala:87:24] wire out_womask_1121 = &_out_womask_T_1121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1121 = out_rivalid_1_975 & out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10830 = out_f_rivalid_1121; // @[RegisterRouter.scala:87:24] wire out_f_roready_1121 = out_roready_1_975 & out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10831 = out_f_roready_1121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1121 = out_wivalid_1_975 & out_wimask_1121; // @[RegisterRouter.scala:87:24] wire out_f_woready_1121 = out_woready_1_975 & out_womask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10832 = ~out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10833 = ~out_wimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10834 = ~out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10835 = ~out_womask_1121; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_961 = {hi_469, flags_0_go, _out_prepend_T_961}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10836 = out_prepend_961; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10837 = _out_T_10836; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_962 = _out_T_10837; // @[RegisterRouter.scala:87:24] wire out_rimask_1122 = \|_out_rimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_wimask_1122 = &_out_wimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_romask_1122 = \|_out_romask_T_1122; // @[RegisterRouter.scala:87:24] wire out_womask_1122 = &_out_womask_T_1122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1122 = out_rivalid_1_976 & out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10839 = out_f_rivalid_1122; // @[RegisterRouter.scala:87:24] wire out_f_roready_1122 = out_roready_1_976 & out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10840 = out_f_roready_1122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1122 = out_wivalid_1_976 & out_wimask_1122; // @[RegisterRouter.scala:87:24] wire out_f_woready_1122 = out_woready_1_976 & out_womask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10841 = ~out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10842 = ~out_wimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10843 = ~out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10844 = ~out_womask_1122; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_962 = {hi_470, flags_0_go, _out_prepend_T_962}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10845 = out_prepend_962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10846 = _out_T_10845; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_963 = _out_T_10846; // @[RegisterRouter.scala:87:24] wire out_rimask_1123 = \|_out_rimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_wimask_1123 = &_out_wimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_romask_1123 = \|_out_romask_T_1123; // @[RegisterRouter.scala:87:24] wire out_womask_1123 = &_out_womask_T_1123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1123 = out_rivalid_1_977 & out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10848 = out_f_rivalid_1123; // @[RegisterRouter.scala:87:24] wire out_f_roready_1123 = out_roready_1_977 & out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10849 = out_f_roready_1123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1123 = out_wivalid_1_977 & out_wimask_1123; // @[RegisterRouter.scala:87:24] wire out_f_woready_1123 = out_woready_1_977 & out_womask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10850 = ~out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10851 = ~out_wimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10852 = ~out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10853 = ~out_womask_1123; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_963 = {hi_471, flags_0_go, _out_prepend_T_963}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10854 = out_prepend_963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10855 = _out_T_10854; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_964 = _out_T_10855; // @[RegisterRouter.scala:87:24] wire out_rimask_1124 = \|_out_rimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_wimask_1124 = &_out_wimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_romask_1124 = \|_out_romask_T_1124; // @[RegisterRouter.scala:87:24] wire out_womask_1124 = &_out_womask_T_1124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1124 = out_rivalid_1_978 & out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10857 = out_f_rivalid_1124; // @[RegisterRouter.scala:87:24] wire out_f_roready_1124 = out_roready_1_978 & out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10858 = out_f_roready_1124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1124 = out_wivalid_1_978 & out_wimask_1124; // @[RegisterRouter.scala:87:24] wire out_f_woready_1124 = out_woready_1_978 & out_womask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10859 = ~out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10860 = ~out_wimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10861 = ~out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10862 = ~out_womask_1124; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_964 = {hi_472, flags_0_go, _out_prepend_T_964}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10863 = out_prepend_964; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10864 = _out_T_10863; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_186 = _out_T_10864; // @[MuxLiteral.scala:49:48] wire out_rimask_1125 = \|_out_rimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_wimask_1125 = &_out_wimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_romask_1125 = \|_out_romask_T_1125; // @[RegisterRouter.scala:87:24] wire out_womask_1125 = &_out_womask_T_1125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1125 = out_rivalid_1_979 & out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10866 = out_f_rivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_roready_1125 = out_roready_1_979 & out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10867 = out_f_roready_1125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1125 = out_wivalid_1_979 & out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10868 = out_f_wivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_woready_1125 = out_woready_1_979 & out_womask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10869 = out_f_woready_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10870 = ~out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10871 = ~out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10872 = ~out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10873 = ~out_womask_1125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10875 = _out_T_10874; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_965 = _out_T_10875; // @[RegisterRouter.scala:87:24] wire out_rimask_1126 = \|_out_rimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_wimask_1126 = &_out_wimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_romask_1126 = \|_out_romask_T_1126; // @[RegisterRouter.scala:87:24] wire out_womask_1126 = &_out_womask_T_1126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1126 = out_rivalid_1_980 & out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10877 = out_f_rivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_roready_1126 = out_roready_1_980 & out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10878 = out_f_roready_1126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1126 = out_wivalid_1_980 & out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10879 = out_f_wivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_woready_1126 = out_woready_1_980 & out_womask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10880 = out_f_woready_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10881 = ~out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10882 = ~out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10883 = ~out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10884 = ~out_womask_1126; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_965 = {abstractDataMem_17, _out_prepend_T_965}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10885 = out_prepend_965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10886 = _out_T_10885; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_966 = _out_T_10886; // @[RegisterRouter.scala:87:24] wire out_rimask_1127 = \|_out_rimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_wimask_1127 = &_out_wimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_romask_1127 = \|_out_romask_T_1127; // @[RegisterRouter.scala:87:24] wire out_womask_1127 = &_out_womask_T_1127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1127 = out_rivalid_1_981 & out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10888 = out_f_rivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_roready_1127 = out_roready_1_981 & out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10889 = out_f_roready_1127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1127 = out_wivalid_1_981 & out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10890 = out_f_wivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_woready_1127 = out_woready_1_981 & out_womask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10891 = out_f_woready_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10892 = ~out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10893 = ~out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10894 = ~out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10895 = ~out_womask_1127; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_966 = {abstractDataMem_18, _out_prepend_T_966}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10896 = out_prepend_966; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10897 = _out_T_10896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_967 = _out_T_10897; // @[RegisterRouter.scala:87:24] wire out_rimask_1128 = \|_out_rimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_wimask_1128 = &_out_wimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_romask_1128 = \|_out_romask_T_1128; // @[RegisterRouter.scala:87:24] wire out_womask_1128 = &_out_womask_T_1128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1128 = out_rivalid_1_982 & out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10899 = out_f_rivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_roready_1128 = out_roready_1_982 & out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10900 = out_f_roready_1128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1128 = out_wivalid_1_982 & out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10901 = out_f_wivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_woready_1128 = out_woready_1_982 & out_womask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10902 = out_f_woready_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10903 = ~out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10904 = ~out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10905 = ~out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10906 = ~out_womask_1128; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_967 = {abstractDataMem_19, _out_prepend_T_967}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10907 = out_prepend_967; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10908 = _out_T_10907; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_968 = _out_T_10908; // @[RegisterRouter.scala:87:24] wire out_rimask_1129 = \|_out_rimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_wimask_1129 = &_out_wimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_romask_1129 = \|_out_romask_T_1129; // @[RegisterRouter.scala:87:24] wire out_womask_1129 = &_out_womask_T_1129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1129 = out_rivalid_1_983 & out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10910 = out_f_rivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_roready_1129 = out_roready_1_983 & out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10911 = out_f_roready_1129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1129 = out_wivalid_1_983 & out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10912 = out_f_wivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_woready_1129 = out_woready_1_983 & out_womask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10913 = out_f_woready_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10914 = ~out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10915 = ~out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10916 = ~out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10917 = ~out_womask_1129; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_968 = {abstractDataMem_20, _out_prepend_T_968}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10918 = out_prepend_968; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10919 = _out_T_10918; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_969 = _out_T_10919; // @[RegisterRouter.scala:87:24] wire out_rimask_1130 = \|_out_rimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_wimask_1130 = &_out_wimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_romask_1130 = \|_out_romask_T_1130; // @[RegisterRouter.scala:87:24] wire out_womask_1130 = &_out_womask_T_1130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1130 = out_rivalid_1_984 & out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10921 = out_f_rivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_roready_1130 = out_roready_1_984 & out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10922 = out_f_roready_1130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1130 = out_wivalid_1_984 & out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10923 = out_f_wivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_woready_1130 = out_woready_1_984 & out_womask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10924 = out_f_woready_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10925 = ~out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10926 = ~out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10927 = ~out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10928 = ~out_womask_1130; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_969 = {abstractDataMem_21, _out_prepend_T_969}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10929 = out_prepend_969; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10930 = _out_T_10929; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_970 = _out_T_10930; // @[RegisterRouter.scala:87:24] wire out_rimask_1131 = \|_out_rimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_wimask_1131 = &_out_wimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_romask_1131 = \|_out_romask_T_1131; // @[RegisterRouter.scala:87:24] wire out_womask_1131 = &_out_womask_T_1131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1131 = out_rivalid_1_985 & out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10932 = out_f_rivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_roready_1131 = out_roready_1_985 & out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10933 = out_f_roready_1131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1131 = out_wivalid_1_985 & out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10934 = out_f_wivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_woready_1131 = out_woready_1_985 & out_womask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10935 = out_f_woready_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10936 = ~out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10937 = ~out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10938 = ~out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10939 = ~out_womask_1131; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_970 = {abstractDataMem_22, _out_prepend_T_970}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10940 = out_prepend_970; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10941 = _out_T_10940; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_971 = _out_T_10941; // @[RegisterRouter.scala:87:24] wire out_rimask_1132 = \|_out_rimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_wimask_1132 = &_out_wimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_romask_1132 = \|_out_romask_T_1132; // @[RegisterRouter.scala:87:24] wire out_womask_1132 = &_out_womask_T_1132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1132 = out_rivalid_1_986 & out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10943 = out_f_rivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_roready_1132 = out_roready_1_986 & out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10944 = out_f_roready_1132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1132 = out_wivalid_1_986 & out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10945 = out_f_wivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_woready_1132 = out_woready_1_986 & out_womask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10946 = out_f_woready_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10947 = ~out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10948 = ~out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10949 = ~out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10950 = ~out_womask_1132; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_971 = {abstractDataMem_23, _out_prepend_T_971}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10951 = out_prepend_971; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10952 = _out_T_10951; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_114 = _out_T_10952; // @[MuxLiteral.scala:49:48] wire out_rimask_1133 = \|_out_rimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_wimask_1133 = &_out_wimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_romask_1133 = \|_out_romask_T_1133; // @[RegisterRouter.scala:87:24] wire out_womask_1133 = &_out_womask_T_1133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1133 = out_rivalid_1_987 & out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10954 = out_f_rivalid_1133; // @[RegisterRouter.scala:87:24] wire out_f_roready_1133 = out_roready_1_987 & out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10955 = out_f_roready_1133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1133 = out_wivalid_1_987 & out_wimask_1133; // @[RegisterRouter.scala:87:24] wire out_f_woready_1133 = out_woready_1_987 & out_womask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10956 = ~out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10957 = ~out_wimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10958 = ~out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10959 = ~out_womask_1133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10961 = _out_T_10960; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_972 = _out_T_10961; // @[RegisterRouter.scala:87:24] wire out_rimask_1134 = \|_out_rimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_wimask_1134 = &_out_wimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_romask_1134 = \|_out_romask_T_1134; // @[RegisterRouter.scala:87:24] wire out_womask_1134 = &_out_womask_T_1134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1134 = out_rivalid_1_988 & out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10963 = out_f_rivalid_1134; // @[RegisterRouter.scala:87:24] wire out_f_roready_1134 = out_roready_1_988 & out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10964 = out_f_roready_1134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1134 = out_wivalid_1_988 & out_wimask_1134; // @[RegisterRouter.scala:87:24] wire out_f_woready_1134 = out_woready_1_988 & out_womask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10965 = ~out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10966 = ~out_wimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10967 = ~out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10968 = ~out_womask_1134; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_972 = {hi_346, flags_0_go, _out_prepend_T_972}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10969 = out_prepend_972; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10970 = _out_T_10969; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_973 = _out_T_10970; // @[RegisterRouter.scala:87:24] wire out_rimask_1135 = \|_out_rimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_wimask_1135 = &_out_wimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_romask_1135 = \|_out_romask_T_1135; // @[RegisterRouter.scala:87:24] wire out_womask_1135 = &_out_womask_T_1135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1135 = out_rivalid_1_989 & out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10972 = out_f_rivalid_1135; // @[RegisterRouter.scala:87:24] wire out_f_roready_1135 = out_roready_1_989 & out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10973 = out_f_roready_1135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1135 = out_wivalid_1_989 & out_wimask_1135; // @[RegisterRouter.scala:87:24] wire out_f_woready_1135 = out_woready_1_989 & out_womask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10974 = ~out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10975 = ~out_wimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10976 = ~out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10977 = ~out_womask_1135; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_973 = {hi_347, flags_0_go, _out_prepend_T_973}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10978 = out_prepend_973; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10979 = _out_T_10978; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_974 = _out_T_10979; // @[RegisterRouter.scala:87:24] wire out_rimask_1136 = \|_out_rimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_wimask_1136 = &_out_wimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_romask_1136 = \|_out_romask_T_1136; // @[RegisterRouter.scala:87:24] wire out_womask_1136 = &_out_womask_T_1136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1136 = out_rivalid_1_990 & out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10981 = out_f_rivalid_1136; // @[RegisterRouter.scala:87:24] wire out_f_roready_1136 = out_roready_1_990 & out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10982 = out_f_roready_1136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1136 = out_wivalid_1_990 & out_wimask_1136; // @[RegisterRouter.scala:87:24] wire out_f_woready_1136 = out_woready_1_990 & out_womask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10983 = ~out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10984 = ~out_wimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10985 = ~out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10986 = ~out_womask_1136; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_974 = {hi_348, flags_0_go, _out_prepend_T_974}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10987 = out_prepend_974; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10988 = _out_T_10987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_975 = _out_T_10988; // @[RegisterRouter.scala:87:24] wire out_rimask_1137 = \|_out_rimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_wimask_1137 = &_out_wimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_romask_1137 = \|_out_romask_T_1137; // @[RegisterRouter.scala:87:24] wire out_womask_1137 = &_out_womask_T_1137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1137 = out_rivalid_1_991 & out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10990 = out_f_rivalid_1137; // @[RegisterRouter.scala:87:24] wire out_f_roready_1137 = out_roready_1_991 & out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10991 = out_f_roready_1137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1137 = out_wivalid_1_991 & out_wimask_1137; // @[RegisterRouter.scala:87:24] wire out_f_woready_1137 = out_woready_1_991 & out_womask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10992 = ~out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10993 = ~out_wimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10994 = ~out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10995 = ~out_womask_1137; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_975 = {hi_349, flags_0_go, _out_prepend_T_975}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10996 = out_prepend_975; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10997 = _out_T_10996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_976 = _out_T_10997; // @[RegisterRouter.scala:87:24] wire out_rimask_1138 = \|_out_rimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_wimask_1138 = &_out_wimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_romask_1138 = \|_out_romask_T_1138; // @[RegisterRouter.scala:87:24] wire out_womask_1138 = &_out_womask_T_1138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1138 = out_rivalid_1_992 & out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_10999 = out_f_rivalid_1138; // @[RegisterRouter.scala:87:24] wire out_f_roready_1138 = out_roready_1_992 & out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11000 = out_f_roready_1138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1138 = out_wivalid_1_992 & out_wimask_1138; // @[RegisterRouter.scala:87:24] wire out_f_woready_1138 = out_woready_1_992 & out_womask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11001 = ~out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11002 = ~out_wimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11003 = ~out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11004 = ~out_womask_1138; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_976 = {hi_350, flags_0_go, _out_prepend_T_976}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11005 = out_prepend_976; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11006 = _out_T_11005; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_977 = _out_T_11006; // @[RegisterRouter.scala:87:24] wire out_rimask_1139 = \|_out_rimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_wimask_1139 = &_out_wimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_romask_1139 = \|_out_romask_T_1139; // @[RegisterRouter.scala:87:24] wire out_womask_1139 = &_out_womask_T_1139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1139 = out_rivalid_1_993 & out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11008 = out_f_rivalid_1139; // @[RegisterRouter.scala:87:24] wire out_f_roready_1139 = out_roready_1_993 & out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11009 = out_f_roready_1139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1139 = out_wivalid_1_993 & out_wimask_1139; // @[RegisterRouter.scala:87:24] wire out_f_woready_1139 = out_woready_1_993 & out_womask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11010 = ~out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11011 = ~out_wimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11012 = ~out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11013 = ~out_womask_1139; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_977 = {hi_351, flags_0_go, _out_prepend_T_977}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11014 = out_prepend_977; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11015 = _out_T_11014; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_978 = _out_T_11015; // @[RegisterRouter.scala:87:24] wire out_rimask_1140 = \|_out_rimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_wimask_1140 = &_out_wimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_romask_1140 = \|_out_romask_T_1140; // @[RegisterRouter.scala:87:24] wire out_womask_1140 = &_out_womask_T_1140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1140 = out_rivalid_1_994 & out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11017 = out_f_rivalid_1140; // @[RegisterRouter.scala:87:24] wire out_f_roready_1140 = out_roready_1_994 & out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11018 = out_f_roready_1140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1140 = out_wivalid_1_994 & out_wimask_1140; // @[RegisterRouter.scala:87:24] wire out_f_woready_1140 = out_woready_1_994 & out_womask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11019 = ~out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11020 = ~out_wimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11021 = ~out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11022 = ~out_womask_1140; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_978 = {hi_352, flags_0_go, _out_prepend_T_978}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11023 = out_prepend_978; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11024 = _out_T_11023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_171 = _out_T_11024; // @[MuxLiteral.scala:49:48] wire out_rimask_1141 = \|_out_rimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_wimask_1141 = &_out_wimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_romask_1141 = \|_out_romask_T_1141; // @[RegisterRouter.scala:87:24] wire out_womask_1141 = &_out_womask_T_1141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1141 = out_rivalid_1_995 & out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11026 = out_f_rivalid_1141; // @[RegisterRouter.scala:87:24] wire out_f_roready_1141 = out_roready_1_995 & out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11027 = out_f_roready_1141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1141 = out_wivalid_1_995 & out_wimask_1141; // @[RegisterRouter.scala:87:24] wire out_f_woready_1141 = out_woready_1_995 & out_womask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11028 = ~out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11029 = ~out_wimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11030 = ~out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11031 = ~out_womask_1141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11033 = _out_T_11032; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_979 = _out_T_11033; // @[RegisterRouter.scala:87:24] wire out_rimask_1142 = \|_out_rimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_wimask_1142 = &_out_wimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_romask_1142 = \|_out_romask_T_1142; // @[RegisterRouter.scala:87:24] wire out_womask_1142 = &_out_womask_T_1142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1142 = out_rivalid_1_996 & out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11035 = out_f_rivalid_1142; // @[RegisterRouter.scala:87:24] wire out_f_roready_1142 = out_roready_1_996 & out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11036 = out_f_roready_1142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1142 = out_wivalid_1_996 & out_wimask_1142; // @[RegisterRouter.scala:87:24] wire out_f_woready_1142 = out_woready_1_996 & out_womask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11037 = ~out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11038 = ~out_wimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11039 = ~out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11040 = ~out_womask_1142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_979 = {hi_90, flags_0_go, _out_prepend_T_979}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11041 = out_prepend_979; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11042 = _out_T_11041; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_980 = _out_T_11042; // @[RegisterRouter.scala:87:24] wire out_rimask_1143 = \|_out_rimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_wimask_1143 = &_out_wimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_romask_1143 = \|_out_romask_T_1143; // @[RegisterRouter.scala:87:24] wire out_womask_1143 = &_out_womask_T_1143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1143 = out_rivalid_1_997 & out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11044 = out_f_rivalid_1143; // @[RegisterRouter.scala:87:24] wire out_f_roready_1143 = out_roready_1_997 & out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11045 = out_f_roready_1143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1143 = out_wivalid_1_997 & out_wimask_1143; // @[RegisterRouter.scala:87:24] wire out_f_woready_1143 = out_woready_1_997 & out_womask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11046 = ~out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11047 = ~out_wimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11048 = ~out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11049 = ~out_womask_1143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_980 = {hi_91, flags_0_go, _out_prepend_T_980}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11050 = out_prepend_980; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11051 = _out_T_11050; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_981 = _out_T_11051; // @[RegisterRouter.scala:87:24] wire out_rimask_1144 = \|_out_rimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_wimask_1144 = &_out_wimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_romask_1144 = \|_out_romask_T_1144; // @[RegisterRouter.scala:87:24] wire out_womask_1144 = &_out_womask_T_1144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1144 = out_rivalid_1_998 & out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11053 = out_f_rivalid_1144; // @[RegisterRouter.scala:87:24] wire out_f_roready_1144 = out_roready_1_998 & out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11054 = out_f_roready_1144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1144 = out_wivalid_1_998 & out_wimask_1144; // @[RegisterRouter.scala:87:24] wire out_f_woready_1144 = out_woready_1_998 & out_womask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11055 = ~out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11056 = ~out_wimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11057 = ~out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11058 = ~out_womask_1144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_981 = {hi_92, flags_0_go, _out_prepend_T_981}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11059 = out_prepend_981; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11060 = _out_T_11059; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_982 = _out_T_11060; // @[RegisterRouter.scala:87:24] wire out_rimask_1145 = \|_out_rimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_wimask_1145 = &_out_wimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_romask_1145 = \|_out_romask_T_1145; // @[RegisterRouter.scala:87:24] wire out_womask_1145 = &_out_womask_T_1145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1145 = out_rivalid_1_999 & out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11062 = out_f_rivalid_1145; // @[RegisterRouter.scala:87:24] wire out_f_roready_1145 = out_roready_1_999 & out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11063 = out_f_roready_1145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1145 = out_wivalid_1_999 & out_wimask_1145; // @[RegisterRouter.scala:87:24] wire out_f_woready_1145 = out_woready_1_999 & out_womask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11064 = ~out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11065 = ~out_wimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11066 = ~out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11067 = ~out_womask_1145; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_982 = {hi_93, flags_0_go, _out_prepend_T_982}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11068 = out_prepend_982; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11069 = _out_T_11068; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_983 = _out_T_11069; // @[RegisterRouter.scala:87:24] wire out_rimask_1146 = \|_out_rimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_wimask_1146 = &_out_wimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_romask_1146 = \|_out_romask_T_1146; // @[RegisterRouter.scala:87:24] wire out_womask_1146 = &_out_womask_T_1146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1146 = out_rivalid_1_1000 & out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11071 = out_f_rivalid_1146; // @[RegisterRouter.scala:87:24] wire out_f_roready_1146 = out_roready_1_1000 & out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11072 = out_f_roready_1146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1146 = out_wivalid_1_1000 & out_wimask_1146; // @[RegisterRouter.scala:87:24] wire out_f_woready_1146 = out_woready_1_1000 & out_womask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11073 = ~out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11074 = ~out_wimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11075 = ~out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11076 = ~out_womask_1146; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_983 = {hi_94, flags_0_go, _out_prepend_T_983}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11077 = out_prepend_983; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11078 = _out_T_11077; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_984 = _out_T_11078; // @[RegisterRouter.scala:87:24] wire out_rimask_1147 = \|_out_rimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_wimask_1147 = &_out_wimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_romask_1147 = \|_out_romask_T_1147; // @[RegisterRouter.scala:87:24] wire out_womask_1147 = &_out_womask_T_1147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1147 = out_rivalid_1_1001 & out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11080 = out_f_rivalid_1147; // @[RegisterRouter.scala:87:24] wire out_f_roready_1147 = out_roready_1_1001 & out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11081 = out_f_roready_1147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1147 = out_wivalid_1_1001 & out_wimask_1147; // @[RegisterRouter.scala:87:24] wire out_f_woready_1147 = out_woready_1_1001 & out_womask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11082 = ~out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11083 = ~out_wimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11084 = ~out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11085 = ~out_womask_1147; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_984 = {hi_95, flags_0_go, _out_prepend_T_984}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11086 = out_prepend_984; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11087 = _out_T_11086; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_985 = _out_T_11087; // @[RegisterRouter.scala:87:24] wire out_rimask_1148 = \|_out_rimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_wimask_1148 = &_out_wimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_romask_1148 = \|_out_romask_T_1148; // @[RegisterRouter.scala:87:24] wire out_womask_1148 = &_out_womask_T_1148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1148 = out_rivalid_1_1002 & out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11089 = out_f_rivalid_1148; // @[RegisterRouter.scala:87:24] wire out_f_roready_1148 = out_roready_1_1002 & out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11090 = out_f_roready_1148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1148 = out_wivalid_1_1002 & out_wimask_1148; // @[RegisterRouter.scala:87:24] wire out_f_woready_1148 = out_woready_1_1002 & out_womask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11091 = ~out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11092 = ~out_wimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11093 = ~out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11094 = ~out_womask_1148; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_985 = {hi_96, flags_0_go, _out_prepend_T_985}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11095 = out_prepend_985; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11096 = _out_T_11095; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_139 = _out_T_11096; // @[MuxLiteral.scala:49:48] wire out_rimask_1149 = \|_out_rimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_wimask_1149 = &_out_wimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_romask_1149 = \|_out_romask_T_1149; // @[RegisterRouter.scala:87:24] wire out_womask_1149 = &_out_womask_T_1149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1149 = out_rivalid_1_1003 & out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11098 = out_f_rivalid_1149; // @[RegisterRouter.scala:87:24] wire out_f_roready_1149 = out_roready_1_1003 & out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11099 = out_f_roready_1149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1149 = out_wivalid_1_1003 & out_wimask_1149; // @[RegisterRouter.scala:87:24] wire out_f_woready_1149 = out_woready_1_1003 & out_womask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11100 = ~out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11101 = ~out_wimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11102 = ~out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11103 = ~out_womask_1149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11105 = _out_T_11104; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_986 = _out_T_11105; // @[RegisterRouter.scala:87:24] wire out_rimask_1150 = \|_out_rimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_wimask_1150 = &_out_wimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_romask_1150 = \|_out_romask_T_1150; // @[RegisterRouter.scala:87:24] wire out_womask_1150 = &_out_womask_T_1150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1150 = out_rivalid_1_1004 & out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11107 = out_f_rivalid_1150; // @[RegisterRouter.scala:87:24] wire out_f_roready_1150 = out_roready_1_1004 & out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11108 = out_f_roready_1150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1150 = out_wivalid_1_1004 & out_wimask_1150; // @[RegisterRouter.scala:87:24] wire out_f_woready_1150 = out_woready_1_1004 & out_womask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11109 = ~out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11110 = ~out_wimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11111 = ~out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11112 = ~out_womask_1150; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_986 = {hi_634, flags_0_go, _out_prepend_T_986}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11113 = out_prepend_986; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11114 = _out_T_11113; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_987 = _out_T_11114; // @[RegisterRouter.scala:87:24] wire out_rimask_1151 = \|_out_rimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_wimask_1151 = &_out_wimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_romask_1151 = \|_out_romask_T_1151; // @[RegisterRouter.scala:87:24] wire out_womask_1151 = &_out_womask_T_1151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1151 = out_rivalid_1_1005 & out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11116 = out_f_rivalid_1151; // @[RegisterRouter.scala:87:24] wire out_f_roready_1151 = out_roready_1_1005 & out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11117 = out_f_roready_1151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1151 = out_wivalid_1_1005 & out_wimask_1151; // @[RegisterRouter.scala:87:24] wire out_f_woready_1151 = out_woready_1_1005 & out_womask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11118 = ~out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11119 = ~out_wimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11120 = ~out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11121 = ~out_womask_1151; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_987 = {hi_635, flags_0_go, _out_prepend_T_987}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11122 = out_prepend_987; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11123 = _out_T_11122; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_988 = _out_T_11123; // @[RegisterRouter.scala:87:24] wire out_rimask_1152 = \|_out_rimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_wimask_1152 = &_out_wimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_romask_1152 = \|_out_romask_T_1152; // @[RegisterRouter.scala:87:24] wire out_womask_1152 = &_out_womask_T_1152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1152 = out_rivalid_1_1006 & out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11125 = out_f_rivalid_1152; // @[RegisterRouter.scala:87:24] wire out_f_roready_1152 = out_roready_1_1006 & out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11126 = out_f_roready_1152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1152 = out_wivalid_1_1006 & out_wimask_1152; // @[RegisterRouter.scala:87:24] wire out_f_woready_1152 = out_woready_1_1006 & out_womask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11127 = ~out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11128 = ~out_wimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11129 = ~out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11130 = ~out_womask_1152; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_988 = {hi_636, flags_0_go, _out_prepend_T_988}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11131 = out_prepend_988; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11132 = _out_T_11131; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_989 = _out_T_11132; // @[RegisterRouter.scala:87:24] wire out_rimask_1153 = \|_out_rimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_wimask_1153 = &_out_wimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_romask_1153 = \|_out_romask_T_1153; // @[RegisterRouter.scala:87:24] wire out_womask_1153 = &_out_womask_T_1153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1153 = out_rivalid_1_1007 & out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11134 = out_f_rivalid_1153; // @[RegisterRouter.scala:87:24] wire out_f_roready_1153 = out_roready_1_1007 & out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11135 = out_f_roready_1153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1153 = out_wivalid_1_1007 & out_wimask_1153; // @[RegisterRouter.scala:87:24] wire out_f_woready_1153 = out_woready_1_1007 & out_womask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11136 = ~out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11137 = ~out_wimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11138 = ~out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11139 = ~out_womask_1153; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_989 = {hi_637, flags_0_go, _out_prepend_T_989}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11140 = out_prepend_989; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11141 = _out_T_11140; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_990 = _out_T_11141; // @[RegisterRouter.scala:87:24] wire out_rimask_1154 = \|_out_rimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_wimask_1154 = &_out_wimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_romask_1154 = \|_out_romask_T_1154; // @[RegisterRouter.scala:87:24] wire out_womask_1154 = &_out_womask_T_1154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1154 = out_rivalid_1_1008 & out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11143 = out_f_rivalid_1154; // @[RegisterRouter.scala:87:24] wire out_f_roready_1154 = out_roready_1_1008 & out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11144 = out_f_roready_1154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1154 = out_wivalid_1_1008 & out_wimask_1154; // @[RegisterRouter.scala:87:24] wire out_f_woready_1154 = out_woready_1_1008 & out_womask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11145 = ~out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11146 = ~out_wimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11147 = ~out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11148 = ~out_womask_1154; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_990 = {hi_638, flags_0_go, _out_prepend_T_990}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11149 = out_prepend_990; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11150 = _out_T_11149; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_991 = _out_T_11150; // @[RegisterRouter.scala:87:24] wire out_rimask_1155 = \|_out_rimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_wimask_1155 = &_out_wimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_romask_1155 = \|_out_romask_T_1155; // @[RegisterRouter.scala:87:24] wire out_womask_1155 = &_out_womask_T_1155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1155 = out_rivalid_1_1009 & out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11152 = out_f_rivalid_1155; // @[RegisterRouter.scala:87:24] wire out_f_roready_1155 = out_roready_1_1009 & out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11153 = out_f_roready_1155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1155 = out_wivalid_1_1009 & out_wimask_1155; // @[RegisterRouter.scala:87:24] wire out_f_woready_1155 = out_woready_1_1009 & out_womask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11154 = ~out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11155 = ~out_wimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11156 = ~out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11157 = ~out_womask_1155; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_991 = {hi_639, flags_0_go, _out_prepend_T_991}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11158 = out_prepend_991; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11159 = _out_T_11158; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_992 = _out_T_11159; // @[RegisterRouter.scala:87:24] wire out_rimask_1156 = \|_out_rimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_wimask_1156 = &_out_wimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_romask_1156 = \|_out_romask_T_1156; // @[RegisterRouter.scala:87:24] wire out_womask_1156 = &_out_womask_T_1156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1156 = out_rivalid_1_1010 & out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11161 = out_f_rivalid_1156; // @[RegisterRouter.scala:87:24] wire out_f_roready_1156 = out_roready_1_1010 & out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11162 = out_f_roready_1156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1156 = out_wivalid_1_1010 & out_wimask_1156; // @[RegisterRouter.scala:87:24] wire out_f_woready_1156 = out_woready_1_1010 & out_womask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11163 = ~out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11164 = ~out_wimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11165 = ~out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11166 = ~out_womask_1156; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_992 = {hi_640, flags_0_go, _out_prepend_T_992}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11167 = out_prepend_992; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11168 = _out_T_11167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_207 = _out_T_11168; // @[MuxLiteral.scala:49:48] wire out_rimask_1157 = \|_out_rimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_wimask_1157 = &_out_wimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_romask_1157 = \|_out_romask_T_1157; // @[RegisterRouter.scala:87:24] wire out_womask_1157 = &_out_womask_T_1157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1157 = out_rivalid_1_1011 & out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11170 = out_f_rivalid_1157; // @[RegisterRouter.scala:87:24] wire out_f_roready_1157 = out_roready_1_1011 & out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11171 = out_f_roready_1157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1157 = out_wivalid_1_1011 & out_wimask_1157; // @[RegisterRouter.scala:87:24] wire out_f_woready_1157 = out_woready_1_1011 & out_womask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11172 = ~out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11173 = ~out_wimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11174 = ~out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11175 = ~out_womask_1157; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11177 = _out_T_11176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_993 = _out_T_11177; // @[RegisterRouter.scala:87:24] wire out_rimask_1158 = \|_out_rimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_wimask_1158 = &_out_wimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_romask_1158 = \|_out_romask_T_1158; // @[RegisterRouter.scala:87:24] wire out_womask_1158 = &_out_womask_T_1158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1158 = out_rivalid_1_1012 & out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11179 = out_f_rivalid_1158; // @[RegisterRouter.scala:87:24] wire out_f_roready_1158 = out_roready_1_1012 & out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11180 = out_f_roready_1158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1158 = out_wivalid_1_1012 & out_wimask_1158; // @[RegisterRouter.scala:87:24] wire out_f_woready_1158 = out_woready_1_1012 & out_womask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11181 = ~out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11182 = ~out_wimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11183 = ~out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11184 = ~out_womask_1158; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_993 = {hi_690, flags_0_go, _out_prepend_T_993}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11185 = out_prepend_993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11186 = _out_T_11185; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_994 = _out_T_11186; // @[RegisterRouter.scala:87:24] wire out_rimask_1159 = \|_out_rimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_wimask_1159 = &_out_wimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_romask_1159 = \|_out_romask_T_1159; // @[RegisterRouter.scala:87:24] wire out_womask_1159 = &_out_womask_T_1159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1159 = out_rivalid_1_1013 & out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11188 = out_f_rivalid_1159; // @[RegisterRouter.scala:87:24] wire out_f_roready_1159 = out_roready_1_1013 & out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11189 = out_f_roready_1159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1159 = out_wivalid_1_1013 & out_wimask_1159; // @[RegisterRouter.scala:87:24] wire out_f_woready_1159 = out_woready_1_1013 & out_womask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11190 = ~out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11191 = ~out_wimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11192 = ~out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11193 = ~out_womask_1159; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_994 = {hi_691, flags_0_go, _out_prepend_T_994}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11194 = out_prepend_994; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11195 = _out_T_11194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_995 = _out_T_11195; // @[RegisterRouter.scala:87:24] wire out_rimask_1160 = \|_out_rimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_wimask_1160 = &_out_wimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_romask_1160 = \|_out_romask_T_1160; // @[RegisterRouter.scala:87:24] wire out_womask_1160 = &_out_womask_T_1160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1160 = out_rivalid_1_1014 & out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11197 = out_f_rivalid_1160; // @[RegisterRouter.scala:87:24] wire out_f_roready_1160 = out_roready_1_1014 & out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11198 = out_f_roready_1160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1160 = out_wivalid_1_1014 & out_wimask_1160; // @[RegisterRouter.scala:87:24] wire out_f_woready_1160 = out_woready_1_1014 & out_womask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11199 = ~out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11200 = ~out_wimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11201 = ~out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11202 = ~out_womask_1160; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_995 = {hi_692, flags_0_go, _out_prepend_T_995}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11203 = out_prepend_995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11204 = _out_T_11203; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_996 = _out_T_11204; // @[RegisterRouter.scala:87:24] wire out_rimask_1161 = \|_out_rimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_wimask_1161 = &_out_wimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_romask_1161 = \|_out_romask_T_1161; // @[RegisterRouter.scala:87:24] wire out_womask_1161 = &_out_womask_T_1161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1161 = out_rivalid_1_1015 & out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11206 = out_f_rivalid_1161; // @[RegisterRouter.scala:87:24] wire out_f_roready_1161 = out_roready_1_1015 & out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11207 = out_f_roready_1161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1161 = out_wivalid_1_1015 & out_wimask_1161; // @[RegisterRouter.scala:87:24] wire out_f_woready_1161 = out_woready_1_1015 & out_womask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11208 = ~out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11209 = ~out_wimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11210 = ~out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11211 = ~out_womask_1161; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_996 = {hi_693, flags_0_go, _out_prepend_T_996}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11212 = out_prepend_996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11213 = _out_T_11212; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_997 = _out_T_11213; // @[RegisterRouter.scala:87:24] wire out_rimask_1162 = \|_out_rimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_wimask_1162 = &_out_wimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_romask_1162 = \|_out_romask_T_1162; // @[RegisterRouter.scala:87:24] wire out_womask_1162 = &_out_womask_T_1162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1162 = out_rivalid_1_1016 & out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11215 = out_f_rivalid_1162; // @[RegisterRouter.scala:87:24] wire out_f_roready_1162 = out_roready_1_1016 & out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11216 = out_f_roready_1162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1162 = out_wivalid_1_1016 & out_wimask_1162; // @[RegisterRouter.scala:87:24] wire out_f_woready_1162 = out_woready_1_1016 & out_womask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11217 = ~out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11218 = ~out_wimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11219 = ~out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11220 = ~out_womask_1162; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_997 = {hi_694, flags_0_go, _out_prepend_T_997}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11221 = out_prepend_997; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11222 = _out_T_11221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_998 = _out_T_11222; // @[RegisterRouter.scala:87:24] wire out_rimask_1163 = \|_out_rimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_wimask_1163 = &_out_wimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_romask_1163 = \|_out_romask_T_1163; // @[RegisterRouter.scala:87:24] wire out_womask_1163 = &_out_womask_T_1163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1163 = out_rivalid_1_1017 & out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11224 = out_f_rivalid_1163; // @[RegisterRouter.scala:87:24] wire out_f_roready_1163 = out_roready_1_1017 & out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11225 = out_f_roready_1163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1163 = out_wivalid_1_1017 & out_wimask_1163; // @[RegisterRouter.scala:87:24] wire out_f_woready_1163 = out_woready_1_1017 & out_womask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11226 = ~out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11227 = ~out_wimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11228 = ~out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11229 = ~out_womask_1163; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_998 = {hi_695, flags_0_go, _out_prepend_T_998}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11230 = out_prepend_998; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11231 = _out_T_11230; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_999 = _out_T_11231; // @[RegisterRouter.scala:87:24] wire out_rimask_1164 = \|_out_rimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_wimask_1164 = &_out_wimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_romask_1164 = \|_out_romask_T_1164; // @[RegisterRouter.scala:87:24] wire out_womask_1164 = &_out_womask_T_1164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1164 = out_rivalid_1_1018 & out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11233 = out_f_rivalid_1164; // @[RegisterRouter.scala:87:24] wire out_f_roready_1164 = out_roready_1_1018 & out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11234 = out_f_roready_1164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1164 = out_wivalid_1_1018 & out_wimask_1164; // @[RegisterRouter.scala:87:24] wire out_f_woready_1164 = out_woready_1_1018 & out_womask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11235 = ~out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11236 = ~out_wimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11237 = ~out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11238 = ~out_womask_1164; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_999 = {hi_696, flags_0_go, _out_prepend_T_999}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11239 = out_prepend_999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11240 = _out_T_11239; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_214 = _out_T_11240; // @[MuxLiteral.scala:49:48] wire out_rimask_1165 = \|_out_rimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_wimask_1165 = &_out_wimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_romask_1165 = \|_out_romask_T_1165; // @[RegisterRouter.scala:87:24] wire out_womask_1165 = &_out_womask_T_1165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1165 = out_rivalid_1_1019 & out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11242 = out_f_rivalid_1165; // @[RegisterRouter.scala:87:24] wire out_f_roready_1165 = out_roready_1_1019 & out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11243 = out_f_roready_1165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1165 = out_wivalid_1_1019 & out_wimask_1165; // @[RegisterRouter.scala:87:24] wire out_f_woready_1165 = out_woready_1_1019 & out_womask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11244 = ~out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11245 = ~out_wimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11246 = ~out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11247 = ~out_womask_1165; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11249 = _out_T_11248; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1000 = _out_T_11249; // @[RegisterRouter.scala:87:24] wire out_rimask_1166 = \|_out_rimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_wimask_1166 = &_out_wimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_romask_1166 = \|_out_romask_T_1166; // @[RegisterRouter.scala:87:24] wire out_womask_1166 = &_out_womask_T_1166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1166 = out_rivalid_1_1020 & out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11251 = out_f_rivalid_1166; // @[RegisterRouter.scala:87:24] wire out_f_roready_1166 = out_roready_1_1020 & out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11252 = out_f_roready_1166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1166 = out_wivalid_1_1020 & out_wimask_1166; // @[RegisterRouter.scala:87:24] wire out_f_woready_1166 = out_woready_1_1020 & out_womask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11253 = ~out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11254 = ~out_wimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11255 = ~out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11256 = ~out_womask_1166; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1000 = {hi_858, flags_0_go, _out_prepend_T_1000}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11257 = out_prepend_1000; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11258 = _out_T_11257; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1001 = _out_T_11258; // @[RegisterRouter.scala:87:24] wire out_rimask_1167 = \|_out_rimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_wimask_1167 = &_out_wimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_romask_1167 = \|_out_romask_T_1167; // @[RegisterRouter.scala:87:24] wire out_womask_1167 = &_out_womask_T_1167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1167 = out_rivalid_1_1021 & out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11260 = out_f_rivalid_1167; // @[RegisterRouter.scala:87:24] wire out_f_roready_1167 = out_roready_1_1021 & out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11261 = out_f_roready_1167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1167 = out_wivalid_1_1021 & out_wimask_1167; // @[RegisterRouter.scala:87:24] wire out_f_woready_1167 = out_woready_1_1021 & out_womask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11262 = ~out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11263 = ~out_wimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11264 = ~out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11265 = ~out_womask_1167; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1001 = {hi_859, flags_0_go, _out_prepend_T_1001}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11266 = out_prepend_1001; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11267 = _out_T_11266; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1002 = _out_T_11267; // @[RegisterRouter.scala:87:24] wire out_rimask_1168 = \|_out_rimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_wimask_1168 = &_out_wimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_romask_1168 = \|_out_romask_T_1168; // @[RegisterRouter.scala:87:24] wire out_womask_1168 = &_out_womask_T_1168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1168 = out_rivalid_1_1022 & out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11269 = out_f_rivalid_1168; // @[RegisterRouter.scala:87:24] wire out_f_roready_1168 = out_roready_1_1022 & out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11270 = out_f_roready_1168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1168 = out_wivalid_1_1022 & out_wimask_1168; // @[RegisterRouter.scala:87:24] wire out_f_woready_1168 = out_woready_1_1022 & out_womask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11271 = ~out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11272 = ~out_wimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11273 = ~out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11274 = ~out_womask_1168; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1002 = {hi_860, flags_0_go, _out_prepend_T_1002}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11275 = out_prepend_1002; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11276 = _out_T_11275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1003 = _out_T_11276; // @[RegisterRouter.scala:87:24] wire out_rimask_1169 = \|_out_rimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_wimask_1169 = &_out_wimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_romask_1169 = \|_out_romask_T_1169; // @[RegisterRouter.scala:87:24] wire out_womask_1169 = &_out_womask_T_1169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1169 = out_rivalid_1_1023 & out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11278 = out_f_rivalid_1169; // @[RegisterRouter.scala:87:24] wire out_f_roready_1169 = out_roready_1_1023 & out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11279 = out_f_roready_1169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1169 = out_wivalid_1_1023 & out_wimask_1169; // @[RegisterRouter.scala:87:24] wire out_f_woready_1169 = out_woready_1_1023 & out_womask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11280 = ~out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11281 = ~out_wimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11282 = ~out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11283 = ~out_womask_1169; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1003 = {hi_861, flags_0_go, _out_prepend_T_1003}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11284 = out_prepend_1003; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11285 = _out_T_11284; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1004 = _out_T_11285; // @[RegisterRouter.scala:87:24] wire out_rimask_1170 = \|_out_rimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_wimask_1170 = &_out_wimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_romask_1170 = \|_out_romask_T_1170; // @[RegisterRouter.scala:87:24] wire out_womask_1170 = &_out_womask_T_1170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1170 = out_rivalid_1_1024 & out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11287 = out_f_rivalid_1170; // @[RegisterRouter.scala:87:24] wire out_f_roready_1170 = out_roready_1_1024 & out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11288 = out_f_roready_1170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1170 = out_wivalid_1_1024 & out_wimask_1170; // @[RegisterRouter.scala:87:24] wire out_f_woready_1170 = out_woready_1_1024 & out_womask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11289 = ~out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11290 = ~out_wimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11291 = ~out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11292 = ~out_womask_1170; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1004 = {hi_862, flags_0_go, _out_prepend_T_1004}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11293 = out_prepend_1004; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11294 = _out_T_11293; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1005 = _out_T_11294; // @[RegisterRouter.scala:87:24] wire out_rimask_1171 = \|_out_rimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_wimask_1171 = &_out_wimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_romask_1171 = \|_out_romask_T_1171; // @[RegisterRouter.scala:87:24] wire out_womask_1171 = &_out_womask_T_1171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1171 = out_rivalid_1_1025 & out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11296 = out_f_rivalid_1171; // @[RegisterRouter.scala:87:24] wire out_f_roready_1171 = out_roready_1_1025 & out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11297 = out_f_roready_1171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1171 = out_wivalid_1_1025 & out_wimask_1171; // @[RegisterRouter.scala:87:24] wire out_f_woready_1171 = out_woready_1_1025 & out_womask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11298 = ~out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11299 = ~out_wimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11300 = ~out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11301 = ~out_womask_1171; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1005 = {hi_863, flags_0_go, _out_prepend_T_1005}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11302 = out_prepend_1005; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11303 = _out_T_11302; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1006 = _out_T_11303; // @[RegisterRouter.scala:87:24] wire out_rimask_1172 = \|_out_rimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_wimask_1172 = &_out_wimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_romask_1172 = \|_out_romask_T_1172; // @[RegisterRouter.scala:87:24] wire out_womask_1172 = &_out_womask_T_1172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1172 = out_rivalid_1_1026 & out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11305 = out_f_rivalid_1172; // @[RegisterRouter.scala:87:24] wire out_f_roready_1172 = out_roready_1_1026 & out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11306 = out_f_roready_1172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1172 = out_wivalid_1_1026 & out_wimask_1172; // @[RegisterRouter.scala:87:24] wire out_f_woready_1172 = out_woready_1_1026 & out_womask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11307 = ~out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11308 = ~out_wimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11309 = ~out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11310 = ~out_womask_1172; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1006 = {hi_864, flags_0_go, _out_prepend_T_1006}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11311 = out_prepend_1006; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11312 = _out_T_11311; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_235 = _out_T_11312; // @[MuxLiteral.scala:49:48] wire out_rimask_1173 = \|_out_rimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_wimask_1173 = &_out_wimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_romask_1173 = \|_out_romask_T_1173; // @[RegisterRouter.scala:87:24] wire out_womask_1173 = &_out_womask_T_1173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1173 = out_rivalid_1_1027 & out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11314 = out_f_rivalid_1173; // @[RegisterRouter.scala:87:24] wire out_f_roready_1173 = out_roready_1_1027 & out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11315 = out_f_roready_1173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1173 = out_wivalid_1_1027 & out_wimask_1173; // @[RegisterRouter.scala:87:24] wire out_f_woready_1173 = out_woready_1_1027 & out_womask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11316 = ~out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11317 = ~out_wimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11318 = ~out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11319 = ~out_womask_1173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11321 = _out_T_11320; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1007 = _out_T_11321; // @[RegisterRouter.scala:87:24] wire out_rimask_1174 = \|_out_rimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_wimask_1174 = &_out_wimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_romask_1174 = \|_out_romask_T_1174; // @[RegisterRouter.scala:87:24] wire out_womask_1174 = &_out_womask_T_1174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1174 = out_rivalid_1_1028 & out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11323 = out_f_rivalid_1174; // @[RegisterRouter.scala:87:24] wire out_f_roready_1174 = out_roready_1_1028 & out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11324 = out_f_roready_1174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1174 = out_wivalid_1_1028 & out_wimask_1174; // @[RegisterRouter.scala:87:24] wire out_f_woready_1174 = out_woready_1_1028 & out_womask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11325 = ~out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11326 = ~out_wimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11327 = ~out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11328 = ~out_womask_1174; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1007 = {hi_946, flags_0_go, _out_prepend_T_1007}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11329 = out_prepend_1007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11330 = _out_T_11329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1008 = _out_T_11330; // @[RegisterRouter.scala:87:24] wire out_rimask_1175 = \|_out_rimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_wimask_1175 = &_out_wimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_romask_1175 = \|_out_romask_T_1175; // @[RegisterRouter.scala:87:24] wire out_womask_1175 = &_out_womask_T_1175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1175 = out_rivalid_1_1029 & out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11332 = out_f_rivalid_1175; // @[RegisterRouter.scala:87:24] wire out_f_roready_1175 = out_roready_1_1029 & out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11333 = out_f_roready_1175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1175 = out_wivalid_1_1029 & out_wimask_1175; // @[RegisterRouter.scala:87:24] wire out_f_woready_1175 = out_woready_1_1029 & out_womask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11334 = ~out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11335 = ~out_wimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11336 = ~out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11337 = ~out_womask_1175; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1008 = {hi_947, flags_0_go, _out_prepend_T_1008}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11338 = out_prepend_1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11339 = _out_T_11338; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1009 = _out_T_11339; // @[RegisterRouter.scala:87:24] wire out_rimask_1176 = \|_out_rimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_wimask_1176 = &_out_wimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_romask_1176 = \|_out_romask_T_1176; // @[RegisterRouter.scala:87:24] wire out_womask_1176 = &_out_womask_T_1176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1176 = out_rivalid_1_1030 & out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11341 = out_f_rivalid_1176; // @[RegisterRouter.scala:87:24] wire out_f_roready_1176 = out_roready_1_1030 & out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11342 = out_f_roready_1176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1176 = out_wivalid_1_1030 & out_wimask_1176; // @[RegisterRouter.scala:87:24] wire out_f_woready_1176 = out_woready_1_1030 & out_womask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11343 = ~out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11344 = ~out_wimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11345 = ~out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11346 = ~out_womask_1176; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1009 = {hi_948, flags_0_go, _out_prepend_T_1009}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11347 = out_prepend_1009; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11348 = _out_T_11347; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1010 = _out_T_11348; // @[RegisterRouter.scala:87:24] wire out_rimask_1177 = \|_out_rimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_wimask_1177 = &_out_wimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_romask_1177 = \|_out_romask_T_1177; // @[RegisterRouter.scala:87:24] wire out_womask_1177 = &_out_womask_T_1177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1177 = out_rivalid_1_1031 & out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11350 = out_f_rivalid_1177; // @[RegisterRouter.scala:87:24] wire out_f_roready_1177 = out_roready_1_1031 & out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11351 = out_f_roready_1177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1177 = out_wivalid_1_1031 & out_wimask_1177; // @[RegisterRouter.scala:87:24] wire out_f_woready_1177 = out_woready_1_1031 & out_womask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11352 = ~out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11353 = ~out_wimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11354 = ~out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11355 = ~out_womask_1177; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1010 = {hi_949, flags_0_go, _out_prepend_T_1010}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11356 = out_prepend_1010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11357 = _out_T_11356; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1011 = _out_T_11357; // @[RegisterRouter.scala:87:24] wire out_rimask_1178 = \|_out_rimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_wimask_1178 = &_out_wimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_romask_1178 = \|_out_romask_T_1178; // @[RegisterRouter.scala:87:24] wire out_womask_1178 = &_out_womask_T_1178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1178 = out_rivalid_1_1032 & out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11359 = out_f_rivalid_1178; // @[RegisterRouter.scala:87:24] wire out_f_roready_1178 = out_roready_1_1032 & out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11360 = out_f_roready_1178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1178 = out_wivalid_1_1032 & out_wimask_1178; // @[RegisterRouter.scala:87:24] wire out_f_woready_1178 = out_woready_1_1032 & out_womask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11361 = ~out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11362 = ~out_wimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11363 = ~out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11364 = ~out_womask_1178; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1011 = {hi_950, flags_0_go, _out_prepend_T_1011}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11365 = out_prepend_1011; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11366 = _out_T_11365; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1012 = _out_T_11366; // @[RegisterRouter.scala:87:24] wire out_rimask_1179 = \|_out_rimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_wimask_1179 = &_out_wimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_romask_1179 = \|_out_romask_T_1179; // @[RegisterRouter.scala:87:24] wire out_womask_1179 = &_out_womask_T_1179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1179 = out_rivalid_1_1033 & out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11368 = out_f_rivalid_1179; // @[RegisterRouter.scala:87:24] wire out_f_roready_1179 = out_roready_1_1033 & out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11369 = out_f_roready_1179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1179 = out_wivalid_1_1033 & out_wimask_1179; // @[RegisterRouter.scala:87:24] wire out_f_woready_1179 = out_woready_1_1033 & out_womask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11370 = ~out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11371 = ~out_wimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11372 = ~out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11373 = ~out_womask_1179; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1012 = {hi_951, flags_0_go, _out_prepend_T_1012}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11374 = out_prepend_1012; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11375 = _out_T_11374; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1013 = _out_T_11375; // @[RegisterRouter.scala:87:24] wire out_rimask_1180 = \|_out_rimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_wimask_1180 = &_out_wimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_romask_1180 = \|_out_romask_T_1180; // @[RegisterRouter.scala:87:24] wire out_womask_1180 = &_out_womask_T_1180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1180 = out_rivalid_1_1034 & out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11377 = out_f_rivalid_1180; // @[RegisterRouter.scala:87:24] wire out_f_roready_1180 = out_roready_1_1034 & out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11378 = out_f_roready_1180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1180 = out_wivalid_1_1034 & out_wimask_1180; // @[RegisterRouter.scala:87:24] wire out_f_woready_1180 = out_woready_1_1034 & out_womask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11379 = ~out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11380 = ~out_wimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11381 = ~out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11382 = ~out_womask_1180; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1013 = {hi_952, flags_0_go, _out_prepend_T_1013}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11383 = out_prepend_1013; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11384 = _out_T_11383; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_246 = _out_T_11384; // @[MuxLiteral.scala:49:48] wire out_rimask_1181 = \|_out_rimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_wimask_1181 = &_out_wimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_romask_1181 = \|_out_romask_T_1181; // @[RegisterRouter.scala:87:24] wire out_womask_1181 = &_out_womask_T_1181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1181 = out_rivalid_1_1035 & out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11386 = out_f_rivalid_1181; // @[RegisterRouter.scala:87:24] wire out_f_roready_1181 = out_roready_1_1035 & out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11387 = out_f_roready_1181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1181 = out_wivalid_1_1035 & out_wimask_1181; // @[RegisterRouter.scala:87:24] wire out_f_woready_1181 = out_woready_1_1035 & out_womask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11388 = ~out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11389 = ~out_wimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11390 = ~out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11391 = ~out_womask_1181; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11393 = _out_T_11392; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1014 = _out_T_11393; // @[RegisterRouter.scala:87:24] wire out_rimask_1182 = \|_out_rimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_wimask_1182 = &_out_wimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_romask_1182 = \|_out_romask_T_1182; // @[RegisterRouter.scala:87:24] wire out_womask_1182 = &_out_womask_T_1182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1182 = out_rivalid_1_1036 & out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11395 = out_f_rivalid_1182; // @[RegisterRouter.scala:87:24] wire out_f_roready_1182 = out_roready_1_1036 & out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11396 = out_f_roready_1182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1182 = out_wivalid_1_1036 & out_wimask_1182; // @[RegisterRouter.scala:87:24] wire out_f_woready_1182 = out_woready_1_1036 & out_womask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11397 = ~out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11398 = ~out_wimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11399 = ~out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11400 = ~out_womask_1182; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1014 = {hi_186, flags_0_go, _out_prepend_T_1014}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11401 = out_prepend_1014; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11402 = _out_T_11401; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1015 = _out_T_11402; // @[RegisterRouter.scala:87:24] wire out_rimask_1183 = \|_out_rimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_wimask_1183 = &_out_wimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_romask_1183 = \|_out_romask_T_1183; // @[RegisterRouter.scala:87:24] wire out_womask_1183 = &_out_womask_T_1183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1183 = out_rivalid_1_1037 & out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11404 = out_f_rivalid_1183; // @[RegisterRouter.scala:87:24] wire out_f_roready_1183 = out_roready_1_1037 & out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11405 = out_f_roready_1183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1183 = out_wivalid_1_1037 & out_wimask_1183; // @[RegisterRouter.scala:87:24] wire out_f_woready_1183 = out_woready_1_1037 & out_womask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11406 = ~out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11407 = ~out_wimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11408 = ~out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11409 = ~out_womask_1183; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1015 = {hi_187, flags_0_go, _out_prepend_T_1015}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11410 = out_prepend_1015; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11411 = _out_T_11410; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1016 = _out_T_11411; // @[RegisterRouter.scala:87:24] wire out_rimask_1184 = \|_out_rimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_wimask_1184 = &_out_wimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_romask_1184 = \|_out_romask_T_1184; // @[RegisterRouter.scala:87:24] wire out_womask_1184 = &_out_womask_T_1184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1184 = out_rivalid_1_1038 & out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11413 = out_f_rivalid_1184; // @[RegisterRouter.scala:87:24] wire out_f_roready_1184 = out_roready_1_1038 & out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11414 = out_f_roready_1184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1184 = out_wivalid_1_1038 & out_wimask_1184; // @[RegisterRouter.scala:87:24] wire out_f_woready_1184 = out_woready_1_1038 & out_womask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11415 = ~out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11416 = ~out_wimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11417 = ~out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11418 = ~out_womask_1184; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1016 = {hi_188, flags_0_go, _out_prepend_T_1016}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11419 = out_prepend_1016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11420 = _out_T_11419; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1017 = _out_T_11420; // @[RegisterRouter.scala:87:24] wire out_rimask_1185 = \|_out_rimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_wimask_1185 = &_out_wimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_romask_1185 = \|_out_romask_T_1185; // @[RegisterRouter.scala:87:24] wire out_womask_1185 = &_out_womask_T_1185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1185 = out_rivalid_1_1039 & out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11422 = out_f_rivalid_1185; // @[RegisterRouter.scala:87:24] wire out_f_roready_1185 = out_roready_1_1039 & out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11423 = out_f_roready_1185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1185 = out_wivalid_1_1039 & out_wimask_1185; // @[RegisterRouter.scala:87:24] wire out_f_woready_1185 = out_woready_1_1039 & out_womask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11424 = ~out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11425 = ~out_wimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11426 = ~out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11427 = ~out_womask_1185; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1017 = {hi_189, flags_0_go, _out_prepend_T_1017}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11428 = out_prepend_1017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11429 = _out_T_11428; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1018 = _out_T_11429; // @[RegisterRouter.scala:87:24] wire out_rimask_1186 = \|_out_rimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_wimask_1186 = &_out_wimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_romask_1186 = \|_out_romask_T_1186; // @[RegisterRouter.scala:87:24] wire out_womask_1186 = &_out_womask_T_1186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1186 = out_rivalid_1_1040 & out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11431 = out_f_rivalid_1186; // @[RegisterRouter.scala:87:24] wire out_f_roready_1186 = out_roready_1_1040 & out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11432 = out_f_roready_1186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1186 = out_wivalid_1_1040 & out_wimask_1186; // @[RegisterRouter.scala:87:24] wire out_f_woready_1186 = out_woready_1_1040 & out_womask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11433 = ~out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11434 = ~out_wimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11435 = ~out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11436 = ~out_womask_1186; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1018 = {hi_190, flags_0_go, _out_prepend_T_1018}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11437 = out_prepend_1018; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11438 = _out_T_11437; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1019 = _out_T_11438; // @[RegisterRouter.scala:87:24] wire out_rimask_1187 = \|_out_rimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_wimask_1187 = &_out_wimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_romask_1187 = \|_out_romask_T_1187; // @[RegisterRouter.scala:87:24] wire out_womask_1187 = &_out_womask_T_1187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1187 = out_rivalid_1_1041 & out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11440 = out_f_rivalid_1187; // @[RegisterRouter.scala:87:24] wire out_f_roready_1187 = out_roready_1_1041 & out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11441 = out_f_roready_1187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1187 = out_wivalid_1_1041 & out_wimask_1187; // @[RegisterRouter.scala:87:24] wire out_f_woready_1187 = out_woready_1_1041 & out_womask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11442 = ~out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11443 = ~out_wimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11444 = ~out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11445 = ~out_womask_1187; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1019 = {hi_191, flags_0_go, _out_prepend_T_1019}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11446 = out_prepend_1019; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11447 = _out_T_11446; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1020 = _out_T_11447; // @[RegisterRouter.scala:87:24] wire out_rimask_1188 = \|_out_rimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_wimask_1188 = &_out_wimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_romask_1188 = \|_out_romask_T_1188; // @[RegisterRouter.scala:87:24] wire out_womask_1188 = &_out_womask_T_1188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1188 = out_rivalid_1_1042 & out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11449 = out_f_rivalid_1188; // @[RegisterRouter.scala:87:24] wire out_f_roready_1188 = out_roready_1_1042 & out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11450 = out_f_roready_1188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1188 = out_wivalid_1_1042 & out_wimask_1188; // @[RegisterRouter.scala:87:24] wire out_f_woready_1188 = out_woready_1_1042 & out_womask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11451 = ~out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11452 = ~out_wimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11453 = ~out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11454 = ~out_womask_1188; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1020 = {hi_192, flags_0_go, _out_prepend_T_1020}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11455 = out_prepend_1020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11456 = _out_T_11455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_151 = _out_T_11456; // @[MuxLiteral.scala:49:48] wire out_rimask_1189 = \|_out_rimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_wimask_1189 = &_out_wimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_romask_1189 = \|_out_romask_T_1189; // @[RegisterRouter.scala:87:24] wire out_womask_1189 = &_out_womask_T_1189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1189 = out_rivalid_1_1043 & out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11458 = out_f_rivalid_1189; // @[RegisterRouter.scala:87:24] wire out_f_roready_1189 = out_roready_1_1043 & out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11459 = out_f_roready_1189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1189 = out_wivalid_1_1043 & out_wimask_1189; // @[RegisterRouter.scala:87:24] wire out_f_woready_1189 = out_woready_1_1043 & out_womask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11460 = ~out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11461 = ~out_wimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11462 = ~out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11463 = ~out_womask_1189; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11465 = _out_T_11464; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1021 = _out_T_11465; // @[RegisterRouter.scala:87:24] wire out_rimask_1190 = \|_out_rimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_wimask_1190 = &_out_wimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_romask_1190 = \|_out_romask_T_1190; // @[RegisterRouter.scala:87:24] wire out_womask_1190 = &_out_womask_T_1190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1190 = out_rivalid_1_1044 & out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11467 = out_f_rivalid_1190; // @[RegisterRouter.scala:87:24] wire out_f_roready_1190 = out_roready_1_1044 & out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11468 = out_f_roready_1190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1190 = out_wivalid_1_1044 & out_wimask_1190; // @[RegisterRouter.scala:87:24] wire out_f_woready_1190 = out_woready_1_1044 & out_womask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11469 = ~out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11470 = ~out_wimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11471 = ~out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11472 = ~out_womask_1190; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1021 = {hi_146, flags_0_go, _out_prepend_T_1021}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11473 = out_prepend_1021; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11474 = _out_T_11473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1022 = _out_T_11474; // @[RegisterRouter.scala:87:24] wire out_rimask_1191 = \|_out_rimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_wimask_1191 = &_out_wimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_romask_1191 = \|_out_romask_T_1191; // @[RegisterRouter.scala:87:24] wire out_womask_1191 = &_out_womask_T_1191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1191 = out_rivalid_1_1045 & out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11476 = out_f_rivalid_1191; // @[RegisterRouter.scala:87:24] wire out_f_roready_1191 = out_roready_1_1045 & out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11477 = out_f_roready_1191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1191 = out_wivalid_1_1045 & out_wimask_1191; // @[RegisterRouter.scala:87:24] wire out_f_woready_1191 = out_woready_1_1045 & out_womask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11478 = ~out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11479 = ~out_wimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11480 = ~out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11481 = ~out_womask_1191; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1022 = {hi_147, flags_0_go, _out_prepend_T_1022}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11482 = out_prepend_1022; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11483 = _out_T_11482; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1023 = _out_T_11483; // @[RegisterRouter.scala:87:24] wire out_rimask_1192 = \|_out_rimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_wimask_1192 = &_out_wimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_romask_1192 = \|_out_romask_T_1192; // @[RegisterRouter.scala:87:24] wire out_womask_1192 = &_out_womask_T_1192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1192 = out_rivalid_1_1046 & out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11485 = out_f_rivalid_1192; // @[RegisterRouter.scala:87:24] wire out_f_roready_1192 = out_roready_1_1046 & out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11486 = out_f_roready_1192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1192 = out_wivalid_1_1046 & out_wimask_1192; // @[RegisterRouter.scala:87:24] wire out_f_woready_1192 = out_woready_1_1046 & out_womask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11487 = ~out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11488 = ~out_wimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11489 = ~out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11490 = ~out_womask_1192; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1023 = {hi_148, flags_0_go, _out_prepend_T_1023}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11491 = out_prepend_1023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11492 = _out_T_11491; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1024 = _out_T_11492; // @[RegisterRouter.scala:87:24] wire out_rimask_1193 = \|_out_rimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_wimask_1193 = &_out_wimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_romask_1193 = \|_out_romask_T_1193; // @[RegisterRouter.scala:87:24] wire out_womask_1193 = &_out_womask_T_1193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1193 = out_rivalid_1_1047 & out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11494 = out_f_rivalid_1193; // @[RegisterRouter.scala:87:24] wire out_f_roready_1193 = out_roready_1_1047 & out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11495 = out_f_roready_1193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1193 = out_wivalid_1_1047 & out_wimask_1193; // @[RegisterRouter.scala:87:24] wire out_f_woready_1193 = out_woready_1_1047 & out_womask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11496 = ~out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11497 = ~out_wimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11498 = ~out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11499 = ~out_womask_1193; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1024 = {hi_149, flags_0_go, _out_prepend_T_1024}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11500 = out_prepend_1024; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11501 = _out_T_11500; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1025 = _out_T_11501; // @[RegisterRouter.scala:87:24] wire out_rimask_1194 = \|_out_rimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_wimask_1194 = &_out_wimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_romask_1194 = \|_out_romask_T_1194; // @[RegisterRouter.scala:87:24] wire out_womask_1194 = &_out_womask_T_1194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1194 = out_rivalid_1_1048 & out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11503 = out_f_rivalid_1194; // @[RegisterRouter.scala:87:24] wire out_f_roready_1194 = out_roready_1_1048 & out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11504 = out_f_roready_1194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1194 = out_wivalid_1_1048 & out_wimask_1194; // @[RegisterRouter.scala:87:24] wire out_f_woready_1194 = out_woready_1_1048 & out_womask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11505 = ~out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11506 = ~out_wimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11507 = ~out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11508 = ~out_womask_1194; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1025 = {hi_150, flags_0_go, _out_prepend_T_1025}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11509 = out_prepend_1025; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11510 = _out_T_11509; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1026 = _out_T_11510; // @[RegisterRouter.scala:87:24] wire out_rimask_1195 = \|_out_rimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_wimask_1195 = &_out_wimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_romask_1195 = \|_out_romask_T_1195; // @[RegisterRouter.scala:87:24] wire out_womask_1195 = &_out_womask_T_1195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1195 = out_rivalid_1_1049 & out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11512 = out_f_rivalid_1195; // @[RegisterRouter.scala:87:24] wire out_f_roready_1195 = out_roready_1_1049 & out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11513 = out_f_roready_1195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1195 = out_wivalid_1_1049 & out_wimask_1195; // @[RegisterRouter.scala:87:24] wire out_f_woready_1195 = out_woready_1_1049 & out_womask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11514 = ~out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11515 = ~out_wimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11516 = ~out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11517 = ~out_womask_1195; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1026 = {hi_151, flags_0_go, _out_prepend_T_1026}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11518 = out_prepend_1026; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11519 = _out_T_11518; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1027 = _out_T_11519; // @[RegisterRouter.scala:87:24] wire out_rimask_1196 = \|_out_rimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_wimask_1196 = &_out_wimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_romask_1196 = \|_out_romask_T_1196; // @[RegisterRouter.scala:87:24] wire out_womask_1196 = &_out_womask_T_1196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1196 = out_rivalid_1_1050 & out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11521 = out_f_rivalid_1196; // @[RegisterRouter.scala:87:24] wire out_f_roready_1196 = out_roready_1_1050 & out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11522 = out_f_roready_1196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1196 = out_wivalid_1_1050 & out_wimask_1196; // @[RegisterRouter.scala:87:24] wire out_f_woready_1196 = out_woready_1_1050 & out_womask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11523 = ~out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11524 = ~out_wimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11525 = ~out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11526 = ~out_womask_1196; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1027 = {hi_152, flags_0_go, _out_prepend_T_1027}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11527 = out_prepend_1027; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11528 = _out_T_11527; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_146 = _out_T_11528; // @[MuxLiteral.scala:49:48] wire out_rimask_1197 = \|_out_rimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_wimask_1197 = &_out_wimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_romask_1197 = \|_out_romask_T_1197; // @[RegisterRouter.scala:87:24] wire out_womask_1197 = &_out_womask_T_1197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1197 = out_rivalid_1_1051 & out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11530 = out_f_rivalid_1197; // @[RegisterRouter.scala:87:24] wire out_f_roready_1197 = out_roready_1_1051 & out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11531 = out_f_roready_1197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1197 = out_wivalid_1_1051 & out_wimask_1197; // @[RegisterRouter.scala:87:24] wire out_f_woready_1197 = out_woready_1_1051 & out_womask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11532 = ~out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11533 = ~out_wimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11534 = ~out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11535 = ~out_womask_1197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11537 = _out_T_11536; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1028 = _out_T_11537; // @[RegisterRouter.scala:87:24] wire out_rimask_1198 = \|_out_rimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_wimask_1198 = &_out_wimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_romask_1198 = \|_out_romask_T_1198; // @[RegisterRouter.scala:87:24] wire out_womask_1198 = &_out_womask_T_1198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1198 = out_rivalid_1_1052 & out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11539 = out_f_rivalid_1198; // @[RegisterRouter.scala:87:24] wire out_f_roready_1198 = out_roready_1_1052 & out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11540 = out_f_roready_1198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1198 = out_wivalid_1_1052 & out_wimask_1198; // @[RegisterRouter.scala:87:24] wire out_f_woready_1198 = out_woready_1_1052 & out_womask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11541 = ~out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11542 = ~out_wimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11543 = ~out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11544 = ~out_womask_1198; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1028 = {hi_498, flags_0_go, _out_prepend_T_1028}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11545 = out_prepend_1028; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11546 = _out_T_11545; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1029 = _out_T_11546; // @[RegisterRouter.scala:87:24] wire out_rimask_1199 = \|_out_rimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_wimask_1199 = &_out_wimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_romask_1199 = \|_out_romask_T_1199; // @[RegisterRouter.scala:87:24] wire out_womask_1199 = &_out_womask_T_1199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1199 = out_rivalid_1_1053 & out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11548 = out_f_rivalid_1199; // @[RegisterRouter.scala:87:24] wire out_f_roready_1199 = out_roready_1_1053 & out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11549 = out_f_roready_1199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1199 = out_wivalid_1_1053 & out_wimask_1199; // @[RegisterRouter.scala:87:24] wire out_f_woready_1199 = out_woready_1_1053 & out_womask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11550 = ~out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11551 = ~out_wimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11552 = ~out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11553 = ~out_womask_1199; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1029 = {hi_499, flags_0_go, _out_prepend_T_1029}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11554 = out_prepend_1029; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11555 = _out_T_11554; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1030 = _out_T_11555; // @[RegisterRouter.scala:87:24] wire out_rimask_1200 = \|_out_rimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_wimask_1200 = &_out_wimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_romask_1200 = \|_out_romask_T_1200; // @[RegisterRouter.scala:87:24] wire out_womask_1200 = &_out_womask_T_1200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1200 = out_rivalid_1_1054 & out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11557 = out_f_rivalid_1200; // @[RegisterRouter.scala:87:24] wire out_f_roready_1200 = out_roready_1_1054 & out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11558 = out_f_roready_1200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1200 = out_wivalid_1_1054 & out_wimask_1200; // @[RegisterRouter.scala:87:24] wire out_f_woready_1200 = out_woready_1_1054 & out_womask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11559 = ~out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11560 = ~out_wimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11561 = ~out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11562 = ~out_womask_1200; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1030 = {hi_500, flags_0_go, _out_prepend_T_1030}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11563 = out_prepend_1030; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11564 = _out_T_11563; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1031 = _out_T_11564; // @[RegisterRouter.scala:87:24] wire out_rimask_1201 = \|_out_rimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_wimask_1201 = &_out_wimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_romask_1201 = \|_out_romask_T_1201; // @[RegisterRouter.scala:87:24] wire out_womask_1201 = &_out_womask_T_1201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1201 = out_rivalid_1_1055 & out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11566 = out_f_rivalid_1201; // @[RegisterRouter.scala:87:24] wire out_f_roready_1201 = out_roready_1_1055 & out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11567 = out_f_roready_1201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1201 = out_wivalid_1_1055 & out_wimask_1201; // @[RegisterRouter.scala:87:24] wire out_f_woready_1201 = out_woready_1_1055 & out_womask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11568 = ~out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11569 = ~out_wimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11570 = ~out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11571 = ~out_womask_1201; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1031 = {hi_501, flags_0_go, _out_prepend_T_1031}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11572 = out_prepend_1031; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11573 = _out_T_11572; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1032 = _out_T_11573; // @[RegisterRouter.scala:87:24] wire out_rimask_1202 = \|_out_rimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_wimask_1202 = &_out_wimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_romask_1202 = \|_out_romask_T_1202; // @[RegisterRouter.scala:87:24] wire out_womask_1202 = &_out_womask_T_1202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1202 = out_rivalid_1_1056 & out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11575 = out_f_rivalid_1202; // @[RegisterRouter.scala:87:24] wire out_f_roready_1202 = out_roready_1_1056 & out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11576 = out_f_roready_1202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1202 = out_wivalid_1_1056 & out_wimask_1202; // @[RegisterRouter.scala:87:24] wire out_f_woready_1202 = out_woready_1_1056 & out_womask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11577 = ~out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11578 = ~out_wimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11579 = ~out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11580 = ~out_womask_1202; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1032 = {hi_502, flags_0_go, _out_prepend_T_1032}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11581 = out_prepend_1032; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11582 = _out_T_11581; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1033 = _out_T_11582; // @[RegisterRouter.scala:87:24] wire out_rimask_1203 = \|_out_rimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_wimask_1203 = &_out_wimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_romask_1203 = \|_out_romask_T_1203; // @[RegisterRouter.scala:87:24] wire out_womask_1203 = &_out_womask_T_1203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1203 = out_rivalid_1_1057 & out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11584 = out_f_rivalid_1203; // @[RegisterRouter.scala:87:24] wire out_f_roready_1203 = out_roready_1_1057 & out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11585 = out_f_roready_1203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1203 = out_wivalid_1_1057 & out_wimask_1203; // @[RegisterRouter.scala:87:24] wire out_f_woready_1203 = out_woready_1_1057 & out_womask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11586 = ~out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11587 = ~out_wimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11588 = ~out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11589 = ~out_womask_1203; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1033 = {hi_503, flags_0_go, _out_prepend_T_1033}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11590 = out_prepend_1033; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11591 = _out_T_11590; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1034 = _out_T_11591; // @[RegisterRouter.scala:87:24] wire out_rimask_1204 = \|_out_rimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_wimask_1204 = &_out_wimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_romask_1204 = \|_out_romask_T_1204; // @[RegisterRouter.scala:87:24] wire out_womask_1204 = &_out_womask_T_1204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1204 = out_rivalid_1_1058 & out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11593 = out_f_rivalid_1204; // @[RegisterRouter.scala:87:24] wire out_f_roready_1204 = out_roready_1_1058 & out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11594 = out_f_roready_1204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1204 = out_wivalid_1_1058 & out_wimask_1204; // @[RegisterRouter.scala:87:24] wire out_f_woready_1204 = out_woready_1_1058 & out_womask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11595 = ~out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11596 = ~out_wimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11597 = ~out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11598 = ~out_womask_1204; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1034 = {hi_504, flags_0_go, _out_prepend_T_1034}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11599 = out_prepend_1034; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11600 = _out_T_11599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_190 = _out_T_11600; // @[MuxLiteral.scala:49:48] wire out_rimask_1205 = \|_out_rimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_wimask_1205 = &_out_wimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_romask_1205 = \|_out_romask_T_1205; // @[RegisterRouter.scala:87:24] wire out_womask_1205 = &_out_womask_T_1205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1205 = out_rivalid_1_1059 & out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11602 = out_f_rivalid_1205; // @[RegisterRouter.scala:87:24] wire out_f_roready_1205 = out_roready_1_1059 & out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11603 = out_f_roready_1205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1205 = out_wivalid_1_1059 & out_wimask_1205; // @[RegisterRouter.scala:87:24] wire out_f_woready_1205 = out_woready_1_1059 & out_womask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11604 = ~out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11605 = ~out_wimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11606 = ~out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11607 = ~out_womask_1205; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11609 = _out_T_11608; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1035 = _out_T_11609; // @[RegisterRouter.scala:87:24] wire out_rimask_1206 = \|_out_rimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_wimask_1206 = &_out_wimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_romask_1206 = \|_out_romask_T_1206; // @[RegisterRouter.scala:87:24] wire out_womask_1206 = &_out_womask_T_1206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1206 = out_rivalid_1_1060 & out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11611 = out_f_rivalid_1206; // @[RegisterRouter.scala:87:24] wire out_f_roready_1206 = out_roready_1_1060 & out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11612 = out_f_roready_1206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1206 = out_wivalid_1_1060 & out_wimask_1206; // @[RegisterRouter.scala:87:24] wire out_f_woready_1206 = out_woready_1_1060 & out_womask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11613 = ~out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11614 = ~out_wimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11615 = ~out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11616 = ~out_womask_1206; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1035 = {hi_442, flags_0_go, _out_prepend_T_1035}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11617 = out_prepend_1035; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11618 = _out_T_11617; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1036 = _out_T_11618; // @[RegisterRouter.scala:87:24] wire out_rimask_1207 = \|_out_rimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_wimask_1207 = &_out_wimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_romask_1207 = \|_out_romask_T_1207; // @[RegisterRouter.scala:87:24] wire out_womask_1207 = &_out_womask_T_1207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1207 = out_rivalid_1_1061 & out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11620 = out_f_rivalid_1207; // @[RegisterRouter.scala:87:24] wire out_f_roready_1207 = out_roready_1_1061 & out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11621 = out_f_roready_1207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1207 = out_wivalid_1_1061 & out_wimask_1207; // @[RegisterRouter.scala:87:24] wire out_f_woready_1207 = out_woready_1_1061 & out_womask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11622 = ~out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11623 = ~out_wimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11624 = ~out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11625 = ~out_womask_1207; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1036 = {hi_443, flags_0_go, _out_prepend_T_1036}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11626 = out_prepend_1036; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11627 = _out_T_11626; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1037 = _out_T_11627; // @[RegisterRouter.scala:87:24] wire out_rimask_1208 = \|_out_rimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_wimask_1208 = &_out_wimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_romask_1208 = \|_out_romask_T_1208; // @[RegisterRouter.scala:87:24] wire out_womask_1208 = &_out_womask_T_1208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1208 = out_rivalid_1_1062 & out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11629 = out_f_rivalid_1208; // @[RegisterRouter.scala:87:24] wire out_f_roready_1208 = out_roready_1_1062 & out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11630 = out_f_roready_1208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1208 = out_wivalid_1_1062 & out_wimask_1208; // @[RegisterRouter.scala:87:24] wire out_f_woready_1208 = out_woready_1_1062 & out_womask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11631 = ~out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11632 = ~out_wimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11633 = ~out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11634 = ~out_womask_1208; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1037 = {hi_444, flags_0_go, _out_prepend_T_1037}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11635 = out_prepend_1037; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11636 = _out_T_11635; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1038 = _out_T_11636; // @[RegisterRouter.scala:87:24] wire out_rimask_1209 = \|_out_rimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_wimask_1209 = &_out_wimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_romask_1209 = \|_out_romask_T_1209; // @[RegisterRouter.scala:87:24] wire out_womask_1209 = &_out_womask_T_1209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1209 = out_rivalid_1_1063 & out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11638 = out_f_rivalid_1209; // @[RegisterRouter.scala:87:24] wire out_f_roready_1209 = out_roready_1_1063 & out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11639 = out_f_roready_1209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1209 = out_wivalid_1_1063 & out_wimask_1209; // @[RegisterRouter.scala:87:24] wire out_f_woready_1209 = out_woready_1_1063 & out_womask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11640 = ~out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11641 = ~out_wimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11642 = ~out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11643 = ~out_womask_1209; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1038 = {hi_445, flags_0_go, _out_prepend_T_1038}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11644 = out_prepend_1038; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11645 = _out_T_11644; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1039 = _out_T_11645; // @[RegisterRouter.scala:87:24] wire out_rimask_1210 = \|_out_rimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_wimask_1210 = &_out_wimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_romask_1210 = \|_out_romask_T_1210; // @[RegisterRouter.scala:87:24] wire out_womask_1210 = &_out_womask_T_1210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1210 = out_rivalid_1_1064 & out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11647 = out_f_rivalid_1210; // @[RegisterRouter.scala:87:24] wire out_f_roready_1210 = out_roready_1_1064 & out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11648 = out_f_roready_1210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1210 = out_wivalid_1_1064 & out_wimask_1210; // @[RegisterRouter.scala:87:24] wire out_f_woready_1210 = out_woready_1_1064 & out_womask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11649 = ~out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11650 = ~out_wimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11651 = ~out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11652 = ~out_womask_1210; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1039 = {hi_446, flags_0_go, _out_prepend_T_1039}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11653 = out_prepend_1039; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11654 = _out_T_11653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1040 = _out_T_11654; // @[RegisterRouter.scala:87:24] wire out_rimask_1211 = \|_out_rimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_wimask_1211 = &_out_wimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_romask_1211 = \|_out_romask_T_1211; // @[RegisterRouter.scala:87:24] wire out_womask_1211 = &_out_womask_T_1211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1211 = out_rivalid_1_1065 & out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11656 = out_f_rivalid_1211; // @[RegisterRouter.scala:87:24] wire out_f_roready_1211 = out_roready_1_1065 & out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11657 = out_f_roready_1211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1211 = out_wivalid_1_1065 & out_wimask_1211; // @[RegisterRouter.scala:87:24] wire out_f_woready_1211 = out_woready_1_1065 & out_womask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11658 = ~out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11659 = ~out_wimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11660 = ~out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11661 = ~out_womask_1211; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1040 = {hi_447, flags_0_go, _out_prepend_T_1040}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11662 = out_prepend_1040; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11663 = _out_T_11662; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1041 = _out_T_11663; // @[RegisterRouter.scala:87:24] wire out_rimask_1212 = \|_out_rimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_wimask_1212 = &_out_wimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_romask_1212 = \|_out_romask_T_1212; // @[RegisterRouter.scala:87:24] wire out_womask_1212 = &_out_womask_T_1212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1212 = out_rivalid_1_1066 & out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11665 = out_f_rivalid_1212; // @[RegisterRouter.scala:87:24] wire out_f_roready_1212 = out_roready_1_1066 & out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11666 = out_f_roready_1212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1212 = out_wivalid_1_1066 & out_wimask_1212; // @[RegisterRouter.scala:87:24] wire out_f_woready_1212 = out_woready_1_1066 & out_womask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11667 = ~out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11668 = ~out_wimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11669 = ~out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11670 = ~out_womask_1212; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1041 = {hi_448, flags_0_go, _out_prepend_T_1041}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11671 = out_prepend_1041; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11672 = _out_T_11671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_183 = _out_T_11672; // @[MuxLiteral.scala:49:48] wire out_rimask_1213 = \|_out_rimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_wimask_1213 = &_out_wimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_romask_1213 = \|_out_romask_T_1213; // @[RegisterRouter.scala:87:24] wire out_womask_1213 = &_out_womask_T_1213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1213 = out_rivalid_1_1067 & out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11674 = out_f_rivalid_1213; // @[RegisterRouter.scala:87:24] wire out_f_roready_1213 = out_roready_1_1067 & out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11675 = out_f_roready_1213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1213 = out_wivalid_1_1067 & out_wimask_1213; // @[RegisterRouter.scala:87:24] wire out_f_woready_1213 = out_woready_1_1067 & out_womask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11676 = ~out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11677 = ~out_wimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11678 = ~out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11679 = ~out_womask_1213; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11681 = _out_T_11680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1042 = _out_T_11681; // @[RegisterRouter.scala:87:24] wire out_rimask_1214 = \|_out_rimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_wimask_1214 = &_out_wimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_romask_1214 = \|_out_romask_T_1214; // @[RegisterRouter.scala:87:24] wire out_womask_1214 = &_out_womask_T_1214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1214 = out_rivalid_1_1068 & out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11683 = out_f_rivalid_1214; // @[RegisterRouter.scala:87:24] wire out_f_roready_1214 = out_roready_1_1068 & out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11684 = out_f_roready_1214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1214 = out_wivalid_1_1068 & out_wimask_1214; // @[RegisterRouter.scala:87:24] wire out_f_woready_1214 = out_woready_1_1068 & out_womask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11685 = ~out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11686 = ~out_wimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11687 = ~out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11688 = ~out_womask_1214; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1042 = {hi_322, flags_0_go, _out_prepend_T_1042}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11689 = out_prepend_1042; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11690 = _out_T_11689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1043 = _out_T_11690; // @[RegisterRouter.scala:87:24] wire out_rimask_1215 = \|_out_rimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_wimask_1215 = &_out_wimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_romask_1215 = \|_out_romask_T_1215; // @[RegisterRouter.scala:87:24] wire out_womask_1215 = &_out_womask_T_1215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1215 = out_rivalid_1_1069 & out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11692 = out_f_rivalid_1215; // @[RegisterRouter.scala:87:24] wire out_f_roready_1215 = out_roready_1_1069 & out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11693 = out_f_roready_1215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1215 = out_wivalid_1_1069 & out_wimask_1215; // @[RegisterRouter.scala:87:24] wire out_f_woready_1215 = out_woready_1_1069 & out_womask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11694 = ~out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11695 = ~out_wimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11696 = ~out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11697 = ~out_womask_1215; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1043 = {hi_323, flags_0_go, _out_prepend_T_1043}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11698 = out_prepend_1043; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11699 = _out_T_11698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1044 = _out_T_11699; // @[RegisterRouter.scala:87:24] wire out_rimask_1216 = \|_out_rimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_wimask_1216 = &_out_wimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_romask_1216 = \|_out_romask_T_1216; // @[RegisterRouter.scala:87:24] wire out_womask_1216 = &_out_womask_T_1216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1216 = out_rivalid_1_1070 & out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11701 = out_f_rivalid_1216; // @[RegisterRouter.scala:87:24] wire out_f_roready_1216 = out_roready_1_1070 & out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11702 = out_f_roready_1216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1216 = out_wivalid_1_1070 & out_wimask_1216; // @[RegisterRouter.scala:87:24] wire out_f_woready_1216 = out_woready_1_1070 & out_womask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11703 = ~out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11704 = ~out_wimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11705 = ~out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11706 = ~out_womask_1216; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1044 = {hi_324, flags_0_go, _out_prepend_T_1044}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11707 = out_prepend_1044; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11708 = _out_T_11707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1045 = _out_T_11708; // @[RegisterRouter.scala:87:24] wire out_rimask_1217 = \|_out_rimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_wimask_1217 = &_out_wimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_romask_1217 = \|_out_romask_T_1217; // @[RegisterRouter.scala:87:24] wire out_womask_1217 = &_out_womask_T_1217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1217 = out_rivalid_1_1071 & out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11710 = out_f_rivalid_1217; // @[RegisterRouter.scala:87:24] wire out_f_roready_1217 = out_roready_1_1071 & out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11711 = out_f_roready_1217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1217 = out_wivalid_1_1071 & out_wimask_1217; // @[RegisterRouter.scala:87:24] wire out_f_woready_1217 = out_woready_1_1071 & out_womask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11712 = ~out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11713 = ~out_wimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11714 = ~out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11715 = ~out_womask_1217; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1045 = {hi_325, flags_0_go, _out_prepend_T_1045}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11716 = out_prepend_1045; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11717 = _out_T_11716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1046 = _out_T_11717; // @[RegisterRouter.scala:87:24] wire out_rimask_1218 = \|_out_rimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_wimask_1218 = &_out_wimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_romask_1218 = \|_out_romask_T_1218; // @[RegisterRouter.scala:87:24] wire out_womask_1218 = &_out_womask_T_1218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1218 = out_rivalid_1_1072 & out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11719 = out_f_rivalid_1218; // @[RegisterRouter.scala:87:24] wire out_f_roready_1218 = out_roready_1_1072 & out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11720 = out_f_roready_1218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1218 = out_wivalid_1_1072 & out_wimask_1218; // @[RegisterRouter.scala:87:24] wire out_f_woready_1218 = out_woready_1_1072 & out_womask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11721 = ~out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11722 = ~out_wimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11723 = ~out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11724 = ~out_womask_1218; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1046 = {hi_326, flags_0_go, _out_prepend_T_1046}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11725 = out_prepend_1046; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11726 = _out_T_11725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1047 = _out_T_11726; // @[RegisterRouter.scala:87:24] wire out_rimask_1219 = \|_out_rimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_wimask_1219 = &_out_wimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_romask_1219 = \|_out_romask_T_1219; // @[RegisterRouter.scala:87:24] wire out_womask_1219 = &_out_womask_T_1219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1219 = out_rivalid_1_1073 & out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11728 = out_f_rivalid_1219; // @[RegisterRouter.scala:87:24] wire out_f_roready_1219 = out_roready_1_1073 & out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11729 = out_f_roready_1219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1219 = out_wivalid_1_1073 & out_wimask_1219; // @[RegisterRouter.scala:87:24] wire out_f_woready_1219 = out_woready_1_1073 & out_womask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11730 = ~out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11731 = ~out_wimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11732 = ~out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11733 = ~out_womask_1219; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1047 = {hi_327, flags_0_go, _out_prepend_T_1047}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11734 = out_prepend_1047; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11735 = _out_T_11734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1048 = _out_T_11735; // @[RegisterRouter.scala:87:24] wire out_rimask_1220 = \|_out_rimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_wimask_1220 = &_out_wimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_romask_1220 = \|_out_romask_T_1220; // @[RegisterRouter.scala:87:24] wire out_womask_1220 = &_out_womask_T_1220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1220 = out_rivalid_1_1074 & out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11737 = out_f_rivalid_1220; // @[RegisterRouter.scala:87:24] wire out_f_roready_1220 = out_roready_1_1074 & out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11738 = out_f_roready_1220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1220 = out_wivalid_1_1074 & out_wimask_1220; // @[RegisterRouter.scala:87:24] wire out_f_woready_1220 = out_woready_1_1074 & out_womask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11739 = ~out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11740 = ~out_wimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11741 = ~out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11742 = ~out_womask_1220; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1048 = {hi_328, flags_0_go, _out_prepend_T_1048}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11743 = out_prepend_1048; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11744 = _out_T_11743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_168 = _out_T_11744; // @[MuxLiteral.scala:49:48] wire out_rimask_1221 = \|_out_rimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_wimask_1221 = &_out_wimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_romask_1221 = \|_out_romask_T_1221; // @[RegisterRouter.scala:87:24] wire out_womask_1221 = &_out_womask_T_1221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1221 = out_rivalid_1_1075 & out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11746 = out_f_rivalid_1221; // @[RegisterRouter.scala:87:24] wire out_f_roready_1221 = out_roready_1_1075 & out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11747 = out_f_roready_1221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1221 = out_wivalid_1_1075 & out_wimask_1221; // @[RegisterRouter.scala:87:24] wire out_f_woready_1221 = out_woready_1_1075 & out_womask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11748 = ~out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11749 = ~out_wimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11750 = ~out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11751 = ~out_womask_1221; // @[RegisterRouter.scala:87:24] wire out_rimask_1222 = \|_out_rimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_wimask_1222 = &_out_wimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_romask_1222 = \|_out_romask_T_1222; // @[RegisterRouter.scala:87:24] wire out_womask_1222 = &_out_womask_T_1222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1222 = out_rivalid_1_1076 & out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11755 = out_f_rivalid_1222; // @[RegisterRouter.scala:87:24] wire out_f_roready_1222 = out_roready_1_1076 & out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11756 = out_f_roready_1222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1222 = out_wivalid_1_1076 & out_wimask_1222; // @[RegisterRouter.scala:87:24] wire out_f_woready_1222 = out_woready_1_1076 & out_womask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11757 = ~out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11758 = ~out_wimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11759 = ~out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11760 = ~out_womask_1222; // @[RegisterRouter.scala:87:24] wire out_rimask_1223 = \|_out_rimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_wimask_1223 = &_out_wimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_romask_1223 = \|_out_romask_T_1223; // @[RegisterRouter.scala:87:24] wire out_womask_1223 = &_out_womask_T_1223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1223 = out_rivalid_1_1077 & out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11764 = out_f_rivalid_1223; // @[RegisterRouter.scala:87:24] wire out_f_roready_1223 = out_roready_1_1077 & out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11765 = out_f_roready_1223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1223 = out_wivalid_1_1077 & out_wimask_1223; // @[RegisterRouter.scala:87:24] wire out_f_woready_1223 = out_woready_1_1077 & out_womask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11766 = ~out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11767 = ~out_wimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11768 = ~out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11769 = ~out_womask_1223; // @[RegisterRouter.scala:87:24] wire out_rimask_1224 = \|_out_rimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_wimask_1224 = &_out_wimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_romask_1224 = \|_out_romask_T_1224; // @[RegisterRouter.scala:87:24] wire out_womask_1224 = &_out_womask_T_1224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1224 = out_rivalid_1_1078 & out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11773 = out_f_rivalid_1224; // @[RegisterRouter.scala:87:24] wire out_f_roready_1224 = out_roready_1_1078 & out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11774 = out_f_roready_1224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1224 = out_wivalid_1_1078 & out_wimask_1224; // @[RegisterRouter.scala:87:24] wire out_f_woready_1224 = out_woready_1_1078 & out_womask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11775 = ~out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11776 = ~out_wimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11777 = ~out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11778 = ~out_womask_1224; // @[RegisterRouter.scala:87:24] wire out_rimask_1225 = \|_out_rimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_wimask_1225 = &_out_wimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_romask_1225 = \|_out_romask_T_1225; // @[RegisterRouter.scala:87:24] wire out_womask_1225 = &_out_womask_T_1225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1225 = out_rivalid_1_1079 & out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11782 = out_f_rivalid_1225; // @[RegisterRouter.scala:87:24] wire out_f_roready_1225 = out_roready_1_1079 & out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11783 = out_f_roready_1225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1225 = out_wivalid_1_1079 & out_wimask_1225; // @[RegisterRouter.scala:87:24] wire out_f_woready_1225 = out_woready_1_1079 & out_womask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11784 = ~out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11785 = ~out_wimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11786 = ~out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11787 = ~out_womask_1225; // @[RegisterRouter.scala:87:24] wire out_rimask_1226 = \|_out_rimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_wimask_1226 = &_out_wimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_romask_1226 = \|_out_romask_T_1226; // @[RegisterRouter.scala:87:24] wire out_womask_1226 = &_out_womask_T_1226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1226 = out_rivalid_1_1080 & out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11791 = out_f_rivalid_1226; // @[RegisterRouter.scala:87:24] wire out_f_roready_1226 = out_roready_1_1080 & out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11792 = out_f_roready_1226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1226 = out_wivalid_1_1080 & out_wimask_1226; // @[RegisterRouter.scala:87:24] wire out_f_woready_1226 = out_woready_1_1080 & out_womask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11793 = ~out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11794 = ~out_wimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11795 = ~out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11796 = ~out_womask_1226; // @[RegisterRouter.scala:87:24] wire out_rimask_1227 = \|_out_rimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_wimask_1227 = &_out_wimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_romask_1227 = \|_out_romask_T_1227; // @[RegisterRouter.scala:87:24] wire out_womask_1227 = &_out_womask_T_1227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1227 = out_rivalid_1_1081 & out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11800 = out_f_rivalid_1227; // @[RegisterRouter.scala:87:24] wire out_f_roready_1227 = out_roready_1_1081 & out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11801 = out_f_roready_1227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1227 = out_wivalid_1_1081 & out_wimask_1227; // @[RegisterRouter.scala:87:24] wire out_f_woready_1227 = out_woready_1_1081 & out_womask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11802 = ~out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11803 = ~out_wimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11804 = ~out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11805 = ~out_womask_1227; // @[RegisterRouter.scala:87:24] wire out_rimask_1228 = \|_out_rimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_wimask_1228 = &_out_wimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_romask_1228 = \|_out_romask_T_1228; // @[RegisterRouter.scala:87:24] wire out_womask_1228 = &_out_womask_T_1228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1228 = out_rivalid_1_1082 & out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11809 = out_f_rivalid_1228; // @[RegisterRouter.scala:87:24] wire out_f_roready_1228 = out_roready_1_1082 & out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11810 = out_f_roready_1228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1228 = out_wivalid_1_1082 & out_wimask_1228; // @[RegisterRouter.scala:87:24] wire out_f_woready_1228 = out_woready_1_1082 & out_womask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11811 = ~out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11812 = ~out_wimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11813 = ~out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11814 = ~out_womask_1228; // @[RegisterRouter.scala:87:24] wire out_rimask_1229 = \|_out_rimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_wimask_1229 = &_out_wimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_romask_1229 = \|_out_romask_T_1229; // @[RegisterRouter.scala:87:24] wire out_womask_1229 = &_out_womask_T_1229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1229 = out_rivalid_1_1083 & out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11818 = out_f_rivalid_1229; // @[RegisterRouter.scala:87:24] wire out_f_roready_1229 = out_roready_1_1083 & out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11819 = out_f_roready_1229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1229 = out_wivalid_1_1083 & out_wimask_1229; // @[RegisterRouter.scala:87:24] wire out_f_woready_1229 = out_woready_1_1083 & out_womask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11820 = ~out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11821 = ~out_wimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11822 = ~out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11823 = ~out_womask_1229; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11825 = _out_T_11824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1056 = _out_T_11825; // @[RegisterRouter.scala:87:24] wire out_rimask_1230 = \|_out_rimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_wimask_1230 = &_out_wimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_romask_1230 = \|_out_romask_T_1230; // @[RegisterRouter.scala:87:24] wire out_womask_1230 = &_out_womask_T_1230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1230 = out_rivalid_1_1084 & out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11827 = out_f_rivalid_1230; // @[RegisterRouter.scala:87:24] wire out_f_roready_1230 = out_roready_1_1084 & out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11828 = out_f_roready_1230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1230 = out_wivalid_1_1084 & out_wimask_1230; // @[RegisterRouter.scala:87:24] wire out_f_woready_1230 = out_woready_1_1084 & out_womask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11829 = ~out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11830 = ~out_wimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11831 = ~out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11832 = ~out_womask_1230; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1056 = {hi_658, flags_0_go, _out_prepend_T_1056}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11833 = out_prepend_1056; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11834 = _out_T_11833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1057 = _out_T_11834; // @[RegisterRouter.scala:87:24] wire out_rimask_1231 = \|_out_rimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_wimask_1231 = &_out_wimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_romask_1231 = \|_out_romask_T_1231; // @[RegisterRouter.scala:87:24] wire out_womask_1231 = &_out_womask_T_1231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1231 = out_rivalid_1_1085 & out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11836 = out_f_rivalid_1231; // @[RegisterRouter.scala:87:24] wire out_f_roready_1231 = out_roready_1_1085 & out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11837 = out_f_roready_1231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1231 = out_wivalid_1_1085 & out_wimask_1231; // @[RegisterRouter.scala:87:24] wire out_f_woready_1231 = out_woready_1_1085 & out_womask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11838 = ~out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11839 = ~out_wimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11840 = ~out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11841 = ~out_womask_1231; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1057 = {hi_659, flags_0_go, _out_prepend_T_1057}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11842 = out_prepend_1057; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11843 = _out_T_11842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1058 = _out_T_11843; // @[RegisterRouter.scala:87:24] wire out_rimask_1232 = \|_out_rimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_wimask_1232 = &_out_wimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_romask_1232 = \|_out_romask_T_1232; // @[RegisterRouter.scala:87:24] wire out_womask_1232 = &_out_womask_T_1232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1232 = out_rivalid_1_1086 & out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11845 = out_f_rivalid_1232; // @[RegisterRouter.scala:87:24] wire out_f_roready_1232 = out_roready_1_1086 & out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11846 = out_f_roready_1232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1232 = out_wivalid_1_1086 & out_wimask_1232; // @[RegisterRouter.scala:87:24] wire out_f_woready_1232 = out_woready_1_1086 & out_womask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11847 = ~out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11848 = ~out_wimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11849 = ~out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11850 = ~out_womask_1232; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1058 = {hi_660, flags_0_go, _out_prepend_T_1058}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11851 = out_prepend_1058; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11852 = _out_T_11851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1059 = _out_T_11852; // @[RegisterRouter.scala:87:24] wire out_rimask_1233 = \|_out_rimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_wimask_1233 = &_out_wimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_romask_1233 = \|_out_romask_T_1233; // @[RegisterRouter.scala:87:24] wire out_womask_1233 = &_out_womask_T_1233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1233 = out_rivalid_1_1087 & out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11854 = out_f_rivalid_1233; // @[RegisterRouter.scala:87:24] wire out_f_roready_1233 = out_roready_1_1087 & out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11855 = out_f_roready_1233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1233 = out_wivalid_1_1087 & out_wimask_1233; // @[RegisterRouter.scala:87:24] wire out_f_woready_1233 = out_woready_1_1087 & out_womask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11856 = ~out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11857 = ~out_wimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11858 = ~out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11859 = ~out_womask_1233; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1059 = {hi_661, flags_0_go, _out_prepend_T_1059}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11860 = out_prepend_1059; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11861 = _out_T_11860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1060 = _out_T_11861; // @[RegisterRouter.scala:87:24] wire out_rimask_1234 = \|_out_rimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_wimask_1234 = &_out_wimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_romask_1234 = \|_out_romask_T_1234; // @[RegisterRouter.scala:87:24] wire out_womask_1234 = &_out_womask_T_1234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1234 = out_rivalid_1_1088 & out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11863 = out_f_rivalid_1234; // @[RegisterRouter.scala:87:24] wire out_f_roready_1234 = out_roready_1_1088 & out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11864 = out_f_roready_1234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1234 = out_wivalid_1_1088 & out_wimask_1234; // @[RegisterRouter.scala:87:24] wire out_f_woready_1234 = out_woready_1_1088 & out_womask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11865 = ~out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11866 = ~out_wimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11867 = ~out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11868 = ~out_womask_1234; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1060 = {hi_662, flags_0_go, _out_prepend_T_1060}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11869 = out_prepend_1060; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11870 = _out_T_11869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1061 = _out_T_11870; // @[RegisterRouter.scala:87:24] wire out_rimask_1235 = \|_out_rimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_wimask_1235 = &_out_wimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_romask_1235 = \|_out_romask_T_1235; // @[RegisterRouter.scala:87:24] wire out_womask_1235 = &_out_womask_T_1235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1235 = out_rivalid_1_1089 & out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11872 = out_f_rivalid_1235; // @[RegisterRouter.scala:87:24] wire out_f_roready_1235 = out_roready_1_1089 & out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11873 = out_f_roready_1235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1235 = out_wivalid_1_1089 & out_wimask_1235; // @[RegisterRouter.scala:87:24] wire out_f_woready_1235 = out_woready_1_1089 & out_womask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11874 = ~out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11875 = ~out_wimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11876 = ~out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11877 = ~out_womask_1235; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1061 = {hi_663, flags_0_go, _out_prepend_T_1061}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11878 = out_prepend_1061; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11879 = _out_T_11878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1062 = _out_T_11879; // @[RegisterRouter.scala:87:24] wire out_rimask_1236 = \|_out_rimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_wimask_1236 = &_out_wimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_romask_1236 = \|_out_romask_T_1236; // @[RegisterRouter.scala:87:24] wire out_womask_1236 = &_out_womask_T_1236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1236 = out_rivalid_1_1090 & out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11881 = out_f_rivalid_1236; // @[RegisterRouter.scala:87:24] wire out_f_roready_1236 = out_roready_1_1090 & out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11882 = out_f_roready_1236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1236 = out_wivalid_1_1090 & out_wimask_1236; // @[RegisterRouter.scala:87:24] wire out_f_woready_1236 = out_woready_1_1090 & out_womask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11883 = ~out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11884 = ~out_wimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11885 = ~out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11886 = ~out_womask_1236; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1062 = {hi_664, flags_0_go, _out_prepend_T_1062}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11887 = out_prepend_1062; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11888 = _out_T_11887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_210 = _out_T_11888; // @[MuxLiteral.scala:49:48] wire out_rimask_1237 = \|_out_rimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_wimask_1237 = &_out_wimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_romask_1237 = \|_out_romask_T_1237; // @[RegisterRouter.scala:87:24] wire out_womask_1237 = &_out_womask_T_1237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1237 = out_rivalid_1_1091 & out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11890 = out_f_rivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_roready_1237 = out_roready_1_1091 & out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11891 = out_f_roready_1237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1237 = out_wivalid_1_1091 & out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11892 = out_f_wivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_woready_1237 = out_woready_1_1091 & out_womask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11893 = out_f_woready_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11894 = ~out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11895 = ~out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11896 = ~out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11897 = ~out_womask_1237; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11899 = _out_T_11898; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1063 = _out_T_11899; // @[RegisterRouter.scala:87:24] wire out_rimask_1238 = \|_out_rimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_wimask_1238 = &_out_wimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_romask_1238 = \|_out_romask_T_1238; // @[RegisterRouter.scala:87:24] wire out_womask_1238 = &_out_womask_T_1238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1238 = out_rivalid_1_1092 & out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11901 = out_f_rivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_roready_1238 = out_roready_1_1092 & out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11902 = out_f_roready_1238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1238 = out_wivalid_1_1092 & out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11903 = out_f_wivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_woready_1238 = out_woready_1_1092 & out_womask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11904 = out_f_woready_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11905 = ~out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11906 = ~out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11907 = ~out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11908 = ~out_womask_1238; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1063 = {programBufferMem_25, _out_prepend_T_1063}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11909 = out_prepend_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11910 = _out_T_11909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1064 = _out_T_11910; // @[RegisterRouter.scala:87:24] wire out_rimask_1239 = \|_out_rimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_wimask_1239 = &_out_wimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_romask_1239 = \|_out_romask_T_1239; // @[RegisterRouter.scala:87:24] wire out_womask_1239 = &_out_womask_T_1239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1239 = out_rivalid_1_1093 & out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11912 = out_f_rivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_roready_1239 = out_roready_1_1093 & out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11913 = out_f_roready_1239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1239 = out_wivalid_1_1093 & out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11914 = out_f_wivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_woready_1239 = out_woready_1_1093 & out_womask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11915 = out_f_woready_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11916 = ~out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11917 = ~out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11918 = ~out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11919 = ~out_womask_1239; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1064 = {programBufferMem_26, _out_prepend_T_1064}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11920 = out_prepend_1064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11921 = _out_T_11920; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1065 = _out_T_11921; // @[RegisterRouter.scala:87:24] wire out_rimask_1240 = \|_out_rimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_wimask_1240 = &_out_wimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_romask_1240 = \|_out_romask_T_1240; // @[RegisterRouter.scala:87:24] wire out_womask_1240 = &_out_womask_T_1240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1240 = out_rivalid_1_1094 & out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11923 = out_f_rivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_roready_1240 = out_roready_1_1094 & out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11924 = out_f_roready_1240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1240 = out_wivalid_1_1094 & out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11925 = out_f_wivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_woready_1240 = out_woready_1_1094 & out_womask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11926 = out_f_woready_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11927 = ~out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11928 = ~out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11929 = ~out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11930 = ~out_womask_1240; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1065 = {programBufferMem_27, _out_prepend_T_1065}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11931 = out_prepend_1065; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11932 = _out_T_11931; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1066 = _out_T_11932; // @[RegisterRouter.scala:87:24] wire out_rimask_1241 = \|_out_rimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_wimask_1241 = &_out_wimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_romask_1241 = \|_out_romask_T_1241; // @[RegisterRouter.scala:87:24] wire out_womask_1241 = &_out_womask_T_1241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1241 = out_rivalid_1_1095 & out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11934 = out_f_rivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_roready_1241 = out_roready_1_1095 & out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11935 = out_f_roready_1241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1241 = out_wivalid_1_1095 & out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11936 = out_f_wivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_woready_1241 = out_woready_1_1095 & out_womask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11937 = out_f_woready_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11938 = ~out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11939 = ~out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11940 = ~out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11941 = ~out_womask_1241; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1066 = {programBufferMem_28, _out_prepend_T_1066}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11942 = out_prepend_1066; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11943 = _out_T_11942; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1067 = _out_T_11943; // @[RegisterRouter.scala:87:24] wire out_rimask_1242 = \|_out_rimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_wimask_1242 = &_out_wimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_romask_1242 = \|_out_romask_T_1242; // @[RegisterRouter.scala:87:24] wire out_womask_1242 = &_out_womask_T_1242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1242 = out_rivalid_1_1096 & out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11945 = out_f_rivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_roready_1242 = out_roready_1_1096 & out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11946 = out_f_roready_1242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1242 = out_wivalid_1_1096 & out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11947 = out_f_wivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_woready_1242 = out_woready_1_1096 & out_womask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11948 = out_f_woready_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11949 = ~out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11950 = ~out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11951 = ~out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11952 = ~out_womask_1242; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1067 = {programBufferMem_29, _out_prepend_T_1067}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11953 = out_prepend_1067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11954 = _out_T_11953; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1068 = _out_T_11954; // @[RegisterRouter.scala:87:24] wire out_rimask_1243 = \|_out_rimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_wimask_1243 = &_out_wimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_romask_1243 = \|_out_romask_T_1243; // @[RegisterRouter.scala:87:24] wire out_womask_1243 = &_out_womask_T_1243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1243 = out_rivalid_1_1097 & out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11956 = out_f_rivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_roready_1243 = out_roready_1_1097 & out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11957 = out_f_roready_1243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1243 = out_wivalid_1_1097 & out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11958 = out_f_wivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_woready_1243 = out_woready_1_1097 & out_womask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11959 = out_f_woready_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11960 = ~out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11961 = ~out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11962 = ~out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11963 = ~out_womask_1243; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1068 = {programBufferMem_30, _out_prepend_T_1068}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11964 = out_prepend_1068; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11965 = _out_T_11964; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1069 = _out_T_11965; // @[RegisterRouter.scala:87:24] wire out_rimask_1244 = \|_out_rimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_wimask_1244 = &_out_wimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_romask_1244 = \|_out_romask_T_1244; // @[RegisterRouter.scala:87:24] wire out_womask_1244 = &_out_womask_T_1244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1244 = out_rivalid_1_1098 & out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11967 = out_f_rivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_roready_1244 = out_roready_1_1098 & out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11968 = out_f_roready_1244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1244 = out_wivalid_1_1098 & out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11969 = out_f_wivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_woready_1244 = out_woready_1_1098 & out_womask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11970 = out_f_woready_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11971 = ~out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11972 = ~out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11973 = ~out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11974 = ~out_womask_1244; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1069 = {programBufferMem_31, _out_prepend_T_1069}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11975 = out_prepend_1069; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11976 = _out_T_11975; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_107 = _out_T_11976; // @[MuxLiteral.scala:49:48] wire out_rimask_1245 = \|_out_rimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_wimask_1245 = &_out_wimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_romask_1245 = \|_out_romask_T_1245; // @[RegisterRouter.scala:87:24] wire out_womask_1245 = &_out_womask_T_1245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1245 = out_rivalid_1_1099 & out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11978 = out_f_rivalid_1245; // @[RegisterRouter.scala:87:24] wire out_f_roready_1245 = out_roready_1_1099 & out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11979 = out_f_roready_1245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1245 = out_wivalid_1_1099 & out_wimask_1245; // @[RegisterRouter.scala:87:24] wire out_f_woready_1245 = out_woready_1_1099 & out_womask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11980 = ~out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11981 = ~out_wimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11982 = ~out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11983 = ~out_womask_1245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11985 = _out_T_11984; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1070 = _out_T_11985; // @[RegisterRouter.scala:87:24] wire out_rimask_1246 = \|_out_rimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_wimask_1246 = &_out_wimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_romask_1246 = \|_out_romask_T_1246; // @[RegisterRouter.scala:87:24] wire out_womask_1246 = &_out_womask_T_1246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1246 = out_rivalid_1_1100 & out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11987 = out_f_rivalid_1246; // @[RegisterRouter.scala:87:24] wire out_f_roready_1246 = out_roready_1_1100 & out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11988 = out_f_roready_1246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1246 = out_wivalid_1_1100 & out_wimask_1246; // @[RegisterRouter.scala:87:24] wire out_f_woready_1246 = out_woready_1_1100 & out_womask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11989 = ~out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11990 = ~out_wimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11991 = ~out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11992 = ~out_womask_1246; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1070 = {hi_66, flags_0_go, _out_prepend_T_1070}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11993 = out_prepend_1070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11994 = _out_T_11993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1071 = _out_T_11994; // @[RegisterRouter.scala:87:24] wire out_rimask_1247 = \|_out_rimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_wimask_1247 = &_out_wimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_romask_1247 = \|_out_romask_T_1247; // @[RegisterRouter.scala:87:24] wire out_womask_1247 = &_out_womask_T_1247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1247 = out_rivalid_1_1101 & out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11996 = out_f_rivalid_1247; // @[RegisterRouter.scala:87:24] wire out_f_roready_1247 = out_roready_1_1101 & out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11997 = out_f_roready_1247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1247 = out_wivalid_1_1101 & out_wimask_1247; // @[RegisterRouter.scala:87:24] wire out_f_woready_1247 = out_woready_1_1101 & out_womask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11998 = ~out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11999 = ~out_wimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12000 = ~out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12001 = ~out_womask_1247; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1071 = {hi_67, flags_0_go, _out_prepend_T_1071}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12002 = out_prepend_1071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12003 = _out_T_12002; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1072 = _out_T_12003; // @[RegisterRouter.scala:87:24] wire out_rimask_1248 = \|_out_rimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_wimask_1248 = &_out_wimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_romask_1248 = \|_out_romask_T_1248; // @[RegisterRouter.scala:87:24] wire out_womask_1248 = &_out_womask_T_1248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1248 = out_rivalid_1_1102 & out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12005 = out_f_rivalid_1248; // @[RegisterRouter.scala:87:24] wire out_f_roready_1248 = out_roready_1_1102 & out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12006 = out_f_roready_1248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1248 = out_wivalid_1_1102 & out_wimask_1248; // @[RegisterRouter.scala:87:24] wire out_f_woready_1248 = out_woready_1_1102 & out_womask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12007 = ~out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12008 = ~out_wimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12009 = ~out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12010 = ~out_womask_1248; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1072 = {hi_68, flags_0_go, _out_prepend_T_1072}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12011 = out_prepend_1072; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12012 = _out_T_12011; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1073 = _out_T_12012; // @[RegisterRouter.scala:87:24] wire out_rimask_1249 = \|_out_rimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_wimask_1249 = &_out_wimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_romask_1249 = \|_out_romask_T_1249; // @[RegisterRouter.scala:87:24] wire out_womask_1249 = &_out_womask_T_1249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1249 = out_rivalid_1_1103 & out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12014 = out_f_rivalid_1249; // @[RegisterRouter.scala:87:24] wire out_f_roready_1249 = out_roready_1_1103 & out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12015 = out_f_roready_1249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1249 = out_wivalid_1_1103 & out_wimask_1249; // @[RegisterRouter.scala:87:24] wire out_f_woready_1249 = out_woready_1_1103 & out_womask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12016 = ~out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12017 = ~out_wimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12018 = ~out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12019 = ~out_womask_1249; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1073 = {hi_69, flags_0_go, _out_prepend_T_1073}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12020 = out_prepend_1073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12021 = _out_T_12020; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1074 = _out_T_12021; // @[RegisterRouter.scala:87:24] wire out_rimask_1250 = \|_out_rimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_wimask_1250 = &_out_wimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_romask_1250 = \|_out_romask_T_1250; // @[RegisterRouter.scala:87:24] wire out_womask_1250 = &_out_womask_T_1250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1250 = out_rivalid_1_1104 & out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12023 = out_f_rivalid_1250; // @[RegisterRouter.scala:87:24] wire out_f_roready_1250 = out_roready_1_1104 & out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12024 = out_f_roready_1250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1250 = out_wivalid_1_1104 & out_wimask_1250; // @[RegisterRouter.scala:87:24] wire out_f_woready_1250 = out_woready_1_1104 & out_womask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12025 = ~out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12026 = ~out_wimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12027 = ~out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12028 = ~out_womask_1250; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1074 = {hi_70, flags_0_go, _out_prepend_T_1074}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12029 = out_prepend_1074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12030 = _out_T_12029; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1075 = _out_T_12030; // @[RegisterRouter.scala:87:24] wire out_rimask_1251 = \|_out_rimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_wimask_1251 = &_out_wimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_romask_1251 = \|_out_romask_T_1251; // @[RegisterRouter.scala:87:24] wire out_womask_1251 = &_out_womask_T_1251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1251 = out_rivalid_1_1105 & out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12032 = out_f_rivalid_1251; // @[RegisterRouter.scala:87:24] wire out_f_roready_1251 = out_roready_1_1105 & out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12033 = out_f_roready_1251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1251 = out_wivalid_1_1105 & out_wimask_1251; // @[RegisterRouter.scala:87:24] wire out_f_woready_1251 = out_woready_1_1105 & out_womask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12034 = ~out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12035 = ~out_wimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12036 = ~out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12037 = ~out_womask_1251; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1075 = {hi_71, flags_0_go, _out_prepend_T_1075}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12038 = out_prepend_1075; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12039 = _out_T_12038; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1076 = _out_T_12039; // @[RegisterRouter.scala:87:24] wire out_rimask_1252 = \|_out_rimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_wimask_1252 = &_out_wimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_romask_1252 = \|_out_romask_T_1252; // @[RegisterRouter.scala:87:24] wire out_womask_1252 = &_out_womask_T_1252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1252 = out_rivalid_1_1106 & out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12041 = out_f_rivalid_1252; // @[RegisterRouter.scala:87:24] wire out_f_roready_1252 = out_roready_1_1106 & out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12042 = out_f_roready_1252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1252 = out_wivalid_1_1106 & out_wimask_1252; // @[RegisterRouter.scala:87:24] wire out_f_woready_1252 = out_woready_1_1106 & out_womask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12043 = ~out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12044 = ~out_wimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12045 = ~out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12046 = ~out_womask_1252; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1076 = {hi_72, flags_0_go, _out_prepend_T_1076}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12047 = out_prepend_1076; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12048 = _out_T_12047; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_136 = _out_T_12048; // @[MuxLiteral.scala:49:48] wire out_rimask_1253 = \|_out_rimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_wimask_1253 = &_out_wimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_romask_1253 = \|_out_romask_T_1253; // @[RegisterRouter.scala:87:24] wire out_womask_1253 = &_out_womask_T_1253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1253 = out_rivalid_1_1107 & out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12050 = out_f_rivalid_1253; // @[RegisterRouter.scala:87:24] wire out_f_roready_1253 = out_roready_1_1107 & out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12051 = out_f_roready_1253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1253 = out_wivalid_1_1107 & out_wimask_1253; // @[RegisterRouter.scala:87:24] wire out_f_woready_1253 = out_woready_1_1107 & out_womask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12052 = ~out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12053 = ~out_wimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12054 = ~out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12055 = ~out_womask_1253; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12057 = _out_T_12056; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1077 = _out_T_12057; // @[RegisterRouter.scala:87:24] wire out_rimask_1254 = \|_out_rimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_wimask_1254 = &_out_wimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_romask_1254 = \|_out_romask_T_1254; // @[RegisterRouter.scala:87:24] wire out_womask_1254 = &_out_womask_T_1254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1254 = out_rivalid_1_1108 & out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12059 = out_f_rivalid_1254; // @[RegisterRouter.scala:87:24] wire out_f_roready_1254 = out_roready_1_1108 & out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12060 = out_f_roready_1254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1254 = out_wivalid_1_1108 & out_wimask_1254; // @[RegisterRouter.scala:87:24] wire out_f_woready_1254 = out_woready_1_1108 & out_womask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12061 = ~out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12062 = ~out_wimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12063 = ~out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12064 = ~out_womask_1254; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1077 = {hi_538, flags_0_go, _out_prepend_T_1077}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12065 = out_prepend_1077; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12066 = _out_T_12065; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1078 = _out_T_12066; // @[RegisterRouter.scala:87:24] wire out_rimask_1255 = \|_out_rimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_wimask_1255 = &_out_wimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_romask_1255 = \|_out_romask_T_1255; // @[RegisterRouter.scala:87:24] wire out_womask_1255 = &_out_womask_T_1255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1255 = out_rivalid_1_1109 & out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12068 = out_f_rivalid_1255; // @[RegisterRouter.scala:87:24] wire out_f_roready_1255 = out_roready_1_1109 & out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12069 = out_f_roready_1255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1255 = out_wivalid_1_1109 & out_wimask_1255; // @[RegisterRouter.scala:87:24] wire out_f_woready_1255 = out_woready_1_1109 & out_womask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12070 = ~out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12071 = ~out_wimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12072 = ~out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12073 = ~out_womask_1255; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1078 = {hi_539, flags_0_go, _out_prepend_T_1078}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12074 = out_prepend_1078; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12075 = _out_T_12074; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1079 = _out_T_12075; // @[RegisterRouter.scala:87:24] wire out_rimask_1256 = \|_out_rimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_wimask_1256 = &_out_wimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_romask_1256 = \|_out_romask_T_1256; // @[RegisterRouter.scala:87:24] wire out_womask_1256 = &_out_womask_T_1256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1256 = out_rivalid_1_1110 & out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12077 = out_f_rivalid_1256; // @[RegisterRouter.scala:87:24] wire out_f_roready_1256 = out_roready_1_1110 & out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12078 = out_f_roready_1256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1256 = out_wivalid_1_1110 & out_wimask_1256; // @[RegisterRouter.scala:87:24] wire out_f_woready_1256 = out_woready_1_1110 & out_womask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12079 = ~out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12080 = ~out_wimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12081 = ~out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12082 = ~out_womask_1256; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1079 = {hi_540, flags_0_go, _out_prepend_T_1079}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12083 = out_prepend_1079; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12084 = _out_T_12083; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1080 = _out_T_12084; // @[RegisterRouter.scala:87:24] wire out_rimask_1257 = \|_out_rimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_wimask_1257 = &_out_wimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_romask_1257 = \|_out_romask_T_1257; // @[RegisterRouter.scala:87:24] wire out_womask_1257 = &_out_womask_T_1257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1257 = out_rivalid_1_1111 & out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12086 = out_f_rivalid_1257; // @[RegisterRouter.scala:87:24] wire out_f_roready_1257 = out_roready_1_1111 & out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12087 = out_f_roready_1257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1257 = out_wivalid_1_1111 & out_wimask_1257; // @[RegisterRouter.scala:87:24] wire out_f_woready_1257 = out_woready_1_1111 & out_womask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12088 = ~out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12089 = ~out_wimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12090 = ~out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12091 = ~out_womask_1257; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1080 = {hi_541, flags_0_go, _out_prepend_T_1080}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12092 = out_prepend_1080; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12093 = _out_T_12092; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1081 = _out_T_12093; // @[RegisterRouter.scala:87:24] wire out_rimask_1258 = \|_out_rimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_wimask_1258 = &_out_wimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_romask_1258 = \|_out_romask_T_1258; // @[RegisterRouter.scala:87:24] wire out_womask_1258 = &_out_womask_T_1258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1258 = out_rivalid_1_1112 & out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12095 = out_f_rivalid_1258; // @[RegisterRouter.scala:87:24] wire out_f_roready_1258 = out_roready_1_1112 & out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12096 = out_f_roready_1258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1258 = out_wivalid_1_1112 & out_wimask_1258; // @[RegisterRouter.scala:87:24] wire out_f_woready_1258 = out_woready_1_1112 & out_womask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12097 = ~out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12098 = ~out_wimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12099 = ~out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12100 = ~out_womask_1258; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1081 = {hi_542, flags_0_go, _out_prepend_T_1081}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12101 = out_prepend_1081; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12102 = _out_T_12101; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1082 = _out_T_12102; // @[RegisterRouter.scala:87:24] wire out_rimask_1259 = \|_out_rimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_wimask_1259 = &_out_wimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_romask_1259 = \|_out_romask_T_1259; // @[RegisterRouter.scala:87:24] wire out_womask_1259 = &_out_womask_T_1259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1259 = out_rivalid_1_1113 & out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12104 = out_f_rivalid_1259; // @[RegisterRouter.scala:87:24] wire out_f_roready_1259 = out_roready_1_1113 & out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12105 = out_f_roready_1259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1259 = out_wivalid_1_1113 & out_wimask_1259; // @[RegisterRouter.scala:87:24] wire out_f_woready_1259 = out_woready_1_1113 & out_womask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12106 = ~out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12107 = ~out_wimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12108 = ~out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12109 = ~out_womask_1259; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1082 = {hi_543, flags_0_go, _out_prepend_T_1082}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12110 = out_prepend_1082; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12111 = _out_T_12110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1083 = _out_T_12111; // @[RegisterRouter.scala:87:24] wire out_rimask_1260 = \|_out_rimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_wimask_1260 = &_out_wimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_romask_1260 = \|_out_romask_T_1260; // @[RegisterRouter.scala:87:24] wire out_womask_1260 = &_out_womask_T_1260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1260 = out_rivalid_1_1114 & out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12113 = out_f_rivalid_1260; // @[RegisterRouter.scala:87:24] wire out_f_roready_1260 = out_roready_1_1114 & out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12114 = out_f_roready_1260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1260 = out_wivalid_1_1114 & out_wimask_1260; // @[RegisterRouter.scala:87:24] wire out_f_woready_1260 = out_woready_1_1114 & out_womask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12115 = ~out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12116 = ~out_wimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12117 = ~out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12118 = ~out_womask_1260; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1083 = {hi_544, flags_0_go, _out_prepend_T_1083}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12119 = out_prepend_1083; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12120 = _out_T_12119; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_195 = _out_T_12120; // @[MuxLiteral.scala:49:48] wire out_rimask_1261 = \|_out_rimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_wimask_1261 = &_out_wimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_romask_1261 = \|_out_romask_T_1261; // @[RegisterRouter.scala:87:24] wire out_womask_1261 = &_out_womask_T_1261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1261 = out_rivalid_1_1115 & out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12122 = out_f_rivalid_1261; // @[RegisterRouter.scala:87:24] wire out_f_roready_1261 = out_roready_1_1115 & out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12123 = out_f_roready_1261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1261 = out_wivalid_1_1115 & out_wimask_1261; // @[RegisterRouter.scala:87:24] wire out_f_woready_1261 = out_woready_1_1115 & out_womask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12124 = ~out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12125 = ~out_wimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12126 = ~out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12127 = ~out_womask_1261; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12129 = _out_T_12128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1084 = _out_T_12129; // @[RegisterRouter.scala:87:24] wire out_rimask_1262 = \|_out_rimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_wimask_1262 = &_out_wimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_romask_1262 = \|_out_romask_T_1262; // @[RegisterRouter.scala:87:24] wire out_womask_1262 = &_out_womask_T_1262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1262 = out_rivalid_1_1116 & out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12131 = out_f_rivalid_1262; // @[RegisterRouter.scala:87:24] wire out_f_roready_1262 = out_roready_1_1116 & out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12132 = out_f_roready_1262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1262 = out_wivalid_1_1116 & out_wimask_1262; // @[RegisterRouter.scala:87:24] wire out_f_woready_1262 = out_woready_1_1116 & out_womask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12133 = ~out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12134 = ~out_wimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12135 = ~out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12136 = ~out_womask_1262; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1084 = {hi_890, flags_0_go, _out_prepend_T_1084}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12137 = out_prepend_1084; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12138 = _out_T_12137; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1085 = _out_T_12138; // @[RegisterRouter.scala:87:24] wire out_rimask_1263 = \|_out_rimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_wimask_1263 = &_out_wimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_romask_1263 = \|_out_romask_T_1263; // @[RegisterRouter.scala:87:24] wire out_womask_1263 = &_out_womask_T_1263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1263 = out_rivalid_1_1117 & out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12140 = out_f_rivalid_1263; // @[RegisterRouter.scala:87:24] wire out_f_roready_1263 = out_roready_1_1117 & out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12141 = out_f_roready_1263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1263 = out_wivalid_1_1117 & out_wimask_1263; // @[RegisterRouter.scala:87:24] wire out_f_woready_1263 = out_woready_1_1117 & out_womask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12142 = ~out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12143 = ~out_wimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12144 = ~out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12145 = ~out_womask_1263; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1085 = {hi_891, flags_0_go, _out_prepend_T_1085}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12146 = out_prepend_1085; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12147 = _out_T_12146; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1086 = _out_T_12147; // @[RegisterRouter.scala:87:24] wire out_rimask_1264 = \|_out_rimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_wimask_1264 = &_out_wimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_romask_1264 = \|_out_romask_T_1264; // @[RegisterRouter.scala:87:24] wire out_womask_1264 = &_out_womask_T_1264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1264 = out_rivalid_1_1118 & out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12149 = out_f_rivalid_1264; // @[RegisterRouter.scala:87:24] wire out_f_roready_1264 = out_roready_1_1118 & out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12150 = out_f_roready_1264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1264 = out_wivalid_1_1118 & out_wimask_1264; // @[RegisterRouter.scala:87:24] wire out_f_woready_1264 = out_woready_1_1118 & out_womask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12151 = ~out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12152 = ~out_wimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12153 = ~out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12154 = ~out_womask_1264; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1086 = {hi_892, flags_0_go, _out_prepend_T_1086}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12155 = out_prepend_1086; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12156 = _out_T_12155; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1087 = _out_T_12156; // @[RegisterRouter.scala:87:24] wire out_rimask_1265 = \|_out_rimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_wimask_1265 = &_out_wimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_romask_1265 = \|_out_romask_T_1265; // @[RegisterRouter.scala:87:24] wire out_womask_1265 = &_out_womask_T_1265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1265 = out_rivalid_1_1119 & out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12158 = out_f_rivalid_1265; // @[RegisterRouter.scala:87:24] wire out_f_roready_1265 = out_roready_1_1119 & out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12159 = out_f_roready_1265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1265 = out_wivalid_1_1119 & out_wimask_1265; // @[RegisterRouter.scala:87:24] wire out_f_woready_1265 = out_woready_1_1119 & out_womask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12160 = ~out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12161 = ~out_wimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12162 = ~out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12163 = ~out_womask_1265; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1087 = {hi_893, flags_0_go, _out_prepend_T_1087}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12164 = out_prepend_1087; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12165 = _out_T_12164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1088 = _out_T_12165; // @[RegisterRouter.scala:87:24] wire out_rimask_1266 = \|_out_rimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_wimask_1266 = &_out_wimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_romask_1266 = \|_out_romask_T_1266; // @[RegisterRouter.scala:87:24] wire out_womask_1266 = &_out_womask_T_1266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1266 = out_rivalid_1_1120 & out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12167 = out_f_rivalid_1266; // @[RegisterRouter.scala:87:24] wire out_f_roready_1266 = out_roready_1_1120 & out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12168 = out_f_roready_1266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1266 = out_wivalid_1_1120 & out_wimask_1266; // @[RegisterRouter.scala:87:24] wire out_f_woready_1266 = out_woready_1_1120 & out_womask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12169 = ~out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12170 = ~out_wimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12171 = ~out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12172 = ~out_womask_1266; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1088 = {hi_894, flags_0_go, _out_prepend_T_1088}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12173 = out_prepend_1088; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12174 = _out_T_12173; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1089 = _out_T_12174; // @[RegisterRouter.scala:87:24] wire out_rimask_1267 = \|_out_rimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_wimask_1267 = &_out_wimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_romask_1267 = \|_out_romask_T_1267; // @[RegisterRouter.scala:87:24] wire out_womask_1267 = &_out_womask_T_1267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1267 = out_rivalid_1_1121 & out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12176 = out_f_rivalid_1267; // @[RegisterRouter.scala:87:24] wire out_f_roready_1267 = out_roready_1_1121 & out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12177 = out_f_roready_1267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1267 = out_wivalid_1_1121 & out_wimask_1267; // @[RegisterRouter.scala:87:24] wire out_f_woready_1267 = out_woready_1_1121 & out_womask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12178 = ~out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12179 = ~out_wimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12180 = ~out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12181 = ~out_womask_1267; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1089 = {hi_895, flags_0_go, _out_prepend_T_1089}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12182 = out_prepend_1089; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12183 = _out_T_12182; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1090 = _out_T_12183; // @[RegisterRouter.scala:87:24] wire out_rimask_1268 = \|_out_rimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_wimask_1268 = &_out_wimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_romask_1268 = \|_out_romask_T_1268; // @[RegisterRouter.scala:87:24] wire out_womask_1268 = &_out_womask_T_1268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1268 = out_rivalid_1_1122 & out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12185 = out_f_rivalid_1268; // @[RegisterRouter.scala:87:24] wire out_f_roready_1268 = out_roready_1_1122 & out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12186 = out_f_roready_1268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1268 = out_wivalid_1_1122 & out_wimask_1268; // @[RegisterRouter.scala:87:24] wire out_f_woready_1268 = out_woready_1_1122 & out_womask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12187 = ~out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12188 = ~out_wimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12189 = ~out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12190 = ~out_womask_1268; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1090 = {hi_896, flags_0_go, _out_prepend_T_1090}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12191 = out_prepend_1090; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12192 = _out_T_12191; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_239 = _out_T_12192; // @[MuxLiteral.scala:49:48] wire out_rimask_1269 = \|_out_rimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_wimask_1269 = &_out_wimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_romask_1269 = \|_out_romask_T_1269; // @[RegisterRouter.scala:87:24] wire out_womask_1269 = &_out_womask_T_1269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1269 = out_rivalid_1_1123 & out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12194 = out_f_rivalid_1269; // @[RegisterRouter.scala:87:24] wire out_f_roready_1269 = out_roready_1_1123 & out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12195 = out_f_roready_1269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1269 = out_wivalid_1_1123 & out_wimask_1269; // @[RegisterRouter.scala:87:24] wire out_f_woready_1269 = out_woready_1_1123 & out_womask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12196 = ~out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12197 = ~out_wimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12198 = ~out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12199 = ~out_womask_1269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12201 = _out_T_12200; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1091 = _out_T_12201; // @[RegisterRouter.scala:87:24] wire out_rimask_1270 = \|_out_rimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_wimask_1270 = &_out_wimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_romask_1270 = \|_out_romask_T_1270; // @[RegisterRouter.scala:87:24] wire out_womask_1270 = &_out_womask_T_1270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1270 = out_rivalid_1_1124 & out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12203 = out_f_rivalid_1270; // @[RegisterRouter.scala:87:24] wire out_f_roready_1270 = out_roready_1_1124 & out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12204 = out_f_roready_1270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1270 = out_wivalid_1_1124 & out_wimask_1270; // @[RegisterRouter.scala:87:24] wire out_f_woready_1270 = out_woready_1_1124 & out_womask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12205 = ~out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12206 = ~out_wimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12207 = ~out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12208 = ~out_womask_1270; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1091 = {hi_914, flags_0_go, _out_prepend_T_1091}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12209 = out_prepend_1091; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12210 = _out_T_12209; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1092 = _out_T_12210; // @[RegisterRouter.scala:87:24] wire out_rimask_1271 = \|_out_rimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_wimask_1271 = &_out_wimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_romask_1271 = \|_out_romask_T_1271; // @[RegisterRouter.scala:87:24] wire out_womask_1271 = &_out_womask_T_1271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1271 = out_rivalid_1_1125 & out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12212 = out_f_rivalid_1271; // @[RegisterRouter.scala:87:24] wire out_f_roready_1271 = out_roready_1_1125 & out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12213 = out_f_roready_1271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1271 = out_wivalid_1_1125 & out_wimask_1271; // @[RegisterRouter.scala:87:24] wire out_f_woready_1271 = out_woready_1_1125 & out_womask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12214 = ~out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12215 = ~out_wimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12216 = ~out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12217 = ~out_womask_1271; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1092 = {hi_915, flags_0_go, _out_prepend_T_1092}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12218 = out_prepend_1092; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12219 = _out_T_12218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1093 = _out_T_12219; // @[RegisterRouter.scala:87:24] wire out_rimask_1272 = \|_out_rimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_wimask_1272 = &_out_wimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_romask_1272 = \|_out_romask_T_1272; // @[RegisterRouter.scala:87:24] wire out_womask_1272 = &_out_womask_T_1272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1272 = out_rivalid_1_1126 & out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12221 = out_f_rivalid_1272; // @[RegisterRouter.scala:87:24] wire out_f_roready_1272 = out_roready_1_1126 & out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12222 = out_f_roready_1272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1272 = out_wivalid_1_1126 & out_wimask_1272; // @[RegisterRouter.scala:87:24] wire out_f_woready_1272 = out_woready_1_1126 & out_womask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12223 = ~out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12224 = ~out_wimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12225 = ~out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12226 = ~out_womask_1272; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1093 = {hi_916, flags_0_go, _out_prepend_T_1093}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12227 = out_prepend_1093; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12228 = _out_T_12227; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1094 = _out_T_12228; // @[RegisterRouter.scala:87:24] wire out_rimask_1273 = \|_out_rimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_wimask_1273 = &_out_wimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_romask_1273 = \|_out_romask_T_1273; // @[RegisterRouter.scala:87:24] wire out_womask_1273 = &_out_womask_T_1273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1273 = out_rivalid_1_1127 & out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12230 = out_f_rivalid_1273; // @[RegisterRouter.scala:87:24] wire out_f_roready_1273 = out_roready_1_1127 & out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12231 = out_f_roready_1273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1273 = out_wivalid_1_1127 & out_wimask_1273; // @[RegisterRouter.scala:87:24] wire out_f_woready_1273 = out_woready_1_1127 & out_womask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12232 = ~out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12233 = ~out_wimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12234 = ~out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12235 = ~out_womask_1273; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1094 = {hi_917, flags_0_go, _out_prepend_T_1094}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12236 = out_prepend_1094; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12237 = _out_T_12236; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1095 = _out_T_12237; // @[RegisterRouter.scala:87:24] wire out_rimask_1274 = \|_out_rimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_wimask_1274 = &_out_wimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_romask_1274 = \|_out_romask_T_1274; // @[RegisterRouter.scala:87:24] wire out_womask_1274 = &_out_womask_T_1274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1274 = out_rivalid_1_1128 & out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12239 = out_f_rivalid_1274; // @[RegisterRouter.scala:87:24] wire out_f_roready_1274 = out_roready_1_1128 & out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12240 = out_f_roready_1274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1274 = out_wivalid_1_1128 & out_wimask_1274; // @[RegisterRouter.scala:87:24] wire out_f_woready_1274 = out_woready_1_1128 & out_womask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12241 = ~out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12242 = ~out_wimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12243 = ~out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12244 = ~out_womask_1274; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1095 = {hi_918, flags_0_go, _out_prepend_T_1095}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12245 = out_prepend_1095; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12246 = _out_T_12245; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1096 = _out_T_12246; // @[RegisterRouter.scala:87:24] wire out_rimask_1275 = \|_out_rimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_wimask_1275 = &_out_wimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_romask_1275 = \|_out_romask_T_1275; // @[RegisterRouter.scala:87:24] wire out_womask_1275 = &_out_womask_T_1275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1275 = out_rivalid_1_1129 & out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12248 = out_f_rivalid_1275; // @[RegisterRouter.scala:87:24] wire out_f_roready_1275 = out_roready_1_1129 & out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12249 = out_f_roready_1275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1275 = out_wivalid_1_1129 & out_wimask_1275; // @[RegisterRouter.scala:87:24] wire out_f_woready_1275 = out_woready_1_1129 & out_womask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12250 = ~out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12251 = ~out_wimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12252 = ~out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12253 = ~out_womask_1275; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1096 = {hi_919, flags_0_go, _out_prepend_T_1096}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12254 = out_prepend_1096; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12255 = _out_T_12254; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1097 = _out_T_12255; // @[RegisterRouter.scala:87:24] wire out_rimask_1276 = \|_out_rimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_wimask_1276 = &_out_wimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_romask_1276 = \|_out_romask_T_1276; // @[RegisterRouter.scala:87:24] wire out_womask_1276 = &_out_womask_T_1276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1276 = out_rivalid_1_1130 & out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12257 = out_f_rivalid_1276; // @[RegisterRouter.scala:87:24] wire out_f_roready_1276 = out_roready_1_1130 & out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12258 = out_f_roready_1276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1276 = out_wivalid_1_1130 & out_wimask_1276; // @[RegisterRouter.scala:87:24] wire out_f_woready_1276 = out_woready_1_1130 & out_womask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12259 = ~out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12260 = ~out_wimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12261 = ~out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12262 = ~out_womask_1276; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1097 = {hi_920, flags_0_go, _out_prepend_T_1097}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12263 = out_prepend_1097; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12264 = _out_T_12263; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_242 = _out_T_12264; // @[MuxLiteral.scala:49:48] wire out_rimask_1277 = \|_out_rimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_wimask_1277 = &_out_wimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_romask_1277 = \|_out_romask_T_1277; // @[RegisterRouter.scala:87:24] wire out_womask_1277 = &_out_womask_T_1277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1277 = out_rivalid_1_1131 & out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12266 = out_f_rivalid_1277; // @[RegisterRouter.scala:87:24] wire out_f_roready_1277 = out_roready_1_1131 & out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12267 = out_f_roready_1277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1277 = out_wivalid_1_1131 & out_wimask_1277; // @[RegisterRouter.scala:87:24] wire out_f_woready_1277 = out_woready_1_1131 & out_womask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12268 = ~out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12269 = ~out_wimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12270 = ~out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12271 = ~out_womask_1277; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12273 = _out_T_12272; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1098 = _out_T_12273; // @[RegisterRouter.scala:87:24] wire out_rimask_1278 = \|_out_rimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_wimask_1278 = &_out_wimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_romask_1278 = \|_out_romask_T_1278; // @[RegisterRouter.scala:87:24] wire out_womask_1278 = &_out_womask_T_1278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1278 = out_rivalid_1_1132 & out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12275 = out_f_rivalid_1278; // @[RegisterRouter.scala:87:24] wire out_f_roready_1278 = out_roready_1_1132 & out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12276 = out_f_roready_1278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1278 = out_wivalid_1_1132 & out_wimask_1278; // @[RegisterRouter.scala:87:24] wire out_f_woready_1278 = out_woready_1_1132 & out_womask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12277 = ~out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12278 = ~out_wimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12279 = ~out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12280 = ~out_womask_1278; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1098 = {hi_26, flags_0_go, _out_prepend_T_1098}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12281 = out_prepend_1098; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12282 = _out_T_12281; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1099 = _out_T_12282; // @[RegisterRouter.scala:87:24] wire out_rimask_1279 = \|_out_rimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_wimask_1279 = &_out_wimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_romask_1279 = \|_out_romask_T_1279; // @[RegisterRouter.scala:87:24] wire out_womask_1279 = &_out_womask_T_1279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1279 = out_rivalid_1_1133 & out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12284 = out_f_rivalid_1279; // @[RegisterRouter.scala:87:24] wire out_f_roready_1279 = out_roready_1_1133 & out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12285 = out_f_roready_1279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1279 = out_wivalid_1_1133 & out_wimask_1279; // @[RegisterRouter.scala:87:24] wire out_f_woready_1279 = out_woready_1_1133 & out_womask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12286 = ~out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12287 = ~out_wimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12288 = ~out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12289 = ~out_womask_1279; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1099 = {hi_27, flags_0_go, _out_prepend_T_1099}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12290 = out_prepend_1099; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12291 = _out_T_12290; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1100 = _out_T_12291; // @[RegisterRouter.scala:87:24] wire out_rimask_1280 = \|_out_rimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_wimask_1280 = &_out_wimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_romask_1280 = \|_out_romask_T_1280; // @[RegisterRouter.scala:87:24] wire out_womask_1280 = &_out_womask_T_1280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1280 = out_rivalid_1_1134 & out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12293 = out_f_rivalid_1280; // @[RegisterRouter.scala:87:24] wire out_f_roready_1280 = out_roready_1_1134 & out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12294 = out_f_roready_1280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1280 = out_wivalid_1_1134 & out_wimask_1280; // @[RegisterRouter.scala:87:24] wire out_f_woready_1280 = out_woready_1_1134 & out_womask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12295 = ~out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12296 = ~out_wimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12297 = ~out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12298 = ~out_womask_1280; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1100 = {hi_28, flags_0_go, _out_prepend_T_1100}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12299 = out_prepend_1100; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12300 = _out_T_12299; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1101 = _out_T_12300; // @[RegisterRouter.scala:87:24] wire out_rimask_1281 = \|_out_rimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_wimask_1281 = &_out_wimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_romask_1281 = \|_out_romask_T_1281; // @[RegisterRouter.scala:87:24] wire out_womask_1281 = &_out_womask_T_1281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1281 = out_rivalid_1_1135 & out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12302 = out_f_rivalid_1281; // @[RegisterRouter.scala:87:24] wire out_f_roready_1281 = out_roready_1_1135 & out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12303 = out_f_roready_1281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1281 = out_wivalid_1_1135 & out_wimask_1281; // @[RegisterRouter.scala:87:24] wire out_f_woready_1281 = out_woready_1_1135 & out_womask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12304 = ~out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12305 = ~out_wimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12306 = ~out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12307 = ~out_womask_1281; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1101 = {hi_29, flags_0_go, _out_prepend_T_1101}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12308 = out_prepend_1101; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12309 = _out_T_12308; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1102 = _out_T_12309; // @[RegisterRouter.scala:87:24] wire out_rimask_1282 = \|_out_rimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_wimask_1282 = &_out_wimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_romask_1282 = \|_out_romask_T_1282; // @[RegisterRouter.scala:87:24] wire out_womask_1282 = &_out_womask_T_1282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1282 = out_rivalid_1_1136 & out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12311 = out_f_rivalid_1282; // @[RegisterRouter.scala:87:24] wire out_f_roready_1282 = out_roready_1_1136 & out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12312 = out_f_roready_1282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1282 = out_wivalid_1_1136 & out_wimask_1282; // @[RegisterRouter.scala:87:24] wire out_f_woready_1282 = out_woready_1_1136 & out_womask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12313 = ~out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12314 = ~out_wimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12315 = ~out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12316 = ~out_womask_1282; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1102 = {hi_30, flags_0_go, _out_prepend_T_1102}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12317 = out_prepend_1102; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12318 = _out_T_12317; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1103 = _out_T_12318; // @[RegisterRouter.scala:87:24] wire out_rimask_1283 = \|_out_rimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_wimask_1283 = &_out_wimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_romask_1283 = \|_out_romask_T_1283; // @[RegisterRouter.scala:87:24] wire out_womask_1283 = &_out_womask_T_1283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1283 = out_rivalid_1_1137 & out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12320 = out_f_rivalid_1283; // @[RegisterRouter.scala:87:24] wire out_f_roready_1283 = out_roready_1_1137 & out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12321 = out_f_roready_1283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1283 = out_wivalid_1_1137 & out_wimask_1283; // @[RegisterRouter.scala:87:24] wire out_f_woready_1283 = out_woready_1_1137 & out_womask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12322 = ~out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12323 = ~out_wimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12324 = ~out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12325 = ~out_womask_1283; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1103 = {hi_31, flags_0_go, _out_prepend_T_1103}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12326 = out_prepend_1103; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12327 = _out_T_12326; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1104 = _out_T_12327; // @[RegisterRouter.scala:87:24] wire out_rimask_1284 = \|_out_rimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_wimask_1284 = &_out_wimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_romask_1284 = \|_out_romask_T_1284; // @[RegisterRouter.scala:87:24] wire out_womask_1284 = &_out_womask_T_1284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1284 = out_rivalid_1_1138 & out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12329 = out_f_rivalid_1284; // @[RegisterRouter.scala:87:24] wire out_f_roready_1284 = out_roready_1_1138 & out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12330 = out_f_roready_1284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1284 = out_wivalid_1_1138 & out_wimask_1284; // @[RegisterRouter.scala:87:24] wire out_f_woready_1284 = out_woready_1_1138 & out_womask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12331 = ~out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12332 = ~out_wimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12333 = ~out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12334 = ~out_womask_1284; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1104 = {hi_32, flags_0_go, _out_prepend_T_1104}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12335 = out_prepend_1104; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12336 = _out_T_12335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_131 = _out_T_12336; // @[MuxLiteral.scala:49:48] wire out_rimask_1285 = \|_out_rimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_wimask_1285 = &_out_wimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_romask_1285 = \|_out_romask_T_1285; // @[RegisterRouter.scala:87:24] wire out_womask_1285 = &_out_womask_T_1285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1285 = out_rivalid_1_1139 & out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12338 = out_f_rivalid_1285; // @[RegisterRouter.scala:87:24] wire out_f_roready_1285 = out_roready_1_1139 & out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12339 = out_f_roready_1285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1285 = out_wivalid_1_1139 & out_wimask_1285; // @[RegisterRouter.scala:87:24] wire out_f_woready_1285 = out_woready_1_1139 & out_womask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12340 = ~out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12341 = ~out_wimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12342 = ~out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12343 = ~out_womask_1285; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12345 = _out_T_12344; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1105 = _out_T_12345; // @[RegisterRouter.scala:87:24] wire out_rimask_1286 = \|_out_rimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_wimask_1286 = &_out_wimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_romask_1286 = \|_out_romask_T_1286; // @[RegisterRouter.scala:87:24] wire out_womask_1286 = &_out_womask_T_1286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1286 = out_rivalid_1_1140 & out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12347 = out_f_rivalid_1286; // @[RegisterRouter.scala:87:24] wire out_f_roready_1286 = out_roready_1_1140 & out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12348 = out_f_roready_1286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1286 = out_wivalid_1_1140 & out_wimask_1286; // @[RegisterRouter.scala:87:24] wire out_f_woready_1286 = out_woready_1_1140 & out_womask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12349 = ~out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12350 = ~out_wimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12351 = ~out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12352 = ~out_womask_1286; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1105 = {hi_402, flags_0_go, _out_prepend_T_1105}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12353 = out_prepend_1105; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12354 = _out_T_12353; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1106 = _out_T_12354; // @[RegisterRouter.scala:87:24] wire out_rimask_1287 = \|_out_rimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_wimask_1287 = &_out_wimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_romask_1287 = \|_out_romask_T_1287; // @[RegisterRouter.scala:87:24] wire out_womask_1287 = &_out_womask_T_1287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1287 = out_rivalid_1_1141 & out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12356 = out_f_rivalid_1287; // @[RegisterRouter.scala:87:24] wire out_f_roready_1287 = out_roready_1_1141 & out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12357 = out_f_roready_1287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1287 = out_wivalid_1_1141 & out_wimask_1287; // @[RegisterRouter.scala:87:24] wire out_f_woready_1287 = out_woready_1_1141 & out_womask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12358 = ~out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12359 = ~out_wimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12360 = ~out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12361 = ~out_womask_1287; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1106 = {hi_403, flags_0_go, _out_prepend_T_1106}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12362 = out_prepend_1106; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12363 = _out_T_12362; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1107 = _out_T_12363; // @[RegisterRouter.scala:87:24] wire out_rimask_1288 = \|_out_rimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_wimask_1288 = &_out_wimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_romask_1288 = \|_out_romask_T_1288; // @[RegisterRouter.scala:87:24] wire out_womask_1288 = &_out_womask_T_1288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1288 = out_rivalid_1_1142 & out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12365 = out_f_rivalid_1288; // @[RegisterRouter.scala:87:24] wire out_f_roready_1288 = out_roready_1_1142 & out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12366 = out_f_roready_1288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1288 = out_wivalid_1_1142 & out_wimask_1288; // @[RegisterRouter.scala:87:24] wire out_f_woready_1288 = out_woready_1_1142 & out_womask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12367 = ~out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12368 = ~out_wimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12369 = ~out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12370 = ~out_womask_1288; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1107 = {hi_404, flags_0_go, _out_prepend_T_1107}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12371 = out_prepend_1107; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12372 = _out_T_12371; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1108 = _out_T_12372; // @[RegisterRouter.scala:87:24] wire out_rimask_1289 = \|_out_rimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_wimask_1289 = &_out_wimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_romask_1289 = \|_out_romask_T_1289; // @[RegisterRouter.scala:87:24] wire out_womask_1289 = &_out_womask_T_1289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1289 = out_rivalid_1_1143 & out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12374 = out_f_rivalid_1289; // @[RegisterRouter.scala:87:24] wire out_f_roready_1289 = out_roready_1_1143 & out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12375 = out_f_roready_1289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1289 = out_wivalid_1_1143 & out_wimask_1289; // @[RegisterRouter.scala:87:24] wire out_f_woready_1289 = out_woready_1_1143 & out_womask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12376 = ~out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12377 = ~out_wimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12378 = ~out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12379 = ~out_womask_1289; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1108 = {hi_405, flags_0_go, _out_prepend_T_1108}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12380 = out_prepend_1108; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12381 = _out_T_12380; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1109 = _out_T_12381; // @[RegisterRouter.scala:87:24] wire out_rimask_1290 = \|_out_rimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_wimask_1290 = &_out_wimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_romask_1290 = \|_out_romask_T_1290; // @[RegisterRouter.scala:87:24] wire out_womask_1290 = &_out_womask_T_1290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1290 = out_rivalid_1_1144 & out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12383 = out_f_rivalid_1290; // @[RegisterRouter.scala:87:24] wire out_f_roready_1290 = out_roready_1_1144 & out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12384 = out_f_roready_1290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1290 = out_wivalid_1_1144 & out_wimask_1290; // @[RegisterRouter.scala:87:24] wire out_f_woready_1290 = out_woready_1_1144 & out_womask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12385 = ~out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12386 = ~out_wimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12387 = ~out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12388 = ~out_womask_1290; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1109 = {hi_406, flags_0_go, _out_prepend_T_1109}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12389 = out_prepend_1109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12390 = _out_T_12389; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1110 = _out_T_12390; // @[RegisterRouter.scala:87:24] wire out_rimask_1291 = \|_out_rimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_wimask_1291 = &_out_wimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_romask_1291 = \|_out_romask_T_1291; // @[RegisterRouter.scala:87:24] wire out_womask_1291 = &_out_womask_T_1291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1291 = out_rivalid_1_1145 & out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12392 = out_f_rivalid_1291; // @[RegisterRouter.scala:87:24] wire out_f_roready_1291 = out_roready_1_1145 & out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12393 = out_f_roready_1291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1291 = out_wivalid_1_1145 & out_wimask_1291; // @[RegisterRouter.scala:87:24] wire out_f_woready_1291 = out_woready_1_1145 & out_womask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12394 = ~out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12395 = ~out_wimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12396 = ~out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12397 = ~out_womask_1291; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1110 = {hi_407, flags_0_go, _out_prepend_T_1110}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12398 = out_prepend_1110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12399 = _out_T_12398; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1111 = _out_T_12399; // @[RegisterRouter.scala:87:24] wire out_rimask_1292 = \|_out_rimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_wimask_1292 = &_out_wimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_romask_1292 = \|_out_romask_T_1292; // @[RegisterRouter.scala:87:24] wire out_womask_1292 = &_out_womask_T_1292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1292 = out_rivalid_1_1146 & out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12401 = out_f_rivalid_1292; // @[RegisterRouter.scala:87:24] wire out_f_roready_1292 = out_roready_1_1146 & out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12402 = out_f_roready_1292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1292 = out_wivalid_1_1146 & out_wimask_1292; // @[RegisterRouter.scala:87:24] wire out_f_woready_1292 = out_woready_1_1146 & out_womask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12403 = ~out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12404 = ~out_wimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12405 = ~out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12406 = ~out_womask_1292; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1111 = {hi_408, flags_0_go, _out_prepend_T_1111}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12407 = out_prepend_1111; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12408 = _out_T_12407; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_178 = _out_T_12408; // @[MuxLiteral.scala:49:48] wire out_rimask_1293 = \|_out_rimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_wimask_1293 = &_out_wimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_romask_1293 = \|_out_romask_T_1293; // @[RegisterRouter.scala:87:24] wire out_womask_1293 = &_out_womask_T_1293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1293 = out_rivalid_1_1147 & out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12410 = out_f_rivalid_1293; // @[RegisterRouter.scala:87:24] wire out_f_roready_1293 = out_roready_1_1147 & out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12411 = out_f_roready_1293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1293 = out_wivalid_1_1147 & out_wimask_1293; // @[RegisterRouter.scala:87:24] wire out_f_woready_1293 = out_woready_1_1147 & out_womask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12412 = ~out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12413 = ~out_wimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12414 = ~out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12415 = ~out_womask_1293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12417 = _out_T_12416; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1112 = _out_T_12417; // @[RegisterRouter.scala:87:24] wire out_rimask_1294 = \|_out_rimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_wimask_1294 = &_out_wimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_romask_1294 = \|_out_romask_T_1294; // @[RegisterRouter.scala:87:24] wire out_womask_1294 = &_out_womask_T_1294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1294 = out_rivalid_1_1148 & out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12419 = out_f_rivalid_1294; // @[RegisterRouter.scala:87:24] wire out_f_roready_1294 = out_roready_1_1148 & out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12420 = out_f_roready_1294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1294 = out_wivalid_1_1148 & out_wimask_1294; // @[RegisterRouter.scala:87:24] wire out_f_woready_1294 = out_woready_1_1148 & out_womask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12421 = ~out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12422 = ~out_wimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12423 = ~out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12424 = ~out_womask_1294; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1112 = {hi_282, flags_0_go, _out_prepend_T_1112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12425 = out_prepend_1112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12426 = _out_T_12425; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1113 = _out_T_12426; // @[RegisterRouter.scala:87:24] wire out_rimask_1295 = \|_out_rimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_wimask_1295 = &_out_wimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_romask_1295 = \|_out_romask_T_1295; // @[RegisterRouter.scala:87:24] wire out_womask_1295 = &_out_womask_T_1295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1295 = out_rivalid_1_1149 & out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12428 = out_f_rivalid_1295; // @[RegisterRouter.scala:87:24] wire out_f_roready_1295 = out_roready_1_1149 & out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12429 = out_f_roready_1295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1295 = out_wivalid_1_1149 & out_wimask_1295; // @[RegisterRouter.scala:87:24] wire out_f_woready_1295 = out_woready_1_1149 & out_womask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12430 = ~out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12431 = ~out_wimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12432 = ~out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12433 = ~out_womask_1295; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1113 = {hi_283, flags_0_go, _out_prepend_T_1113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12434 = out_prepend_1113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12435 = _out_T_12434; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1114 = _out_T_12435; // @[RegisterRouter.scala:87:24] wire out_rimask_1296 = \|_out_rimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_wimask_1296 = &_out_wimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_romask_1296 = \|_out_romask_T_1296; // @[RegisterRouter.scala:87:24] wire out_womask_1296 = &_out_womask_T_1296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1296 = out_rivalid_1_1150 & out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12437 = out_f_rivalid_1296; // @[RegisterRouter.scala:87:24] wire out_f_roready_1296 = out_roready_1_1150 & out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12438 = out_f_roready_1296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1296 = out_wivalid_1_1150 & out_wimask_1296; // @[RegisterRouter.scala:87:24] wire out_f_woready_1296 = out_woready_1_1150 & out_womask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12439 = ~out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12440 = ~out_wimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12441 = ~out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12442 = ~out_womask_1296; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1114 = {hi_284, flags_0_go, _out_prepend_T_1114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12443 = out_prepend_1114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12444 = _out_T_12443; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1115 = _out_T_12444; // @[RegisterRouter.scala:87:24] wire out_rimask_1297 = \|_out_rimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_wimask_1297 = &_out_wimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_romask_1297 = \|_out_romask_T_1297; // @[RegisterRouter.scala:87:24] wire out_womask_1297 = &_out_womask_T_1297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1297 = out_rivalid_1_1151 & out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12446 = out_f_rivalid_1297; // @[RegisterRouter.scala:87:24] wire out_f_roready_1297 = out_roready_1_1151 & out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12447 = out_f_roready_1297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1297 = out_wivalid_1_1151 & out_wimask_1297; // @[RegisterRouter.scala:87:24] wire out_f_woready_1297 = out_woready_1_1151 & out_womask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12448 = ~out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12449 = ~out_wimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12450 = ~out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12451 = ~out_womask_1297; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1115 = {hi_285, flags_0_go, _out_prepend_T_1115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12452 = out_prepend_1115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12453 = _out_T_12452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1116 = _out_T_12453; // @[RegisterRouter.scala:87:24] wire out_rimask_1298 = \|_out_rimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_wimask_1298 = &_out_wimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_romask_1298 = \|_out_romask_T_1298; // @[RegisterRouter.scala:87:24] wire out_womask_1298 = &_out_womask_T_1298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1298 = out_rivalid_1_1152 & out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12455 = out_f_rivalid_1298; // @[RegisterRouter.scala:87:24] wire out_f_roready_1298 = out_roready_1_1152 & out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12456 = out_f_roready_1298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1298 = out_wivalid_1_1152 & out_wimask_1298; // @[RegisterRouter.scala:87:24] wire out_f_woready_1298 = out_woready_1_1152 & out_womask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12457 = ~out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12458 = ~out_wimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12459 = ~out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12460 = ~out_womask_1298; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1116 = {hi_286, flags_0_go, _out_prepend_T_1116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12461 = out_prepend_1116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12462 = _out_T_12461; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1117 = _out_T_12462; // @[RegisterRouter.scala:87:24] wire out_rimask_1299 = \|_out_rimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_wimask_1299 = &_out_wimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_romask_1299 = \|_out_romask_T_1299; // @[RegisterRouter.scala:87:24] wire out_womask_1299 = &_out_womask_T_1299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1299 = out_rivalid_1_1153 & out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12464 = out_f_rivalid_1299; // @[RegisterRouter.scala:87:24] wire out_f_roready_1299 = out_roready_1_1153 & out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12465 = out_f_roready_1299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1299 = out_wivalid_1_1153 & out_wimask_1299; // @[RegisterRouter.scala:87:24] wire out_f_woready_1299 = out_woready_1_1153 & out_womask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12466 = ~out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12467 = ~out_wimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12468 = ~out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12469 = ~out_womask_1299; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1117 = {hi_287, flags_0_go, _out_prepend_T_1117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12470 = out_prepend_1117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12471 = _out_T_12470; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1118 = _out_T_12471; // @[RegisterRouter.scala:87:24] wire out_rimask_1300 = \|_out_rimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_wimask_1300 = &_out_wimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_romask_1300 = \|_out_romask_T_1300; // @[RegisterRouter.scala:87:24] wire out_womask_1300 = &_out_womask_T_1300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1300 = out_rivalid_1_1154 & out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12473 = out_f_rivalid_1300; // @[RegisterRouter.scala:87:24] wire out_f_roready_1300 = out_roready_1_1154 & out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12474 = out_f_roready_1300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1300 = out_wivalid_1_1154 & out_wimask_1300; // @[RegisterRouter.scala:87:24] wire out_f_woready_1300 = out_woready_1_1154 & out_womask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12475 = ~out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12476 = ~out_wimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12477 = ~out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12478 = ~out_womask_1300; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1118 = {hi_288, flags_0_go, _out_prepend_T_1118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12479 = out_prepend_1118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12480 = _out_T_12479; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_163 = _out_T_12480; // @[MuxLiteral.scala:49:48] wire out_rimask_1301 = \|_out_rimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_wimask_1301 = &_out_wimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_romask_1301 = \|_out_romask_T_1301; // @[RegisterRouter.scala:87:24] wire out_womask_1301 = &_out_womask_T_1301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1301 = out_rivalid_1_1155 & out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12482 = out_f_rivalid_1301; // @[RegisterRouter.scala:87:24] wire out_f_roready_1301 = out_roready_1_1155 & out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12483 = out_f_roready_1301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1301 = out_wivalid_1_1155 & out_wimask_1301; // @[RegisterRouter.scala:87:24] wire out_f_woready_1301 = out_woready_1_1155 & out_womask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12484 = ~out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12485 = ~out_wimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12486 = ~out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12487 = ~out_womask_1301; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12489 = _out_T_12488; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1119 = _out_T_12489; // @[RegisterRouter.scala:87:24] wire out_rimask_1302 = \|_out_rimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_wimask_1302 = &_out_wimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_romask_1302 = \|_out_romask_T_1302; // @[RegisterRouter.scala:87:24] wire out_womask_1302 = &_out_womask_T_1302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1302 = out_rivalid_1_1156 & out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12491 = out_f_rivalid_1302; // @[RegisterRouter.scala:87:24] wire out_f_roready_1302 = out_roready_1_1156 & out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12492 = out_f_roready_1302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1302 = out_wivalid_1_1156 & out_wimask_1302; // @[RegisterRouter.scala:87:24] wire out_f_woready_1302 = out_woready_1_1156 & out_womask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12493 = ~out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12494 = ~out_wimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12495 = ~out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12496 = ~out_womask_1302; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1119 = {hi_578, flags_0_go, _out_prepend_T_1119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12497 = out_prepend_1119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12498 = _out_T_12497; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1120 = _out_T_12498; // @[RegisterRouter.scala:87:24] wire out_rimask_1303 = \|_out_rimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_wimask_1303 = &_out_wimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_romask_1303 = \|_out_romask_T_1303; // @[RegisterRouter.scala:87:24] wire out_womask_1303 = &_out_womask_T_1303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1303 = out_rivalid_1_1157 & out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12500 = out_f_rivalid_1303; // @[RegisterRouter.scala:87:24] wire out_f_roready_1303 = out_roready_1_1157 & out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12501 = out_f_roready_1303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1303 = out_wivalid_1_1157 & out_wimask_1303; // @[RegisterRouter.scala:87:24] wire out_f_woready_1303 = out_woready_1_1157 & out_womask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12502 = ~out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12503 = ~out_wimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12504 = ~out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12505 = ~out_womask_1303; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1120 = {hi_579, flags_0_go, _out_prepend_T_1120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12506 = out_prepend_1120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12507 = _out_T_12506; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1121 = _out_T_12507; // @[RegisterRouter.scala:87:24] wire out_rimask_1304 = \|_out_rimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_wimask_1304 = &_out_wimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_romask_1304 = \|_out_romask_T_1304; // @[RegisterRouter.scala:87:24] wire out_womask_1304 = &_out_womask_T_1304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1304 = out_rivalid_1_1158 & out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12509 = out_f_rivalid_1304; // @[RegisterRouter.scala:87:24] wire out_f_roready_1304 = out_roready_1_1158 & out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12510 = out_f_roready_1304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1304 = out_wivalid_1_1158 & out_wimask_1304; // @[RegisterRouter.scala:87:24] wire out_f_woready_1304 = out_woready_1_1158 & out_womask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12511 = ~out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12512 = ~out_wimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12513 = ~out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12514 = ~out_womask_1304; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1121 = {hi_580, flags_0_go, _out_prepend_T_1121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12515 = out_prepend_1121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12516 = _out_T_12515; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1122 = _out_T_12516; // @[RegisterRouter.scala:87:24] wire out_rimask_1305 = \|_out_rimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_wimask_1305 = &_out_wimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_romask_1305 = \|_out_romask_T_1305; // @[RegisterRouter.scala:87:24] wire out_womask_1305 = &_out_womask_T_1305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1305 = out_rivalid_1_1159 & out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12518 = out_f_rivalid_1305; // @[RegisterRouter.scala:87:24] wire out_f_roready_1305 = out_roready_1_1159 & out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12519 = out_f_roready_1305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1305 = out_wivalid_1_1159 & out_wimask_1305; // @[RegisterRouter.scala:87:24] wire out_f_woready_1305 = out_woready_1_1159 & out_womask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12520 = ~out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12521 = ~out_wimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12522 = ~out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12523 = ~out_womask_1305; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1122 = {hi_581, flags_0_go, _out_prepend_T_1122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12524 = out_prepend_1122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12525 = _out_T_12524; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1123 = _out_T_12525; // @[RegisterRouter.scala:87:24] wire out_rimask_1306 = \|_out_rimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_wimask_1306 = &_out_wimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_romask_1306 = \|_out_romask_T_1306; // @[RegisterRouter.scala:87:24] wire out_womask_1306 = &_out_womask_T_1306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1306 = out_rivalid_1_1160 & out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12527 = out_f_rivalid_1306; // @[RegisterRouter.scala:87:24] wire out_f_roready_1306 = out_roready_1_1160 & out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12528 = out_f_roready_1306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1306 = out_wivalid_1_1160 & out_wimask_1306; // @[RegisterRouter.scala:87:24] wire out_f_woready_1306 = out_woready_1_1160 & out_womask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12529 = ~out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12530 = ~out_wimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12531 = ~out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12532 = ~out_womask_1306; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1123 = {hi_582, flags_0_go, _out_prepend_T_1123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12533 = out_prepend_1123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12534 = _out_T_12533; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1124 = _out_T_12534; // @[RegisterRouter.scala:87:24] wire out_rimask_1307 = \|_out_rimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_wimask_1307 = &_out_wimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_romask_1307 = \|_out_romask_T_1307; // @[RegisterRouter.scala:87:24] wire out_womask_1307 = &_out_womask_T_1307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1307 = out_rivalid_1_1161 & out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12536 = out_f_rivalid_1307; // @[RegisterRouter.scala:87:24] wire out_f_roready_1307 = out_roready_1_1161 & out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12537 = out_f_roready_1307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1307 = out_wivalid_1_1161 & out_wimask_1307; // @[RegisterRouter.scala:87:24] wire out_f_woready_1307 = out_woready_1_1161 & out_womask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12538 = ~out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12539 = ~out_wimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12540 = ~out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12541 = ~out_womask_1307; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1124 = {hi_583, flags_0_go, _out_prepend_T_1124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12542 = out_prepend_1124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12543 = _out_T_12542; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1125 = _out_T_12543; // @[RegisterRouter.scala:87:24] wire out_rimask_1308 = \|_out_rimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_wimask_1308 = &_out_wimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_romask_1308 = \|_out_romask_T_1308; // @[RegisterRouter.scala:87:24] wire out_womask_1308 = &_out_womask_T_1308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1308 = out_rivalid_1_1162 & out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12545 = out_f_rivalid_1308; // @[RegisterRouter.scala:87:24] wire out_f_roready_1308 = out_roready_1_1162 & out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12546 = out_f_roready_1308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1308 = out_wivalid_1_1162 & out_wimask_1308; // @[RegisterRouter.scala:87:24] wire out_f_woready_1308 = out_woready_1_1162 & out_womask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12547 = ~out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12548 = ~out_wimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12549 = ~out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12550 = ~out_womask_1308; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1125 = {hi_584, flags_0_go, _out_prepend_T_1125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12551 = out_prepend_1125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12552 = _out_T_12551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_200 = _out_T_12552; // @[MuxLiteral.scala:49:48] wire out_rimask_1309 = \|_out_rimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_wimask_1309 = &_out_wimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_romask_1309 = \|_out_romask_T_1309; // @[RegisterRouter.scala:87:24] wire out_womask_1309 = &_out_womask_T_1309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1309 = out_rivalid_1_1163 & out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12554 = out_f_rivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_roready_1309 = out_roready_1_1163 & out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12555 = out_f_roready_1309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1309 = out_wivalid_1_1163 & out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12556 = out_f_wivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_woready_1309 = out_woready_1_1163 & out_womask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12557 = out_f_woready_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12558 = ~out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12559 = ~out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12560 = ~out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12561 = ~out_womask_1309; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12563 = _out_T_12562; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1126 = _out_T_12563; // @[RegisterRouter.scala:87:24] wire out_rimask_1310 = \|_out_rimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_wimask_1310 = &_out_wimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_romask_1310 = \|_out_romask_T_1310; // @[RegisterRouter.scala:87:24] wire out_womask_1310 = &_out_womask_T_1310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1310 = out_rivalid_1_1164 & out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12565 = out_f_rivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_roready_1310 = out_roready_1_1164 & out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12566 = out_f_roready_1310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1310 = out_wivalid_1_1164 & out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12567 = out_f_wivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_woready_1310 = out_woready_1_1164 & out_womask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12568 = out_f_woready_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12569 = ~out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12570 = ~out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12571 = ~out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12572 = ~out_womask_1310; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1126 = {programBufferMem_57, _out_prepend_T_1126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12573 = out_prepend_1126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12574 = _out_T_12573; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1127 = _out_T_12574; // @[RegisterRouter.scala:87:24] wire out_rimask_1311 = \|_out_rimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_wimask_1311 = &_out_wimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_romask_1311 = \|_out_romask_T_1311; // @[RegisterRouter.scala:87:24] wire out_womask_1311 = &_out_womask_T_1311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1311 = out_rivalid_1_1165 & out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12576 = out_f_rivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_roready_1311 = out_roready_1_1165 & out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12577 = out_f_roready_1311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1311 = out_wivalid_1_1165 & out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12578 = out_f_wivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_woready_1311 = out_woready_1_1165 & out_womask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12579 = out_f_woready_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12580 = ~out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12581 = ~out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12582 = ~out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12583 = ~out_womask_1311; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1127 = {programBufferMem_58, _out_prepend_T_1127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12584 = out_prepend_1127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12585 = _out_T_12584; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1128 = _out_T_12585; // @[RegisterRouter.scala:87:24] wire out_rimask_1312 = \|_out_rimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_wimask_1312 = &_out_wimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_romask_1312 = \|_out_romask_T_1312; // @[RegisterRouter.scala:87:24] wire out_womask_1312 = &_out_womask_T_1312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1312 = out_rivalid_1_1166 & out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12587 = out_f_rivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_roready_1312 = out_roready_1_1166 & out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12588 = out_f_roready_1312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1312 = out_wivalid_1_1166 & out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12589 = out_f_wivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_woready_1312 = out_woready_1_1166 & out_womask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12590 = out_f_woready_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12591 = ~out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12592 = ~out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12593 = ~out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12594 = ~out_womask_1312; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1128 = {programBufferMem_59, _out_prepend_T_1128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12595 = out_prepend_1128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12596 = _out_T_12595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1129 = _out_T_12596; // @[RegisterRouter.scala:87:24] wire out_rimask_1313 = \|_out_rimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_wimask_1313 = &_out_wimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_romask_1313 = \|_out_romask_T_1313; // @[RegisterRouter.scala:87:24] wire out_womask_1313 = &_out_womask_T_1313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1313 = out_rivalid_1_1167 & out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12598 = out_f_rivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_roready_1313 = out_roready_1_1167 & out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12599 = out_f_roready_1313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1313 = out_wivalid_1_1167 & out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12600 = out_f_wivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_woready_1313 = out_woready_1_1167 & out_womask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12601 = out_f_woready_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12602 = ~out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12603 = ~out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12604 = ~out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12605 = ~out_womask_1313; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1129 = {programBufferMem_60, _out_prepend_T_1129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12606 = out_prepend_1129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12607 = _out_T_12606; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1130 = _out_T_12607; // @[RegisterRouter.scala:87:24] wire out_rimask_1314 = \|_out_rimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_wimask_1314 = &_out_wimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_romask_1314 = \|_out_romask_T_1314; // @[RegisterRouter.scala:87:24] wire out_womask_1314 = &_out_womask_T_1314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1314 = out_rivalid_1_1168 & out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12609 = out_f_rivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_roready_1314 = out_roready_1_1168 & out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12610 = out_f_roready_1314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1314 = out_wivalid_1_1168 & out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12611 = out_f_wivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_woready_1314 = out_woready_1_1168 & out_womask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12612 = out_f_woready_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12613 = ~out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12614 = ~out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12615 = ~out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12616 = ~out_womask_1314; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1130 = {programBufferMem_61, _out_prepend_T_1130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12617 = out_prepend_1130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12618 = _out_T_12617; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1131 = _out_T_12618; // @[RegisterRouter.scala:87:24] wire out_rimask_1315 = \|_out_rimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_wimask_1315 = &_out_wimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_romask_1315 = \|_out_romask_T_1315; // @[RegisterRouter.scala:87:24] wire out_womask_1315 = &_out_womask_T_1315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1315 = out_rivalid_1_1169 & out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12620 = out_f_rivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_roready_1315 = out_roready_1_1169 & out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12621 = out_f_roready_1315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1315 = out_wivalid_1_1169 & out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12622 = out_f_wivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_woready_1315 = out_woready_1_1169 & out_womask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12623 = out_f_woready_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12624 = ~out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12625 = ~out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12626 = ~out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12627 = ~out_womask_1315; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1131 = {programBufferMem_62, _out_prepend_T_1131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12628 = out_prepend_1131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12629 = _out_T_12628; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1132 = _out_T_12629; // @[RegisterRouter.scala:87:24] wire out_rimask_1316 = \|_out_rimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_wimask_1316 = &_out_wimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_romask_1316 = \|_out_romask_T_1316; // @[RegisterRouter.scala:87:24] wire out_womask_1316 = &_out_womask_T_1316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1316 = out_rivalid_1_1170 & out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12631 = out_f_rivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_roready_1316 = out_roready_1_1170 & out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12632 = out_f_roready_1316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1316 = out_wivalid_1_1170 & out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12633 = out_f_wivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_woready_1316 = out_woready_1_1170 & out_womask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12634 = out_f_woready_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12635 = ~out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12636 = ~out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12637 = ~out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12638 = ~out_womask_1316; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1132 = {programBufferMem_63, _out_prepend_T_1132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12639 = out_prepend_1132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12640 = _out_T_12639; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_111 = _out_T_12640; // @[MuxLiteral.scala:49:48] wire out_rimask_1317 = \|_out_rimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_wimask_1317 = &_out_wimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_romask_1317 = \|_out_romask_T_1317; // @[RegisterRouter.scala:87:24] wire out_womask_1317 = &_out_womask_T_1317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1317 = out_rivalid_1_1171 & out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12642 = out_f_rivalid_1317; // @[RegisterRouter.scala:87:24] wire out_f_roready_1317 = out_roready_1_1171 & out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12643 = out_f_roready_1317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1317 = out_wivalid_1_1171 & out_wimask_1317; // @[RegisterRouter.scala:87:24] wire out_f_woready_1317 = out_woready_1_1171 & out_womask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12644 = ~out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12645 = ~out_wimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12646 = ~out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12647 = ~out_womask_1317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12649 = _out_T_12648; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1133 = _out_T_12649; // @[RegisterRouter.scala:87:24] wire out_rimask_1318 = \|_out_rimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_wimask_1318 = &_out_wimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_romask_1318 = \|_out_romask_T_1318; // @[RegisterRouter.scala:87:24] wire out_womask_1318 = &_out_womask_T_1318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1318 = out_rivalid_1_1172 & out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12651 = out_f_rivalid_1318; // @[RegisterRouter.scala:87:24] wire out_f_roready_1318 = out_roready_1_1172 & out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12652 = out_f_roready_1318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1318 = out_wivalid_1_1172 & out_wimask_1318; // @[RegisterRouter.scala:87:24] wire out_f_woready_1318 = out_woready_1_1172 & out_womask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12653 = ~out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12654 = ~out_wimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12655 = ~out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12656 = ~out_womask_1318; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1133 = {hi_698, flags_0_go, _out_prepend_T_1133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12657 = out_prepend_1133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12658 = _out_T_12657; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1134 = _out_T_12658; // @[RegisterRouter.scala:87:24] wire out_rimask_1319 = \|_out_rimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_wimask_1319 = &_out_wimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_romask_1319 = \|_out_romask_T_1319; // @[RegisterRouter.scala:87:24] wire out_womask_1319 = &_out_womask_T_1319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1319 = out_rivalid_1_1173 & out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12660 = out_f_rivalid_1319; // @[RegisterRouter.scala:87:24] wire out_f_roready_1319 = out_roready_1_1173 & out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12661 = out_f_roready_1319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1319 = out_wivalid_1_1173 & out_wimask_1319; // @[RegisterRouter.scala:87:24] wire out_f_woready_1319 = out_woready_1_1173 & out_womask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12662 = ~out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12663 = ~out_wimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12664 = ~out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12665 = ~out_womask_1319; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1134 = {hi_699, flags_0_go, _out_prepend_T_1134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12666 = out_prepend_1134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12667 = _out_T_12666; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1135 = _out_T_12667; // @[RegisterRouter.scala:87:24] wire out_rimask_1320 = \|_out_rimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_wimask_1320 = &_out_wimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_romask_1320 = \|_out_romask_T_1320; // @[RegisterRouter.scala:87:24] wire out_womask_1320 = &_out_womask_T_1320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1320 = out_rivalid_1_1174 & out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12669 = out_f_rivalid_1320; // @[RegisterRouter.scala:87:24] wire out_f_roready_1320 = out_roready_1_1174 & out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12670 = out_f_roready_1320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1320 = out_wivalid_1_1174 & out_wimask_1320; // @[RegisterRouter.scala:87:24] wire out_f_woready_1320 = out_woready_1_1174 & out_womask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12671 = ~out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12672 = ~out_wimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12673 = ~out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12674 = ~out_womask_1320; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1135 = {hi_700, flags_0_go, _out_prepend_T_1135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12675 = out_prepend_1135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12676 = _out_T_12675; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1136 = _out_T_12676; // @[RegisterRouter.scala:87:24] wire out_rimask_1321 = \|_out_rimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_wimask_1321 = &_out_wimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_romask_1321 = \|_out_romask_T_1321; // @[RegisterRouter.scala:87:24] wire out_womask_1321 = &_out_womask_T_1321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1321 = out_rivalid_1_1175 & out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12678 = out_f_rivalid_1321; // @[RegisterRouter.scala:87:24] wire out_f_roready_1321 = out_roready_1_1175 & out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12679 = out_f_roready_1321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1321 = out_wivalid_1_1175 & out_wimask_1321; // @[RegisterRouter.scala:87:24] wire out_f_woready_1321 = out_woready_1_1175 & out_womask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12680 = ~out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12681 = ~out_wimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12682 = ~out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12683 = ~out_womask_1321; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1136 = {hi_701, flags_0_go, _out_prepend_T_1136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12684 = out_prepend_1136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12685 = _out_T_12684; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1137 = _out_T_12685; // @[RegisterRouter.scala:87:24] wire out_rimask_1322 = \|_out_rimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_wimask_1322 = &_out_wimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_romask_1322 = \|_out_romask_T_1322; // @[RegisterRouter.scala:87:24] wire out_womask_1322 = &_out_womask_T_1322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1322 = out_rivalid_1_1176 & out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12687 = out_f_rivalid_1322; // @[RegisterRouter.scala:87:24] wire out_f_roready_1322 = out_roready_1_1176 & out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12688 = out_f_roready_1322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1322 = out_wivalid_1_1176 & out_wimask_1322; // @[RegisterRouter.scala:87:24] wire out_f_woready_1322 = out_woready_1_1176 & out_womask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12689 = ~out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12690 = ~out_wimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12691 = ~out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12692 = ~out_womask_1322; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1137 = {hi_702, flags_0_go, _out_prepend_T_1137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12693 = out_prepend_1137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12694 = _out_T_12693; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1138 = _out_T_12694; // @[RegisterRouter.scala:87:24] wire out_rimask_1323 = \|_out_rimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_wimask_1323 = &_out_wimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_romask_1323 = \|_out_romask_T_1323; // @[RegisterRouter.scala:87:24] wire out_womask_1323 = &_out_womask_T_1323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1323 = out_rivalid_1_1177 & out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12696 = out_f_rivalid_1323; // @[RegisterRouter.scala:87:24] wire out_f_roready_1323 = out_roready_1_1177 & out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12697 = out_f_roready_1323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1323 = out_wivalid_1_1177 & out_wimask_1323; // @[RegisterRouter.scala:87:24] wire out_f_woready_1323 = out_woready_1_1177 & out_womask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12698 = ~out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12699 = ~out_wimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12700 = ~out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12701 = ~out_womask_1323; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1138 = {hi_703, flags_0_go, _out_prepend_T_1138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12702 = out_prepend_1138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12703 = _out_T_12702; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1139 = _out_T_12703; // @[RegisterRouter.scala:87:24] wire out_rimask_1324 = \|_out_rimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_wimask_1324 = &_out_wimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_romask_1324 = \|_out_romask_T_1324; // @[RegisterRouter.scala:87:24] wire out_womask_1324 = &_out_womask_T_1324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1324 = out_rivalid_1_1178 & out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12705 = out_f_rivalid_1324; // @[RegisterRouter.scala:87:24] wire out_f_roready_1324 = out_roready_1_1178 & out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12706 = out_f_roready_1324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1324 = out_wivalid_1_1178 & out_wimask_1324; // @[RegisterRouter.scala:87:24] wire out_f_woready_1324 = out_woready_1_1178 & out_womask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12707 = ~out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12708 = ~out_wimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12709 = ~out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12710 = ~out_womask_1324; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1139 = {hi_704, flags_0_go, _out_prepend_T_1139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12711 = out_prepend_1139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12712 = _out_T_12711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_215 = _out_T_12712; // @[MuxLiteral.scala:49:48] wire out_rimask_1325 = \|_out_rimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_wimask_1325 = &_out_wimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_romask_1325 = \|_out_romask_T_1325; // @[RegisterRouter.scala:87:24] wire out_womask_1325 = &_out_womask_T_1325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1325 = out_rivalid_1_1179 & out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12714 = out_f_rivalid_1325; // @[RegisterRouter.scala:87:24] wire out_f_roready_1325 = out_roready_1_1179 & out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12715 = out_f_roready_1325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1325 = out_wivalid_1_1179 & out_wimask_1325; // @[RegisterRouter.scala:87:24] wire out_f_woready_1325 = out_woready_1_1179 & out_womask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12716 = ~out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12717 = ~out_wimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12718 = ~out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12719 = ~out_womask_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12721 = _out_T_12720; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1140 = _out_T_12721; // @[RegisterRouter.scala:87:24] wire out_rimask_1326 = \|_out_rimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_wimask_1326 = &_out_wimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_romask_1326 = \|_out_romask_T_1326; // @[RegisterRouter.scala:87:24] wire out_womask_1326 = &_out_womask_T_1326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1326 = out_rivalid_1_1180 & out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12723 = out_f_rivalid_1326; // @[RegisterRouter.scala:87:24] wire out_f_roready_1326 = out_roready_1_1180 & out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12724 = out_f_roready_1326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1326 = out_wivalid_1_1180 & out_wimask_1326; // @[RegisterRouter.scala:87:24] wire out_f_woready_1326 = out_woready_1_1180 & out_womask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12725 = ~out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12726 = ~out_wimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12727 = ~out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12728 = ~out_womask_1326; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1140 = {hi_754, flags_0_go, _out_prepend_T_1140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12729 = out_prepend_1140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12730 = _out_T_12729; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1141 = _out_T_12730; // @[RegisterRouter.scala:87:24] wire out_rimask_1327 = \|_out_rimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_wimask_1327 = &_out_wimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_romask_1327 = \|_out_romask_T_1327; // @[RegisterRouter.scala:87:24] wire out_womask_1327 = &_out_womask_T_1327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1327 = out_rivalid_1_1181 & out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12732 = out_f_rivalid_1327; // @[RegisterRouter.scala:87:24] wire out_f_roready_1327 = out_roready_1_1181 & out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12733 = out_f_roready_1327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1327 = out_wivalid_1_1181 & out_wimask_1327; // @[RegisterRouter.scala:87:24] wire out_f_woready_1327 = out_woready_1_1181 & out_womask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12734 = ~out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12735 = ~out_wimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12736 = ~out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12737 = ~out_womask_1327; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1141 = {hi_755, flags_0_go, _out_prepend_T_1141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12738 = out_prepend_1141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12739 = _out_T_12738; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1142 = _out_T_12739; // @[RegisterRouter.scala:87:24] wire out_rimask_1328 = \|_out_rimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_wimask_1328 = &_out_wimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_romask_1328 = \|_out_romask_T_1328; // @[RegisterRouter.scala:87:24] wire out_womask_1328 = &_out_womask_T_1328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1328 = out_rivalid_1_1182 & out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12741 = out_f_rivalid_1328; // @[RegisterRouter.scala:87:24] wire out_f_roready_1328 = out_roready_1_1182 & out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12742 = out_f_roready_1328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1328 = out_wivalid_1_1182 & out_wimask_1328; // @[RegisterRouter.scala:87:24] wire out_f_woready_1328 = out_woready_1_1182 & out_womask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12743 = ~out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12744 = ~out_wimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12745 = ~out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12746 = ~out_womask_1328; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1142 = {hi_756, flags_0_go, _out_prepend_T_1142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12747 = out_prepend_1142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12748 = _out_T_12747; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1143 = _out_T_12748; // @[RegisterRouter.scala:87:24] wire out_rimask_1329 = \|_out_rimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_wimask_1329 = &_out_wimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_romask_1329 = \|_out_romask_T_1329; // @[RegisterRouter.scala:87:24] wire out_womask_1329 = &_out_womask_T_1329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1329 = out_rivalid_1_1183 & out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12750 = out_f_rivalid_1329; // @[RegisterRouter.scala:87:24] wire out_f_roready_1329 = out_roready_1_1183 & out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12751 = out_f_roready_1329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1329 = out_wivalid_1_1183 & out_wimask_1329; // @[RegisterRouter.scala:87:24] wire out_f_woready_1329 = out_woready_1_1183 & out_womask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12752 = ~out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12753 = ~out_wimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12754 = ~out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12755 = ~out_womask_1329; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1143 = {hi_757, flags_0_go, _out_prepend_T_1143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12756 = out_prepend_1143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12757 = _out_T_12756; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1144 = _out_T_12757; // @[RegisterRouter.scala:87:24] wire out_rimask_1330 = \|_out_rimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_wimask_1330 = &_out_wimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_romask_1330 = \|_out_romask_T_1330; // @[RegisterRouter.scala:87:24] wire out_womask_1330 = &_out_womask_T_1330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1330 = out_rivalid_1_1184 & out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12759 = out_f_rivalid_1330; // @[RegisterRouter.scala:87:24] wire out_f_roready_1330 = out_roready_1_1184 & out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12760 = out_f_roready_1330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1330 = out_wivalid_1_1184 & out_wimask_1330; // @[RegisterRouter.scala:87:24] wire out_f_woready_1330 = out_woready_1_1184 & out_womask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12761 = ~out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12762 = ~out_wimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12763 = ~out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12764 = ~out_womask_1330; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1144 = {hi_758, flags_0_go, _out_prepend_T_1144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12765 = out_prepend_1144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12766 = _out_T_12765; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1145 = _out_T_12766; // @[RegisterRouter.scala:87:24] wire out_rimask_1331 = \|_out_rimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_wimask_1331 = &_out_wimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_romask_1331 = \|_out_romask_T_1331; // @[RegisterRouter.scala:87:24] wire out_womask_1331 = &_out_womask_T_1331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1331 = out_rivalid_1_1185 & out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12768 = out_f_rivalid_1331; // @[RegisterRouter.scala:87:24] wire out_f_roready_1331 = out_roready_1_1185 & out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12769 = out_f_roready_1331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1331 = out_wivalid_1_1185 & out_wimask_1331; // @[RegisterRouter.scala:87:24] wire out_f_woready_1331 = out_woready_1_1185 & out_womask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12770 = ~out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12771 = ~out_wimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12772 = ~out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12773 = ~out_womask_1331; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1145 = {hi_759, flags_0_go, _out_prepend_T_1145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12774 = out_prepend_1145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12775 = _out_T_12774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1146 = _out_T_12775; // @[RegisterRouter.scala:87:24] wire out_rimask_1332 = \|_out_rimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_wimask_1332 = &_out_wimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_romask_1332 = \|_out_romask_T_1332; // @[RegisterRouter.scala:87:24] wire out_womask_1332 = &_out_womask_T_1332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1332 = out_rivalid_1_1186 & out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12777 = out_f_rivalid_1332; // @[RegisterRouter.scala:87:24] wire out_f_roready_1332 = out_roready_1_1186 & out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12778 = out_f_roready_1332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1332 = out_wivalid_1_1186 & out_wimask_1332; // @[RegisterRouter.scala:87:24] wire out_f_woready_1332 = out_woready_1_1186 & out_womask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12779 = ~out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12780 = ~out_wimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12781 = ~out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12782 = ~out_womask_1332; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1146 = {hi_760, flags_0_go, _out_prepend_T_1146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12783 = out_prepend_1146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12784 = _out_T_12783; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_222 = _out_T_12784; // @[MuxLiteral.scala:49:48] wire out_rimask_1333 = \|_out_rimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_wimask_1333 = &_out_wimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_romask_1333 = \|_out_romask_T_1333; // @[RegisterRouter.scala:87:24] wire out_womask_1333 = &_out_womask_T_1333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1333 = out_rivalid_1_1187 & out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12786 = out_f_rivalid_1333; // @[RegisterRouter.scala:87:24] wire out_f_roready_1333 = out_roready_1_1187 & out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12787 = out_f_roready_1333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1333 = out_wivalid_1_1187 & out_wimask_1333; // @[RegisterRouter.scala:87:24] wire out_f_woready_1333 = out_woready_1_1187 & out_womask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12788 = ~out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12789 = ~out_wimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12790 = ~out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12791 = ~out_womask_1333; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12793 = _out_T_12792; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1147 = _out_T_12793; // @[RegisterRouter.scala:87:24] wire out_rimask_1334 = \|_out_rimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_wimask_1334 = &_out_wimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_romask_1334 = \|_out_romask_T_1334; // @[RegisterRouter.scala:87:24] wire out_womask_1334 = &_out_womask_T_1334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1334 = out_rivalid_1_1188 & out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12795 = out_f_rivalid_1334; // @[RegisterRouter.scala:87:24] wire out_f_roready_1334 = out_roready_1_1188 & out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12796 = out_f_roready_1334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1334 = out_wivalid_1_1188 & out_wimask_1334; // @[RegisterRouter.scala:87:24] wire out_f_woready_1334 = out_woready_1_1188 & out_womask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12797 = ~out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12798 = ~out_wimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12799 = ~out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12800 = ~out_womask_1334; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1147 = {hi_834, flags_0_go, _out_prepend_T_1147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12801 = out_prepend_1147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12802 = _out_T_12801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1148 = _out_T_12802; // @[RegisterRouter.scala:87:24] wire out_rimask_1335 = \|_out_rimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_wimask_1335 = &_out_wimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_romask_1335 = \|_out_romask_T_1335; // @[RegisterRouter.scala:87:24] wire out_womask_1335 = &_out_womask_T_1335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1335 = out_rivalid_1_1189 & out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12804 = out_f_rivalid_1335; // @[RegisterRouter.scala:87:24] wire out_f_roready_1335 = out_roready_1_1189 & out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12805 = out_f_roready_1335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1335 = out_wivalid_1_1189 & out_wimask_1335; // @[RegisterRouter.scala:87:24] wire out_f_woready_1335 = out_woready_1_1189 & out_womask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12806 = ~out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12807 = ~out_wimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12808 = ~out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12809 = ~out_womask_1335; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1148 = {hi_835, flags_0_go, _out_prepend_T_1148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12810 = out_prepend_1148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12811 = _out_T_12810; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1149 = _out_T_12811; // @[RegisterRouter.scala:87:24] wire out_rimask_1336 = \|_out_rimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_wimask_1336 = &_out_wimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_romask_1336 = \|_out_romask_T_1336; // @[RegisterRouter.scala:87:24] wire out_womask_1336 = &_out_womask_T_1336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1336 = out_rivalid_1_1190 & out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12813 = out_f_rivalid_1336; // @[RegisterRouter.scala:87:24] wire out_f_roready_1336 = out_roready_1_1190 & out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12814 = out_f_roready_1336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1336 = out_wivalid_1_1190 & out_wimask_1336; // @[RegisterRouter.scala:87:24] wire out_f_woready_1336 = out_woready_1_1190 & out_womask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12815 = ~out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12816 = ~out_wimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12817 = ~out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12818 = ~out_womask_1336; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1149 = {hi_836, flags_0_go, _out_prepend_T_1149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12819 = out_prepend_1149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12820 = _out_T_12819; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1150 = _out_T_12820; // @[RegisterRouter.scala:87:24] wire out_rimask_1337 = \|_out_rimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_wimask_1337 = &_out_wimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_romask_1337 = \|_out_romask_T_1337; // @[RegisterRouter.scala:87:24] wire out_womask_1337 = &_out_womask_T_1337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1337 = out_rivalid_1_1191 & out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12822 = out_f_rivalid_1337; // @[RegisterRouter.scala:87:24] wire out_f_roready_1337 = out_roready_1_1191 & out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12823 = out_f_roready_1337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1337 = out_wivalid_1_1191 & out_wimask_1337; // @[RegisterRouter.scala:87:24] wire out_f_woready_1337 = out_woready_1_1191 & out_womask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12824 = ~out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12825 = ~out_wimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12826 = ~out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12827 = ~out_womask_1337; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1150 = {hi_837, flags_0_go, _out_prepend_T_1150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12828 = out_prepend_1150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12829 = _out_T_12828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1151 = _out_T_12829; // @[RegisterRouter.scala:87:24] wire out_rimask_1338 = \|_out_rimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_wimask_1338 = &_out_wimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_romask_1338 = \|_out_romask_T_1338; // @[RegisterRouter.scala:87:24] wire out_womask_1338 = &_out_womask_T_1338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1338 = out_rivalid_1_1192 & out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12831 = out_f_rivalid_1338; // @[RegisterRouter.scala:87:24] wire out_f_roready_1338 = out_roready_1_1192 & out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12832 = out_f_roready_1338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1338 = out_wivalid_1_1192 & out_wimask_1338; // @[RegisterRouter.scala:87:24] wire out_f_woready_1338 = out_woready_1_1192 & out_womask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12833 = ~out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12834 = ~out_wimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12835 = ~out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12836 = ~out_womask_1338; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1151 = {hi_838, flags_0_go, _out_prepend_T_1151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12837 = out_prepend_1151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12838 = _out_T_12837; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1152 = _out_T_12838; // @[RegisterRouter.scala:87:24] wire out_rimask_1339 = \|_out_rimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_wimask_1339 = &_out_wimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_romask_1339 = \|_out_romask_T_1339; // @[RegisterRouter.scala:87:24] wire out_womask_1339 = &_out_womask_T_1339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1339 = out_rivalid_1_1193 & out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12840 = out_f_rivalid_1339; // @[RegisterRouter.scala:87:24] wire out_f_roready_1339 = out_roready_1_1193 & out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12841 = out_f_roready_1339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1339 = out_wivalid_1_1193 & out_wimask_1339; // @[RegisterRouter.scala:87:24] wire out_f_woready_1339 = out_woready_1_1193 & out_womask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12842 = ~out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12843 = ~out_wimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12844 = ~out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12845 = ~out_womask_1339; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1152 = {hi_839, flags_0_go, _out_prepend_T_1152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12846 = out_prepend_1152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12847 = _out_T_12846; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1153 = _out_T_12847; // @[RegisterRouter.scala:87:24] wire out_rimask_1340 = \|_out_rimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_wimask_1340 = &_out_wimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_romask_1340 = \|_out_romask_T_1340; // @[RegisterRouter.scala:87:24] wire out_womask_1340 = &_out_womask_T_1340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1340 = out_rivalid_1_1194 & out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12849 = out_f_rivalid_1340; // @[RegisterRouter.scala:87:24] wire out_f_roready_1340 = out_roready_1_1194 & out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12850 = out_f_roready_1340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1340 = out_wivalid_1_1194 & out_wimask_1340; // @[RegisterRouter.scala:87:24] wire out_f_woready_1340 = out_woready_1_1194 & out_womask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12851 = ~out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12852 = ~out_wimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12853 = ~out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12854 = ~out_womask_1340; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1153 = {hi_840, flags_0_go, _out_prepend_T_1153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12855 = out_prepend_1153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12856 = _out_T_12855; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_232 = _out_T_12856; // @[MuxLiteral.scala:49:48] wire out_rimask_1341 = \|_out_rimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_wimask_1341 = &_out_wimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_romask_1341 = \|_out_romask_T_1341; // @[RegisterRouter.scala:87:24] wire out_womask_1341 = &_out_womask_T_1341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1341 = out_rivalid_1_1195 & out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12858 = out_f_rivalid_1341; // @[RegisterRouter.scala:87:24] wire out_f_roready_1341 = out_roready_1_1195 & out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12859 = out_f_roready_1341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1341 = out_wivalid_1_1195 & out_wimask_1341; // @[RegisterRouter.scala:87:24] wire out_f_woready_1341 = out_woready_1_1195 & out_womask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12860 = ~out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12861 = ~out_wimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12862 = ~out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12863 = ~out_womask_1341; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12865 = _out_T_12864; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1154 = _out_T_12865; // @[RegisterRouter.scala:87:24] wire out_rimask_1342 = \|_out_rimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_wimask_1342 = &_out_wimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_romask_1342 = \|_out_romask_T_1342; // @[RegisterRouter.scala:87:24] wire out_womask_1342 = &_out_womask_T_1342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1342 = out_rivalid_1_1196 & out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12867 = out_f_rivalid_1342; // @[RegisterRouter.scala:87:24] wire out_f_roready_1342 = out_roready_1_1196 & out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12868 = out_f_roready_1342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1342 = out_wivalid_1_1196 & out_wimask_1342; // @[RegisterRouter.scala:87:24] wire out_f_woready_1342 = out_woready_1_1196 & out_womask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12869 = ~out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12870 = ~out_wimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12871 = ~out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12872 = ~out_womask_1342; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1154 = {hi_1010, flags_0_go, _out_prepend_T_1154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12873 = out_prepend_1154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12874 = _out_T_12873; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1155 = _out_T_12874; // @[RegisterRouter.scala:87:24] wire out_rimask_1343 = \|_out_rimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_wimask_1343 = &_out_wimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_romask_1343 = \|_out_romask_T_1343; // @[RegisterRouter.scala:87:24] wire out_womask_1343 = &_out_womask_T_1343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1343 = out_rivalid_1_1197 & out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12876 = out_f_rivalid_1343; // @[RegisterRouter.scala:87:24] wire out_f_roready_1343 = out_roready_1_1197 & out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12877 = out_f_roready_1343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1343 = out_wivalid_1_1197 & out_wimask_1343; // @[RegisterRouter.scala:87:24] wire out_f_woready_1343 = out_woready_1_1197 & out_womask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12878 = ~out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12879 = ~out_wimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12880 = ~out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12881 = ~out_womask_1343; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1155 = {hi_1011, flags_0_go, _out_prepend_T_1155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12882 = out_prepend_1155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12883 = _out_T_12882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1156 = _out_T_12883; // @[RegisterRouter.scala:87:24] wire out_rimask_1344 = \|_out_rimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_wimask_1344 = &_out_wimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_romask_1344 = \|_out_romask_T_1344; // @[RegisterRouter.scala:87:24] wire out_womask_1344 = &_out_womask_T_1344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1344 = out_rivalid_1_1198 & out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12885 = out_f_rivalid_1344; // @[RegisterRouter.scala:87:24] wire out_f_roready_1344 = out_roready_1_1198 & out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12886 = out_f_roready_1344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1344 = out_wivalid_1_1198 & out_wimask_1344; // @[RegisterRouter.scala:87:24] wire out_f_woready_1344 = out_woready_1_1198 & out_womask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12887 = ~out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12888 = ~out_wimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12889 = ~out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12890 = ~out_womask_1344; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1156 = {hi_1012, flags_0_go, _out_prepend_T_1156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12891 = out_prepend_1156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12892 = _out_T_12891; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1157 = _out_T_12892; // @[RegisterRouter.scala:87:24] wire out_rimask_1345 = \|_out_rimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_wimask_1345 = &_out_wimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_romask_1345 = \|_out_romask_T_1345; // @[RegisterRouter.scala:87:24] wire out_womask_1345 = &_out_womask_T_1345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1345 = out_rivalid_1_1199 & out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12894 = out_f_rivalid_1345; // @[RegisterRouter.scala:87:24] wire out_f_roready_1345 = out_roready_1_1199 & out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12895 = out_f_roready_1345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1345 = out_wivalid_1_1199 & out_wimask_1345; // @[RegisterRouter.scala:87:24] wire out_f_woready_1345 = out_woready_1_1199 & out_womask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12896 = ~out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12897 = ~out_wimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12898 = ~out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12899 = ~out_womask_1345; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1157 = {hi_1013, flags_0_go, _out_prepend_T_1157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12900 = out_prepend_1157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12901 = _out_T_12900; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1158 = _out_T_12901; // @[RegisterRouter.scala:87:24] wire out_rimask_1346 = \|_out_rimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_wimask_1346 = &_out_wimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_romask_1346 = \|_out_romask_T_1346; // @[RegisterRouter.scala:87:24] wire out_womask_1346 = &_out_womask_T_1346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1346 = out_rivalid_1_1200 & out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12903 = out_f_rivalid_1346; // @[RegisterRouter.scala:87:24] wire out_f_roready_1346 = out_roready_1_1200 & out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12904 = out_f_roready_1346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1346 = out_wivalid_1_1200 & out_wimask_1346; // @[RegisterRouter.scala:87:24] wire out_f_woready_1346 = out_woready_1_1200 & out_womask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12905 = ~out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12906 = ~out_wimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12907 = ~out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12908 = ~out_womask_1346; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1158 = {hi_1014, flags_0_go, _out_prepend_T_1158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12909 = out_prepend_1158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12910 = _out_T_12909; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1159 = _out_T_12910; // @[RegisterRouter.scala:87:24] wire out_rimask_1347 = \|_out_rimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_wimask_1347 = &_out_wimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_romask_1347 = \|_out_romask_T_1347; // @[RegisterRouter.scala:87:24] wire out_womask_1347 = &_out_womask_T_1347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1347 = out_rivalid_1_1201 & out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12912 = out_f_rivalid_1347; // @[RegisterRouter.scala:87:24] wire out_f_roready_1347 = out_roready_1_1201 & out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12913 = out_f_roready_1347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1347 = out_wivalid_1_1201 & out_wimask_1347; // @[RegisterRouter.scala:87:24] wire out_f_woready_1347 = out_woready_1_1201 & out_womask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12914 = ~out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12915 = ~out_wimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12916 = ~out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12917 = ~out_womask_1347; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1159 = {hi_1015, flags_0_go, _out_prepend_T_1159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12918 = out_prepend_1159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12919 = _out_T_12918; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1160 = _out_T_12919; // @[RegisterRouter.scala:87:24] wire out_rimask_1348 = \|_out_rimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_wimask_1348 = &_out_wimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_romask_1348 = \|_out_romask_T_1348; // @[RegisterRouter.scala:87:24] wire out_womask_1348 = &_out_womask_T_1348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1348 = out_rivalid_1_1202 & out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12921 = out_f_rivalid_1348; // @[RegisterRouter.scala:87:24] wire out_f_roready_1348 = out_roready_1_1202 & out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12922 = out_f_roready_1348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1348 = out_wivalid_1_1202 & out_wimask_1348; // @[RegisterRouter.scala:87:24] wire out_f_woready_1348 = out_woready_1_1202 & out_womask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12923 = ~out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12924 = ~out_wimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12925 = ~out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12926 = ~out_womask_1348; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1160 = {hi_1016, flags_0_go, _out_prepend_T_1160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12927 = out_prepend_1160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12928 = _out_T_12927; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_254 = _out_T_12928; // @[MuxLiteral.scala:49:48] wire out_rimask_1349 = \|_out_rimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_wimask_1349 = &_out_wimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_romask_1349 = \|_out_romask_T_1349; // @[RegisterRouter.scala:87:24] wire out_womask_1349 = &_out_womask_T_1349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1349 = out_rivalid_1_1203 & out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12930 = out_f_rivalid_1349; // @[RegisterRouter.scala:87:24] wire out_f_roready_1349 = out_roready_1_1203 & out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12931 = out_f_roready_1349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1349 = out_wivalid_1_1203 & out_wimask_1349; // @[RegisterRouter.scala:87:24] wire out_f_woready_1349 = out_woready_1_1203 & out_womask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12932 = ~out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12933 = ~out_wimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12934 = ~out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12935 = ~out_womask_1349; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12937 = _out_T_12936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1161 = _out_T_12937; // @[RegisterRouter.scala:87:24] wire out_rimask_1350 = \|_out_rimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_wimask_1350 = &_out_wimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_romask_1350 = \|_out_romask_T_1350; // @[RegisterRouter.scala:87:24] wire out_womask_1350 = &_out_womask_T_1350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1350 = out_rivalid_1_1204 & out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12939 = out_f_rivalid_1350; // @[RegisterRouter.scala:87:24] wire out_f_roready_1350 = out_roready_1_1204 & out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12940 = out_f_roready_1350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1350 = out_wivalid_1_1204 & out_wimask_1350; // @[RegisterRouter.scala:87:24] wire out_f_woready_1350 = out_woready_1_1204 & out_womask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12941 = ~out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12942 = ~out_wimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12943 = ~out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12944 = ~out_womask_1350; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1161 = {hi_794, flags_0_go, _out_prepend_T_1161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12945 = out_prepend_1161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12946 = _out_T_12945; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1162 = _out_T_12946; // @[RegisterRouter.scala:87:24] wire out_rimask_1351 = \|_out_rimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_wimask_1351 = &_out_wimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_romask_1351 = \|_out_romask_T_1351; // @[RegisterRouter.scala:87:24] wire out_womask_1351 = &_out_womask_T_1351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1351 = out_rivalid_1_1205 & out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12948 = out_f_rivalid_1351; // @[RegisterRouter.scala:87:24] wire out_f_roready_1351 = out_roready_1_1205 & out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12949 = out_f_roready_1351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1351 = out_wivalid_1_1205 & out_wimask_1351; // @[RegisterRouter.scala:87:24] wire out_f_woready_1351 = out_woready_1_1205 & out_womask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12950 = ~out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12951 = ~out_wimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12952 = ~out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12953 = ~out_womask_1351; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1162 = {hi_795, flags_0_go, _out_prepend_T_1162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12954 = out_prepend_1162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12955 = _out_T_12954; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1163 = _out_T_12955; // @[RegisterRouter.scala:87:24] wire out_rimask_1352 = \|_out_rimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_wimask_1352 = &_out_wimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_romask_1352 = \|_out_romask_T_1352; // @[RegisterRouter.scala:87:24] wire out_womask_1352 = &_out_womask_T_1352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1352 = out_rivalid_1_1206 & out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12957 = out_f_rivalid_1352; // @[RegisterRouter.scala:87:24] wire out_f_roready_1352 = out_roready_1_1206 & out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12958 = out_f_roready_1352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1352 = out_wivalid_1_1206 & out_wimask_1352; // @[RegisterRouter.scala:87:24] wire out_f_woready_1352 = out_woready_1_1206 & out_womask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12959 = ~out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12960 = ~out_wimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12961 = ~out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12962 = ~out_womask_1352; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1163 = {hi_796, flags_0_go, _out_prepend_T_1163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12963 = out_prepend_1163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12964 = _out_T_12963; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1164 = _out_T_12964; // @[RegisterRouter.scala:87:24] wire out_rimask_1353 = \|_out_rimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_wimask_1353 = &_out_wimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_romask_1353 = \|_out_romask_T_1353; // @[RegisterRouter.scala:87:24] wire out_womask_1353 = &_out_womask_T_1353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1353 = out_rivalid_1_1207 & out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12966 = out_f_rivalid_1353; // @[RegisterRouter.scala:87:24] wire out_f_roready_1353 = out_roready_1_1207 & out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12967 = out_f_roready_1353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1353 = out_wivalid_1_1207 & out_wimask_1353; // @[RegisterRouter.scala:87:24] wire out_f_woready_1353 = out_woready_1_1207 & out_womask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12968 = ~out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12969 = ~out_wimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12970 = ~out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12971 = ~out_womask_1353; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1164 = {hi_797, flags_0_go, _out_prepend_T_1164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12972 = out_prepend_1164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12973 = _out_T_12972; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1165 = _out_T_12973; // @[RegisterRouter.scala:87:24] wire out_rimask_1354 = \|_out_rimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_wimask_1354 = &_out_wimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_romask_1354 = \|_out_romask_T_1354; // @[RegisterRouter.scala:87:24] wire out_womask_1354 = &_out_womask_T_1354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1354 = out_rivalid_1_1208 & out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12975 = out_f_rivalid_1354; // @[RegisterRouter.scala:87:24] wire out_f_roready_1354 = out_roready_1_1208 & out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12976 = out_f_roready_1354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1354 = out_wivalid_1_1208 & out_wimask_1354; // @[RegisterRouter.scala:87:24] wire out_f_woready_1354 = out_woready_1_1208 & out_womask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12977 = ~out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12978 = ~out_wimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12979 = ~out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12980 = ~out_womask_1354; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1165 = {hi_798, flags_0_go, _out_prepend_T_1165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12981 = out_prepend_1165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12982 = _out_T_12981; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1166 = _out_T_12982; // @[RegisterRouter.scala:87:24] wire out_rimask_1355 = \|_out_rimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_wimask_1355 = &_out_wimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_romask_1355 = \|_out_romask_T_1355; // @[RegisterRouter.scala:87:24] wire out_womask_1355 = &_out_womask_T_1355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1355 = out_rivalid_1_1209 & out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12984 = out_f_rivalid_1355; // @[RegisterRouter.scala:87:24] wire out_f_roready_1355 = out_roready_1_1209 & out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12985 = out_f_roready_1355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1355 = out_wivalid_1_1209 & out_wimask_1355; // @[RegisterRouter.scala:87:24] wire out_f_woready_1355 = out_woready_1_1209 & out_womask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12986 = ~out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12987 = ~out_wimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12988 = ~out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12989 = ~out_womask_1355; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1166 = {hi_799, flags_0_go, _out_prepend_T_1166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12990 = out_prepend_1166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12991 = _out_T_12990; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1167 = _out_T_12991; // @[RegisterRouter.scala:87:24] wire out_rimask_1356 = \|_out_rimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_wimask_1356 = &_out_wimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_romask_1356 = \|_out_romask_T_1356; // @[RegisterRouter.scala:87:24] wire out_womask_1356 = &_out_womask_T_1356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1356 = out_rivalid_1_1210 & out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12993 = out_f_rivalid_1356; // @[RegisterRouter.scala:87:24] wire out_f_roready_1356 = out_roready_1_1210 & out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12994 = out_f_roready_1356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1356 = out_wivalid_1_1210 & out_wimask_1356; // @[RegisterRouter.scala:87:24] wire out_f_woready_1356 = out_woready_1_1210 & out_womask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12995 = ~out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12996 = ~out_wimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12997 = ~out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12998 = ~out_womask_1356; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1167 = {hi_800, flags_0_go, _out_prepend_T_1167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12999 = out_prepend_1167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_13000 = _out_T_12999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_227 = _out_T_13000; // @[MuxLiteral.scala:49:48] wire _out_iindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_lo = {_out_iindex_T_8, _out_iindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi_1 = {_out_iindex_T_10, _out_iindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_lo_1 = {out_iindex_lo_hi_1, out_iindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_lo = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi_1 = {_out_iindex_T_14, _out_iindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_hi_1 = {out_iindex_hi_hi_1, out_iindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_iindex_1 = {out_iindex_hi_1, out_iindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_lo = {_out_oindex_T_8, _out_oindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi_1 = {_out_oindex_T_10, _out_oindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_lo_1 = {out_oindex_lo_hi_1, out_oindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_lo = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi_1 = {_out_oindex_T_14, _out_oindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_hi_1 = {out_oindex_hi_hi_1, out_oindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_oindex_1 = {out_oindex_hi_1, out_oindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [255:0] _out_frontSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala:58:35] wire out_frontSel_0_1 = _out_frontSel_T_1[0]; // @[OneHot.scala:58:35] wire out_frontSel_1_1 = _out_frontSel_T_1[1]; // @[OneHot.scala:58:35] wire out_frontSel_2_1 = _out_frontSel_T_1[2]; // @[OneHot.scala:58:35] wire out_frontSel_3_1 = _out_frontSel_T_1[3]; // @[OneHot.scala:58:35] wire out_frontSel_4_1 = _out_frontSel_T_1[4]; // @[OneHot.scala:58:35] wire out_frontSel_5_1 = _out_frontSel_T_1[5]; // @[OneHot.scala:58:35] wire out_frontSel_6_1 = _out_frontSel_T_1[6]; // @[OneHot.scala:58:35] wire out_frontSel_7_1 = _out_frontSel_T_1[7]; // @[OneHot.scala:58:35] wire out_frontSel_8_1 = _out_frontSel_T_1[8]; // @[OneHot.scala:58:35] wire out_frontSel_9_1 = _out_frontSel_T_1[9]; // @[OneHot.scala:58:35] wire out_frontSel_10_1 = _out_frontSel_T_1[10]; // @[OneHot.scala:58:35] wire out_frontSel_11_1 = _out_frontSel_T_1[11]; // @[OneHot.scala:58:35] wire out_frontSel_12_1 = _out_frontSel_T_1[12]; // @[OneHot.scala:58:35] wire out_frontSel_13_1 = _out_frontSel_T_1[13]; // @[OneHot.scala:58:35] wire out_frontSel_14_1 = _out_frontSel_T_1[14]; // @[OneHot.scala:58:35] wire out_frontSel_15_1 = _out_frontSel_T_1[15]; // @[OneHot.scala:58:35] wire out_frontSel_16_1 = _out_frontSel_T_1[16]; // @[OneHot.scala:58:35] wire out_frontSel_17_1 = _out_frontSel_T_1[17]; // @[OneHot.scala:58:35] wire out_frontSel_18_1 = _out_frontSel_T_1[18]; // @[OneHot.scala:58:35] wire out_frontSel_19_1 = _out_frontSel_T_1[19]; // @[OneHot.scala:58:35] wire out_frontSel_20_1 = _out_frontSel_T_1[20]; // @[OneHot.scala:58:35] wire out_frontSel_21_1 = _out_frontSel_T_1[21]; // @[OneHot.scala:58:35] wire out_frontSel_22_1 = _out_frontSel_T_1[22]; // @[OneHot.scala:58:35] wire out_frontSel_23_1 = _out_frontSel_T_1[23]; // @[OneHot.scala:58:35] wire out_frontSel_24_1 = _out_frontSel_T_1[24]; // @[OneHot.scala:58:35] wire out_frontSel_25_1 = _out_frontSel_T_1[25]; // @[OneHot.scala:58:35] wire out_frontSel_26_1 = _out_frontSel_T_1[26]; // @[OneHot.scala:58:35] wire out_frontSel_27_1 = _out_frontSel_T_1[27]; // @[OneHot.scala:58:35] wire out_frontSel_28_1 = _out_frontSel_T_1[28]; // @[OneHot.scala:58:35] wire out_frontSel_29_1 = _out_frontSel_T_1[29]; // @[OneHot.scala:58:35] wire out_frontSel_30_1 = _out_frontSel_T_1[30]; // @[OneHot.scala:58:35] wire out_frontSel_31_1 = _out_frontSel_T_1[31]; // @[OneHot.scala:58:35] wire out_frontSel_32_1 = _out_frontSel_T_1[32]; // @[OneHot.scala:58:35] wire out_frontSel_33_1 = _out_frontSel_T_1[33]; // @[OneHot.scala:58:35] wire out_frontSel_34_1 = _out_frontSel_T_1[34]; // @[OneHot.scala:58:35] wire out_frontSel_35_1 = _out_frontSel_T_1[35]; // @[OneHot.scala:58:35] wire out_frontSel_36_1 = _out_frontSel_T_1[36]; // @[OneHot.scala:58:35] wire out_frontSel_37_1 = _out_frontSel_T_1[37]; // @[OneHot.scala:58:35] wire out_frontSel_38_1 = _out_frontSel_T_1[38]; // @[OneHot.scala:58:35] wire out_frontSel_39_1 = _out_frontSel_T_1[39]; // @[OneHot.scala:58:35] wire out_frontSel_40_1 = _out_frontSel_T_1[40]; // @[OneHot.scala:58:35] wire out_frontSel_41_1 = _out_frontSel_T_1[41]; // @[OneHot.scala:58:35] wire out_frontSel_42_1 = _out_frontSel_T_1[42]; // @[OneHot.scala:58:35] wire out_frontSel_43_1 = _out_frontSel_T_1[43]; // @[OneHot.scala:58:35] wire out_frontSel_44_1 = _out_frontSel_T_1[44]; // @[OneHot.scala:58:35] wire out_frontSel_45_1 = _out_frontSel_T_1[45]; // @[OneHot.scala:58:35] wire out_frontSel_46_1 = _out_frontSel_T_1[46]; // @[OneHot.scala:58:35] wire out_frontSel_47_1 = _out_frontSel_T_1[47]; // @[OneHot.scala:58:35] wire out_frontSel_48_1 = _out_frontSel_T_1[48]; // @[OneHot.scala:58:35] wire out_frontSel_49_1 = _out_frontSel_T_1[49]; // @[OneHot.scala:58:35] wire out_frontSel_50_1 = _out_frontSel_T_1[50]; // @[OneHot.scala:58:35] wire out_frontSel_51_1 = _out_frontSel_T_1[51]; // @[OneHot.scala:58:35] wire out_frontSel_52_1 = _out_frontSel_T_1[52]; // @[OneHot.scala:58:35] wire out_frontSel_53_1 = _out_frontSel_T_1[53]; // @[OneHot.scala:58:35] wire out_frontSel_54_1 = _out_frontSel_T_1[54]; // @[OneHot.scala:58:35] wire out_frontSel_55_1 = _out_frontSel_T_1[55]; // @[OneHot.scala:58:35] wire out_frontSel_56_1 = _out_frontSel_T_1[56]; // @[OneHot.scala:58:35] wire out_frontSel_57_1 = _out_frontSel_T_1[57]; // @[OneHot.scala:58:35] wire out_frontSel_58_1 = _out_frontSel_T_1[58]; // @[OneHot.scala:58:35] wire out_frontSel_59_1 = _out_frontSel_T_1[59]; // @[OneHot.scala:58:35] wire out_frontSel_60_1 = _out_frontSel_T_1[60]; // @[OneHot.scala:58:35] wire out_frontSel_61_1 = _out_frontSel_T_1[61]; // @[OneHot.scala:58:35] wire out_frontSel_62_1 = _out_frontSel_T_1[62]; // @[OneHot.scala:58:35] wire out_frontSel_63_1 = _out_frontSel_T_1[63]; // @[OneHot.scala:58:35] wire out_frontSel_64 = _out_frontSel_T_1[64]; // @[OneHot.scala:58:35] wire out_frontSel_65 = _out_frontSel_T_1[65]; // @[OneHot.scala:58:35] wire out_frontSel_66 = _out_frontSel_T_1[66]; // @[OneHot.scala:58:35] wire out_frontSel_67 = _out_frontSel_T_1[67]; // @[OneHot.scala:58:35] wire out_frontSel_68 = _out_frontSel_T_1[68]; // @[OneHot.scala:58:35] wire out_frontSel_69 = _out_frontSel_T_1[69]; // @[OneHot.scala:58:35] wire out_frontSel_70 = _out_frontSel_T_1[70]; // @[OneHot.scala:58:35] wire out_frontSel_71 = _out_frontSel_T_1[71]; // @[OneHot.scala:58:35] wire out_frontSel_72 = _out_frontSel_T_1[72]; // @[OneHot.scala:58:35] wire out_frontSel_73 = _out_frontSel_T_1[73]; // @[OneHot.scala:58:35] wire out_frontSel_74 = _out_frontSel_T_1[74]; // @[OneHot.scala:58:35] wire out_frontSel_75 = _out_frontSel_T_1[75]; // @[OneHot.scala:58:35] wire out_frontSel_76 = _out_frontSel_T_1[76]; // @[OneHot.scala:58:35] wire out_frontSel_77 = _out_frontSel_T_1[77]; // @[OneHot.scala:58:35] wire out_frontSel_78 = _out_frontSel_T_1[78]; // @[OneHot.scala:58:35] wire out_frontSel_79 = _out_frontSel_T_1[79]; // @[OneHot.scala:58:35] wire out_frontSel_80 = _out_frontSel_T_1[80]; // @[OneHot.scala:58:35] wire out_frontSel_81 = _out_frontSel_T_1[81]; // @[OneHot.scala:58:35] wire out_frontSel_82 = _out_frontSel_T_1[82]; // @[OneHot.scala:58:35] wire out_frontSel_83 = _out_frontSel_T_1[83]; // @[OneHot.scala:58:35] wire out_frontSel_84 = _out_frontSel_T_1[84]; // @[OneHot.scala:58:35] wire out_frontSel_85 = _out_frontSel_T_1[85]; // @[OneHot.scala:58:35] wire out_frontSel_86 = _out_frontSel_T_1[86]; // @[OneHot.scala:58:35] wire out_frontSel_87 = _out_frontSel_T_1[87]; // @[OneHot.scala:58:35] wire out_frontSel_88 = _out_frontSel_T_1[88]; // @[OneHot.scala:58:35] wire out_frontSel_89 = _out_frontSel_T_1[89]; // @[OneHot.scala:58:35] wire out_frontSel_90 = _out_frontSel_T_1[90]; // @[OneHot.scala:58:35] wire out_frontSel_91 = _out_frontSel_T_1[91]; // @[OneHot.scala:58:35] wire out_frontSel_92 = _out_frontSel_T_1[92]; // @[OneHot.scala:58:35] wire out_frontSel_93 = _out_frontSel_T_1[93]; // @[OneHot.scala:58:35] wire out_frontSel_94 = _out_frontSel_T_1[94]; // @[OneHot.scala:58:35] wire out_frontSel_95 = _out_frontSel_T_1[95]; // @[OneHot.scala:58:35] wire out_frontSel_96 = _out_frontSel_T_1[96]; // @[OneHot.scala:58:35] wire out_frontSel_97 = _out_frontSel_T_1[97]; // @[OneHot.scala:58:35] wire out_frontSel_98 = _out_frontSel_T_1[98]; // @[OneHot.scala:58:35] wire out_frontSel_99 = _out_frontSel_T_1[99]; // @[OneHot.scala:58:35] wire out_frontSel_100 = _out_frontSel_T_1[100]; // @[OneHot.scala:58:35] wire out_frontSel_101 = _out_frontSel_T_1[101]; // @[OneHot.scala:58:35] wire out_frontSel_102 = _out_frontSel_T_1[102]; // @[OneHot.scala:58:35] wire out_frontSel_103 = _out_frontSel_T_1[103]; // @[OneHot.scala:58:35] wire out_frontSel_104 = _out_frontSel_T_1[104]; // @[OneHot.scala:58:35] wire out_frontSel_105 = _out_frontSel_T_1[105]; // @[OneHot.scala:58:35] wire out_frontSel_106 = _out_frontSel_T_1[106]; // @[OneHot.scala:58:35] wire out_frontSel_107 = _out_frontSel_T_1[107]; // @[OneHot.scala:58:35] wire out_frontSel_108 = _out_frontSel_T_1[108]; // @[OneHot.scala:58:35] wire out_frontSel_109 = _out_frontSel_T_1[109]; // @[OneHot.scala:58:35] wire out_frontSel_110 = _out_frontSel_T_1[110]; // @[OneHot.scala:58:35] wire out_frontSel_111 = _out_frontSel_T_1[111]; // @[OneHot.scala:58:35] wire out_frontSel_112 = _out_frontSel_T_1[112]; // @[OneHot.scala:58:35] wire out_frontSel_113 = _out_frontSel_T_1[113]; // @[OneHot.scala:58:35] wire out_frontSel_114 = _out_frontSel_T_1[114]; // @[OneHot.scala:58:35] wire out_frontSel_115 = _out_frontSel_T_1[115]; // @[OneHot.scala:58:35] wire out_frontSel_116 = _out_frontSel_T_1[116]; // @[OneHot.scala:58:35] wire out_frontSel_117 = _out_frontSel_T_1[117]; // @[OneHot.scala:58:35] wire out_frontSel_118 = _out_frontSel_T_1[118]; // @[OneHot.scala:58:35] wire out_frontSel_119 = _out_frontSel_T_1[119]; // @[OneHot.scala:58:35] wire out_frontSel_120 = _out_frontSel_T_1[120]; // @[OneHot.scala:58:35] wire out_frontSel_121 = _out_frontSel_T_1[121]; // @[OneHot.scala:58:35] wire out_frontSel_122 = _out_frontSel_T_1[122]; // @[OneHot.scala:58:35] wire out_frontSel_123 = _out_frontSel_T_1[123]; // @[OneHot.scala:58:35] wire out_frontSel_124 = _out_frontSel_T_1[124]; // @[OneHot.scala:58:35] wire out_frontSel_125 = _out_frontSel_T_1[125]; // @[OneHot.scala:58:35] wire out_frontSel_126 = _out_frontSel_T_1[126]; // @[OneHot.scala:58:35] wire out_frontSel_127 = _out_frontSel_T_1[127]; // @[OneHot.scala:58:35] wire out_frontSel_128 = _out_frontSel_T_1[128]; // @[OneHot.scala:58:35] wire out_frontSel_129 = _out_frontSel_T_1[129]; // @[OneHot.scala:58:35] wire out_frontSel_130 = _out_frontSel_T_1[130]; // @[OneHot.scala:58:35] wire out_frontSel_131 = _out_frontSel_T_1[131]; // @[OneHot.scala:58:35] wire out_frontSel_132 = _out_frontSel_T_1[132]; // @[OneHot.scala:58:35] wire out_frontSel_133 = _out_frontSel_T_1[133]; // @[OneHot.scala:58:35] wire out_frontSel_134 = _out_frontSel_T_1[134]; // @[OneHot.scala:58:35] wire out_frontSel_135 = _out_frontSel_T_1[135]; // @[OneHot.scala:58:35] wire out_frontSel_136 = _out_frontSel_T_1[136]; // @[OneHot.scala:58:35] wire out_frontSel_137 = _out_frontSel_T_1[137]; // @[OneHot.scala:58:35] wire out_frontSel_138 = _out_frontSel_T_1[138]; // @[OneHot.scala:58:35] wire out_frontSel_139 = _out_frontSel_T_1[139]; // @[OneHot.scala:58:35] wire out_frontSel_140 = _out_frontSel_T_1[140]; // @[OneHot.scala:58:35] wire out_frontSel_141 = _out_frontSel_T_1[141]; // @[OneHot.scala:58:35] wire out_frontSel_142 = _out_frontSel_T_1[142]; // @[OneHot.scala:58:35] wire out_frontSel_143 = _out_frontSel_T_1[143]; // @[OneHot.scala:58:35] wire out_frontSel_144 = _out_frontSel_T_1[144]; // @[OneHot.scala:58:35] wire out_frontSel_145 = _out_frontSel_T_1[145]; // @[OneHot.scala:58:35] wire out_frontSel_146 = _out_frontSel_T_1[146]; // @[OneHot.scala:58:35] wire out_frontSel_147 = _out_frontSel_T_1[147]; // @[OneHot.scala:58:35] wire out_frontSel_148 = _out_frontSel_T_1[148]; // @[OneHot.scala:58:35] wire out_frontSel_149 = _out_frontSel_T_1[149]; // @[OneHot.scala:58:35] wire out_frontSel_150 = _out_frontSel_T_1[150]; // @[OneHot.scala:58:35] wire out_frontSel_151 = _out_frontSel_T_1[151]; // @[OneHot.scala:58:35] wire out_frontSel_152 = _out_frontSel_T_1[152]; // @[OneHot.scala:58:35] wire out_frontSel_153 = _out_frontSel_T_1[153]; // @[OneHot.scala:58:35] wire out_frontSel_154 = _out_frontSel_T_1[154]; // @[OneHot.scala:58:35] wire out_frontSel_155 = _out_frontSel_T_1[155]; // @[OneHot.scala:58:35] wire out_frontSel_156 = _out_frontSel_T_1[156]; // @[OneHot.scala:58:35] wire out_frontSel_157 = _out_frontSel_T_1[157]; // @[OneHot.scala:58:35] wire out_frontSel_158 = _out_frontSel_T_1[158]; // @[OneHot.scala:58:35] wire out_frontSel_159 = _out_frontSel_T_1[159]; // @[OneHot.scala:58:35] wire out_frontSel_160 = _out_frontSel_T_1[160]; // @[OneHot.scala:58:35] wire out_frontSel_161 = _out_frontSel_T_1[161]; // @[OneHot.scala:58:35] wire out_frontSel_162 = _out_frontSel_T_1[162]; // @[OneHot.scala:58:35] wire out_frontSel_163 = _out_frontSel_T_1[163]; // @[OneHot.scala:58:35] wire out_frontSel_164 = _out_frontSel_T_1[164]; // @[OneHot.scala:58:35] wire out_frontSel_165 = _out_frontSel_T_1[165]; // @[OneHot.scala:58:35] wire out_frontSel_166 = _out_frontSel_T_1[166]; // @[OneHot.scala:58:35] wire out_frontSel_167 = _out_frontSel_T_1[167]; // @[OneHot.scala:58:35] wire out_frontSel_168 = _out_frontSel_T_1[168]; // @[OneHot.scala:58:35] wire out_frontSel_169 = _out_frontSel_T_1[169]; // @[OneHot.scala:58:35] wire out_frontSel_170 = _out_frontSel_T_1[170]; // @[OneHot.scala:58:35] wire out_frontSel_171 = _out_frontSel_T_1[171]; // @[OneHot.scala:58:35] wire out_frontSel_172 = _out_frontSel_T_1[172]; // @[OneHot.scala:58:35] wire out_frontSel_173 = _out_frontSel_T_1[173]; // @[OneHot.scala:58:35] wire out_frontSel_174 = _out_frontSel_T_1[174]; // @[OneHot.scala:58:35] wire out_frontSel_175 = _out_frontSel_T_1[175]; // @[OneHot.scala:58:35] wire out_frontSel_176 = _out_frontSel_T_1[176]; // @[OneHot.scala:58:35] wire out_frontSel_177 = _out_frontSel_T_1[177]; // @[OneHot.scala:58:35] wire out_frontSel_178 = _out_frontSel_T_1[178]; // @[OneHot.scala:58:35] wire out_frontSel_179 = _out_frontSel_T_1[179]; // @[OneHot.scala:58:35] wire out_frontSel_180 = _out_frontSel_T_1[180]; // @[OneHot.scala:58:35] wire out_frontSel_181 = _out_frontSel_T_1[181]; // @[OneHot.scala:58:35] wire out_frontSel_182 = _out_frontSel_T_1[182]; // @[OneHot.scala:58:35] wire out_frontSel_183 = _out_frontSel_T_1[183]; // @[OneHot.scala:58:35] wire out_frontSel_184 = _out_frontSel_T_1[184]; // @[OneHot.scala:58:35] wire out_frontSel_185 = _out_frontSel_T_1[185]; // @[OneHot.scala:58:35] wire out_frontSel_186 = _out_frontSel_T_1[186]; // @[OneHot.scala:58:35] wire out_frontSel_187 = _out_frontSel_T_1[187]; // @[OneHot.scala:58:35] wire out_frontSel_188 = _out_frontSel_T_1[188]; // @[OneHot.scala:58:35] wire out_frontSel_189 = _out_frontSel_T_1[189]; // @[OneHot.scala:58:35] wire out_frontSel_190 = _out_frontSel_T_1[190]; // @[OneHot.scala:58:35] wire out_frontSel_191 = _out_frontSel_T_1[191]; // @[OneHot.scala:58:35] wire out_frontSel_192 = _out_frontSel_T_1[192]; // @[OneHot.scala:58:35] wire out_frontSel_193 = _out_frontSel_T_1[193]; // @[OneHot.scala:58:35] wire out_frontSel_194 = _out_frontSel_T_1[194]; // @[OneHot.scala:58:35] wire out_frontSel_195 = _out_frontSel_T_1[195]; // @[OneHot.scala:58:35] wire out_frontSel_196 = _out_frontSel_T_1[196]; // @[OneHot.scala:58:35] wire out_frontSel_197 = _out_frontSel_T_1[197]; // @[OneHot.scala:58:35] wire out_frontSel_198 = _out_frontSel_T_1[198]; // @[OneHot.scala:58:35] wire out_frontSel_199 = _out_frontSel_T_1[199]; // @[OneHot.scala:58:35] wire out_frontSel_200 = _out_frontSel_T_1[200]; // @[OneHot.scala:58:35] wire out_frontSel_201 = _out_frontSel_T_1[201]; // @[OneHot.scala:58:35] wire out_frontSel_202 = _out_frontSel_T_1[202]; // @[OneHot.scala:58:35] wire out_frontSel_203 = _out_frontSel_T_1[203]; // @[OneHot.scala:58:35] wire out_frontSel_204 = _out_frontSel_T_1[204]; // @[OneHot.scala:58:35] wire out_frontSel_205 = _out_frontSel_T_1[205]; // @[OneHot.scala:58:35] wire out_frontSel_206 = _out_frontSel_T_1[206]; // @[OneHot.scala:58:35] wire out_frontSel_207 = _out_frontSel_T_1[207]; // @[OneHot.scala:58:35] wire out_frontSel_208 = _out_frontSel_T_1[208]; // @[OneHot.scala:58:35] wire out_frontSel_209 = _out_frontSel_T_1[209]; // @[OneHot.scala:58:35] wire out_frontSel_210 = _out_frontSel_T_1[210]; // @[OneHot.scala:58:35] wire out_frontSel_211 = _out_frontSel_T_1[211]; // @[OneHot.scala:58:35] wire out_frontSel_212 = _out_frontSel_T_1[212]; // @[OneHot.scala:58:35] wire out_frontSel_213 = _out_frontSel_T_1[213]; // @[OneHot.scala:58:35] wire out_frontSel_214 = _out_frontSel_T_1[214]; // @[OneHot.scala:58:35] wire out_frontSel_215 = _out_frontSel_T_1[215]; // @[OneHot.scala:58:35] wire out_frontSel_216 = _out_frontSel_T_1[216]; // @[OneHot.scala:58:35] wire out_frontSel_217 = _out_frontSel_T_1[217]; // @[OneHot.scala:58:35] wire out_frontSel_218 = _out_frontSel_T_1[218]; // @[OneHot.scala:58:35] wire out_frontSel_219 = _out_frontSel_T_1[219]; // @[OneHot.scala:58:35] wire out_frontSel_220 = _out_frontSel_T_1[220]; // @[OneHot.scala:58:35] wire out_frontSel_221 = _out_frontSel_T_1[221]; // @[OneHot.scala:58:35] wire out_frontSel_222 = _out_frontSel_T_1[222]; // @[OneHot.scala:58:35] wire out_frontSel_223 = _out_frontSel_T_1[223]; // @[OneHot.scala:58:35] wire out_frontSel_224 = _out_frontSel_T_1[224]; // @[OneHot.scala:58:35] wire out_frontSel_225 = _out_frontSel_T_1[225]; // @[OneHot.scala:58:35] wire out_frontSel_226 = _out_frontSel_T_1[226]; // @[OneHot.scala:58:35] wire out_frontSel_227 = _out_frontSel_T_1[227]; // @[OneHot.scala:58:35] wire out_frontSel_228 = _out_frontSel_T_1[228]; // @[OneHot.scala:58:35] wire out_frontSel_229 = _out_frontSel_T_1[229]; // @[OneHot.scala:58:35] wire out_frontSel_230 = _out_frontSel_T_1[230]; // @[OneHot.scala:58:35] wire out_frontSel_231 = _out_frontSel_T_1[231]; // @[OneHot.scala:58:35] wire out_frontSel_232 = _out_frontSel_T_1[232]; // @[OneHot.scala:58:35] wire out_frontSel_233 = _out_frontSel_T_1[233]; // @[OneHot.scala:58:35] wire out_frontSel_234 = _out_frontSel_T_1[234]; // @[OneHot.scala:58:35] wire out_frontSel_235 = _out_frontSel_T_1[235]; // @[OneHot.scala:58:35] wire out_frontSel_236 = _out_frontSel_T_1[236]; // @[OneHot.scala:58:35] wire out_frontSel_237 = _out_frontSel_T_1[237]; // @[OneHot.scala:58:35] wire out_frontSel_238 = _out_frontSel_T_1[238]; // @[OneHot.scala:58:35] wire out_frontSel_239 = _out_frontSel_T_1[239]; // @[OneHot.scala:58:35] wire out_frontSel_240 = _out_frontSel_T_1[240]; // @[OneHot.scala:58:35] wire out_frontSel_241 = _out_frontSel_T_1[241]; // @[OneHot.scala:58:35] wire out_frontSel_242 = _out_frontSel_T_1[242]; // @[OneHot.scala:58:35] wire out_frontSel_243 = _out_frontSel_T_1[243]; // @[OneHot.scala:58:35] wire out_frontSel_244 = _out_frontSel_T_1[244]; // @[OneHot.scala:58:35] wire out_frontSel_245 = _out_frontSel_T_1[245]; // @[OneHot.scala:58:35] wire out_frontSel_246 = _out_frontSel_T_1[246]; // @[OneHot.scala:58:35] wire out_frontSel_247 = _out_frontSel_T_1[247]; // @[OneHot.scala:58:35] wire out_frontSel_248 = _out_frontSel_T_1[248]; // @[OneHot.scala:58:35] wire out_frontSel_249 = _out_frontSel_T_1[249]; // @[OneHot.scala:58:35] wire out_frontSel_250 = _out_frontSel_T_1[250]; // @[OneHot.scala:58:35] wire out_frontSel_251 = _out_frontSel_T_1[251]; // @[OneHot.scala:58:35] wire out_frontSel_252 = _out_frontSel_T_1[252]; // @[OneHot.scala:58:35] wire out_frontSel_253 = _out_frontSel_T_1[253]; // @[OneHot.scala:58:35] wire out_frontSel_254 = _out_frontSel_T_1[254]; // @[OneHot.scala:58:35] wire out_frontSel_255 = _out_frontSel_T_1[255]; // @[OneHot.scala:58:35] wire [255:0] _out_backSel_T_1 = 256'h1 << out_oindex_1; // @[OneHot.scala:58:35] wire out_backSel_0_1 = _out_backSel_T_1[0]; // @[OneHot.scala:58:35] wire out_backSel_1_1 = _out_backSel_T_1[1]; // @[OneHot.scala:58:35] wire out_backSel_2_1 = _out_backSel_T_1[2]; // @[OneHot.scala:58:35] wire out_backSel_3_1 = _out_backSel_T_1[3]; // @[OneHot.scala:58:35] wire out_backSel_4_1 = _out_backSel_T_1[4]; // @[OneHot.scala:58:35] wire out_backSel_5_1 = _out_backSel_T_1[5]; // @[OneHot.scala:58:35] wire out_backSel_6_1 = _out_backSel_T_1[6]; // @[OneHot.scala:58:35] wire out_backSel_7_1 = _out_backSel_T_1[7]; // @[OneHot.scala:58:35] wire out_backSel_8_1 = _out_backSel_T_1[8]; // @[OneHot.scala:58:35] wire out_backSel_9_1 = _out_backSel_T_1[9]; // @[OneHot.scala:58:35] wire out_backSel_10_1 = _out_backSel_T_1[10]; // @[OneHot.scala:58:35] wire out_backSel_11_1 = _out_backSel_T_1[11]; // @[OneHot.scala:58:35] wire out_backSel_12_1 = _out_backSel_T_1[12]; // @[OneHot.scala:58:35] wire out_backSel_13_1 = _out_backSel_T_1[13]; // @[OneHot.scala:58:35] wire out_backSel_14_1 = _out_backSel_T_1[14]; // @[OneHot.scala:58:35] wire out_backSel_15_1 = _out_backSel_T_1[15]; // @[OneHot.scala:58:35] wire out_backSel_16_1 = _out_backSel_T_1[16]; // @[OneHot.scala:58:35] wire out_backSel_17_1 = _out_backSel_T_1[17]; // @[OneHot.scala:58:35] wire out_backSel_18_1 = _out_backSel_T_1[18]; // @[OneHot.scala:58:35] wire out_backSel_19_1 = _out_backSel_T_1[19]; // @[OneHot.scala:58:35] wire out_backSel_20_1 = _out_backSel_T_1[20]; // @[OneHot.scala:58:35] wire out_backSel_21_1 = _out_backSel_T_1[21]; // @[OneHot.scala:58:35] wire out_backSel_22_1 = _out_backSel_T_1[22]; // @[OneHot.scala:58:35] wire out_backSel_23_1 = _out_backSel_T_1[23]; // @[OneHot.scala:58:35] wire out_backSel_24_1 = _out_backSel_T_1[24]; // @[OneHot.scala:58:35] wire out_backSel_25_1 = _out_backSel_T_1[25]; // @[OneHot.scala:58:35] wire out_backSel_26_1 = _out_backSel_T_1[26]; // @[OneHot.scala:58:35] wire out_backSel_27_1 = _out_backSel_T_1[27]; // @[OneHot.scala:58:35] wire out_backSel_28_1 = _out_backSel_T_1[28]; // @[OneHot.scala:58:35] wire out_backSel_29_1 = _out_backSel_T_1[29]; // @[OneHot.scala:58:35] wire out_backSel_30_1 = _out_backSel_T_1[30]; // @[OneHot.scala:58:35] wire out_backSel_31_1 = _out_backSel_T_1[31]; // @[OneHot.scala:58:35] wire out_backSel_32_1 = _out_backSel_T_1[32]; // @[OneHot.scala:58:35] wire out_backSel_33_1 = _out_backSel_T_1[33]; // @[OneHot.scala:58:35] wire out_backSel_34_1 = _out_backSel_T_1[34]; // @[OneHot.scala:58:35] wire out_backSel_35_1 = _out_backSel_T_1[35]; // @[OneHot.scala:58:35] wire out_backSel_36_1 = _out_backSel_T_1[36]; // @[OneHot.scala:58:35] wire out_backSel_37_1 = _out_backSel_T_1[37]; // @[OneHot.scala:58:35] wire out_backSel_38_1 = _out_backSel_T_1[38]; // @[OneHot.scala:58:35] wire out_backSel_39_1 = _out_backSel_T_1[39]; // @[OneHot.scala:58:35] wire out_backSel_40_1 = _out_backSel_T_1[40]; // @[OneHot.scala:58:35] wire out_backSel_41_1 = _out_backSel_T_1[41]; // @[OneHot.scala:58:35] wire out_backSel_42_1 = _out_backSel_T_1[42]; // @[OneHot.scala:58:35] wire out_backSel_43_1 = _out_backSel_T_1[43]; // @[OneHot.scala:58:35] wire out_backSel_44_1 = _out_backSel_T_1[44]; // @[OneHot.scala:58:35] wire out_backSel_45_1 = _out_backSel_T_1[45]; // @[OneHot.scala:58:35] wire out_backSel_46_1 = _out_backSel_T_1[46]; // @[OneHot.scala:58:35] wire out_backSel_47_1 = _out_backSel_T_1[47]; // @[OneHot.scala:58:35] wire out_backSel_48_1 = _out_backSel_T_1[48]; // @[OneHot.scala:58:35] wire out_backSel_49_1 = _out_backSel_T_1[49]; // @[OneHot.scala:58:35] wire out_backSel_50_1 = _out_backSel_T_1[50]; // @[OneHot.scala:58:35] wire out_backSel_51_1 = _out_backSel_T_1[51]; // @[OneHot.scala:58:35] wire out_backSel_52_1 = _out_backSel_T_1[52]; // @[OneHot.scala:58:35] wire out_backSel_53_1 = _out_backSel_T_1[53]; // @[OneHot.scala:58:35] wire out_backSel_54_1 = _out_backSel_T_1[54]; // @[OneHot.scala:58:35] wire out_backSel_55_1 = _out_backSel_T_1[55]; // @[OneHot.scala:58:35] wire out_backSel_56_1 = _out_backSel_T_1[56]; // @[OneHot.scala:58:35] wire out_backSel_57_1 = _out_backSel_T_1[57]; // @[OneHot.scala:58:35] wire out_backSel_58_1 = _out_backSel_T_1[58]; // @[OneHot.scala:58:35] wire out_backSel_59_1 = _out_backSel_T_1[59]; // @[OneHot.scala:58:35] wire out_backSel_60_1 = _out_backSel_T_1[60]; // @[OneHot.scala:58:35] wire out_backSel_61_1 = _out_backSel_T_1[61]; // @[OneHot.scala:58:35] wire out_backSel_62_1 = _out_backSel_T_1[62]; // @[OneHot.scala:58:35] wire out_backSel_63_1 = _out_backSel_T_1[63]; // @[OneHot.scala:58:35] wire out_backSel_64 = _out_backSel_T_1[64]; // @[OneHot.scala:58:35] wire out_backSel_65 = _out_backSel_T_1[65]; // @[OneHot.scala:58:35] wire out_backSel_66 = _out_backSel_T_1[66]; // @[OneHot.scala:58:35] wire out_backSel_67 = _out_backSel_T_1[67]; // @[OneHot.scala:58:35] wire out_backSel_68 = _out_backSel_T_1[68]; // @[OneHot.scala:58:35] wire out_backSel_69 = _out_backSel_T_1[69]; // @[OneHot.scala:58:35] wire out_backSel_70 = _out_backSel_T_1[70]; // @[OneHot.scala:58:35] wire out_backSel_71 = _out_backSel_T_1[71]; // @[OneHot.scala:58:35] wire out_backSel_72 = _out_backSel_T_1[72]; // @[OneHot.scala:58:35] wire out_backSel_73 = _out_backSel_T_1[73]; // @[OneHot.scala:58:35] wire out_backSel_74 = _out_backSel_T_1[74]; // @[OneHot.scala:58:35] wire out_backSel_75 = _out_backSel_T_1[75]; // @[OneHot.scala:58:35] wire out_backSel_76 = _out_backSel_T_1[76]; // @[OneHot.scala:58:35] wire out_backSel_77 = _out_backSel_T_1[77]; // @[OneHot.scala:58:35] wire out_backSel_78 = _out_backSel_T_1[78]; // @[OneHot.scala:58:35] wire out_backSel_79 = _out_backSel_T_1[79]; // @[OneHot.scala:58:35] wire out_backSel_80 = _out_backSel_T_1[80]; // @[OneHot.scala:58:35] wire out_backSel_81 = _out_backSel_T_1[81]; // @[OneHot.scala:58:35] wire out_backSel_82 = _out_backSel_T_1[82]; // @[OneHot.scala:58:35] wire out_backSel_83 = _out_backSel_T_1[83]; // @[OneHot.scala:58:35] wire out_backSel_84 = _out_backSel_T_1[84]; // @[OneHot.scala:58:35] wire out_backSel_85 = _out_backSel_T_1[85]; // @[OneHot.scala:58:35] wire out_backSel_86 = _out_backSel_T_1[86]; // @[OneHot.scala:58:35] wire out_backSel_87 = _out_backSel_T_1[87]; // @[OneHot.scala:58:35] wire out_backSel_88 = _out_backSel_T_1[88]; // @[OneHot.scala:58:35] wire out_backSel_89 = _out_backSel_T_1[89]; // @[OneHot.scala:58:35] wire out_backSel_90 = _out_backSel_T_1[90]; // @[OneHot.scala:58:35] wire out_backSel_91 = _out_backSel_T_1[91]; // @[OneHot.scala:58:35] wire out_backSel_92 = _out_backSel_T_1[92]; // @[OneHot.scala:58:35] wire out_backSel_93 = _out_backSel_T_1[93]; // @[OneHot.scala:58:35] wire out_backSel_94 = _out_backSel_T_1[94]; // @[OneHot.scala:58:35] wire out_backSel_95 = _out_backSel_T_1[95]; // @[OneHot.scala:58:35] wire out_backSel_96 = _out_backSel_T_1[96]; // @[OneHot.scala:58:35] wire out_backSel_97 = _out_backSel_T_1[97]; // @[OneHot.scala:58:35] wire out_backSel_98 = _out_backSel_T_1[98]; // @[OneHot.scala:58:35] wire out_backSel_99 = _out_backSel_T_1[99]; // @[OneHot.scala:58:35] wire out_backSel_100 = _out_backSel_T_1[100]; // @[OneHot.scala:58:35] wire out_backSel_101 = _out_backSel_T_1[101]; // @[OneHot.scala:58:35] wire out_backSel_102 = _out_backSel_T_1[102]; // @[OneHot.scala:58:35] wire out_backSel_103 = _out_backSel_T_1[103]; // @[OneHot.scala:58:35] wire out_backSel_104 = _out_backSel_T_1[104]; // @[OneHot.scala:58:35] wire out_backSel_105 = _out_backSel_T_1[105]; // @[OneHot.scala:58:35] wire out_backSel_106 = _out_backSel_T_1[106]; // @[OneHot.scala:58:35] wire out_backSel_107 = _out_backSel_T_1[107]; // @[OneHot.scala:58:35] wire out_backSel_108 = _out_backSel_T_1[108]; // @[OneHot.scala:58:35] wire out_backSel_109 = _out_backSel_T_1[109]; // @[OneHot.scala:58:35] wire out_backSel_110 = _out_backSel_T_1[110]; // @[OneHot.scala:58:35] wire out_backSel_111 = _out_backSel_T_1[111]; // @[OneHot.scala:58:35] wire out_backSel_112 = _out_backSel_T_1[112]; // @[OneHot.scala:58:35] wire out_backSel_113 = _out_backSel_T_1[113]; // @[OneHot.scala:58:35] wire out_backSel_114 = _out_backSel_T_1[114]; // @[OneHot.scala:58:35] wire out_backSel_115 = _out_backSel_T_1[115]; // @[OneHot.scala:58:35] wire out_backSel_116 = _out_backSel_T_1[116]; // @[OneHot.scala:58:35] wire out_backSel_117 = _out_backSel_T_1[117]; // @[OneHot.scala:58:35] wire out_backSel_118 = _out_backSel_T_1[118]; // @[OneHot.scala:58:35] wire out_backSel_119 = _out_backSel_T_1[119]; // @[OneHot.scala:58:35] wire out_backSel_120 = _out_backSel_T_1[120]; // @[OneHot.scala:58:35] wire out_backSel_121 = _out_backSel_T_1[121]; // @[OneHot.scala:58:35] wire out_backSel_122 = _out_backSel_T_1[122]; // @[OneHot.scala:58:35] wire out_backSel_123 = _out_backSel_T_1[123]; // @[OneHot.scala:58:35] wire out_backSel_124 = _out_backSel_T_1[124]; // @[OneHot.scala:58:35] wire out_backSel_125 = _out_backSel_T_1[125]; // @[OneHot.scala:58:35] wire out_backSel_126 = _out_backSel_T_1[126]; // @[OneHot.scala:58:35] wire out_backSel_127 = _out_backSel_T_1[127]; // @[OneHot.scala:58:35] wire out_backSel_128 = _out_backSel_T_1[128]; // @[OneHot.scala:58:35] wire out_backSel_129 = _out_backSel_T_1[129]; // @[OneHot.scala:58:35] wire out_backSel_130 = _out_backSel_T_1[130]; // @[OneHot.scala:58:35] wire out_backSel_131 = _out_backSel_T_1[131]; // @[OneHot.scala:58:35] wire out_backSel_132 = _out_backSel_T_1[132]; // @[OneHot.scala:58:35] wire out_backSel_133 = _out_backSel_T_1[133]; // @[OneHot.scala:58:35] wire out_backSel_134 = _out_backSel_T_1[134]; // @[OneHot.scala:58:35] wire out_backSel_135 = _out_backSel_T_1[135]; // @[OneHot.scala:58:35] wire out_backSel_136 = _out_backSel_T_1[136]; // @[OneHot.scala:58:35] wire out_backSel_137 = _out_backSel_T_1[137]; // @[OneHot.scala:58:35] wire out_backSel_138 = _out_backSel_T_1[138]; // @[OneHot.scala:58:35] wire out_backSel_139 = _out_backSel_T_1[139]; // @[OneHot.scala:58:35] wire out_backSel_140 = _out_backSel_T_1[140]; // @[OneHot.scala:58:35] wire out_backSel_141 = _out_backSel_T_1[141]; // @[OneHot.scala:58:35] wire out_backSel_142 = _out_backSel_T_1[142]; // @[OneHot.scala:58:35] wire out_backSel_143 = _out_backSel_T_1[143]; // @[OneHot.scala:58:35] wire out_backSel_144 = _out_backSel_T_1[144]; // @[OneHot.scala:58:35] wire out_backSel_145 = _out_backSel_T_1[145]; // @[OneHot.scala:58:35] wire out_backSel_146 = _out_backSel_T_1[146]; // @[OneHot.scala:58:35] wire out_backSel_147 = _out_backSel_T_1[147]; // @[OneHot.scala:58:35] wire out_backSel_148 = _out_backSel_T_1[148]; // @[OneHot.scala:58:35] wire out_backSel_149 = _out_backSel_T_1[149]; // @[OneHot.scala:58:35] wire out_backSel_150 = _out_backSel_T_1[150]; // @[OneHot.scala:58:35] wire out_backSel_151 = _out_backSel_T_1[151]; // @[OneHot.scala:58:35] wire out_backSel_152 = _out_backSel_T_1[152]; // @[OneHot.scala:58:35] wire out_backSel_153 = _out_backSel_T_1[153]; // @[OneHot.scala:58:35] wire out_backSel_154 = _out_backSel_T_1[154]; // @[OneHot.scala:58:35] wire out_backSel_155 = _out_backSel_T_1[155]; // @[OneHot.scala:58:35] wire out_backSel_156 = _out_backSel_T_1[156]; // @[OneHot.scala:58:35] wire out_backSel_157 = _out_backSel_T_1[157]; // @[OneHot.scala:58:35] wire out_backSel_158 = _out_backSel_T_1[158]; // @[OneHot.scala:58:35] wire out_backSel_159 = _out_backSel_T_1[159]; // @[OneHot.scala:58:35] wire out_backSel_160 = _out_backSel_T_1[160]; // @[OneHot.scala:58:35] wire out_backSel_161 = _out_backSel_T_1[161]; // @[OneHot.scala:58:35] wire out_backSel_162 = _out_backSel_T_1[162]; // @[OneHot.scala:58:35] wire out_backSel_163 = _out_backSel_T_1[163]; // @[OneHot.scala:58:35] wire out_backSel_164 = _out_backSel_T_1[164]; // @[OneHot.scala:58:35] wire out_backSel_165 = _out_backSel_T_1[165]; // @[OneHot.scala:58:35] wire out_backSel_166 = _out_backSel_T_1[166]; // @[OneHot.scala:58:35] wire out_backSel_167 = _out_backSel_T_1[167]; // @[OneHot.scala:58:35] wire out_backSel_168 = _out_backSel_T_1[168]; // @[OneHot.scala:58:35] wire out_backSel_169 = _out_backSel_T_1[169]; // @[OneHot.scala:58:35] wire out_backSel_170 = _out_backSel_T_1[170]; // @[OneHot.scala:58:35] wire out_backSel_171 = _out_backSel_T_1[171]; // @[OneHot.scala:58:35] wire out_backSel_172 = _out_backSel_T_1[172]; // @[OneHot.scala:58:35] wire out_backSel_173 = _out_backSel_T_1[173]; // @[OneHot.scala:58:35] wire out_backSel_174 = _out_backSel_T_1[174]; // @[OneHot.scala:58:35] wire out_backSel_175 = _out_backSel_T_1[175]; // @[OneHot.scala:58:35] wire out_backSel_176 = _out_backSel_T_1[176]; // @[OneHot.scala:58:35] wire out_backSel_177 = _out_backSel_T_1[177]; // @[OneHot.scala:58:35] wire out_backSel_178 = _out_backSel_T_1[178]; // @[OneHot.scala:58:35] wire out_backSel_179 = _out_backSel_T_1[179]; // @[OneHot.scala:58:35] wire out_backSel_180 = _out_backSel_T_1[180]; // @[OneHot.scala:58:35] wire out_backSel_181 = _out_backSel_T_1[181]; // @[OneHot.scala:58:35] wire out_backSel_182 = _out_backSel_T_1[182]; // @[OneHot.scala:58:35] wire out_backSel_183 = _out_backSel_T_1[183]; // @[OneHot.scala:58:35] wire out_backSel_184 = _out_backSel_T_1[184]; // @[OneHot.scala:58:35] wire out_backSel_185 = _out_backSel_T_1[185]; // @[OneHot.scala:58:35] wire out_backSel_186 = _out_backSel_T_1[186]; // @[OneHot.scala:58:35] wire out_backSel_187 = _out_backSel_T_1[187]; // @[OneHot.scala:58:35] wire out_backSel_188 = _out_backSel_T_1[188]; // @[OneHot.scala:58:35] wire out_backSel_189 = _out_backSel_T_1[189]; // @[OneHot.scala:58:35] wire out_backSel_190 = _out_backSel_T_1[190]; // @[OneHot.scala:58:35] wire out_backSel_191 = _out_backSel_T_1[191]; // @[OneHot.scala:58:35] wire out_backSel_192 = _out_backSel_T_1[192]; // @[OneHot.scala:58:35] wire out_backSel_193 = _out_backSel_T_1[193]; // @[OneHot.scala:58:35] wire out_backSel_194 = _out_backSel_T_1[194]; // @[OneHot.scala:58:35] wire out_backSel_195 = _out_backSel_T_1[195]; // @[OneHot.scala:58:35] wire out_backSel_196 = _out_backSel_T_1[196]; // @[OneHot.scala:58:35] wire out_backSel_197 = _out_backSel_T_1[197]; // @[OneHot.scala:58:35] wire out_backSel_198 = _out_backSel_T_1[198]; // @[OneHot.scala:58:35] wire out_backSel_199 = _out_backSel_T_1[199]; // @[OneHot.scala:58:35] wire out_backSel_200 = _out_backSel_T_1[200]; // @[OneHot.scala:58:35] wire out_backSel_201 = _out_backSel_T_1[201]; // @[OneHot.scala:58:35] wire out_backSel_202 = _out_backSel_T_1[202]; // @[OneHot.scala:58:35] wire out_backSel_203 = _out_backSel_T_1[203]; // @[OneHot.scala:58:35] wire out_backSel_204 = _out_backSel_T_1[204]; // @[OneHot.scala:58:35] wire out_backSel_205 = _out_backSel_T_1[205]; // @[OneHot.scala:58:35] wire out_backSel_206 = _out_backSel_T_1[206]; // @[OneHot.scala:58:35] wire out_backSel_207 = _out_backSel_T_1[207]; // @[OneHot.scala:58:35] wire out_backSel_208 = _out_backSel_T_1[208]; // @[OneHot.scala:58:35] wire out_backSel_209 = _out_backSel_T_1[209]; // @[OneHot.scala:58:35] wire out_backSel_210 = _out_backSel_T_1[210]; // @[OneHot.scala:58:35] wire out_backSel_211 = _out_backSel_T_1[211]; // @[OneHot.scala:58:35] wire out_backSel_212 = _out_backSel_T_1[212]; // @[OneHot.scala:58:35] wire out_backSel_213 = _out_backSel_T_1[213]; // @[OneHot.scala:58:35] wire out_backSel_214 = _out_backSel_T_1[214]; // @[OneHot.scala:58:35] wire out_backSel_215 = _out_backSel_T_1[215]; // @[OneHot.scala:58:35] wire out_backSel_216 = _out_backSel_T_1[216]; // @[OneHot.scala:58:35] wire out_backSel_217 = _out_backSel_T_1[217]; // @[OneHot.scala:58:35] wire out_backSel_218 = _out_backSel_T_1[218]; // @[OneHot.scala:58:35] wire out_backSel_219 = _out_backSel_T_1[219]; // @[OneHot.scala:58:35] wire out_backSel_220 = _out_backSel_T_1[220]; // @[OneHot.scala:58:35] wire out_backSel_221 = _out_backSel_T_1[221]; // @[OneHot.scala:58:35] wire out_backSel_222 = _out_backSel_T_1[222]; // @[OneHot.scala:58:35] wire out_backSel_223 = _out_backSel_T_1[223]; // @[OneHot.scala:58:35] wire out_backSel_224 = _out_backSel_T_1[224]; // @[OneHot.scala:58:35] wire out_backSel_225 = _out_backSel_T_1[225]; // @[OneHot.scala:58:35] wire out_backSel_226 = _out_backSel_T_1[226]; // @[OneHot.scala:58:35] wire out_backSel_227 = _out_backSel_T_1[227]; // @[OneHot.scala:58:35] wire out_backSel_228 = _out_backSel_T_1[228]; // @[OneHot.scala:58:35] wire out_backSel_229 = _out_backSel_T_1[229]; // @[OneHot.scala:58:35] wire out_backSel_230 = _out_backSel_T_1[230]; // @[OneHot.scala:58:35] wire out_backSel_231 = _out_backSel_T_1[231]; // @[OneHot.scala:58:35] wire out_backSel_232 = _out_backSel_T_1[232]; // @[OneHot.scala:58:35] wire out_backSel_233 = _out_backSel_T_1[233]; // @[OneHot.scala:58:35] wire out_backSel_234 = _out_backSel_T_1[234]; // @[OneHot.scala:58:35] wire out_backSel_235 = _out_backSel_T_1[235]; // @[OneHot.scala:58:35] wire out_backSel_236 = _out_backSel_T_1[236]; // @[OneHot.scala:58:35] wire out_backSel_237 = _out_backSel_T_1[237]; // @[OneHot.scala:58:35] wire out_backSel_238 = _out_backSel_T_1[238]; // @[OneHot.scala:58:35] wire out_backSel_239 = _out_backSel_T_1[239]; // @[OneHot.scala:58:35] wire out_backSel_240 = _out_backSel_T_1[240]; // @[OneHot.scala:58:35] wire out_backSel_241 = _out_backSel_T_1[241]; // @[OneHot.scala:58:35] wire out_backSel_242 = _out_backSel_T_1[242]; // @[OneHot.scala:58:35] wire out_backSel_243 = _out_backSel_T_1[243]; // @[OneHot.scala:58:35] wire out_backSel_244 = _out_backSel_T_1[244]; // @[OneHot.scala:58:35] wire out_backSel_245 = _out_backSel_T_1[245]; // @[OneHot.scala:58:35] wire out_backSel_246 = _out_backSel_T_1[246]; // @[OneHot.scala:58:35] wire out_backSel_247 = _out_backSel_T_1[247]; // @[OneHot.scala:58:35] wire out_backSel_248 = _out_backSel_T_1[248]; // @[OneHot.scala:58:35] wire out_backSel_249 = _out_backSel_T_1[249]; // @[OneHot.scala:58:35] wire out_backSel_250 = _out_backSel_T_1[250]; // @[OneHot.scala:58:35] wire out_backSel_251 = _out_backSel_T_1[251]; // @[OneHot.scala:58:35] wire out_backSel_252 = _out_backSel_T_1[252]; // @[OneHot.scala:58:35] wire out_backSel_253 = _out_backSel_T_1[253]; // @[OneHot.scala:58:35] wire out_backSel_254 = _out_backSel_T_1[254]; // @[OneHot.scala:58:35] wire out_backSel_255 = _out_backSel_T_1[255]; // @[OneHot.scala:58:35] wire _GEN_22 = in_1_valid & out_front_1_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_259 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_260 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_260 = _out_rifireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_261 = _out_rifireMux_T_260 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_262 = _out_rifireMux_T_261 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_451 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_452 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_453 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_454 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_455 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_456 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_457 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_458 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_263 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_265 = _out_rifireMux_T_260 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_266 = _out_rifireMux_T_265 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_96 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_97 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_98 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_99 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_100 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_101 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_102 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_103 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_267 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_269 = _out_rifireMux_T_260 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_270 = _out_rifireMux_T_269 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_955 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_956 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_957 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_958 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_959 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_960 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_961 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_962 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_271 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_273 = _out_rifireMux_T_260 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_274 = _out_rifireMux_T_273 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_601 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_602 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_603 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_604 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_605 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_606 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_607 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_608 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_275 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_277 = _out_rifireMux_T_260 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_278 = _out_rifireMux_T_277 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_312 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_313 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_314 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_315 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_316 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_317 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_318 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_319 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_279 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_281 = _out_rifireMux_T_260 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_282 = _out_rifireMux_T_281 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_160 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_161 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_162 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_163 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_164 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_165 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_166 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_167 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_283 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_285 = _out_rifireMux_T_260 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_286 = _out_rifireMux_T_285 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1075 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1076 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1077 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1078 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1079 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1080 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1081 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1082 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_287 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_289 = _out_rifireMux_T_260 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_290 = _out_rifireMux_T_289 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_859 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_860 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_861 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_862 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_863 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_864 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_865 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_866 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_291 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_293 = _out_rifireMux_T_260 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_294 = _out_rifireMux_T_293 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_545 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_546 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_547 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_548 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_549 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_550 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_551 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_552 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_295 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_297 = _out_rifireMux_T_260 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_298 = _out_rifireMux_T_297 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_264 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_265 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_266 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_267 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_268 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_269 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_270 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_271 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_299 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_301 = _out_rifireMux_T_260 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_302 = _out_rifireMux_T_301 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_483 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_484 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_485 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_486 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_303 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_305 = _out_rifireMux_T_260 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_306 = _out_rifireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_309 = _out_rifireMux_T_260 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_310 = _out_rifireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_313 = _out_rifireMux_T_260 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_314 = _out_rifireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_317 = _out_rifireMux_T_260 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_318 = _out_rifireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_321 = _out_rifireMux_T_260 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_322 = _out_rifireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_325 = _out_rifireMux_T_260 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_326 = _out_rifireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_329 = _out_rifireMux_T_260 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_330 = _out_rifireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_333 = _out_rifireMux_T_260 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_334 = _out_rifireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_337 = _out_rifireMux_T_260 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_338 = _out_rifireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_341 = _out_rifireMux_T_260 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_342 = _out_rifireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_345 = _out_rifireMux_T_260 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_346 = _out_rifireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_349 = _out_rifireMux_T_260 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_350 = _out_rifireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_353 = _out_rifireMux_T_260 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_354 = _out_rifireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_357 = _out_rifireMux_T_260 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_358 = _out_rifireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_361 = _out_rifireMux_T_260 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_362 = _out_rifireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_365 = _out_rifireMux_T_260 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_366 = _out_rifireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_369 = _out_rifireMux_T_260 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_370 = _out_rifireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_373 = _out_rifireMux_T_260 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_374 = _out_rifireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_377 = _out_rifireMux_T_260 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_378 = _out_rifireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_381 = _out_rifireMux_T_260 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_382 = _out_rifireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_385 = _out_rifireMux_T_260 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_386 = _out_rifireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_389 = _out_rifireMux_T_260 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_390 = _out_rifireMux_T_389 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_535 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_536 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_391 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_393 = _out_rifireMux_T_260 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_394 = _out_rifireMux_T_393 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_352 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_353 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_395 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_397 = _out_rifireMux_T_260 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_398 = _out_rifireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_401 = _out_rifireMux_T_260 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_402 = _out_rifireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_405 = _out_rifireMux_T_260 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_406 = _out_rifireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_409 = _out_rifireMux_T_260 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_410 = _out_rifireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_413 = _out_rifireMux_T_260 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_414 = _out_rifireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_417 = _out_rifireMux_T_260 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_418 = _out_rifireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_421 = _out_rifireMux_T_260 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_422 = _out_rifireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_425 = _out_rifireMux_T_260 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_426 = _out_rifireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_429 = _out_rifireMux_T_260 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_430 = _out_rifireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_433 = _out_rifireMux_T_260 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_434 = _out_rifireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_437 = _out_rifireMux_T_260 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_438 = _out_rifireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_441 = _out_rifireMux_T_260 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_442 = _out_rifireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_445 = _out_rifireMux_T_260 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_446 = _out_rifireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_449 = _out_rifireMux_T_260 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_450 = _out_rifireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_453 = _out_rifireMux_T_260 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_454 = _out_rifireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_457 = _out_rifireMux_T_260 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_458 = _out_rifireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_461 = _out_rifireMux_T_260 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_462 = _out_rifireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_465 = _out_rifireMux_T_260 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_466 = _out_rifireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_469 = _out_rifireMux_T_260 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_470 = _out_rifireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_473 = _out_rifireMux_T_260 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_474 = _out_rifireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_477 = _out_rifireMux_T_260 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_478 = _out_rifireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_481 = _out_rifireMux_T_260 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_482 = _out_rifireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_485 = _out_rifireMux_T_260 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_486 = _out_rifireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_489 = _out_rifireMux_T_260 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_490 = _out_rifireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_493 = _out_rifireMux_T_260 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_494 = _out_rifireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_497 = _out_rifireMux_T_260 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_498 = _out_rifireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_501 = _out_rifireMux_T_260 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_502 = _out_rifireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_505 = _out_rifireMux_T_260 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_506 = _out_rifireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_509 = _out_rifireMux_T_260 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_510 = _out_rifireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_513 = _out_rifireMux_T_260 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_514 = _out_rifireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_517 = _out_rifireMux_T_260 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_518 = _out_rifireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_521 = _out_rifireMux_T_260 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_522 = _out_rifireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_525 = _out_rifireMux_T_260 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_526 = _out_rifireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_529 = _out_rifireMux_T_260 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_530 = _out_rifireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_533 = _out_rifireMux_T_260 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_534 = _out_rifireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_537 = _out_rifireMux_T_260 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_538 = _out_rifireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_541 = _out_rifireMux_T_260 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_542 = _out_rifireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_545 = _out_rifireMux_T_260 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_546 = _out_rifireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_549 = _out_rifireMux_T_260 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_550 = _out_rifireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_553 = _out_rifireMux_T_260 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_554 = _out_rifireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_557 = _out_rifireMux_T_260 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_558 = _out_rifireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_561 = _out_rifireMux_T_260 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_562 = _out_rifireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_565 = _out_rifireMux_T_260 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_566 = _out_rifireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_569 = _out_rifireMux_T_260 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_570 = _out_rifireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_573 = _out_rifireMux_T_260 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_574 = _out_rifireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_577 = _out_rifireMux_T_260 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_578 = _out_rifireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_581 = _out_rifireMux_T_260 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_582 = _out_rifireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_585 = _out_rifireMux_T_260 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_586 = _out_rifireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_589 = _out_rifireMux_T_260 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_590 = _out_rifireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_593 = _out_rifireMux_T_260 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_594 = _out_rifireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_597 = _out_rifireMux_T_260 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_598 = _out_rifireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_601 = _out_rifireMux_T_260 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_602 = _out_rifireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_605 = _out_rifireMux_T_260 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_606 = _out_rifireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_609 = _out_rifireMux_T_260 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_610 = _out_rifireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_613 = _out_rifireMux_T_260 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_614 = _out_rifireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_617 = _out_rifireMux_T_260 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_618 = _out_rifireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_621 = _out_rifireMux_T_260 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_622 = _out_rifireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_625 = _out_rifireMux_T_260 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_626 = _out_rifireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_629 = _out_rifireMux_T_260 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_630 = _out_rifireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_633 = _out_rifireMux_T_260 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_634 = _out_rifireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_637 = _out_rifireMux_T_260 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_638 = _out_rifireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_641 = _out_rifireMux_T_260 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_642 = _out_rifireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_645 = _out_rifireMux_T_260 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_646 = _out_rifireMux_T_645 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_442 = _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_647 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_649 = _out_rifireMux_T_260 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_650 = _out_rifireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_653 = _out_rifireMux_T_260 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_654 = _out_rifireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_657 = _out_rifireMux_T_260 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_658 = _out_rifireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_661 = _out_rifireMux_T_260 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_662 = _out_rifireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_665 = _out_rifireMux_T_260 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_666 = _out_rifireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_669 = _out_rifireMux_T_260 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_670 = _out_rifireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_673 = _out_rifireMux_T_260 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_674 = _out_rifireMux_T_673 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_697 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_698 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_675 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_677 = _out_rifireMux_T_260 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_678 = _out_rifireMux_T_677 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_931 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_932 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_933 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_934 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_935 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_936 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_937 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_938 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_679 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_681 = _out_rifireMux_T_260 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_682 = _out_rifireMux_T_681 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_511 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_512 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_513 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_514 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_515 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_516 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_517 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_518 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_683 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_685 = _out_rifireMux_T_260 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_686 = _out_rifireMux_T_685 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_192 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_193 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_194 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_195 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_196 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_197 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_198 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_199 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_687 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_689 = _out_rifireMux_T_260 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_690 = _out_rifireMux_T_689 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1091 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1092 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1093 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1094 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1095 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1096 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1097 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1098 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_691 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_693 = _out_rifireMux_T_260 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_694 = _out_rifireMux_T_693 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_731 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_732 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_733 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_734 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_735 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_736 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_737 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_738 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_695 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_697 = _out_rifireMux_T_260 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_698 = _out_rifireMux_T_697 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_443 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_444 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_445 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_446 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_447 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_448 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_449 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_450 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_699 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_701 = _out_rifireMux_T_260 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_702 = _out_rifireMux_T_701 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_112 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_113 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_114 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_115 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_116 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_117 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_118 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_119 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_703 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_705 = _out_rifireMux_T_260 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_706 = _out_rifireMux_T_705 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1163 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1164 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1165 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1166 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1167 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1168 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1169 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1170 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_707 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_709 = _out_rifireMux_T_260 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_710 = _out_rifireMux_T_709 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_827 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_828 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_829 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_830 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_831 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_832 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_833 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_834 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_711 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_713 = _out_rifireMux_T_260 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_714 = _out_rifireMux_T_713 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_657 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_658 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_659 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_660 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_661 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_662 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_663 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_664 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_715 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_717 = _out_rifireMux_T_260 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_718 = _out_rifireMux_T_717 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_979 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_980 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_981 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_982 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_983 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_984 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_985 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_986 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_719 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_721 = _out_rifireMux_T_260 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_722 = _out_rifireMux_T_721 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_32 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_33 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_34 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_35 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_36 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_37 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_38 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_39 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_723 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_725 = _out_rifireMux_T_260 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_726 = _out_rifireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_729 = _out_rifireMux_T_260 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_730 = _out_rifireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_733 = _out_rifireMux_T_260 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_734 = _out_rifireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_737 = _out_rifireMux_T_260 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_738 = _out_rifireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_741 = _out_rifireMux_T_260 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_742 = _out_rifireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_745 = _out_rifireMux_T_260 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_746 = _out_rifireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_749 = _out_rifireMux_T_260 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_750 = _out_rifireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_753 = _out_rifireMux_T_260 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_754 = _out_rifireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_757 = _out_rifireMux_T_260 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_758 = _out_rifireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_761 = _out_rifireMux_T_260 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_762 = _out_rifireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_765 = _out_rifireMux_T_260 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_766 = _out_rifireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_769 = _out_rifireMux_T_260 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_770 = _out_rifireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_773 = _out_rifireMux_T_260 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_774 = _out_rifireMux_T_773 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_495 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_496 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_497 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_498 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_499 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_500 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_501 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_502 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_775 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_777 = _out_rifireMux_T_260 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_778 = _out_rifireMux_T_777 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_467 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_468 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_469 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_470 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_471 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_472 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_473 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_474 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_779 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_781 = _out_rifireMux_T_260 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_782 = _out_rifireMux_T_781 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_755 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_756 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_757 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_758 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_759 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_760 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_761 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_762 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_783 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_785 = _out_rifireMux_T_260 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_786 = _out_rifireMux_T_785 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1131 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1132 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1133 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1134 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1135 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1136 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1137 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1138 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_787 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_789 = _out_rifireMux_T_260 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_790 = _out_rifireMux_T_789 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_240 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_241 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_242 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_243 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_244 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_245 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_246 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_247 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_791 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_793 = _out_rifireMux_T_260 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_794 = _out_rifireMux_T_793 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_248 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_249 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_250 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_251 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_252 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_253 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_254 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_255 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_795 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_797 = _out_rifireMux_T_260 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_798 = _out_rifireMux_T_797 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_475 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_476 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_477 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_478 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_479 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_480 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_481 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_482 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_799 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_801 = _out_rifireMux_T_260 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_802 = _out_rifireMux_T_801 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_771 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_772 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_773 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_774 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_775 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_776 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_777 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_778 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_803 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_805 = _out_rifireMux_T_260 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_806 = _out_rifireMux_T_805 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1099 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1100 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1101 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1102 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1103 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1104 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1105 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1106 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_807 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_809 = _out_rifireMux_T_260 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_810 = _out_rifireMux_T_809 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_336 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_337 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_338 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_339 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_340 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_341 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_342 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_343 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_811 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_813 = _out_rifireMux_T_260 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_814 = _out_rifireMux_T_813 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_0 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_2 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_3 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_4 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_5 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_6 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_7 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_815 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_817 = _out_rifireMux_T_260 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_818 = _out_rifireMux_T_817 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_995 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_996 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_997 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_998 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_999 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1000 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1001 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1002 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_819 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_821 = _out_rifireMux_T_260 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_822 = _out_rifireMux_T_821 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_699 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_700 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_701 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_702 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_703 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_704 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_705 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_706 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_823 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_825 = _out_rifireMux_T_260 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_826 = _out_rifireMux_T_825 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_410 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_411 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_412 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_413 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_414 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_415 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_416 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_417 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_827 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_829 = _out_rifireMux_T_260 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_830 = _out_rifireMux_T_829 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_64 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_65 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_66 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_67 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_68 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_69 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_70 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_71 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_831 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_833 = _out_rifireMux_T_260 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_834 = _out_rifireMux_T_833 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_907 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_908 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_909 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_910 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_911 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_912 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_913 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_914 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_835 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_837 = _out_rifireMux_T_260 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_838 = _out_rifireMux_T_837 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_609 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_610 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_611 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_612 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_613 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_614 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_615 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_616 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_839 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_841 = _out_rifireMux_T_260 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_842 = _out_rifireMux_T_841 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_843 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_844 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_845 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_846 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_847 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_848 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_849 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_850 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_843 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_845 = _out_rifireMux_T_260 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_846 = _out_rifireMux_T_845 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1043 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1044 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1045 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1046 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1047 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1048 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1049 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1050 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_847 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_849 = _out_rifireMux_T_260 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_850 = _out_rifireMux_T_849 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_224 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_225 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_226 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_227 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_228 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_229 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_230 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_231 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_851 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_853 = _out_rifireMux_T_260 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_854 = _out_rifireMux_T_853 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_537 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_538 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_539 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_540 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_541 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_542 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_543 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_544 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_855 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_857 = _out_rifireMux_T_260 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_858 = _out_rifireMux_T_857 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_569 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_570 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_571 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_572 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_573 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_574 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_575 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_576 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_859 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_861 = _out_rifireMux_T_260 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_862 = _out_rifireMux_T_861 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_851 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_852 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_853 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_854 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_855 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_856 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_857 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_858 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_863 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_865 = _out_rifireMux_T_260 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_866 = _out_rifireMux_T_865 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1035 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1036 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1037 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1038 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1039 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1040 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1041 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1042 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_867 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_869 = _out_rifireMux_T_260 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_870 = _out_rifireMux_T_869 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_144 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_145 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_146 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_147 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_148 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_149 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_150 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_151 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_871 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_873 = _out_rifireMux_T_260 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_874 = _out_rifireMux_T_873 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_72 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_73 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_74 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_75 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_76 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_77 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_78 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_79 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_875 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_877 = _out_rifireMux_T_260 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_878 = _out_rifireMux_T_877 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_891 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_892 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_893 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_894 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_895 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_896 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_897 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_898 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_879 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_881 = _out_rifireMux_T_260 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_882 = _out_rifireMux_T_881 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_715 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_716 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_717 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_718 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_719 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_720 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_721 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_722 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_883 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_885 = _out_rifireMux_T_260 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_886 = _out_rifireMux_T_885 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_386 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_387 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_388 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_389 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_390 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_391 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_392 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_393 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_887 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_889 = _out_rifireMux_T_260 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_890 = _out_rifireMux_T_889 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_128 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_129 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_130 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_131 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_132 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_133 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_134 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_135 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_891 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_893 = _out_rifireMux_T_260 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_894 = _out_rifireMux_T_893 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_963 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_964 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_965 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_966 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_967 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_968 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_969 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_970 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_895 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_897 = _out_rifireMux_T_260 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_898 = _out_rifireMux_T_897 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_633 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_634 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_635 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_636 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_637 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_638 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_639 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_640 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_899 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_901 = _out_rifireMux_T_260 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_902 = _out_rifireMux_T_901 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_320 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_321 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_322 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_323 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_324 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_325 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_326 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_327 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_903 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_905 = _out_rifireMux_T_260 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_906 = _out_rifireMux_T_905 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_553 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_554 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_555 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_556 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_557 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_558 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_559 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_560 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_907 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_909 = _out_rifireMux_T_260 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_910 = _out_rifireMux_T_909 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_803 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_804 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_805 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_806 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_807 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_808 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_809 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_810 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_911 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_913 = _out_rifireMux_T_260 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_914 = _out_rifireMux_T_913 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1147 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1148 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1149 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1150 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1151 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1152 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1153 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1154 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_915 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_917 = _out_rifireMux_T_260 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_918 = _out_rifireMux_T_917 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_176 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_177 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_178 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_179 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_180 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_181 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_182 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_183 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_919 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_921 = _out_rifireMux_T_260 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_922 = _out_rifireMux_T_921 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_344 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_345 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_346 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_347 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_348 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_349 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_350 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_351 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_923 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_925 = _out_rifireMux_T_260 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_926 = _out_rifireMux_T_925 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_527 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_528 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_529 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_530 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_531 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_532 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_533 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_534 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_927 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_929 = _out_rifireMux_T_260 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_930 = _out_rifireMux_T_929 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_795 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_796 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_797 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_798 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_799 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_800 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_801 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_802 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_931 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_933 = _out_rifireMux_T_260 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_934 = _out_rifireMux_T_933 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1067 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1068 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1069 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1070 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1071 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1072 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1073 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1074 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_935 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_937 = _out_rifireMux_T_260 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_938 = _out_rifireMux_T_937 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_402 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_403 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_404 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_405 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_406 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_407 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_408 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_409 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_939 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_941 = _out_rifireMux_T_260 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_942 = _out_rifireMux_T_941 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_24 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_25 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_26 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_27 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_28 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_29 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_30 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_31 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_943 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_945 = _out_rifireMux_T_260 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_946 = _out_rifireMux_T_945 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_987 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_988 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_989 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_990 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_991 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_992 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_993 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_994 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_947 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_949 = _out_rifireMux_T_260 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_950 = _out_rifireMux_T_949 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_649 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_650 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_651 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_652 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_653 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_654 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_655 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_656 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_951 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_953 = _out_rifireMux_T_260 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_954 = _out_rifireMux_T_953 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_459 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_460 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_461 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_462 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_463 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_464 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_465 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_466 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_955 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_957 = _out_rifireMux_T_260 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_958 = _out_rifireMux_T_957 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_80 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_81 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_82 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_83 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_84 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_85 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_86 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_87 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_959 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_961 = _out_rifireMux_T_260 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_962 = _out_rifireMux_T_961 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_899 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_900 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_901 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_902 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_903 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_904 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_905 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_906 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_963 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_965 = _out_rifireMux_T_260 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_966 = _out_rifireMux_T_965 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_577 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_578 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_579 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_580 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_581 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_582 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_583 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_584 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_967 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_969 = _out_rifireMux_T_260 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_970 = _out_rifireMux_T_969 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_875 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_876 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_877 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_878 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_879 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_880 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_881 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_882 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_971 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_973 = _out_rifireMux_T_260 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_974 = _out_rifireMux_T_973 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1139 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1140 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1141 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1142 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1143 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1144 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1145 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1146 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_975 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_977 = _out_rifireMux_T_260 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_978 = _out_rifireMux_T_977 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_184 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_185 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_186 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_187 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_188 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_189 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_190 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_191 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_979 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_981 = _out_rifireMux_T_260 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_982 = _out_rifireMux_T_981 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_561 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_562 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_563 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_564 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_565 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_566 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_567 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_568 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_983 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_985 = _out_rifireMux_T_260 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_986 = _out_rifireMux_T_985 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_625 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_626 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_627 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_628 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_629 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_630 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_631 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_632 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_987 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_989 = _out_rifireMux_T_260 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_990 = _out_rifireMux_T_989 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_883 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_884 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_885 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_886 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_887 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_888 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_889 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_890 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_991 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_993 = _out_rifireMux_T_260 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_994 = _out_rifireMux_T_993 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1059 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1060 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1061 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1062 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1063 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1064 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1065 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1066 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_995 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_997 = _out_rifireMux_T_260 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_998 = _out_rifireMux_T_997 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_104 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_105 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_106 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_107 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_108 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_109 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_110 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_111 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_999 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1001 = _out_rifireMux_T_260 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1002 = _out_rifireMux_T_1001 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_88 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_89 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_90 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_91 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_92 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_93 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_94 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_95 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1003 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1005 = _out_rifireMux_T_260 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1006 = _out_rifireMux_T_1005 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_971 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_972 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_973 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_974 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_975 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_976 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_977 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_978 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1007 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1009 = _out_rifireMux_T_260 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1010 = _out_rifireMux_T_1009 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_641 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_642 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_643 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_644 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_645 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_646 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_647 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_648 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1011 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1013 = _out_rifireMux_T_260 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1014 = _out_rifireMux_T_1013 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_394 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_395 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_396 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_397 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_398 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_399 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_400 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_401 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1015 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1017 = _out_rifireMux_T_260 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1018 = _out_rifireMux_T_1017 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_136 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_137 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_138 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_139 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_140 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_141 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_142 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_143 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1019 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1021 = _out_rifireMux_T_260 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1022 = _out_rifireMux_T_1021 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1051 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1052 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1053 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1054 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1055 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1056 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1057 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1058 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1023 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1025 = _out_rifireMux_T_260 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1026 = _out_rifireMux_T_1025 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_585 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_586 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_587 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_588 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_589 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_590 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_591 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_592 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1027 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1029 = _out_rifireMux_T_260 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1030 = _out_rifireMux_T_1029 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_328 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_329 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_330 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_331 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_332 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_333 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_334 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_335 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1031 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1033 = _out_rifireMux_T_260 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1034 = _out_rifireMux_T_1033 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_426 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_427 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_428 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_429 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_430 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_431 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_432 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_433 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1035 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1037 = _out_rifireMux_T_260 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1038 = _out_rifireMux_T_1037 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_835 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_836 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_837 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_838 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_839 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_840 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_841 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_842 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1039 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1041 = _out_rifireMux_T_260 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1042 = _out_rifireMux_T_1041 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1107 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1108 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1109 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1110 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1111 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1112 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1113 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1114 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1043 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1045 = _out_rifireMux_T_260 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1046 = _out_rifireMux_T_1045 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_120 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_121 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_122 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_123 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_124 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_125 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_126 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_127 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1047 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1049 = _out_rifireMux_T_260 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1050 = _out_rifireMux_T_1049 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_370 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_371 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_372 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_373 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_374 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_375 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_376 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_377 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1051 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1053 = _out_rifireMux_T_260 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1054 = _out_rifireMux_T_1053 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_723 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_724 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_725 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_726 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_727 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_728 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_729 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_730 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1055 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1057 = _out_rifireMux_T_260 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1058 = _out_rifireMux_T_1057 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_867 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_868 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_869 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_870 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_871 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_872 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_873 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_874 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1059 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1061 = _out_rifireMux_T_260 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1062 = _out_rifireMux_T_1061 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1155 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1156 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1157 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1158 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1159 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1160 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1161 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1162 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1063 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1065 = _out_rifireMux_T_260 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1066 = _out_rifireMux_T_1065 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_296 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_297 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_298 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_299 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_300 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_301 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_302 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_303 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1067 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1069 = _out_rifireMux_T_260 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1070 = _out_rifireMux_T_1069 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_56 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_57 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_58 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_59 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_60 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_61 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_62 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_63 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1071 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1073 = _out_rifireMux_T_260 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1074 = _out_rifireMux_T_1073 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_915 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_916 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_917 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_918 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_919 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_920 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_921 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_922 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1075 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1077 = _out_rifireMux_T_260 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1078 = _out_rifireMux_T_1077 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_593 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_594 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_595 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_596 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_597 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_598 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_599 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_600 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1079 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1081 = _out_rifireMux_T_260 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1082 = _out_rifireMux_T_1081 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_487 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_488 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_489 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_490 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_491 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_492 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_493 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_494 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1083 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1085 = _out_rifireMux_T_260 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1086 = _out_rifireMux_T_1085 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_272 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_273 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_274 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_275 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_276 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_277 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_278 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_279 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1087 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1089 = _out_rifireMux_T_260 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1090 = _out_rifireMux_T_1089 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1003 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1004 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1005 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1006 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1007 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1008 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1009 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1010 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1091 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1093 = _out_rifireMux_T_260 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1094 = _out_rifireMux_T_1093 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_689 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_690 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_691 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_692 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_693 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_694 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_695 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_696 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1095 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1097 = _out_rifireMux_T_260 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1098 = _out_rifireMux_T_1097 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_819 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_820 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_821 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_822 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_823 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_824 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_825 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_826 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1099 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1101 = _out_rifireMux_T_260 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1102 = _out_rifireMux_T_1101 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1083 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1084 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1085 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1086 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1087 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1088 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1089 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1090 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1103 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1105 = _out_rifireMux_T_260 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1106 = _out_rifireMux_T_1105 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_208 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_209 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_210 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_211 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_212 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_213 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_214 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_215 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1107 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1109 = _out_rifireMux_T_260 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1110 = _out_rifireMux_T_1109 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_434 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_435 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_436 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_437 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_438 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_439 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_440 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_441 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1111 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1113 = _out_rifireMux_T_260 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1114 = _out_rifireMux_T_1113 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_707 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_708 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_709 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_710 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_711 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_712 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_713 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_714 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1115 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1117 = _out_rifireMux_T_260 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1118 = _out_rifireMux_T_1117 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1011 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1012 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1013 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1014 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1015 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1016 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1017 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1018 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1119 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1121 = _out_rifireMux_T_260 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1122 = _out_rifireMux_T_1121 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1171 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1172 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1173 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1174 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1175 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1176 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1177 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1178 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1123 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1125 = _out_rifireMux_T_260 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1126 = _out_rifireMux_T_1125 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_168 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_169 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_170 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_171 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_172 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_173 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_174 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_175 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1127 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1129 = _out_rifireMux_T_260 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1130 = _out_rifireMux_T_1129 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_40 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_41 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_42 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_43 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_44 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_45 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_46 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_47 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1131 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1133 = _out_rifireMux_T_260 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1134 = _out_rifireMux_T_1133 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_923 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_924 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_925 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_926 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_927 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_928 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_929 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_930 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1135 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1137 = _out_rifireMux_T_260 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1138 = _out_rifireMux_T_1137 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_665 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_666 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_667 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_668 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_669 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_670 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_671 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_672 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1139 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1141 = _out_rifireMux_T_260 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1142 = _out_rifireMux_T_1141 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_304 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_305 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_306 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_307 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_308 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_309 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_310 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_311 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1143 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1145 = _out_rifireMux_T_260 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1146 = _out_rifireMux_T_1145 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_232 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_233 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_234 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_235 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_236 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_237 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_238 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_239 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1147 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1149 = _out_rifireMux_T_260 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1150 = _out_rifireMux_T_1149 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1179 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1180 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1181 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1182 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1183 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1184 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1185 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1186 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1151 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1153 = _out_rifireMux_T_260 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1154 = _out_rifireMux_T_1153 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_763 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_764 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_765 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_766 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_767 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_768 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_769 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_770 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1155 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1157 = _out_rifireMux_T_260 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1158 = _out_rifireMux_T_1157 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_378 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_379 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_380 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_381 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_382 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_383 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_384 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_385 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1159 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1161 = _out_rifireMux_T_260 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1162 = _out_rifireMux_T_1161 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_418 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_419 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_420 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_421 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_422 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_423 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_424 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_425 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1163 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1165 = _out_rifireMux_T_260 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1166 = _out_rifireMux_T_1165 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_779 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_780 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_781 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_782 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_783 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_784 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_785 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_786 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1167 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1169 = _out_rifireMux_T_260 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1170 = _out_rifireMux_T_1169 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1203 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1204 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1205 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1206 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1207 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1208 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1209 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1210 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1171 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1173 = _out_rifireMux_T_260 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1174 = _out_rifireMux_T_1173 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_152 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_153 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_154 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_155 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_156 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_157 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_158 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_159 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1175 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1177 = _out_rifireMux_T_260 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1178 = _out_rifireMux_T_1177 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_354 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_355 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_356 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_357 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_358 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_359 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_360 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_361 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1179 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1181 = _out_rifireMux_T_260 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1182 = _out_rifireMux_T_1181 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_673 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_674 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_675 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_676 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_677 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_678 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_679 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_680 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1183 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1185 = _out_rifireMux_T_260 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1186 = _out_rifireMux_T_1185 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_947 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_948 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_949 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_950 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_951 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_952 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_953 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_954 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1187 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1189 = _out_rifireMux_T_260 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1190 = _out_rifireMux_T_1189 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1187 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1188 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1189 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1190 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1191 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1192 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1193 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1194 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1191 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1193 = _out_rifireMux_T_260 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1194 = _out_rifireMux_T_1193 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_280 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_281 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_282 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_283 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_284 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_285 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_286 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_287 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1195 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1197 = _out_rifireMux_T_260 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1198 = _out_rifireMux_T_1197 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_16 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_17 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_18 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_19 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_20 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_21 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_22 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_23 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1199 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1201 = _out_rifireMux_T_260 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1202 = _out_rifireMux_T_1201 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1019 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1020 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1021 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1022 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1023 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1024 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1025 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1026 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1203 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1205 = _out_rifireMux_T_260 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1206 = _out_rifireMux_T_1205 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_617 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_618 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_619 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_620 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_621 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_622 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_623 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_624 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1207 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1209 = _out_rifireMux_T_260 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1210 = _out_rifireMux_T_1209 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_503 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_504 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_505 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_506 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_507 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_508 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_509 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_510 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1211 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1213 = _out_rifireMux_T_260 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1214 = _out_rifireMux_T_1213 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_200 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_201 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_202 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_203 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_204 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_205 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_206 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_207 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1215 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1217 = _out_rifireMux_T_260 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1218 = _out_rifireMux_T_1217 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1115 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1116 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1117 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1118 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1119 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1120 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1121 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1122 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1219 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1221 = _out_rifireMux_T_260 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1222 = _out_rifireMux_T_1221 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_739 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_740 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_741 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_742 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_743 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_744 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_745 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_746 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1223 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1225 = _out_rifireMux_T_260 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1226 = _out_rifireMux_T_1225 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_787 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_788 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_789 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_790 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_791 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_792 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_793 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_794 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1227 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1229 = _out_rifireMux_T_260 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1230 = _out_rifireMux_T_1229 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1123 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1124 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1125 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1126 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1127 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1128 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1129 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1130 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1231 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1233 = _out_rifireMux_T_260 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1234 = _out_rifireMux_T_1233 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_256 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_257 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_258 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_259 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_260 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_261 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_262 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_263 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1235 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1237 = _out_rifireMux_T_260 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1238 = _out_rifireMux_T_1237 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_519 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_520 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_521 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_522 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_523 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_524 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_525 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_526 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1239 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1241 = _out_rifireMux_T_260 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1242 = _out_rifireMux_T_1241 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_681 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_682 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_683 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_684 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_685 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_686 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_687 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_688 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1243 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1245 = _out_rifireMux_T_260 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1246 = _out_rifireMux_T_1245 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1027 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1028 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1029 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1030 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1031 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1032 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1033 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1034 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1247 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1249 = _out_rifireMux_T_260 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1250 = _out_rifireMux_T_1249 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_48 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_49 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_50 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_51 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_52 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_53 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_54 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_55 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1251 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1253 = _out_rifireMux_T_260 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1254 = _out_rifireMux_T_1253 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_288 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_289 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_290 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_291 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_292 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_293 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_294 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_295 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1255 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1257 = _out_rifireMux_T_260 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1258 = _out_rifireMux_T_1257 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_8 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_9 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_10 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_11 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_12 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_13 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_14 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_15 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1259 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1261 = _out_rifireMux_T_260 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1262 = _out_rifireMux_T_1261 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_939 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_940 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_941 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_942 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_943 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_944 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_945 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_946 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1263 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1265 = _out_rifireMux_T_260 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1266 = _out_rifireMux_T_1265 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_747 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_748 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_749 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_750 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_751 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_752 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_753 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_754 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1267 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1269 = _out_rifireMux_T_260 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1270 = _out_rifireMux_T_1269 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_362 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_363 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_364 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_365 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_366 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_367 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_368 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_369 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1271 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1273 = _out_rifireMux_T_260 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1274 = _out_rifireMux_T_1273 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_216 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_217 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_218 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_219 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_220 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_221 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_222 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_223 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1275 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1277 = _out_rifireMux_T_260 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1278 = _out_rifireMux_T_1277 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1195 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1196 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1197 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1198 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1199 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1200 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1201 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1202 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1279 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1281 = _out_rifireMux_T_260 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1282 = _out_rifireMux_T_1281 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_811 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_812 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_813 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_814 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_815 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_816 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_817 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_818 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1283 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_262 = _out_wifireMux_T_260 & _out_wifireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_263 = _out_wifireMux_T_262 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_264 = _out_wifireMux_T_263 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_451 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_452 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_453 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_454 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_455 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_456 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_457 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_458 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_265 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_267 = _out_wifireMux_T_262 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_268 = _out_wifireMux_T_267 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_96 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_97 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_98 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_99 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_100 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_101 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_102 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_103 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_269 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_271 = _out_wifireMux_T_262 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_272 = _out_wifireMux_T_271 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_955 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_956 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_957 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_958 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_959 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_960 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_961 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_962 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_273 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_275 = _out_wifireMux_T_262 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_276 = _out_wifireMux_T_275 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_601 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_602 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_603 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_604 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_605 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_606 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_607 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_608 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_277 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_279 = _out_wifireMux_T_262 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_280 = _out_wifireMux_T_279 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_312 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_313 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_314 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_315 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_316 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_317 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_318 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_319 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_281 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_283 = _out_wifireMux_T_262 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_284 = _out_wifireMux_T_283 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_160 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_161 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_162 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_163 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_164 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_165 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_166 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_167 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_285 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_287 = _out_wifireMux_T_262 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_288 = _out_wifireMux_T_287 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1075 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1076 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1077 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1078 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1079 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1080 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1081 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1082 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_289 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_291 = _out_wifireMux_T_262 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_292 = _out_wifireMux_T_291 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_859 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_860 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_861 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_862 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_863 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_864 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_865 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_866 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_293 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_295 = _out_wifireMux_T_262 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_296 = _out_wifireMux_T_295 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_545 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_546 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_547 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_548 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_549 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_550 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_551 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_552 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_297 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_299 = _out_wifireMux_T_262 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_300 = _out_wifireMux_T_299 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_264 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_265 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_266 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_267 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_268 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_269 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_270 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_271 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_301 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_303 = _out_wifireMux_T_262 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_304 = _out_wifireMux_T_303 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_483 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_484 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_485 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_486 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_305 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_307 = _out_wifireMux_T_262 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_308 = _out_wifireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_311 = _out_wifireMux_T_262 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_312 = _out_wifireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_315 = _out_wifireMux_T_262 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_316 = _out_wifireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_319 = _out_wifireMux_T_262 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_320 = _out_wifireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_323 = _out_wifireMux_T_262 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_324 = _out_wifireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_327 = _out_wifireMux_T_262 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_328 = _out_wifireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_331 = _out_wifireMux_T_262 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_332 = _out_wifireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_335 = _out_wifireMux_T_262 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_336 = _out_wifireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_339 = _out_wifireMux_T_262 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_340 = _out_wifireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_343 = _out_wifireMux_T_262 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_344 = _out_wifireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_347 = _out_wifireMux_T_262 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_348 = _out_wifireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_351 = _out_wifireMux_T_262 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_352 = _out_wifireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_355 = _out_wifireMux_T_262 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_356 = _out_wifireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_359 = _out_wifireMux_T_262 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_360 = _out_wifireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_363 = _out_wifireMux_T_262 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_364 = _out_wifireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_367 = _out_wifireMux_T_262 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_368 = _out_wifireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_371 = _out_wifireMux_T_262 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_372 = _out_wifireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_375 = _out_wifireMux_T_262 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_376 = _out_wifireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_379 = _out_wifireMux_T_262 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_380 = _out_wifireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_383 = _out_wifireMux_T_262 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_384 = _out_wifireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_387 = _out_wifireMux_T_262 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_388 = _out_wifireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_391 = _out_wifireMux_T_262 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_392 = _out_wifireMux_T_391 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_535 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_536 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_393 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_395 = _out_wifireMux_T_262 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_396 = _out_wifireMux_T_395 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_352 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_353 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_397 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_399 = _out_wifireMux_T_262 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_400 = _out_wifireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_403 = _out_wifireMux_T_262 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_404 = _out_wifireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_407 = _out_wifireMux_T_262 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_408 = _out_wifireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_411 = _out_wifireMux_T_262 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_412 = _out_wifireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_415 = _out_wifireMux_T_262 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_416 = _out_wifireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_419 = _out_wifireMux_T_262 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_420 = _out_wifireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_423 = _out_wifireMux_T_262 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_424 = _out_wifireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_427 = _out_wifireMux_T_262 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_428 = _out_wifireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_431 = _out_wifireMux_T_262 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_432 = _out_wifireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_435 = _out_wifireMux_T_262 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_436 = _out_wifireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_439 = _out_wifireMux_T_262 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_440 = _out_wifireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_443 = _out_wifireMux_T_262 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_444 = _out_wifireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_447 = _out_wifireMux_T_262 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_448 = _out_wifireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_451 = _out_wifireMux_T_262 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_452 = _out_wifireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_455 = _out_wifireMux_T_262 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_456 = _out_wifireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_459 = _out_wifireMux_T_262 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_460 = _out_wifireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_463 = _out_wifireMux_T_262 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_464 = _out_wifireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_467 = _out_wifireMux_T_262 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_468 = _out_wifireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_471 = _out_wifireMux_T_262 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_472 = _out_wifireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_475 = _out_wifireMux_T_262 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_476 = _out_wifireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_479 = _out_wifireMux_T_262 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_480 = _out_wifireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_483 = _out_wifireMux_T_262 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_484 = _out_wifireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_487 = _out_wifireMux_T_262 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_488 = _out_wifireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_491 = _out_wifireMux_T_262 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_492 = _out_wifireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_495 = _out_wifireMux_T_262 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_496 = _out_wifireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_499 = _out_wifireMux_T_262 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_500 = _out_wifireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_503 = _out_wifireMux_T_262 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_504 = _out_wifireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_507 = _out_wifireMux_T_262 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_508 = _out_wifireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_511 = _out_wifireMux_T_262 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_512 = _out_wifireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_515 = _out_wifireMux_T_262 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_516 = _out_wifireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_519 = _out_wifireMux_T_262 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_520 = _out_wifireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_523 = _out_wifireMux_T_262 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_524 = _out_wifireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_527 = _out_wifireMux_T_262 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_528 = _out_wifireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_531 = _out_wifireMux_T_262 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_532 = _out_wifireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_535 = _out_wifireMux_T_262 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_536 = _out_wifireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_539 = _out_wifireMux_T_262 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_540 = _out_wifireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_543 = _out_wifireMux_T_262 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_544 = _out_wifireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_547 = _out_wifireMux_T_262 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_548 = _out_wifireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_551 = _out_wifireMux_T_262 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_552 = _out_wifireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_555 = _out_wifireMux_T_262 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_556 = _out_wifireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_559 = _out_wifireMux_T_262 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_560 = _out_wifireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_563 = _out_wifireMux_T_262 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_564 = _out_wifireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_567 = _out_wifireMux_T_262 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_568 = _out_wifireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_571 = _out_wifireMux_T_262 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_572 = _out_wifireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_575 = _out_wifireMux_T_262 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_576 = _out_wifireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_579 = _out_wifireMux_T_262 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_580 = _out_wifireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_583 = _out_wifireMux_T_262 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_584 = _out_wifireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_587 = _out_wifireMux_T_262 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_588 = _out_wifireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_591 = _out_wifireMux_T_262 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_592 = _out_wifireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_595 = _out_wifireMux_T_262 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_596 = _out_wifireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_599 = _out_wifireMux_T_262 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_600 = _out_wifireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_603 = _out_wifireMux_T_262 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_604 = _out_wifireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_607 = _out_wifireMux_T_262 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_608 = _out_wifireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_611 = _out_wifireMux_T_262 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_612 = _out_wifireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_615 = _out_wifireMux_T_262 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_616 = _out_wifireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_619 = _out_wifireMux_T_262 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_620 = _out_wifireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_623 = _out_wifireMux_T_262 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_624 = _out_wifireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_627 = _out_wifireMux_T_262 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_628 = _out_wifireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_631 = _out_wifireMux_T_262 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_632 = _out_wifireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_635 = _out_wifireMux_T_262 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_636 = _out_wifireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_639 = _out_wifireMux_T_262 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_640 = _out_wifireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_643 = _out_wifireMux_T_262 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_644 = _out_wifireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_647 = _out_wifireMux_T_262 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_648 = _out_wifireMux_T_647 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_442 = _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_649 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_651 = _out_wifireMux_T_262 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_652 = _out_wifireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_655 = _out_wifireMux_T_262 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_656 = _out_wifireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_659 = _out_wifireMux_T_262 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_660 = _out_wifireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_663 = _out_wifireMux_T_262 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_664 = _out_wifireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_667 = _out_wifireMux_T_262 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_668 = _out_wifireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_671 = _out_wifireMux_T_262 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_672 = _out_wifireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_675 = _out_wifireMux_T_262 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_676 = _out_wifireMux_T_675 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_697 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_698 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_677 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_679 = _out_wifireMux_T_262 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_680 = _out_wifireMux_T_679 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_931 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_932 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_933 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_934 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_935 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_936 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_937 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_938 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_681 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_683 = _out_wifireMux_T_262 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_684 = _out_wifireMux_T_683 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_511 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_512 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_513 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_514 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_515 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_516 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_517 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_518 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_685 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_687 = _out_wifireMux_T_262 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_688 = _out_wifireMux_T_687 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_192 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_193 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_194 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_195 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_196 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_197 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_198 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_199 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_689 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_691 = _out_wifireMux_T_262 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_692 = _out_wifireMux_T_691 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1091 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1092 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1093 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1094 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1095 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1096 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1097 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1098 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_693 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_695 = _out_wifireMux_T_262 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_696 = _out_wifireMux_T_695 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_731 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_732 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_733 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_734 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_735 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_736 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_737 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_738 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_697 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_699 = _out_wifireMux_T_262 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_700 = _out_wifireMux_T_699 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_443 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_444 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_445 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_446 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_447 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_448 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_449 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_450 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_701 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_703 = _out_wifireMux_T_262 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_704 = _out_wifireMux_T_703 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_112 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_113 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_114 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_115 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_116 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_117 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_118 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_119 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_705 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_707 = _out_wifireMux_T_262 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_708 = _out_wifireMux_T_707 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1163 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1164 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1165 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1166 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1167 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1168 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1169 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1170 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_709 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_711 = _out_wifireMux_T_262 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_712 = _out_wifireMux_T_711 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_827 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_828 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_829 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_830 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_831 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_832 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_833 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_834 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_713 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_715 = _out_wifireMux_T_262 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_716 = _out_wifireMux_T_715 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_657 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_658 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_659 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_660 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_661 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_662 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_663 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_664 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_717 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_719 = _out_wifireMux_T_262 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_720 = _out_wifireMux_T_719 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_979 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_980 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_981 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_982 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_983 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_984 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_985 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_986 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_721 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_723 = _out_wifireMux_T_262 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_724 = _out_wifireMux_T_723 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_32 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_33 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_34 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_35 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_36 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_37 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_38 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_39 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_725 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_727 = _out_wifireMux_T_262 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_728 = _out_wifireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_731 = _out_wifireMux_T_262 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_732 = _out_wifireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_735 = _out_wifireMux_T_262 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_736 = _out_wifireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_739 = _out_wifireMux_T_262 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_740 = _out_wifireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_743 = _out_wifireMux_T_262 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_744 = _out_wifireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_747 = _out_wifireMux_T_262 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_748 = _out_wifireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_751 = _out_wifireMux_T_262 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_752 = _out_wifireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_755 = _out_wifireMux_T_262 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_756 = _out_wifireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_759 = _out_wifireMux_T_262 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_760 = _out_wifireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_763 = _out_wifireMux_T_262 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_764 = _out_wifireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_767 = _out_wifireMux_T_262 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_768 = _out_wifireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_771 = _out_wifireMux_T_262 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_772 = _out_wifireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_775 = _out_wifireMux_T_262 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_776 = _out_wifireMux_T_775 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_495 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_496 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_497 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_498 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_499 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_500 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_501 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_502 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_777 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_779 = _out_wifireMux_T_262 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_780 = _out_wifireMux_T_779 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_467 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_468 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_469 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_470 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_471 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_472 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_473 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_474 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_781 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_783 = _out_wifireMux_T_262 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_784 = _out_wifireMux_T_783 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_755 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_756 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_757 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_758 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_759 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_760 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_761 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_762 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_785 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_787 = _out_wifireMux_T_262 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_788 = _out_wifireMux_T_787 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1131 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1132 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1133 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1134 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1135 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1136 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1137 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1138 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_789 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_791 = _out_wifireMux_T_262 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_792 = _out_wifireMux_T_791 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_240 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_241 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_242 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_243 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_244 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_245 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_246 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_247 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_793 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_795 = _out_wifireMux_T_262 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_796 = _out_wifireMux_T_795 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_248 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_249 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_250 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_251 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_252 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_253 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_254 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_255 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_797 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_799 = _out_wifireMux_T_262 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_800 = _out_wifireMux_T_799 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_475 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_476 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_477 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_478 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_479 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_480 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_481 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_482 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_801 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_803 = _out_wifireMux_T_262 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_804 = _out_wifireMux_T_803 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_771 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_772 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_773 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_774 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_775 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_776 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_777 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_778 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_805 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_807 = _out_wifireMux_T_262 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_808 = _out_wifireMux_T_807 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1099 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1100 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1101 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1102 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1103 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1104 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1105 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1106 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_809 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_811 = _out_wifireMux_T_262 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_812 = _out_wifireMux_T_811 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_336 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_337 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_338 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_339 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_340 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_341 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_342 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_343 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_813 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_815 = _out_wifireMux_T_262 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_816 = _out_wifireMux_T_815 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_0 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_2 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_3 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_4 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_5 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_6 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_7 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_817 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_819 = _out_wifireMux_T_262 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_820 = _out_wifireMux_T_819 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_995 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_996 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_997 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_998 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_999 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1000 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1001 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1002 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_821 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_823 = _out_wifireMux_T_262 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_824 = _out_wifireMux_T_823 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_699 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_700 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_701 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_702 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_703 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_704 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_705 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_706 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_825 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_827 = _out_wifireMux_T_262 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_828 = _out_wifireMux_T_827 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_410 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_411 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_412 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_413 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_414 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_415 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_416 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_417 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_829 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_831 = _out_wifireMux_T_262 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_832 = _out_wifireMux_T_831 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_64 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_65 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_66 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_67 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_68 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_69 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_70 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_71 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_833 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_835 = _out_wifireMux_T_262 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_836 = _out_wifireMux_T_835 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_907 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_908 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_909 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_910 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_911 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_912 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_913 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_914 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_837 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_839 = _out_wifireMux_T_262 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_840 = _out_wifireMux_T_839 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_609 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_610 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_611 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_612 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_613 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_614 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_615 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_616 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_841 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_843 = _out_wifireMux_T_262 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_844 = _out_wifireMux_T_843 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_843 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_844 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_845 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_846 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_847 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_848 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_849 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_850 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_845 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_847 = _out_wifireMux_T_262 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_848 = _out_wifireMux_T_847 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1043 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1044 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1045 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1046 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1047 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1048 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1049 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1050 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_849 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_851 = _out_wifireMux_T_262 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_852 = _out_wifireMux_T_851 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_224 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_225 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_226 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_227 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_228 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_229 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_230 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_231 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_853 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_855 = _out_wifireMux_T_262 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_856 = _out_wifireMux_T_855 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_537 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_538 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_539 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_540 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_541 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_542 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_543 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_544 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_857 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_859 = _out_wifireMux_T_262 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_860 = _out_wifireMux_T_859 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_569 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_570 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_571 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_572 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_573 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_574 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_575 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_576 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_861 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_863 = _out_wifireMux_T_262 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_864 = _out_wifireMux_T_863 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_851 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_852 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_853 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_854 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_855 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_856 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_857 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_858 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_865 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_867 = _out_wifireMux_T_262 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_868 = _out_wifireMux_T_867 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1035 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1036 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1037 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1038 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1039 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1040 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1041 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1042 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_869 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_871 = _out_wifireMux_T_262 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_872 = _out_wifireMux_T_871 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_144 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_145 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_146 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_147 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_148 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_149 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_150 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_151 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_873 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_875 = _out_wifireMux_T_262 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_876 = _out_wifireMux_T_875 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_72 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_73 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_74 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_75 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_76 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_77 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_78 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_79 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_877 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_879 = _out_wifireMux_T_262 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_880 = _out_wifireMux_T_879 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_891 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_892 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_893 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_894 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_895 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_896 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_897 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_898 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_881 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_883 = _out_wifireMux_T_262 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_884 = _out_wifireMux_T_883 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_715 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_716 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_717 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_718 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_719 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_720 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_721 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_722 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_885 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_887 = _out_wifireMux_T_262 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_888 = _out_wifireMux_T_887 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_386 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_387 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_388 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_389 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_390 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_391 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_392 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_393 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_889 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_891 = _out_wifireMux_T_262 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_892 = _out_wifireMux_T_891 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_128 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_129 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_130 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_131 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_132 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_133 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_134 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_135 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_893 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_895 = _out_wifireMux_T_262 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_896 = _out_wifireMux_T_895 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_963 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_964 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_965 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_966 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_967 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_968 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_969 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_970 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_897 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_899 = _out_wifireMux_T_262 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_900 = _out_wifireMux_T_899 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_633 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_634 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_635 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_636 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_637 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_638 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_639 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_640 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_901 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_903 = _out_wifireMux_T_262 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_904 = _out_wifireMux_T_903 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_320 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_321 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_322 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_323 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_324 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_325 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_326 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_327 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_905 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_907 = _out_wifireMux_T_262 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_908 = _out_wifireMux_T_907 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_553 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_554 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_555 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_556 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_557 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_558 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_559 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_560 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_909 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_911 = _out_wifireMux_T_262 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_912 = _out_wifireMux_T_911 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_803 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_804 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_805 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_806 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_807 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_808 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_809 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_810 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_913 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_915 = _out_wifireMux_T_262 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_916 = _out_wifireMux_T_915 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1147 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1148 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1149 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1150 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1151 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1152 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1153 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1154 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_917 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_919 = _out_wifireMux_T_262 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_920 = _out_wifireMux_T_919 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_176 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_177 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_178 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_179 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_180 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_181 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_182 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_183 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_921 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_923 = _out_wifireMux_T_262 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_924 = _out_wifireMux_T_923 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_344 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_345 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_346 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_347 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_348 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_349 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_350 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_351 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_925 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_927 = _out_wifireMux_T_262 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_928 = _out_wifireMux_T_927 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_527 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_528 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_529 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_530 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_531 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_532 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_533 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_534 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_929 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_931 = _out_wifireMux_T_262 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_932 = _out_wifireMux_T_931 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_795 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_796 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_797 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_798 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_799 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_800 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_801 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_802 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_933 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_935 = _out_wifireMux_T_262 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_936 = _out_wifireMux_T_935 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1067 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1068 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1069 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1070 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1071 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1072 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1073 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1074 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_937 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_939 = _out_wifireMux_T_262 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_940 = _out_wifireMux_T_939 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_402 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_403 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_404 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_405 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_406 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_407 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_408 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_409 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_941 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_943 = _out_wifireMux_T_262 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_944 = _out_wifireMux_T_943 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_24 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_25 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_26 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_27 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_28 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_29 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_30 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_31 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_945 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_947 = _out_wifireMux_T_262 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_948 = _out_wifireMux_T_947 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_987 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_988 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_989 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_990 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_991 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_992 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_993 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_994 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_949 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_951 = _out_wifireMux_T_262 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_952 = _out_wifireMux_T_951 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_649 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_650 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_651 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_652 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_653 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_654 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_655 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_656 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_953 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_955 = _out_wifireMux_T_262 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_956 = _out_wifireMux_T_955 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_459 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_460 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_461 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_462 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_463 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_464 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_465 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_466 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_957 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_959 = _out_wifireMux_T_262 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_960 = _out_wifireMux_T_959 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_80 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_81 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_82 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_83 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_84 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_85 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_86 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_87 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_961 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_963 = _out_wifireMux_T_262 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_964 = _out_wifireMux_T_963 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_899 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_900 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_901 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_902 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_903 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_904 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_905 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_906 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_965 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_967 = _out_wifireMux_T_262 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_968 = _out_wifireMux_T_967 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_577 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_578 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_579 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_580 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_581 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_582 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_583 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_584 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_969 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_971 = _out_wifireMux_T_262 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_972 = _out_wifireMux_T_971 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_875 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_876 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_877 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_878 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_879 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_880 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_881 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_882 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_973 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_975 = _out_wifireMux_T_262 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_976 = _out_wifireMux_T_975 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1139 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1140 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1141 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1142 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1143 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1144 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1145 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1146 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_977 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_979 = _out_wifireMux_T_262 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_980 = _out_wifireMux_T_979 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_184 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_185 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_186 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_187 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_188 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_189 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_190 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_191 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_981 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_983 = _out_wifireMux_T_262 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_984 = _out_wifireMux_T_983 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_561 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_562 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_563 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_564 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_565 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_566 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_567 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_568 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_985 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_987 = _out_wifireMux_T_262 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_988 = _out_wifireMux_T_987 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_625 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_626 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_627 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_628 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_629 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_630 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_631 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_632 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_989 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_991 = _out_wifireMux_T_262 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_992 = _out_wifireMux_T_991 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_883 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_884 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_885 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_886 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_887 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_888 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_889 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_890 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_993 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_995 = _out_wifireMux_T_262 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_996 = _out_wifireMux_T_995 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1059 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1060 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1061 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1062 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1063 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1064 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1065 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1066 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_997 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_999 = _out_wifireMux_T_262 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1000 = _out_wifireMux_T_999 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_104 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_105 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_106 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_107 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_108 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_109 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_110 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_111 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1001 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1003 = _out_wifireMux_T_262 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1004 = _out_wifireMux_T_1003 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_88 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_89 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_90 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_91 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_92 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_93 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_94 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_95 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1005 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1007 = _out_wifireMux_T_262 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1008 = _out_wifireMux_T_1007 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_971 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_972 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_973 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_974 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_975 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_976 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_977 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_978 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1009 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1011 = _out_wifireMux_T_262 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1012 = _out_wifireMux_T_1011 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_641 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_642 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_643 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_644 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_645 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_646 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_647 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_648 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1013 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1015 = _out_wifireMux_T_262 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1016 = _out_wifireMux_T_1015 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_394 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_395 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_396 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_397 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_398 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_399 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_400 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_401 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1017 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1019 = _out_wifireMux_T_262 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1020 = _out_wifireMux_T_1019 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_136 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_137 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_138 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_139 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_140 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_141 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_142 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_143 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1021 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1023 = _out_wifireMux_T_262 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1024 = _out_wifireMux_T_1023 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1051 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1052 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1053 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1054 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1055 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1056 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1057 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1058 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1025 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1027 = _out_wifireMux_T_262 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1028 = _out_wifireMux_T_1027 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_585 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_586 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_587 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_588 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_589 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_590 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_591 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_592 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1029 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1031 = _out_wifireMux_T_262 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1032 = _out_wifireMux_T_1031 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_328 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_329 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_330 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_331 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_332 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_333 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_334 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_335 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1033 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1035 = _out_wifireMux_T_262 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1036 = _out_wifireMux_T_1035 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_426 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_427 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_428 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_429 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_430 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_431 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_432 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_433 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1037 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1039 = _out_wifireMux_T_262 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1040 = _out_wifireMux_T_1039 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_835 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_836 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_837 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_838 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_839 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_840 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_841 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_842 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1041 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1043 = _out_wifireMux_T_262 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1044 = _out_wifireMux_T_1043 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1107 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1108 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1109 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1110 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1111 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1112 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1113 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1114 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1045 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1047 = _out_wifireMux_T_262 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1048 = _out_wifireMux_T_1047 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_120 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_121 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_122 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_123 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_124 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_125 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_126 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_127 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1049 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1051 = _out_wifireMux_T_262 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1052 = _out_wifireMux_T_1051 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_370 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_371 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_372 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_373 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_374 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_375 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_376 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_377 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1053 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1055 = _out_wifireMux_T_262 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1056 = _out_wifireMux_T_1055 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_723 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_724 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_725 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_726 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_727 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_728 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_729 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_730 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1057 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1059 = _out_wifireMux_T_262 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1060 = _out_wifireMux_T_1059 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_867 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_868 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_869 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_870 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_871 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_872 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_873 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_874 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1061 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1063 = _out_wifireMux_T_262 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1064 = _out_wifireMux_T_1063 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1155 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1156 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1157 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1158 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1159 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1160 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1161 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1162 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1065 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1067 = _out_wifireMux_T_262 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1068 = _out_wifireMux_T_1067 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_296 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_297 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_298 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_299 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_300 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_301 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_302 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_303 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1069 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1071 = _out_wifireMux_T_262 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1072 = _out_wifireMux_T_1071 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_56 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_57 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_58 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_59 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_60 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_61 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_62 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_63 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1073 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1075 = _out_wifireMux_T_262 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1076 = _out_wifireMux_T_1075 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_915 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_916 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_917 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_918 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_919 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_920 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_921 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_922 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1077 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1079 = _out_wifireMux_T_262 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1080 = _out_wifireMux_T_1079 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_593 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_594 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_595 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_596 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_597 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_598 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_599 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_600 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1081 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1083 = _out_wifireMux_T_262 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1084 = _out_wifireMux_T_1083 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_487 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_488 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_489 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_490 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_491 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_492 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_493 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_494 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1085 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1087 = _out_wifireMux_T_262 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1088 = _out_wifireMux_T_1087 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_272 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_273 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_274 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_275 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_276 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_277 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_278 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_279 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1089 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1091 = _out_wifireMux_T_262 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1092 = _out_wifireMux_T_1091 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1003 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1004 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1005 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1006 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1007 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1008 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1009 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1010 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1093 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1095 = _out_wifireMux_T_262 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1096 = _out_wifireMux_T_1095 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_689 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_690 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_691 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_692 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_693 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_694 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_695 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_696 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1097 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1099 = _out_wifireMux_T_262 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1100 = _out_wifireMux_T_1099 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_819 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_820 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_821 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_822 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_823 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_824 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_825 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_826 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1101 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1103 = _out_wifireMux_T_262 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1104 = _out_wifireMux_T_1103 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1083 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1084 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1085 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1086 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1087 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1088 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1089 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1090 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1105 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1107 = _out_wifireMux_T_262 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1108 = _out_wifireMux_T_1107 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_208 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_209 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_210 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_211 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_212 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_213 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_214 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_215 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1109 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1111 = _out_wifireMux_T_262 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1112 = _out_wifireMux_T_1111 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_434 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_435 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_436 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_437 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_438 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_439 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_440 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_441 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1113 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1115 = _out_wifireMux_T_262 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1116 = _out_wifireMux_T_1115 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_707 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_708 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_709 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_710 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_711 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_712 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_713 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_714 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1117 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1119 = _out_wifireMux_T_262 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1120 = _out_wifireMux_T_1119 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1011 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1012 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1013 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1014 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1015 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1016 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1017 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1018 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1121 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1123 = _out_wifireMux_T_262 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1124 = _out_wifireMux_T_1123 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1171 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1172 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1173 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1174 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1175 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1176 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1177 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1178 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1125 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1127 = _out_wifireMux_T_262 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1128 = _out_wifireMux_T_1127 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_168 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_169 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_170 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_171 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_172 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_173 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_174 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_175 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1129 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1131 = _out_wifireMux_T_262 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1132 = _out_wifireMux_T_1131 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_40 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_41 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_42 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_43 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_44 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_45 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_46 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_47 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1133 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1135 = _out_wifireMux_T_262 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1136 = _out_wifireMux_T_1135 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_923 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_924 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_925 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_926 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_927 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_928 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_929 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_930 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1137 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1139 = _out_wifireMux_T_262 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1140 = _out_wifireMux_T_1139 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_665 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_666 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_667 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_668 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_669 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_670 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_671 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_672 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1141 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1143 = _out_wifireMux_T_262 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1144 = _out_wifireMux_T_1143 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_304 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_305 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_306 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_307 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_308 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_309 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_310 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_311 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1145 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1147 = _out_wifireMux_T_262 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1148 = _out_wifireMux_T_1147 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_232 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_233 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_234 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_235 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_236 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_237 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_238 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_239 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1149 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1151 = _out_wifireMux_T_262 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1152 = _out_wifireMux_T_1151 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1179 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1180 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1181 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1182 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1183 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1184 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1185 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1186 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1153 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1155 = _out_wifireMux_T_262 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1156 = _out_wifireMux_T_1155 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_763 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_764 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_765 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_766 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_767 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_768 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_769 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_770 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1157 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1159 = _out_wifireMux_T_262 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1160 = _out_wifireMux_T_1159 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_378 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_379 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_380 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_381 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_382 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_383 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_384 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_385 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1161 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1163 = _out_wifireMux_T_262 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1164 = _out_wifireMux_T_1163 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_418 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_419 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_420 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_421 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_422 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_423 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_424 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_425 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1165 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1167 = _out_wifireMux_T_262 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1168 = _out_wifireMux_T_1167 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_779 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_780 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_781 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_782 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_783 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_784 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_785 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_786 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1169 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1171 = _out_wifireMux_T_262 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1172 = _out_wifireMux_T_1171 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1203 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1204 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1205 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1206 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1207 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1208 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1209 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1210 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1173 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1175 = _out_wifireMux_T_262 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1176 = _out_wifireMux_T_1175 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_152 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_153 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_154 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_155 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_156 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_157 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_158 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_159 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1177 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1179 = _out_wifireMux_T_262 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1180 = _out_wifireMux_T_1179 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_354 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_355 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_356 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_357 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_358 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_359 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_360 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_361 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1181 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1183 = _out_wifireMux_T_262 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1184 = _out_wifireMux_T_1183 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_673 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_674 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_675 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_676 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_677 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_678 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_679 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_680 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1185 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1187 = _out_wifireMux_T_262 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1188 = _out_wifireMux_T_1187 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_947 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_948 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_949 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_950 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_951 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_952 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_953 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_954 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1189 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1191 = _out_wifireMux_T_262 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1192 = _out_wifireMux_T_1191 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1187 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1188 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1189 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1190 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1191 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1192 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1193 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1194 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1193 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1195 = _out_wifireMux_T_262 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1196 = _out_wifireMux_T_1195 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_280 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_281 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_282 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_283 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_284 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_285 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_286 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_287 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1197 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1199 = _out_wifireMux_T_262 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1200 = _out_wifireMux_T_1199 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_16 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_17 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_18 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_19 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_20 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_21 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_22 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_23 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1201 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1203 = _out_wifireMux_T_262 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1204 = _out_wifireMux_T_1203 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1019 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1020 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1021 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1022 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1023 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1024 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1025 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1026 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1205 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1207 = _out_wifireMux_T_262 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1208 = _out_wifireMux_T_1207 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_617 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_618 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_619 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_620 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_621 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_622 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_623 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_624 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1209 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1211 = _out_wifireMux_T_262 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1212 = _out_wifireMux_T_1211 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_503 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_504 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_505 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_506 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_507 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_508 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_509 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_510 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1213 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1215 = _out_wifireMux_T_262 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1216 = _out_wifireMux_T_1215 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_200 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_201 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_202 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_203 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_204 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_205 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_206 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_207 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1217 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1219 = _out_wifireMux_T_262 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1220 = _out_wifireMux_T_1219 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1115 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1116 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1117 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1118 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1119 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1120 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1121 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1122 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1221 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1223 = _out_wifireMux_T_262 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1224 = _out_wifireMux_T_1223 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_739 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_740 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_741 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_742 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_743 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_744 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_745 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_746 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1225 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1227 = _out_wifireMux_T_262 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1228 = _out_wifireMux_T_1227 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_787 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_788 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_789 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_790 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_791 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_792 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_793 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_794 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1229 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1231 = _out_wifireMux_T_262 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1232 = _out_wifireMux_T_1231 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1123 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1124 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1125 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1126 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1127 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1128 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1129 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1130 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1233 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1235 = _out_wifireMux_T_262 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1236 = _out_wifireMux_T_1235 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_256 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_257 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_258 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_259 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_260 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_261 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_262 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_263 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1237 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1239 = _out_wifireMux_T_262 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1240 = _out_wifireMux_T_1239 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_519 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_520 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_521 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_522 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_523 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_524 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_525 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_526 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1241 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1243 = _out_wifireMux_T_262 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1244 = _out_wifireMux_T_1243 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_681 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_682 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_683 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_684 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_685 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_686 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_687 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_688 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1245 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1247 = _out_wifireMux_T_262 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1248 = _out_wifireMux_T_1247 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1027 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1028 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1029 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1030 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1031 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1032 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1033 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1034 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1249 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1251 = _out_wifireMux_T_262 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1252 = _out_wifireMux_T_1251 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_48 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_49 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_50 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_51 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_52 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_53 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_54 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_55 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1253 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1255 = _out_wifireMux_T_262 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1256 = _out_wifireMux_T_1255 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_288 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_289 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_290 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_291 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_292 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_293 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_294 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_295 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1257 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1259 = _out_wifireMux_T_262 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1260 = _out_wifireMux_T_1259 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_8 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_9 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_10 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_11 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_12 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_13 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_14 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_15 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1261 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1263 = _out_wifireMux_T_262 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1264 = _out_wifireMux_T_1263 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_939 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_940 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_941 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_942 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_943 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_944 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_945 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_946 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1265 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1267 = _out_wifireMux_T_262 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1268 = _out_wifireMux_T_1267 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_747 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_748 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_749 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_750 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_751 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_752 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_753 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_754 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1269 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1271 = _out_wifireMux_T_262 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1272 = _out_wifireMux_T_1271 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_362 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_363 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_364 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_365 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_366 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_367 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_368 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_369 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1273 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1275 = _out_wifireMux_T_262 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1276 = _out_wifireMux_T_1275 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_216 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_217 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_218 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_219 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_220 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_221 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_222 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_223 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1277 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1279 = _out_wifireMux_T_262 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1280 = _out_wifireMux_T_1279 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1195 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1196 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1197 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1198 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1199 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1200 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1201 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1202 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1281 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1283 = _out_wifireMux_T_262 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1284 = _out_wifireMux_T_1283 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_811 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_812 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_813 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_814 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_815 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_816 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_817 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_818 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1285 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _GEN_23 = out_front_1_valid & out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_259 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_260 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_260 = _out_rofireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_261 = _out_rofireMux_T_260 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_262 = _out_rofireMux_T_261 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_roready_1_451 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_452 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_453 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_454 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_455 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_456 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_457 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_458 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_263 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_265 = _out_rofireMux_T_260 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_266 = _out_rofireMux_T_265 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_roready_1_96 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_97 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_98 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_99 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_100 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_101 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_102 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_103 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_267 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_269 = _out_rofireMux_T_260 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_270 = _out_rofireMux_T_269 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_roready_1_955 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_956 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_957 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_958 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_959 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_960 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_961 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_962 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_271 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_273 = _out_rofireMux_T_260 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_274 = _out_rofireMux_T_273 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_roready_1_601 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_602 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_603 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_604 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_605 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_606 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_607 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_608 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_275 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_277 = _out_rofireMux_T_260 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_278 = _out_rofireMux_T_277 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_roready_1_312 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_313 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_314 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_315 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_316 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_317 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_318 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_319 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_279 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_281 = _out_rofireMux_T_260 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_282 = _out_rofireMux_T_281 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_roready_1_160 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_161 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_162 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_163 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_164 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_165 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_166 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_167 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_283 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_285 = _out_rofireMux_T_260 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_286 = _out_rofireMux_T_285 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_roready_1_1075 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1076 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1077 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1078 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1079 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1080 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1081 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1082 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_287 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_289 = _out_rofireMux_T_260 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_290 = _out_rofireMux_T_289 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_roready_1_859 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_860 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_861 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_862 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_863 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_864 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_865 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_866 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_291 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_293 = _out_rofireMux_T_260 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_294 = _out_rofireMux_T_293 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_roready_1_545 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_546 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_547 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_548 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_549 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_550 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_551 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_552 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_295 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_297 = _out_rofireMux_T_260 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_298 = _out_rofireMux_T_297 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_roready_1_264 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_265 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_266 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_267 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_268 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_269 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_270 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_271 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_299 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_301 = _out_rofireMux_T_260 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_302 = _out_rofireMux_T_301 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_roready_1_483 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_484 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_485 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_486 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_303 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_305 = _out_rofireMux_T_260 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_306 = _out_rofireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_309 = _out_rofireMux_T_260 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_310 = _out_rofireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_313 = _out_rofireMux_T_260 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_314 = _out_rofireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_317 = _out_rofireMux_T_260 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_318 = _out_rofireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_321 = _out_rofireMux_T_260 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_322 = _out_rofireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_325 = _out_rofireMux_T_260 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_326 = _out_rofireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_329 = _out_rofireMux_T_260 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_330 = _out_rofireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_333 = _out_rofireMux_T_260 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_334 = _out_rofireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_337 = _out_rofireMux_T_260 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_338 = _out_rofireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_341 = _out_rofireMux_T_260 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_342 = _out_rofireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_345 = _out_rofireMux_T_260 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_346 = _out_rofireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_349 = _out_rofireMux_T_260 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_350 = _out_rofireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_353 = _out_rofireMux_T_260 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_354 = _out_rofireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_357 = _out_rofireMux_T_260 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_358 = _out_rofireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_361 = _out_rofireMux_T_260 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_362 = _out_rofireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_365 = _out_rofireMux_T_260 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_366 = _out_rofireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_369 = _out_rofireMux_T_260 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_370 = _out_rofireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_373 = _out_rofireMux_T_260 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_374 = _out_rofireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_377 = _out_rofireMux_T_260 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_378 = _out_rofireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_381 = _out_rofireMux_T_260 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_382 = _out_rofireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_385 = _out_rofireMux_T_260 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_386 = _out_rofireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_389 = _out_rofireMux_T_260 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_390 = _out_rofireMux_T_389 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_roready_1_535 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_roready_1_536 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_391 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_393 = _out_rofireMux_T_260 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_394 = _out_rofireMux_T_393 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_roready_1_352 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_roready_1_353 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_395 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_397 = _out_rofireMux_T_260 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_398 = _out_rofireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_401 = _out_rofireMux_T_260 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_402 = _out_rofireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_405 = _out_rofireMux_T_260 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_406 = _out_rofireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_409 = _out_rofireMux_T_260 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_410 = _out_rofireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_413 = _out_rofireMux_T_260 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_414 = _out_rofireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_417 = _out_rofireMux_T_260 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_418 = _out_rofireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_421 = _out_rofireMux_T_260 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_422 = _out_rofireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_425 = _out_rofireMux_T_260 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_426 = _out_rofireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_429 = _out_rofireMux_T_260 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_430 = _out_rofireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_433 = _out_rofireMux_T_260 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_434 = _out_rofireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_437 = _out_rofireMux_T_260 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_438 = _out_rofireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_441 = _out_rofireMux_T_260 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_442 = _out_rofireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_445 = _out_rofireMux_T_260 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_446 = _out_rofireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_449 = _out_rofireMux_T_260 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_450 = _out_rofireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_453 = _out_rofireMux_T_260 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_454 = _out_rofireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_457 = _out_rofireMux_T_260 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_458 = _out_rofireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_461 = _out_rofireMux_T_260 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_462 = _out_rofireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_465 = _out_rofireMux_T_260 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_466 = _out_rofireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_469 = _out_rofireMux_T_260 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_470 = _out_rofireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_473 = _out_rofireMux_T_260 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_474 = _out_rofireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_477 = _out_rofireMux_T_260 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_478 = _out_rofireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_481 = _out_rofireMux_T_260 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_482 = _out_rofireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_485 = _out_rofireMux_T_260 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_486 = _out_rofireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_489 = _out_rofireMux_T_260 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_490 = _out_rofireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_493 = _out_rofireMux_T_260 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_494 = _out_rofireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_497 = _out_rofireMux_T_260 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_498 = _out_rofireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_501 = _out_rofireMux_T_260 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_502 = _out_rofireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_505 = _out_rofireMux_T_260 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_506 = _out_rofireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_509 = _out_rofireMux_T_260 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_510 = _out_rofireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_513 = _out_rofireMux_T_260 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_514 = _out_rofireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_517 = _out_rofireMux_T_260 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_518 = _out_rofireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_521 = _out_rofireMux_T_260 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_522 = _out_rofireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_525 = _out_rofireMux_T_260 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_526 = _out_rofireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_529 = _out_rofireMux_T_260 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_530 = _out_rofireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_533 = _out_rofireMux_T_260 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_534 = _out_rofireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_537 = _out_rofireMux_T_260 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_538 = _out_rofireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_541 = _out_rofireMux_T_260 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_542 = _out_rofireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_545 = _out_rofireMux_T_260 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_546 = _out_rofireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_549 = _out_rofireMux_T_260 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_550 = _out_rofireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_553 = _out_rofireMux_T_260 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_554 = _out_rofireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_557 = _out_rofireMux_T_260 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_558 = _out_rofireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_561 = _out_rofireMux_T_260 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_562 = _out_rofireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_565 = _out_rofireMux_T_260 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_566 = _out_rofireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_569 = _out_rofireMux_T_260 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_570 = _out_rofireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_573 = _out_rofireMux_T_260 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_574 = _out_rofireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_577 = _out_rofireMux_T_260 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_578 = _out_rofireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_581 = _out_rofireMux_T_260 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_582 = _out_rofireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_585 = _out_rofireMux_T_260 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_586 = _out_rofireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_589 = _out_rofireMux_T_260 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_590 = _out_rofireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_593 = _out_rofireMux_T_260 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_594 = _out_rofireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_597 = _out_rofireMux_T_260 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_598 = _out_rofireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_601 = _out_rofireMux_T_260 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_602 = _out_rofireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_605 = _out_rofireMux_T_260 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_606 = _out_rofireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_609 = _out_rofireMux_T_260 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_610 = _out_rofireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_613 = _out_rofireMux_T_260 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_614 = _out_rofireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_617 = _out_rofireMux_T_260 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_618 = _out_rofireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_621 = _out_rofireMux_T_260 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_622 = _out_rofireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_625 = _out_rofireMux_T_260 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_626 = _out_rofireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_629 = _out_rofireMux_T_260 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_630 = _out_rofireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_633 = _out_rofireMux_T_260 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_634 = _out_rofireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_637 = _out_rofireMux_T_260 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_638 = _out_rofireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_641 = _out_rofireMux_T_260 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_642 = _out_rofireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_645 = _out_rofireMux_T_260 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_646 = _out_rofireMux_T_645 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_roready_1_442 = _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_647 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_649 = _out_rofireMux_T_260 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_650 = _out_rofireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_653 = _out_rofireMux_T_260 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_654 = _out_rofireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_657 = _out_rofireMux_T_260 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_658 = _out_rofireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_661 = _out_rofireMux_T_260 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_662 = _out_rofireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_665 = _out_rofireMux_T_260 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_666 = _out_rofireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_669 = _out_rofireMux_T_260 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_670 = _out_rofireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_673 = _out_rofireMux_T_260 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_674 = _out_rofireMux_T_673 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_roready_1_697 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_roready_1_698 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_675 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_677 = _out_rofireMux_T_260 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_678 = _out_rofireMux_T_677 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_roready_1_931 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_932 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_933 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_934 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_935 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_936 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_937 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_938 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_679 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_681 = _out_rofireMux_T_260 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_682 = _out_rofireMux_T_681 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_roready_1_511 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_512 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_513 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_514 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_515 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_516 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_517 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_518 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_683 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_685 = _out_rofireMux_T_260 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_686 = _out_rofireMux_T_685 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_roready_1_192 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_193 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_194 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_195 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_196 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_197 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_198 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_199 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_687 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_689 = _out_rofireMux_T_260 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_690 = _out_rofireMux_T_689 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_roready_1_1091 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1092 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1093 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1094 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1095 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1096 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1097 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1098 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_691 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_693 = _out_rofireMux_T_260 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_694 = _out_rofireMux_T_693 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_roready_1_731 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_732 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_733 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_734 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_735 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_736 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_737 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_738 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_695 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_697 = _out_rofireMux_T_260 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_698 = _out_rofireMux_T_697 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_roready_1_443 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_444 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_445 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_446 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_447 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_448 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_449 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_450 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_699 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_701 = _out_rofireMux_T_260 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_702 = _out_rofireMux_T_701 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_roready_1_112 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_113 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_114 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_115 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_116 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_117 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_118 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_119 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_703 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_705 = _out_rofireMux_T_260 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_706 = _out_rofireMux_T_705 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_roready_1_1163 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1164 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1165 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1166 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1167 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1168 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1169 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1170 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_707 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_709 = _out_rofireMux_T_260 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_710 = _out_rofireMux_T_709 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_roready_1_827 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_828 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_829 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_830 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_831 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_832 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_833 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_834 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_711 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_713 = _out_rofireMux_T_260 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_714 = _out_rofireMux_T_713 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_roready_1_657 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_658 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_659 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_660 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_661 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_662 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_663 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_664 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_715 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_717 = _out_rofireMux_T_260 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_718 = _out_rofireMux_T_717 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_roready_1_979 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_980 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_981 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_982 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_983 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_984 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_985 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_986 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_719 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_721 = _out_rofireMux_T_260 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_722 = _out_rofireMux_T_721 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_roready_1_32 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_33 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_34 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_35 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_36 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_37 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_38 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_39 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_723 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_725 = _out_rofireMux_T_260 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_726 = _out_rofireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_729 = _out_rofireMux_T_260 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_730 = _out_rofireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_733 = _out_rofireMux_T_260 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_734 = _out_rofireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_737 = _out_rofireMux_T_260 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_738 = _out_rofireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_741 = _out_rofireMux_T_260 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_742 = _out_rofireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_745 = _out_rofireMux_T_260 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_746 = _out_rofireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_749 = _out_rofireMux_T_260 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_750 = _out_rofireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_753 = _out_rofireMux_T_260 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_754 = _out_rofireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_757 = _out_rofireMux_T_260 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_758 = _out_rofireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_761 = _out_rofireMux_T_260 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_762 = _out_rofireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_765 = _out_rofireMux_T_260 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_766 = _out_rofireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_769 = _out_rofireMux_T_260 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_770 = _out_rofireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_773 = _out_rofireMux_T_260 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_774 = _out_rofireMux_T_773 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_roready_1_495 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_496 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_497 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_498 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_499 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_500 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_501 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_502 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_775 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_777 = _out_rofireMux_T_260 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_778 = _out_rofireMux_T_777 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_roready_1_467 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_468 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_469 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_470 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_471 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_472 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_473 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_474 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_779 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_781 = _out_rofireMux_T_260 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_782 = _out_rofireMux_T_781 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_roready_1_755 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_756 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_757 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_758 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_759 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_760 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_761 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_762 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_783 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_785 = _out_rofireMux_T_260 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_786 = _out_rofireMux_T_785 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_roready_1_1131 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1132 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1133 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1134 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1135 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1136 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1137 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1138 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_787 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_789 = _out_rofireMux_T_260 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_790 = _out_rofireMux_T_789 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_roready_1_240 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_241 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_242 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_243 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_244 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_245 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_246 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_247 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_791 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_793 = _out_rofireMux_T_260 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_794 = _out_rofireMux_T_793 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_roready_1_248 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_249 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_250 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_251 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_252 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_253 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_254 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_255 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_795 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_797 = _out_rofireMux_T_260 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_798 = _out_rofireMux_T_797 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_roready_1_475 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_476 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_477 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_478 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_479 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_480 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_481 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_482 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_799 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_801 = _out_rofireMux_T_260 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_802 = _out_rofireMux_T_801 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_roready_1_771 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_772 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_773 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_774 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_775 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_776 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_777 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_778 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_803 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_805 = _out_rofireMux_T_260 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_806 = _out_rofireMux_T_805 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_roready_1_1099 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1100 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1101 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1102 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1103 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1104 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1105 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1106 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_807 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_809 = _out_rofireMux_T_260 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_810 = _out_rofireMux_T_809 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_roready_1_336 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_337 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_338 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_339 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_340 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_341 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_342 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_343 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_811 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_813 = _out_rofireMux_T_260 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_814 = _out_rofireMux_T_813 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_roready_1_0 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_1 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_2 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_3 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_4 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_5 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_6 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_7 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_815 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_817 = _out_rofireMux_T_260 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_818 = _out_rofireMux_T_817 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_roready_1_995 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_996 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_997 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_998 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_999 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1000 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1001 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1002 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_819 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_821 = _out_rofireMux_T_260 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_822 = _out_rofireMux_T_821 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_roready_1_699 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_700 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_701 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_702 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_703 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_704 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_705 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_706 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_823 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_825 = _out_rofireMux_T_260 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_826 = _out_rofireMux_T_825 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_roready_1_410 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_411 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_412 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_413 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_414 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_415 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_416 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_417 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_827 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_829 = _out_rofireMux_T_260 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_830 = _out_rofireMux_T_829 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_roready_1_64 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_65 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_66 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_67 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_68 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_69 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_70 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_71 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_831 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_833 = _out_rofireMux_T_260 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_834 = _out_rofireMux_T_833 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_roready_1_907 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_908 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_909 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_910 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_911 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_912 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_913 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_914 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_835 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_837 = _out_rofireMux_T_260 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_838 = _out_rofireMux_T_837 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_roready_1_609 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_610 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_611 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_612 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_613 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_614 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_615 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_616 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_839 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_841 = _out_rofireMux_T_260 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_842 = _out_rofireMux_T_841 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_roready_1_843 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_844 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_845 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_846 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_847 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_848 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_849 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_850 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_843 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_845 = _out_rofireMux_T_260 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_846 = _out_rofireMux_T_845 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_roready_1_1043 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1044 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1045 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1046 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1047 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1048 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1049 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1050 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_847 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_849 = _out_rofireMux_T_260 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_850 = _out_rofireMux_T_849 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_roready_1_224 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_225 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_226 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_227 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_228 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_229 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_230 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_231 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_851 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_853 = _out_rofireMux_T_260 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_854 = _out_rofireMux_T_853 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_roready_1_537 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_538 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_539 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_540 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_541 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_542 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_543 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_544 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_855 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_857 = _out_rofireMux_T_260 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_858 = _out_rofireMux_T_857 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_roready_1_569 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_570 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_571 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_572 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_573 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_574 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_575 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_576 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_859 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_861 = _out_rofireMux_T_260 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_862 = _out_rofireMux_T_861 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_roready_1_851 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_852 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_853 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_854 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_855 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_856 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_857 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_858 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_863 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_865 = _out_rofireMux_T_260 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_866 = _out_rofireMux_T_865 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_roready_1_1035 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1036 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1037 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1038 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1039 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1040 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1041 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1042 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_867 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_869 = _out_rofireMux_T_260 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_870 = _out_rofireMux_T_869 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_roready_1_144 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_145 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_146 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_147 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_148 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_149 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_150 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_151 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_871 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_873 = _out_rofireMux_T_260 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_874 = _out_rofireMux_T_873 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_roready_1_72 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_73 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_74 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_75 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_76 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_77 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_78 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_79 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_875 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_877 = _out_rofireMux_T_260 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_878 = _out_rofireMux_T_877 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_roready_1_891 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_892 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_893 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_894 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_895 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_896 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_897 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_898 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_879 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_881 = _out_rofireMux_T_260 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_882 = _out_rofireMux_T_881 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_roready_1_715 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_716 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_717 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_718 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_719 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_720 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_721 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_722 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_883 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_885 = _out_rofireMux_T_260 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_886 = _out_rofireMux_T_885 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_roready_1_386 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_387 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_388 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_389 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_390 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_391 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_392 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_393 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_887 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_889 = _out_rofireMux_T_260 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_890 = _out_rofireMux_T_889 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_roready_1_128 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_129 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_130 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_131 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_132 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_133 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_134 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_135 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_891 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_893 = _out_rofireMux_T_260 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_894 = _out_rofireMux_T_893 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_roready_1_963 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_964 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_965 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_966 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_967 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_968 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_969 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_970 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_895 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_897 = _out_rofireMux_T_260 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_898 = _out_rofireMux_T_897 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_roready_1_633 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_634 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_635 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_636 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_637 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_638 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_639 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_640 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_899 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_901 = _out_rofireMux_T_260 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_902 = _out_rofireMux_T_901 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_roready_1_320 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_321 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_322 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_323 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_324 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_325 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_326 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_327 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_903 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_905 = _out_rofireMux_T_260 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_906 = _out_rofireMux_T_905 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_roready_1_553 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_554 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_555 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_556 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_557 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_558 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_559 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_560 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_907 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_909 = _out_rofireMux_T_260 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_910 = _out_rofireMux_T_909 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_roready_1_803 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_804 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_805 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_806 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_807 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_808 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_809 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_810 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_911 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_913 = _out_rofireMux_T_260 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_914 = _out_rofireMux_T_913 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_roready_1_1147 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1148 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1149 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1150 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1151 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1152 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1153 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1154 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_915 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_917 = _out_rofireMux_T_260 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_918 = _out_rofireMux_T_917 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_roready_1_176 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_177 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_178 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_179 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_180 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_181 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_182 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_183 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_919 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_921 = _out_rofireMux_T_260 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_922 = _out_rofireMux_T_921 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_roready_1_344 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_345 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_346 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_347 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_348 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_349 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_350 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_351 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_923 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_925 = _out_rofireMux_T_260 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_926 = _out_rofireMux_T_925 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_roready_1_527 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_528 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_529 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_530 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_531 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_532 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_533 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_534 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_927 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_929 = _out_rofireMux_T_260 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_930 = _out_rofireMux_T_929 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_roready_1_795 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_796 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_797 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_798 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_799 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_800 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_801 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_802 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_931 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_933 = _out_rofireMux_T_260 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_934 = _out_rofireMux_T_933 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_roready_1_1067 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1068 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1069 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1070 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1071 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1072 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1073 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1074 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_935 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_937 = _out_rofireMux_T_260 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_938 = _out_rofireMux_T_937 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_roready_1_402 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_403 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_404 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_405 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_406 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_407 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_408 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_409 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_939 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_941 = _out_rofireMux_T_260 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_942 = _out_rofireMux_T_941 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_roready_1_24 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_25 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_26 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_27 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_28 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_29 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_30 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_31 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_943 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_945 = _out_rofireMux_T_260 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_946 = _out_rofireMux_T_945 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_roready_1_987 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_988 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_989 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_990 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_991 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_992 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_993 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_994 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_947 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_949 = _out_rofireMux_T_260 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_950 = _out_rofireMux_T_949 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_roready_1_649 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_650 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_651 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_652 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_653 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_654 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_655 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_656 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_951 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_953 = _out_rofireMux_T_260 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_954 = _out_rofireMux_T_953 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_roready_1_459 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_460 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_461 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_462 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_463 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_464 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_465 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_466 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_955 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_957 = _out_rofireMux_T_260 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_958 = _out_rofireMux_T_957 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_roready_1_80 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_81 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_82 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_83 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_84 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_85 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_86 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_87 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_959 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_961 = _out_rofireMux_T_260 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_962 = _out_rofireMux_T_961 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_roready_1_899 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_900 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_901 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_902 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_903 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_904 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_905 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_906 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_963 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_965 = _out_rofireMux_T_260 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_966 = _out_rofireMux_T_965 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_roready_1_577 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_578 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_579 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_580 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_581 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_582 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_583 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_584 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_967 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_969 = _out_rofireMux_T_260 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_970 = _out_rofireMux_T_969 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_roready_1_875 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_876 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_877 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_878 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_879 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_880 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_881 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_882 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_971 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_973 = _out_rofireMux_T_260 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_974 = _out_rofireMux_T_973 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_roready_1_1139 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1140 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1141 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1142 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1143 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1144 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1145 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1146 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_975 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_977 = _out_rofireMux_T_260 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_978 = _out_rofireMux_T_977 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_roready_1_184 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_185 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_186 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_187 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_188 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_189 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_190 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_191 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_979 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_981 = _out_rofireMux_T_260 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_982 = _out_rofireMux_T_981 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_roready_1_561 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_562 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_563 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_564 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_565 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_566 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_567 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_568 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_983 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_985 = _out_rofireMux_T_260 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_986 = _out_rofireMux_T_985 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_roready_1_625 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_626 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_627 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_628 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_629 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_630 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_631 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_632 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_987 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_989 = _out_rofireMux_T_260 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_990 = _out_rofireMux_T_989 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_roready_1_883 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_884 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_885 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_886 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_887 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_888 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_889 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_890 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_991 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_993 = _out_rofireMux_T_260 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_994 = _out_rofireMux_T_993 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_roready_1_1059 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1060 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1061 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1062 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1063 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1064 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1065 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1066 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_995 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_997 = _out_rofireMux_T_260 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_998 = _out_rofireMux_T_997 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_roready_1_104 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_105 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_106 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_107 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_108 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_109 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_110 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_111 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_999 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1001 = _out_rofireMux_T_260 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1002 = _out_rofireMux_T_1001 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_roready_1_88 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_89 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_90 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_91 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_92 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_93 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_94 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_95 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1003 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1005 = _out_rofireMux_T_260 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1006 = _out_rofireMux_T_1005 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_roready_1_971 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_972 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_973 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_974 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_975 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_976 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_977 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_978 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1007 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1009 = _out_rofireMux_T_260 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1010 = _out_rofireMux_T_1009 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_roready_1_641 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_642 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_643 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_644 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_645 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_646 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_647 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_648 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1011 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1013 = _out_rofireMux_T_260 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1014 = _out_rofireMux_T_1013 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_roready_1_394 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_395 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_396 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_397 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_398 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_399 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_400 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_401 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1015 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1017 = _out_rofireMux_T_260 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1018 = _out_rofireMux_T_1017 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_roready_1_136 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_137 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_138 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_139 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_140 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_141 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_142 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_143 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1019 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1021 = _out_rofireMux_T_260 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1022 = _out_rofireMux_T_1021 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_roready_1_1051 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1052 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1053 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1054 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1055 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1056 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1057 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1058 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1023 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1025 = _out_rofireMux_T_260 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1026 = _out_rofireMux_T_1025 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_roready_1_585 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_586 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_587 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_588 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_589 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_590 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_591 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_592 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1027 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1029 = _out_rofireMux_T_260 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1030 = _out_rofireMux_T_1029 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_roready_1_328 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_329 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_330 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_331 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_332 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_333 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_334 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_335 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1031 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1033 = _out_rofireMux_T_260 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1034 = _out_rofireMux_T_1033 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_roready_1_426 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_427 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_428 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_429 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_430 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_431 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_432 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_433 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1035 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1037 = _out_rofireMux_T_260 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1038 = _out_rofireMux_T_1037 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_roready_1_835 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_836 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_837 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_838 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_839 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_840 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_841 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_842 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1039 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1041 = _out_rofireMux_T_260 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1042 = _out_rofireMux_T_1041 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_roready_1_1107 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1108 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1109 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1110 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1111 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1112 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1113 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1114 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1043 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1045 = _out_rofireMux_T_260 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1046 = _out_rofireMux_T_1045 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_roready_1_120 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_121 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_122 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_123 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_124 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_125 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_126 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_127 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1047 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1049 = _out_rofireMux_T_260 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1050 = _out_rofireMux_T_1049 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_roready_1_370 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_371 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_372 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_373 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_374 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_375 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_376 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_377 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1051 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1053 = _out_rofireMux_T_260 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1054 = _out_rofireMux_T_1053 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_roready_1_723 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_724 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_725 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_726 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_727 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_728 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_729 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_730 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1055 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1057 = _out_rofireMux_T_260 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1058 = _out_rofireMux_T_1057 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_roready_1_867 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_868 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_869 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_870 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_871 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_872 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_873 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_874 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1059 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1061 = _out_rofireMux_T_260 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1062 = _out_rofireMux_T_1061 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_roready_1_1155 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1156 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1157 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1158 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1159 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1160 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1161 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1162 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1063 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1065 = _out_rofireMux_T_260 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1066 = _out_rofireMux_T_1065 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_roready_1_296 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_297 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_298 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_299 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_300 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_301 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_302 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_303 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1067 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1069 = _out_rofireMux_T_260 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1070 = _out_rofireMux_T_1069 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_roready_1_56 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_57 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_58 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_59 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_60 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_61 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_62 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_63 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1071 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1073 = _out_rofireMux_T_260 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1074 = _out_rofireMux_T_1073 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_roready_1_915 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_916 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_917 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_918 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_919 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_920 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_921 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_922 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1075 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1077 = _out_rofireMux_T_260 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1078 = _out_rofireMux_T_1077 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_roready_1_593 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_594 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_595 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_596 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_597 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_598 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_599 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_600 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1079 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1081 = _out_rofireMux_T_260 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1082 = _out_rofireMux_T_1081 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_roready_1_487 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_488 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_489 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_490 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_491 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_492 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_493 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_494 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1083 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1085 = _out_rofireMux_T_260 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1086 = _out_rofireMux_T_1085 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_roready_1_272 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_273 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_274 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_275 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_276 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_277 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_278 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_279 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1087 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1089 = _out_rofireMux_T_260 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1090 = _out_rofireMux_T_1089 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_roready_1_1003 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1004 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1005 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1006 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1007 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1008 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1009 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1010 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1091 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1093 = _out_rofireMux_T_260 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1094 = _out_rofireMux_T_1093 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_roready_1_689 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_690 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_691 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_692 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_693 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_694 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_695 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_696 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1095 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1097 = _out_rofireMux_T_260 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1098 = _out_rofireMux_T_1097 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_roready_1_819 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_820 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_821 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_822 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_823 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_824 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_825 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_826 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1099 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1101 = _out_rofireMux_T_260 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1102 = _out_rofireMux_T_1101 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_roready_1_1083 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1084 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1085 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1086 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1087 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1088 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1089 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1090 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1103 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1105 = _out_rofireMux_T_260 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1106 = _out_rofireMux_T_1105 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_roready_1_208 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_209 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_210 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_211 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_212 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_213 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_214 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_215 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1107 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1109 = _out_rofireMux_T_260 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1110 = _out_rofireMux_T_1109 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_roready_1_434 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_435 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_436 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_437 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_438 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_439 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_440 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_441 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1111 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1113 = _out_rofireMux_T_260 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1114 = _out_rofireMux_T_1113 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_roready_1_707 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_708 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_709 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_710 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_711 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_712 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_713 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_714 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1115 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1117 = _out_rofireMux_T_260 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1118 = _out_rofireMux_T_1117 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_roready_1_1011 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1012 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1013 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1014 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1015 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1016 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1017 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1018 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1119 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1121 = _out_rofireMux_T_260 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1122 = _out_rofireMux_T_1121 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_roready_1_1171 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1172 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1173 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1174 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1175 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1176 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1177 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1178 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1123 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1125 = _out_rofireMux_T_260 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1126 = _out_rofireMux_T_1125 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_roready_1_168 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_169 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_170 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_171 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_172 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_173 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_174 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_175 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1127 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1129 = _out_rofireMux_T_260 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1130 = _out_rofireMux_T_1129 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_roready_1_40 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_41 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_42 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_43 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_44 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_45 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_46 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_47 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1131 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1133 = _out_rofireMux_T_260 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1134 = _out_rofireMux_T_1133 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_roready_1_923 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_924 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_925 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_926 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_927 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_928 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_929 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_930 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1135 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1137 = _out_rofireMux_T_260 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1138 = _out_rofireMux_T_1137 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_roready_1_665 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_666 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_667 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_668 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_669 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_670 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_671 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_672 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1139 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1141 = _out_rofireMux_T_260 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1142 = _out_rofireMux_T_1141 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_roready_1_304 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_305 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_306 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_307 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_308 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_309 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_310 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_311 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1143 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1145 = _out_rofireMux_T_260 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1146 = _out_rofireMux_T_1145 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_roready_1_232 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_233 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_234 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_235 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_236 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_237 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_238 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_239 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1147 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1149 = _out_rofireMux_T_260 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1150 = _out_rofireMux_T_1149 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_roready_1_1179 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1180 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1181 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1182 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1183 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1184 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1185 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1186 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1151 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1153 = _out_rofireMux_T_260 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1154 = _out_rofireMux_T_1153 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_roready_1_763 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_764 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_765 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_766 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_767 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_768 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_769 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_770 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1155 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1157 = _out_rofireMux_T_260 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1158 = _out_rofireMux_T_1157 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_roready_1_378 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_379 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_380 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_381 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_382 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_383 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_384 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_385 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1159 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1161 = _out_rofireMux_T_260 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1162 = _out_rofireMux_T_1161 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_roready_1_418 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_419 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_420 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_421 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_422 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_423 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_424 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_425 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1163 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1165 = _out_rofireMux_T_260 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1166 = _out_rofireMux_T_1165 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_roready_1_779 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_780 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_781 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_782 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_783 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_784 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_785 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_786 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1167 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1169 = _out_rofireMux_T_260 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1170 = _out_rofireMux_T_1169 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_roready_1_1203 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1204 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1205 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1206 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1207 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1208 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1209 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1210 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1171 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1173 = _out_rofireMux_T_260 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1174 = _out_rofireMux_T_1173 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_roready_1_152 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_153 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_154 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_155 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_156 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_157 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_158 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_159 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1175 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1177 = _out_rofireMux_T_260 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1178 = _out_rofireMux_T_1177 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_roready_1_354 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_355 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_356 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_357 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_358 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_359 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_360 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_361 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1179 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1181 = _out_rofireMux_T_260 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1182 = _out_rofireMux_T_1181 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_roready_1_673 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_674 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_675 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_676 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_677 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_678 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_679 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_680 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1183 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1185 = _out_rofireMux_T_260 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1186 = _out_rofireMux_T_1185 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_roready_1_947 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_948 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_949 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_950 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_951 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_952 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_953 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_954 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1187 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1189 = _out_rofireMux_T_260 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1190 = _out_rofireMux_T_1189 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_roready_1_1187 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1188 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1189 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1190 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1191 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1192 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1193 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1194 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1191 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1193 = _out_rofireMux_T_260 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1194 = _out_rofireMux_T_1193 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_roready_1_280 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_281 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_282 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_283 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_284 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_285 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_286 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_287 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1195 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1197 = _out_rofireMux_T_260 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1198 = _out_rofireMux_T_1197 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_roready_1_16 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_17 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_18 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_19 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_20 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_21 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_22 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_23 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1199 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1201 = _out_rofireMux_T_260 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1202 = _out_rofireMux_T_1201 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_roready_1_1019 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1020 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1021 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1022 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1023 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1024 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1025 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1026 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1203 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1205 = _out_rofireMux_T_260 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1206 = _out_rofireMux_T_1205 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_roready_1_617 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_618 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_619 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_620 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_621 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_622 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_623 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_624 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1207 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1209 = _out_rofireMux_T_260 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1210 = _out_rofireMux_T_1209 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_roready_1_503 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_504 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_505 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_506 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_507 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_508 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_509 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_510 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1211 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1213 = _out_rofireMux_T_260 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1214 = _out_rofireMux_T_1213 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_roready_1_200 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_201 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_202 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_203 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_204 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_205 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_206 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_207 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1215 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1217 = _out_rofireMux_T_260 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1218 = _out_rofireMux_T_1217 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_roready_1_1115 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1116 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1117 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1118 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1119 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1120 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1121 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1122 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1219 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1221 = _out_rofireMux_T_260 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1222 = _out_rofireMux_T_1221 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_roready_1_739 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_740 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_741 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_742 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_743 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_744 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_745 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_746 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1223 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1225 = _out_rofireMux_T_260 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1226 = _out_rofireMux_T_1225 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_roready_1_787 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_788 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_789 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_790 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_791 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_792 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_793 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_794 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1227 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1229 = _out_rofireMux_T_260 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1230 = _out_rofireMux_T_1229 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_roready_1_1123 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1124 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1125 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1126 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1127 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1128 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1129 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1130 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1231 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1233 = _out_rofireMux_T_260 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1234 = _out_rofireMux_T_1233 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_roready_1_256 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_257 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_258 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_259 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_260 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_261 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_262 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_263 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1235 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1237 = _out_rofireMux_T_260 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1238 = _out_rofireMux_T_1237 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_roready_1_519 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_520 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_521 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_522 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_523 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_524 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_525 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_526 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1239 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1241 = _out_rofireMux_T_260 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1242 = _out_rofireMux_T_1241 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_roready_1_681 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_682 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_683 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_684 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_685 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_686 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_687 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_688 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1243 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1245 = _out_rofireMux_T_260 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1246 = _out_rofireMux_T_1245 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_roready_1_1027 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1028 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1029 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1030 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1031 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1032 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1033 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1034 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1247 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1249 = _out_rofireMux_T_260 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1250 = _out_rofireMux_T_1249 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_roready_1_48 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_49 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_50 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_51 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_52 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_53 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_54 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_55 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1251 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1253 = _out_rofireMux_T_260 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1254 = _out_rofireMux_T_1253 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_roready_1_288 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_289 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_290 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_291 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_292 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_293 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_294 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_295 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1255 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1257 = _out_rofireMux_T_260 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1258 = _out_rofireMux_T_1257 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_roready_1_8 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_9 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_10 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_11 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_12 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_13 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_14 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_15 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1259 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1261 = _out_rofireMux_T_260 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1262 = _out_rofireMux_T_1261 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_roready_1_939 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_940 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_941 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_942 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_943 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_944 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_945 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_946 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1263 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1265 = _out_rofireMux_T_260 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1266 = _out_rofireMux_T_1265 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_roready_1_747 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_748 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_749 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_750 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_751 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_752 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_753 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_754 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1267 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1269 = _out_rofireMux_T_260 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1270 = _out_rofireMux_T_1269 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_roready_1_362 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_363 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_364 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_365 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_366 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_367 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_368 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_369 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1271 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1273 = _out_rofireMux_T_260 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1274 = _out_rofireMux_T_1273 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_roready_1_216 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_217 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_218 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_219 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_220 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_221 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_222 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_223 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1275 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1277 = _out_rofireMux_T_260 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1278 = _out_rofireMux_T_1277 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_roready_1_1195 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1196 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1197 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1198 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1199 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1200 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1201 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1202 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1279 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1281 = _out_rofireMux_T_260 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1282 = _out_rofireMux_T_1281 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_roready_1_811 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_812 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_813 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_814 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_815 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_816 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_817 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_818 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1283 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = _out_wofireMux_T_260 & _out_wofireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_263 = _out_wofireMux_T_262 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_264 = _out_wofireMux_T_263 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_woready_1_451 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_452 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_453 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_454 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_455 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_456 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_457 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_458 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_265 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_267 = _out_wofireMux_T_262 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_268 = _out_wofireMux_T_267 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_woready_1_96 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_97 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_98 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_99 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_100 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_101 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_102 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_103 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_269 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_271 = _out_wofireMux_T_262 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_272 = _out_wofireMux_T_271 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_woready_1_955 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_956 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_957 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_958 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_959 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_960 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_961 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_962 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_273 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_275 = _out_wofireMux_T_262 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_276 = _out_wofireMux_T_275 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_woready_1_601 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_602 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_603 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_604 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_605 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_606 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_607 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_608 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_277 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_279 = _out_wofireMux_T_262 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_280 = _out_wofireMux_T_279 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_woready_1_312 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_313 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_314 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_315 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_316 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_317 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_318 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_319 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_281 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_283 = _out_wofireMux_T_262 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_284 = _out_wofireMux_T_283 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_woready_1_160 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_161 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_162 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_163 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_164 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_165 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_166 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_167 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_285 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_287 = _out_wofireMux_T_262 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_288 = _out_wofireMux_T_287 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_woready_1_1075 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1076 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1077 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1078 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1079 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1080 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1081 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1082 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_289 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_291 = _out_wofireMux_T_262 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_292 = _out_wofireMux_T_291 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_woready_1_859 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_860 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_861 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_862 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_863 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_864 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_865 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_866 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_293 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_295 = _out_wofireMux_T_262 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_296 = _out_wofireMux_T_295 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_woready_1_545 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_546 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_547 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_548 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_549 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_550 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_551 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_552 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_297 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_299 = _out_wofireMux_T_262 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_300 = _out_wofireMux_T_299 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_woready_1_264 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_265 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_266 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_267 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_268 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_269 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_270 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_271 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_301 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_303 = _out_wofireMux_T_262 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_304 = _out_wofireMux_T_303 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_woready_1_483 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_484 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_485 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_486 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_305 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_307 = _out_wofireMux_T_262 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_308 = _out_wofireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_311 = _out_wofireMux_T_262 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_312 = _out_wofireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_315 = _out_wofireMux_T_262 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_316 = _out_wofireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_319 = _out_wofireMux_T_262 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_320 = _out_wofireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_323 = _out_wofireMux_T_262 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_324 = _out_wofireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_327 = _out_wofireMux_T_262 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_328 = _out_wofireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_331 = _out_wofireMux_T_262 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_332 = _out_wofireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_335 = _out_wofireMux_T_262 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_336 = _out_wofireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_339 = _out_wofireMux_T_262 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_340 = _out_wofireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_343 = _out_wofireMux_T_262 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_344 = _out_wofireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_347 = _out_wofireMux_T_262 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_348 = _out_wofireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_351 = _out_wofireMux_T_262 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_352 = _out_wofireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_355 = _out_wofireMux_T_262 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_356 = _out_wofireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_359 = _out_wofireMux_T_262 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_360 = _out_wofireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_363 = _out_wofireMux_T_262 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_364 = _out_wofireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_367 = _out_wofireMux_T_262 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_368 = _out_wofireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_371 = _out_wofireMux_T_262 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_372 = _out_wofireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_375 = _out_wofireMux_T_262 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_376 = _out_wofireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_379 = _out_wofireMux_T_262 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_380 = _out_wofireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_383 = _out_wofireMux_T_262 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_384 = _out_wofireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_387 = _out_wofireMux_T_262 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_388 = _out_wofireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_391 = _out_wofireMux_T_262 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_392 = _out_wofireMux_T_391 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_woready_1_535 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_woready_1_536 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_393 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_395 = _out_wofireMux_T_262 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_396 = _out_wofireMux_T_395 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_woready_1_352 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_woready_1_353 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_397 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_399 = _out_wofireMux_T_262 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_400 = _out_wofireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_403 = _out_wofireMux_T_262 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_404 = _out_wofireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_407 = _out_wofireMux_T_262 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_408 = _out_wofireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_411 = _out_wofireMux_T_262 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_412 = _out_wofireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_415 = _out_wofireMux_T_262 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_416 = _out_wofireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_419 = _out_wofireMux_T_262 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_420 = _out_wofireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_423 = _out_wofireMux_T_262 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_424 = _out_wofireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_427 = _out_wofireMux_T_262 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_428 = _out_wofireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_431 = _out_wofireMux_T_262 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_432 = _out_wofireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_435 = _out_wofireMux_T_262 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_436 = _out_wofireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_439 = _out_wofireMux_T_262 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_440 = _out_wofireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_443 = _out_wofireMux_T_262 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_444 = _out_wofireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_447 = _out_wofireMux_T_262 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_448 = _out_wofireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_451 = _out_wofireMux_T_262 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_452 = _out_wofireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_455 = _out_wofireMux_T_262 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_456 = _out_wofireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_459 = _out_wofireMux_T_262 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_460 = _out_wofireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_463 = _out_wofireMux_T_262 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_464 = _out_wofireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_467 = _out_wofireMux_T_262 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_468 = _out_wofireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_471 = _out_wofireMux_T_262 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_472 = _out_wofireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_475 = _out_wofireMux_T_262 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_476 = _out_wofireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_479 = _out_wofireMux_T_262 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_480 = _out_wofireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_483 = _out_wofireMux_T_262 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_484 = _out_wofireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_487 = _out_wofireMux_T_262 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_488 = _out_wofireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_491 = _out_wofireMux_T_262 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_492 = _out_wofireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_495 = _out_wofireMux_T_262 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_496 = _out_wofireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_499 = _out_wofireMux_T_262 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_500 = _out_wofireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_503 = _out_wofireMux_T_262 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_504 = _out_wofireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_507 = _out_wofireMux_T_262 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_508 = _out_wofireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_511 = _out_wofireMux_T_262 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_512 = _out_wofireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_515 = _out_wofireMux_T_262 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_516 = _out_wofireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_519 = _out_wofireMux_T_262 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_520 = _out_wofireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_523 = _out_wofireMux_T_262 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_524 = _out_wofireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_527 = _out_wofireMux_T_262 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_528 = _out_wofireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_531 = _out_wofireMux_T_262 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_532 = _out_wofireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_535 = _out_wofireMux_T_262 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_536 = _out_wofireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_539 = _out_wofireMux_T_262 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_540 = _out_wofireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_543 = _out_wofireMux_T_262 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_544 = _out_wofireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_547 = _out_wofireMux_T_262 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_548 = _out_wofireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_551 = _out_wofireMux_T_262 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_552 = _out_wofireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_555 = _out_wofireMux_T_262 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_556 = _out_wofireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_559 = _out_wofireMux_T_262 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_560 = _out_wofireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_563 = _out_wofireMux_T_262 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_564 = _out_wofireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_567 = _out_wofireMux_T_262 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_568 = _out_wofireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_571 = _out_wofireMux_T_262 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_572 = _out_wofireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_575 = _out_wofireMux_T_262 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_576 = _out_wofireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_579 = _out_wofireMux_T_262 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_580 = _out_wofireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_583 = _out_wofireMux_T_262 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_584 = _out_wofireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_587 = _out_wofireMux_T_262 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_588 = _out_wofireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_591 = _out_wofireMux_T_262 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_592 = _out_wofireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_595 = _out_wofireMux_T_262 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_596 = _out_wofireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_599 = _out_wofireMux_T_262 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_600 = _out_wofireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_603 = _out_wofireMux_T_262 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_604 = _out_wofireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_607 = _out_wofireMux_T_262 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_608 = _out_wofireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_611 = _out_wofireMux_T_262 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_612 = _out_wofireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_615 = _out_wofireMux_T_262 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_616 = _out_wofireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_619 = _out_wofireMux_T_262 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_620 = _out_wofireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_623 = _out_wofireMux_T_262 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_624 = _out_wofireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_627 = _out_wofireMux_T_262 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_628 = _out_wofireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_631 = _out_wofireMux_T_262 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_632 = _out_wofireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_635 = _out_wofireMux_T_262 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_636 = _out_wofireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_639 = _out_wofireMux_T_262 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_640 = _out_wofireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_643 = _out_wofireMux_T_262 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_644 = _out_wofireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_647 = _out_wofireMux_T_262 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_648 = _out_wofireMux_T_647 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_woready_1_442 = _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_649 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_651 = _out_wofireMux_T_262 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_652 = _out_wofireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_655 = _out_wofireMux_T_262 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_656 = _out_wofireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_659 = _out_wofireMux_T_262 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_660 = _out_wofireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_663 = _out_wofireMux_T_262 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_664 = _out_wofireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_667 = _out_wofireMux_T_262 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_668 = _out_wofireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_671 = _out_wofireMux_T_262 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_672 = _out_wofireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_675 = _out_wofireMux_T_262 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_676 = _out_wofireMux_T_675 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_woready_1_697 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_woready_1_698 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_677 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_679 = _out_wofireMux_T_262 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_680 = _out_wofireMux_T_679 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_woready_1_931 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_932 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_933 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_934 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_935 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_936 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_937 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_938 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_681 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_683 = _out_wofireMux_T_262 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_684 = _out_wofireMux_T_683 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_woready_1_511 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_512 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_513 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_514 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_515 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_516 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_517 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_518 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_685 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_687 = _out_wofireMux_T_262 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_688 = _out_wofireMux_T_687 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_woready_1_192 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_193 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_194 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_195 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_196 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_197 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_198 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_199 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_689 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_691 = _out_wofireMux_T_262 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_692 = _out_wofireMux_T_691 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_woready_1_1091 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1092 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1093 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1094 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1095 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1096 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1097 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1098 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_693 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_695 = _out_wofireMux_T_262 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_696 = _out_wofireMux_T_695 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_woready_1_731 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_732 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_733 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_734 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_735 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_736 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_737 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_738 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_697 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_699 = _out_wofireMux_T_262 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_700 = _out_wofireMux_T_699 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_woready_1_443 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_444 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_445 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_446 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_447 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_448 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_449 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_450 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_701 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_703 = _out_wofireMux_T_262 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_704 = _out_wofireMux_T_703 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_woready_1_112 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_113 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_114 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_115 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_116 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_117 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_118 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_119 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_705 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_707 = _out_wofireMux_T_262 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_708 = _out_wofireMux_T_707 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_woready_1_1163 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1164 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1165 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1166 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1167 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1168 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1169 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1170 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_709 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_711 = _out_wofireMux_T_262 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_712 = _out_wofireMux_T_711 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_woready_1_827 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_828 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_829 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_830 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_831 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_832 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_833 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_834 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_713 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_715 = _out_wofireMux_T_262 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_716 = _out_wofireMux_T_715 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_woready_1_657 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_658 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_659 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_660 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_661 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_662 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_663 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_664 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_717 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_719 = _out_wofireMux_T_262 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_720 = _out_wofireMux_T_719 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_woready_1_979 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_980 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_981 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_982 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_983 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_984 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_985 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_986 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_721 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_723 = _out_wofireMux_T_262 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_724 = _out_wofireMux_T_723 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_woready_1_32 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_33 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_34 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_35 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_36 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_37 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_38 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_39 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_725 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_727 = _out_wofireMux_T_262 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_728 = _out_wofireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_731 = _out_wofireMux_T_262 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_732 = _out_wofireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_735 = _out_wofireMux_T_262 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_736 = _out_wofireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_739 = _out_wofireMux_T_262 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_740 = _out_wofireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_743 = _out_wofireMux_T_262 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_744 = _out_wofireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_747 = _out_wofireMux_T_262 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_748 = _out_wofireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_751 = _out_wofireMux_T_262 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_752 = _out_wofireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_755 = _out_wofireMux_T_262 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_756 = _out_wofireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_759 = _out_wofireMux_T_262 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_760 = _out_wofireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_763 = _out_wofireMux_T_262 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_764 = _out_wofireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_767 = _out_wofireMux_T_262 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_768 = _out_wofireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_771 = _out_wofireMux_T_262 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_772 = _out_wofireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_775 = _out_wofireMux_T_262 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_776 = _out_wofireMux_T_775 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_woready_1_495 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_496 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_497 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_498 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_499 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_500 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_501 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_502 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_777 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_779 = _out_wofireMux_T_262 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_780 = _out_wofireMux_T_779 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_woready_1_467 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_468 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_469 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_470 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_471 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_472 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_473 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_474 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_781 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_783 = _out_wofireMux_T_262 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_784 = _out_wofireMux_T_783 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_woready_1_755 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_756 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_757 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_758 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_759 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_760 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_761 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_762 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_785 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_787 = _out_wofireMux_T_262 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_788 = _out_wofireMux_T_787 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_woready_1_1131 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1132 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1133 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1134 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1135 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1136 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1137 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1138 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_789 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_791 = _out_wofireMux_T_262 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_792 = _out_wofireMux_T_791 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_woready_1_240 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_241 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_242 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_243 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_244 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_245 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_246 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_247 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_793 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_795 = _out_wofireMux_T_262 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_796 = _out_wofireMux_T_795 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_woready_1_248 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_249 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_250 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_251 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_252 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_253 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_254 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_255 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_797 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_799 = _out_wofireMux_T_262 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_800 = _out_wofireMux_T_799 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_woready_1_475 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_476 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_477 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_478 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_479 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_480 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_481 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_482 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_801 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_803 = _out_wofireMux_T_262 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_804 = _out_wofireMux_T_803 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_woready_1_771 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_772 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_773 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_774 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_775 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_776 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_777 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_778 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_805 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_807 = _out_wofireMux_T_262 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_808 = _out_wofireMux_T_807 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_woready_1_1099 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1100 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1101 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1102 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1103 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1104 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1105 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1106 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_809 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_811 = _out_wofireMux_T_262 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_812 = _out_wofireMux_T_811 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_woready_1_336 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_337 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_338 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_339 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_340 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_341 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_342 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_343 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_813 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_815 = _out_wofireMux_T_262 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_816 = _out_wofireMux_T_815 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_woready_1_0 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_1 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_2 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_3 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_4 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_5 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_6 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_7 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_817 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_819 = _out_wofireMux_T_262 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_820 = _out_wofireMux_T_819 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_woready_1_995 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_996 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_997 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_998 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_999 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1000 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1001 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1002 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_821 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_823 = _out_wofireMux_T_262 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_824 = _out_wofireMux_T_823 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_woready_1_699 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_700 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_701 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_702 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_703 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_704 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_705 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_706 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_825 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_827 = _out_wofireMux_T_262 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_828 = _out_wofireMux_T_827 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_woready_1_410 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_411 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_412 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_413 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_414 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_415 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_416 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_417 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_829 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_831 = _out_wofireMux_T_262 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_832 = _out_wofireMux_T_831 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_woready_1_64 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_65 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_66 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_67 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_68 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_69 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_70 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_71 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_833 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_835 = _out_wofireMux_T_262 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_836 = _out_wofireMux_T_835 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_woready_1_907 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_908 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_909 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_910 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_911 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_912 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_913 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_914 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_837 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_839 = _out_wofireMux_T_262 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_840 = _out_wofireMux_T_839 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_woready_1_609 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_610 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_611 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_612 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_613 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_614 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_615 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_616 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_841 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_843 = _out_wofireMux_T_262 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_844 = _out_wofireMux_T_843 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_woready_1_843 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_844 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_845 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_846 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_847 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_848 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_849 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_850 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_845 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_847 = _out_wofireMux_T_262 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_848 = _out_wofireMux_T_847 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_woready_1_1043 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1044 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1045 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1046 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1047 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1048 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1049 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1050 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_849 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_851 = _out_wofireMux_T_262 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_852 = _out_wofireMux_T_851 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_woready_1_224 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_225 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_226 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_227 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_228 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_229 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_230 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_231 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_853 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_855 = _out_wofireMux_T_262 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_856 = _out_wofireMux_T_855 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_woready_1_537 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_538 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_539 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_540 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_541 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_542 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_543 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_544 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_857 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_859 = _out_wofireMux_T_262 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_860 = _out_wofireMux_T_859 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_woready_1_569 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_570 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_571 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_572 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_573 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_574 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_575 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_576 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_861 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_863 = _out_wofireMux_T_262 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_864 = _out_wofireMux_T_863 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_woready_1_851 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_852 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_853 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_854 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_855 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_856 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_857 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_858 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_865 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_867 = _out_wofireMux_T_262 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_868 = _out_wofireMux_T_867 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_woready_1_1035 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1036 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1037 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1038 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1039 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1040 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1041 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1042 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_869 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_871 = _out_wofireMux_T_262 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_872 = _out_wofireMux_T_871 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_woready_1_144 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_145 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_146 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_147 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_148 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_149 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_150 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_151 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_873 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_875 = _out_wofireMux_T_262 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_876 = _out_wofireMux_T_875 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_woready_1_72 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_73 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_74 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_75 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_76 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_77 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_78 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_79 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_877 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_879 = _out_wofireMux_T_262 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_880 = _out_wofireMux_T_879 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_woready_1_891 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_892 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_893 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_894 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_895 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_896 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_897 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_898 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_881 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_883 = _out_wofireMux_T_262 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_884 = _out_wofireMux_T_883 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_woready_1_715 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_716 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_717 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_718 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_719 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_720 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_721 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_722 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_885 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_887 = _out_wofireMux_T_262 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_888 = _out_wofireMux_T_887 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_woready_1_386 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_387 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_388 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_389 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_390 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_391 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_392 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_393 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_889 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_891 = _out_wofireMux_T_262 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_892 = _out_wofireMux_T_891 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_woready_1_128 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_129 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_130 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_131 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_132 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_133 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_134 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_135 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_893 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_895 = _out_wofireMux_T_262 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_896 = _out_wofireMux_T_895 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_woready_1_963 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_964 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_965 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_966 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_967 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_968 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_969 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_970 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_897 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_899 = _out_wofireMux_T_262 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_900 = _out_wofireMux_T_899 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_woready_1_633 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_634 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_635 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_636 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_637 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_638 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_639 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_640 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_901 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_903 = _out_wofireMux_T_262 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_904 = _out_wofireMux_T_903 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_woready_1_320 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_321 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_322 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_323 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_324 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_325 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_326 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_327 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_905 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_907 = _out_wofireMux_T_262 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_908 = _out_wofireMux_T_907 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_woready_1_553 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_554 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_555 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_556 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_557 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_558 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_559 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_560 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_909 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_911 = _out_wofireMux_T_262 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_912 = _out_wofireMux_T_911 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_woready_1_803 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_804 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_805 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_806 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_807 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_808 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_809 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_810 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_913 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_915 = _out_wofireMux_T_262 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_916 = _out_wofireMux_T_915 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_woready_1_1147 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1148 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1149 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1150 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1151 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1152 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1153 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1154 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_917 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_919 = _out_wofireMux_T_262 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_920 = _out_wofireMux_T_919 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_woready_1_176 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_177 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_178 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_179 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_180 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_181 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_182 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_183 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_921 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_923 = _out_wofireMux_T_262 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_924 = _out_wofireMux_T_923 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_woready_1_344 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_345 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_346 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_347 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_348 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_349 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_350 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_351 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_925 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_927 = _out_wofireMux_T_262 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_928 = _out_wofireMux_T_927 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_woready_1_527 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_528 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_529 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_530 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_531 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_532 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_533 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_534 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_929 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_931 = _out_wofireMux_T_262 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_932 = _out_wofireMux_T_931 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_woready_1_795 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_796 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_797 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_798 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_799 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_800 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_801 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_802 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_933 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_935 = _out_wofireMux_T_262 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_936 = _out_wofireMux_T_935 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_woready_1_1067 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1068 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1069 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1070 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1071 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1072 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1073 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1074 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_937 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_939 = _out_wofireMux_T_262 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_940 = _out_wofireMux_T_939 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_woready_1_402 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_403 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_404 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_405 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_406 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_407 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_408 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_409 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_941 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_943 = _out_wofireMux_T_262 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_944 = _out_wofireMux_T_943 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_woready_1_24 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_25 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_26 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_27 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_28 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_29 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_30 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_31 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_945 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_947 = _out_wofireMux_T_262 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_948 = _out_wofireMux_T_947 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_woready_1_987 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_988 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_989 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_990 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_991 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_992 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_993 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_994 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_949 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_951 = _out_wofireMux_T_262 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_952 = _out_wofireMux_T_951 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_woready_1_649 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_650 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_651 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_652 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_653 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_654 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_655 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_656 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_953 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_955 = _out_wofireMux_T_262 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_956 = _out_wofireMux_T_955 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_woready_1_459 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_460 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_461 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_462 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_463 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_464 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_465 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_466 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_957 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_959 = _out_wofireMux_T_262 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_960 = _out_wofireMux_T_959 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_woready_1_80 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_81 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_82 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_83 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_84 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_85 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_86 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_87 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_961 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_963 = _out_wofireMux_T_262 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_964 = _out_wofireMux_T_963 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_woready_1_899 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_900 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_901 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_902 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_903 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_904 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_905 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_906 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_965 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_967 = _out_wofireMux_T_262 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_968 = _out_wofireMux_T_967 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_woready_1_577 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_578 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_579 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_580 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_581 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_582 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_583 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_584 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_969 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_971 = _out_wofireMux_T_262 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_972 = _out_wofireMux_T_971 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_woready_1_875 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_876 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_877 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_878 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_879 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_880 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_881 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_882 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_973 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_975 = _out_wofireMux_T_262 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_976 = _out_wofireMux_T_975 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_woready_1_1139 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1140 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1141 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1142 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1143 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1144 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1145 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1146 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_977 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_979 = _out_wofireMux_T_262 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_980 = _out_wofireMux_T_979 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_woready_1_184 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_185 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_186 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_187 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_188 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_189 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_190 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_191 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_981 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_983 = _out_wofireMux_T_262 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_984 = _out_wofireMux_T_983 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_woready_1_561 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_562 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_563 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_564 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_565 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_566 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_567 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_568 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_985 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_987 = _out_wofireMux_T_262 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_988 = _out_wofireMux_T_987 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_woready_1_625 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_626 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_627 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_628 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_629 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_630 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_631 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_632 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_989 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_991 = _out_wofireMux_T_262 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_992 = _out_wofireMux_T_991 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_woready_1_883 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_884 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_885 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_886 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_887 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_888 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_889 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_890 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_993 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_995 = _out_wofireMux_T_262 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_996 = _out_wofireMux_T_995 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_woready_1_1059 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1060 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1061 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1062 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1063 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1064 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1065 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1066 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_997 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_999 = _out_wofireMux_T_262 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1000 = _out_wofireMux_T_999 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_woready_1_104 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_105 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_106 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_107 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_108 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_109 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_110 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_111 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1001 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1003 = _out_wofireMux_T_262 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1004 = _out_wofireMux_T_1003 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_woready_1_88 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_89 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_90 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_91 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_92 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_93 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_94 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_95 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1005 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1007 = _out_wofireMux_T_262 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1008 = _out_wofireMux_T_1007 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_woready_1_971 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_972 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_973 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_974 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_975 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_976 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_977 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_978 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1009 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1011 = _out_wofireMux_T_262 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1012 = _out_wofireMux_T_1011 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_woready_1_641 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_642 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_643 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_644 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_645 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_646 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_647 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_648 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1013 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1015 = _out_wofireMux_T_262 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1016 = _out_wofireMux_T_1015 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_woready_1_394 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_395 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_396 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_397 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_398 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_399 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_400 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_401 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1017 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1019 = _out_wofireMux_T_262 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1020 = _out_wofireMux_T_1019 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_woready_1_136 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_137 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_138 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_139 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_140 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_141 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_142 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_143 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1021 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1023 = _out_wofireMux_T_262 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1024 = _out_wofireMux_T_1023 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_woready_1_1051 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1052 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1053 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1054 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1055 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1056 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1057 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1058 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1025 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1027 = _out_wofireMux_T_262 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1028 = _out_wofireMux_T_1027 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_woready_1_585 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_586 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_587 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_588 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_589 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_590 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_591 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_592 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1029 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1031 = _out_wofireMux_T_262 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1032 = _out_wofireMux_T_1031 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_woready_1_328 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_329 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_330 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_331 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_332 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_333 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_334 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_335 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1033 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1035 = _out_wofireMux_T_262 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1036 = _out_wofireMux_T_1035 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_woready_1_426 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_427 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_428 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_429 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_430 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_431 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_432 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_433 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1037 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1039 = _out_wofireMux_T_262 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1040 = _out_wofireMux_T_1039 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_woready_1_835 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_836 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_837 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_838 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_839 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_840 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_841 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_842 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1041 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1043 = _out_wofireMux_T_262 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1044 = _out_wofireMux_T_1043 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_woready_1_1107 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1108 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1109 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1110 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1111 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1112 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1113 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1114 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1045 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1047 = _out_wofireMux_T_262 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1048 = _out_wofireMux_T_1047 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_woready_1_120 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_121 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_122 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_123 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_124 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_125 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_126 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_127 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1049 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1051 = _out_wofireMux_T_262 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1052 = _out_wofireMux_T_1051 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_woready_1_370 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_371 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_372 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_373 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_374 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_375 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_376 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_377 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1053 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1055 = _out_wofireMux_T_262 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1056 = _out_wofireMux_T_1055 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_woready_1_723 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_724 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_725 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_726 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_727 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_728 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_729 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_730 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1057 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1059 = _out_wofireMux_T_262 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1060 = _out_wofireMux_T_1059 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_woready_1_867 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_868 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_869 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_870 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_871 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_872 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_873 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_874 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1061 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1063 = _out_wofireMux_T_262 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1064 = _out_wofireMux_T_1063 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_woready_1_1155 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1156 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1157 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1158 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1159 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1160 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1161 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1162 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1065 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1067 = _out_wofireMux_T_262 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1068 = _out_wofireMux_T_1067 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_woready_1_296 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_297 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_298 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_299 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_300 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_301 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_302 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_303 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1069 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1071 = _out_wofireMux_T_262 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1072 = _out_wofireMux_T_1071 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_woready_1_56 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_57 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_58 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_59 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_60 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_61 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_62 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_63 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1073 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1075 = _out_wofireMux_T_262 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1076 = _out_wofireMux_T_1075 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_woready_1_915 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_916 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_917 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_918 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_919 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_920 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_921 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_922 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1077 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1079 = _out_wofireMux_T_262 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1080 = _out_wofireMux_T_1079 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_woready_1_593 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_594 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_595 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_596 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_597 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_598 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_599 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_600 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1081 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1083 = _out_wofireMux_T_262 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1084 = _out_wofireMux_T_1083 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_woready_1_487 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_488 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_489 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_490 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_491 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_492 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_493 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_494 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1085 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1087 = _out_wofireMux_T_262 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1088 = _out_wofireMux_T_1087 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_woready_1_272 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_273 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_274 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_275 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_276 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_277 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_278 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_279 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1089 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1091 = _out_wofireMux_T_262 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1092 = _out_wofireMux_T_1091 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_woready_1_1003 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1004 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1005 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1006 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1007 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1008 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1009 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1010 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1093 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1095 = _out_wofireMux_T_262 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1096 = _out_wofireMux_T_1095 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_woready_1_689 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_690 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_691 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_692 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_693 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_694 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_695 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_696 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1097 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1099 = _out_wofireMux_T_262 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1100 = _out_wofireMux_T_1099 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_woready_1_819 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_820 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_821 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_822 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_823 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_824 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_825 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_826 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1101 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1103 = _out_wofireMux_T_262 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1104 = _out_wofireMux_T_1103 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_woready_1_1083 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1084 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1085 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1086 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1087 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1088 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1089 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1090 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1105 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1107 = _out_wofireMux_T_262 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1108 = _out_wofireMux_T_1107 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_woready_1_208 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_209 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_210 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_211 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_212 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_213 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_214 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_215 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1109 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1111 = _out_wofireMux_T_262 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1112 = _out_wofireMux_T_1111 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_woready_1_434 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_435 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_436 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_437 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_438 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_439 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_440 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_441 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1113 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1115 = _out_wofireMux_T_262 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1116 = _out_wofireMux_T_1115 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_woready_1_707 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_708 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_709 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_710 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_711 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_712 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_713 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_714 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1117 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1119 = _out_wofireMux_T_262 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1120 = _out_wofireMux_T_1119 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_woready_1_1011 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1012 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1013 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1014 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1015 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1016 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1017 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1018 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1121 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1123 = _out_wofireMux_T_262 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1124 = _out_wofireMux_T_1123 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_woready_1_1171 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1172 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1173 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1174 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1175 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1176 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1177 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1178 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1125 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1127 = _out_wofireMux_T_262 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1128 = _out_wofireMux_T_1127 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_woready_1_168 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_169 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_170 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_171 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_172 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_173 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_174 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_175 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1129 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1131 = _out_wofireMux_T_262 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1132 = _out_wofireMux_T_1131 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_woready_1_40 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_41 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_42 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_43 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_44 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_45 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_46 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_47 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1133 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1135 = _out_wofireMux_T_262 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1136 = _out_wofireMux_T_1135 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_woready_1_923 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_924 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_925 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_926 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_927 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_928 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_929 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_930 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1137 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1139 = _out_wofireMux_T_262 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1140 = _out_wofireMux_T_1139 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_woready_1_665 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_666 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_667 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_668 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_669 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_670 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_671 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_672 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1141 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1143 = _out_wofireMux_T_262 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1144 = _out_wofireMux_T_1143 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_woready_1_304 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_305 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_306 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_307 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_308 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_309 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_310 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_311 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1145 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1147 = _out_wofireMux_T_262 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1148 = _out_wofireMux_T_1147 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_woready_1_232 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_233 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_234 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_235 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_236 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_237 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_238 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_239 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1149 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1151 = _out_wofireMux_T_262 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1152 = _out_wofireMux_T_1151 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_woready_1_1179 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1180 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1181 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1182 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1183 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1184 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1185 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1186 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1153 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1155 = _out_wofireMux_T_262 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1156 = _out_wofireMux_T_1155 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_woready_1_763 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_764 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_765 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_766 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_767 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_768 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_769 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_770 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1157 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1159 = _out_wofireMux_T_262 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1160 = _out_wofireMux_T_1159 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_woready_1_378 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_379 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_380 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_381 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_382 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_383 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_384 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_385 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1161 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1163 = _out_wofireMux_T_262 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1164 = _out_wofireMux_T_1163 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_woready_1_418 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_419 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_420 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_421 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_422 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_423 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_424 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_425 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1165 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1167 = _out_wofireMux_T_262 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1168 = _out_wofireMux_T_1167 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_woready_1_779 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_780 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_781 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_782 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_783 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_784 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_785 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_786 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1169 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1171 = _out_wofireMux_T_262 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1172 = _out_wofireMux_T_1171 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_woready_1_1203 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1204 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1205 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1206 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1207 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1208 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1209 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1210 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1173 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1175 = _out_wofireMux_T_262 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1176 = _out_wofireMux_T_1175 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_woready_1_152 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_153 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_154 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_155 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_156 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_157 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_158 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_159 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1177 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1179 = _out_wofireMux_T_262 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1180 = _out_wofireMux_T_1179 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_woready_1_354 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_355 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_356 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_357 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_358 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_359 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_360 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_361 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1181 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1183 = _out_wofireMux_T_262 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1184 = _out_wofireMux_T_1183 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_woready_1_673 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_674 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_675 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_676 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_677 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_678 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_679 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_680 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1185 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1187 = _out_wofireMux_T_262 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1188 = _out_wofireMux_T_1187 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_woready_1_947 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_948 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_949 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_950 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_951 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_952 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_953 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_954 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1189 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1191 = _out_wofireMux_T_262 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1192 = _out_wofireMux_T_1191 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_woready_1_1187 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1188 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1189 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1190 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1191 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1192 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1193 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1194 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1193 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1195 = _out_wofireMux_T_262 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1196 = _out_wofireMux_T_1195 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_woready_1_280 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_281 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_282 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_283 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_284 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_285 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_286 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_287 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1197 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1199 = _out_wofireMux_T_262 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1200 = _out_wofireMux_T_1199 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_woready_1_16 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_17 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_18 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_19 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_20 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_21 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_22 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_23 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1201 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1203 = _out_wofireMux_T_262 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1204 = _out_wofireMux_T_1203 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_woready_1_1019 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1020 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1021 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1022 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1023 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1024 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1025 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1026 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1205 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1207 = _out_wofireMux_T_262 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1208 = _out_wofireMux_T_1207 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_woready_1_617 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_618 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_619 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_620 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_621 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_622 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_623 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_624 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1209 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1211 = _out_wofireMux_T_262 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1212 = _out_wofireMux_T_1211 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_woready_1_503 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_504 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_505 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_506 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_507 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_508 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_509 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_510 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1213 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1215 = _out_wofireMux_T_262 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1216 = _out_wofireMux_T_1215 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_woready_1_200 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_201 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_202 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_203 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_204 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_205 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_206 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_207 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1217 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1219 = _out_wofireMux_T_262 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1220 = _out_wofireMux_T_1219 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_woready_1_1115 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1116 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1117 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1118 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1119 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1120 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1121 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1122 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1221 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1223 = _out_wofireMux_T_262 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1224 = _out_wofireMux_T_1223 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_woready_1_739 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_740 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_741 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_742 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_743 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_744 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_745 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_746 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1225 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1227 = _out_wofireMux_T_262 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1228 = _out_wofireMux_T_1227 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_woready_1_787 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_788 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_789 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_790 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_791 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_792 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_793 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_794 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1229 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1231 = _out_wofireMux_T_262 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1232 = _out_wofireMux_T_1231 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_woready_1_1123 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1124 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1125 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1126 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1127 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1128 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1129 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1130 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1233 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1235 = _out_wofireMux_T_262 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1236 = _out_wofireMux_T_1235 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_woready_1_256 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_257 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_258 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_259 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_260 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_261 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_262 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_263 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1237 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1239 = _out_wofireMux_T_262 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1240 = _out_wofireMux_T_1239 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_woready_1_519 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_520 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_521 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_522 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_523 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_524 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_525 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_526 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1241 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1243 = _out_wofireMux_T_262 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1244 = _out_wofireMux_T_1243 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_woready_1_681 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_682 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_683 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_684 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_685 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_686 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_687 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_688 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1245 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1247 = _out_wofireMux_T_262 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1248 = _out_wofireMux_T_1247 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_woready_1_1027 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1028 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1029 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1030 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1031 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1032 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1033 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1034 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1249 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1251 = _out_wofireMux_T_262 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1252 = _out_wofireMux_T_1251 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_woready_1_48 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_49 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_50 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_51 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_52 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_53 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_54 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_55 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1253 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1255 = _out_wofireMux_T_262 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1256 = _out_wofireMux_T_1255 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_woready_1_288 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_289 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_290 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_291 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_292 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_293 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_294 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_295 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1257 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1259 = _out_wofireMux_T_262 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1260 = _out_wofireMux_T_1259 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_woready_1_8 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_9 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_10 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_11 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_12 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_13 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_14 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_15 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1261 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1263 = _out_wofireMux_T_262 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1264 = _out_wofireMux_T_1263 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_woready_1_939 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_940 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_941 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_942 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_943 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_944 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_945 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_946 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1265 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1267 = _out_wofireMux_T_262 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1268 = _out_wofireMux_T_1267 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_woready_1_747 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_748 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_749 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_750 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_751 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_752 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_753 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_754 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1269 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1271 = _out_wofireMux_T_262 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1272 = _out_wofireMux_T_1271 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_woready_1_362 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_363 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_364 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_365 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_366 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_367 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_368 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_369 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1273 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1275 = _out_wofireMux_T_262 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1276 = _out_wofireMux_T_1275 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_woready_1_216 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_217 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_218 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_219 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_220 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_221 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_222 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_223 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1277 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1279 = _out_wofireMux_T_262 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1280 = _out_wofireMux_T_1279 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_woready_1_1195 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1196 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1197 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1198 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1199 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1200 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1201 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1202 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1281 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1283 = _out_wofireMux_T_262 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1284 = _out_wofireMux_T_1283 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_woready_1_811 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_812 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_813 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_814 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_815 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_816 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_817 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_818 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1285 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] assign in_1_ready = _out_in_ready_T_1; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_1_valid = _out_front_valid_T_1; // @[RegisterRouter.scala:87:24] assign out_front_1_ready = _out_front_ready_T_1; // @[RegisterRouter.scala:87:24] assign out_1_valid = _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] wire [255:0] _GEN_24 = {{_out_out_bits_data_WIRE_2_255}, {_out_out_bits_data_WIRE_2_254}, {_out_out_bits_data_WIRE_2_253}, {_out_out_bits_data_WIRE_2_252}, {_out_out_bits_data_WIRE_2_251}, {_out_out_bits_data_WIRE_2_250}, {_out_out_bits_data_WIRE_2_249}, {_out_out_bits_data_WIRE_2_248}, {_out_out_bits_data_WIRE_2_247}, {_out_out_bits_data_WIRE_2_246}, {_out_out_bits_data_WIRE_2_245}, {_out_out_bits_data_WIRE_2_244}, {_out_out_bits_data_WIRE_2_243}, {_out_out_bits_data_WIRE_2_242}, {_out_out_bits_data_WIRE_2_241}, {_out_out_bits_data_WIRE_2_240}, {_out_out_bits_data_WIRE_2_239}, {_out_out_bits_data_WIRE_2_238}, {_out_out_bits_data_WIRE_2_237}, {_out_out_bits_data_WIRE_2_236}, {_out_out_bits_data_WIRE_2_235}, {_out_out_bits_data_WIRE_2_234}, {_out_out_bits_data_WIRE_2_233}, {_out_out_bits_data_WIRE_2_232}, {_out_out_bits_data_WIRE_2_231}, {_out_out_bits_data_WIRE_2_230}, {_out_out_bits_data_WIRE_2_229}, {_out_out_bits_data_WIRE_2_228}, {_out_out_bits_data_WIRE_2_227}, {_out_out_bits_data_WIRE_2_226}, {_out_out_bits_data_WIRE_2_225}, {_out_out_bits_data_WIRE_2_224}, {_out_out_bits_data_WIRE_2_223}, {_out_out_bits_data_WIRE_2_222}, {_out_out_bits_data_WIRE_2_221}, {_out_out_bits_data_WIRE_2_220}, {_out_out_bits_data_WIRE_2_219}, {_out_out_bits_data_WIRE_2_218}, {_out_out_bits_data_WIRE_2_217}, {_out_out_bits_data_WIRE_2_216}, {_out_out_bits_data_WIRE_2_215}, {_out_out_bits_data_WIRE_2_214}, {_out_out_bits_data_WIRE_2_213}, {_out_out_bits_data_WIRE_2_212}, {_out_out_bits_data_WIRE_2_211}, {_out_out_bits_data_WIRE_2_210}, {_out_out_bits_data_WIRE_2_209}, {_out_out_bits_data_WIRE_2_208}, {_out_out_bits_data_WIRE_2_207}, {_out_out_bits_data_WIRE_2_206}, {_out_out_bits_data_WIRE_2_205}, {_out_out_bits_data_WIRE_2_204}, {_out_out_bits_data_WIRE_2_203}, {_out_out_bits_data_WIRE_2_202}, {_out_out_bits_data_WIRE_2_201}, {_out_out_bits_data_WIRE_2_200}, {_out_out_bits_data_WIRE_2_199}, {_out_out_bits_data_WIRE_2_198}, {_out_out_bits_data_WIRE_2_197}, {_out_out_bits_data_WIRE_2_196}, {_out_out_bits_data_WIRE_2_195}, {_out_out_bits_data_WIRE_2_194}, {_out_out_bits_data_WIRE_2_193}, {_out_out_bits_data_WIRE_2_192}, {_out_out_bits_data_WIRE_2_191}, {_out_out_bits_data_WIRE_2_190}, {_out_out_bits_data_WIRE_2_189}, {_out_out_bits_data_WIRE_2_188}, {_out_out_bits_data_WIRE_2_187}, {_out_out_bits_data_WIRE_2_186}, {_out_out_bits_data_WIRE_2_185}, {_out_out_bits_data_WIRE_2_184}, {_out_out_bits_data_WIRE_2_183}, {_out_out_bits_data_WIRE_2_182}, {_out_out_bits_data_WIRE_2_181}, {_out_out_bits_data_WIRE_2_180}, {_out_out_bits_data_WIRE_2_179}, {_out_out_bits_data_WIRE_2_178}, {_out_out_bits_data_WIRE_2_177}, {_out_out_bits_data_WIRE_2_176}, {_out_out_bits_data_WIRE_2_175}, {_out_out_bits_data_WIRE_2_174}, {_out_out_bits_data_WIRE_2_173}, {_out_out_bits_data_WIRE_2_172}, {_out_out_bits_data_WIRE_2_171}, {_out_out_bits_data_WIRE_2_170}, {_out_out_bits_data_WIRE_2_169}, {_out_out_bits_data_WIRE_2_168}, {_out_out_bits_data_WIRE_2_167}, {_out_out_bits_data_WIRE_2_166}, {_out_out_bits_data_WIRE_2_165}, {_out_out_bits_data_WIRE_2_164}, {_out_out_bits_data_WIRE_2_163}, {_out_out_bits_data_WIRE_2_162}, {_out_out_bits_data_WIRE_2_161}, {_out_out_bits_data_WIRE_2_160}, {_out_out_bits_data_WIRE_2_159}, {_out_out_bits_data_WIRE_2_158}, {_out_out_bits_data_WIRE_2_157}, {_out_out_bits_data_WIRE_2_156}, {_out_out_bits_data_WIRE_2_155}, {_out_out_bits_data_WIRE_2_154}, {_out_out_bits_data_WIRE_2_153}, {_out_out_bits_data_WIRE_2_152}, {_out_out_bits_data_WIRE_2_151}, {_out_out_bits_data_WIRE_2_150}, {_out_out_bits_data_WIRE_2_149}, {_out_out_bits_data_WIRE_2_148}, {_out_out_bits_data_WIRE_2_147}, {_out_out_bits_data_WIRE_2_146}, {_out_out_bits_data_WIRE_2_145}, {_out_out_bits_data_WIRE_2_144}, {_out_out_bits_data_WIRE_2_143}, {_out_out_bits_data_WIRE_2_142}, {_out_out_bits_data_WIRE_2_141}, {_out_out_bits_data_WIRE_2_140}, {_out_out_bits_data_WIRE_2_139}, {_out_out_bits_data_WIRE_2_138}, {_out_out_bits_data_WIRE_2_137}, {_out_out_bits_data_WIRE_2_136}, {_out_out_bits_data_WIRE_2_135}, {_out_out_bits_data_WIRE_2_134}, {_out_out_bits_data_WIRE_2_133}, {_out_out_bits_data_WIRE_2_132}, {_out_out_bits_data_WIRE_2_131}, {_out_out_bits_data_WIRE_2_130}, {_out_out_bits_data_WIRE_2_129}, {_out_out_bits_data_WIRE_2_128}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_115}, {_out_out_bits_data_WIRE_2_114}, {_out_out_bits_data_WIRE_2_113}, {_out_out_bits_data_WIRE_2_112}, {_out_out_bits_data_WIRE_2_111}, {_out_out_bits_data_WIRE_2_110}, {_out_out_bits_data_WIRE_2_109}, {_out_out_bits_data_WIRE_2_108}, {_out_out_bits_data_WIRE_2_107}, {_out_out_bits_data_WIRE_2_106}, {_out_out_bits_data_WIRE_2_105}, {_out_out_bits_data_WIRE_2_104}, {_out_out_bits_data_WIRE_2_103}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_96}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_33}, {_out_out_bits_data_WIRE_2_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_10}, {_out_out_bits_data_WIRE_2_9}, {_out_out_bits_data_WIRE_2_8}, {_out_out_bits_data_WIRE_2_7}, {_out_out_bits_data_WIRE_2_6}, {_out_out_bits_data_WIRE_2_5}, {_out_out_bits_data_WIRE_2_4}, {_out_out_bits_data_WIRE_2_3}, {_out_out_bits_data_WIRE_2_2}, {_out_out_bits_data_WIRE_2_1}, {_out_out_bits_data_WIRE_2_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_6 = _GEN_24[out_oindex_1]; // @[MuxLiteral.scala:49:10] wire [255:0][63:0] _GEN_25 = {{_out_out_bits_data_WIRE_3_255}, {_out_out_bits_data_WIRE_3_254}, {_out_out_bits_data_WIRE_3_253}, {_out_out_bits_data_WIRE_3_252}, {_out_out_bits_data_WIRE_3_251}, {_out_out_bits_data_WIRE_3_250}, {_out_out_bits_data_WIRE_3_249}, {_out_out_bits_data_WIRE_3_248}, {_out_out_bits_data_WIRE_3_247}, {_out_out_bits_data_WIRE_3_246}, {_out_out_bits_data_WIRE_3_245}, {_out_out_bits_data_WIRE_3_244}, {_out_out_bits_data_WIRE_3_243}, {_out_out_bits_data_WIRE_3_242}, {_out_out_bits_data_WIRE_3_241}, {_out_out_bits_data_WIRE_3_240}, {_out_out_bits_data_WIRE_3_239}, {_out_out_bits_data_WIRE_3_238}, {_out_out_bits_data_WIRE_3_237}, {_out_out_bits_data_WIRE_3_236}, {_out_out_bits_data_WIRE_3_235}, {_out_out_bits_data_WIRE_3_234}, {_out_out_bits_data_WIRE_3_233}, {_out_out_bits_data_WIRE_3_232}, {_out_out_bits_data_WIRE_3_231}, {_out_out_bits_data_WIRE_3_230}, {_out_out_bits_data_WIRE_3_229}, {_out_out_bits_data_WIRE_3_228}, {_out_out_bits_data_WIRE_3_227}, {_out_out_bits_data_WIRE_3_226}, {_out_out_bits_data_WIRE_3_225}, {_out_out_bits_data_WIRE_3_224}, {_out_out_bits_data_WIRE_3_223}, {_out_out_bits_data_WIRE_3_222}, {_out_out_bits_data_WIRE_3_221}, {_out_out_bits_data_WIRE_3_220}, {_out_out_bits_data_WIRE_3_219}, {_out_out_bits_data_WIRE_3_218}, {_out_out_bits_data_WIRE_3_217}, {_out_out_bits_data_WIRE_3_216}, {_out_out_bits_data_WIRE_3_215}, {_out_out_bits_data_WIRE_3_214}, {_out_out_bits_data_WIRE_3_213}, {_out_out_bits_data_WIRE_3_212}, {_out_out_bits_data_WIRE_3_211}, {_out_out_bits_data_WIRE_3_210}, {_out_out_bits_data_WIRE_3_209}, {_out_out_bits_data_WIRE_3_208}, {_out_out_bits_data_WIRE_3_207}, {_out_out_bits_data_WIRE_3_206}, {_out_out_bits_data_WIRE_3_205}, {_out_out_bits_data_WIRE_3_204}, {_out_out_bits_data_WIRE_3_203}, {_out_out_bits_data_WIRE_3_202}, {_out_out_bits_data_WIRE_3_201}, {_out_out_bits_data_WIRE_3_200}, {_out_out_bits_data_WIRE_3_199}, {_out_out_bits_data_WIRE_3_198}, {_out_out_bits_data_WIRE_3_197}, {_out_out_bits_data_WIRE_3_196}, {_out_out_bits_data_WIRE_3_195}, {_out_out_bits_data_WIRE_3_194}, {_out_out_bits_data_WIRE_3_193}, {_out_out_bits_data_WIRE_3_192}, {_out_out_bits_data_WIRE_3_191}, {_out_out_bits_data_WIRE_3_190}, {_out_out_bits_data_WIRE_3_189}, {_out_out_bits_data_WIRE_3_188}, {_out_out_bits_data_WIRE_3_187}, {_out_out_bits_data_WIRE_3_186}, {_out_out_bits_data_WIRE_3_185}, {_out_out_bits_data_WIRE_3_184}, {_out_out_bits_data_WIRE_3_183}, {_out_out_bits_data_WIRE_3_182}, {_out_out_bits_data_WIRE_3_181}, {_out_out_bits_data_WIRE_3_180}, {_out_out_bits_data_WIRE_3_179}, {_out_out_bits_data_WIRE_3_178}, {_out_out_bits_data_WIRE_3_177}, {_out_out_bits_data_WIRE_3_176}, {_out_out_bits_data_WIRE_3_175}, {_out_out_bits_data_WIRE_3_174}, {_out_out_bits_data_WIRE_3_173}, {_out_out_bits_data_WIRE_3_172}, {_out_out_bits_data_WIRE_3_171}, {_out_out_bits_data_WIRE_3_170}, {_out_out_bits_data_WIRE_3_169}, {_out_out_bits_data_WIRE_3_168}, {_out_out_bits_data_WIRE_3_167}, {_out_out_bits_data_WIRE_3_166}, {_out_out_bits_data_WIRE_3_165}, {_out_out_bits_data_WIRE_3_164}, {_out_out_bits_data_WIRE_3_163}, {_out_out_bits_data_WIRE_3_162}, {_out_out_bits_data_WIRE_3_161}, {_out_out_bits_data_WIRE_3_160}, {_out_out_bits_data_WIRE_3_159}, {_out_out_bits_data_WIRE_3_158}, {_out_out_bits_data_WIRE_3_157}, {_out_out_bits_data_WIRE_3_156}, {_out_out_bits_data_WIRE_3_155}, {_out_out_bits_data_WIRE_3_154}, {_out_out_bits_data_WIRE_3_153}, {_out_out_bits_data_WIRE_3_152}, {_out_out_bits_data_WIRE_3_151}, {_out_out_bits_data_WIRE_3_150}, {_out_out_bits_data_WIRE_3_149}, {_out_out_bits_data_WIRE_3_148}, {_out_out_bits_data_WIRE_3_147}, {_out_out_bits_data_WIRE_3_146}, {_out_out_bits_data_WIRE_3_145}, {_out_out_bits_data_WIRE_3_144}, {_out_out_bits_data_WIRE_3_143}, {_out_out_bits_data_WIRE_3_142}, {_out_out_bits_data_WIRE_3_141}, {_out_out_bits_data_WIRE_3_140}, {_out_out_bits_data_WIRE_3_139}, {_out_out_bits_data_WIRE_3_138}, {_out_out_bits_data_WIRE_3_137}, {_out_out_bits_data_WIRE_3_136}, {_out_out_bits_data_WIRE_3_135}, {_out_out_bits_data_WIRE_3_134}, {_out_out_bits_data_WIRE_3_133}, {_out_out_bits_data_WIRE_3_132}, {_out_out_bits_data_WIRE_3_131}, {_out_out_bits_data_WIRE_3_130}, {_out_out_bits_data_WIRE_3_129}, {_out_out_bits_data_WIRE_3_128}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {_out_out_bits_data_WIRE_3_115}, {_out_out_bits_data_WIRE_3_114}, {_out_out_bits_data_WIRE_3_113}, {_out_out_bits_data_WIRE_3_112}, {_out_out_bits_data_WIRE_3_111}, {_out_out_bits_data_WIRE_3_110}, {_out_out_bits_data_WIRE_3_109}, {_out_out_bits_data_WIRE_3_108}, {_out_out_bits_data_WIRE_3_107}, {_out_out_bits_data_WIRE_3_106}, {_out_out_bits_data_WIRE_3_105}, {_out_out_bits_data_WIRE_3_104}, {_out_out_bits_data_WIRE_3_103}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h380006F}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h100073}, {64'h100026237B200073}, {64'h7B20247310802423}, {64'hF140247330000067}, {64'h100022237B202473}, {64'h4086300147413}, {64'hFE0408E300347413}, {64'h4004440310802023}, {64'hF14024737B241073}, {64'hFF0000F0440006F}, {64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_8 = _GEN_25[out_oindex_1]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_9 = _out_out_bits_data_T_6 ? _out_out_bits_data_T_8 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_1_bits_data = _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27] wire hartHalted = _hartHalted_T; // @[Debug.scala:1734:37] wire [1:0] ctrlStateNxt; // @[Debug.scala:1735:32] assign _abstractCommandBusy_T = \|ctrlStateReg; // @[Debug.scala:1732:27, :1740:42] assign abstractCommandBusy = _abstractCommandBusy_T; // @[Debug.scala:1220:39, :1740:42] assign _ABSTRACTCSWrEnLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44] assign ABSTRACTCSWrEnLegal = _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1190:39, :1742:44] assign _COMMANDWrEnLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1743:44] assign COMMANDWrEnLegal = _COMMANDWrEnLegal_T; // @[Debug.scala:1282:39, :1743:44] assign _ABSTRACTAUTOWrEnLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1744:44] assign ABSTRACTAUTOWrEnLegal = _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1243:41, :1744:44] assign _dmiAbstractDataAccessLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1745:50] assign dmiAbstractDataAccessLegal = _dmiAbstractDataAccessLegal_T; // @[Debug.scala:892:46, :1745:50] assign _dmiProgramBufferAccessLegal_T = ~(\|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1746:50] assign dmiProgramBufferAccessLegal = _dmiProgramBufferAccessLegal_T; // @[Debug.scala:888:47, :1746:50] wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39, :1748:45] wire _errorBusy_T_1 = ABSTRACTCSWrEnMaybe & _errorBusy_T; // @[Debug.scala:1188:39, :1748:{42,45}] wire _errorBusy_T_2 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45] wire _errorBusy_T_3 = autoexecdataWrEnMaybe & _errorBusy_T_2; // @[Debug.scala:1240:41, :1749:{42,45}] wire _errorBusy_T_4 = _errorBusy_T_1 \| _errorBusy_T_3; // @[Debug.scala:1748:{42,74}, :1749:42] wire _errorBusy_T_5 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45, :1750:47] wire _errorBusy_T_6 = autoexecprogbufWrEnMaybe & _errorBusy_T_5; // @[Debug.scala:1241:44, :1750:{44,47}] wire _errorBusy_T_7 = _errorBusy_T_4 \| _errorBusy_T_6; // @[Debug.scala:1748:74, :1749:74, :1750:44] wire _errorBusy_T_8 = ~COMMANDWrEnLegal; // @[Debug.scala:1282:39, :1751:45] wire _errorBusy_T_9 = COMMANDWrEnMaybe & _errorBusy_T_8; // @[Debug.scala:1281:39, :1751:{42,45}] wire _errorBusy_T_10 = _errorBusy_T_7 \| _errorBusy_T_9; // @[Debug.scala:1749:74, :1750:74, :1751:42] wire _errorBusy_T_11 = ~dmiAbstractDataAccessLegal; // @[Debug.scala:892:46, :1752:45] wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T_11; // @[Debug.scala:1263:68, :1752:{42,45}] wire _errorBusy_T_13 = _errorBusy_T_10 \| _errorBusy_T_12; // @[Debug.scala:1750:74, :1751:74, :1752:42] wire _errorBusy_T_14 = ~dmiProgramBufferAccessLegal; // @[Debug.scala:888:47, :1753:45] wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T_14; // @[Debug.scala:1264:69, :1753:{42,45}] assign _errorBusy_T_16 = _errorBusy_T_13 \| _errorBusy_T_15; // @[Debug.scala:1751:74, :1752:74, :1753:42] assign errorBusy = _errorBusy_T_16; // @[Debug.scala:1195:36, :1752:74] wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala:1280:39, :1756:60] wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58] wire _commandWrIsUnsupported_T = ~commandWrIsAccessRegister; // @[Debug.scala:1756:60, :1759:49] wire commandWrIsUnsupported = COMMANDWrEn & _commandWrIsUnsupported_T; // @[Debug.scala:1285:40, :1759:{46,49}] wire commandRegIsUnsupported; // @[Debug.scala:1761:43] wire commandRegBadHaltResume; // @[Debug.scala:1762:43] wire _accessRegIsLegalSize_T = accessRegisterCommandReg_size == 3'h2; // @[Debug.scala:1533:44, :1765:63] wire _accessRegIsLegalSize_T_1 = accessRegisterCommandReg_size == 3'h3; // @[Debug.scala:1533:44, :1765:106] wire accessRegIsLegalSize = _accessRegIsLegalSize_T \| _accessRegIsLegalSize_T_1; // @[Debug.scala:1765:{63,72,106}] wire _accessRegIsGPR_T = \|(accessRegisterCommandReg_regno[15:12]); // @[Debug.scala:1533:44, :1766:58] wire _accessRegIsGPR_T_1 = accessRegisterCommandReg_regno < 16'h1020; // @[Debug.scala:1533:44, :1766:104] wire _accessRegIsGPR_T_2 = _accessRegIsGPR_T & _accessRegIsGPR_T_1; // @[Debug.scala:1766:{58,70,104}] wire accessRegIsGPR = _accessRegIsGPR_T_2 & accessRegIsLegalSize; // @[Debug.scala:1765:72, :1766:{70,117}] wire _T_1567 = ~accessRegisterCommandReg_transfer \| accessRegIsGPR; // @[Debug.scala:1533:44, :1766:117, :1776:{19,54}] assign commandRegIsUnsupported = ~commandRegIsAccessRegister \| ~_T_1567; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33] wire _commandRegBadHaltResume_T = ~hartHalted; // @[Debug.scala:1734:37, :1778:36] assign commandRegBadHaltResume = commandRegIsAccessRegister & _T_1567 & _commandRegBadHaltResume_T; // @[Debug.scala:1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}] wire _wrAccessRegisterCommand_T = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala:1285:40, :1756:60, :1782:48] wire _GEN_26 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103] wire _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:103] assign _wrAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103] wire _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:103] assign _regAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103, :1783:103] wire wrAccessRegisterCommand = _wrAccessRegisterCommand_T & _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:{48,78,103}] wire _regAccessRegisterCommand_T = autoexec & commandRegIsAccessRegister; // @[Debug.scala:1272:48, :1757:58, :1783:48] wire regAccessRegisterCommand = _regAccessRegisterCommand_T & _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:{48,78,103}] wire _T_1569 = wrAccessRegisterCommand \| regAccessRegisterCommand; // @[Debug.scala:1782:78, :1783:78, :1790:37] wire _T_1571 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30] assign errorUnsupported = (\|ctrlStateReg) ? _T_1571 & commandRegIsUnsupported : ~_T_1569 & (commandWrIsUnsupported \| autoexec & commandRegIsUnsupported); // @[Debug.scala:1197:36, :1272:48, :1732:27, :1740:42, :1759:46, :1761:43, :1789:47, :1790:{37,66}, :1792:43, :1793:26, :1794:{28,56}, :1797:{30,59}, :1804:38] assign errorHaltResume = (\|ctrlStateReg) & _T_1571 & ~commandRegIsUnsupported & commandRegBadHaltResume; // @[Debug.scala:1198:36, :1732:27, :1740:42, :1761:43, :1762:43, :1789:47, :1797:{30,59}, :1804:38, :1807:43] wire _GEN_27 = commandRegIsUnsupported \| commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] assign goAbstract = (\|ctrlStateReg) & _T_1571 & ~_GEN_27; // @[Debug.scala:1495:32, :1732:27, :1740:42, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire _T_1572 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30] wire _GEN_28 = ~(\|ctrlStateReg) \| _T_1571; // @[Debug.scala:1196:36, :1732:27, :1740:42, :1742:44, :1789:47, :1797:{30,59}, :1818:51] assign errorException = ~_GEN_28 & _T_1572 & hartExceptionWrEn; // @[Debug.scala:881:36, :1196:36, :1789:47, :1797:59, :1818:{30,51}, :1826:31] assign goCustom = ~(_GEN_28 \| _T_1572) & (&ctrlStateReg); // @[Debug.scala:1196:36, :1496:32, :1732:27, :1789:47, :1797:59, :1818:{30,51}, :1831:{30,53}] assign ctrlStateNxt = (\|ctrlStateReg) ? (_T_1571 ? {~_GEN_27, 1'h0} : _T_1572 & (hartExceptionWrEn \| ~goReg & hartHaltedWrEn) ? 2'h0 : ctrlStateReg) : _T_1569 ? 2'h1 : ctrlStateReg; // @[Debug.scala:875:36, :881:36, :1494:27, :1732:27, :1735:32, :1740:42, :1789:47, :1790:{37,66}, :1791:22, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33, :1818:{30,51}, :1823:{18,30,116}, :1824:22, :1826:31, :1828:24, :1831:53]
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module AsyncResetRegVec_w1_i0_4( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLInterconnectCoupler_cbus_to_debug( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [11:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] TLFragmenter_Debug fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7] ); // @[Fragmenter.scala:345:34] assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_73( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a32d128s4k4z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_source = 4'h0; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_source = 4'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_45 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s4k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s4k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s4k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s4k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s4k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLBuffer_a32d64s4k5z4u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (auto_buffer_in_a_ready), .auto_in_a_valid (auto_buffer_in_a_valid), .auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode), .auto_in_a_bits_param (auto_buffer_in_a_bits_param), .auto_in_a_bits_size (auto_buffer_in_a_bits_size), .auto_in_a_bits_source (auto_buffer_in_a_bits_source), .auto_in_a_bits_address (auto_buffer_in_a_bits_address), .auto_in_a_bits_mask (auto_buffer_in_a_bits_mask), .auto_in_a_bits_data (auto_buffer_in_a_bits_data), .auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt), .auto_in_d_ready (auto_buffer_in_d_ready), .auto_in_d_valid (auto_buffer_in_d_valid), .auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode), .auto_in_d_bits_param (auto_buffer_in_d_bits_param), .auto_in_d_bits_size (auto_buffer_in_d_bits_size), .auto_in_d_bits_source (auto_buffer_in_d_bits_source), .auto_in_d_bits_sink (auto_buffer_in_d_bits_sink), .auto_in_d_bits_denied (auto_buffer_in_d_bits_denied), .auto_in_d_bits_data (auto_buffer_in_d_bits_data), .auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt), .auto_out_a_ready (auto_tl_out_a_ready), .auto_out_a_valid (auto_tl_out_a_valid), .auto_out_a_bits_opcode (auto_tl_out_a_bits_opcode), .auto_out_a_bits_param (auto_tl_out_a_bits_param), .auto_out_a_bits_size (auto_tl_out_a_bits_size), .auto_out_a_bits_source (auto_tl_out_a_bits_source), .auto_out_a_bits_address (auto_tl_out_a_bits_address), .auto_out_a_bits_mask (auto_tl_out_a_bits_mask), .auto_out_a_bits_data (auto_tl_out_a_bits_data), .auto_out_a_bits_corrupt (auto_tl_out_a_bits_corrupt), .auto_out_d_ready (auto_tl_out_d_ready), .auto_out_d_valid (auto_tl_out_d_valid), .auto_out_d_bits_opcode (auto_tl_out_d_bits_opcode), .auto_out_d_bits_param (auto_tl_out_d_bits_param), .auto_out_d_bits_size (auto_tl_out_d_bits_size), .auto_out_d_bits_source (auto_tl_out_d_bits_source), .auto_out_d_bits_sink (auto_tl_out_d_bits_sink), .auto_out_d_bits_denied (auto_tl_out_d_bits_denied), .auto_out_d_bits_data (auto_tl_out_d_bits_data), .auto_out_d_bits_corrupt (auto_tl_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLBuffer_a29d64s7k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_9 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s7k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s7k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }	module L1MetadataArray_1( // @[HellaCache.scala:322:7] input clock, // @[HellaCache.scala:322:7] input reset, // @[HellaCache.scala:322:7] output io_read_ready, // @[HellaCache.scala:324:14] input io_read_valid, // @[HellaCache.scala:324:14] input [3:0] io_read_bits_idx, // @[HellaCache.scala:324:14] input [1:0] io_read_bits_way_en, // @[HellaCache.scala:324:14] input [21:0] io_read_bits_tag, // @[HellaCache.scala:324:14] output io_write_ready, // @[HellaCache.scala:324:14] input io_write_valid, // @[HellaCache.scala:324:14] input [3:0] io_write_bits_idx, // @[HellaCache.scala:324:14] input [1:0] io_write_bits_way_en, // @[HellaCache.scala:324:14] input [21:0] io_write_bits_tag, // @[HellaCache.scala:324:14] input [1:0] io_write_bits_data_coh_state, // @[HellaCache.scala:324:14] input [21:0] io_write_bits_data_tag, // @[HellaCache.scala:324:14] output [1:0] io_resp_0_coh_state, // @[HellaCache.scala:324:14] output [21:0] io_resp_0_tag, // @[HellaCache.scala:324:14] output [1:0] io_resp_1_coh_state, // @[HellaCache.scala:324:14] output [21:0] io_resp_1_tag // @[HellaCache.scala:324:14] ); wire tag_array_MPORT_1_en; // @[Decoupled.scala:51:35] wire [3:0] tag_array_MPORT_addr; // @[HellaCache.scala:342:20] wire [47:0] _tag_array_RW0_rdata; // @[HellaCache.scala:339:30] wire io_read_valid_0 = io_read_valid; // @[HellaCache.scala:322:7] wire [3:0] io_read_bits_idx_0 = io_read_bits_idx; // @[HellaCache.scala:322:7] wire [1:0] io_read_bits_way_en_0 = io_read_bits_way_en; // @[HellaCache.scala:322:7] wire [21:0] io_read_bits_tag_0 = io_read_bits_tag; // @[HellaCache.scala:322:7] wire io_write_valid_0 = io_write_valid; // @[HellaCache.scala:322:7] wire [3:0] io_write_bits_idx_0 = io_write_bits_idx; // @[HellaCache.scala:322:7] wire [1:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[HellaCache.scala:322:7] wire [21:0] io_write_bits_tag_0 = io_write_bits_tag; // @[HellaCache.scala:322:7] wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[HellaCache.scala:322:7] wire [21:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[HellaCache.scala:322:7] wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [21:0] rstVal_tag = 22'h0; // @[HellaCache.scala:305:20] wire _io_read_ready_T; // @[HellaCache.scala:346:20] wire [1:0] _rmask_T_1 = io_read_bits_way_en_0; // @[HellaCache.scala:322:7, :335:70] wire _io_write_ready_T; // @[HellaCache.scala:347:21] wire [1:0] _wmask_T_1 = io_write_bits_way_en_0; // @[HellaCache.scala:322:7, :334:71] wire io_read_ready_0; // @[HellaCache.scala:322:7] wire io_write_ready_0; // @[HellaCache.scala:322:7] wire [1:0] io_resp_0_coh_state_0; // @[HellaCache.scala:322:7] wire [21:0] io_resp_0_tag_0; // @[HellaCache.scala:322:7] wire [1:0] io_resp_1_coh_state_0; // @[HellaCache.scala:322:7] wire [21:0] io_resp_1_tag_0; // @[HellaCache.scala:322:7] reg [4:0] rst_cnt; // @[HellaCache.scala:330:24] wire rst = ~(rst_cnt[4]); // @[HellaCache.scala:330:24, :331:21] wire _wmask_T = rst; // @[HellaCache.scala:331:21, :334:23] wire _rmask_T = rst; // @[HellaCache.scala:331:21, :335:23] wire [4:0] waddr = rst ? rst_cnt : {1'h0, io_write_bits_idx_0}; // @[HellaCache.scala:322:7, :330:24, :331:21, :332:18] wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[HellaCache.scala:322:7, :331:21, :333:18] wire [21:0] _wdata_T_tag = rst ? 22'h0 : io_write_bits_data_tag_0; // @[HellaCache.scala:322:7, :331:21, :333:18] wire [23:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[HellaCache.scala:333:{18,52}] wire [1:0] _wmask_T_2 = _wmask_T ? 2'h3 : _wmask_T_1; // @[HellaCache.scala:334:{18,23,71}] wire wmask_0 = _wmask_T_2[0]; // @[HellaCache.scala:334:{18,79}] wire wmask_1 = _wmask_T_2[1]; // @[HellaCache.scala:334:{18,79}] wire [1:0] _rmask_T_2 = _rmask_T ? 2'h3 : _rmask_T_1; // @[HellaCache.scala:335:{18,23,70}] wire rmask_0 = _rmask_T_2[0]; // @[HellaCache.scala:335:{18,78}] wire rmask_1 = _rmask_T_2[1]; // @[HellaCache.scala:335:{18,78}] wire [5:0] _rst_cnt_T = {1'h0, rst_cnt} + 6'h1; // @[HellaCache.scala:330:24, :332:18, :336:34] wire [4:0] _rst_cnt_T_1 = _rst_cnt_T[4:0]; // @[HellaCache.scala:336:34] wire wen; // @[HellaCache.scala:340:17] assign wen = rst \| io_write_valid_0; // @[HellaCache.scala:322:7, :331:21, :340:17] assign tag_array_MPORT_addr = waddr[3:0]; // @[HellaCache.scala:332:18, :342:20] assign tag_array_MPORT_1_en = io_read_ready_0 & io_read_valid_0; // @[Decoupled.scala:51:35] assign io_resp_0_tag_0 = _tag_array_RW0_rdata[21:0]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_0_coh_state_0 = _tag_array_RW0_rdata[23:22]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_1_tag_0 = _tag_array_RW0_rdata[45:24]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_1_coh_state_0 = _tag_array_RW0_rdata[47:46]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign _io_read_ready_T = ~wen; // @[HellaCache.scala:340:17, :346:20] assign io_read_ready_0 = _io_read_ready_T; // @[HellaCache.scala:322:7, :346:20] assign _io_write_ready_T = ~rst; // @[HellaCache.scala:331:21, :347:21] assign io_write_ready_0 = _io_write_ready_T; // @[HellaCache.scala:322:7, :347:21] always @(posedge clock) begin // @[HellaCache.scala:322:7] if (reset) // @[HellaCache.scala:322:7] rst_cnt <= 5'h0; // @[HellaCache.scala:330:24] else if (rst) // @[HellaCache.scala:331:21] rst_cnt <= _rst_cnt_T_1; // @[HellaCache.scala:330:24, :336:34] always @(posedge) tag_array_0 tag_array ( // @[HellaCache.scala:339:30] .RW0_addr (wen ? tag_array_MPORT_addr : io_read_bits_idx_0), // @[HellaCache.scala:322:7, :339:30, :340:17, :342:20] .RW0_en (tag_array_MPORT_1_en \| wen), // @[Decoupled.scala:51:35] .RW0_clk (clock), .RW0_wmode (wen), // @[HellaCache.scala:340:17] .RW0_wdata ({2{wdata}}), // @[HellaCache.scala:333:52, :339:30] .RW0_rdata (_tag_array_RW0_rdata), .RW0_wmask ({wmask_1, wmask_0}) // @[HellaCache.scala:334:79, :339:30] ); // @[HellaCache.scala:339:30] assign io_read_ready = io_read_ready_0; // @[HellaCache.scala:322:7] assign io_write_ready = io_write_ready_0; // @[HellaCache.scala:322:7] assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[HellaCache.scala:322:7] assign io_resp_0_tag = io_resp_0_tag_0; // @[HellaCache.scala:322:7] assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[HellaCache.scala:322:7] assign io_resp_1_tag = io_resp_1_tag_0; // @[HellaCache.scala:322:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module AsyncResetRegVec_w1_i0_49( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File SourceE.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceERequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val sink = UInt(params.outer.bundle.sinkBits.W) } class SourceE(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceERequest(params))) val e = Decoupled(new TLBundleE(params.outer.bundle)) }) // ready must be a register, because we derive valid from ready require (!params.micro.outerBuf.e.pipe && params.micro.outerBuf.e.isDefined) val e = Wire(chiselTypeOf(io.e)) io.e <> params.micro.outerBuf.e(e) io.req.ready := e.ready e.valid := io.req.valid e.bits.sink := io.req.bits.sink // we can't cover valid+!ready, because no backpressure on E is common }	module SourceE_6( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_6 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_369( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_113 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_11( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [3:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [3:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [31:0] io_out_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_27 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7] .io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7] .io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7] .io_out_a_bits (io_out_a_0_bits), .io_out_b_bits (io_out_b_0_bits_0), .io_out_c_bits (io_out_c_0_bits_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7] assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File JtagShifter.scala: // See LICENSE.jtag for license details. package freechips.rocketchip.jtag import chisel3._ import chisel3.reflect.DataMirror import chisel3.internal.firrtl.KnownWidth import chisel3.util.{Cat, Valid} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.property /** Base JTAG shifter IO, viewed from input to shift register chain. * Can be chained together. / class ShifterIO extends Bundle { val shift = Bool() // advance the scan chain on clock high val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB val capture = Bool() // high in the CaptureIR/DR state when this chain is selected val update = Bool() // high in the UpdateIR/DR state when this chain is selected /* Sets a output shifter IO's control signals from a input shifter IO's control signals. / def chainControlFrom(in: ShifterIO): Unit = { shift := in.shift capture := in.capture update := in.update } } trait ChainIO extends Bundle { val chainIn = Input(new ShifterIO) val chainOut = Output(new ShifterIO) } class Capture[+T <: Data](gen: T) extends Bundle { val bits = Input(gen) // data to capture, should be always valid val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge } object Capture { def apply[T <: Data](gen: T): Capture[T] = new Capture(gen) } /* Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain * IO. / trait Chain extends Module { val io: ChainIO } /* One-element shift register, data register for bypass mode. * * Implements Clause 10. / class JtagBypassChain(implicit val p: Parameters) extends Chain { class ModIO extends ChainIO val io = IO(new ModIO) io.chainOut chainControlFrom io.chainIn val reg = Reg(Bool()) // 10.1.1a single shift register stage io.chainOut.data := reg property.cover(io.chainIn.capture, "bypass_chain_capture", "JTAG; bypass_chain_capture; This Bypass Chain captured data") when (io.chainIn.capture) { reg := false.B // 10.1.1b capture logic 0 on TCK rising } .elsewhen (io.chainIn.shift) { reg := io.chainIn.data } assert(!(io.chainIn.capture && io.chainIn.update) && !(io.chainIn.capture && io.chainIn.shift) && !(io.chainIn.update && io.chainIn.shift)) } object JtagBypassChain { def apply()(implicit p: Parameters) = new JtagBypassChain } /* Simple shift register with parallel capture only, for read-only data registers. * * Number of stages is the number of bits in gen, which must have a known width. * * Useful notes: * 7.2.1c shifter shifts on TCK rising edge * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge / class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain { override def desiredName = s"CaptureChain_${gen.typeName}" class ModIO extends ChainIO { val capture = Capture(gen) } val io = IO(new ModIO) io.chainOut chainControlFrom io.chainIn val n = DataMirror.widthOf(gen) match { case KnownWidth(x) => x case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack } val regs = (0 until n) map (x => Reg(Bool())) io.chainOut.data := regs(0) property.cover(io.chainIn.capture, "chain_capture", "JTAG; chain_capture; This Chain captured data") when (io.chainIn.capture) { (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x)) io.capture.capture := true.B } .elsewhen (io.chainIn.shift) { regs(n-1) := io.chainIn.data (0 until n-1) map (x => regs(x) := regs(x+1)) io.capture.capture := false.B } .otherwise { io.capture.capture := false.B } assert(!(io.chainIn.capture && io.chainIn.update) && !(io.chainIn.capture && io.chainIn.shift) && !(io.chainIn.update && io.chainIn.shift)) } object CaptureChain { def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen) } /* Simple shift register with parallel capture and update. Useful for general instruction and data * scan registers. * * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have * known widths. If there is a width mismatch, the unused most significant bits will be zero. * * Useful notes: * 7.2.1c shifter shifts on TCK rising edge * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge / class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain { override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}" class ModIO extends ChainIO { val capture = Capture(genCapture) val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after } val io = IO(new ModIO) io.chainOut chainControlFrom io.chainIn val captureWidth = DataMirror.widthOf(genCapture) match { case KnownWidth(x) => x case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack } val updateWidth = DataMirror.widthOf(genUpdate) match { case KnownWidth(x) => x case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack } val n = math.max(captureWidth, updateWidth) val regs = (0 until n) map (x => Reg(Bool())) io.chainOut.data := regs(0) val updateBits = Cat(regs.reverse)(updateWidth-1, 0) io.update.bits := updateBits.asTypeOf(io.update.bits) val captureBits = io.capture.bits.asUInt property.cover(io.chainIn.capture, "chain_capture", "JTAG;chain_capture; This Chain captured data") property.cover(io.chainIn.capture, "chain_update", "JTAG;chain_update; This Chain updated data") when (io.chainIn.capture) { (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x)) (captureWidth until n) map (x => regs(x) := 0.U) io.capture.capture := true.B io.update.valid := false.B } .elsewhen (io.chainIn.update) { io.capture.capture := false.B io.update.valid := true.B } .elsewhen (io.chainIn.shift) { regs(n-1) := io.chainIn.data (0 until n-1) map (x => regs(x) := regs(x+1)) io.capture.capture := false.B io.update.valid := false.B } .otherwise { io.capture.capture := false.B io.update.valid := false.B } assert(!(io.chainIn.capture && io.chainIn.update) && !(io.chainIn.capture && io.chainIn.shift) && !(io.chainIn.update && io.chainIn.shift)) } object CaptureUpdateChain { /* Capture-update chain with matching capture and update types. */ def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen) def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) = new CaptureUpdateChain(genCapture, genUpdate) }	module JtagBypassChain( // @[JtagShifter.scala:56:7] input clock, // @[JtagShifter.scala:56:7] input reset, // @[JtagShifter.scala:56:7] input io_chainIn_shift, // @[JtagShifter.scala:58:14] input io_chainIn_data, // @[JtagShifter.scala:58:14] input io_chainIn_capture, // @[JtagShifter.scala:58:14] input io_chainIn_update, // @[JtagShifter.scala:58:14] output io_chainOut_data // @[JtagShifter.scala:58:14] ); reg reg_0; // @[JtagShifter.scala:61:16]
Generate the Verilog code corresponding to the following Chisel files. File Mesh.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ /** * A Grid is a 2D array of Tile modules with registers in between each tile and * registers from the bottom row and rightmost column of tiles to the Grid outputs. * @param width * @param tileRows * @param tileColumns * @param meshRows * @param meshColumns */ class Mesh[T <: Data : Arithmetic](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, tile_latency: Int, max_simultaneous_matmuls: Int, output_delay: Int, val tileRows: Int, val tileColumns: Int, val meshRows: Int, val meshColumns: Int) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(meshRows, Vec(tileRows, inputType))) val in_b = Input(Vec(meshColumns, Vec(tileColumns, inputType))) val in_d = Input(Vec(meshColumns, Vec(tileColumns, inputType))) val in_control = Input(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) val in_id = Input(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) // The unique id of this particular matmul val in_last = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) val out_b = Output(Vec(meshColumns, Vec(tileColumns, outputType))) val out_c = Output(Vec(meshColumns, Vec(tileColumns, outputType))) val in_valid = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) val out_valid = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) val out_control = Output(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) val out_id = Output(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) val out_last = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) }) // mesh(r)(c) => Tile at row r, column c val mesh: Seq[Seq[Tile[T]]] = Seq.fill(meshRows, meshColumns)(Module(new Tile(inputType, outputType, accType, df, tree_reduction, max_simultaneous_matmuls, tileRows, tileColumns))) val meshT = mesh.transpose def pipe[T <: Data](valid: Bool, t: T, latency: Int): T = { // The default "Pipe" function apparently resets the valid signals to false.B. We would like to avoid using global // signals in the Mesh, so over here, we make it clear that the reset signal will never be asserted chisel3.withReset(false.B) { Pipe(valid, t, latency).bits } } // Chain tile_a_out -> tile_a_in (pipeline a across each row) // TODO clock-gate A signals with in_garbage for (r <- 0 until meshRows) { mesh(r).foldLeft(io.in_a(r)) { case (in_a, tile) => tile.io.in_a := ShiftRegister(in_a, tile_latency+1) tile.io.out_a } } // Chain tile_out_b -> tile_b_in (pipeline b across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft((io.in_b(c), io.in_valid(c))) { case ((in_b, valid), tile) => tile.io.in_b := pipe(valid.head, in_b, tile_latency+1) (tile.io.out_b, tile.io.out_valid) } } // Chain tile_out -> tile_propag (pipeline output across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft((io.in_d(c), io.in_valid(c))) { case ((in_propag, valid), tile) => tile.io.in_d := pipe(valid.head, in_propag, tile_latency+1) (tile.io.out_c, tile.io.out_valid) } } // Chain control signals (pipeline across each column) assert(!(mesh.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_))) for (c <- 0 until meshColumns) { meshT(c).foldLeft((io.in_control(c), io.in_valid(c))) { case ((in_ctrl, valid), tile) => (tile.io.in_control, in_ctrl, valid).zipped.foreach { case (tile_ctrl, ctrl, v) => tile_ctrl.shift := pipe(v, ctrl.shift, tile_latency+1) tile_ctrl.dataflow := pipe(v, ctrl.dataflow, tile_latency+1) tile_ctrl.propagate := pipe(v, ctrl.propagate, tile_latency+1) } (tile.io.out_control, tile.io.out_valid) } } // Chain in_valid (pipeline across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft(io.in_valid(c)) { case (in_v, tile) => tile.io.in_valid := ShiftRegister(in_v, tile_latency+1) tile.io.out_valid } } // Chain in_id (pipeline across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft(io.in_id(c)) { case (in_id, tile) => tile.io.in_id := ShiftRegister(in_id, tile_latency+1) tile.io.out_id } } // Chain in_last (pipeline across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft(io.in_last(c)) { case (in_last, tile) => tile.io.in_last := ShiftRegister(in_last, tile_latency+1) tile.io.out_last } } // Capture out_vec and out_control_vec (connect IO to bottom row of mesh) // (The only reason we have so many zips is because Scala doesn't provide a zipped function for Tuple4) for (((((((b, c), v), ctrl), id), last), tile) <- io.out_b zip io.out_c zip io.out_valid zip io.out_control zip io.out_id zip io.out_last zip mesh.last) { // TODO we pipelined this to make physical design easier. Consider removing these if possible // TODO shouldn't we clock-gate these signals with "garbage" as well? b := ShiftRegister(tile.io.out_b, output_delay) c := ShiftRegister(tile.io.out_c, output_delay) v := ShiftRegister(tile.io.out_valid, output_delay) ctrl := ShiftRegister(tile.io.out_control, output_delay) id := ShiftRegister(tile.io.out_id, output_delay) last := ShiftRegister(tile.io.out_last, output_delay) } }	module Mesh( // @[Mesh.scala:17:7] input clock, // @[Mesh.scala:17:7] input reset, // @[Mesh.scala:17:7] input [7:0] io_in_a_0_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_1_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_2_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_3_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_4_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_5_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_6_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_7_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_8_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_9_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_10_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_11_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_12_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_13_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_14_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_15_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_0_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_1_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_2_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_3_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_4_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_5_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_6_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_7_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_8_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_9_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_10_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_11_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_12_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_13_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_14_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_15_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_0_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_1_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_2_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_3_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_4_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_5_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_6_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_7_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_8_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_9_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_10_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_11_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_12_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_13_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_14_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_15_0, // @[Mesh.scala:22:14] input io_in_control_0_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_0_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_0_0_shift, // @[Mesh.scala:22:14] input io_in_control_1_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_1_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_1_0_shift, // @[Mesh.scala:22:14] input io_in_control_2_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_2_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_2_0_shift, // @[Mesh.scala:22:14] input io_in_control_3_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_3_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_3_0_shift, // @[Mesh.scala:22:14] input io_in_control_4_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_4_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_4_0_shift, // @[Mesh.scala:22:14] input io_in_control_5_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_5_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_5_0_shift, // @[Mesh.scala:22:14] input io_in_control_6_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_6_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_6_0_shift, // @[Mesh.scala:22:14] input io_in_control_7_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_7_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_7_0_shift, // @[Mesh.scala:22:14] input io_in_control_8_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_8_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_8_0_shift, // @[Mesh.scala:22:14] input io_in_control_9_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_9_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_9_0_shift, // @[Mesh.scala:22:14] input io_in_control_10_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_10_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_10_0_shift, // @[Mesh.scala:22:14] input io_in_control_11_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_11_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_11_0_shift, // @[Mesh.scala:22:14] input io_in_control_12_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_12_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_12_0_shift, // @[Mesh.scala:22:14] input io_in_control_13_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_13_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_13_0_shift, // @[Mesh.scala:22:14] input io_in_control_14_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_14_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_14_0_shift, // @[Mesh.scala:22:14] input io_in_control_15_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_15_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_15_0_shift, // @[Mesh.scala:22:14] input [2:0] io_in_id_0_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_1_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_2_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_3_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_4_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_5_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_6_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_7_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_8_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_9_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_10_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_11_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_12_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_13_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_14_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_15_0, // @[Mesh.scala:22:14] input io_in_last_0_0, // @[Mesh.scala:22:14] input io_in_last_1_0, // @[Mesh.scala:22:14] input io_in_last_2_0, // @[Mesh.scala:22:14] input io_in_last_3_0, // @[Mesh.scala:22:14] input io_in_last_4_0, // @[Mesh.scala:22:14] input io_in_last_5_0, // @[Mesh.scala:22:14] input io_in_last_6_0, // @[Mesh.scala:22:14] input io_in_last_7_0, // @[Mesh.scala:22:14] input io_in_last_8_0, // @[Mesh.scala:22:14] input io_in_last_9_0, // @[Mesh.scala:22:14] input io_in_last_10_0, // @[Mesh.scala:22:14] input io_in_last_11_0, // @[Mesh.scala:22:14] input io_in_last_12_0, // @[Mesh.scala:22:14] input io_in_last_13_0, // @[Mesh.scala:22:14] input io_in_last_14_0, // @[Mesh.scala:22:14] input io_in_last_15_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_0_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_1_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_2_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_3_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_4_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_5_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_6_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_7_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_8_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_9_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_10_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_11_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_12_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_13_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_14_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_15_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_0_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_1_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_2_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_3_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_4_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_5_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_6_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_7_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_8_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_9_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_10_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_11_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_12_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_13_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_14_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_15_0, // @[Mesh.scala:22:14] input io_in_valid_0_0, // @[Mesh.scala:22:14] input io_in_valid_1_0, // @[Mesh.scala:22:14] input io_in_valid_2_0, // @[Mesh.scala:22:14] input io_in_valid_3_0, // @[Mesh.scala:22:14] input io_in_valid_4_0, // @[Mesh.scala:22:14] input io_in_valid_5_0, // @[Mesh.scala:22:14] input io_in_valid_6_0, // @[Mesh.scala:22:14] input io_in_valid_7_0, // @[Mesh.scala:22:14] input io_in_valid_8_0, // @[Mesh.scala:22:14] input io_in_valid_9_0, // @[Mesh.scala:22:14] input io_in_valid_10_0, // @[Mesh.scala:22:14] input io_in_valid_11_0, // @[Mesh.scala:22:14] input io_in_valid_12_0, // @[Mesh.scala:22:14] input io_in_valid_13_0, // @[Mesh.scala:22:14] input io_in_valid_14_0, // @[Mesh.scala:22:14] input io_in_valid_15_0, // @[Mesh.scala:22:14] output io_out_valid_0_0, // @[Mesh.scala:22:14] output io_out_valid_1_0, // @[Mesh.scala:22:14] output io_out_valid_2_0, // @[Mesh.scala:22:14] output io_out_valid_3_0, // @[Mesh.scala:22:14] output io_out_valid_4_0, // @[Mesh.scala:22:14] output io_out_valid_5_0, // @[Mesh.scala:22:14] output io_out_valid_6_0, // @[Mesh.scala:22:14] output io_out_valid_7_0, // @[Mesh.scala:22:14] output io_out_valid_8_0, // @[Mesh.scala:22:14] output io_out_valid_9_0, // @[Mesh.scala:22:14] output io_out_valid_10_0, // @[Mesh.scala:22:14] output io_out_valid_11_0, // @[Mesh.scala:22:14] output io_out_valid_12_0, // @[Mesh.scala:22:14] output io_out_valid_13_0, // @[Mesh.scala:22:14] output io_out_valid_14_0, // @[Mesh.scala:22:14] output io_out_valid_15_0, // @[Mesh.scala:22:14] output io_out_control_0_0_dataflow, // @[Mesh.scala:22:14] output [2:0] io_out_id_0_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_1_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_2_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_3_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_4_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_5_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_6_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_7_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_8_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_9_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_10_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_11_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_12_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_13_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_14_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_15_0, // @[Mesh.scala:22:14] output io_out_last_0_0, // @[Mesh.scala:22:14] output io_out_last_1_0, // @[Mesh.scala:22:14] output io_out_last_2_0, // @[Mesh.scala:22:14] output io_out_last_3_0, // @[Mesh.scala:22:14] output io_out_last_4_0, // @[Mesh.scala:22:14] output io_out_last_5_0, // @[Mesh.scala:22:14] output io_out_last_6_0, // @[Mesh.scala:22:14] output io_out_last_7_0, // @[Mesh.scala:22:14] output io_out_last_8_0, // @[Mesh.scala:22:14] output io_out_last_9_0, // @[Mesh.scala:22:14] output io_out_last_10_0, // @[Mesh.scala:22:14] output io_out_last_11_0, // @[Mesh.scala:22:14] output io_out_last_12_0, // @[Mesh.scala:22:14] output io_out_last_13_0, // @[Mesh.scala:22:14] output io_out_last_14_0, // @[Mesh.scala:22:14] output io_out_last_15_0 // @[Mesh.scala:22:14] ); wire [19:0] _mesh_15_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] io_in_a_0_0_0 = io_in_a_0_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_1_0_0 = io_in_a_1_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_2_0_0 = io_in_a_2_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_3_0_0 = io_in_a_3_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_4_0_0 = io_in_a_4_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_5_0_0 = io_in_a_5_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_6_0_0 = io_in_a_6_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_7_0_0 = io_in_a_7_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_8_0_0 = io_in_a_8_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_9_0_0 = io_in_a_9_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_10_0_0 = io_in_a_10_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_11_0_0 = io_in_a_11_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_12_0_0 = io_in_a_12_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_13_0_0 = io_in_a_13_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_14_0_0 = io_in_a_14_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_15_0_0 = io_in_a_15_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_0_0_0 = io_in_b_0_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_1_0_0 = io_in_b_1_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_2_0_0 = io_in_b_2_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_3_0_0 = io_in_b_3_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_4_0_0 = io_in_b_4_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_5_0_0 = io_in_b_5_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_6_0_0 = io_in_b_6_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_7_0_0 = io_in_b_7_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_8_0_0 = io_in_b_8_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_9_0_0 = io_in_b_9_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_10_0_0 = io_in_b_10_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_11_0_0 = io_in_b_11_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_12_0_0 = io_in_b_12_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_13_0_0 = io_in_b_13_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_14_0_0 = io_in_b_14_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_15_0_0 = io_in_b_15_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_0_0_0 = io_in_d_0_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_1_0_0 = io_in_d_1_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_2_0_0 = io_in_d_2_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_3_0_0 = io_in_d_3_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_4_0_0 = io_in_d_4_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_5_0_0 = io_in_d_5_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_6_0_0 = io_in_d_6_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_7_0_0 = io_in_d_7_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_8_0_0 = io_in_d_8_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_9_0_0 = io_in_d_9_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_10_0_0 = io_in_d_10_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_11_0_0 = io_in_d_11_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_12_0_0 = io_in_d_12_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_13_0_0 = io_in_d_13_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_14_0_0 = io_in_d_14_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_15_0_0 = io_in_d_15_0; // @[Mesh.scala:17:7] wire io_in_control_0_0_dataflow_0 = io_in_control_0_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_0_0_propagate_0 = io_in_control_0_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_0_0_shift_0 = io_in_control_0_0_shift; // @[Mesh.scala:17:7] wire io_in_control_1_0_dataflow_0 = io_in_control_1_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_1_0_propagate_0 = io_in_control_1_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_1_0_shift_0 = io_in_control_1_0_shift; // @[Mesh.scala:17:7] wire io_in_control_2_0_dataflow_0 = io_in_control_2_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_2_0_propagate_0 = io_in_control_2_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_2_0_shift_0 = io_in_control_2_0_shift; // @[Mesh.scala:17:7] wire io_in_control_3_0_dataflow_0 = io_in_control_3_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_3_0_propagate_0 = io_in_control_3_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_3_0_shift_0 = io_in_control_3_0_shift; // @[Mesh.scala:17:7] wire io_in_control_4_0_dataflow_0 = io_in_control_4_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_4_0_propagate_0 = io_in_control_4_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_4_0_shift_0 = io_in_control_4_0_shift; // @[Mesh.scala:17:7] wire io_in_control_5_0_dataflow_0 = io_in_control_5_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_5_0_propagate_0 = io_in_control_5_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_5_0_shift_0 = io_in_control_5_0_shift; // @[Mesh.scala:17:7] wire io_in_control_6_0_dataflow_0 = io_in_control_6_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_6_0_propagate_0 = io_in_control_6_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_6_0_shift_0 = io_in_control_6_0_shift; // @[Mesh.scala:17:7] wire io_in_control_7_0_dataflow_0 = io_in_control_7_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_7_0_propagate_0 = io_in_control_7_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_7_0_shift_0 = io_in_control_7_0_shift; // @[Mesh.scala:17:7] wire io_in_control_8_0_dataflow_0 = io_in_control_8_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_8_0_propagate_0 = io_in_control_8_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_8_0_shift_0 = io_in_control_8_0_shift; // @[Mesh.scala:17:7] wire io_in_control_9_0_dataflow_0 = io_in_control_9_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_9_0_propagate_0 = io_in_control_9_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_9_0_shift_0 = io_in_control_9_0_shift; // @[Mesh.scala:17:7] wire io_in_control_10_0_dataflow_0 = io_in_control_10_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_10_0_propagate_0 = io_in_control_10_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_10_0_shift_0 = io_in_control_10_0_shift; // @[Mesh.scala:17:7] wire io_in_control_11_0_dataflow_0 = io_in_control_11_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_11_0_propagate_0 = io_in_control_11_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_11_0_shift_0 = io_in_control_11_0_shift; // @[Mesh.scala:17:7] wire io_in_control_12_0_dataflow_0 = io_in_control_12_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_12_0_propagate_0 = io_in_control_12_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_12_0_shift_0 = io_in_control_12_0_shift; // @[Mesh.scala:17:7] wire io_in_control_13_0_dataflow_0 = io_in_control_13_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_13_0_propagate_0 = io_in_control_13_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_13_0_shift_0 = io_in_control_13_0_shift; // @[Mesh.scala:17:7] wire io_in_control_14_0_dataflow_0 = io_in_control_14_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_14_0_propagate_0 = io_in_control_14_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_14_0_shift_0 = io_in_control_14_0_shift; // @[Mesh.scala:17:7] wire io_in_control_15_0_dataflow_0 = io_in_control_15_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_15_0_propagate_0 = io_in_control_15_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_15_0_shift_0 = io_in_control_15_0_shift; // @[Mesh.scala:17:7] wire [2:0] io_in_id_0_0_0 = io_in_id_0_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_1_0_0 = io_in_id_1_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_2_0_0 = io_in_id_2_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_3_0_0 = io_in_id_3_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_4_0_0 = io_in_id_4_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_5_0_0 = io_in_id_5_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_6_0_0 = io_in_id_6_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_7_0_0 = io_in_id_7_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_8_0_0 = io_in_id_8_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_9_0_0 = io_in_id_9_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_10_0_0 = io_in_id_10_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_11_0_0 = io_in_id_11_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_12_0_0 = io_in_id_12_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_13_0_0 = io_in_id_13_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_14_0_0 = io_in_id_14_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_15_0_0 = io_in_id_15_0; // @[Mesh.scala:17:7] wire io_in_last_0_0_0 = io_in_last_0_0; // @[Mesh.scala:17:7] wire io_in_last_1_0_0 = io_in_last_1_0; // @[Mesh.scala:17:7] wire io_in_last_2_0_0 = io_in_last_2_0; // @[Mesh.scala:17:7] wire io_in_last_3_0_0 = io_in_last_3_0; // @[Mesh.scala:17:7] wire io_in_last_4_0_0 = io_in_last_4_0; // @[Mesh.scala:17:7] wire io_in_last_5_0_0 = io_in_last_5_0; // @[Mesh.scala:17:7] wire io_in_last_6_0_0 = io_in_last_6_0; // @[Mesh.scala:17:7] wire io_in_last_7_0_0 = io_in_last_7_0; // @[Mesh.scala:17:7] wire io_in_last_8_0_0 = io_in_last_8_0; // @[Mesh.scala:17:7] wire io_in_last_9_0_0 = io_in_last_9_0; // @[Mesh.scala:17:7] wire io_in_last_10_0_0 = io_in_last_10_0; // @[Mesh.scala:17:7] wire io_in_last_11_0_0 = io_in_last_11_0; // @[Mesh.scala:17:7] wire io_in_last_12_0_0 = io_in_last_12_0; // @[Mesh.scala:17:7] wire io_in_last_13_0_0 = io_in_last_13_0; // @[Mesh.scala:17:7] wire io_in_last_14_0_0 = io_in_last_14_0; // @[Mesh.scala:17:7] wire io_in_last_15_0_0 = io_in_last_15_0; // @[Mesh.scala:17:7] wire io_in_valid_0_0_0 = io_in_valid_0_0; // @[Mesh.scala:17:7] wire io_in_valid_1_0_0 = io_in_valid_1_0; // @[Mesh.scala:17:7] wire io_in_valid_2_0_0 = io_in_valid_2_0; // @[Mesh.scala:17:7] wire io_in_valid_3_0_0 = io_in_valid_3_0; // @[Mesh.scala:17:7] wire io_in_valid_4_0_0 = io_in_valid_4_0; // @[Mesh.scala:17:7] wire io_in_valid_5_0_0 = io_in_valid_5_0; // @[Mesh.scala:17:7] wire io_in_valid_6_0_0 = io_in_valid_6_0; // @[Mesh.scala:17:7] wire io_in_valid_7_0_0 = io_in_valid_7_0; // @[Mesh.scala:17:7] wire io_in_valid_8_0_0 = io_in_valid_8_0; // @[Mesh.scala:17:7] wire io_in_valid_9_0_0 = io_in_valid_9_0; // @[Mesh.scala:17:7] wire io_in_valid_10_0_0 = io_in_valid_10_0; // @[Mesh.scala:17:7] wire io_in_valid_11_0_0 = io_in_valid_11_0; // @[Mesh.scala:17:7] wire io_in_valid_12_0_0 = io_in_valid_12_0; // @[Mesh.scala:17:7] wire io_in_valid_13_0_0 = io_in_valid_13_0; // @[Mesh.scala:17:7] wire io_in_valid_14_0_0 = io_in_valid_14_0; // @[Mesh.scala:17:7] wire io_in_valid_15_0_0 = io_in_valid_15_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_0_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_1_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_2_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_3_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_4_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_5_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_6_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_7_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_8_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_9_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_10_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_11_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_12_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_13_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_14_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_15_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_0_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_1_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_2_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_3_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_4_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_5_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_6_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_7_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_8_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_9_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_10_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_11_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_12_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_13_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_14_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_15_0_0; // @[Mesh.scala:17:7] wire io_out_valid_0_0_0; // @[Mesh.scala:17:7] wire io_out_valid_1_0_0; // @[Mesh.scala:17:7] wire io_out_valid_2_0_0; // @[Mesh.scala:17:7] wire io_out_valid_3_0_0; // @[Mesh.scala:17:7] wire io_out_valid_4_0_0; // @[Mesh.scala:17:7] wire io_out_valid_5_0_0; // @[Mesh.scala:17:7] wire io_out_valid_6_0_0; // @[Mesh.scala:17:7] wire io_out_valid_7_0_0; // @[Mesh.scala:17:7] wire io_out_valid_8_0_0; // @[Mesh.scala:17:7] wire io_out_valid_9_0_0; // @[Mesh.scala:17:7] wire io_out_valid_10_0_0; // @[Mesh.scala:17:7] wire io_out_valid_11_0_0; // @[Mesh.scala:17:7] wire io_out_valid_12_0_0; // @[Mesh.scala:17:7] wire io_out_valid_13_0_0; // @[Mesh.scala:17:7] wire io_out_valid_14_0_0; // @[Mesh.scala:17:7] wire io_out_valid_15_0_0; // @[Mesh.scala:17:7] wire io_out_control_0_0_dataflow_0; // @[Mesh.scala:17:7] wire io_out_control_0_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_0_0_shift; // @[Mesh.scala:17:7] wire io_out_control_1_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_1_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_1_0_shift; // @[Mesh.scala:17:7] wire io_out_control_2_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_2_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_2_0_shift; // @[Mesh.scala:17:7] wire io_out_control_3_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_3_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_3_0_shift; // @[Mesh.scala:17:7] wire io_out_control_4_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_4_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_4_0_shift; // @[Mesh.scala:17:7] wire io_out_control_5_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_5_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_5_0_shift; // @[Mesh.scala:17:7] wire io_out_control_6_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_6_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_6_0_shift; // @[Mesh.scala:17:7] wire io_out_control_7_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_7_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_7_0_shift; // @[Mesh.scala:17:7] wire io_out_control_8_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_8_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_8_0_shift; // @[Mesh.scala:17:7] wire io_out_control_9_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_9_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_9_0_shift; // @[Mesh.scala:17:7] wire io_out_control_10_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_10_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_10_0_shift; // @[Mesh.scala:17:7] wire io_out_control_11_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_11_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_11_0_shift; // @[Mesh.scala:17:7] wire io_out_control_12_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_12_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_12_0_shift; // @[Mesh.scala:17:7] wire io_out_control_13_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_13_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_13_0_shift; // @[Mesh.scala:17:7] wire io_out_control_14_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_14_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_14_0_shift; // @[Mesh.scala:17:7] wire io_out_control_15_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_15_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_15_0_shift; // @[Mesh.scala:17:7] wire [2:0] io_out_id_0_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_1_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_2_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_3_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_4_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_5_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_6_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_7_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_8_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_9_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_10_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_11_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_12_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_13_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_14_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_15_0_0; // @[Mesh.scala:17:7] wire io_out_last_0_0_0; // @[Mesh.scala:17:7] wire io_out_last_1_0_0; // @[Mesh.scala:17:7] wire io_out_last_2_0_0; // @[Mesh.scala:17:7] wire io_out_last_3_0_0; // @[Mesh.scala:17:7] wire io_out_last_4_0_0; // @[Mesh.scala:17:7] wire io_out_last_5_0_0; // @[Mesh.scala:17:7] wire io_out_last_6_0_0; // @[Mesh.scala:17:7] wire io_out_last_7_0_0; // @[Mesh.scala:17:7] wire io_out_last_8_0_0; // @[Mesh.scala:17:7] wire io_out_last_9_0_0; // @[Mesh.scala:17:7] wire io_out_last_10_0_0; // @[Mesh.scala:17:7] wire io_out_last_11_0_0; // @[Mesh.scala:17:7] wire io_out_last_12_0_0; // @[Mesh.scala:17:7] wire io_out_last_13_0_0; // @[Mesh.scala:17:7] wire io_out_last_14_0_0; // @[Mesh.scala:17:7] wire io_out_last_15_0_0; // @[Mesh.scala:17:7] reg [7:0] r_0; // @[Mesh.scala:53:38] reg [7:0] r_1_0; // @[Mesh.scala:53:38] reg [7:0] r_2_0; // @[Mesh.scala:53:38] reg [7:0] r_3_0; // @[Mesh.scala:53:38] reg [7:0] r_4_0; // @[Mesh.scala:53:38] reg [7:0] r_5_0; // @[Mesh.scala:53:38] reg [7:0] r_6_0; // @[Mesh.scala:53:38] reg [7:0] r_7_0; // @[Mesh.scala:53:38] reg [7:0] r_8_0; // @[Mesh.scala:53:38] reg [7:0] r_9_0; // @[Mesh.scala:53:38] reg [7:0] r_10_0; // @[Mesh.scala:53:38] reg [7:0] r_11_0; // @[Mesh.scala:53:38] reg [7:0] r_12_0; // @[Mesh.scala:53:38] reg [7:0] r_13_0; // @[Mesh.scala:53:38] reg [7:0] r_14_0; // @[Mesh.scala:53:38] reg [7:0] r_15_0; // @[Mesh.scala:53:38] reg [7:0] r_16_0; // @[Mesh.scala:53:38] reg [7:0] r_17_0; // @[Mesh.scala:53:38] reg [7:0] r_18_0; // @[Mesh.scala:53:38] reg [7:0] r_19_0; // @[Mesh.scala:53:38] reg [7:0] r_20_0; // @[Mesh.scala:53:38] reg [7:0] r_21_0; // @[Mesh.scala:53:38] reg [7:0] r_22_0; // @[Mesh.scala:53:38] reg [7:0] r_23_0; // @[Mesh.scala:53:38] reg [7:0] r_24_0; // @[Mesh.scala:53:38] reg [7:0] r_25_0; // @[Mesh.scala:53:38] reg [7:0] r_26_0; // @[Mesh.scala:53:38] reg [7:0] r_27_0; // @[Mesh.scala:53:38] reg [7:0] r_28_0; // @[Mesh.scala:53:38] reg [7:0] r_29_0; // @[Mesh.scala:53:38] reg [7:0] r_30_0; // @[Mesh.scala:53:38] reg [7:0] r_31_0; // @[Mesh.scala:53:38] reg [7:0] r_32_0; // @[Mesh.scala:53:38] reg [7:0] r_33_0; // @[Mesh.scala:53:38] reg [7:0] r_34_0; // @[Mesh.scala:53:38] reg [7:0] r_35_0; // @[Mesh.scala:53:38] reg [7:0] r_36_0; // @[Mesh.scala:53:38] reg [7:0] r_37_0; // @[Mesh.scala:53:38] reg [7:0] r_38_0; // @[Mesh.scala:53:38] reg [7:0] r_39_0; // @[Mesh.scala:53:38] reg [7:0] r_40_0; // @[Mesh.scala:53:38] reg [7:0] r_41_0; // @[Mesh.scala:53:38] reg [7:0] r_42_0; // @[Mesh.scala:53:38] reg [7:0] r_43_0; // @[Mesh.scala:53:38] reg [7:0] r_44_0; // @[Mesh.scala:53:38] reg [7:0] r_45_0; // @[Mesh.scala:53:38] reg [7:0] r_46_0; // @[Mesh.scala:53:38] reg [7:0] r_47_0; // @[Mesh.scala:53:38] reg [7:0] r_48_0; // @[Mesh.scala:53:38] reg [7:0] r_49_0; // @[Mesh.scala:53:38] reg [7:0] r_50_0; // @[Mesh.scala:53:38] reg [7:0] r_51_0; // @[Mesh.scala:53:38] reg [7:0] r_52_0; // @[Mesh.scala:53:38] reg [7:0] r_53_0; // @[Mesh.scala:53:38] reg [7:0] r_54_0; // @[Mesh.scala:53:38] reg [7:0] r_55_0; // @[Mesh.scala:53:38] reg [7:0] r_56_0; // @[Mesh.scala:53:38] reg [7:0] r_57_0; // @[Mesh.scala:53:38] reg [7:0] r_58_0; // @[Mesh.scala:53:38] reg [7:0] r_59_0; // @[Mesh.scala:53:38] reg [7:0] r_60_0; // @[Mesh.scala:53:38] reg [7:0] r_61_0; // @[Mesh.scala:53:38] reg [7:0] r_62_0; // @[Mesh.scala:53:38] reg [7:0] r_63_0; // @[Mesh.scala:53:38] reg [7:0] r_64_0; // @[Mesh.scala:53:38] reg [7:0] r_65_0; // @[Mesh.scala:53:38] reg [7:0] r_66_0; // @[Mesh.scala:53:38] reg [7:0] r_67_0; // @[Mesh.scala:53:38] reg [7:0] r_68_0; // @[Mesh.scala:53:38] reg [7:0] r_69_0; // @[Mesh.scala:53:38] reg [7:0] r_70_0; // @[Mesh.scala:53:38] reg [7:0] r_71_0; // @[Mesh.scala:53:38] reg [7:0] r_72_0; // @[Mesh.scala:53:38] reg [7:0] r_73_0; // @[Mesh.scala:53:38] reg [7:0] r_74_0; // @[Mesh.scala:53:38] reg [7:0] r_75_0; // @[Mesh.scala:53:38] reg [7:0] r_76_0; // @[Mesh.scala:53:38] reg [7:0] r_77_0; // @[Mesh.scala:53:38] reg [7:0] r_78_0; // @[Mesh.scala:53:38] reg [7:0] r_79_0; // @[Mesh.scala:53:38] reg [7:0] r_80_0; // @[Mesh.scala:53:38] reg [7:0] r_81_0; // @[Mesh.scala:53:38] reg [7:0] r_82_0; // @[Mesh.scala:53:38] reg [7:0] r_83_0; // @[Mesh.scala:53:38] reg [7:0] r_84_0; // @[Mesh.scala:53:38] reg [7:0] r_85_0; // @[Mesh.scala:53:38] reg [7:0] r_86_0; // @[Mesh.scala:53:38] reg [7:0] r_87_0; // @[Mesh.scala:53:38] reg [7:0] r_88_0; // @[Mesh.scala:53:38] reg [7:0] r_89_0; // @[Mesh.scala:53:38] reg [7:0] r_90_0; // @[Mesh.scala:53:38] reg [7:0] r_91_0; // @[Mesh.scala:53:38] reg [7:0] r_92_0; // @[Mesh.scala:53:38] reg [7:0] r_93_0; // @[Mesh.scala:53:38] reg [7:0] r_94_0; // @[Mesh.scala:53:38] reg [7:0] r_95_0; // @[Mesh.scala:53:38] reg [7:0] r_96_0; // @[Mesh.scala:53:38] reg [7:0] r_97_0; // @[Mesh.scala:53:38] reg [7:0] r_98_0; // @[Mesh.scala:53:38] reg [7:0] r_99_0; // @[Mesh.scala:53:38] reg [7:0] r_100_0; // @[Mesh.scala:53:38] reg [7:0] r_101_0; // @[Mesh.scala:53:38] reg [7:0] r_102_0; // @[Mesh.scala:53:38] reg [7:0] r_103_0; // @[Mesh.scala:53:38] reg [7:0] r_104_0; // @[Mesh.scala:53:38] reg [7:0] r_105_0; // @[Mesh.scala:53:38] reg [7:0] r_106_0; // @[Mesh.scala:53:38] reg [7:0] r_107_0; // @[Mesh.scala:53:38] reg [7:0] r_108_0; // @[Mesh.scala:53:38] reg [7:0] r_109_0; // @[Mesh.scala:53:38] reg [7:0] r_110_0; // @[Mesh.scala:53:38] reg [7:0] r_111_0; // @[Mesh.scala:53:38] reg [7:0] r_112_0; // @[Mesh.scala:53:38] reg [7:0] r_113_0; // @[Mesh.scala:53:38] reg [7:0] r_114_0; // @[Mesh.scala:53:38] reg [7:0] r_115_0; // @[Mesh.scala:53:38] reg [7:0] r_116_0; // @[Mesh.scala:53:38] reg [7:0] r_117_0; // @[Mesh.scala:53:38] reg [7:0] r_118_0; // @[Mesh.scala:53:38] reg [7:0] r_119_0; // @[Mesh.scala:53:38] reg [7:0] r_120_0; // @[Mesh.scala:53:38] reg [7:0] r_121_0; // @[Mesh.scala:53:38] reg [7:0] r_122_0; // @[Mesh.scala:53:38] reg [7:0] r_123_0; // @[Mesh.scala:53:38] reg [7:0] r_124_0; // @[Mesh.scala:53:38] reg [7:0] r_125_0; // @[Mesh.scala:53:38] reg [7:0] r_126_0; // @[Mesh.scala:53:38] reg [7:0] r_127_0; // @[Mesh.scala:53:38] reg [7:0] r_128_0; // @[Mesh.scala:53:38] reg [7:0] r_129_0; // @[Mesh.scala:53:38] reg [7:0] r_130_0; // @[Mesh.scala:53:38] reg [7:0] r_131_0; // @[Mesh.scala:53:38] reg [7:0] r_132_0; // @[Mesh.scala:53:38] reg [7:0] r_133_0; // @[Mesh.scala:53:38] reg [7:0] r_134_0; // @[Mesh.scala:53:38] reg [7:0] r_135_0; // @[Mesh.scala:53:38] reg [7:0] r_136_0; // @[Mesh.scala:53:38] reg [7:0] r_137_0; // @[Mesh.scala:53:38] reg [7:0] r_138_0; // @[Mesh.scala:53:38] reg [7:0] r_139_0; // @[Mesh.scala:53:38] reg [7:0] r_140_0; // @[Mesh.scala:53:38] reg [7:0] r_141_0; // @[Mesh.scala:53:38] reg [7:0] r_142_0; // @[Mesh.scala:53:38] reg [7:0] r_143_0; // @[Mesh.scala:53:38] reg [7:0] r_144_0; // @[Mesh.scala:53:38] reg [7:0] r_145_0; // @[Mesh.scala:53:38] reg [7:0] r_146_0; // @[Mesh.scala:53:38] reg [7:0] r_147_0; // @[Mesh.scala:53:38] reg [7:0] r_148_0; // @[Mesh.scala:53:38] reg [7:0] r_149_0; // @[Mesh.scala:53:38] reg [7:0] r_150_0; // @[Mesh.scala:53:38] reg [7:0] r_151_0; // @[Mesh.scala:53:38] reg [7:0] r_152_0; // @[Mesh.scala:53:38] reg [7:0] r_153_0; // @[Mesh.scala:53:38] reg [7:0] r_154_0; // @[Mesh.scala:53:38] reg [7:0] r_155_0; // @[Mesh.scala:53:38] reg [7:0] r_156_0; // @[Mesh.scala:53:38] reg [7:0] r_157_0; // @[Mesh.scala:53:38] reg [7:0] r_158_0; // @[Mesh.scala:53:38] reg [7:0] r_159_0; // @[Mesh.scala:53:38] reg [7:0] r_160_0; // @[Mesh.scala:53:38] reg [7:0] r_161_0; // @[Mesh.scala:53:38] reg [7:0] r_162_0; // @[Mesh.scala:53:38] reg [7:0] r_163_0; // @[Mesh.scala:53:38] reg [7:0] r_164_0; // @[Mesh.scala:53:38] reg [7:0] r_165_0; // @[Mesh.scala:53:38] reg [7:0] r_166_0; // @[Mesh.scala:53:38] reg [7:0] r_167_0; // @[Mesh.scala:53:38] reg [7:0] r_168_0; // @[Mesh.scala:53:38] reg [7:0] r_169_0; // @[Mesh.scala:53:38] reg [7:0] r_170_0; // @[Mesh.scala:53:38] reg [7:0] r_171_0; // @[Mesh.scala:53:38] reg [7:0] r_172_0; // @[Mesh.scala:53:38] reg [7:0] r_173_0; // @[Mesh.scala:53:38] reg [7:0] r_174_0; // @[Mesh.scala:53:38] reg [7:0] r_175_0; // @[Mesh.scala:53:38] reg [7:0] r_176_0; // @[Mesh.scala:53:38] reg [7:0] r_177_0; // @[Mesh.scala:53:38] reg [7:0] r_178_0; // @[Mesh.scala:53:38] reg [7:0] r_179_0; // @[Mesh.scala:53:38] reg [7:0] r_180_0; // @[Mesh.scala:53:38] reg [7:0] r_181_0; // @[Mesh.scala:53:38] reg [7:0] r_182_0; // @[Mesh.scala:53:38] reg [7:0] r_183_0; // @[Mesh.scala:53:38] reg [7:0] r_184_0; // @[Mesh.scala:53:38] reg [7:0] r_185_0; // @[Mesh.scala:53:38] reg [7:0] r_186_0; // @[Mesh.scala:53:38] reg [7:0] r_187_0; // @[Mesh.scala:53:38] reg [7:0] r_188_0; // @[Mesh.scala:53:38] reg [7:0] r_189_0; // @[Mesh.scala:53:38] reg [7:0] r_190_0; // @[Mesh.scala:53:38] reg [7:0] r_191_0; // @[Mesh.scala:53:38] reg [7:0] r_192_0; // @[Mesh.scala:53:38] reg [7:0] r_193_0; // @[Mesh.scala:53:38] reg [7:0] r_194_0; // @[Mesh.scala:53:38] reg [7:0] r_195_0; // @[Mesh.scala:53:38] reg [7:0] r_196_0; // @[Mesh.scala:53:38] reg [7:0] r_197_0; // @[Mesh.scala:53:38] reg [7:0] r_198_0; // @[Mesh.scala:53:38] reg [7:0] r_199_0; // @[Mesh.scala:53:38] reg [7:0] r_200_0; // @[Mesh.scala:53:38] reg [7:0] r_201_0; // @[Mesh.scala:53:38] reg [7:0] r_202_0; // @[Mesh.scala:53:38] reg [7:0] r_203_0; // @[Mesh.scala:53:38] reg [7:0] r_204_0; // @[Mesh.scala:53:38] reg [7:0] r_205_0; // @[Mesh.scala:53:38] reg [7:0] r_206_0; // @[Mesh.scala:53:38] reg [7:0] r_207_0; // @[Mesh.scala:53:38] reg [7:0] r_208_0; // @[Mesh.scala:53:38] reg [7:0] r_209_0; // @[Mesh.scala:53:38] reg [7:0] r_210_0; // @[Mesh.scala:53:38] reg [7:0] r_211_0; // @[Mesh.scala:53:38] reg [7:0] r_212_0; // @[Mesh.scala:53:38] reg [7:0] r_213_0; // @[Mesh.scala:53:38] reg [7:0] r_214_0; // @[Mesh.scala:53:38] reg [7:0] r_215_0; // @[Mesh.scala:53:38] reg [7:0] r_216_0; // @[Mesh.scala:53:38] reg [7:0] r_217_0; // @[Mesh.scala:53:38] reg [7:0] r_218_0; // @[Mesh.scala:53:38] reg [7:0] r_219_0; // @[Mesh.scala:53:38] reg [7:0] r_220_0; // @[Mesh.scala:53:38] reg [7:0] r_221_0; // @[Mesh.scala:53:38] reg [7:0] r_222_0; // @[Mesh.scala:53:38] reg [7:0] r_223_0; // @[Mesh.scala:53:38] reg [7:0] r_224_0; // @[Mesh.scala:53:38] reg [7:0] r_225_0; // @[Mesh.scala:53:38] reg [7:0] r_226_0; // @[Mesh.scala:53:38] reg [7:0] r_227_0; // @[Mesh.scala:53:38] reg [7:0] r_228_0; // @[Mesh.scala:53:38] reg [7:0] r_229_0; // @[Mesh.scala:53:38] reg [7:0] r_230_0; // @[Mesh.scala:53:38] reg [7:0] r_231_0; // @[Mesh.scala:53:38] reg [7:0] r_232_0; // @[Mesh.scala:53:38] reg [7:0] r_233_0; // @[Mesh.scala:53:38] reg [7:0] r_234_0; // @[Mesh.scala:53:38] reg [7:0] r_235_0; // @[Mesh.scala:53:38] reg [7:0] r_236_0; // @[Mesh.scala:53:38] reg [7:0] r_237_0; // @[Mesh.scala:53:38] reg [7:0] r_238_0; // @[Mesh.scala:53:38] reg [7:0] r_239_0; // @[Mesh.scala:53:38] reg [7:0] r_240_0; // @[Mesh.scala:53:38] reg [7:0] r_241_0; // @[Mesh.scala:53:38] reg [7:0] r_242_0; // @[Mesh.scala:53:38] reg [7:0] r_243_0; // @[Mesh.scala:53:38] reg [7:0] r_244_0; // @[Mesh.scala:53:38] reg [7:0] r_245_0; // @[Mesh.scala:53:38] reg [7:0] r_246_0; // @[Mesh.scala:53:38] reg [7:0] r_247_0; // @[Mesh.scala:53:38] reg [7:0] r_248_0; // @[Mesh.scala:53:38] reg [7:0] r_249_0; // @[Mesh.scala:53:38] reg [7:0] r_250_0; // @[Mesh.scala:53:38] reg [7:0] r_251_0; // @[Mesh.scala:53:38] reg [7:0] r_252_0; // @[Mesh.scala:53:38] reg [7:0] r_253_0; // @[Mesh.scala:53:38] reg [7:0] r_254_0; // @[Mesh.scala:53:38] reg [7:0] r_255_0; // @[Mesh.scala:53:38] reg pipe_v; // @[Valid.scala:141:24] wire pipe_out_valid = pipe_v; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_bits_0 = pipe_b_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_1; // @[Valid.scala:141:24] wire pipe_out_1_valid = pipe_v_1; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_1_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_1_bits_0 = pipe_b_1_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_2; // @[Valid.scala:141:24] wire pipe_out_2_valid = pipe_v_2; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_2_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_2_bits_0 = pipe_b_2_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_3; // @[Valid.scala:141:24] wire pipe_out_3_valid = pipe_v_3; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_3_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_3_bits_0 = pipe_b_3_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_4; // @[Valid.scala:141:24] wire pipe_out_4_valid = pipe_v_4; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_4_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_4_bits_0 = pipe_b_4_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_5; // @[Valid.scala:141:24] wire pipe_out_5_valid = pipe_v_5; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_5_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_5_bits_0 = pipe_b_5_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_6; // @[Valid.scala:141:24] wire pipe_out_6_valid = pipe_v_6; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_6_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_6_bits_0 = pipe_b_6_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_7; // @[Valid.scala:141:24] wire pipe_out_7_valid = pipe_v_7; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_7_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_7_bits_0 = pipe_b_7_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_8; // @[Valid.scala:141:24] wire pipe_out_8_valid = pipe_v_8; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_8_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_8_bits_0 = pipe_b_8_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_9; // @[Valid.scala:141:24] wire pipe_out_9_valid = pipe_v_9; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_9_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_9_bits_0 = pipe_b_9_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_10; // @[Valid.scala:141:24] wire pipe_out_10_valid = pipe_v_10; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_10_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_10_bits_0 = pipe_b_10_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_11; // @[Valid.scala:141:24] wire pipe_out_11_valid = pipe_v_11; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_11_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_11_bits_0 = pipe_b_11_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_12; // @[Valid.scala:141:24] wire pipe_out_12_valid = pipe_v_12; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_12_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_12_bits_0 = pipe_b_12_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_13; // @[Valid.scala:141:24] wire pipe_out_13_valid = pipe_v_13; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_13_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_13_bits_0 = pipe_b_13_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_14; // @[Valid.scala:141:24] wire pipe_out_14_valid = pipe_v_14; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_14_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_14_bits_0 = pipe_b_14_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_15; // @[Valid.scala:141:24] wire pipe_out_15_valid = pipe_v_15; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_15_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_15_bits_0 = pipe_b_15_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_16; // @[Valid.scala:141:24] wire pipe_out_16_valid = pipe_v_16; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_16_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_16_bits_0 = pipe_b_16_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_17; // @[Valid.scala:141:24] wire pipe_out_17_valid = pipe_v_17; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_17_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_17_bits_0 = pipe_b_17_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_18; // @[Valid.scala:141:24] wire pipe_out_18_valid = pipe_v_18; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_18_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_18_bits_0 = pipe_b_18_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_19; // @[Valid.scala:141:24] wire pipe_out_19_valid = pipe_v_19; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_19_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_19_bits_0 = pipe_b_19_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_20; // @[Valid.scala:141:24] wire pipe_out_20_valid = pipe_v_20; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_20_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_20_bits_0 = pipe_b_20_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_21; // @[Valid.scala:141:24] wire pipe_out_21_valid = pipe_v_21; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_21_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_21_bits_0 = pipe_b_21_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_22; // @[Valid.scala:141:24] wire pipe_out_22_valid = pipe_v_22; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_22_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_22_bits_0 = pipe_b_22_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_23; // @[Valid.scala:141:24] wire pipe_out_23_valid = pipe_v_23; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_23_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_23_bits_0 = pipe_b_23_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_24; // @[Valid.scala:141:24] wire pipe_out_24_valid = pipe_v_24; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_24_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_24_bits_0 = pipe_b_24_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_25; // @[Valid.scala:141:24] wire pipe_out_25_valid = pipe_v_25; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_25_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_25_bits_0 = pipe_b_25_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_26; // @[Valid.scala:141:24] wire pipe_out_26_valid = pipe_v_26; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_26_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_26_bits_0 = pipe_b_26_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_27; // @[Valid.scala:141:24] wire pipe_out_27_valid = pipe_v_27; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_27_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_27_bits_0 = pipe_b_27_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_28; // @[Valid.scala:141:24] wire pipe_out_28_valid = pipe_v_28; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_28_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_28_bits_0 = pipe_b_28_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_29; // @[Valid.scala:141:24] wire pipe_out_29_valid = pipe_v_29; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_29_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_29_bits_0 = pipe_b_29_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_30; // @[Valid.scala:141:24] wire pipe_out_30_valid = pipe_v_30; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_30_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_30_bits_0 = pipe_b_30_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_31; // @[Valid.scala:141:24] wire pipe_out_31_valid = pipe_v_31; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_31_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_31_bits_0 = pipe_b_31_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_32; // @[Valid.scala:141:24] wire pipe_out_32_valid = pipe_v_32; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_32_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_32_bits_0 = pipe_b_32_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_33; // @[Valid.scala:141:24] wire pipe_out_33_valid = pipe_v_33; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_33_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_33_bits_0 = pipe_b_33_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_34; // @[Valid.scala:141:24] wire pipe_out_34_valid = pipe_v_34; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_34_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_34_bits_0 = pipe_b_34_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_35; // @[Valid.scala:141:24] wire pipe_out_35_valid = pipe_v_35; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_35_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_35_bits_0 = pipe_b_35_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_36; // @[Valid.scala:141:24] wire pipe_out_36_valid = pipe_v_36; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_36_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_36_bits_0 = pipe_b_36_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_37; // @[Valid.scala:141:24] wire pipe_out_37_valid = pipe_v_37; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_37_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_37_bits_0 = pipe_b_37_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_38; // @[Valid.scala:141:24] wire pipe_out_38_valid = pipe_v_38; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_38_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_38_bits_0 = pipe_b_38_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_39; // @[Valid.scala:141:24] wire pipe_out_39_valid = pipe_v_39; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_39_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_39_bits_0 = pipe_b_39_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_40; // @[Valid.scala:141:24] wire pipe_out_40_valid = pipe_v_40; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_40_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_40_bits_0 = pipe_b_40_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_41; // @[Valid.scala:141:24] wire pipe_out_41_valid = pipe_v_41; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_41_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_41_bits_0 = pipe_b_41_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_42; // @[Valid.scala:141:24] wire pipe_out_42_valid = pipe_v_42; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_42_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_42_bits_0 = pipe_b_42_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_43; // @[Valid.scala:141:24] wire pipe_out_43_valid = pipe_v_43; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_43_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_43_bits_0 = pipe_b_43_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_44; // @[Valid.scala:141:24] wire pipe_out_44_valid = pipe_v_44; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_44_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_44_bits_0 = pipe_b_44_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_45; // @[Valid.scala:141:24] wire pipe_out_45_valid = pipe_v_45; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_45_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_45_bits_0 = pipe_b_45_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_46; // @[Valid.scala:141:24] wire pipe_out_46_valid = pipe_v_46; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_46_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_46_bits_0 = pipe_b_46_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_47; // @[Valid.scala:141:24] wire pipe_out_47_valid = pipe_v_47; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_47_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_47_bits_0 = pipe_b_47_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_48; // @[Valid.scala:141:24] wire pipe_out_48_valid = pipe_v_48; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_48_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_48_bits_0 = pipe_b_48_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_49; // @[Valid.scala:141:24] wire pipe_out_49_valid = pipe_v_49; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_49_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_49_bits_0 = pipe_b_49_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_50; // @[Valid.scala:141:24] wire pipe_out_50_valid = pipe_v_50; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_50_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_50_bits_0 = pipe_b_50_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_51; // @[Valid.scala:141:24] wire pipe_out_51_valid = pipe_v_51; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_51_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_51_bits_0 = pipe_b_51_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_52; // @[Valid.scala:141:24] wire pipe_out_52_valid = pipe_v_52; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_52_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_52_bits_0 = pipe_b_52_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_53; // @[Valid.scala:141:24] wire pipe_out_53_valid = pipe_v_53; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_53_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_53_bits_0 = pipe_b_53_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_54; // @[Valid.scala:141:24] wire pipe_out_54_valid = pipe_v_54; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_54_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_54_bits_0 = pipe_b_54_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_55; // @[Valid.scala:141:24] wire pipe_out_55_valid = pipe_v_55; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_55_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_55_bits_0 = pipe_b_55_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_56; // @[Valid.scala:141:24] wire pipe_out_56_valid = pipe_v_56; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_56_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_56_bits_0 = pipe_b_56_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_57; // @[Valid.scala:141:24] wire pipe_out_57_valid = pipe_v_57; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_57_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_57_bits_0 = pipe_b_57_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_58; // @[Valid.scala:141:24] wire pipe_out_58_valid = pipe_v_58; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_58_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_58_bits_0 = pipe_b_58_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_59; // @[Valid.scala:141:24] wire pipe_out_59_valid = pipe_v_59; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_59_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_59_bits_0 = pipe_b_59_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_60; // @[Valid.scala:141:24] wire pipe_out_60_valid = pipe_v_60; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_60_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_60_bits_0 = pipe_b_60_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_61; // @[Valid.scala:141:24] wire pipe_out_61_valid = pipe_v_61; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_61_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_61_bits_0 = pipe_b_61_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_62; // @[Valid.scala:141:24] wire pipe_out_62_valid = pipe_v_62; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_62_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_62_bits_0 = pipe_b_62_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_63; // @[Valid.scala:141:24] wire pipe_out_63_valid = pipe_v_63; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_63_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_63_bits_0 = pipe_b_63_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_64; // @[Valid.scala:141:24] wire pipe_out_64_valid = pipe_v_64; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_64_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_64_bits_0 = pipe_b_64_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_65; // @[Valid.scala:141:24] wire pipe_out_65_valid = pipe_v_65; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_65_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_65_bits_0 = pipe_b_65_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_66; // @[Valid.scala:141:24] wire pipe_out_66_valid = pipe_v_66; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_66_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_66_bits_0 = pipe_b_66_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_67; // @[Valid.scala:141:24] wire pipe_out_67_valid = pipe_v_67; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_67_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_67_bits_0 = pipe_b_67_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_68; // @[Valid.scala:141:24] wire pipe_out_68_valid = pipe_v_68; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_68_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_68_bits_0 = pipe_b_68_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_69; // @[Valid.scala:141:24] wire pipe_out_69_valid = pipe_v_69; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_69_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_69_bits_0 = pipe_b_69_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_70; // @[Valid.scala:141:24] wire pipe_out_70_valid = pipe_v_70; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_70_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_70_bits_0 = pipe_b_70_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_71; // @[Valid.scala:141:24] wire pipe_out_71_valid = pipe_v_71; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_71_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_71_bits_0 = pipe_b_71_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_72; // @[Valid.scala:141:24] wire pipe_out_72_valid = pipe_v_72; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_72_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_72_bits_0 = pipe_b_72_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_73; // @[Valid.scala:141:24] wire pipe_out_73_valid = pipe_v_73; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_73_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_73_bits_0 = pipe_b_73_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_74; // @[Valid.scala:141:24] wire pipe_out_74_valid = pipe_v_74; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_74_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_74_bits_0 = pipe_b_74_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_75; // @[Valid.scala:141:24] wire pipe_out_75_valid = pipe_v_75; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_75_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_75_bits_0 = pipe_b_75_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_76; // @[Valid.scala:141:24] wire pipe_out_76_valid = pipe_v_76; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_76_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_76_bits_0 = pipe_b_76_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_77; // @[Valid.scala:141:24] wire pipe_out_77_valid = pipe_v_77; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_77_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_77_bits_0 = pipe_b_77_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_78; // @[Valid.scala:141:24] wire pipe_out_78_valid = pipe_v_78; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_78_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_78_bits_0 = pipe_b_78_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_79; // @[Valid.scala:141:24] wire pipe_out_79_valid = pipe_v_79; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_79_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_79_bits_0 = pipe_b_79_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_80; // @[Valid.scala:141:24] wire pipe_out_80_valid = pipe_v_80; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_80_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_80_bits_0 = pipe_b_80_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_81; // @[Valid.scala:141:24] wire pipe_out_81_valid = pipe_v_81; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_81_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_81_bits_0 = pipe_b_81_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_82; // @[Valid.scala:141:24] wire pipe_out_82_valid = pipe_v_82; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_82_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_82_bits_0 = pipe_b_82_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_83; // @[Valid.scala:141:24] wire pipe_out_83_valid = pipe_v_83; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_83_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_83_bits_0 = pipe_b_83_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_84; // @[Valid.scala:141:24] wire pipe_out_84_valid = pipe_v_84; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_84_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_84_bits_0 = pipe_b_84_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_85; // @[Valid.scala:141:24] wire pipe_out_85_valid = pipe_v_85; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_85_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_85_bits_0 = pipe_b_85_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_86; // @[Valid.scala:141:24] wire pipe_out_86_valid = pipe_v_86; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_86_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_86_bits_0 = pipe_b_86_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_87; // @[Valid.scala:141:24] wire pipe_out_87_valid = pipe_v_87; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_87_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_87_bits_0 = pipe_b_87_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_88; // @[Valid.scala:141:24] wire pipe_out_88_valid = pipe_v_88; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_88_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_88_bits_0 = pipe_b_88_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_89; // @[Valid.scala:141:24] wire pipe_out_89_valid = pipe_v_89; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_89_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_89_bits_0 = pipe_b_89_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_90; // @[Valid.scala:141:24] wire pipe_out_90_valid = pipe_v_90; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_90_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_90_bits_0 = pipe_b_90_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_91; // @[Valid.scala:141:24] wire pipe_out_91_valid = pipe_v_91; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_91_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_91_bits_0 = pipe_b_91_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_92; // @[Valid.scala:141:24] wire pipe_out_92_valid = pipe_v_92; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_92_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_92_bits_0 = pipe_b_92_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_93; // @[Valid.scala:141:24] wire pipe_out_93_valid = pipe_v_93; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_93_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_93_bits_0 = pipe_b_93_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_94; // @[Valid.scala:141:24] wire pipe_out_94_valid = pipe_v_94; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_94_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_94_bits_0 = pipe_b_94_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_95; // @[Valid.scala:141:24] wire pipe_out_95_valid = pipe_v_95; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_95_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_95_bits_0 = pipe_b_95_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_96; // @[Valid.scala:141:24] wire pipe_out_96_valid = pipe_v_96; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_96_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_96_bits_0 = pipe_b_96_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_97; // @[Valid.scala:141:24] wire pipe_out_97_valid = pipe_v_97; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_97_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_97_bits_0 = pipe_b_97_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_98; // @[Valid.scala:141:24] wire pipe_out_98_valid = pipe_v_98; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_98_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_98_bits_0 = pipe_b_98_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_99; // @[Valid.scala:141:24] wire pipe_out_99_valid = pipe_v_99; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_99_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_99_bits_0 = pipe_b_99_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_100; // @[Valid.scala:141:24] wire pipe_out_100_valid = pipe_v_100; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_100_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_100_bits_0 = pipe_b_100_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_101; // @[Valid.scala:141:24] wire pipe_out_101_valid = pipe_v_101; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_101_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_101_bits_0 = pipe_b_101_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_102; // @[Valid.scala:141:24] wire pipe_out_102_valid = pipe_v_102; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_102_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_102_bits_0 = pipe_b_102_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_103; // @[Valid.scala:141:24] wire pipe_out_103_valid = pipe_v_103; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_103_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_103_bits_0 = pipe_b_103_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_104; // @[Valid.scala:141:24] wire pipe_out_104_valid = pipe_v_104; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_104_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_104_bits_0 = pipe_b_104_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_105; // @[Valid.scala:141:24] wire pipe_out_105_valid = pipe_v_105; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_105_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_105_bits_0 = pipe_b_105_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_106; // @[Valid.scala:141:24] wire pipe_out_106_valid = pipe_v_106; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_106_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_106_bits_0 = pipe_b_106_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_107; // @[Valid.scala:141:24] wire pipe_out_107_valid = pipe_v_107; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_107_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_107_bits_0 = pipe_b_107_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_108; // @[Valid.scala:141:24] wire pipe_out_108_valid = pipe_v_108; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_108_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_108_bits_0 = pipe_b_108_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_109; // @[Valid.scala:141:24] wire pipe_out_109_valid = pipe_v_109; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_109_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_109_bits_0 = pipe_b_109_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_110; // @[Valid.scala:141:24] wire pipe_out_110_valid = pipe_v_110; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_110_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_110_bits_0 = pipe_b_110_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_111; // @[Valid.scala:141:24] wire pipe_out_111_valid = pipe_v_111; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_111_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_111_bits_0 = pipe_b_111_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_112; // @[Valid.scala:141:24] wire pipe_out_112_valid = pipe_v_112; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_112_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_112_bits_0 = pipe_b_112_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_113; // @[Valid.scala:141:24] wire pipe_out_113_valid = pipe_v_113; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_113_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_113_bits_0 = pipe_b_113_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_114; // @[Valid.scala:141:24] wire pipe_out_114_valid = pipe_v_114; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_114_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_114_bits_0 = pipe_b_114_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_115; // @[Valid.scala:141:24] wire pipe_out_115_valid = pipe_v_115; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_115_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_115_bits_0 = pipe_b_115_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_116; // @[Valid.scala:141:24] wire pipe_out_116_valid = pipe_v_116; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_116_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_116_bits_0 = pipe_b_116_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_117; // @[Valid.scala:141:24] wire pipe_out_117_valid = pipe_v_117; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_117_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_117_bits_0 = pipe_b_117_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_118; // @[Valid.scala:141:24] wire pipe_out_118_valid = pipe_v_118; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_118_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_118_bits_0 = pipe_b_118_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_119; // @[Valid.scala:141:24] wire pipe_out_119_valid = pipe_v_119; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_119_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_119_bits_0 = pipe_b_119_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_120; // @[Valid.scala:141:24] wire pipe_out_120_valid = pipe_v_120; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_120_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_120_bits_0 = pipe_b_120_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_121; // @[Valid.scala:141:24] wire pipe_out_121_valid = pipe_v_121; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_121_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_121_bits_0 = pipe_b_121_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_122; // @[Valid.scala:141:24] wire pipe_out_122_valid = pipe_v_122; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_122_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_122_bits_0 = pipe_b_122_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_123; // @[Valid.scala:141:24] wire pipe_out_123_valid = pipe_v_123; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_123_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_123_bits_0 = pipe_b_123_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_124; // @[Valid.scala:141:24] wire pipe_out_124_valid = pipe_v_124; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_124_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_124_bits_0 = pipe_b_124_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_125; // @[Valid.scala:141:24] wire pipe_out_125_valid = pipe_v_125; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_125_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_125_bits_0 = pipe_b_125_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_126; // @[Valid.scala:141:24] wire pipe_out_126_valid = pipe_v_126; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_126_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_126_bits_0 = pipe_b_126_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_127; // @[Valid.scala:141:24] wire pipe_out_127_valid = pipe_v_127; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_127_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_127_bits_0 = pipe_b_127_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_128; // @[Valid.scala:141:24] wire pipe_out_128_valid = pipe_v_128; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_128_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_128_bits_0 = pipe_b_128_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_129; // @[Valid.scala:141:24] wire pipe_out_129_valid = pipe_v_129; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_129_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_129_bits_0 = pipe_b_129_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_130; // @[Valid.scala:141:24] wire pipe_out_130_valid = pipe_v_130; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_130_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_130_bits_0 = pipe_b_130_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_131; // @[Valid.scala:141:24] wire pipe_out_131_valid = pipe_v_131; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_131_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_131_bits_0 = pipe_b_131_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_132; // @[Valid.scala:141:24] wire pipe_out_132_valid = pipe_v_132; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_132_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_132_bits_0 = pipe_b_132_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_133; // @[Valid.scala:141:24] wire pipe_out_133_valid = pipe_v_133; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_133_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_133_bits_0 = pipe_b_133_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_134; // @[Valid.scala:141:24] wire pipe_out_134_valid = pipe_v_134; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_134_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_134_bits_0 = pipe_b_134_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_135; // @[Valid.scala:141:24] wire pipe_out_135_valid = pipe_v_135; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_135_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_135_bits_0 = pipe_b_135_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_136; // @[Valid.scala:141:24] wire pipe_out_136_valid = pipe_v_136; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_136_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_136_bits_0 = pipe_b_136_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_137; // @[Valid.scala:141:24] wire pipe_out_137_valid = pipe_v_137; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_137_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_137_bits_0 = pipe_b_137_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_138; // @[Valid.scala:141:24] wire pipe_out_138_valid = pipe_v_138; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_138_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_138_bits_0 = pipe_b_138_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_139; // @[Valid.scala:141:24] wire pipe_out_139_valid = pipe_v_139; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_139_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_139_bits_0 = pipe_b_139_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_140; // @[Valid.scala:141:24] wire pipe_out_140_valid = pipe_v_140; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_140_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_140_bits_0 = pipe_b_140_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_141; // @[Valid.scala:141:24] wire pipe_out_141_valid = pipe_v_141; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_141_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_141_bits_0 = pipe_b_141_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_142; // @[Valid.scala:141:24] wire pipe_out_142_valid = pipe_v_142; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_142_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_142_bits_0 = pipe_b_142_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_143; // @[Valid.scala:141:24] wire pipe_out_143_valid = pipe_v_143; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_143_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_143_bits_0 = pipe_b_143_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_144; // @[Valid.scala:141:24] wire pipe_out_144_valid = pipe_v_144; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_144_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_144_bits_0 = pipe_b_144_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_145; // @[Valid.scala:141:24] wire pipe_out_145_valid = pipe_v_145; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_145_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_145_bits_0 = pipe_b_145_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_146; // @[Valid.scala:141:24] wire pipe_out_146_valid = pipe_v_146; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_146_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_146_bits_0 = pipe_b_146_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_147; // @[Valid.scala:141:24] wire pipe_out_147_valid = pipe_v_147; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_147_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_147_bits_0 = pipe_b_147_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_148; // @[Valid.scala:141:24] wire pipe_out_148_valid = pipe_v_148; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_148_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_148_bits_0 = pipe_b_148_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_149; // @[Valid.scala:141:24] wire pipe_out_149_valid = pipe_v_149; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_149_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_149_bits_0 = pipe_b_149_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_150; // @[Valid.scala:141:24] wire pipe_out_150_valid = pipe_v_150; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_150_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_150_bits_0 = pipe_b_150_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_151; // @[Valid.scala:141:24] wire pipe_out_151_valid = pipe_v_151; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_151_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_151_bits_0 = pipe_b_151_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_152; // @[Valid.scala:141:24] wire pipe_out_152_valid = pipe_v_152; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_152_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_152_bits_0 = pipe_b_152_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_153; // @[Valid.scala:141:24] wire pipe_out_153_valid = pipe_v_153; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_153_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_153_bits_0 = pipe_b_153_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_154; // @[Valid.scala:141:24] wire pipe_out_154_valid = pipe_v_154; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_154_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_154_bits_0 = pipe_b_154_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_155; // @[Valid.scala:141:24] wire pipe_out_155_valid = pipe_v_155; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_155_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_155_bits_0 = pipe_b_155_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_156; // @[Valid.scala:141:24] wire pipe_out_156_valid = pipe_v_156; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_156_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_156_bits_0 = pipe_b_156_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_157; // @[Valid.scala:141:24] wire pipe_out_157_valid = pipe_v_157; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_157_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_157_bits_0 = pipe_b_157_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_158; // @[Valid.scala:141:24] wire pipe_out_158_valid = pipe_v_158; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_158_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_158_bits_0 = pipe_b_158_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_159; // @[Valid.scala:141:24] wire pipe_out_159_valid = pipe_v_159; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_159_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_159_bits_0 = pipe_b_159_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_160; // @[Valid.scala:141:24] wire pipe_out_160_valid = pipe_v_160; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_160_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_160_bits_0 = pipe_b_160_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_161; // @[Valid.scala:141:24] wire pipe_out_161_valid = pipe_v_161; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_161_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_161_bits_0 = pipe_b_161_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_162; // @[Valid.scala:141:24] wire pipe_out_162_valid = pipe_v_162; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_162_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_162_bits_0 = pipe_b_162_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_163; // @[Valid.scala:141:24] wire pipe_out_163_valid = pipe_v_163; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_163_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_163_bits_0 = pipe_b_163_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_164; // @[Valid.scala:141:24] wire pipe_out_164_valid = pipe_v_164; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_164_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_164_bits_0 = pipe_b_164_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_165; // @[Valid.scala:141:24] wire pipe_out_165_valid = pipe_v_165; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_165_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_165_bits_0 = pipe_b_165_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_166; // @[Valid.scala:141:24] wire pipe_out_166_valid = pipe_v_166; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_166_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_166_bits_0 = pipe_b_166_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_167; // @[Valid.scala:141:24] wire pipe_out_167_valid = pipe_v_167; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_167_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_167_bits_0 = pipe_b_167_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_168; // @[Valid.scala:141:24] wire pipe_out_168_valid = pipe_v_168; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_168_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_168_bits_0 = pipe_b_168_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_169; // @[Valid.scala:141:24] wire pipe_out_169_valid = pipe_v_169; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_169_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_169_bits_0 = pipe_b_169_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_170; // @[Valid.scala:141:24] wire pipe_out_170_valid = pipe_v_170; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_170_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_170_bits_0 = pipe_b_170_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_171; // @[Valid.scala:141:24] wire pipe_out_171_valid = pipe_v_171; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_171_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_171_bits_0 = pipe_b_171_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_172; // @[Valid.scala:141:24] wire pipe_out_172_valid = pipe_v_172; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_172_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_172_bits_0 = pipe_b_172_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_173; // @[Valid.scala:141:24] wire pipe_out_173_valid = pipe_v_173; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_173_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_173_bits_0 = pipe_b_173_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_174; // @[Valid.scala:141:24] wire pipe_out_174_valid = pipe_v_174; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_174_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_174_bits_0 = pipe_b_174_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_175; // @[Valid.scala:141:24] wire pipe_out_175_valid = pipe_v_175; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_175_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_175_bits_0 = pipe_b_175_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_176; // @[Valid.scala:141:24] wire pipe_out_176_valid = pipe_v_176; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_176_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_176_bits_0 = pipe_b_176_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_177; // @[Valid.scala:141:24] wire pipe_out_177_valid = pipe_v_177; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_177_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_177_bits_0 = pipe_b_177_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_178; // @[Valid.scala:141:24] wire pipe_out_178_valid = pipe_v_178; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_178_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_178_bits_0 = pipe_b_178_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_179; // @[Valid.scala:141:24] wire pipe_out_179_valid = pipe_v_179; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_179_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_179_bits_0 = pipe_b_179_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_180; // @[Valid.scala:141:24] wire pipe_out_180_valid = pipe_v_180; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_180_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_180_bits_0 = pipe_b_180_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_181; // @[Valid.scala:141:24] wire pipe_out_181_valid = pipe_v_181; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_181_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_181_bits_0 = pipe_b_181_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_182; // @[Valid.scala:141:24] wire pipe_out_182_valid = pipe_v_182; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_182_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_182_bits_0 = pipe_b_182_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_183; // @[Valid.scala:141:24] wire pipe_out_183_valid = pipe_v_183; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_183_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_183_bits_0 = pipe_b_183_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_184; // @[Valid.scala:141:24] wire pipe_out_184_valid = pipe_v_184; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_184_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_184_bits_0 = pipe_b_184_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_185; // @[Valid.scala:141:24] wire pipe_out_185_valid = pipe_v_185; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_185_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_185_bits_0 = pipe_b_185_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_186; // @[Valid.scala:141:24] wire pipe_out_186_valid = pipe_v_186; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_186_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_186_bits_0 = pipe_b_186_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_187; // @[Valid.scala:141:24] wire pipe_out_187_valid = pipe_v_187; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_187_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_187_bits_0 = pipe_b_187_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_188; // @[Valid.scala:141:24] wire pipe_out_188_valid = pipe_v_188; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_188_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_188_bits_0 = pipe_b_188_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_189; // @[Valid.scala:141:24] wire pipe_out_189_valid = pipe_v_189; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_189_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_189_bits_0 = pipe_b_189_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_190; // @[Valid.scala:141:24] wire pipe_out_190_valid = pipe_v_190; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_190_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_190_bits_0 = pipe_b_190_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_191; // @[Valid.scala:141:24] wire pipe_out_191_valid = pipe_v_191; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_191_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_191_bits_0 = pipe_b_191_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_192; // @[Valid.scala:141:24] wire pipe_out_192_valid = pipe_v_192; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_192_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_192_bits_0 = pipe_b_192_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_193; // @[Valid.scala:141:24] wire pipe_out_193_valid = pipe_v_193; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_193_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_193_bits_0 = pipe_b_193_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_194; // @[Valid.scala:141:24] wire pipe_out_194_valid = pipe_v_194; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_194_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_194_bits_0 = pipe_b_194_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_195; // @[Valid.scala:141:24] wire pipe_out_195_valid = pipe_v_195; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_195_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_195_bits_0 = pipe_b_195_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_196; // @[Valid.scala:141:24] wire pipe_out_196_valid = pipe_v_196; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_196_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_196_bits_0 = pipe_b_196_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_197; // @[Valid.scala:141:24] wire pipe_out_197_valid = pipe_v_197; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_197_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_197_bits_0 = pipe_b_197_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_198; // @[Valid.scala:141:24] wire pipe_out_198_valid = pipe_v_198; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_198_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_198_bits_0 = pipe_b_198_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_199; // @[Valid.scala:141:24] wire pipe_out_199_valid = pipe_v_199; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_199_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_199_bits_0 = pipe_b_199_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_200; // @[Valid.scala:141:24] wire pipe_out_200_valid = pipe_v_200; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_200_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_200_bits_0 = pipe_b_200_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_201; // @[Valid.scala:141:24] wire pipe_out_201_valid = pipe_v_201; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_201_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_201_bits_0 = pipe_b_201_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_202; // @[Valid.scala:141:24] wire pipe_out_202_valid = pipe_v_202; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_202_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_202_bits_0 = pipe_b_202_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_203; // @[Valid.scala:141:24] wire pipe_out_203_valid = pipe_v_203; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_203_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_203_bits_0 = pipe_b_203_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_204; // @[Valid.scala:141:24] wire pipe_out_204_valid = pipe_v_204; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_204_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_204_bits_0 = pipe_b_204_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_205; // @[Valid.scala:141:24] wire pipe_out_205_valid = pipe_v_205; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_205_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_205_bits_0 = pipe_b_205_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_206; // @[Valid.scala:141:24] wire pipe_out_206_valid = pipe_v_206; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_206_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_206_bits_0 = pipe_b_206_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_207; // @[Valid.scala:141:24] wire pipe_out_207_valid = pipe_v_207; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_207_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_207_bits_0 = pipe_b_207_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_208; // @[Valid.scala:141:24] wire pipe_out_208_valid = pipe_v_208; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_208_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_208_bits_0 = pipe_b_208_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_209; // @[Valid.scala:141:24] wire pipe_out_209_valid = pipe_v_209; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_209_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_209_bits_0 = pipe_b_209_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_210; // @[Valid.scala:141:24] wire pipe_out_210_valid = pipe_v_210; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_210_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_210_bits_0 = pipe_b_210_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_211; // @[Valid.scala:141:24] wire pipe_out_211_valid = pipe_v_211; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_211_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_211_bits_0 = pipe_b_211_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_212; // @[Valid.scala:141:24] wire pipe_out_212_valid = pipe_v_212; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_212_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_212_bits_0 = pipe_b_212_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_213; // @[Valid.scala:141:24] wire pipe_out_213_valid = pipe_v_213; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_213_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_213_bits_0 = pipe_b_213_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_214; // @[Valid.scala:141:24] wire pipe_out_214_valid = pipe_v_214; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_214_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_214_bits_0 = pipe_b_214_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_215; // @[Valid.scala:141:24] wire pipe_out_215_valid = pipe_v_215; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_215_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_215_bits_0 = pipe_b_215_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_216; // @[Valid.scala:141:24] wire pipe_out_216_valid = pipe_v_216; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_216_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_216_bits_0 = pipe_b_216_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_217; // @[Valid.scala:141:24] wire pipe_out_217_valid = pipe_v_217; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_217_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_217_bits_0 = pipe_b_217_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_218; // @[Valid.scala:141:24] wire pipe_out_218_valid = pipe_v_218; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_218_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_218_bits_0 = pipe_b_218_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_219; // @[Valid.scala:141:24] wire pipe_out_219_valid = pipe_v_219; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_219_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_219_bits_0 = pipe_b_219_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_220; // @[Valid.scala:141:24] wire pipe_out_220_valid = pipe_v_220; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_220_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_220_bits_0 = pipe_b_220_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_221; // @[Valid.scala:141:24] wire pipe_out_221_valid = pipe_v_221; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_221_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_221_bits_0 = pipe_b_221_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_222; // @[Valid.scala:141:24] wire pipe_out_222_valid = pipe_v_222; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_222_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_222_bits_0 = pipe_b_222_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_223; // @[Valid.scala:141:24] wire pipe_out_223_valid = pipe_v_223; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_223_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_223_bits_0 = pipe_b_223_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_224; // @[Valid.scala:141:24] wire pipe_out_224_valid = pipe_v_224; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_224_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_224_bits_0 = pipe_b_224_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_225; // @[Valid.scala:141:24] wire pipe_out_225_valid = pipe_v_225; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_225_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_225_bits_0 = pipe_b_225_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_226; // @[Valid.scala:141:24] wire pipe_out_226_valid = pipe_v_226; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_226_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_226_bits_0 = pipe_b_226_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_227; // @[Valid.scala:141:24] wire pipe_out_227_valid = pipe_v_227; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_227_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_227_bits_0 = pipe_b_227_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_228; // @[Valid.scala:141:24] wire pipe_out_228_valid = pipe_v_228; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_228_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_228_bits_0 = pipe_b_228_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_229; // @[Valid.scala:141:24] wire pipe_out_229_valid = pipe_v_229; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_229_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_229_bits_0 = pipe_b_229_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_230; // @[Valid.scala:141:24] wire pipe_out_230_valid = pipe_v_230; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_230_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_230_bits_0 = pipe_b_230_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_231; // @[Valid.scala:141:24] wire pipe_out_231_valid = pipe_v_231; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_231_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_231_bits_0 = pipe_b_231_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_232; // @[Valid.scala:141:24] wire pipe_out_232_valid = pipe_v_232; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_232_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_232_bits_0 = pipe_b_232_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_233; // @[Valid.scala:141:24] wire pipe_out_233_valid = pipe_v_233; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_233_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_233_bits_0 = pipe_b_233_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_234; // @[Valid.scala:141:24] wire pipe_out_234_valid = pipe_v_234; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_234_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_234_bits_0 = pipe_b_234_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_235; // @[Valid.scala:141:24] wire pipe_out_235_valid = pipe_v_235; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_235_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_235_bits_0 = pipe_b_235_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_236; // @[Valid.scala:141:24] wire pipe_out_236_valid = pipe_v_236; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_236_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_236_bits_0 = pipe_b_236_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_237; // @[Valid.scala:141:24] wire pipe_out_237_valid = pipe_v_237; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_237_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_237_bits_0 = pipe_b_237_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_238; // @[Valid.scala:141:24] wire pipe_out_238_valid = pipe_v_238; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_238_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_238_bits_0 = pipe_b_238_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_239; // @[Valid.scala:141:24] wire pipe_out_239_valid = pipe_v_239; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_239_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_239_bits_0 = pipe_b_239_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_240; // @[Valid.scala:141:24] wire pipe_out_240_valid = pipe_v_240; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_240_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_240_bits_0 = pipe_b_240_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_241; // @[Valid.scala:141:24] wire pipe_out_241_valid = pipe_v_241; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_241_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_241_bits_0 = pipe_b_241_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_242; // @[Valid.scala:141:24] wire pipe_out_242_valid = pipe_v_242; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_242_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_242_bits_0 = pipe_b_242_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_243; // @[Valid.scala:141:24] wire pipe_out_243_valid = pipe_v_243; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_243_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_243_bits_0 = pipe_b_243_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_244; // @[Valid.scala:141:24] wire pipe_out_244_valid = pipe_v_244; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_244_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_244_bits_0 = pipe_b_244_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_245; // @[Valid.scala:141:24] wire pipe_out_245_valid = pipe_v_245; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_245_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_245_bits_0 = pipe_b_245_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_246; // @[Valid.scala:141:24] wire pipe_out_246_valid = pipe_v_246; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_246_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_246_bits_0 = pipe_b_246_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_247; // @[Valid.scala:141:24] wire pipe_out_247_valid = pipe_v_247; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_247_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_247_bits_0 = pipe_b_247_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_248; // @[Valid.scala:141:24] wire pipe_out_248_valid = pipe_v_248; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_248_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_248_bits_0 = pipe_b_248_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_249; // @[Valid.scala:141:24] wire pipe_out_249_valid = pipe_v_249; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_249_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_249_bits_0 = pipe_b_249_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_250; // @[Valid.scala:141:24] wire pipe_out_250_valid = pipe_v_250; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_250_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_250_bits_0 = pipe_b_250_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_251; // @[Valid.scala:141:24] wire pipe_out_251_valid = pipe_v_251; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_251_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_251_bits_0 = pipe_b_251_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_252; // @[Valid.scala:141:24] wire pipe_out_252_valid = pipe_v_252; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_252_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_252_bits_0 = pipe_b_252_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_253; // @[Valid.scala:141:24] wire pipe_out_253_valid = pipe_v_253; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_253_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_253_bits_0 = pipe_b_253_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_254; // @[Valid.scala:141:24] wire pipe_out_254_valid = pipe_v_254; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_254_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_254_bits_0 = pipe_b_254_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_255; // @[Valid.scala:141:24] wire pipe_out_255_valid = pipe_v_255; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_255_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_255_bits_0 = pipe_b_255_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_256; // @[Valid.scala:141:24] wire pipe_out_256_valid = pipe_v_256; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_256_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_256_bits_0 = pipe_b_256_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_257; // @[Valid.scala:141:24] wire pipe_out_257_valid = pipe_v_257; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_257_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_257_bits_0 = pipe_b_257_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_258; // @[Valid.scala:141:24] wire pipe_out_258_valid = pipe_v_258; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_258_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_258_bits_0 = pipe_b_258_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_259; // @[Valid.scala:141:24] wire pipe_out_259_valid = pipe_v_259; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_259_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_259_bits_0 = pipe_b_259_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_260; // @[Valid.scala:141:24] wire pipe_out_260_valid = pipe_v_260; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_260_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_260_bits_0 = pipe_b_260_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_261; // @[Valid.scala:141:24] wire pipe_out_261_valid = pipe_v_261; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_261_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_261_bits_0 = pipe_b_261_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_262; // @[Valid.scala:141:24] wire pipe_out_262_valid = pipe_v_262; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_262_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_262_bits_0 = pipe_b_262_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_263; // @[Valid.scala:141:24] wire pipe_out_263_valid = pipe_v_263; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_263_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_263_bits_0 = pipe_b_263_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_264; // @[Valid.scala:141:24] wire pipe_out_264_valid = pipe_v_264; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_264_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_264_bits_0 = pipe_b_264_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_265; // @[Valid.scala:141:24] wire pipe_out_265_valid = pipe_v_265; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_265_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_265_bits_0 = pipe_b_265_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_266; // @[Valid.scala:141:24] wire pipe_out_266_valid = pipe_v_266; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_266_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_266_bits_0 = pipe_b_266_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_267; // @[Valid.scala:141:24] wire pipe_out_267_valid = pipe_v_267; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_267_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_267_bits_0 = pipe_b_267_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_268; // @[Valid.scala:141:24] wire pipe_out_268_valid = pipe_v_268; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_268_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_268_bits_0 = pipe_b_268_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_269; // @[Valid.scala:141:24] wire pipe_out_269_valid = pipe_v_269; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_269_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_269_bits_0 = pipe_b_269_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_270; // @[Valid.scala:141:24] wire pipe_out_270_valid = pipe_v_270; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_270_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_270_bits_0 = pipe_b_270_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_271; // @[Valid.scala:141:24] wire pipe_out_271_valid = pipe_v_271; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_271_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_271_bits_0 = pipe_b_271_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_272; // @[Valid.scala:141:24] wire pipe_out_272_valid = pipe_v_272; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_272_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_272_bits_0 = pipe_b_272_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_273; // @[Valid.scala:141:24] wire pipe_out_273_valid = pipe_v_273; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_273_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_273_bits_0 = pipe_b_273_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_274; // @[Valid.scala:141:24] wire pipe_out_274_valid = pipe_v_274; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_274_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_274_bits_0 = pipe_b_274_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_275; // @[Valid.scala:141:24] wire pipe_out_275_valid = pipe_v_275; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_275_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_275_bits_0 = pipe_b_275_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_276; // @[Valid.scala:141:24] wire pipe_out_276_valid = pipe_v_276; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_276_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_276_bits_0 = pipe_b_276_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_277; // @[Valid.scala:141:24] wire pipe_out_277_valid = pipe_v_277; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_277_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_277_bits_0 = pipe_b_277_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_278; // @[Valid.scala:141:24] wire pipe_out_278_valid = pipe_v_278; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_278_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_278_bits_0 = pipe_b_278_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_279; // @[Valid.scala:141:24] wire pipe_out_279_valid = pipe_v_279; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_279_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_279_bits_0 = pipe_b_279_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_280; // @[Valid.scala:141:24] wire pipe_out_280_valid = pipe_v_280; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_280_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_280_bits_0 = pipe_b_280_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_281; // @[Valid.scala:141:24] wire pipe_out_281_valid = pipe_v_281; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_281_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_281_bits_0 = pipe_b_281_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_282; // @[Valid.scala:141:24] wire pipe_out_282_valid = pipe_v_282; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_282_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_282_bits_0 = pipe_b_282_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_283; // @[Valid.scala:141:24] wire pipe_out_283_valid = pipe_v_283; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_283_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_283_bits_0 = pipe_b_283_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_284; // @[Valid.scala:141:24] wire pipe_out_284_valid = pipe_v_284; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_284_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_284_bits_0 = pipe_b_284_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_285; // @[Valid.scala:141:24] wire pipe_out_285_valid = pipe_v_285; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_285_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_285_bits_0 = pipe_b_285_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_286; // @[Valid.scala:141:24] wire pipe_out_286_valid = pipe_v_286; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_286_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_286_bits_0 = pipe_b_286_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_287; // @[Valid.scala:141:24] wire pipe_out_287_valid = pipe_v_287; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_287_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_287_bits_0 = pipe_b_287_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_288; // @[Valid.scala:141:24] wire pipe_out_288_valid = pipe_v_288; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_288_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_288_bits_0 = pipe_b_288_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_289; // @[Valid.scala:141:24] wire pipe_out_289_valid = pipe_v_289; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_289_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_289_bits_0 = pipe_b_289_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_290; // @[Valid.scala:141:24] wire pipe_out_290_valid = pipe_v_290; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_290_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_290_bits_0 = pipe_b_290_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_291; // @[Valid.scala:141:24] wire pipe_out_291_valid = pipe_v_291; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_291_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_291_bits_0 = pipe_b_291_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_292; // @[Valid.scala:141:24] wire pipe_out_292_valid = pipe_v_292; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_292_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_292_bits_0 = pipe_b_292_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_293; // @[Valid.scala:141:24] wire pipe_out_293_valid = pipe_v_293; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_293_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_293_bits_0 = pipe_b_293_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_294; // @[Valid.scala:141:24] wire pipe_out_294_valid = pipe_v_294; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_294_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_294_bits_0 = pipe_b_294_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_295; // @[Valid.scala:141:24] wire pipe_out_295_valid = pipe_v_295; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_295_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_295_bits_0 = pipe_b_295_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_296; // @[Valid.scala:141:24] wire pipe_out_296_valid = pipe_v_296; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_296_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_296_bits_0 = pipe_b_296_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_297; // @[Valid.scala:141:24] wire pipe_out_297_valid = pipe_v_297; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_297_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_297_bits_0 = pipe_b_297_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_298; // @[Valid.scala:141:24] wire pipe_out_298_valid = pipe_v_298; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_298_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_298_bits_0 = pipe_b_298_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_299; // @[Valid.scala:141:24] wire pipe_out_299_valid = pipe_v_299; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_299_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_299_bits_0 = pipe_b_299_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_300; // @[Valid.scala:141:24] wire pipe_out_300_valid = pipe_v_300; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_300_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_300_bits_0 = pipe_b_300_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_301; // @[Valid.scala:141:24] wire pipe_out_301_valid = pipe_v_301; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_301_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_301_bits_0 = pipe_b_301_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_302; // @[Valid.scala:141:24] wire pipe_out_302_valid = pipe_v_302; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_302_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_302_bits_0 = pipe_b_302_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_303; // @[Valid.scala:141:24] wire pipe_out_303_valid = pipe_v_303; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_303_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_303_bits_0 = pipe_b_303_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_304; // @[Valid.scala:141:24] wire pipe_out_304_valid = pipe_v_304; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_304_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_304_bits_0 = pipe_b_304_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_305; // @[Valid.scala:141:24] wire pipe_out_305_valid = pipe_v_305; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_305_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_305_bits_0 = pipe_b_305_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_306; // @[Valid.scala:141:24] wire pipe_out_306_valid = pipe_v_306; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_306_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_306_bits_0 = pipe_b_306_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_307; // @[Valid.scala:141:24] wire pipe_out_307_valid = pipe_v_307; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_307_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_307_bits_0 = pipe_b_307_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_308; // @[Valid.scala:141:24] wire pipe_out_308_valid = pipe_v_308; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_308_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_308_bits_0 = pipe_b_308_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_309; // @[Valid.scala:141:24] wire pipe_out_309_valid = pipe_v_309; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_309_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_309_bits_0 = pipe_b_309_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_310; // @[Valid.scala:141:24] wire pipe_out_310_valid = pipe_v_310; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_310_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_310_bits_0 = pipe_b_310_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_311; // @[Valid.scala:141:24] wire pipe_out_311_valid = pipe_v_311; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_311_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_311_bits_0 = pipe_b_311_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_312; // @[Valid.scala:141:24] wire pipe_out_312_valid = pipe_v_312; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_312_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_312_bits_0 = pipe_b_312_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_313; // @[Valid.scala:141:24] wire pipe_out_313_valid = pipe_v_313; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_313_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_313_bits_0 = pipe_b_313_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_314; // @[Valid.scala:141:24] wire pipe_out_314_valid = pipe_v_314; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_314_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_314_bits_0 = pipe_b_314_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_315; // @[Valid.scala:141:24] wire pipe_out_315_valid = pipe_v_315; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_315_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_315_bits_0 = pipe_b_315_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_316; // @[Valid.scala:141:24] wire pipe_out_316_valid = pipe_v_316; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_316_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_316_bits_0 = pipe_b_316_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_317; // @[Valid.scala:141:24] wire pipe_out_317_valid = pipe_v_317; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_317_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_317_bits_0 = pipe_b_317_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_318; // @[Valid.scala:141:24] wire pipe_out_318_valid = pipe_v_318; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_318_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_318_bits_0 = pipe_b_318_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_319; // @[Valid.scala:141:24] wire pipe_out_319_valid = pipe_v_319; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_319_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_319_bits_0 = pipe_b_319_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_320; // @[Valid.scala:141:24] wire pipe_out_320_valid = pipe_v_320; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_320_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_320_bits_0 = pipe_b_320_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_321; // @[Valid.scala:141:24] wire pipe_out_321_valid = pipe_v_321; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_321_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_321_bits_0 = pipe_b_321_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_322; // @[Valid.scala:141:24] wire pipe_out_322_valid = pipe_v_322; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_322_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_322_bits_0 = pipe_b_322_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_323; // @[Valid.scala:141:24] wire pipe_out_323_valid = pipe_v_323; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_323_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_323_bits_0 = pipe_b_323_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_324; // @[Valid.scala:141:24] wire pipe_out_324_valid = pipe_v_324; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_324_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_324_bits_0 = pipe_b_324_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_325; // @[Valid.scala:141:24] wire pipe_out_325_valid = pipe_v_325; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_325_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_325_bits_0 = pipe_b_325_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_326; // @[Valid.scala:141:24] wire pipe_out_326_valid = pipe_v_326; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_326_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_326_bits_0 = pipe_b_326_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_327; // @[Valid.scala:141:24] wire pipe_out_327_valid = pipe_v_327; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_327_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_327_bits_0 = pipe_b_327_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_328; // @[Valid.scala:141:24] wire pipe_out_328_valid = pipe_v_328; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_328_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_328_bits_0 = pipe_b_328_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_329; // @[Valid.scala:141:24] wire pipe_out_329_valid = pipe_v_329; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_329_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_329_bits_0 = pipe_b_329_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_330; // @[Valid.scala:141:24] wire pipe_out_330_valid = pipe_v_330; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_330_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_330_bits_0 = pipe_b_330_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_331; // @[Valid.scala:141:24] wire pipe_out_331_valid = pipe_v_331; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_331_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_331_bits_0 = pipe_b_331_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_332; // @[Valid.scala:141:24] wire pipe_out_332_valid = pipe_v_332; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_332_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_332_bits_0 = pipe_b_332_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_333; // @[Valid.scala:141:24] wire pipe_out_333_valid = pipe_v_333; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_333_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_333_bits_0 = pipe_b_333_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_334; // @[Valid.scala:141:24] wire pipe_out_334_valid = pipe_v_334; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_334_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_334_bits_0 = pipe_b_334_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_335; // @[Valid.scala:141:24] wire pipe_out_335_valid = pipe_v_335; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_335_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_335_bits_0 = pipe_b_335_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_336; // @[Valid.scala:141:24] wire pipe_out_336_valid = pipe_v_336; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_336_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_336_bits_0 = pipe_b_336_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_337; // @[Valid.scala:141:24] wire pipe_out_337_valid = pipe_v_337; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_337_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_337_bits_0 = pipe_b_337_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_338; // @[Valid.scala:141:24] wire pipe_out_338_valid = pipe_v_338; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_338_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_338_bits_0 = pipe_b_338_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_339; // @[Valid.scala:141:24] wire pipe_out_339_valid = pipe_v_339; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_339_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_339_bits_0 = pipe_b_339_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_340; // @[Valid.scala:141:24] wire pipe_out_340_valid = pipe_v_340; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_340_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_340_bits_0 = pipe_b_340_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_341; // @[Valid.scala:141:24] wire pipe_out_341_valid = pipe_v_341; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_341_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_341_bits_0 = pipe_b_341_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_342; // @[Valid.scala:141:24] wire pipe_out_342_valid = pipe_v_342; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_342_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_342_bits_0 = pipe_b_342_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_343; // @[Valid.scala:141:24] wire pipe_out_343_valid = pipe_v_343; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_343_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_343_bits_0 = pipe_b_343_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_344; // @[Valid.scala:141:24] wire pipe_out_344_valid = pipe_v_344; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_344_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_344_bits_0 = pipe_b_344_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_345; // @[Valid.scala:141:24] wire pipe_out_345_valid = pipe_v_345; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_345_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_345_bits_0 = pipe_b_345_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_346; // @[Valid.scala:141:24] wire pipe_out_346_valid = pipe_v_346; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_346_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_346_bits_0 = pipe_b_346_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_347; // @[Valid.scala:141:24] wire pipe_out_347_valid = pipe_v_347; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_347_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_347_bits_0 = pipe_b_347_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_348; // @[Valid.scala:141:24] wire pipe_out_348_valid = pipe_v_348; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_348_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_348_bits_0 = pipe_b_348_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_349; // @[Valid.scala:141:24] wire pipe_out_349_valid = pipe_v_349; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_349_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_349_bits_0 = pipe_b_349_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_350; // @[Valid.scala:141:24] wire pipe_out_350_valid = pipe_v_350; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_350_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_350_bits_0 = pipe_b_350_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_351; // @[Valid.scala:141:24] wire pipe_out_351_valid = pipe_v_351; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_351_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_351_bits_0 = pipe_b_351_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_352; // @[Valid.scala:141:24] wire pipe_out_352_valid = pipe_v_352; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_352_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_352_bits_0 = pipe_b_352_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_353; // @[Valid.scala:141:24] wire pipe_out_353_valid = pipe_v_353; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_353_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_353_bits_0 = pipe_b_353_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_354; // @[Valid.scala:141:24] wire pipe_out_354_valid = pipe_v_354; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_354_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_354_bits_0 = pipe_b_354_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_355; // @[Valid.scala:141:24] wire pipe_out_355_valid = pipe_v_355; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_355_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_355_bits_0 = pipe_b_355_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_356; // @[Valid.scala:141:24] wire pipe_out_356_valid = pipe_v_356; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_356_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_356_bits_0 = pipe_b_356_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_357; // @[Valid.scala:141:24] wire pipe_out_357_valid = pipe_v_357; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_357_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_357_bits_0 = pipe_b_357_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_358; // @[Valid.scala:141:24] wire pipe_out_358_valid = pipe_v_358; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_358_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_358_bits_0 = pipe_b_358_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_359; // @[Valid.scala:141:24] wire pipe_out_359_valid = pipe_v_359; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_359_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_359_bits_0 = pipe_b_359_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_360; // @[Valid.scala:141:24] wire pipe_out_360_valid = pipe_v_360; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_360_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_360_bits_0 = pipe_b_360_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_361; // @[Valid.scala:141:24] wire pipe_out_361_valid = pipe_v_361; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_361_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_361_bits_0 = pipe_b_361_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_362; // @[Valid.scala:141:24] wire pipe_out_362_valid = pipe_v_362; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_362_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_362_bits_0 = pipe_b_362_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_363; // @[Valid.scala:141:24] wire pipe_out_363_valid = pipe_v_363; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_363_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_363_bits_0 = pipe_b_363_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_364; // @[Valid.scala:141:24] wire pipe_out_364_valid = pipe_v_364; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_364_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_364_bits_0 = pipe_b_364_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_365; // @[Valid.scala:141:24] wire pipe_out_365_valid = pipe_v_365; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_365_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_365_bits_0 = pipe_b_365_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_366; // @[Valid.scala:141:24] wire pipe_out_366_valid = pipe_v_366; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_366_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_366_bits_0 = pipe_b_366_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_367; // @[Valid.scala:141:24] wire pipe_out_367_valid = pipe_v_367; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_367_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_367_bits_0 = pipe_b_367_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_368; // @[Valid.scala:141:24] wire pipe_out_368_valid = pipe_v_368; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_368_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_368_bits_0 = pipe_b_368_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_369; // @[Valid.scala:141:24] wire pipe_out_369_valid = pipe_v_369; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_369_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_369_bits_0 = pipe_b_369_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_370; // @[Valid.scala:141:24] wire pipe_out_370_valid = pipe_v_370; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_370_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_370_bits_0 = pipe_b_370_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_371; // @[Valid.scala:141:24] wire pipe_out_371_valid = pipe_v_371; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_371_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_371_bits_0 = pipe_b_371_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_372; // @[Valid.scala:141:24] wire pipe_out_372_valid = pipe_v_372; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_372_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_372_bits_0 = pipe_b_372_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_373; // @[Valid.scala:141:24] wire pipe_out_373_valid = pipe_v_373; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_373_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_373_bits_0 = pipe_b_373_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_374; // @[Valid.scala:141:24] wire pipe_out_374_valid = pipe_v_374; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_374_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_374_bits_0 = pipe_b_374_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_375; // @[Valid.scala:141:24] wire pipe_out_375_valid = pipe_v_375; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_375_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_375_bits_0 = pipe_b_375_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_376; // @[Valid.scala:141:24] wire pipe_out_376_valid = pipe_v_376; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_376_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_376_bits_0 = pipe_b_376_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_377; // @[Valid.scala:141:24] wire pipe_out_377_valid = pipe_v_377; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_377_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_377_bits_0 = pipe_b_377_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_378; // @[Valid.scala:141:24] wire pipe_out_378_valid = pipe_v_378; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_378_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_378_bits_0 = pipe_b_378_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_379; // @[Valid.scala:141:24] wire pipe_out_379_valid = pipe_v_379; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_379_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_379_bits_0 = pipe_b_379_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_380; // @[Valid.scala:141:24] wire pipe_out_380_valid = pipe_v_380; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_380_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_380_bits_0 = pipe_b_380_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_381; // @[Valid.scala:141:24] wire pipe_out_381_valid = pipe_v_381; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_381_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_381_bits_0 = pipe_b_381_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_382; // @[Valid.scala:141:24] wire pipe_out_382_valid = pipe_v_382; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_382_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_382_bits_0 = pipe_b_382_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_383; // @[Valid.scala:141:24] wire pipe_out_383_valid = pipe_v_383; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_383_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_383_bits_0 = pipe_b_383_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_384; // @[Valid.scala:141:24] wire pipe_out_384_valid = pipe_v_384; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_384_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_384_bits_0 = pipe_b_384_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_385; // @[Valid.scala:141:24] wire pipe_out_385_valid = pipe_v_385; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_385_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_385_bits_0 = pipe_b_385_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_386; // @[Valid.scala:141:24] wire pipe_out_386_valid = pipe_v_386; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_386_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_386_bits_0 = pipe_b_386_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_387; // @[Valid.scala:141:24] wire pipe_out_387_valid = pipe_v_387; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_387_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_387_bits_0 = pipe_b_387_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_388; // @[Valid.scala:141:24] wire pipe_out_388_valid = pipe_v_388; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_388_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_388_bits_0 = pipe_b_388_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_389; // @[Valid.scala:141:24] wire pipe_out_389_valid = pipe_v_389; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_389_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_389_bits_0 = pipe_b_389_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_390; // @[Valid.scala:141:24] wire pipe_out_390_valid = pipe_v_390; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_390_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_390_bits_0 = pipe_b_390_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_391; // @[Valid.scala:141:24] wire pipe_out_391_valid = pipe_v_391; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_391_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_391_bits_0 = pipe_b_391_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_392; // @[Valid.scala:141:24] wire pipe_out_392_valid = pipe_v_392; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_392_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_392_bits_0 = pipe_b_392_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_393; // @[Valid.scala:141:24] wire pipe_out_393_valid = pipe_v_393; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_393_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_393_bits_0 = pipe_b_393_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_394; // @[Valid.scala:141:24] wire pipe_out_394_valid = pipe_v_394; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_394_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_394_bits_0 = pipe_b_394_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_395; // @[Valid.scala:141:24] wire pipe_out_395_valid = pipe_v_395; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_395_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_395_bits_0 = pipe_b_395_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_396; // @[Valid.scala:141:24] wire pipe_out_396_valid = pipe_v_396; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_396_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_396_bits_0 = pipe_b_396_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_397; // @[Valid.scala:141:24] wire pipe_out_397_valid = pipe_v_397; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_397_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_397_bits_0 = pipe_b_397_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_398; // @[Valid.scala:141:24] wire pipe_out_398_valid = pipe_v_398; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_398_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_398_bits_0 = pipe_b_398_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_399; // @[Valid.scala:141:24] wire pipe_out_399_valid = pipe_v_399; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_399_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_399_bits_0 = pipe_b_399_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_400; // @[Valid.scala:141:24] wire pipe_out_400_valid = pipe_v_400; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_400_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_400_bits_0 = pipe_b_400_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_401; // @[Valid.scala:141:24] wire pipe_out_401_valid = pipe_v_401; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_401_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_401_bits_0 = pipe_b_401_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_402; // @[Valid.scala:141:24] wire pipe_out_402_valid = pipe_v_402; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_402_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_402_bits_0 = pipe_b_402_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_403; // @[Valid.scala:141:24] wire pipe_out_403_valid = pipe_v_403; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_403_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_403_bits_0 = pipe_b_403_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_404; // @[Valid.scala:141:24] wire pipe_out_404_valid = pipe_v_404; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_404_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_404_bits_0 = pipe_b_404_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_405; // @[Valid.scala:141:24] wire pipe_out_405_valid = pipe_v_405; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_405_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_405_bits_0 = pipe_b_405_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_406; // @[Valid.scala:141:24] wire pipe_out_406_valid = pipe_v_406; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_406_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_406_bits_0 = pipe_b_406_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_407; // @[Valid.scala:141:24] wire pipe_out_407_valid = pipe_v_407; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_407_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_407_bits_0 = pipe_b_407_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_408; // @[Valid.scala:141:24] wire pipe_out_408_valid = pipe_v_408; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_408_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_408_bits_0 = pipe_b_408_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_409; // @[Valid.scala:141:24] wire pipe_out_409_valid = pipe_v_409; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_409_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_409_bits_0 = pipe_b_409_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_410; // @[Valid.scala:141:24] wire pipe_out_410_valid = pipe_v_410; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_410_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_410_bits_0 = pipe_b_410_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_411; // @[Valid.scala:141:24] wire pipe_out_411_valid = pipe_v_411; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_411_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_411_bits_0 = pipe_b_411_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_412; // @[Valid.scala:141:24] wire pipe_out_412_valid = pipe_v_412; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_412_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_412_bits_0 = pipe_b_412_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_413; // @[Valid.scala:141:24] wire pipe_out_413_valid = pipe_v_413; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_413_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_413_bits_0 = pipe_b_413_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_414; // @[Valid.scala:141:24] wire pipe_out_414_valid = pipe_v_414; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_414_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_414_bits_0 = pipe_b_414_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_415; // @[Valid.scala:141:24] wire pipe_out_415_valid = pipe_v_415; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_415_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_415_bits_0 = pipe_b_415_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_416; // @[Valid.scala:141:24] wire pipe_out_416_valid = pipe_v_416; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_416_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_416_bits_0 = pipe_b_416_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_417; // @[Valid.scala:141:24] wire pipe_out_417_valid = pipe_v_417; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_417_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_417_bits_0 = pipe_b_417_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_418; // @[Valid.scala:141:24] wire pipe_out_418_valid = pipe_v_418; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_418_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_418_bits_0 = pipe_b_418_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_419; // @[Valid.scala:141:24] wire pipe_out_419_valid = pipe_v_419; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_419_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_419_bits_0 = pipe_b_419_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_420; // @[Valid.scala:141:24] wire pipe_out_420_valid = pipe_v_420; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_420_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_420_bits_0 = pipe_b_420_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_421; // @[Valid.scala:141:24] wire pipe_out_421_valid = pipe_v_421; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_421_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_421_bits_0 = pipe_b_421_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_422; // @[Valid.scala:141:24] wire pipe_out_422_valid = pipe_v_422; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_422_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_422_bits_0 = pipe_b_422_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_423; // @[Valid.scala:141:24] wire pipe_out_423_valid = pipe_v_423; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_423_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_423_bits_0 = pipe_b_423_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_424; // @[Valid.scala:141:24] wire pipe_out_424_valid = pipe_v_424; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_424_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_424_bits_0 = pipe_b_424_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_425; // @[Valid.scala:141:24] wire pipe_out_425_valid = pipe_v_425; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_425_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_425_bits_0 = pipe_b_425_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_426; // @[Valid.scala:141:24] wire pipe_out_426_valid = pipe_v_426; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_426_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_426_bits_0 = pipe_b_426_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_427; // @[Valid.scala:141:24] wire pipe_out_427_valid = pipe_v_427; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_427_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_427_bits_0 = pipe_b_427_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_428; // @[Valid.scala:141:24] wire pipe_out_428_valid = pipe_v_428; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_428_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_428_bits_0 = pipe_b_428_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_429; // @[Valid.scala:141:24] wire pipe_out_429_valid = pipe_v_429; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_429_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_429_bits_0 = pipe_b_429_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_430; // @[Valid.scala:141:24] wire pipe_out_430_valid = pipe_v_430; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_430_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_430_bits_0 = pipe_b_430_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_431; // @[Valid.scala:141:24] wire pipe_out_431_valid = pipe_v_431; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_431_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_431_bits_0 = pipe_b_431_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_432; // @[Valid.scala:141:24] wire pipe_out_432_valid = pipe_v_432; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_432_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_432_bits_0 = pipe_b_432_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_433; // @[Valid.scala:141:24] wire pipe_out_433_valid = pipe_v_433; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_433_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_433_bits_0 = pipe_b_433_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_434; // @[Valid.scala:141:24] wire pipe_out_434_valid = pipe_v_434; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_434_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_434_bits_0 = pipe_b_434_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_435; // @[Valid.scala:141:24] wire pipe_out_435_valid = pipe_v_435; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_435_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_435_bits_0 = pipe_b_435_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_436; // @[Valid.scala:141:24] wire pipe_out_436_valid = pipe_v_436; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_436_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_436_bits_0 = pipe_b_436_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_437; // @[Valid.scala:141:24] wire pipe_out_437_valid = pipe_v_437; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_437_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_437_bits_0 = pipe_b_437_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_438; // @[Valid.scala:141:24] wire pipe_out_438_valid = pipe_v_438; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_438_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_438_bits_0 = pipe_b_438_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_439; // @[Valid.scala:141:24] wire pipe_out_439_valid = pipe_v_439; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_439_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_439_bits_0 = pipe_b_439_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_440; // @[Valid.scala:141:24] wire pipe_out_440_valid = pipe_v_440; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_440_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_440_bits_0 = pipe_b_440_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_441; // @[Valid.scala:141:24] wire pipe_out_441_valid = pipe_v_441; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_441_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_441_bits_0 = pipe_b_441_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_442; // @[Valid.scala:141:24] wire pipe_out_442_valid = pipe_v_442; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_442_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_442_bits_0 = pipe_b_442_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_443; // @[Valid.scala:141:24] wire pipe_out_443_valid = pipe_v_443; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_443_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_443_bits_0 = pipe_b_443_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_444; // @[Valid.scala:141:24] wire pipe_out_444_valid = pipe_v_444; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_444_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_444_bits_0 = pipe_b_444_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_445; // @[Valid.scala:141:24] wire pipe_out_445_valid = pipe_v_445; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_445_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_445_bits_0 = pipe_b_445_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_446; // @[Valid.scala:141:24] wire pipe_out_446_valid = pipe_v_446; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_446_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_446_bits_0 = pipe_b_446_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_447; // @[Valid.scala:141:24] wire pipe_out_447_valid = pipe_v_447; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_447_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_447_bits_0 = pipe_b_447_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_448; // @[Valid.scala:141:24] wire pipe_out_448_valid = pipe_v_448; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_448_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_448_bits_0 = pipe_b_448_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_449; // @[Valid.scala:141:24] wire pipe_out_449_valid = pipe_v_449; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_449_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_449_bits_0 = pipe_b_449_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_450; // @[Valid.scala:141:24] wire pipe_out_450_valid = pipe_v_450; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_450_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_450_bits_0 = pipe_b_450_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_451; // @[Valid.scala:141:24] wire pipe_out_451_valid = pipe_v_451; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_451_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_451_bits_0 = pipe_b_451_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_452; // @[Valid.scala:141:24] wire pipe_out_452_valid = pipe_v_452; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_452_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_452_bits_0 = pipe_b_452_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_453; // @[Valid.scala:141:24] wire pipe_out_453_valid = pipe_v_453; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_453_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_453_bits_0 = pipe_b_453_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_454; // @[Valid.scala:141:24] wire pipe_out_454_valid = pipe_v_454; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_454_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_454_bits_0 = pipe_b_454_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_455; // @[Valid.scala:141:24] wire pipe_out_455_valid = pipe_v_455; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_455_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_455_bits_0 = pipe_b_455_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_456; // @[Valid.scala:141:24] wire pipe_out_456_valid = pipe_v_456; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_456_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_456_bits_0 = pipe_b_456_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_457; // @[Valid.scala:141:24] wire pipe_out_457_valid = pipe_v_457; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_457_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_457_bits_0 = pipe_b_457_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_458; // @[Valid.scala:141:24] wire pipe_out_458_valid = pipe_v_458; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_458_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_458_bits_0 = pipe_b_458_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_459; // @[Valid.scala:141:24] wire pipe_out_459_valid = pipe_v_459; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_459_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_459_bits_0 = pipe_b_459_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_460; // @[Valid.scala:141:24] wire pipe_out_460_valid = pipe_v_460; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_460_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_460_bits_0 = pipe_b_460_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_461; // @[Valid.scala:141:24] wire pipe_out_461_valid = pipe_v_461; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_461_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_461_bits_0 = pipe_b_461_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_462; // @[Valid.scala:141:24] wire pipe_out_462_valid = pipe_v_462; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_462_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_462_bits_0 = pipe_b_462_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_463; // @[Valid.scala:141:24] wire pipe_out_463_valid = pipe_v_463; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_463_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_463_bits_0 = pipe_b_463_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_464; // @[Valid.scala:141:24] wire pipe_out_464_valid = pipe_v_464; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_464_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_464_bits_0 = pipe_b_464_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_465; // @[Valid.scala:141:24] wire pipe_out_465_valid = pipe_v_465; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_465_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_465_bits_0 = pipe_b_465_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_466; // @[Valid.scala:141:24] wire pipe_out_466_valid = pipe_v_466; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_466_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_466_bits_0 = pipe_b_466_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_467; // @[Valid.scala:141:24] wire pipe_out_467_valid = pipe_v_467; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_467_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_467_bits_0 = pipe_b_467_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_468; // @[Valid.scala:141:24] wire pipe_out_468_valid = pipe_v_468; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_468_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_468_bits_0 = pipe_b_468_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_469; // @[Valid.scala:141:24] wire pipe_out_469_valid = pipe_v_469; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_469_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_469_bits_0 = pipe_b_469_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_470; // @[Valid.scala:141:24] wire pipe_out_470_valid = pipe_v_470; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_470_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_470_bits_0 = pipe_b_470_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_471; // @[Valid.scala:141:24] wire pipe_out_471_valid = pipe_v_471; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_471_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_471_bits_0 = pipe_b_471_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_472; // @[Valid.scala:141:24] wire pipe_out_472_valid = pipe_v_472; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_472_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_472_bits_0 = pipe_b_472_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_473; // @[Valid.scala:141:24] wire pipe_out_473_valid = pipe_v_473; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_473_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_473_bits_0 = pipe_b_473_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_474; // @[Valid.scala:141:24] wire pipe_out_474_valid = pipe_v_474; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_474_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_474_bits_0 = pipe_b_474_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_475; // @[Valid.scala:141:24] wire pipe_out_475_valid = pipe_v_475; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_475_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_475_bits_0 = pipe_b_475_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_476; // @[Valid.scala:141:24] wire pipe_out_476_valid = pipe_v_476; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_476_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_476_bits_0 = pipe_b_476_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_477; // @[Valid.scala:141:24] wire pipe_out_477_valid = pipe_v_477; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_477_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_477_bits_0 = pipe_b_477_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_478; // @[Valid.scala:141:24] wire pipe_out_478_valid = pipe_v_478; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_478_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_478_bits_0 = pipe_b_478_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_479; // @[Valid.scala:141:24] wire pipe_out_479_valid = pipe_v_479; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_479_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_479_bits_0 = pipe_b_479_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_480; // @[Valid.scala:141:24] wire pipe_out_480_valid = pipe_v_480; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_480_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_480_bits_0 = pipe_b_480_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_481; // @[Valid.scala:141:24] wire pipe_out_481_valid = pipe_v_481; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_481_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_481_bits_0 = pipe_b_481_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_482; // @[Valid.scala:141:24] wire pipe_out_482_valid = pipe_v_482; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_482_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_482_bits_0 = pipe_b_482_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_483; // @[Valid.scala:141:24] wire pipe_out_483_valid = pipe_v_483; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_483_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_483_bits_0 = pipe_b_483_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_484; // @[Valid.scala:141:24] wire pipe_out_484_valid = pipe_v_484; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_484_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_484_bits_0 = pipe_b_484_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_485; // @[Valid.scala:141:24] wire pipe_out_485_valid = pipe_v_485; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_485_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_485_bits_0 = pipe_b_485_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_486; // @[Valid.scala:141:24] wire pipe_out_486_valid = pipe_v_486; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_486_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_486_bits_0 = pipe_b_486_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_487; // @[Valid.scala:141:24] wire pipe_out_487_valid = pipe_v_487; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_487_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_487_bits_0 = pipe_b_487_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_488; // @[Valid.scala:141:24] wire pipe_out_488_valid = pipe_v_488; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_488_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_488_bits_0 = pipe_b_488_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_489; // @[Valid.scala:141:24] wire pipe_out_489_valid = pipe_v_489; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_489_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_489_bits_0 = pipe_b_489_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_490; // @[Valid.scala:141:24] wire pipe_out_490_valid = pipe_v_490; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_490_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_490_bits_0 = pipe_b_490_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_491; // @[Valid.scala:141:24] wire pipe_out_491_valid = pipe_v_491; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_491_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_491_bits_0 = pipe_b_491_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_492; // @[Valid.scala:141:24] wire pipe_out_492_valid = pipe_v_492; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_492_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_492_bits_0 = pipe_b_492_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_493; // @[Valid.scala:141:24] wire pipe_out_493_valid = pipe_v_493; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_493_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_493_bits_0 = pipe_b_493_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_494; // @[Valid.scala:141:24] wire pipe_out_494_valid = pipe_v_494; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_494_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_494_bits_0 = pipe_b_494_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_495; // @[Valid.scala:141:24] wire pipe_out_495_valid = pipe_v_495; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_495_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_495_bits_0 = pipe_b_495_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_496; // @[Valid.scala:141:24] wire pipe_out_496_valid = pipe_v_496; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_496_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_496_bits_0 = pipe_b_496_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_497; // @[Valid.scala:141:24] wire pipe_out_497_valid = pipe_v_497; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_497_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_497_bits_0 = pipe_b_497_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_498; // @[Valid.scala:141:24] wire pipe_out_498_valid = pipe_v_498; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_498_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_498_bits_0 = pipe_b_498_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_499; // @[Valid.scala:141:24] wire pipe_out_499_valid = pipe_v_499; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_499_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_499_bits_0 = pipe_b_499_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_500; // @[Valid.scala:141:24] wire pipe_out_500_valid = pipe_v_500; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_500_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_500_bits_0 = pipe_b_500_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_501; // @[Valid.scala:141:24] wire pipe_out_501_valid = pipe_v_501; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_501_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_501_bits_0 = pipe_b_501_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_502; // @[Valid.scala:141:24] wire pipe_out_502_valid = pipe_v_502; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_502_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_502_bits_0 = pipe_b_502_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_503; // @[Valid.scala:141:24] wire pipe_out_503_valid = pipe_v_503; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_503_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_503_bits_0 = pipe_b_503_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_504; // @[Valid.scala:141:24] wire pipe_out_504_valid = pipe_v_504; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_504_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_504_bits_0 = pipe_b_504_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_505; // @[Valid.scala:141:24] wire pipe_out_505_valid = pipe_v_505; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_505_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_505_bits_0 = pipe_b_505_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_506; // @[Valid.scala:141:24] wire pipe_out_506_valid = pipe_v_506; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_506_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_506_bits_0 = pipe_b_506_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_507; // @[Valid.scala:141:24] wire pipe_out_507_valid = pipe_v_507; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_507_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_507_bits_0 = pipe_b_507_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_508; // @[Valid.scala:141:24] wire pipe_out_508_valid = pipe_v_508; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_508_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_508_bits_0 = pipe_b_508_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_509; // @[Valid.scala:141:24] wire pipe_out_509_valid = pipe_v_509; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_509_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_509_bits_0 = pipe_b_509_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_510; // @[Valid.scala:141:24] wire pipe_out_510_valid = pipe_v_510; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_510_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_510_bits_0 = pipe_b_510_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_511; // @[Valid.scala:141:24] wire pipe_out_511_valid = pipe_v_511; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_511_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_511_bits_0 = pipe_b_511_0; // @[Valid.scala:135:21, :142:26]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. / object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /* Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. / case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /* the base address of DM / def atzero = (baseAddress == 0) /* The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm / def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /TODO , val configStringAddr: Int/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /* Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above / case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ************************************** // Module Interfaces // // ************************************* / Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} / class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* resume request / val resumereq = Bool() /* hart select / val hartsel = UInt(10.W) /* reset acknowledge / val ackhavereset = Bool() /* hart array enable / val hasel = Bool() /* hart array mask / val hamask = Vec(nComponents, Bool()) /* halt-on-reset mask / val hrmask = Vec(nComponents, Bool()) } /* structure for top-level Debug Module signals which aren't the bus interfaces. / class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /* debug availability status for all harts / val debugUnavail = Input(Vec(nComponents, Bool())) /* reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM / val ndreset = Output(Bool()) /* reset signal for the DM itself / val dmactive = Output(Bool()) /* dmactive acknowlege / val dmactiveAck = Input(Bool()) } // ************************************** // Debug Module // // ************************************* / Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. / // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /* structure for top-level Debug Module signals which aren't the bus interfaces. / val ctrl = (new DebugCtrlBundle(nComponents)) /* control signals for Inner, generated in Outer / val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /* debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* authentication support / val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /* whether the hart is selected / def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive \|\| ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((iihaWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (iihaWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive \|\| ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((iihaWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(iihaWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(iihaWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) \| io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive \|\| ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) \|\| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn \| resumereqWrEn \| ackhaveresetWrEn \| setresethaltreqWrEn \| clrresethaltreqWrEn \| haselWrEn \| (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid \| innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) \| innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) \| innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode := IntSyncCrossingSource(alreadyRegistered = true) := dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /* conrol signals for Inner, generated in Outer / val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /* debug interruption generated in Inner / val hgDebugInt = Input(Vec(nComponents, Bool())) /* hart reset request to core / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Authentication signal from core / val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive \| ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /* dmiNode address set / val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) \| (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /* dm reset signal passed in from Outer / val dmactive = Input(Bool()) /* conrol signals for Inner * * it's generated by Outer and comes in / val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /* debug unavail signal passed in from Outer/ val debugUnavail = Input(Vec(nComponents, Bool())) /* debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset / val hgDebugInt = Output(Vec(nComponents, Bool())) /* interface for trigger / val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug Authentication signals from core / val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) \|\| (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /* all harts halted status / val haltedBitRegs = Reg(UInt(nComponents.W)) /* all harts resume request status / val resumeReqRegs = Reg(UInt(nComponents.W)) /* all harts have reset status / val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /* all harts resume ack status / val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive \|\| ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) \|\| (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive \|\| ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive \|\| ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync \| // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ \| _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ \| _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ \| _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools \| ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools \| ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive \|\| ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) \| hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs \| hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive \|\| ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive \|\| ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive \|\| ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ \| _) hgTrigsAllAcked(hg) := (trigOutAck \| hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools \| hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive \|\| ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) \| hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt \| hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive \|\| ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r \| w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r \| w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ \|\| _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ \|\| _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ \|\| _) \|\| autoexecProg.reduce(_ \|\| _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive \|\| ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive \|\| ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs \| hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs \| hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i8, (i+1)8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) \|\| (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) \|\| (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) \|\| (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) \|\| (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) \|\| (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) \|\| (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result \|\| (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer \|\| accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand \|\| regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive \|\| ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive \|\| !hartExceptionWrEn \|\| ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /* reset signal for DM / val dmactive = Input(Bool()) /* conrol signals for Inner * * generated in Outer / val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /* debug available status / val debugUnavail = Input(Vec(getNComponents(), Bool())) /* debug interruption/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(getNComponents(), Bool())) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /* Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. / class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /* Debug control signals generated in Outer / val ctrl = new DebugCtrlBundle(nComponents) /* Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI / val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /* vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner / val hartIsInReset = Input(Vec(nComponents, Bool())) /* hart reset request generated by hartreset-logic in Outer / val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /* Debug Authentication signals from core / val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLDebugModuleOuterAsync( // @[Debug.scala:709:9] output [2:0] auto_asource_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_asource_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_asource_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_asource_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_asource_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_asource_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_asource_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_asource_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_asource_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_asource_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_asource_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_asource_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_asource_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_asource_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_asource_out_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output auto_int_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input io_dmi_clock, // @[Debug.scala:713:16] input io_dmi_reset, // @[Debug.scala:713:16] output io_dmi_req_ready, // @[Debug.scala:713:16] input io_dmi_req_valid, // @[Debug.scala:713:16] input [6:0] io_dmi_req_bits_addr, // @[Debug.scala:713:16] input [31:0] io_dmi_req_bits_data, // @[Debug.scala:713:16] input [1:0] io_dmi_req_bits_op, // @[Debug.scala:713:16] input io_dmi_resp_ready, // @[Debug.scala:713:16] output io_dmi_resp_valid, // @[Debug.scala:713:16] output [31:0] io_dmi_resp_bits_data, // @[Debug.scala:713:16] output [1:0] io_dmi_resp_bits_resp, // @[Debug.scala:713:16] output io_ctrl_ndreset, // @[Debug.scala:713:16] output io_ctrl_dmactive, // @[Debug.scala:713:16] input io_ctrl_dmactiveAck, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_resumereq, // @[Debug.scala:713:16] output [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hasel, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_0, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_1, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_2, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_3, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_1, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_2, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_3, // @[Debug.scala:713:16] input io_innerCtrl_ridx, // @[Debug.scala:713:16] output io_innerCtrl_widx, // @[Debug.scala:713:16] input io_innerCtrl_safe_ridx_valid, // @[Debug.scala:713:16] output io_innerCtrl_safe_widx_valid, // @[Debug.scala:713:16] output io_innerCtrl_safe_source_reset_n, // @[Debug.scala:713:16] input io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:713:16] input io_hgDebugInt_0, // @[Debug.scala:713:16] input io_hgDebugInt_1, // @[Debug.scala:713:16] input io_hgDebugInt_2, // @[Debug.scala:713:16] input io_hgDebugInt_3, // @[Debug.scala:713:16] input rf_reset // @[Debug.scala:732:22] ); wire _io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala:220:24] wire _asource_auto_in_a_ready; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_valid; // @[AsyncCrossing.scala:94:29] wire [2:0] _asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala:94:29] wire [1:0] _asource_auto_in_d_bits_param; // @[AsyncCrossing.scala:94:29] wire [1:0] _asource_auto_in_d_bits_size; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_source; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala:94:29] wire [31:0] _asource_auto_in_d_bits_data; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala:94:29] wire _dmiBypass_auto_node_out_out_a_valid; // @[Debug.scala:704:29] wire [2:0] _dmiBypass_auto_node_out_out_a_bits_opcode; // @[Debug.scala:704:29] wire [8:0] _dmiBypass_auto_node_out_out_a_bits_address; // @[Debug.scala:704:29] wire [31:0] _dmiBypass_auto_node_out_out_a_bits_data; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_out_out_d_ready; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_a_ready; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_valid; // @[Debug.scala:704:29] wire [2:0] _dmiBypass_auto_node_in_in_d_bits_opcode; // @[Debug.scala:704:29] wire [1:0] _dmiBypass_auto_node_in_in_d_bits_param; // @[Debug.scala:704:29] wire [1:0] _dmiBypass_auto_node_in_in_d_bits_size; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_source; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_sink; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_denied; // @[Debug.scala:704:29] wire [31:0] _dmiBypass_auto_node_in_in_d_bits_data; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_corrupt; // @[Debug.scala:704:29] wire _dmOuter_auto_dmi_in_a_ready; // @[Debug.scala:700:27] wire _dmOuter_auto_dmi_in_d_valid; // @[Debug.scala:700:27] wire [2:0] _dmOuter_auto_dmi_in_d_bits_opcode; // @[Debug.scala:700:27] wire [31:0] _dmOuter_auto_dmi_in_d_bits_data; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_3_0; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_2_0; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_1_0; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_0_0; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_valid; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_resumereq; // @[Debug.scala:700:27] wire [9:0] _dmOuter_io_innerCtrl_bits_hartsel; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_ackhavereset; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hasel; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_0; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_1; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_2; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_3; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_0; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_1; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_2; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_3; // @[Debug.scala:700:27] wire _dmi2tl_auto_out_a_valid; // @[Debug.scala:678:28] wire [2:0] _dmi2tl_auto_out_a_bits_opcode; // @[Debug.scala:678:28] wire [8:0] _dmi2tl_auto_out_a_bits_address; // @[Debug.scala:678:28] wire [31:0] _dmi2tl_auto_out_a_bits_data; // @[Debug.scala:678:28] wire _dmi2tl_auto_out_d_ready; // @[Debug.scala:678:28] wire _dmiXbar_auto_anon_in_a_ready; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_valid; // @[Debug.scala:675:28] wire [2:0] _dmiXbar_auto_anon_in_d_bits_opcode; // @[Debug.scala:675:28] wire [1:0] _dmiXbar_auto_anon_in_d_bits_param; // @[Debug.scala:675:28] wire [1:0] _dmiXbar_auto_anon_in_d_bits_size; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_bits_sink; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_bits_denied; // @[Debug.scala:675:28] wire [31:0] _dmiXbar_auto_anon_in_d_bits_data; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_bits_corrupt; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_1_a_valid; // @[Debug.scala:675:28] wire [2:0] _dmiXbar_auto_anon_out_1_a_bits_opcode; // @[Debug.scala:675:28] wire [6:0] _dmiXbar_auto_anon_out_1_a_bits_address; // @[Debug.scala:675:28] wire [31:0] _dmiXbar_auto_anon_out_1_a_bits_data; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_1_d_ready; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_0_a_valid; // @[Debug.scala:675:28] wire [2:0] _dmiXbar_auto_anon_out_0_a_bits_opcode; // @[Debug.scala:675:28] wire [8:0] _dmiXbar_auto_anon_out_0_a_bits_address; // @[Debug.scala:675:28] wire [31:0] _dmiXbar_auto_anon_out_0_a_bits_data; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_0_d_ready; // @[Debug.scala:675:28] wire auto_asource_out_a_ridx_0 = auto_asource_out_a_ridx; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_ridx_valid_0 = auto_asource_out_a_safe_ridx_valid; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_sink_reset_n_0 = auto_asource_out_a_safe_sink_reset_n; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_d_mem_0_opcode_0 = auto_asource_out_d_mem_0_opcode; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_d_mem_0_size_0 = auto_asource_out_d_mem_0_size; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_source_0 = auto_asource_out_d_mem_0_source; // @[Debug.scala:709:9] wire [31:0] auto_asource_out_d_mem_0_data_0 = auto_asource_out_d_mem_0_data; // @[Debug.scala:709:9] wire auto_asource_out_d_widx_0 = auto_asource_out_d_widx; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_widx_valid_0 = auto_asource_out_d_safe_widx_valid; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_source_reset_n_0 = auto_asource_out_d_safe_source_reset_n; // @[Debug.scala:709:9] wire io_dmi_clock_0 = io_dmi_clock; // @[Debug.scala:709:9] wire io_dmi_reset_0 = io_dmi_reset; // @[Debug.scala:709:9] wire io_dmi_req_valid_0 = io_dmi_req_valid; // @[Debug.scala:709:9] wire [6:0] io_dmi_req_bits_addr_0 = io_dmi_req_bits_addr; // @[Debug.scala:709:9] wire [31:0] io_dmi_req_bits_data_0 = io_dmi_req_bits_data; // @[Debug.scala:709:9] wire [1:0] io_dmi_req_bits_op_0 = io_dmi_req_bits_op; // @[Debug.scala:709:9] wire io_dmi_resp_ready_0 = io_dmi_resp_ready; // @[Debug.scala:709:9] wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck; // @[Debug.scala:709:9] wire io_innerCtrl_ridx_0 = io_innerCtrl_ridx; // @[Debug.scala:709:9] wire io_innerCtrl_safe_ridx_valid_0 = io_innerCtrl_safe_ridx_valid; // @[Debug.scala:709:9] wire io_innerCtrl_safe_sink_reset_n_0 = io_innerCtrl_safe_sink_reset_n; // @[Debug.scala:709:9] wire io_hgDebugInt_0_0 = io_hgDebugInt_0; // @[Debug.scala:709:9] wire io_hgDebugInt_1_0 = io_hgDebugInt_1; // @[Debug.scala:709:9] wire io_hgDebugInt_2_0 = io_hgDebugInt_2; // @[Debug.scala:709:9] wire io_hgDebugInt_3_0 = io_hgDebugInt_3; // @[Debug.scala:709:9] wire auto_asource_out_a_mem_0_source = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_a_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_mem_0_source = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_ridx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_widx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_widx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_mem_0_source = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_ridx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_widx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_widx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_sink = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_denied = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_mem_0_sink = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_ridx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_widx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_widx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_0 = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_1 = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_2 = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_3 = 1'h0; // @[Debug.scala:709:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire [31:0] auto_asource_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:94:29] wire [31:0] auto_asource_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:94:29] wire [3:0] auto_asource_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:94:29] wire [8:0] auto_asource_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:94:29] wire [8:0] auto_asource_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:94:29] wire [1:0] auto_asource_out_b_mem_0_param = 2'h0; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_b_mem_0_size = 2'h0; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_c_mem_0_size = 2'h0; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_d_mem_0_param = 2'h0; // @[Debug.scala:709:9] wire [3:0] auto_asource_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:94:29] wire [1:0] auto_asource_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:94:29] wire [2:0] auto_asource_out_a_mem_0_param = 3'h0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_b_mem_0_opcode = 3'h0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_c_mem_0_opcode = 3'h0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_c_mem_0_param = 3'h0; // @[Debug.scala:709:9] wire x1_intnodeOut_2_sync_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_1_sync_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_sync_0; // @[MixedNode.scala:542:17] wire intnodeOut_sync_0; // @[MixedNode.scala:542:17] wire childClock = io_dmi_clock_0; // @[Debug.scala:709:9] wire childReset = io_dmi_reset_0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_a_mem_0_opcode_0; // @[Debug.scala:709:9] wire [8:0] auto_asource_out_a_mem_0_address_0; // @[Debug.scala:709:9] wire [31:0] auto_asource_out_a_mem_0_data_0; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_widx_valid_0; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_source_reset_n_0; // @[Debug.scala:709:9] wire auto_asource_out_a_widx_0; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_ridx_valid_0; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_sink_reset_n_0; // @[Debug.scala:709:9] wire auto_asource_out_d_ridx_0; // @[Debug.scala:709:9] wire auto_int_out_3_sync_0_0; // @[Debug.scala:709:9] wire auto_int_out_2_sync_0_0; // @[Debug.scala:709:9] wire auto_int_out_1_sync_0_0; // @[Debug.scala:709:9] wire auto_int_out_0_sync_0_0; // @[Debug.scala:709:9] wire io_dmi_req_ready_0; // @[Debug.scala:709:9] wire [31:0] io_dmi_resp_bits_data_0; // @[Debug.scala:709:9] wire [1:0] io_dmi_resp_bits_resp_0; // @[Debug.scala:709:9] wire io_dmi_resp_valid_0; // @[Debug.scala:709:9] wire io_ctrl_ndreset_0; // @[Debug.scala:709:9] wire io_ctrl_dmactive_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_0_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_1_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_2_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_3_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_0_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_1_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_2_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_3_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_resumereq_0; // @[Debug.scala:709:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_ackhavereset_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hasel_0; // @[Debug.scala:709:9] wire io_innerCtrl_safe_widx_valid_0; // @[Debug.scala:709:9] wire io_innerCtrl_safe_source_reset_n_0; // @[Debug.scala:709:9] wire io_innerCtrl_widx_0; // @[Debug.scala:709:9] wire intnodeIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_0_sync_0_0 = intnodeOut_sync_0; // @[Debug.scala:709:9] wire x1_intnodeIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_1_sync_0_0 = x1_intnodeOut_sync_0; // @[Debug.scala:709:9] wire x1_intnodeIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_2_sync_0_0 = x1_intnodeOut_1_sync_0; // @[Debug.scala:709:9] wire x1_intnodeIn_2_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_3_sync_0_0 = x1_intnodeOut_2_sync_0; // @[Debug.scala:709:9] assign intnodeOut_sync_0 = intnodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign x1_intnodeOut_sync_0 = x1_intnodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign x1_intnodeOut_1_sync_0 = x1_intnodeIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign x1_intnodeOut_2_sync_0 = x1_intnodeIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire dmactiveAck; // @[ShiftReg.scala:48:24] wire _dmiBypass_io_bypass_T = ~io_ctrl_dmactive_0; // @[Debug.scala:709:9, :742:37] wire _dmiBypass_io_bypass_T_1 = ~dmactiveAck; // @[ShiftReg.scala:48:24] wire _dmiBypass_io_bypass_T_2 = _dmiBypass_io_bypass_T \| _dmiBypass_io_bypass_T_1; // @[Debug.scala:742:{37,55,57}] TLXbar_dmixbar_i1_o2_a9d32s1k1z2u dmiXbar ( // @[Debug.scala:675:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_dmiXbar_auto_anon_in_a_ready), .auto_anon_in_a_valid (_dmi2tl_auto_out_a_valid), // @[Debug.scala:678:28] .auto_anon_in_a_bits_opcode (_dmi2tl_auto_out_a_bits_opcode), // @[Debug.scala:678:28] .auto_anon_in_a_bits_address (_dmi2tl_auto_out_a_bits_address), // @[Debug.scala:678:28] .auto_anon_in_a_bits_data (_dmi2tl_auto_out_a_bits_data), // @[Debug.scala:678:28] .auto_anon_in_d_ready (_dmi2tl_auto_out_d_ready), // @[Debug.scala:678:28] .auto_anon_in_d_valid (_dmiXbar_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_dmiXbar_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (_dmiXbar_auto_anon_in_d_bits_param), .auto_anon_in_d_bits_size (_dmiXbar_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_sink (_dmiXbar_auto_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (_dmiXbar_auto_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (_dmiXbar_auto_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (_dmiXbar_auto_anon_in_d_bits_corrupt), .auto_anon_out_1_a_ready (_dmOuter_auto_dmi_in_a_ready), // @[Debug.scala:700:27] .auto_anon_out_1_a_valid (_dmiXbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_dmiXbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_address (_dmiXbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_data (_dmiXbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_d_ready (_dmiXbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_dmOuter_auto_dmi_in_d_valid), // @[Debug.scala:700:27] .auto_anon_out_1_d_bits_opcode (_dmOuter_auto_dmi_in_d_bits_opcode), // @[Debug.scala:700:27] .auto_anon_out_1_d_bits_data (_dmOuter_auto_dmi_in_d_bits_data), // @[Debug.scala:700:27] .auto_anon_out_0_a_ready (_dmiBypass_auto_node_in_in_a_ready), // @[Debug.scala:704:29] .auto_anon_out_0_a_valid (_dmiXbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_dmiXbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_address (_dmiXbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_data (_dmiXbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_d_ready (_dmiXbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_dmiBypass_auto_node_in_in_d_valid), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_opcode (_dmiBypass_auto_node_in_in_d_bits_opcode), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_param (_dmiBypass_auto_node_in_in_d_bits_param), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_size (_dmiBypass_auto_node_in_in_d_bits_size), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_source (_dmiBypass_auto_node_in_in_d_bits_source), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_sink (_dmiBypass_auto_node_in_in_d_bits_sink), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_denied (_dmiBypass_auto_node_in_in_d_bits_denied), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_data (_dmiBypass_auto_node_in_in_d_bits_data), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_corrupt (_dmiBypass_auto_node_in_in_d_bits_corrupt) // @[Debug.scala:704:29] ); // @[Debug.scala:675:28] DMIToTL dmi2tl ( // @[Debug.scala:678:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_out_a_ready (_dmiXbar_auto_anon_in_a_ready), // @[Debug.scala:675:28] .auto_out_a_valid (_dmi2tl_auto_out_a_valid), .auto_out_a_bits_opcode (_dmi2tl_auto_out_a_bits_opcode), .auto_out_a_bits_address (_dmi2tl_auto_out_a_bits_address), .auto_out_a_bits_data (_dmi2tl_auto_out_a_bits_data), .auto_out_d_ready (_dmi2tl_auto_out_d_ready), .auto_out_d_valid (_dmiXbar_auto_anon_in_d_valid), // @[Debug.scala:675:28] .auto_out_d_bits_opcode (_dmiXbar_auto_anon_in_d_bits_opcode), // @[Debug.scala:675:28] .auto_out_d_bits_param (_dmiXbar_auto_anon_in_d_bits_param), // @[Debug.scala:675:28] .auto_out_d_bits_size (_dmiXbar_auto_anon_in_d_bits_size), // @[Debug.scala:675:28] .auto_out_d_bits_sink (_dmiXbar_auto_anon_in_d_bits_sink), // @[Debug.scala:675:28] .auto_out_d_bits_denied (_dmiXbar_auto_anon_in_d_bits_denied), // @[Debug.scala:675:28] .auto_out_d_bits_data (_dmiXbar_auto_anon_in_d_bits_data), // @[Debug.scala:675:28] .auto_out_d_bits_corrupt (_dmiXbar_auto_anon_in_d_bits_corrupt), // @[Debug.scala:675:28] .io_dmi_req_ready (io_dmi_req_ready_0), .io_dmi_req_valid (io_dmi_req_valid_0), // @[Debug.scala:709:9] .io_dmi_req_bits_addr (io_dmi_req_bits_addr_0), // @[Debug.scala:709:9] .io_dmi_req_bits_data (io_dmi_req_bits_data_0), // @[Debug.scala:709:9] .io_dmi_req_bits_op (io_dmi_req_bits_op_0), // @[Debug.scala:709:9] .io_dmi_resp_ready (io_dmi_resp_ready_0), // @[Debug.scala:709:9] .io_dmi_resp_valid (io_dmi_resp_valid_0), .io_dmi_resp_bits_data (io_dmi_resp_bits_data_0), .io_dmi_resp_bits_resp (io_dmi_resp_bits_resp_0) ); // @[Debug.scala:678:28] TLDebugModuleOuter dmOuter ( // @[Debug.scala:700:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_dmi_in_a_ready (_dmOuter_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXbar_auto_anon_out_1_a_valid), // @[Debug.scala:675:28] .auto_dmi_in_a_bits_opcode (_dmiXbar_auto_anon_out_1_a_bits_opcode), // @[Debug.scala:675:28] .auto_dmi_in_a_bits_address (_dmiXbar_auto_anon_out_1_a_bits_address), // @[Debug.scala:675:28] .auto_dmi_in_a_bits_data (_dmiXbar_auto_anon_out_1_a_bits_data), // @[Debug.scala:675:28] .auto_dmi_in_d_ready (_dmiXbar_auto_anon_out_1_d_ready), // @[Debug.scala:675:28] .auto_dmi_in_d_valid (_dmOuter_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmOuter_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_data (_dmOuter_auto_dmi_in_d_bits_data), .auto_int_out_3_0 (_dmOuter_auto_int_out_3_0), .auto_int_out_2_0 (_dmOuter_auto_int_out_2_0), .auto_int_out_1_0 (_dmOuter_auto_int_out_1_0), .auto_int_out_0_0 (_dmOuter_auto_int_out_0_0), .io_ctrl_ndreset (io_ctrl_ndreset_0), .io_ctrl_dmactive (io_ctrl_dmactive_0), .io_ctrl_dmactiveAck (dmactiveAck), // @[ShiftReg.scala:48:24] .io_innerCtrl_ready (_io_innerCtrl_source_io_enq_ready), // @[AsyncQueue.scala:220:24] .io_innerCtrl_valid (_dmOuter_io_innerCtrl_valid), .io_innerCtrl_bits_resumereq (_dmOuter_io_innerCtrl_bits_resumereq), .io_innerCtrl_bits_hartsel (_dmOuter_io_innerCtrl_bits_hartsel), .io_innerCtrl_bits_ackhavereset (_dmOuter_io_innerCtrl_bits_ackhavereset), .io_innerCtrl_bits_hasel (_dmOuter_io_innerCtrl_bits_hasel), .io_innerCtrl_bits_hamask_0 (_dmOuter_io_innerCtrl_bits_hamask_0), .io_innerCtrl_bits_hamask_1 (_dmOuter_io_innerCtrl_bits_hamask_1), .io_innerCtrl_bits_hamask_2 (_dmOuter_io_innerCtrl_bits_hamask_2), .io_innerCtrl_bits_hamask_3 (_dmOuter_io_innerCtrl_bits_hamask_3), .io_innerCtrl_bits_hrmask_0 (_dmOuter_io_innerCtrl_bits_hrmask_0), .io_innerCtrl_bits_hrmask_1 (_dmOuter_io_innerCtrl_bits_hrmask_1), .io_innerCtrl_bits_hrmask_2 (_dmOuter_io_innerCtrl_bits_hrmask_2), .io_innerCtrl_bits_hrmask_3 (_dmOuter_io_innerCtrl_bits_hrmask_3), .io_hgDebugInt_0 (io_hgDebugInt_0_0), // @[Debug.scala:709:9] .io_hgDebugInt_1 (io_hgDebugInt_1_0), // @[Debug.scala:709:9] .io_hgDebugInt_2 (io_hgDebugInt_2_0), // @[Debug.scala:709:9] .io_hgDebugInt_3 (io_hgDebugInt_3_0) // @[Debug.scala:709:9] ); // @[Debug.scala:700:27] IntSyncCrossingSource_n4x1_Registered intsource ( // @[Crossing.scala:29:31] .auto_in_3_0 (_dmOuter_auto_int_out_3_0), // @[Debug.scala:700:27] .auto_in_2_0 (_dmOuter_auto_int_out_2_0), // @[Debug.scala:700:27] .auto_in_1_0 (_dmOuter_auto_int_out_1_0), // @[Debug.scala:700:27] .auto_in_0_0 (_dmOuter_auto_int_out_0_0), // @[Debug.scala:700:27] .auto_out_3_sync_0 (x1_intnodeIn_2_sync_0), .auto_out_2_sync_0 (x1_intnodeIn_1_sync_0), .auto_out_1_sync_0 (x1_intnodeIn_sync_0), .auto_out_0_sync_0 (intnodeIn_sync_0) ); // @[Crossing.scala:29:31] TLBusBypass dmiBypass ( // @[Debug.scala:704:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_node_out_out_a_ready (_asource_auto_in_a_ready), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_a_valid (_dmiBypass_auto_node_out_out_a_valid), .auto_node_out_out_a_bits_opcode (_dmiBypass_auto_node_out_out_a_bits_opcode), .auto_node_out_out_a_bits_address (_dmiBypass_auto_node_out_out_a_bits_address), .auto_node_out_out_a_bits_data (_dmiBypass_auto_node_out_out_a_bits_data), .auto_node_out_out_d_ready (_dmiBypass_auto_node_out_out_d_ready), .auto_node_out_out_d_valid (_asource_auto_in_d_valid), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_opcode (_asource_auto_in_d_bits_opcode), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_param (_asource_auto_in_d_bits_param), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_size (_asource_auto_in_d_bits_size), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_source (_asource_auto_in_d_bits_source), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_sink (_asource_auto_in_d_bits_sink), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_denied (_asource_auto_in_d_bits_denied), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_data (_asource_auto_in_d_bits_data), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_corrupt (_asource_auto_in_d_bits_corrupt), // @[AsyncCrossing.scala:94:29] .auto_node_in_in_a_ready (_dmiBypass_auto_node_in_in_a_ready), .auto_node_in_in_a_valid (_dmiXbar_auto_anon_out_0_a_valid), // @[Debug.scala:675:28] .auto_node_in_in_a_bits_opcode (_dmiXbar_auto_anon_out_0_a_bits_opcode), // @[Debug.scala:675:28] .auto_node_in_in_a_bits_address (_dmiXbar_auto_anon_out_0_a_bits_address), // @[Debug.scala:675:28] .auto_node_in_in_a_bits_data (_dmiXbar_auto_anon_out_0_a_bits_data), // @[Debug.scala:675:28] .auto_node_in_in_d_ready (_dmiXbar_auto_anon_out_0_d_ready), // @[Debug.scala:675:28] .auto_node_in_in_d_valid (_dmiBypass_auto_node_in_in_d_valid), .auto_node_in_in_d_bits_opcode (_dmiBypass_auto_node_in_in_d_bits_opcode), .auto_node_in_in_d_bits_param (_dmiBypass_auto_node_in_in_d_bits_param), .auto_node_in_in_d_bits_size (_dmiBypass_auto_node_in_in_d_bits_size), .auto_node_in_in_d_bits_source (_dmiBypass_auto_node_in_in_d_bits_source), .auto_node_in_in_d_bits_sink (_dmiBypass_auto_node_in_in_d_bits_sink), .auto_node_in_in_d_bits_denied (_dmiBypass_auto_node_in_in_d_bits_denied), .auto_node_in_in_d_bits_data (_dmiBypass_auto_node_in_in_d_bits_data), .auto_node_in_in_d_bits_corrupt (_dmiBypass_auto_node_in_in_d_bits_corrupt), .io_bypass (_dmiBypass_io_bypass_T_2) // @[Debug.scala:742:55] ); // @[Debug.scala:704:29] TLAsyncCrossingSource_a9d32s1k1z2u asource ( // @[AsyncCrossing.scala:94:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_asource_auto_in_a_ready), .auto_in_a_valid (_dmiBypass_auto_node_out_out_a_valid), // @[Debug.scala:704:29] .auto_in_a_bits_opcode (_dmiBypass_auto_node_out_out_a_bits_opcode), // @[Debug.scala:704:29] .auto_in_a_bits_address (_dmiBypass_auto_node_out_out_a_bits_address), // @[Debug.scala:704:29] .auto_in_a_bits_data (_dmiBypass_auto_node_out_out_a_bits_data), // @[Debug.scala:704:29] .auto_in_d_ready (_dmiBypass_auto_node_out_out_d_ready), // @[Debug.scala:704:29] .auto_in_d_valid (_asource_auto_in_d_valid), .auto_in_d_bits_opcode (_asource_auto_in_d_bits_opcode), .auto_in_d_bits_param (_asource_auto_in_d_bits_param), .auto_in_d_bits_size (_asource_auto_in_d_bits_size), .auto_in_d_bits_source (_asource_auto_in_d_bits_source), .auto_in_d_bits_sink (_asource_auto_in_d_bits_sink), .auto_in_d_bits_denied (_asource_auto_in_d_bits_denied), .auto_in_d_bits_data (_asource_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_asource_auto_in_d_bits_corrupt), .auto_out_a_mem_0_opcode (auto_asource_out_a_mem_0_opcode_0), .auto_out_a_mem_0_address (auto_asource_out_a_mem_0_address_0), .auto_out_a_mem_0_data (auto_asource_out_a_mem_0_data_0), .auto_out_a_ridx (auto_asource_out_a_ridx_0), // @[Debug.scala:709:9] .auto_out_a_widx (auto_asource_out_a_widx_0), .auto_out_a_safe_ridx_valid (auto_asource_out_a_safe_ridx_valid_0), // @[Debug.scala:709:9] .auto_out_a_safe_widx_valid (auto_asource_out_a_safe_widx_valid_0), .auto_out_a_safe_source_reset_n (auto_asource_out_a_safe_source_reset_n_0), .auto_out_a_safe_sink_reset_n (auto_asource_out_a_safe_sink_reset_n_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_opcode (auto_asource_out_d_mem_0_opcode_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_size (auto_asource_out_d_mem_0_size_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_source (auto_asource_out_d_mem_0_source_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_data (auto_asource_out_d_mem_0_data_0), // @[Debug.scala:709:9] .auto_out_d_ridx (auto_asource_out_d_ridx_0), .auto_out_d_widx (auto_asource_out_d_widx_0), // @[Debug.scala:709:9] .auto_out_d_safe_ridx_valid (auto_asource_out_d_safe_ridx_valid_0), .auto_out_d_safe_widx_valid (auto_asource_out_d_safe_widx_valid_0), // @[Debug.scala:709:9] .auto_out_d_safe_source_reset_n (auto_asource_out_d_safe_source_reset_n_0), // @[Debug.scala:709:9] .auto_out_d_safe_sink_reset_n (auto_asource_out_d_safe_sink_reset_n_0) ); // @[AsyncCrossing.scala:94:29] AsyncResetSynchronizerShiftReg_w1_d3_i0_10 dmactiveAck_dmactiveAckSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_ctrl_dmactiveAck_0), // @[Debug.scala:709:9] .io_q (dmactiveAck) ); // @[ShiftReg.scala:45:23] AsyncQueueSource_DebugInternalBundle io_innerCtrl_source ( // @[AsyncQueue.scala:220:24] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_enq_ready (_io_innerCtrl_source_io_enq_ready), .io_enq_valid (_dmOuter_io_innerCtrl_valid), // @[Debug.scala:700:27] .io_enq_bits_resumereq (_dmOuter_io_innerCtrl_bits_resumereq), // @[Debug.scala:700:27] .io_enq_bits_hartsel (_dmOuter_io_innerCtrl_bits_hartsel), // @[Debug.scala:700:27] .io_enq_bits_ackhavereset (_dmOuter_io_innerCtrl_bits_ackhavereset), // @[Debug.scala:700:27] .io_enq_bits_hasel (_dmOuter_io_innerCtrl_bits_hasel), // @[Debug.scala:700:27] .io_enq_bits_hamask_0 (_dmOuter_io_innerCtrl_bits_hamask_0), // @[Debug.scala:700:27] .io_enq_bits_hamask_1 (_dmOuter_io_innerCtrl_bits_hamask_1), // @[Debug.scala:700:27] .io_enq_bits_hamask_2 (_dmOuter_io_innerCtrl_bits_hamask_2), // @[Debug.scala:700:27] .io_enq_bits_hamask_3 (_dmOuter_io_innerCtrl_bits_hamask_3), // @[Debug.scala:700:27] .io_enq_bits_hrmask_0 (_dmOuter_io_innerCtrl_bits_hrmask_0), // @[Debug.scala:700:27] .io_enq_bits_hrmask_1 (_dmOuter_io_innerCtrl_bits_hrmask_1), // @[Debug.scala:700:27] .io_enq_bits_hrmask_2 (_dmOuter_io_innerCtrl_bits_hrmask_2), // @[Debug.scala:700:27] .io_enq_bits_hrmask_3 (_dmOuter_io_innerCtrl_bits_hrmask_3), // @[Debug.scala:700:27] .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), .io_async_mem_0_hasel (io_innerCtrl_mem_0_hasel_0), .io_async_mem_0_hamask_0 (io_innerCtrl_mem_0_hamask_0_0), .io_async_mem_0_hamask_1 (io_innerCtrl_mem_0_hamask_1_0), .io_async_mem_0_hamask_2 (io_innerCtrl_mem_0_hamask_2_0), .io_async_mem_0_hamask_3 (io_innerCtrl_mem_0_hamask_3_0), .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), .io_async_mem_0_hrmask_1 (io_innerCtrl_mem_0_hrmask_1_0), .io_async_mem_0_hrmask_2 (io_innerCtrl_mem_0_hrmask_2_0), .io_async_mem_0_hrmask_3 (io_innerCtrl_mem_0_hrmask_3_0), .io_async_ridx (io_innerCtrl_ridx_0), // @[Debug.scala:709:9] .io_async_widx (io_innerCtrl_widx_0), .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), // @[Debug.scala:709:9] .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) // @[Debug.scala:709:9] ); // @[AsyncQueue.scala:220:24] assign auto_asource_out_a_mem_0_opcode = auto_asource_out_a_mem_0_opcode_0; // @[Debug.scala:709:9] assign auto_asource_out_a_mem_0_address = auto_asource_out_a_mem_0_address_0; // @[Debug.scala:709:9] assign auto_asource_out_a_mem_0_data = auto_asource_out_a_mem_0_data_0; // @[Debug.scala:709:9] assign auto_asource_out_a_widx = auto_asource_out_a_widx_0; // @[Debug.scala:709:9] assign auto_asource_out_a_safe_widx_valid = auto_asource_out_a_safe_widx_valid_0; // @[Debug.scala:709:9] assign auto_asource_out_a_safe_source_reset_n = auto_asource_out_a_safe_source_reset_n_0; // @[Debug.scala:709:9] assign auto_asource_out_d_ridx = auto_asource_out_d_ridx_0; // @[Debug.scala:709:9] assign auto_asource_out_d_safe_ridx_valid = auto_asource_out_d_safe_ridx_valid_0; // @[Debug.scala:709:9] assign auto_asource_out_d_safe_sink_reset_n = auto_asource_out_d_safe_sink_reset_n_0; // @[Debug.scala:709:9] assign auto_int_out_3_sync_0 = auto_int_out_3_sync_0_0; // @[Debug.scala:709:9] assign auto_int_out_2_sync_0 = auto_int_out_2_sync_0_0; // @[Debug.scala:709:9] assign auto_int_out_1_sync_0 = auto_int_out_1_sync_0_0; // @[Debug.scala:709:9] assign auto_int_out_0_sync_0 = auto_int_out_0_sync_0_0; // @[Debug.scala:709:9] assign io_dmi_req_ready = io_dmi_req_ready_0; // @[Debug.scala:709:9] assign io_dmi_resp_valid = io_dmi_resp_valid_0; // @[Debug.scala:709:9] assign io_dmi_resp_bits_data = io_dmi_resp_bits_data_0; // @[Debug.scala:709:9] assign io_dmi_resp_bits_resp = io_dmi_resp_bits_resp_0; // @[Debug.scala:709:9] assign io_ctrl_ndreset = io_ctrl_ndreset_0; // @[Debug.scala:709:9] assign io_ctrl_dmactive = io_ctrl_dmactive_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_resumereq = io_innerCtrl_mem_0_resumereq_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hartsel = io_innerCtrl_mem_0_hartsel_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_ackhavereset = io_innerCtrl_mem_0_ackhavereset_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hasel = io_innerCtrl_mem_0_hasel_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_0 = io_innerCtrl_mem_0_hamask_0_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_1 = io_innerCtrl_mem_0_hamask_1_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_2 = io_innerCtrl_mem_0_hamask_2_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_3 = io_innerCtrl_mem_0_hamask_3_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_0 = io_innerCtrl_mem_0_hrmask_0_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_1 = io_innerCtrl_mem_0_hrmask_1_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_2 = io_innerCtrl_mem_0_hrmask_2_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_3 = io_innerCtrl_mem_0_hrmask_3_0; // @[Debug.scala:709:9] assign io_innerCtrl_widx = io_innerCtrl_widx_0; // @[Debug.scala:709:9] assign io_innerCtrl_safe_widx_valid = io_innerCtrl_safe_widx_valid_0; // @[Debug.scala:709:9] assign io_innerCtrl_safe_source_reset_n = io_innerCtrl_safe_source_reset_n_0; // @[Debug.scala:709:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLSerdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ object TLSerdesser { // This should be the standard bundle type for TLSerdesser val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters( addressBits=64, dataBits=64, sourceBits=8, sinkBits=8, sizeBits=8, echoFields=Nil, requestFields=Nil, responseFields=Nil, hasBCE=true) } class SerdesDebugIO extends Bundle { val ser_busy = Output(Bool()) val des_busy = Output(Bool()) } class TLSerdesser( val flitWidth: Int, clientPortParams: Option[TLMasterPortParameters], managerPortParams: Option[TLSlavePortParameters], val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS, nameSuffix: Option[String] = None ) (implicit p: Parameters) extends LazyModule { require (clientPortParams.isDefined \|\| managerPortParams.isDefined) val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) } val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) } override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_") lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ser = Vec(5, new DecoupledFlitIO(flitWidth)) val debug = new SerdesDebugIO }) val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val client_edge = clientNode.map(_.out(0)._2) val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val manager_edge = managerNode.map(_.in(0)._2) val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams) val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams) val mergedParams = clientParams.union(managerParams).union(bundleParams) require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields") require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields") require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields") require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams") val out_channels = Seq( (manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))), (client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))), (manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))), (client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))), (manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix)))) ) io.ser.map(_.out.valid := false.B) io.ser.map(_.out.bits := DontCare) val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b => b.io.protocol <> c val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i") ser.io.in <> b.io.beat io.ser(i).out <> ser.io.out ser }}.flatten io.debug.ser_busy := out_sers.map(_.io.busy).orR val in_channels = Seq( (client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))), (manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))), (client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))), (manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))), (client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix))) ) val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) => c <> b.io.protocol val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i") des.io.in <> io.ser(i).in b.io.beat <> des.io.out des } io.debug.des_busy := in_desers.map(_.io.busy).orR } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_0_out_ready, // @[TLSerdes.scala:40:16] output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_2_out_ready, // @[TLSerdes.scala:40:16] output io_ser_2_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_4_out_ready, // @[TLSerdes.scala:40:16] output io_ser_4_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28] wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_4_io_busy; // @[TLSerdes.scala:69:23] wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50] wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50] wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50] wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50] wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9] wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9] wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] _out_channels_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] out_channels_0_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17] wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61] wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire _io_debug_ser_busy_T_1; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy; // @[TLSerdes.scala:39:9] wire io_debug_des_busy; // @[TLSerdes.scala:39:9] assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_a_valid; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_c_valid; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71] wire client_tl_e_valid; // @[TLSerdes.scala:45:71] wire _io_debug_ser_busy_T; // @[package.scala:81:59] assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T \| _ser_4_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9] wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61] wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61] wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61] wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61] wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61] wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61] wire in_channels_3_1_valid; // @[Bundles.scala:264:61] assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[2:0]; // @[TLSerdes.scala:79:28, :85:9] assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T \| _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 \| _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 \| _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLMonitor_87 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_0_2_io_beat_bits_head) ); // @[TLSerdes.scala:59:50] TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_2_2_io_beat_bits_head) ); // @[TLSerdes.scala:61:50] TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_a_ready), .io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21] .io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_4_2_io_beat_valid), .io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_4_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail) ); // @[TLSerdes.scala:63:50] GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_0_io_in_ready), .io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50] .io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_bits_flit (io_ser_0_out_bits_flit_0) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_2_io_in_ready), .io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50] .io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_2_out_valid_0), .io_out_bits_flit (io_ser_2_out_bits_flit_0), .io_busy (_io_debug_ser_busy_T) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_4_io_in_ready), .io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50] .io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50] .io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50] .io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50] .io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_4_out_valid_0), .io_out_bits_flit (io_ser_4_out_bits_flit_0), .io_busy (_ser_4_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_e_valid), .io_protocol_bits_sink (client_tl_e_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_protocol_valid (managerNodeIn_d_valid), .io_protocol_bits_opcode (managerNodeIn_d_bits_opcode), .io_protocol_bits_param (managerNodeIn_d_bits_param), .io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source), .io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink), .io_protocol_bits_denied (managerNodeIn_d_bits_denied), .io_protocol_bits_data (managerNodeIn_d_bits_data), .io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_c_valid), .io_protocol_bits_opcode (client_tl_c_bits_opcode), .io_protocol_bits_param (client_tl_c_bits_param), .io_protocol_bits_size (client_tl_c_bits_size), .io_protocol_bits_source (client_tl_c_bits_source), .io_protocol_bits_address (client_tl_c_bits_address), .io_protocol_bits_data (client_tl_c_bits_data), .io_protocol_bits_corrupt (client_tl_c_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_3_1_valid), .io_protocol_bits_opcode (in_channels_3_1_bits_opcode), .io_protocol_bits_param (in_channels_3_1_bits_param), .io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address), .io_protocol_bits_mask (in_channels_3_1_bits_mask), .io_protocol_bits_data (in_channels_3_1_bits_data), .io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_a_valid), .io_protocol_bits_opcode (client_tl_a_bits_opcode), .io_protocol_bits_param (client_tl_a_bits_param), .io_protocol_bits_size (client_tl_a_bits_size), .io_protocol_bits_source (client_tl_a_bits_source), .io_protocol_bits_address (client_tl_a_bits_address), .io_protocol_bits_mask (client_tl_a_bits_mask), .io_protocol_bits_data (client_tl_a_bits_data), .io_protocol_bits_corrupt (client_tl_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //**************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander / * Mixin for issue queue types / trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /* * Mixin for scalar operation constants / trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //********************************* // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //******************************** // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } / * Mixin for RISCV constants / trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /* * Mixin for exception cause constants / trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //*************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ / * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot / class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /* * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports / class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) \|\| (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned \|\| p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid \|\| io.clear \|\| io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br \|\| slot_uop.is_jal \|\| slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 \|\| p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) \|\| (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned \|\| p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }	module IssueSlot_56( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready \|\| !io.in.bits.head \|\| at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid \|\| !head) && (io.vcalloc_req.ready \|\| !head) && (vcalloc_q.io.enq.ready \|\| !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_\|\|_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }	module IngressUnit_54( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h28; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h31; // @[IngressUnit.scala:30:72] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24_16( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_16 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_16 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_16 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_71( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /* This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_cbus_out_i1_o8_a29d64s7k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire requestAIO_0_0 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], ~(auto_anon_in_a_bits_address[13:12])} == 7'h0; // @[Xbar.scala:222:41] wire [9:0] _GEN = auto_anon_in_a_bits_address[25:16] ^ 10'h201; // @[Xbar.scala:222:41] wire requestAIO_0_1 = {auto_anon_in_a_bits_address[28:27], _GEN[9], auto_anon_in_a_bits_address[20], _GEN[0], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41] wire requestAIO_0_2 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13], ~(auto_anon_in_a_bits_address[12])} == 7'h0 \| {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12] ^ 2'h2} == 7'h0 \| {auto_anon_in_a_bits_address[28:27] ^ 2'h2, auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41, :291:92] wire requestAIO_0_3 = {auto_anon_in_a_bits_address[28:27], ~(auto_anon_in_a_bits_address[25]), auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16]} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}] wire requestAIO_0_4 = {auto_anon_in_a_bits_address[28], ~(auto_anon_in_a_bits_address[27])} == 2'h0; // @[Xbar.scala:222:41] wire requestAIO_0_5 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41] wire requestAIO_0_6 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], ~(auto_anon_in_a_bits_address[16])} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}] wire requestAIO_0_7 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], ~(auto_anon_in_a_bits_address[20]), auto_anon_in_a_bits_address[13:12]} == 6'h0; // @[Xbar.scala:222:41] wire _portsAOI_in_0_a_ready_T_14 = requestAIO_0_0 & auto_anon_out_0_a_ready \| requestAIO_0_1 & auto_anon_out_1_a_ready \| requestAIO_0_2 & auto_anon_out_2_a_ready \| requestAIO_0_3 & auto_anon_out_3_a_ready \| requestAIO_0_4 & auto_anon_out_4_a_ready \| requestAIO_0_5 & auto_anon_out_5_a_ready \| requestAIO_0_6 & auto_anon_out_6_a_ready \| requestAIO_0_7 & auto_anon_out_7_a_ready; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [7:0] readys_valid = {auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [7:0] readys_mask; // @[Arbiter.scala:23:23] wire [7:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [13:0] _GEN_0 = {_readys_filter_T_1[6:0], auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid} \| {_readys_filter_T_1, auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid}; // @[package.scala:262:{43,48}] wire [12:0] _GEN_1 = _GEN_0[12:0] \| {_readys_filter_T_1[7], _GEN_0[13:2]}; // @[package.scala:262:{43,48}] wire [10:0] _GEN_2 = _GEN_1[10:0] \| {_readys_filter_T_1[7], _GEN_0[13], _GEN_1[12:4]}; // @[package.scala:262:{43,48}] wire [7:0] readys_readys = ~({readys_mask[7], _readys_filter_T_1[7] \| readys_mask[6], _GEN_0[13] \| readys_mask[5], _GEN_1[12:11] \| readys_mask[4:3], _GEN_2[10:8] \| readys_mask[2:0]} & _GEN_2[7:0]); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_2 = readys_readys[2] & auto_anon_out_2_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_3 = readys_readys[3] & auto_anon_out_3_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_4 = readys_readys[4] & auto_anon_out_4_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_5 = readys_readys[5] & auto_anon_out_5_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_6 = readys_readys[6] & auto_anon_out_6_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_7 = readys_readys[7] & auto_anon_out_7_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid \| auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_117( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_359( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File memory.scala: //************************************************************************** // Scratchpad Memory (asynchronous) //-------------------------------------------------------------------------- // // Christopher Celio // 2013 Jun 12 // // Provides a variable number of ports to the core, and one port to the HTIF // (host-target interface). // // Assumes that if the port is ready, it will be performed immediately. // For now, don't detect write collisions. // // Optionally uses synchronous read (default is async). For example, a 1-stage // processor can only ever work using asynchronous memory! package sodor.common import chisel3._ import chisel3.util._ import chisel3.experimental._ import Constants._ import sodor.common.Util._ trait MemoryOpConstants { val MT_X = 0.asUInt(3.W) val MT_B = 1.asUInt(3.W) val MT_H = 2.asUInt(3.W) val MT_W = 3.asUInt(3.W) val MT_D = 4.asUInt(3.W) val MT_BU = 5.asUInt(3.W) val MT_HU = 6.asUInt(3.W) val MT_WU = 7.asUInt(3.W) val M_X = "b0".asUInt(1.W) val M_XRD = "b0".asUInt(1.W) // int load val M_XWR = "b1".asUInt(1.W) // int store val DPORT = 0 val IPORT = 1 } // from the pov of the datapath class MemPortIo(data_width: Int)(implicit val conf: SodorCoreParams) extends Bundle { val req = new DecoupledIO(new MemReq(data_width)) val resp = Flipped(new ValidIO(new MemResp(data_width))) } class MemReq(data_width: Int)(implicit val conf: SodorCoreParams) extends Bundle { val addr = Output(UInt(conf.xprlen.W)) val data = Output(UInt(data_width.W)) val fcn = Output(UInt(M_X.getWidth.W)) // memory function code val typ = Output(UInt(MT_X.getWidth.W)) // memory type // To convert MemPortIO type to sign and size in TileLink format: subtract 1 from type, then take inversed MSB as signedness // and the remaining two bits as TileLink size def getTLSize = (typ - 1.U)(1, 0) def getTLSigned = ~(typ - 1.U)(2) def setType(tlSigned: Bool, tlSize: UInt) = { typ := Cat(~tlSigned, tlSize + 1.U) } } class MemResp(data_width: Int) extends Bundle { val data = Output(UInt(data_width.W)) } // Note: All `size` field in this class are base 2 logarithm class MemoryModule(numBytes: Int, useAsync: Boolean) { val addrWidth = log2Ceil(numBytes) val mem = if (useAsync) Mem(numBytes / 4, Vec(4, UInt(8.W))) else SyncReadMem(numBytes / 4, Vec(4, UInt(8.W))) // Convert size exponent to actual number of bytes - 1 private def sizeToBytes(size: UInt) = MuxLookup(size, 3.U)(List(0.U -> 0.U, 1.U -> 1.U, 2.U -> 3.U)) private def getMask(bytes: UInt, storeOffset: UInt = 0.U) = { val mask = ("b00011111".U(8.W) << bytes).apply(7, 4) val maskWithOffset = (mask << storeOffset).apply(3, 0) maskWithOffset.asBools.reverse } private def splitWord(data: UInt) = VecInit(((data(31, 0).asBools.reverse grouped 8) map (bools => Cat(bools))).toSeq) // Read function def read(addr: UInt, size: UInt, signed: Bool) = { // Create a module to show signal inside class MemReader extends Module { val io = IO(new Bundle { val addr = Input(UInt(addrWidth.W)) val size = Input(UInt(2.W)) val signed = Input(Bool()) val data = Output(UInt(32.W)) val mem_addr = Output(UInt((addrWidth - 2).W)) val mem_data = Input(Vec(4, UInt(8.W))) }) // Sync argument if needed val s_offset = if (useAsync) io.addr(1, 0) else RegNext(io.addr(1, 0)) val s_size = if (useAsync) io.size else RegNext(io.size) val s_signed = if (useAsync) io.signed else RegNext(io.signed) // Read data from the banks and align io.mem_addr := io.addr(addrWidth - 1, 2) val readVec = io.mem_data val shiftedVec = splitWord(Cat(readVec) >> (s_offset << 3)) // Mask data according to the size val bytes = sizeToBytes(s_size) val sign = shiftedVec(3.U - bytes).apply(7) val masks = getMask(bytes) val maskedVec = (shiftedVec zip masks) map ({ case (byte, mask) => Mux(sign && s_signed, byte \| ~Fill(8, mask), byte & Fill(8, mask)) }) io.data := Cat(maskedVec) } val memreader = Module(new MemReader) memreader.io.addr := addr memreader.io.size := size memreader.io.signed := signed memreader.io.mem_data := mem.read(memreader.io.mem_addr) memreader.io.data } def apply(addr: UInt, size: UInt, signed: Bool) = read(addr, size, signed) // Write function def write(addr: UInt, data: UInt, size: UInt, en: Bool) = { // Create a module to show signal inside class MemWriter extends Module { val io = IO(new Bundle { val addr = Input(UInt(addrWidth.W)) val data = Input(UInt(32.W)) val size = Input(UInt(2.W)) val en = Input(Bool()) val mem_addr = Output(UInt((addrWidth - 2).W)) val mem_data = Output(Vec(4, UInt(8.W))) val mem_masks = Output(Vec(4, Bool())) }) // Align data and mask val offset = io.addr(1, 0) val shiftedVec = splitWord(io.data << (offset << 3)) val masks = getMask(sizeToBytes(io.size), offset) // Write io.mem_addr := io.addr(addrWidth - 1, 2) io.mem_data := shiftedVec io.mem_masks := VecInit(masks map (mask => mask && io.en)) } val memwriter = Module(new MemWriter) memwriter.io.addr := addr memwriter.io.data := data memwriter.io.size := size memwriter.io.en := en when (en) { mem.write(memwriter.io.mem_addr, memwriter.io.mem_data, memwriter.io.mem_masks) } } } // NOTE: the default is enormous (and may crash your computer), but is bound by // what the fesvr expects the smallest memory size to be. A proper fix would // be to modify the fesvr to expect smaller sizes. //for 1,2 and 5 stage need for combinational reads class ScratchPadMemoryBase(num_core_ports: Int, num_bytes: Int = (1 << 21), useAsync: Boolean = true)(implicit val conf: SodorCoreParams) extends Module { val io = IO(new Bundle { val core_ports = Vec(num_core_ports, Flipped(new MemPortIo(data_width = conf.xprlen)) ) val debug_port = Flipped(new MemPortIo(data_width = 32)) }) val num_bytes_per_line = 8 val num_lines = num_bytes / num_bytes_per_line println("\n Sodor Tile: creating Asynchronous Scratchpad Memory of size " + num_lines*num_bytes_per_line/1024 + " kB\n") val async_data = new MemoryModule(num_bytes, useAsync) for (i <- 0 until num_core_ports) { io.core_ports(i).resp.valid := (if (useAsync) io.core_ports(i).req.valid else RegNext(io.core_ports(i).req.valid, false.B)) io.core_ports(i).req.ready := true.B // for now, no back pressure } /////////// DPORT val req_addri = io.core_ports(DPORT).req.bits.addr val dport_req = io.core_ports(DPORT).req.bits val dport_wen = io.core_ports(DPORT).req.valid && dport_req.fcn === M_XWR io.core_ports(DPORT).resp.bits.data := async_data.read(dport_req.addr, dport_req.getTLSize, dport_req.getTLSigned) async_data.write(dport_req.addr, dport_req.data, dport_req.getTLSize, dport_wen) ///////////////// ///////////// IPORT if (num_core_ports == 2){ val iport_req = io.core_ports(IPORT).req.bits io.core_ports(IPORT).resp.bits.data := async_data.read(iport_req.addr, iport_req.getTLSize, iport_req.getTLSigned) } //////////// // DEBUG PORT------- io.debug_port.req.ready := true.B // for now, no back pressure io.debug_port.resp.valid := (if (useAsync) io.debug_port.req.valid else RegNext(io.debug_port.req.valid, false.B)) // asynchronous read val debug_port_req = io.debug_port.req.bits val debug_port_wen = io.debug_port.req.valid && debug_port_req.fcn === M_XWR io.debug_port.resp.bits.data := async_data.read(debug_port_req.addr, debug_port_req.getTLSize, debug_port_req.getTLSigned) async_data.write(debug_port_req.addr, debug_port_req.data, debug_port_req.getTLSize, debug_port_wen) } class AsyncScratchPadMemory(num_core_ports: Int, num_bytes: Int = (1 << 21))(implicit conf: SodorCoreParams) extends ScratchPadMemoryBase(num_core_ports, num_bytes, true)(conf) class SyncScratchPadMemory(num_core_ports: Int, num_bytes: Int = (1 << 21))(implicit conf: SodorCoreParams) extends ScratchPadMemoryBase(num_core_ports, num_bytes, false)(conf)	module MemWriter_1( // @[memory.scala:133:13] input clock, // @[memory.scala:133:13] input reset, // @[memory.scala:133:13] input [20:0] io_addr, // @[memory.scala:134:21] input [31:0] io_data, // @[memory.scala:134:21] input [1:0] io_size, // @[memory.scala:134:21] input io_en, // @[memory.scala:134:21] output [18:0] io_mem_addr, // @[memory.scala:134:21] output [7:0] io_mem_data_0, // @[memory.scala:134:21] output [7:0] io_mem_data_1, // @[memory.scala:134:21] output [7:0] io_mem_data_2, // @[memory.scala:134:21] output [7:0] io_mem_data_3, // @[memory.scala:134:21] output io_mem_masks_0, // @[memory.scala:134:21] output io_mem_masks_1, // @[memory.scala:134:21] output io_mem_masks_2, // @[memory.scala:134:21] output io_mem_masks_3 // @[memory.scala:134:21] ); wire [20:0] io_addr_0 = io_addr; // @[memory.scala:133:13] wire [31:0] io_data_0 = io_data; // @[memory.scala:133:13] wire [1:0] io_size_0 = io_size; // @[memory.scala:133:13] wire io_en_0 = io_en; // @[memory.scala:133:13] wire [18:0] _io_mem_addr_T; // @[memory.scala:151:32] wire [7:0] shiftedVec_0; // @[memory.scala:84:47] wire [7:0] shiftedVec_1; // @[memory.scala:84:47] wire [7:0] shiftedVec_2; // @[memory.scala:84:47] wire [7:0] shiftedVec_3; // @[memory.scala:84:47] wire [7:0] io_mem_data_0_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_1_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_2_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_3_0; // @[memory.scala:133:13] wire io_mem_masks_0_0; // @[memory.scala:133:13] wire io_mem_masks_1_0; // @[memory.scala:133:13] wire io_mem_masks_2_0; // @[memory.scala:133:13] wire io_mem_masks_3_0; // @[memory.scala:133:13] wire [18:0] io_mem_addr_0; // @[memory.scala:133:13] wire [1:0] offset = io_addr_0[1:0]; // @[memory.scala:133:13, :146:30] wire [4:0] _shiftedVec_T = {offset, 3'h0}; // @[memory.scala:146:30, :147:56] wire [62:0] _shiftedVec_T_1 = {31'h0, io_data_0} << _shiftedVec_T; // @[memory.scala:133:13, :147:{45,56}] wire [31:0] _shiftedVec_T_2 = _shiftedVec_T_1[31:0]; // @[memory.scala:84:54, :147:45] wire _shiftedVec_T_3 = _shiftedVec_T_2[0]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_4 = _shiftedVec_T_2[1]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_5 = _shiftedVec_T_2[2]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_6 = _shiftedVec_T_2[3]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_7 = _shiftedVec_T_2[4]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_8 = _shiftedVec_T_2[5]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_9 = _shiftedVec_T_2[6]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_10 = _shiftedVec_T_2[7]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_11 = _shiftedVec_T_2[8]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_12 = _shiftedVec_T_2[9]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_13 = _shiftedVec_T_2[10]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_14 = _shiftedVec_T_2[11]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_15 = _shiftedVec_T_2[12]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_16 = _shiftedVec_T_2[13]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_17 = _shiftedVec_T_2[14]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_18 = _shiftedVec_T_2[15]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_19 = _shiftedVec_T_2[16]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_20 = _shiftedVec_T_2[17]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_21 = _shiftedVec_T_2[18]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_22 = _shiftedVec_T_2[19]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_23 = _shiftedVec_T_2[20]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_24 = _shiftedVec_T_2[21]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_25 = _shiftedVec_T_2[22]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_26 = _shiftedVec_T_2[23]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_27 = _shiftedVec_T_2[24]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_28 = _shiftedVec_T_2[25]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_29 = _shiftedVec_T_2[26]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_30 = _shiftedVec_T_2[27]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_31 = _shiftedVec_T_2[28]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_32 = _shiftedVec_T_2[29]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_33 = _shiftedVec_T_2[30]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_34 = _shiftedVec_T_2[31]; // @[memory.scala:84:{54,62}] wire [1:0] shiftedVec_lo_lo = {_shiftedVec_T_28, _shiftedVec_T_27}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi = {_shiftedVec_T_30, _shiftedVec_T_29}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo = {shiftedVec_lo_hi, shiftedVec_lo_lo}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo = {_shiftedVec_T_32, _shiftedVec_T_31}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi = {_shiftedVec_T_34, _shiftedVec_T_33}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi = {shiftedVec_hi_hi, shiftedVec_hi_lo}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_35 = {shiftedVec_hi, shiftedVec_lo}; // @[memory.scala:84:106] assign shiftedVec_0 = _shiftedVec_T_35; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_1 = {_shiftedVec_T_20, _shiftedVec_T_19}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_1 = {_shiftedVec_T_22, _shiftedVec_T_21}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_1 = {shiftedVec_lo_hi_1, shiftedVec_lo_lo_1}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_1 = {_shiftedVec_T_24, _shiftedVec_T_23}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_1 = {_shiftedVec_T_26, _shiftedVec_T_25}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_1 = {shiftedVec_hi_hi_1, shiftedVec_hi_lo_1}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_36 = {shiftedVec_hi_1, shiftedVec_lo_1}; // @[memory.scala:84:106] assign shiftedVec_1 = _shiftedVec_T_36; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_2 = {_shiftedVec_T_12, _shiftedVec_T_11}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_2 = {_shiftedVec_T_14, _shiftedVec_T_13}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_2 = {shiftedVec_lo_hi_2, shiftedVec_lo_lo_2}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_2 = {_shiftedVec_T_16, _shiftedVec_T_15}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_2 = {_shiftedVec_T_18, _shiftedVec_T_17}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_2 = {shiftedVec_hi_hi_2, shiftedVec_hi_lo_2}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_37 = {shiftedVec_hi_2, shiftedVec_lo_2}; // @[memory.scala:84:106] assign shiftedVec_2 = _shiftedVec_T_37; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_3 = {_shiftedVec_T_4, _shiftedVec_T_3}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_3 = {_shiftedVec_T_6, _shiftedVec_T_5}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_3 = {shiftedVec_lo_hi_3, shiftedVec_lo_lo_3}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_3 = {_shiftedVec_T_8, _shiftedVec_T_7}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_3 = {_shiftedVec_T_10, _shiftedVec_T_9}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_3 = {shiftedVec_hi_hi_3, shiftedVec_hi_lo_3}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_38 = {shiftedVec_hi_3, shiftedVec_lo_3}; // @[memory.scala:84:106] assign shiftedVec_3 = _shiftedVec_T_38; // @[memory.scala:84:{47,106}] assign io_mem_data_0_0 = shiftedVec_0; // @[memory.scala:84:47, :133:13] assign io_mem_data_1_0 = shiftedVec_1; // @[memory.scala:84:47, :133:13] assign io_mem_data_2_0 = shiftedVec_2; // @[memory.scala:84:47, :133:13] assign io_mem_data_3_0 = shiftedVec_3; // @[memory.scala:84:47, :133:13] wire _masks_T = io_size_0 == 2'h0; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_1 = _masks_T ? 2'h0 : 2'h3; // @[memory.scala:76:62] wire _masks_T_2 = io_size_0 == 2'h1; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_3 = _masks_T_2 ? 2'h1 : _masks_T_1; // @[memory.scala:76:62] wire _masks_T_4 = io_size_0 == 2'h2; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_5 = _masks_T_4 ? 2'h3 : _masks_T_3; // @[memory.scala:76:62] wire [10:0] _masks_mask_T = 11'h1F << _masks_T_5; // @[memory.scala:76:62, :79:38] wire [3:0] masks_mask = _masks_mask_T[7:4]; // @[memory.scala:79:{38,53}] wire [6:0] _masks_maskWithOffset_T = {3'h0, masks_mask} << offset; // @[memory.scala:79:53, :80:34, :146:30, :147:56] wire [3:0] masks_maskWithOffset = _masks_maskWithOffset_T[3:0]; // @[memory.scala:80:{34,55}] wire masks_3 = masks_maskWithOffset[0]; // @[memory.scala:80:55, :81:22] wire masks_2 = masks_maskWithOffset[1]; // @[memory.scala:80:55, :81:22] wire masks_1 = masks_maskWithOffset[2]; // @[memory.scala:80:55, :81:22] wire masks_0 = masks_maskWithOffset[3]; // @[memory.scala:80:55, :81:22] assign _io_mem_addr_T = io_addr_0[20:2]; // @[memory.scala:133:13, :151:32] assign io_mem_addr_0 = _io_mem_addr_T; // @[memory.scala:133:13, :151:32] assign io_mem_masks_0_0 = masks_0 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_1_0 = masks_1 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_2_0 = masks_2 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_3_0 = masks_3 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_addr = io_mem_addr_0; // @[memory.scala:133:13] assign io_mem_data_0 = io_mem_data_0_0; // @[memory.scala:133:13] assign io_mem_data_1 = io_mem_data_1_0; // @[memory.scala:133:13] assign io_mem_data_2 = io_mem_data_2_0; // @[memory.scala:133:13] assign io_mem_data_3 = io_mem_data_3_0; // @[memory.scala:133:13] assign io_mem_masks_0 = io_mem_masks_0_0; // @[memory.scala:133:13] assign io_mem_masks_1 = io_mem_masks_1_0; // @[memory.scala:133:13] assign io_mem_masks_2 = io_mem_masks_2_0; // @[memory.scala:133:13] assign io_mem_masks_3 = io_mem_masks_3_0; // @[memory.scala:133:13] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_22( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_278 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_63 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_117 = _source_ok_T_116 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_118 = _source_ok_T_117 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_119 = _source_ok_T_118 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_120 = _source_ok_T_119 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_121 = _source_ok_T_120 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_127 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _T_1505 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1505; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1505; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1578 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1578; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1578; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1578; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1431 = _T_1505 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1431 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1431 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1431 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1431 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1431 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1477 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1477 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1446 = _T_1578 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1446 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1446 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1446 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1549 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1549 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1531 = _T_1578 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1531 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1531 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1531 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_8(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_75( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_151 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired \|\| fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module Router_20( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_8_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_8_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_8_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_8_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_6_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_6_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_8_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module IntSyncSyncCrossingSink_n1x5_2( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] input auto_in_sync_2, // @[LazyModuleImp.scala:107:25] input auto_in_sync_3, // @[LazyModuleImp.scala:107:25] input auto_in_sync_4, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1, // @[LazyModuleImp.scala:107:25] output auto_out_2, // @[LazyModuleImp.scala:107:25] output auto_out_3, // @[LazyModuleImp.scala:107:25] output auto_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire auto_in_sync_2_0 = auto_in_sync_2; // @[Crossing.scala:96:9] wire auto_in_sync_3_0 = auto_in_sync_3; // @[Crossing.scala:96:9] wire auto_in_sync_4_0 = auto_in_sync_4; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeIn_sync_2 = auto_in_sync_2_0; // @[Crossing.scala:96:9] wire nodeIn_sync_3 = auto_in_sync_3_0; // @[Crossing.scala:96:9] wire nodeIn_sync_4 = auto_in_sync_4_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire nodeOut_2; // @[MixedNode.scala:542:17] wire nodeOut_3; // @[MixedNode.scala:542:17] wire nodeOut_4; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] wire auto_out_2_0; // @[Crossing.scala:96:9] wire auto_out_3_0; // @[Crossing.scala:96:9] wire auto_out_4_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_2 = nodeIn_sync_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_3 = nodeIn_sync_3; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_4 = nodeIn_sync_4; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_2_0 = nodeOut_2; // @[Crossing.scala:96:9] assign auto_out_3_0 = nodeOut_3; // @[Crossing.scala:96:9] assign auto_out_4_0 = nodeOut_4; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] assign auto_out_2 = auto_out_2_0; // @[Crossing.scala:96:9] assign auto_out_3 = auto_out_3_0; // @[Crossing.scala:96:9] assign auto_out_4 = auto_out_4_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }	module AsyncResetRegVec_w1_i0_43( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_1 = 1'h1; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = 1'h1; // @[Mux.scala:30:73] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [1:0] io_in_b_bits_source = 2'h1; // @[Monitor.scala:36:7] wire [1:0] _legal_source_T_6 = 2'h1; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = 2'h1; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = 2'h1; // @[Mux.scala:30:73] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_5 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] _legal_source_T_3 = 2'h0; // @[Mux.scala:30:73] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_20 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_22 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_23 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24( // @[MulAddRecFN.scala:300:7] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = 48'h0; // @[MulAddRecFN.scala:327:45] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [48:0] mulAddResult = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_8 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }	module TLAtomicAutomata_pbus( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _a_canLogical_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_canArithmetic_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83] wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60] wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85] wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _source_c_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _a_canLogical_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canLogical_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canLogical_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canLogical = 1'h0; // @[AtomicAutomata.scala:94:45] wire _a_canArithmetic_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canArithmetic_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canArithmetic_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canArithmetic = 1'h0; // @[AtomicAutomata.scala:95:45] wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [29:0] _a_canLogical_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canLogical_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_6 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27] wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9] wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9] wire [2:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28] wire [28:0] _a_canLogical_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28] wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28] wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28] wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] wire [2:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17] wire [2:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34] reg [7:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] wire [7:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] _source_c_bits_legal_T_4 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = ~(\|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44] wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58] wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82] wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire cam_amo_0; // @[AtomicAutomata.scala:87:44] assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44] wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68] assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68] wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56] wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80] wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28] wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49] wire cam_abusy_0 = _cam_abusy_T \| _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}] wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96] wire cam_dmatch_0 = \|cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49] wire [29:0] _a_canLogical_T_2 = {1'h0, _a_canLogical_T_1}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_2 = {1'h0, _a_canArithmetic_T_1}; // @[Parameters.scala:137:{31,41}] wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47] wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47] wire _a_isSupported_T = ~a_isArithmetic; // @[AtomicAutomata.scala:97:47, :98:63] wire a_isSupported = ~a_isLogical & _a_isSupported_T; // @[AtomicAutomata.scala:96:47, :98:{32,63}] wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}] wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}] wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57] wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28] wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42] wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42] wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39] wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25] wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39] wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] \| _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}] wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}] wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29] wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29] wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38] wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}] wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}] wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38] wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}] wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}] wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_2 = signbit_a \| _signext_a_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_5 = _signext_a_T_2 \| _signext_a_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_8 = _signext_a_T_5 \| _signext_a_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17] wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17] wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17] wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17] wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17] wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17] wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17] wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17] wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40] wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40] wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_2 = signbit_d \| _signext_d_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_5 = _signext_d_T_2 \| _signext_d_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_8 = _signext_d_T_5 \| _signext_d_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17] wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17] wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17] wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17] wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17] wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17] wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17] wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17] wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40] wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40] wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40] wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28] wire [63:0] a_a_ext = _a_a_ext_T \| signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}] wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28] wire [63:0] a_d_ext = _a_d_ext_T \| signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}] wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43] wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}] wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33] wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33] wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49] wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35] wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}] wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50] wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}] wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65] wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}] wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}] wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31] wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50] wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}] wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34] wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}] wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17] wire _source_i_ready_T; // @[Arbiter.scala:94:31] wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38] wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28] wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28] wire source_i_ready; // @[AtomicAutomata.scala:154:28] wire source_i_valid; // @[AtomicAutomata.scala:154:28] wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23] wire _a_allow_T_1 = a_isSupported \| cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53] wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}] assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38] assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32] assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32] wire _source_c_ready_T; // @[Arbiter.scala:94:31] wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17] wire source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [2:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28] wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28] wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28] wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28] wire source_c_ready; // @[AtomicAutomata.scala:165:28] wire _source_c_bits_T = cam_a_0_bits_corrupt \| cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45] assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17] wire _source_c_bits_legal_T_1 = cam_a_0_bits_size != 3'h7; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29] wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3; // @[Parameters.scala:684:{29,54}] wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire source_c_bits_legal = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17] assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17] assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10] assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17] assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17] assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 3'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 \| _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 \| _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 \| _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 \| _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 \| _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 \| _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 \| _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 \| _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 \| _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 \| _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 \| _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 \| _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10] assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10] wire [12:0] _decode_T = 13'h3F << nodeIn_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_1 = _decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] decode = _decode_T_2[5:3]; // @[package.scala:243:46] wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T \| _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = source_c_valid \| source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28]
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundRawFNToRecFN_e8_s24_121( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_121 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := 0.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt }	module LoopBranchPredictorColumn( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [36:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [36:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [36:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [36:0] f4_idx_REG; // @[loop.scala:92:35] reg [36:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (\|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (\|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (\|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (\|_GEN_0[_entry_T_1]) & ~tag_match & (\|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 \| _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 \| _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 \| _T_24 \| _T_27 \| _GEN_5 \| ~(_T_39 \| ~(_T_44 \| _GEN_4 \| ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 \| ~(_T_44 \| ~(_T_47 \| ~(_T_51 \| ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 \| _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 \| _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 \| _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| ~(_GEN_7 \| ~(_T_44 \| _T_47 \| ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 \| ~(_T_27 \| ~(_GEN_5 \| _T_39 \| ~(_T_44 \| ~(_GEN_4 \| _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegMapFIFO.scala: package sifive.blocks.util import chisel3._ import chisel3.util._ import freechips.rocketchip.regmapper._ // MSB indicates full status object NonBlockingEnqueue { def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val enqWidth = enq.bits.getWidth val quash = Wire(Bool()) require(enqWidth > 0) require(regWidth > enqWidth) Seq( RegField(enqWidth, RegReadFn(0.U), RegWriteFn((valid, data) => { enq.valid := valid && !quash enq.bits := data true.B }), RegFieldDesc("data", "Transmit data", access=RegFieldAccessType.W)), RegField(regWidth - enqWidth - 1), RegField(1, !enq.ready, RegWriteFn((valid, data) => { quash := valid && data(0) true.B }), RegFieldDesc("full", "Transmit FIFO full", access=RegFieldAccessType.R, volatile=true))) } } // MSB indicates empty status object NonBlockingDequeue { def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val deqWidth = deq.bits.getWidth require(deqWidth > 0) require(regWidth > deqWidth) Seq( RegField.r(deqWidth, RegReadFn(ready => { deq.ready := ready (true.B, deq.bits) }), RegFieldDesc("data", "Receive data", volatile=true)), RegField(regWidth - deqWidth - 1), RegField.r(1, !deq.valid, RegFieldDesc("empty", "Receive FIFO empty", volatile=true))) } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :=* _) .getOrElse(TLNameNode("no_buffer")) } } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * / case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) \|\| (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /* UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit / class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get \|\| !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy \|\| txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get \|\| errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) \|\| (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] wire _txm_io_tx_busy; // @[UART.scala:129:19] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25] wire [11:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25] wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25] wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32] wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25] wire [11:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire ioNodeOut_txd; // @[MixedNode.scala:542:17] wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25] wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] wire [11:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] wire auto_io_out_txd_0; // @[UART.scala:127:25] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [11:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [11:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25] wire _intnodeOut_0_T_2; // @[UART.scala:191:41] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] reg [15:0] div; // @[UART.scala:135:20] wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24] reg txen; // @[UART.scala:141:21] wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] wire _tx_busy_T = \|_txq_io_count; // @[UART.scala:130:19, :175:49] wire _tx_busy_T_1 = _txm_io_tx_busy \| _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}] wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24] wire _ip_rxwm_T; // @[UART.scala:190:28] wire _ip_txwm_T; // @[UART.scala:189:28] wire ip_rxwm; // @[UART.scala:187:16] wire ip_txwm; // @[UART.scala:187:16] assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28] assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28] wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29] wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53] assign _intnodeOut_0_T_2 = _intnodeOut_0_T \| _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}] assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41] wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26] wire quash; // @[RegMapFIFO.scala:11:21] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33] wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24] wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24] assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26] wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24] wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:141:21] rxen <= 1'h0; // @[UART.scala:142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:151:22] ie_rxwm <= 1'h0; // @[UART.scala:186:19] ie_txwm <= 1'h0; // @[UART.scala:186:19] end else begin // @[UART.scala:127:25] if (out_f_woready_15) // @[RegisterRouter.scala:87:24] div <= _out_T_157; // @[RegisterRouter.scala:87:24] if (out_f_woready_6) // @[RegisterRouter.scala:87:24] txen <= _out_T_62; // @[RegisterRouter.scala:87:24] if (out_f_woready_9) // @[RegisterRouter.scala:87:24] rxen <= _out_T_95; // @[RegisterRouter.scala:87:24] if (out_f_woready_8) // @[RegisterRouter.scala:87:24] txwm <= _out_T_84; // @[RegisterRouter.scala:87:24] if (out_f_woready_10) // @[RegisterRouter.scala:87:24] rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24] if (out_f_woready_7) // @[RegisterRouter.scala:87:24] nstop <= _out_T_73; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24] if (out_f_woready_11) // @[RegisterRouter.scala:87:24] ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x1_20 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0) ); // @[Crossing.scala:29:31] TLMonitor_68 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] UARTTx txm ( // @[UART.scala:129:19] .clock (clock), .reset (reset), .io_en (txen), // @[UART.scala:141:21] .io_in_ready (_txm_io_in_ready), .io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19] .io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19] .io_out (ioNodeOut_txd), .io_div (div), // @[UART.scala:135:20] .io_nstop (nstop), // @[UART.scala:151:22] .io_tx_busy (_txm_io_tx_busy) ); // @[UART.scala:129:19] Queue8_UInt8 txq ( // @[UART.scala:130:19] .clock (clock), .reset (reset), .io_enq_ready (_txq_io_enq_ready), .io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30] .io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24] .io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19] .io_deq_valid (_txq_io_deq_valid), .io_deq_bits (_txq_io_deq_bits), .io_count (_txq_io_count) ); // @[UART.scala:130:19] UARTRx rxm ( // @[UART.scala:132:19] .clock (clock), .reset (reset), .io_en (rxen), // @[UART.scala:142:21] .io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17] .io_out_valid (_rxm_io_out_valid), .io_out_bits (_rxm_io_out_bits), .io_div (div) // @[UART.scala:135:20] ); // @[UART.scala:132:19] Queue8_UInt8_1 rxq ( // @[UART.scala:133:19] .clock (clock), .reset (reset), .io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19] .io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxq_io_deq_valid), .io_deq_bits (_rxq_io_deq_bits), .io_count (_rxq_io_count) ); // @[UART.scala:133:19] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputBuffer_3( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [4:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload, // @[InputUnit.scala:51:14] output io_deq_10_bits_head, // @[InputUnit.scala:51:14] output io_deq_10_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_10_bits_payload, // @[InputUnit.scala:51:14] output io_deq_11_bits_head, // @[InputUnit.scala:51:14] output io_deq_11_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_11_bits_payload, // @[InputUnit.scala:51:14] output io_deq_12_bits_head, // @[InputUnit.scala:51:14] output io_deq_12_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_12_bits_payload, // @[InputUnit.scala:51:14] output io_deq_13_bits_head, // @[InputUnit.scala:51:14] output io_deq_13_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_13_bits_payload, // @[InputUnit.scala:51:14] output io_deq_14_bits_head, // @[InputUnit.scala:51:14] output io_deq_14_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_14_bits_payload, // @[InputUnit.scala:51:14] output io_deq_15_bits_head, // @[InputUnit.scala:51:14] output io_deq_15_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_15_bits_payload, // @[InputUnit.scala:51:14] output io_deq_16_bits_head, // @[InputUnit.scala:51:14] output io_deq_16_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_16_bits_payload, // @[InputUnit.scala:51:14] output io_deq_17_bits_head, // @[InputUnit.scala:51:14] output io_deq_17_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_17_bits_payload, // @[InputUnit.scala:51:14] input io_deq_18_ready, // @[InputUnit.scala:51:14] output io_deq_18_valid, // @[InputUnit.scala:51:14] output io_deq_18_bits_head, // @[InputUnit.scala:51:14] output io_deq_18_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_18_bits_payload, // @[InputUnit.scala:51:14] input io_deq_19_ready, // @[InputUnit.scala:51:14] output io_deq_19_valid, // @[InputUnit.scala:51:14] output io_deq_19_bits_head, // @[InputUnit.scala:51:14] output io_deq_19_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_19_bits_payload, // @[InputUnit.scala:51:14] input io_deq_20_ready, // @[InputUnit.scala:51:14] output io_deq_20_valid, // @[InputUnit.scala:51:14] output io_deq_20_bits_head, // @[InputUnit.scala:51:14] output io_deq_20_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_20_bits_payload, // @[InputUnit.scala:51:14] input io_deq_21_ready, // @[InputUnit.scala:51:14] output io_deq_21_valid, // @[InputUnit.scala:51:14] output io_deq_21_bits_head, // @[InputUnit.scala:51:14] output io_deq_21_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_21_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_21_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_20_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_19_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_18_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_17_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_16_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_15_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_14_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_13_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_12_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_11_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_10_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R10_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R11_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R12_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R13_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R14_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R15_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R16_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R17_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R18_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R19_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R20_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R21_data; // @[InputUnit.scala:85:18] reg [3:0] heads_0; // @[InputUnit.scala:86:24] reg [3:0] heads_1; // @[InputUnit.scala:86:24] reg [3:0] heads_2; // @[InputUnit.scala:86:24] reg [3:0] heads_3; // @[InputUnit.scala:86:24] reg [3:0] heads_4; // @[InputUnit.scala:86:24] reg [3:0] heads_5; // @[InputUnit.scala:86:24] reg [3:0] heads_6; // @[InputUnit.scala:86:24] reg [3:0] heads_7; // @[InputUnit.scala:86:24] reg [3:0] heads_8; // @[InputUnit.scala:86:24] reg [3:0] heads_9; // @[InputUnit.scala:86:24] reg [3:0] heads_10; // @[InputUnit.scala:86:24] reg [3:0] heads_11; // @[InputUnit.scala:86:24] reg [3:0] heads_12; // @[InputUnit.scala:86:24] reg [3:0] heads_13; // @[InputUnit.scala:86:24] reg [3:0] heads_14; // @[InputUnit.scala:86:24] reg [3:0] heads_15; // @[InputUnit.scala:86:24] reg [3:0] heads_16; // @[InputUnit.scala:86:24] reg [3:0] heads_17; // @[InputUnit.scala:86:24] reg [3:0] heads_18; // @[InputUnit.scala:86:24] reg [3:0] heads_19; // @[InputUnit.scala:86:24] reg [3:0] heads_20; // @[InputUnit.scala:86:24] reg [3:0] heads_21; // @[InputUnit.scala:86:24] reg [3:0] tails_0; // @[InputUnit.scala:87:24] reg [3:0] tails_1; // @[InputUnit.scala:87:24] reg [3:0] tails_2; // @[InputUnit.scala:87:24] reg [3:0] tails_3; // @[InputUnit.scala:87:24] reg [3:0] tails_4; // @[InputUnit.scala:87:24] reg [3:0] tails_5; // @[InputUnit.scala:87:24] reg [3:0] tails_6; // @[InputUnit.scala:87:24] reg [3:0] tails_7; // @[InputUnit.scala:87:24] reg [3:0] tails_8; // @[InputUnit.scala:87:24] reg [3:0] tails_9; // @[InputUnit.scala:87:24] reg [3:0] tails_10; // @[InputUnit.scala:87:24] reg [3:0] tails_11; // @[InputUnit.scala:87:24] reg [3:0] tails_12; // @[InputUnit.scala:87:24] reg [3:0] tails_13; // @[InputUnit.scala:87:24] reg [3:0] tails_14; // @[InputUnit.scala:87:24] reg [3:0] tails_15; // @[InputUnit.scala:87:24] reg [3:0] tails_16; // @[InputUnit.scala:87:24] reg [3:0] tails_17; // @[InputUnit.scala:87:24] reg [3:0] tails_18; // @[InputUnit.scala:87:24] reg [3:0] tails_19; // @[InputUnit.scala:87:24] reg [3:0] tails_20; // @[InputUnit.scala:87:24] reg [3:0] tails_21; // @[InputUnit.scala:87:24] wire _tails_T_66 = io_enq_0_bits_virt_channel_id == 5'h0; // @[Mux.scala:32:36] wire _tails_T_67 = io_enq_0_bits_virt_channel_id == 5'h1; // @[Mux.scala:32:36] wire _tails_T_68 = io_enq_0_bits_virt_channel_id == 5'h2; // @[Mux.scala:32:36] wire _tails_T_69 = io_enq_0_bits_virt_channel_id == 5'h3; // @[Mux.scala:32:36] wire _tails_T_70 = io_enq_0_bits_virt_channel_id == 5'h4; // @[Mux.scala:32:36] wire _tails_T_71 = io_enq_0_bits_virt_channel_id == 5'h5; // @[Mux.scala:32:36] wire _tails_T_72 = io_enq_0_bits_virt_channel_id == 5'h6; // @[Mux.scala:32:36] wire _tails_T_73 = io_enq_0_bits_virt_channel_id == 5'h7; // @[Mux.scala:32:36] wire _tails_T_74 = io_enq_0_bits_virt_channel_id == 5'h8; // @[Mux.scala:32:36] wire _tails_T_75 = io_enq_0_bits_virt_channel_id == 5'h9; // @[Mux.scala:32:36] wire _tails_T_76 = io_enq_0_bits_virt_channel_id == 5'hA; // @[Mux.scala:32:36] wire _tails_T_77 = io_enq_0_bits_virt_channel_id == 5'hB; // @[Mux.scala:32:36] wire _tails_T_78 = io_enq_0_bits_virt_channel_id == 5'hC; // @[Mux.scala:32:36] wire _tails_T_79 = io_enq_0_bits_virt_channel_id == 5'hD; // @[Mux.scala:32:36] wire _tails_T_80 = io_enq_0_bits_virt_channel_id == 5'hE; // @[Mux.scala:32:36] wire _tails_T_81 = io_enq_0_bits_virt_channel_id == 5'hF; // @[Mux.scala:32:36] wire _tails_T_82 = io_enq_0_bits_virt_channel_id == 5'h10; // @[Mux.scala:32:36] wire _tails_T_83 = io_enq_0_bits_virt_channel_id == 5'h11; // @[Mux.scala:32:36] wire _tails_T_84 = io_enq_0_bits_virt_channel_id == 5'h12; // @[Mux.scala:32:36] wire _tails_T_85 = io_enq_0_bits_virt_channel_id == 5'h13; // @[Mux.scala:32:36] wire _tails_T_86 = io_enq_0_bits_virt_channel_id == 5'h14; // @[Mux.scala:32:36] wire _tails_T_87 = io_enq_0_bits_virt_channel_id == 5'h15; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_66 & _qs_0_io_enq_ready \| _tails_T_67 & _qs_1_io_enq_ready \| _tails_T_68 & _qs_2_io_enq_ready \| _tails_T_69 & _qs_3_io_enq_ready \| _tails_T_70 & _qs_4_io_enq_ready \| _tails_T_71 & _qs_5_io_enq_ready \| _tails_T_72 & _qs_6_io_enq_ready \| _tails_T_73 & _qs_7_io_enq_ready \| _tails_T_74 & _qs_8_io_enq_ready \| _tails_T_75 & _qs_9_io_enq_ready \| _tails_T_76 & _qs_10_io_enq_ready \| _tails_T_77 & _qs_11_io_enq_ready \| _tails_T_78 & _qs_12_io_enq_ready \| _tails_T_79 & _qs_13_io_enq_ready \| _tails_T_80 & _qs_14_io_enq_ready \| _tails_T_81 & _qs_15_io_enq_ready \| _tails_T_82 & _qs_16_io_enq_ready \| _tails_T_83 & _qs_17_io_enq_ready \| _tails_T_84 & _qs_18_io_enq_ready \| _tails_T_85 & _qs_19_io_enq_ready \| _tails_T_86 & _qs_20_io_enq_ready \| _tails_T_87 & _qs_21_io_enq_ready) & (_tails_T_66 & heads_0 == tails_0 \| _tails_T_67 & heads_1 == tails_1 \| _tails_T_68 & heads_2 == tails_2 \| _tails_T_69 & heads_3 == tails_3 \| _tails_T_70 & heads_4 == tails_4 \| _tails_T_71 & heads_5 == tails_5 \| _tails_T_72 & heads_6 == tails_6 \| _tails_T_73 & heads_7 == tails_7 \| _tails_T_74 & heads_8 == tails_8 \| _tails_T_75 & heads_9 == tails_9 \| _tails_T_76 & heads_10 == tails_10 \| _tails_T_77 & heads_11 == tails_11 \| _tails_T_78 & heads_12 == tails_12 \| _tails_T_79 & heads_13 == tails_13 \| _tails_T_80 & heads_14 == tails_14 \| _tails_T_81 & heads_15 == tails_15 \| _tails_T_82 & heads_16 == tails_16 \| _tails_T_83 & heads_17 == tails_17 \| _tails_T_84 & heads_18 == tails_18 \| _tails_T_85 & heads_19 == tails_19 \| _tails_T_86 & heads_20 == tails_20 \| _tails_T_87 & heads_21 == tails_21); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [31:0][3:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_21}, {tails_20}, {tails_19}, {tails_18}, {tails_17}, {tails_16}, {tails_15}, {tails_14}, {tails_13}, {tails_12}, {tails_11}, {tails_10}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 5'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 5'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 5'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 5'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 5'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 5'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 5'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 5'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 5'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 5'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_bits_virt_channel_id == 5'hA; // @[InputUnit.scala:103:45] wire _GEN_11 = io_enq_0_bits_virt_channel_id == 5'hB; // @[InputUnit.scala:103:45] wire _GEN_12 = io_enq_0_bits_virt_channel_id == 5'hC; // @[InputUnit.scala:103:45] wire _GEN_13 = io_enq_0_bits_virt_channel_id == 5'hD; // @[InputUnit.scala:103:45] wire _GEN_14 = io_enq_0_bits_virt_channel_id == 5'hE; // @[InputUnit.scala:103:45] wire _GEN_15 = io_enq_0_bits_virt_channel_id == 5'hF; // @[InputUnit.scala:103:45] wire _GEN_16 = io_enq_0_bits_virt_channel_id == 5'h10; // @[InputUnit.scala:103:45] wire _GEN_17 = io_enq_0_bits_virt_channel_id == 5'h11; // @[InputUnit.scala:103:45] wire _GEN_18 = io_enq_0_bits_virt_channel_id == 5'h12; // @[InputUnit.scala:103:45] wire _GEN_19 = io_enq_0_bits_virt_channel_id == 5'h13; // @[InputUnit.scala:103:45] wire _GEN_20 = io_enq_0_bits_virt_channel_id == 5'h14; // @[InputUnit.scala:103:45] wire _GEN_21 = io_enq_0_bits_virt_channel_id == 5'h15; // @[InputUnit.scala:103:45] wire _GEN_22 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_10 = heads_10 != tails_10 & _qs_10_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_11 = heads_11 != tails_11 & _qs_11_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_12 = heads_12 != tails_12 & _qs_12_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_13 = heads_13 != tails_13 & _qs_13_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_14 = heads_14 != tails_14 & _qs_14_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_15 = heads_15 != tails_15 & _qs_15_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_16 = heads_16 != tails_16 & _qs_16_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_17 = heads_17 != tails_17 & _qs_17_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_18 = heads_18 != tails_18 & _qs_18_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_19 = heads_19 != tails_19 & _qs_19_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_20 = heads_20 != tails_20 & _qs_20_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_21 = heads_21 != tails_21 & _qs_21_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [21:0] to_q_oh_enc = can_to_q_0 ? 22'h1 : can_to_q_1 ? 22'h2 : can_to_q_2 ? 22'h4 : can_to_q_3 ? 22'h8 : can_to_q_4 ? 22'h10 : can_to_q_5 ? 22'h20 : can_to_q_6 ? 22'h40 : can_to_q_7 ? 22'h80 : can_to_q_8 ? 22'h100 : can_to_q_9 ? 22'h200 : can_to_q_10 ? 22'h400 : can_to_q_11 ? 22'h800 : can_to_q_12 ? 22'h1000 : can_to_q_13 ? 22'h2000 : can_to_q_14 ? 22'h4000 : can_to_q_15 ? 22'h8000 : can_to_q_16 ? 22'h10000 : can_to_q_17 ? 22'h20000 : can_to_q_18 ? 22'h40000 : can_to_q_19 ? 22'h80000 : can_to_q_20 ? 22'h100000 : {can_to_q_21, 21'h0}; // @[Mux.scala:50:70] wire _GEN_23 = can_to_q_0 \| can_to_q_1 \| can_to_q_2 \| can_to_q_3 \| can_to_q_4 \| can_to_q_5 \| can_to_q_6 \| can_to_q_7 \| can_to_q_8 \| can_to_q_9 \| can_to_q_10 \| can_to_q_11 \| can_to_q_12 \| can_to_q_13 \| can_to_q_14 \| can_to_q_15 \| can_to_q_16 \| can_to_q_17 \| can_to_q_18 \| can_to_q_19 \| can_to_q_20 \| can_to_q_21; // @[package.scala:81:59] wire [3:0] head = (to_q_oh_enc[0] ? heads_0 : 4'h0) \| (to_q_oh_enc[1] ? heads_1 : 4'h0) \| (to_q_oh_enc[2] ? heads_2 : 4'h0) \| (to_q_oh_enc[3] ? heads_3 : 4'h0) \| (to_q_oh_enc[4] ? heads_4 : 4'h0) \| (to_q_oh_enc[5] ? heads_5 : 4'h0) \| (to_q_oh_enc[6] ? heads_6 : 4'h0) \| (to_q_oh_enc[7] ? heads_7 : 4'h0) \| (to_q_oh_enc[8] ? heads_8 : 4'h0) \| (to_q_oh_enc[9] ? heads_9 : 4'h0) \| (to_q_oh_enc[10] ? heads_10 : 4'h0) \| (to_q_oh_enc[11] ? heads_11 : 4'h0) \| (to_q_oh_enc[12] ? heads_12 : 4'h0) \| (to_q_oh_enc[13] ? heads_13 : 4'h0) \| (to_q_oh_enc[14] ? heads_14 : 4'h0) \| (to_q_oh_enc[15] ? heads_15 : 4'h0) \| (to_q_oh_enc[16] ? heads_16 : 4'h0) \| (to_q_oh_enc[17] ? heads_17 : 4'h0) \| (to_q_oh_enc[18] ? heads_18 : 4'h0) \| (to_q_oh_enc[19] ? heads_19 : 4'h0) \| (to_q_oh_enc[20] ? heads_20 : 4'h0) \| (to_q_oh_enc[21] ? heads_21 : 4'h0); // @[OneHot.scala:83:30] wire _GEN_24 = _GEN_23 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_25 = _GEN_23 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_26 = _GEN_23 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_27 = _GEN_23 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_28 = _GEN_23 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_29 = _GEN_23 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_30 = _GEN_23 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_31 = _GEN_23 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_32 = _GEN_23 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_33 = _GEN_23 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire _GEN_34 = _GEN_23 & to_q_oh_enc[10]; // @[OneHot.scala:83:30] wire _GEN_35 = _GEN_23 & to_q_oh_enc[11]; // @[OneHot.scala:83:30] wire _GEN_36 = _GEN_23 & to_q_oh_enc[12]; // @[OneHot.scala:83:30] wire _GEN_37 = _GEN_23 & to_q_oh_enc[13]; // @[OneHot.scala:83:30] wire _GEN_38 = _GEN_23 & to_q_oh_enc[14]; // @[OneHot.scala:83:30] wire _GEN_39 = _GEN_23 & to_q_oh_enc[15]; // @[OneHot.scala:83:30] wire _GEN_40 = _GEN_23 & to_q_oh_enc[16]; // @[OneHot.scala:83:30] wire _GEN_41 = _GEN_23 & to_q_oh_enc[17]; // @[OneHot.scala:83:30] wire _GEN_42 = _GEN_23 & to_q_oh_enc[18]; // @[OneHot.scala:83:30] wire _GEN_43 = _GEN_23 & to_q_oh_enc[19]; // @[OneHot.scala:83:30] wire _GEN_44 = _GEN_23 & to_q_oh_enc[20]; // @[OneHot.scala:83:30] wire _GEN_45 = _GEN_23 & to_q_oh_enc[21]; // @[OneHot.scala:83:30] wire [3:0] _tails_T_133 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {2{_tails_T_84}}} \| {3{_tails_T_85}}} \| (_tails_T_86 ? 4'hB : 4'h0) \| {4{_tails_T_87}}) ? {_tails_T_86, _tails_T_85, 2'h0} \| (_tails_T_87 ? 4'hC : 4'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 4'h1; // @[Mux.scala:30:73, :32:36] wire [14:0] _to_q_T_2 = {10'h0, to_q_oh_enc[21:17]} \| to_q_oh_enc[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _to_q_T_4 = _to_q_T_2[14:8] \| _to_q_T_2[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _to_q_T_6 = _to_q_T_4[6:4] \| _to_q_T_4[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_8 = _to_q_T_6[2] \| _to_q_T_6[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] to_q = {\|(to_q_oh_enc[21:16]), \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [3:0] _heads_T_89 = head == ({1'h0, {1'h0, {2{to_q_oh_enc[18]}}} \| {3{to_q_oh_enc[19]}}} \| (to_q_oh_enc[20] ? 4'hB : 4'h0) \| {4{to_q_oh_enc[21]}}) ? {to_q_oh_enc[20:19], 2'h0} \| (to_q_oh_enc[21] ? 4'hC : 4'h0) : head + 4'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 4'h0; // @[InputUnit.scala:86:24] heads_1 <= 4'h0; // @[InputUnit.scala:86:24] heads_2 <= 4'h0; // @[InputUnit.scala:86:24] heads_3 <= 4'h0; // @[InputUnit.scala:86:24] heads_4 <= 4'h0; // @[InputUnit.scala:86:24] heads_5 <= 4'h0; // @[InputUnit.scala:86:24] heads_6 <= 4'h0; // @[InputUnit.scala:86:24] heads_7 <= 4'h0; // @[InputUnit.scala:86:24] heads_8 <= 4'h0; // @[InputUnit.scala:86:24] heads_9 <= 4'h0; // @[InputUnit.scala:86:24] heads_10 <= 4'h0; // @[InputUnit.scala:86:24] heads_11 <= 4'h0; // @[InputUnit.scala:86:24] heads_12 <= 4'h0; // @[InputUnit.scala:86:24] heads_13 <= 4'h0; // @[InputUnit.scala:86:24] heads_14 <= 4'h0; // @[InputUnit.scala:86:24] heads_15 <= 4'h0; // @[InputUnit.scala:86:24] heads_16 <= 4'h0; // @[InputUnit.scala:86:24] heads_17 <= 4'h0; // @[InputUnit.scala:86:24] heads_18 <= 4'h0; // @[InputUnit.scala:86:24] heads_19 <= 4'h4; // @[InputUnit.scala:86:24] heads_20 <= 4'h8; // @[InputUnit.scala:86:24] heads_21 <= 4'hC; // @[InputUnit.scala:86:24] tails_0 <= 4'h0; // @[InputUnit.scala:87:24] tails_1 <= 4'h0; // @[InputUnit.scala:87:24] tails_2 <= 4'h0; // @[InputUnit.scala:87:24] tails_3 <= 4'h0; // @[InputUnit.scala:87:24] tails_4 <= 4'h0; // @[InputUnit.scala:87:24] tails_5 <= 4'h0; // @[InputUnit.scala:87:24] tails_6 <= 4'h0; // @[InputUnit.scala:87:24] tails_7 <= 4'h0; // @[InputUnit.scala:87:24] tails_8 <= 4'h0; // @[InputUnit.scala:87:24] tails_9 <= 4'h0; // @[InputUnit.scala:87:24] tails_10 <= 4'h0; // @[InputUnit.scala:87:24] tails_11 <= 4'h0; // @[InputUnit.scala:87:24] tails_12 <= 4'h0; // @[InputUnit.scala:87:24] tails_13 <= 4'h0; // @[InputUnit.scala:87:24] tails_14 <= 4'h0; // @[InputUnit.scala:87:24] tails_15 <= 4'h0; // @[InputUnit.scala:87:24] tails_16 <= 4'h0; // @[InputUnit.scala:87:24] tails_17 <= 4'h0; // @[InputUnit.scala:87:24] tails_18 <= 4'h0; // @[InputUnit.scala:87:24] tails_19 <= 4'h4; // @[InputUnit.scala:87:24] tails_20 <= 4'h8; // @[InputUnit.scala:87:24] tails_21 <= 4'hC; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_23 & {to_q_oh_enc[21:16], \|(_to_q_T_2[14:7]), \|(_to_q_T_4[6:3]), \|(_to_q_T_6[2:1]), _to_q_T_8} == 10'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hA) // @[OneHot.scala:32:10] heads_10 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hB) // @[OneHot.scala:32:10] heads_11 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hC) // @[OneHot.scala:32:10] heads_12 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hD) // @[OneHot.scala:32:10] heads_13 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hE) // @[OneHot.scala:32:10] heads_14 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hF) // @[OneHot.scala:32:10] heads_15 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h10) // @[OneHot.scala:32:10] heads_16 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h11) // @[OneHot.scala:32:10] heads_17 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h12) // @[OneHot.scala:32:10] heads_18 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h13) // @[OneHot.scala:32:10] heads_19 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h14) // @[OneHot.scala:32:10] heads_20 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h15) // @[OneHot.scala:32:10] heads_21 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_10) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_10 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_11) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_11 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_12) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_12 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_13) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_13 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_14) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_14 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_15) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_15 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_16) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_16 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_17) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_17 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_18) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_18 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_19) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_19 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_20) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_20 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_21) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_21 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_91( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_92( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_225( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Periphery.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.experimental.{noPrefix, IntParam} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} import freechips.rocketchip.jtag.JTAGIO import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget} import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg} import freechips.rocketchip.util.BooleanToAugmentedBoolean /** Protocols used for communicating with external debugging tools */ sealed trait DebugExportProtocol case object DMI extends DebugExportProtocol case object JTAG extends DebugExportProtocol case object CJTAG extends DebugExportProtocol case object APB extends DebugExportProtocol /** Options for possible debug interfaces */ case class DebugAttachParams( protocols: Set[DebugExportProtocol] = Set(DMI), externalDisable: Boolean = false, masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = CBUS ) { def dmi = protocols.contains(DMI) def jtag = protocols.contains(JTAG) def cjtag = protocols.contains(CJTAG) def apb = protocols.contains(APB) } case object ExportDebug extends Field(DebugAttachParams()) class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) { val clock = Clock() val reset = Reset() } class DebugIO(implicit val p: Parameters) extends Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO())) val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO) val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32)))) //------------------------------ val ndreset = Output(Bool()) val dmactive = Output(Bool()) val dmactiveAck = Input(Bool()) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool())) } class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO { } class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle { val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool()))) val hartIsInReset = Input(Vec(nComponents, Bool())) } /** Either adds a JTAG DTM to system, and exports a JTAG interface, * or exports the Debug Module Interface (DMI), or exports and hooks up APB, * based on a global parameter. */ trait HasPeripheryDebug { this: BaseSubsystem => private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere) lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB")))))) val debugTLDomainOpt = p(DebugModuleKey).map { _ => val domain = ClockSinkNode(Seq(ClockSinkParameters())) domain := tlbus.fixedClockNode domain } lazy val debugOpt = p(DebugModuleKey).map { params => val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes)) tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ } tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) => slave := master } tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") { _ := TLWidthWidget(1) := sb2tl.node } } tlDM } val debugNode = debugOpt.map(_.intnode) val psd = InModuleBody { val psd = IO(new PSDIO) psd } val resetctrl = InModuleBody { debugOpt.map { debug => debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size)) debug.module.io.hartIsInReset := resetctrl.hartIsInReset resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }} resetctrl } } // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603 val debug = InModuleBody { noPrefix(debugOpt.map { debugmod => val debug = IO(new DebugIO) require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined), "You cannot have both DMI and JTAG interface in HasPeripheryDebug") require(!(debug.clockeddmi.isDefined && debug.apb.isDefined), "You cannot have both DMI and APB interface in HasPeripheryDebug") require(!(debug.systemjtag.isDefined && debug.apb.isDefined), "You cannot have both APB and JTAG interface in HasPeripheryDebug") debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg } (debug.apb zip apbDebugNodeOpt zip debugmod.module.io.apb_clock zip debugmod.module.io.apb_reset).foreach { case (((io, apb), c ), r) => apb.out(0)._1 <> io c:= io.clock r:= io.reset } debugmod.module.io.debug_reset := debug.reset debugmod.module.io.debug_clock := debug.clock debug.ndreset := debugmod.module.io.ctrl.ndreset debug.dmactive := debugmod.module.io.ctrl.dmactive debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}} // TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down" debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B } debug })} val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) } def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = { val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled dtm.io.jtag_clock := sj.jtag.TCK dtm.io.jtag_reset := sj.reset dtm.io.jtag_mfr_id := sj.mfr_id dtm.io.jtag_part_number := sj.part_number dtm.io.jtag_version := sj.version dtm.rf_reset := sj.reset debugOpt.map { outerdebug => outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK outerdebug.module.io.dmi.get.dmiReset := sj.reset } dtm } } /** BlackBox to export DMI interface */ class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clk = Input(Clock()) val reset = Input(Bool()) val debug = new DMIIO val exit = Output(UInt(32.W)) }) def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = { io.clk := tbclk io.reset := tbreset dutio.dmi <> io.debug dutio.dmiClock := tbclk dutio.dmiReset := tbreset tbsuccess := io.exit === 1.U assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimDTM.v") addResource("/csrc/SimDTM.cc") } /** BlackBox to export JTAG interface */ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val jtag = new JTAGIO(hasTRSTn = true) val enable = Input(Bool()) val init_done = Input(Bool()) val exit = Output(UInt(32.W)) }) def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = { dutio.TCK := io.jtag.TCK dutio.TMS := io.jtag.TMS dutio.TDI := io.jtag.TDI io.jtag.TDO := dutio.TDO io.clock := tbclock io.reset := tbreset io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.") io.init_done := init_done // Success is determined by the gdbserver // which is controlling this simulation. tbsuccess := io.exit === 1.U assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimJTAG.v") addResource("/csrc/SimJTAG.cc") addResource("/csrc/remote_bitbang.h") addResource("/csrc/remote_bitbang.cc") } object Debug { def connectDebug( debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO], psdio: PSDIO, c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode())) (implicit p: Parameters): Unit = { connectDebugClockAndReset(debugOpt, c) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }} debugOpt.map { debug => debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } debug.systemjtag.foreach { sj => val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out) sj.reset := r.asAsyncReset sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) sj.version := p(JtagDTMKey).idcodeVersion.U(4.W) } debug.apb.foreach { apb => require(false, "No support for connectDebug for an APB debug connection.") } psdio.psd.foreach { _ <> psd } debug.disableDebug.foreach { x => x := false.B } } } def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { debugOpt.foreach { debug => val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) | debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) | debug.apb.map(_.reset.asBool).getOrElse(false.B) connectDebugClockHelper(debug, dmi_reset, c, sync) } } def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { val debug_reset = Wire(Bool()) withClockAndReset(c, dmi_reset) { val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset debug_reset := debug_reset_syncd } // Need to clock DM during debug_reset because of synchronous reset, so keep // the clock alive for one cycle after debug_reset asserts to action this behavior. // The unit should also be clocked when dmactive is high. withClockAndReset(c, debug_reset.asAsyncReset) { val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive val clock_en = RegNext(next=dmactiveAck, init=true.B) val gated_clock = if (!p(DebugModuleKey).get.clockGate) c else ClockGate(c, clock_en, "debug_clock_gate") debug.clock := gated_clock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset) debug.dmactiveAck := dmactiveAck } } def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = { psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } ) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }} debugOpt.map { debug => debug.clock := true.B.asClock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset) debug.systemjtag.foreach { sj => sj.jtag.TCK := true.B.asClock sj.jtag.TMS := true.B sj.jtag.TDI := true.B sj.jtag.TRSTn.foreach { r => r := true.B } sj.reset := true.B.asAsyncReset sj.mfr_id := 0.U sj.part_number := 0.U sj.version := 0.U } debug.clockeddmi.foreach { d => d.dmi.req.valid := false.B d.dmi.req.bits.addr := 0.U d.dmi.req.bits.data := 0.U d.dmi.req.bits.op := 0.U d.dmi.resp.ready := true.B d.dmiClock := false.B.asClock d.dmiReset := true.B.asAsyncReset } debug.apb.foreach { apb => apb.clock := false.B.asClock apb.reset := true.B.asAsyncReset apb.pready := false.B apb.pslverr := false.B apb.prdata := 0.U apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser)) apb.psel := false.B apb.penable := false.B } debug.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } debug.disableDebug.foreach { x => x := false.B } debug.dmactiveAck := false.B debug.ndreset }.getOrElse(false.B) } } File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating || enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * */ case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) || (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit */ class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get || !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get || errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /** Parameterization of the memory-side bus created for each memory channel */ case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */ class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :*=* TLFIFOFixer(TLFIFOFixer.all) :*=* _.node) .getOrElse(xbar.node :*=* TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File CanHaveClockTap.scala: package chipyard.clocking import chisel3._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ case object ClockTapKey extends Field[Boolean](true) trait CanHaveClockTap { this: BaseSubsystem => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO") val clockTapNode = Option.when(p(ClockTapKey)) { val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) clockTap := ClockGroup() := allClockGroupsNode clockTap } val clockTapIO = clockTapNode.map { node => InModuleBody { val clock_tap = IO(Output(Clock())) clock_tap := node.in.head._1.clock clock_tap }} } File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node) (out_xbar.node :*= fixer_node :*= TLBuffer(pa.buffer) :*= (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) :*= in_xbar.node) } .getOrElse { TLXbar() :*= fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File BankedCoherenceParams.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.BuiltInDevices import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.interrupts.IntOutwardNode import freechips.rocketchip.tilelink.{ TLBroadcast, HasTLBusParams, BroadcastFilter, TLBusWrapper, TLBusWrapperInstantiationLike, TLJbar, TLEdge, TLOutwardNode, TLTempNode, TLInwardNode, BankBinder, TLBroadcastParams, TLBroadcastControlParams, TLBuffer, TLFragmenter, TLNameNode } import freechips.rocketchip.util.Location import CoherenceManagerWrapper._ /** Global cache coherence granularity, which applies to all caches, for now. */ case object CacheBlockBytes extends Field[Int](64) /** LLC Broadcast Hub configuration */ case object BroadcastKey extends Field(BroadcastParams()) case class BroadcastParams( nTrackers: Int = 4, bufferless: Boolean = false, controlAddress: Option[BigInt] = None, filterFactory: TLBroadcast.ProbeFilterFactory = BroadcastFilter.factory) /** Coherence manager configuration */ case object SubsystemBankedCoherenceKey extends Field(BankedCoherenceParams()) case class ClusterBankedCoherenceKey(clusterId: Int) extends Field(BankedCoherenceParams(nBanks=0)) case class BankedCoherenceParams( nBanks: Int = 1, coherenceManager: CoherenceManagerInstantiationFn = broadcastManager ) { require (isPow2(nBanks) || nBanks == 0) } case class CoherenceManagerWrapperParams( blockBytes: Int, beatBytes: Int, nBanks: Int, name: String, dtsFrequency: Option[BigInt] = None) (val coherenceManager: CoherenceManagerInstantiationFn) extends HasTLBusParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = { val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context)) cmWrapper.suggestName(loc.name + "_wrapper") cmWrapper.halt.foreach { context.anyLocationMap += loc.halt(_) } context.tlBusWrapperLocationMap += (loc -> cmWrapper) cmWrapper } } class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) { val (tempIn, tempOut, halt) = params.coherenceManager(context) private val coherent_jbar = LazyModule(new TLJbar) def busView: TLEdge = coherent_jbar.node.edges.out.head val inwardNode = tempIn :*= coherent_jbar.node val builtInDevices = BuiltInDevices.none val prefixNode = None private def banked(node: TLOutwardNode): TLOutwardNode = if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) :*= node } val outwardNode = banked(tempOut) } object CoherenceManagerWrapper { type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode]) def broadcastManagerFn( name: String, location: HierarchicalLocation, controlPortsSlaveWhere: TLBusWrapperLocation ): CoherenceManagerInstantiationFn = { context => implicit val p = context.p val cbus = context.locateTLBusWrapper(controlPortsSlaveWhere) val BroadcastParams(nTrackers, bufferless, controlAddress, filterFactory) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(TLBroadcastParams( lineBytes = p(CacheBlockBytes), numTrackers = nTrackers, bufferless = bufferless, control = controlAddress.map(x => TLBroadcastControlParams(AddressSet(x, 0xfff), cbus.beatBytes)), filterFactory = filterFactory))) bh.suggestName(name) bh.controlNode.foreach { _ := cbus.coupleTo(s"${name}_ctrl") { TLBuffer(1) := TLFragmenter(cbus) := _ } } bh.intNode.foreach { context.ibus.fromSync := _ } (bh.node, bh.node, None) } val broadcastManager = broadcastManagerFn("broadcast", InSystem, CBUS) val incoherentManager: CoherenceManagerInstantiationFn = { _ => val node = TLNameNode("no_coherence_manager") (node, node, None) } } File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /** Entry point for Config-uring the presence of Tiles */ case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /** List of HierarchicalLocations which might contain a Tile */ case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /** For determining static tile id */ case object NumTiles extends Field[Int](0) /** Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. */ case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. */ case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. */ case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /** These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. */ trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /** tileHartIdNode is used to collect publishers and subscribers of hartids. */ val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. */ val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */ val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */ val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. */ val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. */ val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. */ trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. */ trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /** Narrow waist through which all tiles are intended to pass while being instantiated. */ def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /** A default set of connections that need to occur for most tile types */ def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /** Connect the port where the tile is the master to a TileLink interconnect. */ def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. */ def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus } } } /** Connect the various interrupts sent to and and raised by the tile. */ def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */ def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */ def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /** Connect power/reset/clock resources. */ def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing | _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /** Function to handle all trace crossings when tile is instantiated inside domains */ def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File BusWrapper.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding} // TODO This class should be moved to package subsystem to resolve // the dependency awkwardness of the following imports import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices} import freechips.rocketchip.prci.{ ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode, FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain, ClockGroupEphemeralNode, asyncMux, ClockCrossingType, NoCrossing } import freechips.rocketchip.subsystem.{ HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations, CanInstantiateWithinContextThatHasTileLinkLocations } import freechips.rocketchip.util.Location /** Specifies widths of various attachement points in the SoC */ trait HasTLBusParams { def beatBytes: Int def blockBytes: Int def beatBits: Int = beatBytes * 8 def blockBits: Int = blockBytes * 8 def blockBeats: Int = blockBytes / beatBytes def blockOffset: Int = log2Up(blockBytes) def dtsFrequency: Option[BigInt] def fixedClockOpt = dtsFrequency.map(f => ClockParameters(freqMHz = f.toDouble / 1000000.0)) require (isPow2(beatBytes)) require (isPow2(blockBytes)) } abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters) extends ClockDomain with HasTLBusParams with CanHaveBuiltInDevices { private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups") private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true }) val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here val clockNode = clockGroup.node val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt))) clockGroup.node := clockGroupAggregator.node fixedClockNode := clockGroup.node // first member of group is always domain's own clock clockSinkNode := fixedClockNode InModuleBody { // make sure the above connections work properly because mismatched-by-name signals will just be ignored. (clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) => require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}") } } def clockBundle = clockSinkNode.in.head._1 def beatBytes = params.beatBytes def blockBytes = params.blockBytes def dtsFrequency = params.dtsFrequency val dtsClk = fixedClockNode.fixedClockResources(s"${busName}_clock").flatten.headOption /* If you violate this requirement, you will have a rough time. * The codebase is riddled with the assumption that this is true. */ require(blockBytes >= beatBytes) def inwardNode: TLInwardNode def outwardNode: TLOutwardNode def busView: TLEdge def prefixNode: Option[BundleBridgeNode[UInt]] def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers) def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing")) def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing")) def generateSynchronousDomain(domainName: String): ClockSinkDomain = { val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName))) domain.clockNode := fixedClockNode domain } def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("") protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W))) def to[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_to_${name}", s"TLInterconnectCoupler_${busName}_to_${name}") { body } } } def from[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_from_${name}", s"TLInterconnectCoupler_${busName}_from_${name}") { body } } } def coupleTo[T](name: String)(gen: TLOutwardNode => T): T = to(name) { gen(TLNameNode("tl") :*=* outwardNode) } def coupleFrom[T](name: String)(gen: TLInwardNode => T): T = from(name) { gen(inwardNode :*=* TLNameNode("tl")) } def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleTo(s"bus_named_${bus.busName}") { bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _ } } def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleFrom(s"bus_named_${bus.busName}") { _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType) } } } trait TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper } trait TLBusWrapperConnectionLike { val xType: ClockCrossingType def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit } object TLBusWrapperConnection { /** Backwards compatibility factory for master driving clock and slave setting cardinality */ def crossTo( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(true), nodeBinding: NodeBinding = BIND_STAR, flipRendering: Boolean = false) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) } /** Backwards compatibility factory for slave driving clock and master setting cardinality */ def crossFrom( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(false), nodeBinding: NodeBinding = BIND_QUERY, flipRendering: Boolean = true) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) } /** Factory for making generic connections between TLBusWrappers */ def apply (xType: ClockCrossingType = NoCrossing, driveClockFromMaster: Option[Boolean] = None, nodeBinding: NodeBinding = BIND_ONCE, flipRendering: Boolean = false)( slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, inject: Parameters => TLNode = { _ => TLTempNode() }) = { new TLBusWrapperConnection( xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView, masterNodeView, inject) } } /** TLBusWrapperConnection is a parameterization of a connection between two TLBusWrappers. * It has the following serializable parameters: * - xType: What type of TL clock crossing adapter to insert between the buses. * The appropriate half of the crossing adapter ends up inside each bus. * - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode, * otherwise have either the master or the slave bus bind the other one's clockGroupNode, * assuming the inserted crossing type is not asynchronous. * - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection. * - flipRendering: fine-grained control of the graphML rendering of the connection. * If has the following non-serializable parameters: * - slaveNodeView: programmatic control of the specific attachment point within the slave bus. * - masterNodeView: programmatic control of the specific attachment point within the master bus. * - injectNode: programmatic injection of additional nodes into the middle of the connection. * The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s. */ class TLBusWrapperConnection (val xType: ClockCrossingType, val driveClockFromMaster: Option[Boolean], val nodeBinding: NodeBinding, val flipRendering: Boolean) (slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, inject: Parameters => TLNode) extends TLBusWrapperConnectionLike { def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = { val masterTLBus = context.locateTLBusWrapper(master) val slaveTLBus = context.locateTLBusWrapper(slave) def bindClocks(implicit p: Parameters) = driveClockFromMaster match { case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode) case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode) case None => } def bindTLNodes(implicit p: Parameters) = nodeBinding match { case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_QUERY => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p) case BIND_STAR => slaveNodeView(slaveTLBus, p) :*= TLWidthWidget(masterTLBus.beatBytes) :*= inject(p) :*= masterNodeView(masterTLBus, p) case BIND_FLEX => slaveNodeView(slaveTLBus, p) :*=* TLWidthWidget(masterTLBus.beatBytes) :*=* inject(p) :*=* masterNodeView(masterTLBus, p) } if (flipRendering) { FlipRendering { implicit p => bindClocks(implicitly[Parameters]) slaveTLBus.from(s"bus_named_${masterTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } else { bindClocks(implicitly[Parameters]) masterTLBus.to (s"bus_named_${slaveTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } } class TLBusWrapperTopology( val instantiations: Seq[(Location[TLBusWrapper], TLBusWrapperInstantiationLike)], val connections: Seq[(Location[TLBusWrapper], Location[TLBusWrapper], TLBusWrapperConnectionLike)] ) extends CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations { def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } } } def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } } } } trait HasTLXbarPhy { this: TLBusWrapper => private val xbar = LazyModule(new TLXbar(nameSuffix = Some(busName))).suggestName(busName + "_xbar") override def shouldBeInlined = xbar.node.circuitIdentity def inwardNode: TLInwardNode = xbar.node def outwardNode: TLOutwardNode = xbar.node def busView: TLEdge = xbar.node.edges.in.head } case class AddressAdjusterWrapperParams( blockBytes: Int, beatBytes: Int, replication: Option[ReplicatedRegion], forceLocal: Seq[AddressSet] = Nil, localBaseAddressDefault: Option[BigInt] = None, policy: TLFIFOFixer.Policy = TLFIFOFixer.allVolatile, ordered: Boolean = true ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = { val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name)) aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> aaWrapper) aaWrapper } } class AddressAdjusterWrapper(params: AddressAdjusterWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val address_adjuster = params.replication.map { r => LazyModule(new AddressAdjuster(r, params.forceLocal, params.localBaseAddressDefault, params.ordered)) } private val viewNode = TLIdentityNode() val inwardNode: TLInwardNode = address_adjuster.map(_.node :*=* TLFIFOFixer(params.policy) :*=* viewNode).getOrElse(viewNode) def outwardNode: TLOutwardNode = address_adjuster.map(_.node).getOrElse(viewNode) def busView: TLEdge = viewNode.edges.in.head val prefixNode = address_adjuster.map { a => a.prefix := addressPrefixNexusNode addressPrefixNexusNode } val builtInDevices = BuiltInDevices.none override def shouldBeInlined = !params.replication.isDefined } case class TLJBarWrapperParams( blockBytes: Int, beatBytes: Int ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = { val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name)) jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> jbarWrapper) jbarWrapper } } class TLJBarWrapper(params: TLJBarWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val jbar = LazyModule(new TLJbar) val inwardNode: TLInwardNode = jbar.node val outwardNode: TLOutwardNode = jbar.node def busView: TLEdge = jbar.node.edges.in.head val prefixNode = None val builtInDevices = BuiltInDevices.none override def shouldBeInlined = jbar.node.circuitIdentity } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Scratchpad.scala: package testchipip.soc import chisel3._ import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.resources.{DiplomacyUtils} import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters} import scala.collection.immutable.{ListMap} case class BankedScratchpadParams( base: BigInt, size: BigInt, busWhere: TLBusWrapperLocation = SBUS, banks: Int = 4, subBanks: Int = 2, name: String = "banked-scratchpad", disableMonitors: Boolean = false, buffer: BufferParams = BufferParams.none, outerBuffer: BufferParams = BufferParams.none, dtsEnabled: Boolean = false ) case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil) class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { val mask = (subBanks - 1) * p(CacheBlockBytes) val xbar = TLXbar() (0 until subBanks).map { sb => val ram = LazyModule(new TLRAM( address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask), beatBytes = beatBytes, devOverride = Some(devOverride)) { override lazy val desiredName = s"TLRAM_ScratchpadBank" }) ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar } override lazy val desiredName = "ScratchpadBank" } trait CanHaveBankedScratchpad { this: BaseSubsystem => p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) => val bus = locateTLBusWrapper(params.busWhere) require (params.subBanks >= 1) val name = params.name val banks = params.banks val bankStripe = p(CacheBlockBytes)*params.subBanks val mask = (params.banks-1)*bankStripe val device = new MemoryDevice { override def describe(resources: ResourceBindings): Description = { Description(describeName("memory", resources), ListMap( "reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList, "device_type" -> Seq(ResourceString("memory")), "status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled")) )) } } def genBanks()(implicit p: Parameters) = (0 until banks).map { b => val bank = LazyModule(new ScratchpadBank( params.subBanks, AddressSet(params.base + bankStripe * b, params.size - 1 - mask), bus.beatBytes, device, params.buffer)) bank.clockNode := bus.fixedClockNode bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ } } if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks() } } File ClockGroupCombiner.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ object ClockGroupCombiner { def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = { LazyModule(new ClockGroupCombiner()).node } } case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil) // All clock groups with a name containing any substring in names will be combined into a single clock group class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => { case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) => (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n))) } }) /** This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey * The ClockGroupCombinersKey contains a list of tuples of: * - The name of the combined group * - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node * This node will fail if * - Multiple grouping functions match a single clock group * - A grouping function matches zero clock groups * - A grouping function matches clock groups with different requested frequncies */ class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule { val combiners = p(ClockGroupCombinerKey) val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m } val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u => var i = 0 val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) => val (g, r) = rest.partition(c(_)) val name = combiners(i)._1 i = i + 1 require(g.size >= 1) val names = g.map(_.name.getOrElse("unamed")) val takes = g.map(_.take).flatten require(takes.distinct.size <= 1, s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}") require(takes.size > 0, s"Clock group '$name' has no inheritable frequencies") (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r) } ClockGroupSinkParameters( name = u.name, members = grouped ++ rest ) } val node = ClockGroupAdapterNode(sourceFn, sinkFn) lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, oe), (i, ie)) => { val inMap = (i.member.data zip ie.sink.members).map { case (id, im) => im.name.get -> id }.toMap (o.member.data zip oe.sink.members).map { case (od, om) => val matches = combiners.filter(c => c._2(om)) require(matches.size <= 1) if (matches.size == 0) { od := inMap(om.name.get) } else { od := inMap(matches(0)._1) } } } } } } File SinkNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, IO} import org.chipsalliance.diplomacy.ValName /** A node which represents a node in the graph which has only inward edges, no outward edges. * * A [[SinkNode]] cannot appear cannot appear right of a `:=`, `:*=`, `:=*`, or `:*=*` * * There are no "Mixed" [[SinkNode]]s because each one only has an inward side. */ class SinkNode[D, U, EO, EI, B <: Data]( imp: NodeImp[D, U, EO, EI, B] )(pi: Seq[U] )( implicit valName: ValName) extends MixedNode(imp, imp) { override def description = "sink" protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { def resolveStarInfo: String = s"""$context |$bindingInfo |number of known := bindings to inward nodes: $iKnown |number of known := bindings to outward nodes: $oKnown |number of binding queries from inward nodes: $iStars |number of binding queries from outward nodes: $oStars |${pi.size} inward parameters: [${pi.map(_.toString).mkString(",")}] |""".stripMargin require( iStars <= 1, s"""Diplomacy has detected a problem with your graph: |The following node appears left of a :*= $iStars times; at most once is allowed. |$resolveStarInfo |""".stripMargin ) require( oStars == 0, s"""Diplomacy has detected a problem with your graph: |The following node cannot appear right of a :=* |$resolveStarInfo |""".stripMargin ) require( oKnown == 0, s"""Diplomacy has detected a problem with your graph: |The following node cannot appear right of a := |$resolveStarInfo |""".stripMargin ) if (iStars == 0) require( pi.size == iKnown, s"""Diplomacy has detected a problem with your graph: |The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. |Either the number of inward := bindings should be exactly equal to the number of sink, or connect this node on the left-hand side of a :*= |$resolveStarInfo |""".stripMargin ) else require( pi.size >= iKnown, s"""Diplomacy has detected a problem with your graph: |The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. |To resolve :*=, size of inward parameters can not be less than bindings. |$resolveStarInfo |""".stripMargin ) (pi.size - iKnown, 0) } protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq() protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi def makeIOs( )( implicit valName: ValName ): HeterogeneousBag[B] = { val bundles = this.in.map(_._1) val ios = IO(new HeterogeneousBag(bundles)) ios.suggestName(valName.value) bundles.zip(ios).foreach { case (bundle, io) => io <> bundle } ios } } File DigitalTop.scala: package chipyard import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // BOOM and/or Rocket Top Level Systems // ------------------------------------ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l) with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop File FrontBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams} import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy} import freechips.rocketchip.util.{Location} case class FrontBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = { val fbus = LazyModule(new FrontBus(this, loc.name)) fbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> fbus) fbus } } class FrontBus(params: FrontBusParams, name: String = "front_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) with HasTLXbarPhy { val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) val prefixNode = None } File PeripheryTLSerial.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.util.{ClockedIO} import testchipip.soc.{OBUS} // Parameters for a read-only-memory that appears over serial-TL case class ManagerROMParams( address: BigInt = 0x20000, size: Int = 0x10000, contentFileName: Option[String] = None) // If unset, generates a JALR to DRAM_BASE // Parameters for a read/write memory that appears over serial-TL case class ManagerRAMParams( address: BigInt, size: BigInt) // Parameters for a coherent cacheable read/write memory that appears over serial-TL case class ManagerCOHParams( address: BigInt, size: BigInt) // Parameters for a set of memory regions that appear over serial-TL case class SerialTLManagerParams( memParams: Seq[ManagerRAMParams] = Nil, romParams: Seq[ManagerROMParams] = Nil, cohParams: Seq[ManagerCOHParams] = Nil, isMemoryDevice: Boolean = false, sinkIdBits: Int = 8, totalIdBits: Int = 8, cacheIdBits: Int = 2, slaveWhere: TLBusWrapperLocation = OBUS ) // Parameters for a TL client which may probe this system over serial-TL case class SerialTLClientParams( totalIdBits: Int = 8, cacheIdBits: Int = 2, masterWhere: TLBusWrapperLocation = FBUS, supportsProbe: Boolean = false ) // The SerialTL can be configured to be bidirectional if serialTLManagerParams is set case class SerialTLParams( client: Option[SerialTLClientParams] = None, manager: Option[SerialTLManagerParams] = None, phyParams: SerialPhyParams = ExternalSyncSerialPhyParams(), bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS) case object SerialTLKey extends Field[Seq[SerialTLParams]](Nil) trait CanHavePeripheryTLSerial { this: BaseSubsystem => private val portName = "serial-tl" val tlChannels = 5 val (serdessers, serial_tls, serial_tl_debugs) = p(SerialTLKey).zipWithIndex.map { case (params, sid) => val name = s"serial_tl_$sid" lazy val manager_bus = params.manager.map(m => locateTLBusWrapper(m.slaveWhere)) lazy val client_bus = params.client.map(c => locateTLBusWrapper(c.masterWhere)) val clientPortParams = params.client.map { c => TLMasterPortParameters.v1( clients = Seq.tabulate(1 << c.cacheIdBits){ i => TLMasterParameters.v1( name = s"serial_tl_${sid}_${i}", sourceId = IdRange(i << (c.totalIdBits - c.cacheIdBits), (i + 1) << (c.totalIdBits - c.cacheIdBits)), supportsProbe = if (c.supportsProbe) TransferSizes(client_bus.get.blockBytes, client_bus.get.blockBytes) else TransferSizes.none )} )} val managerPortParams = params.manager.map { m => val memParams = m.memParams val romParams = m.romParams val cohParams = m.cohParams val memDevice = if (m.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil) val romDevice = new SimpleDevice("lbwif-readonly", Nil) val blockBytes = manager_bus.get.blockBytes TLSlavePortParameters.v1( managers = memParams.map { memParams => TLSlaveParameters.v1( address = AddressSet.misaligned(memParams.address, memParams.size), resources = memDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )} ++ romParams.map { romParams => TLSlaveParameters.v1( address = List(AddressSet(romParams.address, romParams.size-1)), resources = romDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), fifoId = Some(0) )} ++ cohParams.map { cohParams => TLSlaveParameters.v1( address = AddressSet.misaligned(cohParams.address, cohParams.size), regionType = RegionType.TRACKED, // cacheable executable = true, supportsAcquireT = TransferSizes(1, blockBytes), supportsAcquireB = TransferSizes(1, blockBytes), supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )}, beatBytes = manager_bus.get.beatBytes, endSinkId = if (cohParams.isEmpty) 0 else (1 << m.sinkIdBits), minLatency = 1 ) } val serial_tl_domain = LazyModule(new ClockSinkDomain(name=Some(s"SerialTL$sid"))) serial_tl_domain.clockNode := manager_bus.getOrElse(client_bus.get).fixedClockNode if (manager_bus.isDefined) require(manager_bus.get.dtsFrequency.isDefined, s"Manager bus ${manager_bus.get.busName} must provide a frequency") if (client_bus.isDefined) require(client_bus.get.dtsFrequency.isDefined, s"Client bus ${client_bus.get.busName} must provide a frequency") if (manager_bus.isDefined && client_bus.isDefined) { val managerFreq = manager_bus.get.dtsFrequency.get val clientFreq = client_bus.get.dtsFrequency.get require(managerFreq == clientFreq, s"Mismatching manager freq $managerFreq != client freq $clientFreq") } val serdesser = serial_tl_domain { LazyModule(new TLSerdesser( flitWidth = params.phyParams.flitWidth, clientPortParams = clientPortParams, managerPortParams = managerPortParams, bundleParams = params.bundleParams, nameSuffix = Some(name) )) } serdesser.managerNode.foreach { managerNode => val maxClients = 1 << params.manager.get.cacheIdBits val maxIdsPerClient = 1 << (params.manager.get.totalIdBits - params.manager.get.cacheIdBits) manager_bus.get.coupleTo(s"port_named_${name}_out") { (managerNode := TLProbeBlocker(p(CacheBlockBytes)) := TLSourceAdjuster(maxClients, maxIdsPerClient) := TLSourceCombiner(maxIdsPerClient) := TLWidthWidget(manager_bus.get.beatBytes) := _) } } serdesser.clientNode.foreach { clientNode => client_bus.get.coupleFrom(s"port_named_${name}_in") { _ := TLBuffer() := clientNode } } // If we provide a clock, generate a clock domain for the outgoing clock val serial_tl_clock_freqMHz = params.phyParams match { case params: InternalSyncSerialPhyParams => Some(params.freqMHz) case params: ExternalSyncSerialPhyParams => None case params: SourceSyncSerialPhyParams => Some(params.freqMHz) } val serial_tl_clock_node = serial_tl_clock_freqMHz.map { f => serial_tl_domain { ClockSinkNode(Seq(ClockSinkParameters(take=Some(ClockParameters(f))))) } } serial_tl_clock_node.foreach(_ := ClockGroup()(p, ValName(s"${name}_clock")) := allClockGroupsNode) val inner_io = serial_tl_domain { InModuleBody { val inner_io = IO(params.phyParams.genIO).suggestName(name) inner_io match { case io: InternalSyncPhitIO => { // Outer clock comes from the clock node. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = serial_tl_clock_node.get.in.head._1.clock io.clock_out := outer_clock val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(io.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: ExternalSyncPhitIO => { // Outer clock comes from the IO. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = io.clock_in val outer_reset = ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(params.phyParams.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: SourceSyncPhitIO => { // 3 clock domains - // - serdesser's "Inner clock": synchronizes signals going to the digital logic // - outgoing clock: synchronizes signals going out // - incoming clock: synchronizes signals coming in val outgoing_clock = serial_tl_clock_node.get.in.head._1.clock val outgoing_reset = ResetCatchAndSync(outgoing_clock, serdesser.module.reset.asBool) val incoming_clock = io.clock_in val incoming_reset = ResetCatchAndSync(incoming_clock, io.reset_in.asBool) io.clock_out := outgoing_clock io.reset_out := outgoing_reset.asAsyncReset val phy = Module(new CreditedSerialPhy(tlChannels, params.phyParams)) phy.io.incoming_clock := incoming_clock phy.io.incoming_reset := incoming_reset phy.io.outgoing_clock := outgoing_clock phy.io.outgoing_reset := outgoing_reset phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.inner_ser <> serdesser.module.io.ser phy.io.outer_ser <> io.viewAsSupertype(new ValidPhitIO(params.phyParams.phitWidth)) } } inner_io }} val outer_io = InModuleBody { val outer_io = IO(params.phyParams.genIO).suggestName(name) outer_io <> inner_io outer_io } val inner_debug_io = serial_tl_domain { InModuleBody { val inner_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") inner_debug_io := serdesser.module.io.debug inner_debug_io }} val outer_debug_io = InModuleBody { val outer_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") outer_debug_io := inner_debug_io outer_debug_io } (serdesser, outer_io, outer_debug_io) }.unzip3 } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File SystemBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{ BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams } import freechips.rocketchip.tilelink.{ TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode, TLFIFOFixer, TLTempNode } import freechips.rocketchip.util.Location case class SystemBusParams( beatBytes: Int, blockBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = { val sbus = LazyModule(new SystemBus(this, loc.name)) sbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> sbus) sbus } } class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name))) val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode()) val outwardNode: TLOutwardNode = system_bus_xbar.node def busView: TLEdge = system_bus_xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File InterruptBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.{Device, DeviceInterrupts, Description, ResourceBindings} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain} import freechips.rocketchip.interrupts.IntClockDomainCrossing /** Collects interrupts from internal and external devices and feeds them into the PLIC */ class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain { override def shouldBeInlined = true val int_bus = LazyModule(new IntXbar) // Interrupt crossbar private val int_in_xing = this.crossIn(int_bus.intnode) private val int_out_xing = this.crossOut(int_bus.intnode) def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) :=* IntNameNode(name) def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) :*= int_out_xing(xing) def fromAsync: IntInwardNode = from(None)(AsynchronousCrossing(8,3)) def fromRational: IntInwardNode = from(None)(RationalCrossing()) def fromSync: IntInwardNode = int_bus.intnode def toPLIC: IntOutwardNode = int_bus.intnode } /** Specifies the number of external interrupts */ case object NExtTopInterrupts extends Field[Int](0) /** This trait adds externally driven interrupts to the system. * However, it should not be used directly; instead one of the below * synchronization wiring child traits should be used. */ abstract trait HasExtInterrupts { this: BaseSubsystem => private val device = new Device with DeviceInterrupts { def describe(resources: ResourceBindings): Description = { Description("soc/external-interrupts", describeInterrupts(resources)) } } val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) } /** This trait should be used if the External Interrupts have NOT * already been synchronized to the Periphery (PLIC) Clock. */ trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromAsync := extInterrupts } } } /** This trait can be used if the External Interrupts have already been synchronized * to the Periphery (PLIC) Clock. */ trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromSync := extInterrupts } } } /** Common io name and methods for propagating or tying off the port bundle */ trait HasExtInterruptsBundle { val interrupts: UInt def tieOffInterrupts(dummy: Int = 1): Unit = { interrupts := 0.U } } /** This trait performs the translation from a UInt IO into Diplomatic Interrupts. * The wiring must be done in the concrete LazyModuleImp. */ trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle { val outer: HasExtInterrupts val interrupts = IO(Input(UInt(outer.nExtInterrupts.W))) outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) } } File BundleBridgeSink.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, IO, Output} import chisel3.reflect.DataMirror import chisel3.reflect.DataMirror.internal.chiselTypeClone import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.SinkNode case class BundleBridgeSink[T <: Data]( genOpt: Option[() => T] = None )( implicit valName: ValName) extends SinkNode(new BundleBridgeImp[T])(Seq(BundleBridgeParams(genOpt))) { def bundle: T = in(0)._1 private def inferOutput = getElements(bundle).forall { elt => DataMirror.directionOf(elt) == ActualDirection.Unspecified } def makeIO( )( implicit valName: ValName ): T = { val io: T = IO( if (inferOutput) Output(chiselTypeOf(bundle)) else chiselTypeClone(bundle) ) io.suggestName(valName.value) io <> bundle io } def makeIO(name: String): T = makeIO()(ValName(name)) } object BundleBridgeSink { def apply[T <: Data]( )( implicit valName: ValName ): BundleBridgeSink[T] = { BundleBridgeSink(None) } }

module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [4:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [15:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1653 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1668 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1753 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_133( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module RecFNToRecFN_18( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_223( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }

module SwitchArbiter_173( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_6_ready, // @[SwitchAllocator.scala:18:14] input io_in_6_valid, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_7_ready, // @[SwitchAllocator.scala:18:14] input io_in_7_valid, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [7:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [7:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [7:0] unassigned = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, 2'h0} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}, :39:21, :41:24] reg [7:0] mask; // @[SwitchAllocator.scala:27:21] wire [7:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [15:0] sel = _sel_T_1[0] ? 16'h1 : _sel_T_1[1] ? 16'h2 : _sel_T_1[2] ? 16'h4 : _sel_T_1[3] ? 16'h8 : _sel_T_1[4] ? 16'h10 : _sel_T_1[5] ? 16'h20 : _sel_T_1[6] ? 16'h40 : _sel_T_1[7] ? 16'h80 : unassigned[0] ? 16'h100 : unassigned[1] ? 16'h200 : unassigned[2] ? 16'h400 : unassigned[3] ? 16'h800 : unassigned[4] ? 16'h1000 : unassigned[5] ? 16'h2000 : unassigned[6] ? 16'h4000 : {unassigned[7], 15'h0}; // @[OneHot.scala:85:71] wire [5:0] _GEN = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid}; // @[SwitchAllocator.scala:41:24] wire [7:0] chosen = (|(_GEN & lock_0[7:2])) ? lock_0 : sel[7:0] | sel[15:8]; // @[Mux.scala:50:70] wire [5:0] _io_out_0_valid_T = _GEN & chosen[7:2]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN_0 = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35] wire [6:0] _GEN_1 = chosen[6:0] | chosen[7:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_2 = _GEN_1[5:0] | chosen[7:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_3 = _GEN_2[4:0] | chosen[7:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_4 = _GEN_3[3:0] | chosen[7:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_5 = _GEN_4[2:0] | chosen[7:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_6 = _GEN_5[1:0] | chosen[7:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 8'h0; // @[SwitchAllocator.scala:24:38] mask <= 8'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_0) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_7_bits_tail, ~io_in_6_bits_tail, ~io_in_5_bits_tail, ~io_in_4_bits_tail, ~io_in_3_bits_tail, ~io_in_2_bits_tail, 2'h3}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_0 ? {chosen[7], _GEN_1[6], _GEN_2[5], _GEN_3[4], _GEN_4[3], _GEN_5[2], _GEN_6[1], _GEN_6[0] | chosen[7]} : (&mask) ? 8'h0 : {mask[6:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_49( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet || m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) || (arithmetic && !m.supportsArithmetic.contains(ourSupport)) || !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ || _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ || _) val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask | (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) | signext_a val a_d_ext = (a_d & wide_mask) | signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8*beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready || d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied in.d.bits.denied := d_cam_denied || out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData val doesR = a.opcode === Get || doesA val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) || (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start }

module TLAtomicAutomata_ccbus0( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset // @[AtomicAutomata.scala:36:9] ); endmodule

Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File TileResetSetter.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ // Currently only works if all tiles are already driven by independent clock groups // TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should // always put all tiles on independent clock groups class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("tile-reset-setter", Nil) val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) val clockNode = ClockGroupIdentityNode() lazy val module = new LazyModuleImp(this) { val nTiles = p(TilesLocated(InSubsystem)).size require (nTiles <= 4096 / 4) val tile_async_resets = Wire(Vec(nTiles, Reset())) val r_tile_resets = (0 until nTiles).map({ i => tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842 withReset (tile_async_resets(i)) { Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0))) } }) if (nTiles > 0) tlNode.regmap((0 until nTiles).map({ i => i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)) }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream // to synchronize the resets // Also, this or enforces that the tiles come out of reset after the reset of the system oD.reset := (rOut.asBool || iD.reset.asBool).asAsyncReset rIn := iD.reset } } } } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_64 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_tl_in_d_ready), .io_in_a_valid (auto_tl_in_a_valid), .io_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .io_in_a_bits_param (auto_tl_in_a_bits_param), .io_in_a_bits_size (auto_tl_in_a_bits_size), .io_in_a_bits_source (auto_tl_in_a_bits_source), .io_in_a_bits_address (auto_tl_in_a_bits_address), .io_in_a_bits_mask (auto_tl_in_a_bits_mask), .io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .io_in_d_ready (auto_tl_in_d_ready), .io_in_d_valid (auto_tl_in_a_valid), .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_tl_in_a_bits_size), .io_in_d_bits_source (auto_tl_in_a_bits_source) ); // @[Nodes.scala:27:25] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLBuffer_a32d64s5k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_13 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_user_amba_prot_privileged (auto_in_a_bits_user_amba_prot_privileged), .io_enq_bits_user_amba_prot_secure (auto_in_a_bits_user_amba_prot_secure), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_user_amba_prot_bufferable (auto_out_a_bits_user_amba_prot_bufferable), .io_deq_bits_user_amba_prot_modifiable (auto_out_a_bits_user_amba_prot_modifiable), .io_deq_bits_user_amba_prot_readalloc (auto_out_a_bits_user_amba_prot_readalloc), .io_deq_bits_user_amba_prot_writealloc (auto_out_a_bits_user_amba_prot_writealloc), .io_deq_bits_user_amba_prot_privileged (auto_out_a_bits_user_amba_prot_privileged), .io_deq_bits_user_amba_prot_secure (auto_out_a_bits_user_amba_prot_secure), .io_deq_bits_user_amba_prot_fetch (auto_out_a_bits_user_amba_prot_fetch), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_EntryData_35( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid || valids.reduce(_||_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }

module Pipeline_9( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_0_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_1_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_2_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_3_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_4_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_5_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_6_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_7_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_8_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_9_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_10_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_11_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_12_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_13_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_14_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_data_15_0, // @[Pipeline.scala:7:14] input io_in_bits_resp_fromDMA, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_scale_bits, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_igelu_qb, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_igelu_qc, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_iexp_qln2, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_resp_iexp_qln2_inv, // @[Pipeline.scala:7:14] input [2:0] io_in_bits_resp_act, // @[Pipeline.scala:7:14] input [1:0] io_in_bits_resp_acc_bank_id, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_0_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_1_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_2_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_3_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_4_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_5_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_6_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_7_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_8_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_9_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_10_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_11_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_12_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_13_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_14_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_full_data_15_0, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_0_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_1_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_2_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_3_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_4_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_5_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_6_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_7_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_8_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_9_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_10_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_11_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_12_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_13_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_14_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_resp_data_15_0, // @[Pipeline.scala:7:14] output io_out_bits_resp_fromDMA, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_resp_acc_bank_id, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_0_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_1_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_2_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_3_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_4_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_5_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_6_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_7_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_8_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_9_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_10_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_11_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_12_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_13_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_14_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_full_data_15_0 // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_0_0_0 = io_in_bits_resp_data_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_1_0_0 = io_in_bits_resp_data_1_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_2_0_0 = io_in_bits_resp_data_2_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_3_0_0 = io_in_bits_resp_data_3_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_4_0_0 = io_in_bits_resp_data_4_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_5_0_0 = io_in_bits_resp_data_5_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_6_0_0 = io_in_bits_resp_data_6_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_7_0_0 = io_in_bits_resp_data_7_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_8_0_0 = io_in_bits_resp_data_8_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_9_0_0 = io_in_bits_resp_data_9_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_10_0_0 = io_in_bits_resp_data_10_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_11_0_0 = io_in_bits_resp_data_11_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_12_0_0 = io_in_bits_resp_data_12_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_13_0_0 = io_in_bits_resp_data_13_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_14_0_0 = io_in_bits_resp_data_14_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_data_15_0_0 = io_in_bits_resp_data_15_0; // @[Pipeline.scala:6:7] wire io_in_bits_resp_fromDMA_0 = io_in_bits_resp_fromDMA; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_scale_bits_0 = io_in_bits_resp_scale_bits; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_igelu_qb_0 = io_in_bits_resp_igelu_qb; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_igelu_qc_0 = io_in_bits_resp_igelu_qc; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_iexp_qln2_0 = io_in_bits_resp_iexp_qln2; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_resp_iexp_qln2_inv_0 = io_in_bits_resp_iexp_qln2_inv; // @[Pipeline.scala:6:7] wire [2:0] io_in_bits_resp_act_0 = io_in_bits_resp_act; // @[Pipeline.scala:6:7] wire [1:0] io_in_bits_resp_acc_bank_id_0 = io_in_bits_resp_acc_bank_id; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_0_0_0 = io_in_bits_full_data_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_1_0_0 = io_in_bits_full_data_1_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_2_0_0 = io_in_bits_full_data_2_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_3_0_0 = io_in_bits_full_data_3_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_4_0_0 = io_in_bits_full_data_4_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_5_0_0 = io_in_bits_full_data_5_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_6_0_0 = io_in_bits_full_data_6_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_7_0_0 = io_in_bits_full_data_7_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_8_0_0 = io_in_bits_full_data_8_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_9_0_0 = io_in_bits_full_data_9_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_10_0_0 = io_in_bits_full_data_10_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_11_0_0 = io_in_bits_full_data_11_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_12_0_0 = io_in_bits_full_data_12_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_13_0_0 = io_in_bits_full_data_13_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_14_0_0 = io_in_bits_full_data_14_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_full_data_15_0_0 = io_in_bits_full_data_15_0; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_4 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_5 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_6 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_7 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_7; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_0_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_1_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_2_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_3_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_4_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_5_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_6_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_7_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_8_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_9_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_10_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_11_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_12_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_13_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_14_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_data_15_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_scale_bits; // @[Pipeline.scala:6:7] wire io_out_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_igelu_qb; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_igelu_qc; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_iexp_qln2; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_resp_iexp_qln2_inv; // @[Pipeline.scala:6:7] wire [2:0] io_out_bits_resp_act; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_0_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_1_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_2_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_3_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_4_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_5_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_6_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_7_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_8_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_9_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_10_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_11_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_12_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_13_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_14_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_full_data_15_0_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy; // @[Pipeline.scala:6:7] reg [31:0] stages_0_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_0_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_0_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_0_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_0_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_0_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_1_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_1_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_1_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_1_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_1_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_2_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_2_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_2_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_2_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_2_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_3_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_3_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_3_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_3_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_3_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_4_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_4_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_4_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_4_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_4_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_5_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_5_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_5_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_5_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_5_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_data_15_0; // @[Pipeline.scala:21:21] reg stages_6_resp_fromDMA; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_scale_bits; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_igelu_qb; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_igelu_qc; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_iexp_qln2; // @[Pipeline.scala:21:21] reg [31:0] stages_6_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] reg [2:0] stages_6_resp_act; // @[Pipeline.scala:21:21] reg [1:0] stages_6_resp_acc_bank_id; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_0_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_1_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_2_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_3_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_4_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_5_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_6_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_7_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_8_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_9_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_10_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_11_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_12_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_13_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_14_0; // @[Pipeline.scala:21:21] reg [31:0] stages_6_full_data_15_0; // @[Pipeline.scala:21:21] reg [31:0] stages_7_resp_data_0_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_0_0_0 = stages_7_resp_data_0_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_1_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_1_0_0 = stages_7_resp_data_1_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_2_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_2_0_0 = stages_7_resp_data_2_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_3_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_3_0_0 = stages_7_resp_data_3_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_4_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_4_0_0 = stages_7_resp_data_4_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_5_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_5_0_0 = stages_7_resp_data_5_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_6_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_6_0_0 = stages_7_resp_data_6_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_7_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_7_0_0 = stages_7_resp_data_7_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_8_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_8_0_0 = stages_7_resp_data_8_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_9_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_9_0_0 = stages_7_resp_data_9_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_10_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_10_0_0 = stages_7_resp_data_10_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_11_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_11_0_0 = stages_7_resp_data_11_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_12_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_12_0_0 = stages_7_resp_data_12_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_13_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_13_0_0 = stages_7_resp_data_13_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_14_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_14_0_0 = stages_7_resp_data_14_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_data_15_0; // @[Pipeline.scala:21:21] assign io_out_bits_resp_data_15_0_0 = stages_7_resp_data_15_0; // @[Pipeline.scala:6:7, :21:21] reg stages_7_resp_fromDMA; // @[Pipeline.scala:21:21] assign io_out_bits_resp_fromDMA_0 = stages_7_resp_fromDMA; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_scale_bits; // @[Pipeline.scala:21:21] assign io_out_bits_resp_scale_bits = stages_7_resp_scale_bits; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_igelu_qb; // @[Pipeline.scala:21:21] assign io_out_bits_resp_igelu_qb = stages_7_resp_igelu_qb; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_igelu_qc; // @[Pipeline.scala:21:21] assign io_out_bits_resp_igelu_qc = stages_7_resp_igelu_qc; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_iexp_qln2; // @[Pipeline.scala:21:21] assign io_out_bits_resp_iexp_qln2 = stages_7_resp_iexp_qln2; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] assign io_out_bits_resp_iexp_qln2_inv = stages_7_resp_iexp_qln2_inv; // @[Pipeline.scala:6:7, :21:21] reg [2:0] stages_7_resp_act; // @[Pipeline.scala:21:21] assign io_out_bits_resp_act = stages_7_resp_act; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_7_resp_acc_bank_id; // @[Pipeline.scala:21:21] assign io_out_bits_resp_acc_bank_id_0 = stages_7_resp_acc_bank_id; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_0_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_0_0_0 = stages_7_full_data_0_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_1_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_1_0_0 = stages_7_full_data_1_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_2_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_2_0_0 = stages_7_full_data_2_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_3_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_3_0_0 = stages_7_full_data_3_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_4_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_4_0_0 = stages_7_full_data_4_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_5_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_5_0_0 = stages_7_full_data_5_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_6_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_6_0_0 = stages_7_full_data_6_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_7_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_7_0_0 = stages_7_full_data_7_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_8_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_8_0_0 = stages_7_full_data_8_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_9_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_9_0_0 = stages_7_full_data_9_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_10_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_10_0_0 = stages_7_full_data_10_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_11_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_11_0_0 = stages_7_full_data_11_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_12_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_12_0_0 = stages_7_full_data_12_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_13_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_13_0_0 = stages_7_full_data_13_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_14_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_14_0_0 = stages_7_full_data_14_0; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_7_full_data_15_0; // @[Pipeline.scala:21:21] assign io_out_bits_full_data_15_0_0 = stages_7_full_data_15_0; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] reg valids_2; // @[Pipeline.scala:22:25] reg valids_3; // @[Pipeline.scala:22:25] reg valids_4; // @[Pipeline.scala:22:25] reg valids_5; // @[Pipeline.scala:22:25] reg valids_6; // @[Pipeline.scala:22:25] reg valids_7; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_7; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T; // @[Pipeline.scala:30:16] wire _stalling_2_T; // @[Pipeline.scala:30:16] wire _stalling_3_T; // @[Pipeline.scala:30:16] wire _stalling_4_T; // @[Pipeline.scala:30:16] wire _stalling_5_T; // @[Pipeline.scala:30:16] wire _stalling_6_T; // @[Pipeline.scala:30:16] wire _stalling_7_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire stalling_2; // @[Pipeline.scala:23:27] wire stalling_3; // @[Pipeline.scala:23:27] wire stalling_4; // @[Pipeline.scala:23:27] wire stalling_5; // @[Pipeline.scala:23:27] wire stalling_6; // @[Pipeline.scala:23:27] wire stalling_7; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_3 = _io_busy_T_2 | valids_4; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_4 = _io_busy_T_3 | valids_5; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_5 = _io_busy_T_4 | valids_6; // @[Pipeline.scala:22:25, :24:46] wire _io_busy_T_6 = _io_busy_T_5 | valids_7; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_7 = io_in_valid_0 | _io_busy_T_6; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy = _io_busy_T_7; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_7_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_7_T_1 = valids_7 & _stalling_7_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_7 = _stalling_7_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_3_T = valids_3 & stalling_4; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_3 = _stalling_3_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_4_T = valids_4 & stalling_5; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_4 = _stalling_4_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_5_T = valids_5 & stalling_6; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_5 = _stalling_5_T; // @[Pipeline.scala:23:27, :30:16] assign _stalling_6_T = valids_6 & stalling_7; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_6 = _stalling_6_T; // @[Pipeline.scala:23:27, :30:16] wire _T_8 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_8) begin // @[Decoupled.scala:51:35] stages_0_resp_data_0_0 <= io_in_bits_resp_data_0_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_1_0 <= io_in_bits_resp_data_1_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_2_0 <= io_in_bits_resp_data_2_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_3_0 <= io_in_bits_resp_data_3_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_4_0 <= io_in_bits_resp_data_4_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_5_0 <= io_in_bits_resp_data_5_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_6_0 <= io_in_bits_resp_data_6_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_7_0 <= io_in_bits_resp_data_7_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_8_0 <= io_in_bits_resp_data_8_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_9_0 <= io_in_bits_resp_data_9_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_10_0 <= io_in_bits_resp_data_10_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_11_0 <= io_in_bits_resp_data_11_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_12_0 <= io_in_bits_resp_data_12_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_13_0 <= io_in_bits_resp_data_13_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_14_0 <= io_in_bits_resp_data_14_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_data_15_0 <= io_in_bits_resp_data_15_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_fromDMA <= io_in_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_scale_bits <= io_in_bits_resp_scale_bits_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_igelu_qb <= io_in_bits_resp_igelu_qb_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_igelu_qc <= io_in_bits_resp_igelu_qc_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_iexp_qln2 <= io_in_bits_resp_iexp_qln2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_iexp_qln2_inv <= io_in_bits_resp_iexp_qln2_inv_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_act <= io_in_bits_resp_act_0; // @[Pipeline.scala:6:7, :21:21] stages_0_resp_acc_bank_id <= io_in_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_0_0 <= io_in_bits_full_data_0_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_1_0 <= io_in_bits_full_data_1_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_2_0 <= io_in_bits_full_data_2_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_3_0 <= io_in_bits_full_data_3_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_4_0 <= io_in_bits_full_data_4_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_5_0 <= io_in_bits_full_data_5_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_6_0 <= io_in_bits_full_data_6_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_7_0 <= io_in_bits_full_data_7_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_8_0 <= io_in_bits_full_data_8_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_9_0 <= io_in_bits_full_data_9_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_10_0 <= io_in_bits_full_data_10_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_11_0 <= io_in_bits_full_data_11_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_12_0 <= io_in_bits_full_data_12_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_13_0 <= io_in_bits_full_data_13_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_14_0 <= io_in_bits_full_data_14_0_0; // @[Pipeline.scala:6:7, :21:21] stages_0_full_data_15_0 <= io_in_bits_full_data_15_0_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_resp_data_0_0 <= stages_0_resp_data_0_0; // @[Pipeline.scala:21:21] stages_1_resp_data_1_0 <= stages_0_resp_data_1_0; // @[Pipeline.scala:21:21] stages_1_resp_data_2_0 <= stages_0_resp_data_2_0; // @[Pipeline.scala:21:21] stages_1_resp_data_3_0 <= stages_0_resp_data_3_0; // @[Pipeline.scala:21:21] stages_1_resp_data_4_0 <= stages_0_resp_data_4_0; // @[Pipeline.scala:21:21] stages_1_resp_data_5_0 <= stages_0_resp_data_5_0; // @[Pipeline.scala:21:21] stages_1_resp_data_6_0 <= stages_0_resp_data_6_0; // @[Pipeline.scala:21:21] stages_1_resp_data_7_0 <= stages_0_resp_data_7_0; // @[Pipeline.scala:21:21] stages_1_resp_data_8_0 <= stages_0_resp_data_8_0; // @[Pipeline.scala:21:21] stages_1_resp_data_9_0 <= stages_0_resp_data_9_0; // @[Pipeline.scala:21:21] stages_1_resp_data_10_0 <= stages_0_resp_data_10_0; // @[Pipeline.scala:21:21] stages_1_resp_data_11_0 <= stages_0_resp_data_11_0; // @[Pipeline.scala:21:21] stages_1_resp_data_12_0 <= stages_0_resp_data_12_0; // @[Pipeline.scala:21:21] stages_1_resp_data_13_0 <= stages_0_resp_data_13_0; // @[Pipeline.scala:21:21] stages_1_resp_data_14_0 <= stages_0_resp_data_14_0; // @[Pipeline.scala:21:21] stages_1_resp_data_15_0 <= stages_0_resp_data_15_0; // @[Pipeline.scala:21:21] stages_1_resp_fromDMA <= stages_0_resp_fromDMA; // @[Pipeline.scala:21:21] stages_1_resp_scale_bits <= stages_0_resp_scale_bits; // @[Pipeline.scala:21:21] stages_1_resp_igelu_qb <= stages_0_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_1_resp_igelu_qc <= stages_0_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_1_resp_iexp_qln2 <= stages_0_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_1_resp_iexp_qln2_inv <= stages_0_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_1_resp_act <= stages_0_resp_act; // @[Pipeline.scala:21:21] stages_1_resp_acc_bank_id <= stages_0_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_1_full_data_0_0 <= stages_0_full_data_0_0; // @[Pipeline.scala:21:21] stages_1_full_data_1_0 <= stages_0_full_data_1_0; // @[Pipeline.scala:21:21] stages_1_full_data_2_0 <= stages_0_full_data_2_0; // @[Pipeline.scala:21:21] stages_1_full_data_3_0 <= stages_0_full_data_3_0; // @[Pipeline.scala:21:21] stages_1_full_data_4_0 <= stages_0_full_data_4_0; // @[Pipeline.scala:21:21] stages_1_full_data_5_0 <= stages_0_full_data_5_0; // @[Pipeline.scala:21:21] stages_1_full_data_6_0 <= stages_0_full_data_6_0; // @[Pipeline.scala:21:21] stages_1_full_data_7_0 <= stages_0_full_data_7_0; // @[Pipeline.scala:21:21] stages_1_full_data_8_0 <= stages_0_full_data_8_0; // @[Pipeline.scala:21:21] stages_1_full_data_9_0 <= stages_0_full_data_9_0; // @[Pipeline.scala:21:21] stages_1_full_data_10_0 <= stages_0_full_data_10_0; // @[Pipeline.scala:21:21] stages_1_full_data_11_0 <= stages_0_full_data_11_0; // @[Pipeline.scala:21:21] stages_1_full_data_12_0 <= stages_0_full_data_12_0; // @[Pipeline.scala:21:21] stages_1_full_data_13_0 <= stages_0_full_data_13_0; // @[Pipeline.scala:21:21] stages_1_full_data_14_0 <= stages_0_full_data_14_0; // @[Pipeline.scala:21:21] stages_1_full_data_15_0 <= stages_0_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_2) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_2_resp_data_0_0 <= stages_1_resp_data_0_0; // @[Pipeline.scala:21:21] stages_2_resp_data_1_0 <= stages_1_resp_data_1_0; // @[Pipeline.scala:21:21] stages_2_resp_data_2_0 <= stages_1_resp_data_2_0; // @[Pipeline.scala:21:21] stages_2_resp_data_3_0 <= stages_1_resp_data_3_0; // @[Pipeline.scala:21:21] stages_2_resp_data_4_0 <= stages_1_resp_data_4_0; // @[Pipeline.scala:21:21] stages_2_resp_data_5_0 <= stages_1_resp_data_5_0; // @[Pipeline.scala:21:21] stages_2_resp_data_6_0 <= stages_1_resp_data_6_0; // @[Pipeline.scala:21:21] stages_2_resp_data_7_0 <= stages_1_resp_data_7_0; // @[Pipeline.scala:21:21] stages_2_resp_data_8_0 <= stages_1_resp_data_8_0; // @[Pipeline.scala:21:21] stages_2_resp_data_9_0 <= stages_1_resp_data_9_0; // @[Pipeline.scala:21:21] stages_2_resp_data_10_0 <= stages_1_resp_data_10_0; // @[Pipeline.scala:21:21] stages_2_resp_data_11_0 <= stages_1_resp_data_11_0; // @[Pipeline.scala:21:21] stages_2_resp_data_12_0 <= stages_1_resp_data_12_0; // @[Pipeline.scala:21:21] stages_2_resp_data_13_0 <= stages_1_resp_data_13_0; // @[Pipeline.scala:21:21] stages_2_resp_data_14_0 <= stages_1_resp_data_14_0; // @[Pipeline.scala:21:21] stages_2_resp_data_15_0 <= stages_1_resp_data_15_0; // @[Pipeline.scala:21:21] stages_2_resp_fromDMA <= stages_1_resp_fromDMA; // @[Pipeline.scala:21:21] stages_2_resp_scale_bits <= stages_1_resp_scale_bits; // @[Pipeline.scala:21:21] stages_2_resp_igelu_qb <= stages_1_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_2_resp_igelu_qc <= stages_1_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_2_resp_iexp_qln2 <= stages_1_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_2_resp_iexp_qln2_inv <= stages_1_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_2_resp_act <= stages_1_resp_act; // @[Pipeline.scala:21:21] stages_2_resp_acc_bank_id <= stages_1_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_2_full_data_0_0 <= stages_1_full_data_0_0; // @[Pipeline.scala:21:21] stages_2_full_data_1_0 <= stages_1_full_data_1_0; // @[Pipeline.scala:21:21] stages_2_full_data_2_0 <= stages_1_full_data_2_0; // @[Pipeline.scala:21:21] stages_2_full_data_3_0 <= stages_1_full_data_3_0; // @[Pipeline.scala:21:21] stages_2_full_data_4_0 <= stages_1_full_data_4_0; // @[Pipeline.scala:21:21] stages_2_full_data_5_0 <= stages_1_full_data_5_0; // @[Pipeline.scala:21:21] stages_2_full_data_6_0 <= stages_1_full_data_6_0; // @[Pipeline.scala:21:21] stages_2_full_data_7_0 <= stages_1_full_data_7_0; // @[Pipeline.scala:21:21] stages_2_full_data_8_0 <= stages_1_full_data_8_0; // @[Pipeline.scala:21:21] stages_2_full_data_9_0 <= stages_1_full_data_9_0; // @[Pipeline.scala:21:21] stages_2_full_data_10_0 <= stages_1_full_data_10_0; // @[Pipeline.scala:21:21] stages_2_full_data_11_0 <= stages_1_full_data_11_0; // @[Pipeline.scala:21:21] stages_2_full_data_12_0 <= stages_1_full_data_12_0; // @[Pipeline.scala:21:21] stages_2_full_data_13_0 <= stages_1_full_data_13_0; // @[Pipeline.scala:21:21] stages_2_full_data_14_0 <= stages_1_full_data_14_0; // @[Pipeline.scala:21:21] stages_2_full_data_15_0 <= stages_1_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_3) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_3_resp_data_0_0 <= stages_2_resp_data_0_0; // @[Pipeline.scala:21:21] stages_3_resp_data_1_0 <= stages_2_resp_data_1_0; // @[Pipeline.scala:21:21] stages_3_resp_data_2_0 <= stages_2_resp_data_2_0; // @[Pipeline.scala:21:21] stages_3_resp_data_3_0 <= stages_2_resp_data_3_0; // @[Pipeline.scala:21:21] stages_3_resp_data_4_0 <= stages_2_resp_data_4_0; // @[Pipeline.scala:21:21] stages_3_resp_data_5_0 <= stages_2_resp_data_5_0; // @[Pipeline.scala:21:21] stages_3_resp_data_6_0 <= stages_2_resp_data_6_0; // @[Pipeline.scala:21:21] stages_3_resp_data_7_0 <= stages_2_resp_data_7_0; // @[Pipeline.scala:21:21] stages_3_resp_data_8_0 <= stages_2_resp_data_8_0; // @[Pipeline.scala:21:21] stages_3_resp_data_9_0 <= stages_2_resp_data_9_0; // @[Pipeline.scala:21:21] stages_3_resp_data_10_0 <= stages_2_resp_data_10_0; // @[Pipeline.scala:21:21] stages_3_resp_data_11_0 <= stages_2_resp_data_11_0; // @[Pipeline.scala:21:21] stages_3_resp_data_12_0 <= stages_2_resp_data_12_0; // @[Pipeline.scala:21:21] stages_3_resp_data_13_0 <= stages_2_resp_data_13_0; // @[Pipeline.scala:21:21] stages_3_resp_data_14_0 <= stages_2_resp_data_14_0; // @[Pipeline.scala:21:21] stages_3_resp_data_15_0 <= stages_2_resp_data_15_0; // @[Pipeline.scala:21:21] stages_3_resp_fromDMA <= stages_2_resp_fromDMA; // @[Pipeline.scala:21:21] stages_3_resp_scale_bits <= stages_2_resp_scale_bits; // @[Pipeline.scala:21:21] stages_3_resp_igelu_qb <= stages_2_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_3_resp_igelu_qc <= stages_2_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_3_resp_iexp_qln2 <= stages_2_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_3_resp_iexp_qln2_inv <= stages_2_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_3_resp_act <= stages_2_resp_act; // @[Pipeline.scala:21:21] stages_3_resp_acc_bank_id <= stages_2_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_3_full_data_0_0 <= stages_2_full_data_0_0; // @[Pipeline.scala:21:21] stages_3_full_data_1_0 <= stages_2_full_data_1_0; // @[Pipeline.scala:21:21] stages_3_full_data_2_0 <= stages_2_full_data_2_0; // @[Pipeline.scala:21:21] stages_3_full_data_3_0 <= stages_2_full_data_3_0; // @[Pipeline.scala:21:21] stages_3_full_data_4_0 <= stages_2_full_data_4_0; // @[Pipeline.scala:21:21] stages_3_full_data_5_0 <= stages_2_full_data_5_0; // @[Pipeline.scala:21:21] stages_3_full_data_6_0 <= stages_2_full_data_6_0; // @[Pipeline.scala:21:21] stages_3_full_data_7_0 <= stages_2_full_data_7_0; // @[Pipeline.scala:21:21] stages_3_full_data_8_0 <= stages_2_full_data_8_0; // @[Pipeline.scala:21:21] stages_3_full_data_9_0 <= stages_2_full_data_9_0; // @[Pipeline.scala:21:21] stages_3_full_data_10_0 <= stages_2_full_data_10_0; // @[Pipeline.scala:21:21] stages_3_full_data_11_0 <= stages_2_full_data_11_0; // @[Pipeline.scala:21:21] stages_3_full_data_12_0 <= stages_2_full_data_12_0; // @[Pipeline.scala:21:21] stages_3_full_data_13_0 <= stages_2_full_data_13_0; // @[Pipeline.scala:21:21] stages_3_full_data_14_0 <= stages_2_full_data_14_0; // @[Pipeline.scala:21:21] stages_3_full_data_15_0 <= stages_2_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_4) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_4_resp_data_0_0 <= stages_3_resp_data_0_0; // @[Pipeline.scala:21:21] stages_4_resp_data_1_0 <= stages_3_resp_data_1_0; // @[Pipeline.scala:21:21] stages_4_resp_data_2_0 <= stages_3_resp_data_2_0; // @[Pipeline.scala:21:21] stages_4_resp_data_3_0 <= stages_3_resp_data_3_0; // @[Pipeline.scala:21:21] stages_4_resp_data_4_0 <= stages_3_resp_data_4_0; // @[Pipeline.scala:21:21] stages_4_resp_data_5_0 <= stages_3_resp_data_5_0; // @[Pipeline.scala:21:21] stages_4_resp_data_6_0 <= stages_3_resp_data_6_0; // @[Pipeline.scala:21:21] stages_4_resp_data_7_0 <= stages_3_resp_data_7_0; // @[Pipeline.scala:21:21] stages_4_resp_data_8_0 <= stages_3_resp_data_8_0; // @[Pipeline.scala:21:21] stages_4_resp_data_9_0 <= stages_3_resp_data_9_0; // @[Pipeline.scala:21:21] stages_4_resp_data_10_0 <= stages_3_resp_data_10_0; // @[Pipeline.scala:21:21] stages_4_resp_data_11_0 <= stages_3_resp_data_11_0; // @[Pipeline.scala:21:21] stages_4_resp_data_12_0 <= stages_3_resp_data_12_0; // @[Pipeline.scala:21:21] stages_4_resp_data_13_0 <= stages_3_resp_data_13_0; // @[Pipeline.scala:21:21] stages_4_resp_data_14_0 <= stages_3_resp_data_14_0; // @[Pipeline.scala:21:21] stages_4_resp_data_15_0 <= stages_3_resp_data_15_0; // @[Pipeline.scala:21:21] stages_4_resp_fromDMA <= stages_3_resp_fromDMA; // @[Pipeline.scala:21:21] stages_4_resp_scale_bits <= stages_3_resp_scale_bits; // @[Pipeline.scala:21:21] stages_4_resp_igelu_qb <= stages_3_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_4_resp_igelu_qc <= stages_3_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_4_resp_iexp_qln2 <= stages_3_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_4_resp_iexp_qln2_inv <= stages_3_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_4_resp_act <= stages_3_resp_act; // @[Pipeline.scala:21:21] stages_4_resp_acc_bank_id <= stages_3_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_4_full_data_0_0 <= stages_3_full_data_0_0; // @[Pipeline.scala:21:21] stages_4_full_data_1_0 <= stages_3_full_data_1_0; // @[Pipeline.scala:21:21] stages_4_full_data_2_0 <= stages_3_full_data_2_0; // @[Pipeline.scala:21:21] stages_4_full_data_3_0 <= stages_3_full_data_3_0; // @[Pipeline.scala:21:21] stages_4_full_data_4_0 <= stages_3_full_data_4_0; // @[Pipeline.scala:21:21] stages_4_full_data_5_0 <= stages_3_full_data_5_0; // @[Pipeline.scala:21:21] stages_4_full_data_6_0 <= stages_3_full_data_6_0; // @[Pipeline.scala:21:21] stages_4_full_data_7_0 <= stages_3_full_data_7_0; // @[Pipeline.scala:21:21] stages_4_full_data_8_0 <= stages_3_full_data_8_0; // @[Pipeline.scala:21:21] stages_4_full_data_9_0 <= stages_3_full_data_9_0; // @[Pipeline.scala:21:21] stages_4_full_data_10_0 <= stages_3_full_data_10_0; // @[Pipeline.scala:21:21] stages_4_full_data_11_0 <= stages_3_full_data_11_0; // @[Pipeline.scala:21:21] stages_4_full_data_12_0 <= stages_3_full_data_12_0; // @[Pipeline.scala:21:21] stages_4_full_data_13_0 <= stages_3_full_data_13_0; // @[Pipeline.scala:21:21] stages_4_full_data_14_0 <= stages_3_full_data_14_0; // @[Pipeline.scala:21:21] stages_4_full_data_15_0 <= stages_3_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_5) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_5_resp_data_0_0 <= stages_4_resp_data_0_0; // @[Pipeline.scala:21:21] stages_5_resp_data_1_0 <= stages_4_resp_data_1_0; // @[Pipeline.scala:21:21] stages_5_resp_data_2_0 <= stages_4_resp_data_2_0; // @[Pipeline.scala:21:21] stages_5_resp_data_3_0 <= stages_4_resp_data_3_0; // @[Pipeline.scala:21:21] stages_5_resp_data_4_0 <= stages_4_resp_data_4_0; // @[Pipeline.scala:21:21] stages_5_resp_data_5_0 <= stages_4_resp_data_5_0; // @[Pipeline.scala:21:21] stages_5_resp_data_6_0 <= stages_4_resp_data_6_0; // @[Pipeline.scala:21:21] stages_5_resp_data_7_0 <= stages_4_resp_data_7_0; // @[Pipeline.scala:21:21] stages_5_resp_data_8_0 <= stages_4_resp_data_8_0; // @[Pipeline.scala:21:21] stages_5_resp_data_9_0 <= stages_4_resp_data_9_0; // @[Pipeline.scala:21:21] stages_5_resp_data_10_0 <= stages_4_resp_data_10_0; // @[Pipeline.scala:21:21] stages_5_resp_data_11_0 <= stages_4_resp_data_11_0; // @[Pipeline.scala:21:21] stages_5_resp_data_12_0 <= stages_4_resp_data_12_0; // @[Pipeline.scala:21:21] stages_5_resp_data_13_0 <= stages_4_resp_data_13_0; // @[Pipeline.scala:21:21] stages_5_resp_data_14_0 <= stages_4_resp_data_14_0; // @[Pipeline.scala:21:21] stages_5_resp_data_15_0 <= stages_4_resp_data_15_0; // @[Pipeline.scala:21:21] stages_5_resp_fromDMA <= stages_4_resp_fromDMA; // @[Pipeline.scala:21:21] stages_5_resp_scale_bits <= stages_4_resp_scale_bits; // @[Pipeline.scala:21:21] stages_5_resp_igelu_qb <= stages_4_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_5_resp_igelu_qc <= stages_4_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_5_resp_iexp_qln2 <= stages_4_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_5_resp_iexp_qln2_inv <= stages_4_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_5_resp_act <= stages_4_resp_act; // @[Pipeline.scala:21:21] stages_5_resp_acc_bank_id <= stages_4_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_5_full_data_0_0 <= stages_4_full_data_0_0; // @[Pipeline.scala:21:21] stages_5_full_data_1_0 <= stages_4_full_data_1_0; // @[Pipeline.scala:21:21] stages_5_full_data_2_0 <= stages_4_full_data_2_0; // @[Pipeline.scala:21:21] stages_5_full_data_3_0 <= stages_4_full_data_3_0; // @[Pipeline.scala:21:21] stages_5_full_data_4_0 <= stages_4_full_data_4_0; // @[Pipeline.scala:21:21] stages_5_full_data_5_0 <= stages_4_full_data_5_0; // @[Pipeline.scala:21:21] stages_5_full_data_6_0 <= stages_4_full_data_6_0; // @[Pipeline.scala:21:21] stages_5_full_data_7_0 <= stages_4_full_data_7_0; // @[Pipeline.scala:21:21] stages_5_full_data_8_0 <= stages_4_full_data_8_0; // @[Pipeline.scala:21:21] stages_5_full_data_9_0 <= stages_4_full_data_9_0; // @[Pipeline.scala:21:21] stages_5_full_data_10_0 <= stages_4_full_data_10_0; // @[Pipeline.scala:21:21] stages_5_full_data_11_0 <= stages_4_full_data_11_0; // @[Pipeline.scala:21:21] stages_5_full_data_12_0 <= stages_4_full_data_12_0; // @[Pipeline.scala:21:21] stages_5_full_data_13_0 <= stages_4_full_data_13_0; // @[Pipeline.scala:21:21] stages_5_full_data_14_0 <= stages_4_full_data_14_0; // @[Pipeline.scala:21:21] stages_5_full_data_15_0 <= stages_4_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_6) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_6_resp_data_0_0 <= stages_5_resp_data_0_0; // @[Pipeline.scala:21:21] stages_6_resp_data_1_0 <= stages_5_resp_data_1_0; // @[Pipeline.scala:21:21] stages_6_resp_data_2_0 <= stages_5_resp_data_2_0; // @[Pipeline.scala:21:21] stages_6_resp_data_3_0 <= stages_5_resp_data_3_0; // @[Pipeline.scala:21:21] stages_6_resp_data_4_0 <= stages_5_resp_data_4_0; // @[Pipeline.scala:21:21] stages_6_resp_data_5_0 <= stages_5_resp_data_5_0; // @[Pipeline.scala:21:21] stages_6_resp_data_6_0 <= stages_5_resp_data_6_0; // @[Pipeline.scala:21:21] stages_6_resp_data_7_0 <= stages_5_resp_data_7_0; // @[Pipeline.scala:21:21] stages_6_resp_data_8_0 <= stages_5_resp_data_8_0; // @[Pipeline.scala:21:21] stages_6_resp_data_9_0 <= stages_5_resp_data_9_0; // @[Pipeline.scala:21:21] stages_6_resp_data_10_0 <= stages_5_resp_data_10_0; // @[Pipeline.scala:21:21] stages_6_resp_data_11_0 <= stages_5_resp_data_11_0; // @[Pipeline.scala:21:21] stages_6_resp_data_12_0 <= stages_5_resp_data_12_0; // @[Pipeline.scala:21:21] stages_6_resp_data_13_0 <= stages_5_resp_data_13_0; // @[Pipeline.scala:21:21] stages_6_resp_data_14_0 <= stages_5_resp_data_14_0; // @[Pipeline.scala:21:21] stages_6_resp_data_15_0 <= stages_5_resp_data_15_0; // @[Pipeline.scala:21:21] stages_6_resp_fromDMA <= stages_5_resp_fromDMA; // @[Pipeline.scala:21:21] stages_6_resp_scale_bits <= stages_5_resp_scale_bits; // @[Pipeline.scala:21:21] stages_6_resp_igelu_qb <= stages_5_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_6_resp_igelu_qc <= stages_5_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_6_resp_iexp_qln2 <= stages_5_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_6_resp_iexp_qln2_inv <= stages_5_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_6_resp_act <= stages_5_resp_act; // @[Pipeline.scala:21:21] stages_6_resp_acc_bank_id <= stages_5_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_6_full_data_0_0 <= stages_5_full_data_0_0; // @[Pipeline.scala:21:21] stages_6_full_data_1_0 <= stages_5_full_data_1_0; // @[Pipeline.scala:21:21] stages_6_full_data_2_0 <= stages_5_full_data_2_0; // @[Pipeline.scala:21:21] stages_6_full_data_3_0 <= stages_5_full_data_3_0; // @[Pipeline.scala:21:21] stages_6_full_data_4_0 <= stages_5_full_data_4_0; // @[Pipeline.scala:21:21] stages_6_full_data_5_0 <= stages_5_full_data_5_0; // @[Pipeline.scala:21:21] stages_6_full_data_6_0 <= stages_5_full_data_6_0; // @[Pipeline.scala:21:21] stages_6_full_data_7_0 <= stages_5_full_data_7_0; // @[Pipeline.scala:21:21] stages_6_full_data_8_0 <= stages_5_full_data_8_0; // @[Pipeline.scala:21:21] stages_6_full_data_9_0 <= stages_5_full_data_9_0; // @[Pipeline.scala:21:21] stages_6_full_data_10_0 <= stages_5_full_data_10_0; // @[Pipeline.scala:21:21] stages_6_full_data_11_0 <= stages_5_full_data_11_0; // @[Pipeline.scala:21:21] stages_6_full_data_12_0 <= stages_5_full_data_12_0; // @[Pipeline.scala:21:21] stages_6_full_data_13_0 <= stages_5_full_data_13_0; // @[Pipeline.scala:21:21] stages_6_full_data_14_0 <= stages_5_full_data_14_0; // @[Pipeline.scala:21:21] stages_6_full_data_15_0 <= stages_5_full_data_15_0; // @[Pipeline.scala:21:21] end if (stalling_7) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_7_resp_data_0_0 <= stages_6_resp_data_0_0; // @[Pipeline.scala:21:21] stages_7_resp_data_1_0 <= stages_6_resp_data_1_0; // @[Pipeline.scala:21:21] stages_7_resp_data_2_0 <= stages_6_resp_data_2_0; // @[Pipeline.scala:21:21] stages_7_resp_data_3_0 <= stages_6_resp_data_3_0; // @[Pipeline.scala:21:21] stages_7_resp_data_4_0 <= stages_6_resp_data_4_0; // @[Pipeline.scala:21:21] stages_7_resp_data_5_0 <= stages_6_resp_data_5_0; // @[Pipeline.scala:21:21] stages_7_resp_data_6_0 <= stages_6_resp_data_6_0; // @[Pipeline.scala:21:21] stages_7_resp_data_7_0 <= stages_6_resp_data_7_0; // @[Pipeline.scala:21:21] stages_7_resp_data_8_0 <= stages_6_resp_data_8_0; // @[Pipeline.scala:21:21] stages_7_resp_data_9_0 <= stages_6_resp_data_9_0; // @[Pipeline.scala:21:21] stages_7_resp_data_10_0 <= stages_6_resp_data_10_0; // @[Pipeline.scala:21:21] stages_7_resp_data_11_0 <= stages_6_resp_data_11_0; // @[Pipeline.scala:21:21] stages_7_resp_data_12_0 <= stages_6_resp_data_12_0; // @[Pipeline.scala:21:21] stages_7_resp_data_13_0 <= stages_6_resp_data_13_0; // @[Pipeline.scala:21:21] stages_7_resp_data_14_0 <= stages_6_resp_data_14_0; // @[Pipeline.scala:21:21] stages_7_resp_data_15_0 <= stages_6_resp_data_15_0; // @[Pipeline.scala:21:21] stages_7_resp_fromDMA <= stages_6_resp_fromDMA; // @[Pipeline.scala:21:21] stages_7_resp_scale_bits <= stages_6_resp_scale_bits; // @[Pipeline.scala:21:21] stages_7_resp_igelu_qb <= stages_6_resp_igelu_qb; // @[Pipeline.scala:21:21] stages_7_resp_igelu_qc <= stages_6_resp_igelu_qc; // @[Pipeline.scala:21:21] stages_7_resp_iexp_qln2 <= stages_6_resp_iexp_qln2; // @[Pipeline.scala:21:21] stages_7_resp_iexp_qln2_inv <= stages_6_resp_iexp_qln2_inv; // @[Pipeline.scala:21:21] stages_7_resp_act <= stages_6_resp_act; // @[Pipeline.scala:21:21] stages_7_resp_acc_bank_id <= stages_6_resp_acc_bank_id; // @[Pipeline.scala:21:21] stages_7_full_data_0_0 <= stages_6_full_data_0_0; // @[Pipeline.scala:21:21] stages_7_full_data_1_0 <= stages_6_full_data_1_0; // @[Pipeline.scala:21:21] stages_7_full_data_2_0 <= stages_6_full_data_2_0; // @[Pipeline.scala:21:21] stages_7_full_data_3_0 <= stages_6_full_data_3_0; // @[Pipeline.scala:21:21] stages_7_full_data_4_0 <= stages_6_full_data_4_0; // @[Pipeline.scala:21:21] stages_7_full_data_5_0 <= stages_6_full_data_5_0; // @[Pipeline.scala:21:21] stages_7_full_data_6_0 <= stages_6_full_data_6_0; // @[Pipeline.scala:21:21] stages_7_full_data_7_0 <= stages_6_full_data_7_0; // @[Pipeline.scala:21:21] stages_7_full_data_8_0 <= stages_6_full_data_8_0; // @[Pipeline.scala:21:21] stages_7_full_data_9_0 <= stages_6_full_data_9_0; // @[Pipeline.scala:21:21] stages_7_full_data_10_0 <= stages_6_full_data_10_0; // @[Pipeline.scala:21:21] stages_7_full_data_11_0 <= stages_6_full_data_11_0; // @[Pipeline.scala:21:21] stages_7_full_data_12_0 <= stages_6_full_data_12_0; // @[Pipeline.scala:21:21] stages_7_full_data_13_0 <= stages_6_full_data_13_0; // @[Pipeline.scala:21:21] stages_7_full_data_14_0 <= stages_6_full_data_14_0; // @[Pipeline.scala:21:21] stages_7_full_data_15_0 <= stages_6_full_data_15_0; // @[Pipeline.scala:21:21] end if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] valids_2 <= 1'h0; // @[Pipeline.scala:22:25] valids_3 <= 1'h0; // @[Pipeline.scala:22:25] valids_4 <= 1'h0; // @[Pipeline.scala:22:25] valids_5 <= 1'h0; // @[Pipeline.scala:22:25] valids_6 <= 1'h0; // @[Pipeline.scala:22:25] valids_7 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_8 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_3 <= valids_2 | stalling_4 & valids_3; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_4 <= valids_3 | stalling_5 & valids_4; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_5 <= valids_4 | stalling_6 & valids_5; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_6 <= valids_5 | stalling_7 & valids_6; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12] valids_7 <= valids_6 | ~io_out_ready_0 & valids_7; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_0_0 = io_out_bits_resp_data_0_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_1_0 = io_out_bits_resp_data_1_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_2_0 = io_out_bits_resp_data_2_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_3_0 = io_out_bits_resp_data_3_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_4_0 = io_out_bits_resp_data_4_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_5_0 = io_out_bits_resp_data_5_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_6_0 = io_out_bits_resp_data_6_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_7_0 = io_out_bits_resp_data_7_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_8_0 = io_out_bits_resp_data_8_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_9_0 = io_out_bits_resp_data_9_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_10_0 = io_out_bits_resp_data_10_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_11_0 = io_out_bits_resp_data_11_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_12_0 = io_out_bits_resp_data_12_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_13_0 = io_out_bits_resp_data_13_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_14_0 = io_out_bits_resp_data_14_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_data_15_0 = io_out_bits_resp_data_15_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_fromDMA = io_out_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7] assign io_out_bits_resp_acc_bank_id = io_out_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_0_0 = io_out_bits_full_data_0_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_1_0 = io_out_bits_full_data_1_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_2_0 = io_out_bits_full_data_2_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_3_0 = io_out_bits_full_data_3_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_4_0 = io_out_bits_full_data_4_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_5_0 = io_out_bits_full_data_5_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_6_0 = io_out_bits_full_data_6_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_7_0 = io_out_bits_full_data_7_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_8_0 = io_out_bits_full_data_8_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_9_0 = io_out_bits_full_data_9_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_10_0 = io_out_bits_full_data_10_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_11_0 = io_out_bits_full_data_11_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_12_0 = io_out_bits_full_data_12_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_13_0 = io_out_bits_full_data_13_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_14_0 = io_out_bits_full_data_14_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_full_data_15_0 = io_out_bits_full_data_15_0_0; // @[Pipeline.scala:6:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module ClockCrossingReg_w32_17( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [31:0] io_d, // @[SynchronizerReg.scala:195:14] output [31:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [31:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [31:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [31:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFNToRaw_postMul_e8_s24_3( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Protocol.scala: package rerocc.bus import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import rerocc.client.{ReRoCCClientParams} import rerocc.manager.{ReRoCCManagerParams} object ReRoCCProtocol { val width = 3 val mAcquire = 0.U(width.W) // beat0: data = inst // beat1: data = mstatus[63:0] // beat2: data = mstatus[127:64] val mInst = 1.U(width.W) // beat0: data = mstatus[63:0] // beat1: data = mstatus[127:0] val mUStatus = 2.U(width.W) // beat0: data = ptbr val mUPtbr = 3.U(width.W) val mRelease = 4.U(width.W) val mUnbusy = 5.U(width.W) // data // data = acquired val sAcqResp = 0.U(width.W) // data = 0 val sInstAck = 1.U(width.W) // beat0: data = data // beat1: data = rd val sWrite = 2.U(width.W) val sRelResp = 3.U(width.W) val sUnbusyAck = 4.U(width.W) val MAX_BEATS = 3 } class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle { val opcode = UInt(ReRoCCProtocol.width.W) val client_id = UInt(params.clientIdBits.W) val manager_id = UInt(params.managerIdBits.W) val data = UInt(64.W) } object ReRoCCMsgFirstLast { def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = { val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val first = beat === 0.U val last = Wire(Bool()) val inst = m.bits.data.asTypeOf(new RoCCInstruction) when (m.fire && first) { max_beat := 0.U if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mInst) { max_beat := inst.xs1 +& inst.xs2 } .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) { max_beat := 1.U } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { max_beat := 1.U } } } last := true.B if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mUStatus) { last := beat === max_beat && !first } .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) { last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat) } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { last := beat === max_beat && !first } } when (m.fire) { beat := beat + 1.U } when (m.fire && last) { max_beat := 0.U beat := 0.U } (first, last, beat) } } class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle { val req = Decoupled(new ReRoCCMsgBundle(params)) val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params))) } case class EmptyParams() object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] { def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = { ReRoCCEdgeParams(pu, pd) } def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle) def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black */) } case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams)))) case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams)))) class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, _), (out, _)) => out.req <> b(in.req) in.resp <> b(out.resp) } } } object ReRoCCBuffer { def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = { val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p)) rerocc_buffer.node } } case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)() File Arbiter.scala: package rerocc.bus import chisel3._ import chisel3.util._ import freechips.rocketchip.util.{HellaLockingArbiter} class ReRoCCMsgArbiter(bundle: ReRoCCBundleParams, arbN: Int, isReq: Boolean) extends HellaLockingArbiter(new ReRoCCMsgBundle(bundle), arbN, false) { when (io.out.fire) { when (!locked) { lockIdx := choice locked := true.B } when (ReRoCCMsgFirstLast(io.out, isReq)._2) { locked := false.B } } } File Arbiters.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters /** A generalized locking RR arbiter that addresses the limitations of the * version in the Chisel standard library */ abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(arbN, Decoupled(typ.cloneType))) val out = Decoupled(typ.cloneType) }) def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { val n = norm.size VecInit.tabulate(n) { i => Mux(rot < (n - i).U, norm(i.U + rot), norm(rot - (n - i).U)) } } val lockIdx = RegInit(0.U(log2Up(arbN).W)) val locked = RegInit(false.B) val choice = if (rr) { PriorityMux( rotateLeft(VecInit(io.in.map(_.valid)), lockIdx + 1.U), rotateLeft(VecInit((0 until arbN).map(_.U)), lockIdx + 1.U)) } else { PriorityEncoder(io.in.map(_.valid)) } val chosen = Mux(locked, lockIdx, choice) for (i <- 0 until arbN) { io.in(i).ready := io.out.ready && chosen === i.U } io.out.valid := io.in(chosen).valid io.out.bits := io.in(chosen).bits } /** This locking arbiter determines when it is safe to unlock * by peeking at the data */ class HellaPeekingArbiter[T <: Data]( typ: T, arbN: Int, canUnlock: T => Bool, needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B } // the unlock statement takes precedent when (canUnlock(io.out.bits)) { locked := false.B } } } /** This arbiter determines when it is safe to unlock by counting transactions */ class HellaCountingArbiter[T <: Data]( typ: T, arbN: Int, count: Int, val needsLock: Option[T => Bool] = None, rr: Boolean = false) extends HellaLockingArbiter(typ, arbN, rr) { def realNeedsLock(data: T): Bool = needsLock.map(_(data)).getOrElse(true.B) // if count is 1, you should use a non-locking arbiter require(count > 1, "CountingArbiter cannot have count <= 1") val lock_ctr = Counter(count) when (io.out.fire) { when (!locked && realNeedsLock(io.out.bits)) { lockIdx := choice locked := true.B lock_ctr.inc() } when (locked) { when (lock_ctr.inc()) { locked := false.B } } } } /** This arbiter preserves the order of responses */ class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) (implicit p: Parameters) extends Module { val io = IO(new Bundle { val in_req = Flipped(Vec(n, Decoupled(reqTyp))) val in_resp = Vec(n, Decoupled(respTyp)) val out_req = Decoupled(reqTyp) val out_resp = Flipped(Decoupled(respTyp)) }) if (n > 1) { val route_q = Module(new Queue(UInt(log2Up(n).W), 2)) val req_arb = Module(new RRArbiter(reqTyp, n)) req_arb.io.in <> io.in_req val req_helper = DecoupledHelper( req_arb.io.out.valid, route_q.io.enq.ready, io.out_req.ready) io.out_req.bits := req_arb.io.out.bits io.out_req.valid := req_helper.fire(io.out_req.ready) route_q.io.enq.bits := req_arb.io.chosen route_q.io.enq.valid := req_helper.fire(route_q.io.enq.ready) req_arb.io.out.ready := req_helper.fire(req_arb.io.out.valid) val resp_sel = route_q.io.deq.bits val resp_ready = io.in_resp(resp_sel).ready val resp_helper = DecoupledHelper( resp_ready, route_q.io.deq.valid, io.out_resp.valid) val resp_valid = resp_helper.fire(resp_ready) for (i <- 0 until n) { io.in_resp(i).bits := io.out_resp.bits io.in_resp(i).valid := resp_valid && resp_sel === i.U } route_q.io.deq.ready := resp_helper.fire(route_q.io.deq.valid) io.out_resp.ready := resp_helper.fire(io.out_resp.valid) } else { io.out_req <> io.in_req.head io.in_resp.head <> io.out_resp } }

module ReRoCCMsgArbiter_6( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_opcode, // @[Arbiters.scala:14:14] input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14] input [2:0] io_in_0_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14] output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_manager_id, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_opcode_0 = io_in_0_bits_opcode; // @[Arbiter.scala:7:7] wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7] wire [2:0] io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7] wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7] wire _io_in_0_ready_T = 1'h1; // @[Arbiters.scala:40:46] wire chosen = 1'h0; // @[Arbiters.scala:37:19] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_out_valid_WIRE = 1'h0; wire _io_out_bits_WIRE = 1'h0; wire io_out_valid_0 = io_in_0_valid_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_opcode_0 = io_in_0_bits_opcode_0; // @[Arbiter.scala:7:7] wire [3:0] io_out_bits_client_id_0 = io_in_0_bits_client_id_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_manager_id_0 = io_in_0_bits_manager_id_0; // @[Arbiter.scala:7:7] wire [63:0] io_out_bits_data_0 = io_in_0_bits_data_0; // @[Arbiter.scala:7:7] assign _io_in_0_ready_T_1 = io_out_ready_0; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[Arbiter.scala:7:7] reg locked; // @[Arbiters.scala:27:23] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] reg [1:0] beat; // @[Protocol.scala:54:23] reg [1:0] max_beat; // @[Protocol.scala:55:27] wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22] wire last; // @[Protocol.scala:57:20] wire [6:0] _inst_T_7; // @[Protocol.scala:58:36] wire [4:0] _inst_T_6; // @[Protocol.scala:58:36] wire [4:0] _inst_T_5; // @[Protocol.scala:58:36] wire _inst_T_4; // @[Protocol.scala:58:36] wire _inst_T_3; // @[Protocol.scala:58:36] wire _inst_T_2; // @[Protocol.scala:58:36] wire [4:0] _inst_T_1; // @[Protocol.scala:58:36] wire [6:0] _inst_T; // @[Protocol.scala:58:36] wire [6:0] inst_funct; // @[Protocol.scala:58:36] wire [4:0] inst_rs2; // @[Protocol.scala:58:36] wire [4:0] inst_rs1; // @[Protocol.scala:58:36] wire inst_xd; // @[Protocol.scala:58:36] wire inst_xs1; // @[Protocol.scala:58:36] wire inst_xs2; // @[Protocol.scala:58:36] wire [4:0] inst_rd; // @[Protocol.scala:58:36] wire [6:0] inst_opcode; // @[Protocol.scala:58:36] wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36] assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36] assign inst_opcode = _inst_T; // @[Protocol.scala:58:36] assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36] assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36] assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36] assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36] assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36] assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36] assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36] assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36] assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36] assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36] assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36] assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36] assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36] assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36] wire [1:0] _max_beat_T = {1'h0, inst_xs1} + {1'h0, inst_xs2}; // @[Protocol.scala:58:36, :63:32] wire _GEN = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :77:22] wire _last_T; // @[Protocol.scala:77:22] assign _last_T = _GEN; // @[Protocol.scala:77:22] wire _last_T_6; // @[Protocol.scala:79:57] assign _last_T_6 = _GEN; // @[Protocol.scala:77:22, :79:57] wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :77:38] wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:77:{22,35,38}] wire _last_T_3 = ~inst_xs1; // @[Protocol.scala:58:36, :79:28] wire _last_T_4 = ~inst_xs2; // @[Protocol.scala:58:36, :79:41] wire _last_T_5 = _last_T_3 & _last_T_4; // @[Protocol.scala:79:{28,38,41}] wire _last_T_7 = first ? _last_T_5 : _last_T_6; // @[Protocol.scala:56:22, :79:{20,38,57}] assign last = io_out_bits_opcode_0 == 3'h2 ? _last_T_2 : io_out_bits_opcode_0 != 3'h1 | _last_T_7; // @[Protocol.scala:57:20, :74:10, :76:{27,56}, :77:{14,35}, :78:{34,60}, :79:{14,20}, :87:34] wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Protocol.scala:54:23, :87:34] wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34] wire _T_9 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Arbiter.scala:7:7] if (reset) begin // @[Arbiter.scala:7:7] locked <= 1'h0; // @[Arbiters.scala:27:23] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Arbiter.scala:7:7] if (_T_9) // @[Decoupled.scala:51:35] locked <= ~last; // @[Arbiters.scala:27:23] if (_T_9 & last) begin // @[Decoupled.scala:51:35] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Protocol.scala:88:18] if (_T_9) // @[Decoupled.scala:51:35] beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34] if (_T_9 & first) // @[Decoupled.scala:51:35] max_beat <= io_out_bits_opcode_0 == 3'h1 ? _max_beat_T : {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Protocol.scala:55:27, :60:16, :62:{29,55}, :63:{20,32}, :64:{36,65}, :65:20, :87:34] end end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7] assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7] assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7] assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_89( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_71( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulFullRawFN_7( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_63( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object consts { /*------------------------------------------------------------------------ | For rounding to integer values, rounding mode 'odd' rounds to minimum | magnitude instead, same as 'minMag'. *------------------------------------------------------------------------*/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }

module RecFNToRecFN_261( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23] .io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23] .io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RecFNToRecFN.scala:72:19] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid || io.clear || io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 || rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_||_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_||_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_||_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready || agen_ready || dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }

module IssueSlot_24( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen_0 = io_in_uop_bits_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen_0 = io_in_uop_bits_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File L2MemHelperLatencyInjection.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import chisel3.reflect.DataMirror import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig, TLBPTWIO, TLB, MStatus, PRV} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.rocket.{RAS} import freechips.rocketchip.tilelink._ class L2MemHelperLatencyInjection(printInfo: String = "", numOutstandingReqs: Int = 32, queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModule { val numOutstandingRequestsAllowed = numOutstandingReqs val tlTagBits = log2Ceil(numOutstandingRequestsAllowed) lazy val module = new L2MemHelperLatencyInjectionModule(this, printInfo, queueRequests, queueResponses, printWriteBytes) val masterNode = TLClientNode(Seq(TLClientPortParameters( Seq(TLClientParameters(name = printInfo, sourceId = IdRange(0, numOutstandingRequestsAllowed))) ))) } class L2MemHelperLatencyInjectionModule(outer: L2MemHelperLatencyInjection, printInfo: String = "", queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModuleImp(outer) with HasCoreParameters with MemoryOpConstants { val io = IO(new Bundle { val userif = Flipped(new L2MemHelperBundle) val latency_inject_cycles = Input(UInt(64.W)) val sfence = Input(Bool()) val ptw = new TLBPTWIO val status = Flipped(Valid(new MStatus)) }) val (dmem, edge) = outer.masterNode.out.head val request_input = Wire(Decoupled(new L2ReqInternal)) if (!queueRequests) { request_input <> io.userif.req } else { val requestQueue = Module(new Queue(new L2ReqInternal, 4)) request_input <> requestQueue.io.deq requestQueue.io.enq <> io.userif.req } val response_output = Wire(Decoupled(new L2RespInternal)) if (!queueResponses) { io.userif.resp <> response_output } else { val responseQueue = Module(new Queue(new L2RespInternal, 4)) responseQueue.io.enq <> response_output io.userif.resp <> responseQueue.io.deq } val status = Reg(new MStatus) when (io.status.valid) { CompressAccelLogger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, PRV.M.U) status := io.status.bits } val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), p(CompressAccelTLB).get)(edge, p)) tlb.io.req.valid := request_input.valid tlb.io.req.bits.vaddr := request_input.bits.addr tlb.io.req.bits.size := request_input.bits.size tlb.io.req.bits.cmd := request_input.bits.cmd tlb.io.req.bits.passthrough := false.B val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss tlb.io.req.bits.prv := DontCare tlb.io.req.bits.v := DontCare tlb.io.sfence.bits.hv := DontCare tlb.io.sfence.bits.hg := DontCare io.ptw <> tlb.io.ptw tlb.io.ptw.status := status tlb.io.sfence.valid := io.sfence tlb.io.sfence.bits.rs1 := false.B tlb.io.sfence.bits.rs2 := false.B tlb.io.sfence.bits.addr := 0.U tlb.io.sfence.bits.asid := 0.U tlb.io.kill := false.B val outstanding_req_addr = Module(new Queue(new L2InternalTracking, outer.numOutstandingRequestsAllowed * 4)) val tags_for_issue_Q = Module(new Queue(UInt(outer.tlTagBits.W), outer.numOutstandingRequestsAllowed * 2)) tags_for_issue_Q.io.enq.valid := false.B tags_for_issue_Q.io.enq.bits := DontCare val tags_init_reg = RegInit(0.U((outer.tlTagBits+1).W)) when (tags_init_reg =/= (outer.numOutstandingRequestsAllowed).U) { tags_for_issue_Q.io.enq.bits := tags_init_reg tags_for_issue_Q.io.enq.valid := true.B when (tags_for_issue_Q.io.enq.ready) { CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) tags_init_reg := tags_init_reg + 1.U } } val addr_mask_check = (1.U(64.W) << request_input.bits.size) - 1.U val assertcheck = RegNext((!request_input.valid) || ((request_input.bits.addr & addr_mask_check) === 0.U)) when (!assertcheck) { CompressAccelLogger.logInfo(printInfo + " L2IF: access addr must be aligned to write width\n") } assert(assertcheck, printInfo + " L2IF: access addr must be aligned to write width\n") val global_memop_accepted = RegInit(0.U(64.W)) when (io.userif.req.fire) { global_memop_accepted := global_memop_accepted + 1.U } val global_memop_sent = RegInit(0.U(64.W)) val global_memop_ackd = RegInit(0.U(64.W)) val global_memop_resp_to_user = RegInit(0.U(64.W)) io.userif.no_memops_inflight := global_memop_accepted === global_memop_ackd val free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) < (1 << outer.tlTagBits).U val assert_free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) <= (1 << outer.tlTagBits).U when (!assert_free_outstanding_op_slots) { CompressAccelLogger.logInfo(printInfo + " L2IF: Too many outstanding requests for tag count.\n") } assert(assert_free_outstanding_op_slots, printInfo + " L2IF: Too many outstanding requests for tag count.\n") when (request_input.fire) { global_memop_sent := global_memop_sent + 1.U } val sendtag = tags_for_issue_Q.io.deq.bits val cur_cycle = RegInit(0.U(64.W)) cur_cycle := cur_cycle + 1.U val release_cycle_q_depth = 2 * outer.numOutstandingRequestsAllowed val request_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth)) // val req_release_cycle_q = Module(new Queue(UInt(64.W), release_cycle_q_depth, flow=true)) // val req_q = Module(new Queue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth, flow=true)) // req_release_cycle_q.io.enq.bits := cur_cycle + io.latency_inject_cycles request_latency_injection_q.io.latency_cycles := io.latency_inject_cycles request_latency_injection_q.io.enq.bits := DontCare when (request_input.bits.cmd === M_XRD) { val (legal, bundle) = edge.Get(fromSource=sendtag, toAddress=tlb.io.resp.paddr, lgSize=request_input.bits.size) request_latency_injection_q.io.enq.bits := bundle // dmem.a.bits := bundle } .elsewhen (request_input.bits.cmd === M_XWR) { val (legal, bundle) = edge.Put(fromSource=sendtag, toAddress=tlb.io.resp.paddr, lgSize=request_input.bits.size, data=request_input.bits.data << ((request_input.bits.addr(4, 0) << 3))) request_latency_injection_q.io.enq.bits := bundle // dmem.a.bits := bundle } .elsewhen (request_input.valid) { CompressAccelLogger.logInfo(printInfo + " ERR") assert(false.B, "ERR") } val tl_resp_queues = Seq.fill(outer.numOutstandingRequestsAllowed)( Module(new Queue(new L2RespInternal, 4, flow=true)).io) // val current_request_tag_has_response_space = tl_resp_queues(tags_for_issue_Q.io.deq.bits).enq.ready val current_request_tag_has_response_space = tl_resp_queues.zipWithIndex.map({ case (q, idx) => q.enq.ready && (idx.U === tags_for_issue_Q.io.deq.bits) }).reduce(_ || _) val fire_req = DecoupledHelper( request_input.valid, request_latency_injection_q.io.enq.ready, tlb_ready, outstanding_req_addr.io.enq.ready, free_outstanding_op_slots, tags_for_issue_Q.io.deq.valid, current_request_tag_has_response_space ) outstanding_req_addr.io.enq.bits.addrindex := request_input.bits.addr & 0x1F.U outstanding_req_addr.io.enq.bits.tag := sendtag request_latency_injection_q.io.enq.valid := fire_req.fire(request_latency_injection_q.io.enq.ready) request_input.ready := fire_req.fire(request_input.valid) outstanding_req_addr.io.enq.valid := fire_req.fire(outstanding_req_addr.io.enq.ready) tags_for_issue_Q.io.deq.ready := fire_req.fire(tags_for_issue_Q.io.deq.valid) dmem.a <> request_latency_injection_q.io.deq when (dmem.a.fire) { when (request_input.bits.cmd === M_XRD) { CompressAccelLogger.logInfo(printInfo + " L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, sendtag) } } when (fire_req.fire) { when (request_input.bits.cmd === M_XWR) { CompressAccelLogger.logCritical(printInfo + " L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, sendtag) if (printWriteBytes) { for (i <- 0 until 32) { when (i.U < (1.U << request_input.bits.size)) { CompressAccelLogger.logInfo("WRITE_BYTE ADDR: 0x%x BYTE: 0x%x " + printInfo + "\n", request_input.bits.addr + i.U, (request_input.bits.data >> (i*8).U)(7, 0)) } } } } } val response_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleD](dmem.d.bits), release_cycle_q_depth)) response_latency_injection_q.io.latency_cycles := io.latency_inject_cycles response_latency_injection_q.io.enq <> dmem.d // val selectQready = tl_resp_queues(response_latency_injection_q.io.deq.bits.source).enq.ready val selectQready = tl_resp_queues.zipWithIndex.map({ case(q, idx) => q.enq.ready && (idx.U === response_latency_injection_q.io.deq.bits.source) }).reduce(_ || _) val fire_actual_mem_resp = DecoupledHelper( selectQready, response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready ) when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready)) { tags_for_issue_Q.io.enq.valid := true.B tags_for_issue_Q.io.enq.bits := response_latency_injection_q.io.deq.bits.source } when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready) && tags_for_issue_Q.io.enq.valid) { CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) } response_latency_injection_q.io.deq.ready := fire_actual_mem_resp.fire(response_latency_injection_q.io.deq.valid) for (i <- 0 until outer.numOutstandingRequestsAllowed) { tl_resp_queues(i).enq.valid := fire_actual_mem_resp.fire(selectQready) && (response_latency_injection_q.io.deq.bits.source === i.U) tl_resp_queues(i).enq.bits.data := response_latency_injection_q.io.deq.bits.data } // val currentQueue = tl_resp_queues(outstanding_req_addr.io.deq.bits.tag) // val queueValid = currentQueue.deq.valid val queueValid = tl_resp_queues.zipWithIndex.map({ case(q, idx) => q.deq.valid && (idx.U === outstanding_req_addr.io.deq.bits.tag) }).reduce(_ || _) val fire_user_resp = DecoupledHelper( queueValid, response_output.ready, outstanding_req_addr.io.deq.valid ) // val resultdata = currentQueue.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3) val resultdata = tl_resp_queues.zipWithIndex.map({ case(q, idx) => val is_current_q = (idx.U === outstanding_req_addr.io.deq.bits.tag) val data = Wire(q.deq.bits.data.cloneType) when (is_current_q) { data := q.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3) } .otherwise { data := 0.U } data }).reduce(_ | _) response_output.bits.data := resultdata response_output.valid := fire_user_resp.fire(response_output.ready) outstanding_req_addr.io.deq.ready := fire_user_resp.fire(outstanding_req_addr.io.deq.valid) for (i <- 0 until outer.numOutstandingRequestsAllowed) { tl_resp_queues(i).deq.ready := fire_user_resp.fire(queueValid) && (outstanding_req_addr.io.deq.bits.tag === i.U) } when (dmem.d.fire) { when (edge.hasData(dmem.d.bits)) { CompressAccelLogger.logInfo(printInfo + " L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", dmem.d.bits.data, global_memop_ackd, dmem.d.bits.source) } .otherwise { CompressAccelLogger.logInfo(printInfo + " L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, dmem.d.bits.source) } } when (response_output.fire) { CompressAccelLogger.logInfo(printInfo + " L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) } when (response_latency_injection_q.io.deq.fire) { global_memop_ackd := global_memop_ackd + 1.U } when (response_output.fire) { global_memop_resp_to_user := global_memop_resp_to_user + 1.U } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } def logCritical(format: String, args: Bits*)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_*)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_*)) } } def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) { } } object CompressAccelParams { } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File annotations.scala: // See LICENSE for license details. package midas.targetutils import chisel3.{ dontTouch, fromBooleanToLiteral, when, Bits, Bool, Clock, Data, MemBase, Module, Printable, RegNext, Reset, UInt, Wire, WireDefault, } import chisel3.printf.Printf import chisel3.experimental.{annotate, requireIsHardware, BaseModule, ChiselAnnotation} import firrtl.RenameMap import firrtl.annotations.{ Annotation, ComponentName, HasSerializationHints, InstanceTarget, ModuleTarget, ReferenceTarget, SingleTargetAnnotation, } /** These are consumed by [[midas.passes.AutoILATransform]] to directly instantiate an ILA at the top of simulator's * design hierarchy (the PlatformShim level). */ case class FpgaDebugAnnotation(target: Data) extends ChiselAnnotation { def toFirrtl = FirrtlFpgaDebugAnnotation(target.toNamed) } case class FirrtlFpgaDebugAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] { def duplicate(n: ComponentName) = this.copy(target = n) } object FpgaDebug { def apply(targets: Data*): Unit = { targets.foreach { requireIsHardware(_, "Target passed to FpgaDebug:") } targets.map({ t => annotate(FpgaDebugAnnotation(t)) }) } } private[midas] class ReferenceTargetRenamer(renames: RenameMap) { // TODO: determine order for multiple renames, or just check of == 1 rename? def exactRename(rt: ReferenceTarget): ReferenceTarget = { val renameMatches = renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) assert( renameMatches.length <= 1, s"${rt} should be renamed exactly once (or not at all). Suggested renames: ${renameMatches}", ) renameMatches.headOption.getOrElse(rt) } def apply(rt: ReferenceTarget): Seq[ReferenceTarget] = { renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt }) } } private[midas] case class SynthPrintfAnnotation( target: ReferenceTarget ) extends firrtl.annotations.SingleTargetAnnotation[ReferenceTarget] { def duplicate(newTarget: ReferenceTarget) = this.copy(newTarget) } object SynthesizePrintf { /** Annotates a chisel printf as a candidate for synthesis. The printf is only synthesized if Printf synthesis is * enabled in Golden Gate. * * See: https://docs.fires.im/en/stable/search.html?q=Printf+Synthesis&check_keywords=yes&area=default * * @param printf * The printf statement to be synthesized. * * @return * The original input, so that this annotator may be applied inline if desired. */ def apply(printf: Printf): Printf = { annotate(new ChiselAnnotation { def toFirrtl = SynthPrintfAnnotation(printf.toTarget) }) printf } private def generateAnnotations(format: String, args: Seq[Bits], name: Option[String]): Printable = { Module.currentModule.getOrElse(throw new RuntimeException("Cannot annotate a printf outside of a Module")) // To preserve the behavior of the printf parameter annotator, generate a // secondary printf and annotate that, instead of the user's printf, which // will be given an empty string. This will be removed with the apply methods in 1.15. val printf = SynthesizePrintf(chisel3.printf(Printable.pack(format, args: _*))) name.foreach { n => printf.suggestName(n) } Printable.pack("") } /** Annotates* a printf by intercepting the parameters to a chisel printf, and returning a printable. As a side * effect, this function generates a ChiselSynthPrintfAnnotation with the format string and references to each of the * args. * * *Note: this isn't actually annotating the statement but instead the arguments. This is a vestige from earlier * versions of chisel / firrtl in which print statements were unnamed, and thus not referenceable from annotations. * * @param format * The format string for the printf * @param args * Hardware references to populate the format string. */ @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(format: String, args: Bits*): Printable = generateAnnotations(format, args, None) /** Like the other apply method, but provides an optional name which can be used by synthesized hardware / bridge. * Generally, users deploy the nameless form. * * @param name * A descriptive name for this printf instance. * @param format * The format string for the printf * @param args * Hardware references to populate the format string. */ @deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14") def apply(name: String, format: String, args: Bits*): Printable = generateAnnotations(format, args, Some(name)) } /** A mixed-in ancestor trait for all FAME annotations, useful for type-casing. */ trait FAMEAnnotation { this: Annotation => } /** This labels an instance so that it is extracted as a separate FAME model. */ case class FAMEModelAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlFAMEModelAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlFAMEModelAnnotation(parent.instOf(target.instanceName, target.name)) } } case class FirrtlFAMEModelAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /** This specifies that the module should be automatically multi-threaded (Chisel annotator). */ case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends ChiselAnnotation { def toFirrtl: FirrtlEnableModelMultiThreadingAnnotation = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) FirrtlEnableModelMultiThreadingAnnotation(parent.instOf(target.instanceName, target.name)) } } /** This specifies that the module should be automatically multi-threaded (FIRRTL annotation). */ case class FirrtlEnableModelMultiThreadingAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } /** This labels a target Mem so that it is extracted and replaced with a separate model. */ case class MemModelAnnotation[T <: Data](target: MemBase[T]) extends ChiselAnnotation { def toFirrtl = FirrtlMemModelAnnotation(target.toNamed.toTarget) } case class FirrtlMemModelAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] { def duplicate(rt: ReferenceTarget) = this.copy(target = rt) } case class ExcludeInstanceAssertsAnnotation(target: (String, String)) extends firrtl.annotations.NoTargetAnnotation { def duplicate(n: (String, String)) = this.copy(target = n) } // TODO: Actually use a real target and not strings. object ExcludeInstanceAsserts { def apply(target: (String, String)): ChiselAnnotation = new ChiselAnnotation { def toFirrtl = ExcludeInstanceAssertsAnnotation(target) } } sealed trait PerfCounterOpType object PerfCounterOps { /** Takes the annotated UInt and adds it to an accumulation register generated in the bridge */ case object Accumulate extends PerfCounterOpType /** Takes the annotated UInt and exposes it directly to the driver NB: Fields longer than 64b are not supported, and * must be divided into smaller segments that are sepearate annotated */ case object Identity extends PerfCounterOpType } /** AutoCounter annotations. Do not emit the FIRRTL annotations unless you are writing a target transformation, use the * Chisel-side [[PerfCounter]] object instead. */ case class AutoCounterFirrtlAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: ReferenceTarget, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, coverGenerated: Boolean = false, ) extends firrtl.annotations.Annotation with HasSerializationHints { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = renamer.exactRename(reset) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } // The AutoCounter tranform will reject this annotation if it's not enclosed def shouldBeIncluded(modList: Seq[String]): Boolean = !coverGenerated || modList.contains(target.module) def enclosingModule(): String = target.module def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, enclosingModule()) def typeHints: Seq[Class[_]] = Seq(opType.getClass) } case class AutoCounterCoverModuleFirrtlAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation { def duplicate(n: ModuleTarget) = this.copy(target = n) } case class AutoCounterCoverModuleAnnotation(target: ModuleTarget) extends ChiselAnnotation { def toFirrtl = AutoCounterCoverModuleFirrtlAnnotation(target) } object PerfCounter { private def emitAnnotation( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType, ): Unit = { requireIsHardware(target, "Target passed to PerfCounter:") requireIsHardware(clock, "Clock passed to PerfCounter:") requireIsHardware(reset, "Reset passed to PerfCounter:") annotate(new ChiselAnnotation { def toFirrtl = AutoCounterFirrtlAnnotation(target.toTarget, clock.toTarget, reset.toTarget, label, description, opType) }) } /** Labels a signal as an event for which an host-side counter (an "AutoCounter") should be generated). Events can be * multi-bit to encode multiple occurances in a cycle (e.g., the number of instructions retired in a superscalar * processor). NB: Golden Gate will not generate the coutner unless AutoCounter is enabled in your the platform * config. See the docs.fires.im for end-to-end usage information. * * @param target * The number of occurances of the event (in the current cycle) * * @param clock * The clock to which this event is sychronized. * * @param reset * If the event is asserted while under the provide reset, it is not counted. TODO: This should be made optional. * * @param label * A verilog-friendly identifier for the event signal * * @param description * A human-friendly description of the event. * * @param opType * Defines how the bridge should be aggregated into a performance counter. */ def apply( target: UInt, clock: Clock, reset: Reset, label: String, description: String, opType: PerfCounterOpType = PerfCounterOps.Accumulate, ): Unit = emitAnnotation(target, clock, reset, label, description, opType) /** A simplified variation of the full apply method above that uses the implicit clock and reset. */ def apply(target: UInt, label: String, description: String): Unit = emitAnnotation(target, Module.clock, Module.reset, label, description, PerfCounterOps.Accumulate) /** Passes the annotated UInt through to the driver without accumulation. Use cases: * - Custom accumulation / counting logic not supported by the driver * - Providing runtime metadata along side standard accumulation registers * * Note: Under reset, the passthrough value is set to 0. This keeps event handling uniform in the transform. */ def identity(target: UInt, label: String, description: String): Unit = { require( target.getWidth <= 64, s"""|PerfCounter.identity can only accept fields <= 64b wide. Provided target for label: | $label |was ${target.getWidth}b.""".stripMargin, ) emitAnnotation(target, Module.clock, Module.reset, label, description, opType = PerfCounterOps.Identity) } } case class PlusArgFirrtlAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } object PlusArg { private def emitAnnotation( target: BaseModule ): Unit = { annotate(new ChiselAnnotation { def toFirrtl = { val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName) PlusArgFirrtlAnnotation(parent.instOf(target.instanceName, target.name)) } }) } /** Labels a Rocket Chip 'plusarg_reader' module to synthesize. Must be of the type found in * https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/PlusArg.scala * * @param target * The 'plusarg_reader' module to synthesize */ def apply(target: BaseModule): Unit = { emitAnnotation(target) } } // Need serialization utils to be upstreamed to FIRRTL before i can use these. //sealed trait TriggerSourceType //case object Credit extends TriggerSourceType //case object Debit extends TriggerSourceType case class TriggerSourceAnnotation( target: ReferenceTarget, clock: ReferenceTarget, reset: Option[ReferenceTarget], sourceType: Boolean, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) val renamedReset = reset.map(renamer.exactRename) Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } case class TriggerSinkAnnotation( target: ReferenceTarget, clock: ReferenceTarget, ) extends Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedTarget = renamer.exactRename(target) val renamedClock = renamer.exactRename(clock) Seq(this.copy(target = renamedTarget, clock = renamedClock)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) } object TriggerSource { private def annotateTrigger(tpe: Boolean)(target: Bool, reset: Option[Bool]): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val clock = WireDefault(Module.clock) reset.map(dontTouch.apply) requireIsHardware(target, "Target passed to TriggerSource:") reset.foreach { requireIsHardware(_, "Reset passed to TriggerSource:") } annotate(new ChiselAnnotation { def toFirrtl = TriggerSourceAnnotation(target.toNamed.toTarget, clock.toNamed.toTarget, reset.map(_.toTarget), tpe) }) } def annotateCredit = annotateTrigger(true) _ def annotateDebit = annotateTrigger(false) _ /** Methods to annotate a Boolean as a trigger credit or debit. Credits and debits issued while the module's implicit * reset is asserted are not counted. */ def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.asBool)) def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.asBool)) def apply(creditSig: Bool, debitSig: Bool): Unit = { credit(creditSig) debit(debitSig) } /** Variations of the above methods that count credits and debits provided while the implicit reset is asserted. */ def creditEvenUnderReset(credit: Bool): Unit = annotateCredit(credit, None) def debitEvenUnderReset(debit: Bool): Unit = annotateDebit(debit, None) def evenUnderReset(creditSig: Bool, debitSig: Bool): Unit = { creditEvenUnderReset(creditSig) debitEvenUnderReset(debitSig) } /** Level sensitive trigger sources. Implemented using [[credit]] and [[debit]]. Note: This generated hardware in your * target design. * * @param src * Enables the trigger when asserted. If no other credits have been issued since (e.g., a second level-sensitive * enable was asserted), the trigger is disabled when src is desasserted. */ def levelSensitiveEnable(src: Bool): Unit = { val srcLast = RegNext(src) credit(src && !srcLast) debit(!src && srcLast) } } object TriggerSink { /** Marks a bool as receiving the global trigger signal. * * @param target * A Bool node that will be driven with the trigger * * @param noSourceDefault * The value that the trigger signal should take on if no trigger soruces are found in the target. This is a * temporary parameter required while this apply method generates a wire. Otherwise this can be punted to the * target's RTL. */ def apply(target: Bool, noSourceDefault: => Bool = true.B): Unit = { // Hack: Create dummy nodes until chisel-side instance annotations have been improved val targetWire = WireDefault(noSourceDefault) val clock = Module.clock target := targetWire // Both the provided node and the generated one need to be dontTouched to stop // constProp from optimizing the down stream logic(?) dontTouch(target) annotate(new ChiselAnnotation { def toFirrtl = TriggerSinkAnnotation(targetWire.toTarget, clock.toTarget) }) } /** Syntatic sugar for a when context that is predicated by a trigger sink. Example usage: * {{{ * TriggerSink.whenEnabled { * printf(<...>) * } * }}} * * @param noSourceDefault * See [[TriggerSink.apply]]. */ def whenEnabled(noSourceDefault: => Bool = true.B)(elaborator: => Unit): Unit = { val sinkEnable = Wire(Bool()) apply(sinkEnable, noSourceDefault) when(sinkEnable) { elaborator } } } case class RoCCBusyFirrtlAnnotation( target: ReferenceTarget, ready: ReferenceTarget, valid: ReferenceTarget, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renamedReady = renamer.exactRename(ready) val renamedValid = renamer.exactRename(valid) val renamedTarget = renamer.exactRename(target) Seq(this.copy(target = renamedTarget, ready = renamedReady, valid = renamedValid)) } def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module) def enclosingModule(): String = target.module } object MakeRoCCBusyLatencyInsensitive { def apply( target: Bool, ready: Bool, valid: Bool, ): Unit = { requireIsHardware(target, "Target passed to ..:") requireIsHardware(ready, "Ready passed to ..:") requireIsHardware(valid, "Valid passed to ..:") annotate(new ChiselAnnotation { def toFirrtl = RoCCBusyFirrtlAnnotation(target.toNamed.toTarget, ready.toNamed.toTarget, valid.toNamed.toTarget) }) } } case class FirrtlPartWrapperParentAnnotation( target: InstanceTarget ) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation { def targets = Seq(target) def duplicate(n: InstanceTarget) = this.copy(n) } case class FirrtlPortToNeighborRouterIdxAnno( target: ReferenceTarget, extractNeighborIdx: Int, removeNeighborIdx: Int, ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } case class FirrtlCombLogicInsideModuleAnno( target: ReferenceTarget ) extends firrtl.annotations.Annotation with FAMEAnnotation { def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = { val renamer = new ReferenceTargetRenamer(renames) val renameTarget = renamer.exactRename(target) Seq(this.copy(target = renameTarget)) } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module L2MemHelperLatencyInjection_2( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [70:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [70:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_userif_req_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire request_input_bits_cmd = 1'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _a_mask_sub_acc_T_16 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_17 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_18 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_19 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_20 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_21 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_22 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_23 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_24 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_25 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_26 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_27 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_28 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_29 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_30 = 1'h0; // @[Misc.scala:215:38] wire _a_mask_sub_acc_T_31 = 1'h0; // @[Misc.scala:215:38] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_74 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_75 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_76 = 1'h1; // @[Parameters.scala:684:29] wire a_mask_sub_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_8_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_9_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_10_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_11_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_12_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_13_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_14_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_sub_15_1_1 = 1'h1; // @[Misc.scala:215:29] wire a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire a_mask_acc_32 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_33 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_34 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_35 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_36 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_37 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_38 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_39 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_40 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_41 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_42 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_43 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_44 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_45 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_46 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_47 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_48 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_49 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_50 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_51 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_52 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_53 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_54 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_55 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_56 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_57 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_58 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_59 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_60 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_61 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_62 = 1'h1; // @[Misc.scala:215:29] wire a_mask_acc_63 = 1'h1; // @[Misc.scala:215:29] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] a_mask_lo_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] _a_mask_sizeOH_T_2 = 5'h0; // @[OneHot.scala:65:27] wire [4:0] _a_mask_sizeOH_T_5 = 5'h0; // @[OneHot.scala:65:27] wire [2:0] io_userif_req_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] request_input_bits_size = 3'h5; // @[L2MemHelperLatencyInjection.scala:44:27] wire [2:0] a_mask_sizeOH_shiftAmount = 3'h5; // @[OneHot.scala:64:49] wire [2:0] a_mask_sizeOH_shiftAmount_1 = 3'h5; // @[OneHot.scala:64:49] wire [255:0] io_userif_req_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] request_input_bits_data = 256'h0; // @[L2MemHelperLatencyInjection.scala:44:27] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] bundle_mask = 32'hFFFFFFFF; // @[Edges.scala:460:17] wire [31:0] _a_mask_T = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [31:0] bundle_1_mask = 32'hFFFFFFFF; // @[Edges.scala:480:17] wire [31:0] _a_mask_T_1 = 32'hFFFFFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_lo_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] a_mask_hi_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [4:0] a_mask_sizeOH = 5'h1; // @[Misc.scala:202:81] wire [4:0] a_mask_sizeOH_1 = 5'h1; // @[Misc.scala:202:81] wire [7:0] _a_mask_sizeOH_T_1 = 8'h20; // @[OneHot.scala:65:12] wire [7:0] _a_mask_sizeOH_T_4 = 8'h20; // @[OneHot.scala:65:12] wire [4:0] _a_mask_sizeOH_T = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = 5'h5; // @[OneHot.scala:64:31] wire [4:0] _a_mask_sizeOH_T_3 = 5'h5; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = 5'h5; // @[OneHot.scala:64:31] wire [3:0] bundle_size = 4'h5; // @[Edges.scala:460:17] wire [3:0] bundle_1_size = 4'h5; // @[Edges.scala:480:17] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire [70:0] addr_mask_check = 71'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [71:0] _addr_mask_check_T_1 = 72'h1F; // @[L2MemHelperLatencyInjection.scala:108:64] wire [70:0] _addr_mask_check_T = 71'h20; // @[L2MemHelperLatencyInjection.scala:108:36] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [70:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = request_input_bits_addr & 71'h1F; // @[L2MemHelperLatencyInjection.scala:44:27, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_3 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_3; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_3; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_60; // @[Parameters.scala:684:54, :685:42] wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_eq; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_eq_16; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_eq_17; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_eq_18; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_eq_19; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_eq_20; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_eq_21; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_eq_22; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_eq_23; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_eq_24; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_eq_25; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_eq_26; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_eq_27; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_eq_28; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_eq_29; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_eq_30; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [510:0] _T_31 = 511'h0 << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_123; // @[Parameters.scala:684:54, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_eq_32; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_eq_33; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_eq_34; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_eq_35; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_eq_36; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_eq_37; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_eq_38; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_eq_39; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_eq_40; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_eq_41; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_eq_42; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_eq_43; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_eq_44; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_eq_45; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_eq_46; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_eq_47; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_eq_48; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_eq_49; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_eq_50; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_eq_51; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_eq_52; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_eq_53; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_eq_54; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_eq_55; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_eq_56; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_eq_57; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_eq_58; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_eq_59; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_eq_60; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_eq_61; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_eq_62; // @[Misc.scala:214:27, :215:38] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_eq_63; // @[Misc.scala:214:27, :215:38] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 | _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 | _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 | _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 | _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 | _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 | _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 | _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 | _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 | _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 | _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 | _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 | _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 | _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 | _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 | _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 | _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 | _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 | _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 | _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 | _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 | _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 | _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 | _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 | _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 | _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 | _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 | _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 | _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 | _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 | _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 | _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [70:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {66'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 | _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 | _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 | _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 | _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 | _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 | _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 | _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 | _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 | _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 | _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 | _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 | _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 | _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 | _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 | _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 | _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 | _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 | _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 | _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 | _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 | _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 | _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 | _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 | _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 | _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 | _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 | _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 | _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 | _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 | _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 | _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_57 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_57 | _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_57 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_156 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_160 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_163 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_166 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_169 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_172 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_175 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_178 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_181 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_184 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_187 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_190 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_193 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_196 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_199 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_202 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_205 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_208 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_211 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_214 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_217 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_220 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_223 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_226 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_229 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_232 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_235 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_238 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_241 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_244 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_247 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_250 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 | _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 | _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 | _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 | _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 | _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 | _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 | _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 | _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 | _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 | _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 | _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 | _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 | _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 | _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 | _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 | _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 | _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 | _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 | _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 | _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 | _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 | _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 | _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 | _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 | _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 | _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 | _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 | _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 | _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 | _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 | _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_8 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_8; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data | resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T | resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 | resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 | resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 | resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 | resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 | resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 | resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 | resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 | resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 | resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 | resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 | resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 | resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 | resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 | resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 | resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 | resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 | resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 | resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 | resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 | resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 | resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 | resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 | resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 | resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 | resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 | resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 | resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 | resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 | resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_252 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] wire _T_270 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to the following Chisel files. File Frontend.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.tile.{CoreBundle, BaseTile} import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut} import freechips.rocketchip.util.{ClockGate, ShiftQueue, property} import freechips.rocketchip.util.UIntToAugmentedUInt class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { val pc = UInt(vaddrBitsExtended.W) val speculative = Bool() } class FrontendExceptions extends Bundle { val pf = new Bundle { val inst = Bool() } val gf = new Bundle { val inst = Bool() } val ae = new Bundle { val inst = Bool() } } class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) { val btb = new BTBResp val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = Bits(fetchWidth.W) val xcpt = new FrontendExceptions val replay = Bool() } class FrontendPerfEvents extends Bundle { val acquire = Bool() val tlbMiss = Bool() } class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val might_request = Output(Bool()) val clock_enabled = Input(Bool()) val req = Valid(new FrontendReq) val sfence = Valid(new SFenceReq) val resp = Flipped(Decoupled(new FrontendResp)) val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W))) val gpa_is_pte = Input(Bool()) val btb_update = Valid(new BTBUpdate) val bht_update = Valid(new BHTUpdate) val ras_update = Valid(new RASUpdate) val flush_icache = Output(Bool()) val npc = Input(UInt(vaddrBitsExtended.W)) val perf = Input(new FrontendPerfEvents()) val progress = Output(Bool()) } class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) val icache = LazyModule(new ICache(icacheParams, tileId)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new FrontendIO()) val ptw = new TLBPTWIO() val errors = new ICacheErrors } class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) with HasRocketCoreParameters with HasL1ICacheParameters { val io = IO(new FrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0) val icache = outer.icache.module require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg || io.cpu.might_request io.cpu.clock_enabled := clock_en assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "icache_clock_gate") icache.clock := gated_clock icache.io.clock_enabled := clock_en withClock (gated_clock) { // entering gated-clock domain val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages))) val s1_valid = Reg(Bool()) val s2_valid = RegInit(false.B) val s0_fq_has_space = !fq.io.mask(fq.io.mask.getWidth-3) || (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) || (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) val s0_valid = io.cpu.req.valid || s0_fq_has_space s1_valid := s0_valid val s1_pc = Reg(UInt(vaddrBitsExtended.W)) val s1_speculative = Reg(Bool()) val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp) val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken val s2_tlb_resp = Reg(tlb.io.resp.cloneType) val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst val s2_speculative = RegInit(false.B) val s2_partial_insn_valid = RegInit(false.B) val s2_partial_insn = Reg(UInt(coreInstBits.W)) val wrong_path = RegInit(false.B) val s1_base_pc = ~(~s1_pc | (fetchBytes - 1).U) val ntpc = s1_base_pc + fetchBytes.U val predicted_npc = WireDefault(ntpc) val predicted_taken = WireDefault(false.B) val s2_replay = Wire(Bool()) s2_replay := (s2_valid && !fq.io.enq.fire) || RegNext(s2_replay && !s0_valid, true.B) val npc = Mux(s2_replay, s2_pc, predicted_npc) s1_pc := io.cpu.npc // consider RVC fetches across blocks to be non-speculative if the first // part was non-speculative val s0_speculative = if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken else true.B s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative)) val s2_redirect = WireDefault(io.cpu.req.valid) s2_valid := false.B when (!s2_replay) { s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp } val recent_progress_counter_init = 3.U val recent_progress_counter = RegInit(recent_progress_counter_init) val recent_progress = recent_progress_counter > 0.U when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U } when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init } val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !s2_replay tlb.io.req.bits.cmd := M_XRD // Frontend only reads tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth).U tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.req.bits.v := io.ptw.status.v tlb.io.sfence := io.cpu.sfence tlb.io.kill := !s2_valid || s2_kill_speculative_tlb_refill icache.io.req.valid := s0_valid icache.io.req.bits.addr := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_paddr := tlb.io.resp.paddr icache.io.s2_vaddr := s2_pc icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt icache.io.s2_cacheable := s2_tlb_resp.cacheable icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) || (!s2_tlb_resp.miss && icache.io.s2_kill)) fq.io.enq.bits.pc := s2_pc io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) fq.io.enq.bits.replay := (icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) fq.io.enq.bits.btb := s2_btb_resp_bits fq.io.enq.bits.btb.taken := s2_btb_taken fq.io.enq.bits.xcpt := s2_tlb_resp assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill)) when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B } if (usingBTB) { val btb = Module(new BTB) btb.io.flush := false.B btb.io.req.valid := false.B btb.io.req.bits.addr := s1_pc btb.io.btb_update := io.cpu.btb_update btb.io.bht_update := io.cpu.bht_update btb.io.ras_update.valid := false.B btb.io.ras_update.bits := DontCare btb.io.bht_advance.valid := false.B btb.io.bht_advance.bits := DontCare when (!s2_replay) { btb.io.req.valid := !s2_redirect s2_btb_resp_valid := btb.io.resp.valid s2_btb_resp_bits := btb.io.resp.bits } when (btb.io.resp.valid && btb.io.resp.bits.taken) { predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended) predicted_taken := true.B } val force_taken = io.ptw.customCSRs.bpmStatic when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B } when (force_taken) { btb.io.bht_update.valid := false.B } val s2_base_pc = ~(~s2_pc | (fetchBytes-1).U) val taken_idx = Wire(UInt()) val after_idx = Wire(UInt()) val useRAS = WireDefault(false.B) val updateBTB = WireDefault(false.B) // If !prevTaken, ras_update / bht_update is always invalid. taken_idx := DontCare after_idx := DontCare def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = { def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U val prevRVI = prevValid && !insnIsRVC(prevBits) val valid = fq.io.enq.bits.mask(idx) && !prevRVI val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx) val rvc = insnIsRVC(bits) val rviBits = Cat(bits, prevBits) val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0) val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0) val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0) val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15) val rviCall = (rviJALR || rviJump) && rviBits(7) val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL val rvcJump = bits === Instructions.C_J || rvcJAL val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt) val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7) val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U val rvcCall = rvcJAL || rvcJALR val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits)) val predict_taken = s2_btb_resp_bits.bht.taken || force_taken val taken = prevRVI && (rviJump || rviJALR || rviBranch && predict_taken) || valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && predict_taken) val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn) val predictJump = prevRVI && rviJump || valid && rvcJump val predictBranch = predict_taken && (prevRVI && rviBranch || valid && rvcBranch) when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) { // The BTB has predicted that the middle of an RVI instruction is // a branch! Flush the BTB and the pipeline. btb.io.flush := true.B fq.io.enq.bits.replay := true.B wrong_path := true.B ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path") } when (!prevTaken) { taken_idx := idx.U after_idx := (idx + 1).U btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn)) btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call, Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch, CFIType.jump))) when (!s2_btb_taken) { when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) { wrong_path := true.B } when (s2_valid && predictReturn) { useRAS := true.B } when (s2_valid && (predictBranch || predictJump)) { val pc = s2_base_pc | (idx*coreInstBytes).U val npc = if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm) else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm) predicted_npc := npc.asUInt } } when (prevRVI && rviBranch || valid && rvcBranch) { btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path btb.io.bht_advance.bits := s2_btb_resp_bits } when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) { updateBTB := true.B } } if (idx == fetchWidth-1) { when (fq.io.enq.fire) { s2_partial_insn_valid := false.B when (valid && !prevTaken && !rvc) { s2_partial_insn_valid := true.B s2_partial_insn := bits | 0x3.U } } prevTaken || taken } else { scanInsns(idx + 1, valid, bits, prevTaken || taken) } } when (!io.cpu.btb_update.valid) { val fetch_bubble_likely = !fq.io.mask(1) btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U btb.io.btb_update.bits.isValid := true.B btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes)) btb.io.btb_update.bits.pc := s2_base_pc } btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes)) val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B) when (useRAS) { predicted_npc := btb.io.ras_head.bits } when (fq.io.enq.fire && (s2_btb_taken || taken)) { s2_partial_insn_valid := false.B } when (!s2_btb_taken) { when (taken) { fq.io.enq.bits.btb.bridx := taken_idx fq.io.enq.bits.btb.taken := true.B fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U when (fq.io.enq.fire) { s2_redirect := true.B } } } assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0)) when (s2_redirect) { s2_partial_insn_valid := false.B } when (io.cpu.req.valid) { wrong_path := false.B } } io.cpu.resp <> fq.io.deq // supply guest physical address to commit stage val gpa_valid = Reg(Bool()) val gpa = Reg(UInt(vaddrBitsExtended.W)) val gpa_is_pte = Reg(Bool()) when (fq.io.enq.fire && s2_tlb_resp.gf.inst) { when (!gpa_valid) { gpa := s2_tlb_resp.gpa gpa_is_pte := s2_tlb_resp.gpa_is_pte } gpa_valid := true.B } when (io.cpu.req.valid) { gpa_valid := false.B } io.cpu.gpa.valid := gpa_valid io.cpu.gpa.bits := gpa io.cpu.gpa_is_pte := gpa_is_pte // performance events io.cpu.perf.acquire := icache.io.perf.acquire io.cpu.perf.tlbMiss := io.ptw.req.fire io.errors := icache.io.errors // gate the clock clock_en_reg := !rocketParams.clockGate.B || io.cpu.might_request || // chicken bit icache.io.keep_clock_enabled || // I$ miss or ITIM access s1_valid || s2_valid || // some fetch in flight !tlb.io.req.ready || // handling TLB miss !fq.io.mask(fq.io.mask.getWidth-1) // queue not full } // leaving gated-clock domain def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1).U) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc) } /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode } frontend.resetVectorSinkNode := resetVectorNexusNode nPTWPorts += 1 // This should be a None in the case of not having an ITIM address, when we // don't actually use the device that is instantiated in the frontend. private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None } trait HasICacheFrontendModule extends CanHavePTWModule { val outer: HasICacheFrontend ptwPorts += outer.frontend.module.io.ptw } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Frontend( // @[Frontend.scala:82:7] input clock, // @[Frontend.scala:82:7] input reset, // @[Frontend.scala:82:7] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_cpu_might_request, // @[Frontend.scala:85:14] input io_cpu_req_valid, // @[Frontend.scala:85:14] input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14] input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14] input io_cpu_sfence_valid, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14] input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14] input io_cpu_resp_ready, // @[Frontend.scala:85:14] output io_cpu_resp_valid, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14] output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14] output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14] output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14] output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14] input io_cpu_btb_update_valid, // @[Frontend.scala:85:14] input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14] input io_cpu_bht_update_valid, // @[Frontend.scala:85:14] input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14] input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14] input io_cpu_flush_icache, // @[Frontend.scala:85:14] input io_cpu_progress, // @[Frontend.scala:85:14] input io_ptw_req_ready, // @[Frontend.scala:85:14] output io_ptw_req_valid, // @[Frontend.scala:85:14] output io_ptw_req_bits_valid, // @[Frontend.scala:85:14] output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14] output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14] input io_ptw_resp_valid, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14] input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14] input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14] input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14] input io_ptw_status_debug, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_0_value // @[Frontend.scala:85:14] ); wire s2_redirect; // @[Frontend.scala:145:32, :336:26, :337:20, :341:{31,45}] wire [38:0] predicted_npc; // @[Frontend.scala:270:25, :330:19, :331:21] wire updateBTB; // @[Frontend.scala:270:25, :298:125, :299:21] wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40] wire [1:0] after_idx; // @[Frontend.scala:270:25, :272:19] wire taken_taken; // @[Frontend.scala:255:71] wire [38:0] _io_cpu_npc_T; // @[Frontend.scala:186:28] wire fq_io_enq_valid; // @[Frontend.scala:184:{40,52}] wire _btb_io_resp_valid; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21] wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21] wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21] wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21] wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21] wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21] wire _tlb_io_resp_miss; // @[Frontend.scala:105:19] wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19] wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19] wire _tlb_io_ptw_req_valid; // @[Frontend.scala:105:19] wire _fq_io_enq_ready; // @[Frontend.scala:91:64] wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64] wire _icache_io_resp_valid; // @[Frontend.scala:70:26] wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26] wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26] reg s1_valid; // @[Frontend.scala:107:21] reg s2_valid; // @[Frontend.scala:108:25] wire s0_valid = io_cpu_req_valid | ~(_fq_io_mask[2]) | ~(_fq_io_mask[3]) & (~s1_valid | ~s2_valid) | ~(_fq_io_mask[4]) & ~s1_valid & ~s2_valid; // @[Frontend.scala:91:64, :107:21, :108:25, :110:{5,16,40}, :111:{6,17,41,45,55,58,70}, :112:{6,17,41,55}, :113:35] reg [39:0] s1_pc; // @[Frontend.scala:115:18] reg s1_speculative; // @[Frontend.scala:116:27] reg [39:0] s2_pc; // @[Frontend.scala:117:22] reg s2_btb_resp_valid; // @[Frontend.scala:118:44] reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29] reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29] reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29] reg taken_predict_taken; // @[Frontend.scala:119:29] wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40] reg s2_tlb_resp_miss; // @[Frontend.scala:121:24] reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24] wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37] reg s2_speculative; // @[Frontend.scala:123:31] reg s2_partial_insn_valid; // @[Frontend.scala:124:38] reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28] reg wrong_path; // @[Frontend.scala:126:27] wire [39:0] _ntpc_T = {s1_pc[39:2], 2'h0} + 40'h4; // @[Frontend.scala:115:18, :129:25] wire _taken_T_57 = _fq_io_enq_ready & fq_io_enq_valid; // @[Decoupled.scala:51:35] reg s2_replay_REG; // @[Frontend.scala:134:56] wire s2_replay = s2_valid & ~_taken_T_57 | s2_replay_REG; // @[Decoupled.scala:51:35] reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40] wire s2_kill_speculative_tlb_refill = s2_speculative & recent_progress_counter == 2'h0; // @[Frontend.scala:123:31, :155:40, :156:49, :160:{55,58}] wire icache_io_s2_kill = s2_speculative & ~(s2_tlb_resp_cacheable & ~(io_ptw_customCSRs_csrs_0_value[3])) | _s2_xcpt_T; // @[CustomCSRs.scala:46:69] reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29] wire _fq_io_enq_bits_replay_T_5 = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112] assign fq_io_enq_valid = fq_io_enq_valid_REG & s2_valid & (_icache_io_resp_valid | _fq_io_enq_bits_replay_T_5 | ~s2_tlb_resp_miss & icache_io_s2_kill); // @[Frontend.scala:70:26, :108:25, :121:24, :180:71, :184:{29,40,52,77,112,133,137,155}] assign _io_cpu_npc_T = io_cpu_req_valid ? io_cpu_req_bits_pc[39:1] : s2_replay ? s2_pc[39:1] : predicted_npc; // @[Frontend.scala:85:14, :117:22, :134:46, :135:16, :186:28, :270:25, :330:19, :331:21] wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << s2_pc[1]; // @[package.scala:163:13] wire predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:198:21, :213:29] wire [38:0] _GEN = {s2_pc[38:2], 2'h0}; // @[Frontend.scala:117:22, :323:36, :324:33] wire taken_prevRVI = s2_partial_insn_valid & (&(s2_partial_insn[1:0])); // @[Frontend.scala:124:38, :125:28, :233:{39,45}, :234:31] wire taken_valid = _fq_io_enq_bits_mask_T_1[0] & ~taken_prevRVI; // @[Frontend.scala:189:50, :234:31, :235:{38,44,47}] wire taken_rviBranch = s2_partial_insn[6:0] == 7'h63; // @[Frontend.scala:125:28, :239:{30,36}] wire taken_rviJump = s2_partial_insn[6:0] == 7'h6F; // @[Frontend.scala:125:28, :239:30, :240:34] wire taken_rviJALR = s2_partial_insn[6:0] == 7'h67; // @[Frontend.scala:125:28, :239:30, :241:34] wire taken_rviReturn = taken_rviJALR & ~(s2_partial_insn[7]) & {_icache_io_resp_bits_data[3:2], _icache_io_resp_bits_data[0], s2_partial_insn[15]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :125:28, :241:34, :242:{31,34,42,46,66,77}] wire _taken_taken_T = taken_rviJALR | taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30] wire taken_rviCall = _taken_taken_T & s2_partial_insn[7]; // @[Frontend.scala:125:28, :242:42, :243:{30,42}] wire [4:0] _GEN_0 = {_icache_io_resp_bits_data[15:13], _icache_io_resp_bits_data[1:0]}; // @[Frontend.scala:70:26, :244:28] wire taken_rvcBranch = _GEN_0 == 5'h19 | _GEN_0 == 5'h1D; // @[Frontend.scala:244:{28,52,60}] wire taken_rvcJump = {_icache_io_resp_bits_data[15:13], _icache_io_resp_bits_data[1:0]} == 5'h15; // @[Frontend.scala:70:26, :236:37, :244:28, :246:26] wire taken_rvcJR = {_icache_io_resp_bits_data[15:12], _icache_io_resp_bits_data[1:0]} == 6'h22 & ~(|(_icache_io_resp_bits_data[6:2])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,46,53,59}] wire taken_rvcReturn = taken_rvcJR & {_icache_io_resp_bits_data[11:10], _icache_io_resp_bits_data[8:7]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :236:37, :248:46, :249:{29,49,57}] wire taken_rvcJALR = {_icache_io_resp_bits_data[15:12], _icache_io_resp_bits_data[1:0]} == 6'h26 & ~(|(_icache_io_resp_bits_data[6:2])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,53,59}, :250:{26,49,62}] assign taken_taken = taken_prevRVI & (_taken_taken_T | taken_rviBranch & taken_predict_taken) | taken_valid & (taken_rvcJump | taken_rvcJALR | taken_rvcJR | taken_rvcBranch & taken_predict_taken); // @[Frontend.scala:119:29, :234:31, :235:44, :239:36, :243:30, :244:52, :246:26, :248:46, :250:49, :255:{17,40,53,71}, :256:{15,27,38,47,60}] wire taken_predictReturn = _btb_io_ras_head_valid & (taken_prevRVI & taken_rviReturn | taken_valid & taken_rvcReturn); // @[Frontend.scala:198:21, :234:31, :235:44, :242:{31,46}, :249:29, :257:{49,61,74,83}] wire taken_predictJump = taken_prevRVI & taken_rviJump | taken_valid & taken_rvcJump; // @[Frontend.scala:234:31, :235:44, :240:34, :246:26, :258:{33,44,53}] wire _taken_T_19 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_T_20 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75] wire taken_predictBranch = taken_predict_taken & (_taken_T_19 | _taken_T_20); // @[Frontend.scala:119:29, :259:{41,53,66,75}] wire _taken_T_29 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22] wire _taken_T_5 = _taken_T_29 & ~s2_btb_resp_bits_bridx & taken_valid & (&(_icache_io_resp_bits_data[1:0])); // @[Frontend.scala:70:26, :119:29, :233:{39,45}, :235:44, :236:37, :261:{22,43,69,79,88}] wire [32:0] _taken_npc_T_2 = taken_prevRVI ? {{13{_icache_io_resp_bits_data[15]}}, s2_partial_insn[3] ? {_icache_io_resp_bits_data[3:0], s2_partial_insn[15:12], _icache_io_resp_bits_data[4], _icache_io_resp_bits_data[14:5]} : {{8{_icache_io_resp_bits_data[15]}}, s2_partial_insn[7], _icache_io_resp_bits_data[14:9], s2_partial_insn[11:8]}, 1'h0} - 33'h2 : {{22{_icache_io_resp_bits_data[12]}}, _icache_io_resp_bits_data[14] ? {{3{_icache_io_resp_bits_data[12]}}, _icache_io_resp_bits_data[6:5], _icache_io_resp_bits_data[2], _icache_io_resp_bits_data[11:10], _icache_io_resp_bits_data[4:3]} : {_icache_io_resp_bits_data[8], _icache_io_resp_bits_data[10:9], _icache_io_resp_bits_data[6], _icache_io_resp_bits_data[7], _icache_io_resp_bits_data[2], _icache_io_resp_bits_data[11], _icache_io_resp_bits_data[5:3]}, 1'h0}; // @[RocketCore.scala:1341:44, :1343:65, :1345:39, :1347:62, :1349:57, :1355:8] wire [39:0] _taken_npc_T_3 = {s2_pc[39:2], 2'h0} + {{7{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:117:22, :289:{39,44}] wire taken_prevRVI_1 = taken_valid & (&(_icache_io_resp_bits_data[1:0])); // @[Frontend.scala:70:26, :233:{39,45}, :234:31, :235:44, :236:37] wire taken_valid_1 = _fq_io_enq_bits_mask_T_1[1] & ~taken_prevRVI_1; // @[Frontend.scala:189:50, :234:31, :235:{38,44,47}] wire taken_rviBranch_1 = _icache_io_resp_bits_data[6:0] == 7'h63; // @[Frontend.scala:70:26, :239:{30,36}] wire taken_rviJump_1 = _icache_io_resp_bits_data[6:0] == 7'h6F; // @[Frontend.scala:70:26, :239:30, :240:34] wire taken_rviJALR_1 = _icache_io_resp_bits_data[6:0] == 7'h67; // @[Frontend.scala:70:26, :239:30, :241:34] wire taken_rviReturn_1 = taken_rviJALR_1 & ~(_icache_io_resp_bits_data[7]) & {_icache_io_resp_bits_data[19:18], _icache_io_resp_bits_data[16:15]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :241:34, :242:{31,34,42,46,66,77}] wire _taken_taken_T_9 = taken_rviJALR_1 | taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30] wire taken_rviCall_1 = _taken_taken_T_9 & _icache_io_resp_bits_data[7]; // @[Frontend.scala:70:26, :242:42, :243:{30,42}] wire [4:0] _GEN_1 = {_icache_io_resp_bits_data[31:29], _icache_io_resp_bits_data[17:16]}; // @[Frontend.scala:70:26, :244:28] wire taken_rvcBranch_1 = _GEN_1 == 5'h19 | _GEN_1 == 5'h1D; // @[Frontend.scala:244:{28,52,60}] wire taken_rvcJump_1 = {_icache_io_resp_bits_data[31:29], _icache_io_resp_bits_data[17:16]} == 5'h15; // @[Frontend.scala:70:26, :236:37, :244:28, :246:26] wire taken_rvcJR_1 = {_icache_io_resp_bits_data[31:28], _icache_io_resp_bits_data[17:16]} == 6'h22 & ~(|(_icache_io_resp_bits_data[22:18])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,46,53,59}] wire taken_rvcReturn_1 = taken_rvcJR_1 & {_icache_io_resp_bits_data[27:26], _icache_io_resp_bits_data[24:23]} == 4'h1; // @[Frontend.scala:70:26, :82:7, :236:37, :248:46, :249:{29,49,57}] wire taken_rvcJALR_1 = {_icache_io_resp_bits_data[31:28], _icache_io_resp_bits_data[17:16]} == 6'h26 & ~(|(_icache_io_resp_bits_data[22:18])); // @[Frontend.scala:70:26, :236:37, :244:28, :248:{24,53,59}, :250:{26,49,62}] wire taken_taken_1 = taken_prevRVI_1 & (_taken_taken_T_9 | taken_rviBranch_1 & taken_predict_taken) | taken_valid_1 & (taken_rvcJump_1 | taken_rvcJALR_1 | taken_rvcJR_1 | taken_rvcBranch_1 & taken_predict_taken); // @[Frontend.scala:119:29, :234:31, :235:44, :239:36, :243:30, :244:52, :246:26, :248:46, :250:49, :255:{17,40,53,71}, :256:{15,27,38,47,60}] wire taken_predictReturn_1 = _btb_io_ras_head_valid & (taken_prevRVI_1 & taken_rviReturn_1 | taken_valid_1 & taken_rvcReturn_1); // @[Frontend.scala:198:21, :234:31, :235:44, :242:{31,46}, :249:29, :257:{49,61,74,83}] wire taken_predictJump_1 = taken_prevRVI_1 & taken_rviJump_1 | taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:234:31, :235:44, :240:34, :246:26, :258:{33,44,53}] wire _taken_T_48 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_T_49 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75] wire taken_predictBranch_1 = taken_predict_taken & (_taken_T_48 | _taken_T_49); // @[Frontend.scala:119:29, :259:{41,53,66,75}] wire _taken_T_34 = _taken_T_29 & s2_btb_resp_bits_bridx & taken_valid_1 & (&(_icache_io_resp_bits_data[17:16])); // @[Frontend.scala:70:26, :119:29, :233:{39,45}, :235:44, :236:37, :261:{22,43,79,88}] assign after_idx = taken_taken ? 2'h1 : 2'h2; // @[Frontend.scala:255:71, :270:25, :272:19] assign btb_io_ras_update_bits_cfiType = taken_taken ? ((taken_prevRVI ? taken_rviReturn : taken_rvcReturn) ? 2'h3 : (taken_prevRVI ? taken_rviCall : taken_rvcJALR) ? 2'h2 : {1'h0, ~(taken_prevRVI ? taken_rviBranch : taken_rvcBranch)}) : (taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1) ? 2'h3 : (taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcJALR_1) ? 2'h2 : {1'h0, ~(taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1)}; // @[Frontend.scala:234:31, :239:36, :242:{31,46}, :243:42, :244:52, :249:29, :250:49, :255:71, :270:25, :274:{40,46,50}, :275:{46,50}, :276:{46,50}] wire [30:0] _GEN_2 = taken_prevRVI_1 ? {{12{_icache_io_resp_bits_data[31]}}, _icache_io_resp_bits_data[3] ? {_icache_io_resp_bits_data[19:12], _icache_io_resp_bits_data[20], _icache_io_resp_bits_data[30:21]} : {{8{_icache_io_resp_bits_data[31]}}, _icache_io_resp_bits_data[7], _icache_io_resp_bits_data[30:25], _icache_io_resp_bits_data[11:8]}} : {{21{_icache_io_resp_bits_data[28]}}, _icache_io_resp_bits_data[30] ? {{3{_icache_io_resp_bits_data[28]}}, _icache_io_resp_bits_data[22:21], _icache_io_resp_bits_data[18], _icache_io_resp_bits_data[27:26], _icache_io_resp_bits_data[20:19]} : {_icache_io_resp_bits_data[24], _icache_io_resp_bits_data[26:25], _icache_io_resp_bits_data[22], _icache_io_resp_bits_data[23], _icache_io_resp_bits_data[18], _icache_io_resp_bits_data[27], _icache_io_resp_bits_data[21:19]}}; // @[RocketCore.scala:1341:44, :1343:65, :1345:39, :1347:62, :1349:57, :1355:8] wire [39:0] _taken_npc_T_10 = (taken_prevRVI_1 ? {s2_pc[39:2], 2'h2} - 40'h2 : {s2_pc[39:2], 2'h2}) + {{8{_GEN_2[30]}}, _GEN_2, 1'h0}; // @[Frontend.scala:117:22, :234:31, :287:33, :290:{23,36,66,71}] assign updateBTB = ~taken_taken & ~s2_btb_resp_valid & (taken_predictBranch_1 | taken_predictJump_1 | taken_predictReturn_1) | ~s2_btb_resp_valid & (taken_predictBranch | taken_predictJump | taken_predictReturn); // @[Frontend.scala:118:44, :255:71, :257:49, :258:44, :259:41, :270:{13,25}, :298:{15,34,91,106,125}, :299:21] wire taken = taken_taken | taken_taken_1; // @[Frontend.scala:255:71, :311:19] assign predicted_npc = ~taken_taken & ~s2_btb_taken & s2_valid & taken_predictReturn_1 | ~s2_btb_taken & s2_valid & taken_predictReturn ? {1'h0, _btb_io_ras_head_bits[38:1]} : ~taken_taken & ~s2_btb_taken & s2_valid & (taken_predictBranch_1 | taken_predictJump_1) ? _taken_npc_T_10[39:1] : ~s2_btb_taken & s2_valid & (taken_predictBranch | taken_predictJump) ? _taken_npc_T_3[39:1] : predicted_taken ? {_btb_io_resp_bits_target[38], _btb_io_resp_bits_target[38:1]} : _ntpc_T[39:1]; // @[package.scala:132:{15,38}] wire _GEN_3 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34] assign s2_redirect = ~s2_btb_taken & taken & _taken_T_57 | io_cpu_req_valid; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_191( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_347 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File LatencyInjectionQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import freechips.rocketchip.util.DecoupledHelper class LatencyInjectionQueue[T <: Data](data: T, depth: Int) extends Module { val io = IO(new Bundle { val latency_cycles = Input(UInt(64.W)) val enq = Flipped(Decoupled(data)) val deq = Decoupled(data) }) val cur_cycle = RegInit(0.U(64.W)) cur_cycle := cur_cycle + 1.U val queue = Module(new Queue(data, depth)) val release_ready_cycle_q = Module(new Queue(UInt(64.W), depth)) release_ready_cycle_q.io.enq.bits := cur_cycle + io.latency_cycles queue.io.enq.bits := io.enq.bits io.deq.bits := queue.io.deq.bits val enq_fire = DecoupledHelper( queue.io.enq.ready, release_ready_cycle_q.io.enq.ready, io.enq.valid ) queue.io.enq.valid := enq_fire.fire(queue.io.enq.ready) release_ready_cycle_q.io.enq.valid := enq_fire.fire(release_ready_cycle_q.io.enq.ready) io.enq.ready := enq_fire.fire(io.enq.valid) val deq_fire = DecoupledHelper( queue.io.deq.valid, release_ready_cycle_q.io.deq.valid, release_ready_cycle_q.io.deq.bits <= cur_cycle, io.deq.ready ) queue.io.deq.ready := deq_fire.fire(queue.io.deq.valid) release_ready_cycle_q.io.deq.ready := deq_fire.fire(release_ready_cycle_q.io.deq.valid) io.deq.valid := deq_fire.fire(io.deq.ready) }

module LatencyInjectionQueue_35( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14] input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14] input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14] input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14] input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7] wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue64_TLBundleD_a32d256s5k3z4u_13 queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode), .io_deq_bits_param (io_deq_bits_param), .io_deq_bits_size (io_deq_bits_size), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_sink (io_deq_bits_sink), .io_deq_bits_denied (io_deq_bits_denied), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt) ); // @[LatencyInjectionQueue.scala:18:21] Queue64_UInt64_27 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle

module MSHR_3( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File functional-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v4.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import freechips.rocketchip.rocket.ALU._ import boom.v4.common._ import boom.v4.ifu._ import boom.v4.util._ /** * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit */ class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val ftq_info = Vec(2, new FTQInfo) // Need this-pc and next-pc for JALR val pred_data = Bool() val imm_data = UInt(xLen.W) // only used for integer ALU and AGen units } class BrInfoBundle(implicit p: Parameters) extends BoomBundle { val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) } /** * Branch resolution information given from the branch unit */ class BrResolutionInfo(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt(21.W) } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /** * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? */ abstract class FunctionalUnit( val dataWidth: Int, val isAluUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val kill = Input(Bool()) val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new ExeUnitResp(dataWidth))) //val fflags = new ValidIO(new FFlagsResp) val brupdate = Input(new BrUpdateInfo()) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(Valid(new BrResolutionInfo)) else null }) io.resp.bits.fflags.valid := false.B io.resp.bits.fflags.bits := DontCare io.resp.bits.predicated := false.B } /** * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit */ class ALUUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isAluUnit = true, dataWidth = dataWidth) with boom.v4.ifu.HasBoomFrontendParameters with freechips.rocketchip.rocket.constants.ScalarOpConstants { io.req.ready := true.B val uop = io.req.bits.uop // immediate generation val imm_xprlen = io.req.bits.imm_data //ImmGen(uop.imm_packed, uop.imm_sel) // operand 1 select // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.req.bits.ftq_info(0).pc, icBlockBytes) val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) val op1_shamt = Mux(uop.fcn_op === FN_ADD, io.req.bits.uop.pimm(2,1), 0.U) val op1_shl = Mux(uop.fcn_dw === DW_32, // shaddw io.req.bits.rs1_data(31,0), io.req.bits.rs1_data) << op1_shamt val op1_data = MuxLookup(uop.op1_sel, 0.U)(Seq( OP1_RS1 -> io.req.bits.rs1_data, OP1_PC -> Sext(uop_pc, xLen), OP1_RS1SHL -> op1_shl )) // operand 2 select val op2_oh = UIntToOH(Mux(uop.op2_sel(0), // rs1 io.req.bits.rs2_data, imm_xprlen)(log2Ceil(xLen)-1,0)) val op2_data = MuxLookup(uop.op2_sel, 0.U)(Seq( OP2_IMM -> Sext(imm_xprlen, xLen), OP2_IMMC -> io.req.bits.uop.prs1(4,0), OP2_RS2 -> io.req.bits.rs2_data, OP2_NEXT -> Mux(uop.is_rvc, 2.U, 4.U), OP2_RS2OH -> op2_oh, OP2_IMMOH -> op2_oh )) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.fcn_op alu.io.dw := Mux(uop.op1_sel === OP1_RS1SHL, DW_64, uop.fcn_dw) val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu | rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.br_type, PC_PLUS4)( Seq( B_N -> PC_PLUS4, B_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), B_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), B_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), B_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), B_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), B_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), B_J -> PC_BRJMP, B_JR -> PC_JALR )) val is_taken = io.req.valid && (uop.br_type =/= BR_N) && (pc_sel =/= PC_PLUS4) // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && uop.is_jal val is_jalr = io.req.valid && uop.is_jalr val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt val cfi_idx = ((uop.pc_lob ^ Mux(io.req.bits.ftq_info(0).entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (is_br || is_jalr) { when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } when (pc_sel === PC_JALR) { mispredict := (!io.req.bits.ftq_info(1).valid || (io.req.bits.ftq_info(1).pc =/= jalr_target) || !io.req.bits.ftq_info(0).entry.cfi_idx.valid || (io.req.bits.ftq_info(0).entry.cfi_idx.bits =/= cfi_idx)) } } val brinfo = Wire(Valid(new BrResolutionInfo)) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br || is_jalr brinfo.bits.mispredict := mispredict brinfo.bits.uop := uop brinfo.bits.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.bits.taken := is_taken brinfo.bits.pc_sel := pc_sel brinfo.bits.jalr_target := DontCare brinfo.bits.jalr_target := jalr_target brinfo.bits.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.is_mov, io.req.bits.rs2_data, alu.io.out)) io.resp.valid := io.req.valid io.resp.bits.uop := io.req.bits.uop io.resp.bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) io.resp.bits.predicated := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data assert(io.resp.ready) } /** * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. */ class FPUUnit(implicit p: Parameters) extends FunctionalUnit( //numBypassStages = 0, dataWidth = 65, needsFcsr = true) { io.req.ready := true.B val numStages = p(tile.TileKey).core.fpu.get.dfmaLatency val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), numStages)) pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.valid := pipe.io.resp(numStages-1).valid io.resp.bits.uop := pipe.io.resp(numStages-1).bits.uop io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits := fpu.io.resp.bits.fflags.bits } /** * Int to FP conversion functional unit * * @param latency the amount of stages to delay by */ class IntToFPUnit(latency: Int)(implicit p: Parameters) extends FunctionalUnit( //numBypassStages = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val io_req = io.req.bits io.req.ready := true.B val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), latency)) pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate val fp_ctrl = io_req.uop.fp_ctrl val fp_rm = Mux(io_req.uop.fp_rm === 7.U, io.fcsr_rm, io_req.uop.fp_rm) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) <> fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := io_req.uop.fp_typ req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits io.resp.valid := pipe.io.resp(latency-1).valid io.resp.bits.uop := pipe.io.resp(latency-1).bits.uop io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits := ifpu.io.out.bits.exc } /** * Divide functional unit. * * @param dataWidth data to be passed into the functional unit */ class DivUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit(dataWidth = dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) val req = Reg(Valid(new MicroOp())) when (io.req.fire) { req.valid := !IsKilledByBranch(io.brupdate, io.kill, io.req.bits) req.bits := UpdateBrMask(io.brupdate, io.req.bits.uop) } .otherwise { req.valid := !IsKilledByBranch(io.brupdate, io.kill, req.bits) && req.valid req.bits := UpdateBrMask(io.brupdate, req.bits) } when (reset.asBool) { req.valid := false.B } // request div.io.req.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.kill, io.req.bits) div.io.req.bits.dw := io.req.bits.uop.fcn_dw div.io.req.bits.fn := io.req.bits.uop.fcn_op div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready && !req.valid // handle pipeline kills and branch misspeculations div.io.kill := (req.valid && IsKilledByBranch(io.brupdate, io.kill, req.bits)) // response io.resp.valid := div.io.resp.valid && req.valid div.io.resp.ready := io.resp.ready io.resp.valid := div.io.resp.valid && req.valid io.resp.bits.data := div.io.resp.bits.data io.resp.bits.uop := req.bits when (io.resp.fire) { req.valid := false.B } } /** * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit(dataWidth = dataWidth) { io.req.ready := true.B val imul = Module(new PipelinedMultiplier(xLen, numStages)) val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.fcn_op imul.io.req.bits.dw := io.req.bits.uop.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate // response io.resp.valid := pipe.io.resp(numStages-1).valid io.resp.bits.uop := pipe.io.resp(numStages-1).bits.uop io.resp.bits.data := imul.io.resp.bits.data io.resp.bits.predicated := false.B } File micro-op.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.common import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ import org.chipsalliance.cde.config.Parameters abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = Vec(IQ_SZ, Bool()) // which issue unit do we use? val fu_code = Vec(FC_SZ, Bool()) // which functional unit do we use? val iw_issued = Bool() // Was this uop issued last cycle? If so, it can vacate this cycle val iw_issued_partial_agen = Bool() val iw_issued_partial_dgen = Bool() val iw_p1_speculative_child = UInt(aluWidth.W) val iw_p2_speculative_child = UInt(aluWidth.W) // Get the operand off the bypass network, avoid a register read port allocation val iw_p1_bypass_hint = Bool() val iw_p2_bypass_hint = Bool() val iw_p3_bypass_hint = Bool() val dis_col_sel = UInt(coreWidth.W) // If using column-issue ALUs with 1-wide dispatch, which column to issue to? val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) val br_type = UInt(4.W) val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val is_fence = Bool() val is_fencei = Bool() val is_sfence = Bool() val is_amo = Bool() val is_eret = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_rocc = Bool() val is_mov = Bool() // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_rename = Bool() val imm_sel = UInt(IS_N.getWidth.W) val pimm = UInt(immPregSz.W) val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val fp_ctrl = new freechips.rocketchip.tile.FPUCtrlSigs val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) // Predication def is_br = br_type.isOneOf(B_NE, B_EQ, B_GE, B_GEU, B_LT, B_LTU) def is_jal = br_type === B_J def is_jalr = br_type === B_JR def is_sfb_br = br_type =/= B_N && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = br_type === B_N && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() val fcn_dw = Bool() val fcn_op = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_rm = UInt(3.W) val fp_typ = UInt(2.W) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) || is_jalr def starts_bsy = !(is_fence || is_fencei) // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def starts_unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr }

module ALUUnit( // @[functional-unit.scala:133:7] input clock, // @[functional-unit.scala:133:7] input reset, // @[functional-unit.scala:133:7] input io_kill, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [11:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [11:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14] ); wire [63:0] _alu_io_out; // @[functional-unit.scala:173:19] wire io_kill_0 = io_kill; // @[functional-unit.scala:133:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [11:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:133:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:133:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:133:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:133:7] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[functional-unit.scala:234:90] wire [39:0] _block_pc_T = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [39:0] _block_pc_T_1 = 40'hFFFFFFFFFF; // @[util.scala:245:{7,11}] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[util.scala:245:5] wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[util.scala:245:5] wire [39:0] block_pc = 40'h0; // @[util.scala:245:5] wire [3:0] io_req_bits_ftq_info_0_entry_br_mask = 4'h0; // @[functional-unit.scala:105:14, :133:7, :234:35] wire [3:0] io_req_bits_ftq_info_1_entry_br_mask = 4'h0; // @[functional-unit.scala:105:14, :133:7, :234:35] wire [3:0] _cfi_idx_T_2 = 4'h0; // @[functional-unit.scala:105:14, :133:7, :234:35] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 2'h0; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 2'h0; // @[functional-unit.scala:133:7] wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:188:48] wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:133:7] wire _cfi_idx_T = 1'h0; // @[functional-unit.scala:234:77] wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:285:51] wire _io_resp_bits_predicated_T_3 = 1'h0; // @[functional-unit.scala:291:60] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:133:7] wire io_resp_ready = 1'h1; // @[functional-unit.scala:133:7] wire _mispredict_T_1 = 1'h1; // @[functional-unit.scala:245:22] wire _mispredict_T_3 = 1'h1; // @[functional-unit.scala:245:53] wire _mispredict_T_4 = 1'h1; // @[functional-unit.scala:247:22] wire _mispredict_T_5 = 1'h1; // @[functional-unit.scala:246:67] wire _mispredict_T_7 = 1'h1; // @[functional-unit.scala:247:67] wire io_resp_valid_0 = io_req_valid_0; // @[functional-unit.scala:133:7] wire [31:0] io_resp_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [31:0] io_resp_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7, :252:20] wire [39:0] io_resp_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] wire [39:0] brinfo_bits_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [11:0] io_resp_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] wire [11:0] brinfo_bits_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_type_0 = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_type = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfence = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_eret_0 = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_eret = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rocc = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_mov_0 = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_mov = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] wire [5:0] _cfi_idx_T_3 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :234:30] wire [5:0] brinfo_bits_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_imm_rename = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_imm_sel = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_pimm_0 = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_pimm = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7, :252:20] wire [19:0] io_resp_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] wire [19:0] brinfo_bits_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_op1_sel = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_op2_sel = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] io_resp_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] wire [63:0] brinfo_bits_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_fcn_op = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_fp_rm = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_typ = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] jalr_target_base = io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :229:47] wire [63:0] _io_resp_bits_data_T_4; // @[functional-unit.scala:290:27] wire brinfo_valid; // @[functional-unit.scala:252:20] wire brinfo_bits_mispredict; // @[functional-unit.scala:252:20] wire brinfo_bits_taken; // @[functional-unit.scala:252:20] wire [2:0] brinfo_bits_cfi_type; // @[functional-unit.scala:252:20] wire [1:0] brinfo_bits_pc_sel; // @[functional-unit.scala:252:20] wire [39:0] brinfo_bits_jalr_target; // @[functional-unit.scala:252:20] wire [20:0] brinfo_bits_target_offset; // @[functional-unit.scala:252:20] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [11:0] io_brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brinfo_bits_mispredict; // @[functional-unit.scala:133:7] wire io_brinfo_bits_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brinfo_bits_target_offset; // @[functional-unit.scala:133:7] wire io_brinfo_valid; // @[functional-unit.scala:133:7] wire [39:0] _uop_pc_T = {34'h0, io_req_bits_uop_pc_lob_0}; // @[functional-unit.scala:133:7, :150:26] wire [1:0] _uop_pc_T_1 = {io_req_bits_uop_edge_inst_0, 1'h0}; // @[functional-unit.scala:133:7, :150:45] wire [40:0] _uop_pc_T_2 = {1'h0, _uop_pc_T} - {39'h0, _uop_pc_T_1}; // @[functional-unit.scala:150:{26,40,45}] wire [39:0] uop_pc = _uop_pc_T_2[39:0]; // @[functional-unit.scala:150:40] wire _op1_shamt_T = io_req_bits_uop_fcn_op_0 == 5'h0; // @[functional-unit.scala:133:7, :151:34] wire [1:0] _op1_shamt_T_1 = io_req_bits_uop_pimm_0[2:1]; // @[functional-unit.scala:133:7, :151:66] wire [1:0] op1_shamt = _op1_shamt_T ? _op1_shamt_T_1 : 2'h0; // @[functional-unit.scala:151:{22,34,66}] wire _op1_shl_T = ~io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :152:32] wire [31:0] _op1_shl_T_1 = io_req_bits_rs1_data_0[31:0]; // @[functional-unit.scala:133:7, :153:25] wire [63:0] _op1_shl_T_2 = _op1_shl_T ? {32'h0, _op1_shl_T_1} : io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :152:{20,32}, :153:25] wire [66:0] op1_shl = {3'h0, _op1_shl_T_2} << op1_shamt; // @[functional-unit.scala:151:22, :152:20, :153:55] wire _op1_data_T = uop_pc[39]; // @[util.scala:269:46] wire [23:0] _op1_data_T_1 = {24{_op1_data_T}}; // @[util.scala:269:{25,46}] wire [63:0] _op1_data_T_2 = {_op1_data_T_1, uop_pc}; // @[util.scala:269:{20,25}] wire _op1_data_T_3 = io_req_bits_uop_op1_sel_0 == 2'h0; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_4 = _op1_data_T_3 ? io_req_bits_rs1_data_0 : 64'h0; // @[functional-unit.scala:133:7, :155:45] wire _op1_data_T_5 = io_req_bits_uop_op1_sel_0 == 2'h2; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_6 = _op1_data_T_5 ? _op1_data_T_2 : _op1_data_T_4; // @[util.scala:269:20] wire _op1_data_T_7 = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45] wire [66:0] op1_data = _op1_data_T_7 ? op1_shl : {3'h0, _op1_data_T_6}; // @[functional-unit.scala:153:55, :155:45] wire _op2_oh_T = io_req_bits_uop_op2_sel_0[0]; // @[functional-unit.scala:133:7, :162:40] wire [63:0] _op2_oh_T_1 = _op2_oh_T ? io_req_bits_rs2_data_0 : io_req_bits_imm_data_0; // @[functional-unit.scala:133:7, :162:{28,40}] wire [5:0] _op2_oh_T_2 = _op2_oh_T_1[5:0]; // @[functional-unit.scala:162:28, :163:38] wire [63:0] op2_oh = 64'h1 << _op2_oh_T_2; // @[OneHot.scala:58:35] wire [4:0] _op2_data_T = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:133:7, :166:37] wire [2:0] _op2_data_T_1 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:133:7, :168:20] wire _op2_data_T_2 = io_req_bits_uop_op2_sel_0 == 3'h1; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_3 = _op2_data_T_2 ? io_req_bits_imm_data_0 : 64'h0; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_4 = io_req_bits_uop_op2_sel_0 == 3'h4; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_5 = _op2_data_T_4 ? {59'h0, _op2_data_T} : _op2_data_T_3; // @[functional-unit.scala:164:45, :166:37] wire _op2_data_T_6 = io_req_bits_uop_op2_sel_0 == 3'h0; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_7 = _op2_data_T_6 ? io_req_bits_rs2_data_0 : _op2_data_T_5; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_8 = io_req_bits_uop_op2_sel_0 == 3'h3; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_9 = _op2_data_T_8 ? {61'h0, _op2_data_T_1} : _op2_data_T_7; // @[functional-unit.scala:164:45, :168:20] wire _op2_data_T_10 = io_req_bits_uop_op2_sel_0 == 3'h5; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_11 = _op2_data_T_10 ? op2_oh : _op2_data_T_9; // @[OneHot.scala:58:35] wire _op2_data_T_12 = io_req_bits_uop_op2_sel_0 == 3'h6; // @[functional-unit.scala:133:7, :164:45] wire [63:0] op2_data = _op2_data_T_12 ? op2_oh : _op2_data_T_11; // @[OneHot.scala:58:35] wire _alu_io_dw_T = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45, :178:33] wire _alu_io_dw_T_1 = _alu_io_dw_T | io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :178:{20,33}] wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :183:21] wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :184:28] wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22] wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22, :186:20] wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36] wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36, :186:35] wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:185:{22,31,36}] wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:185:{17,31}] wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:184:28, :185:{17,46}] wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:186:{31,35}] wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:186:{20,29,31}] wire br_lt = _br_lt_T_4 | _br_lt_T_8; // @[functional-unit.scala:185:{46,55}, :186:29] wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:183:21, :190:38] wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:190:{37,38}] wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:183:21, :191:37] wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:185:55, :192:38] wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:192:{37,38}] wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:184:28, :193:38] wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:193:{37,38}] wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:185:55, :194:37] wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:184:28, :195:37] wire _pc_sel_T_9 = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _GEN = io_req_bits_uop_br_type_0 == 4'h1; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_11; // @[functional-unit.scala:188:48] assign _pc_sel_T_11 = _GEN; // @[functional-unit.scala:188:48] wire _is_br_T; // @[package.scala:16:47] assign _is_br_T = _GEN; // @[package.scala:16:47] wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:188:48, :190:37] wire _GEN_0 = io_req_bits_uop_br_type_0 == 4'h2; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_13; // @[functional-unit.scala:188:48] assign _pc_sel_T_13 = _GEN_0; // @[functional-unit.scala:188:48] wire _is_br_T_1; // @[package.scala:16:47] assign _is_br_T_1 = _GEN_0; // @[package.scala:16:47] wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:188:48, :191:37] wire _GEN_1 = io_req_bits_uop_br_type_0 == 4'h3; // @[functional-unit.scala:133:7, :188:48, :201:33] wire _pc_sel_T_15; // @[functional-unit.scala:188:48] assign _pc_sel_T_15 = _GEN_1; // @[functional-unit.scala:188:48] wire _is_br_T_2; // @[package.scala:16:47] assign _is_br_T_2 = _GEN_1; // @[package.scala:16:47] wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:188:48, :192:37] wire _GEN_2 = io_req_bits_uop_br_type_0 == 4'h4; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_17; // @[functional-unit.scala:188:48] assign _pc_sel_T_17 = _GEN_2; // @[functional-unit.scala:188:48] wire _is_br_T_3; // @[package.scala:16:47] assign _is_br_T_3 = _GEN_2; // @[package.scala:16:47] wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:188:48, :193:37] wire _GEN_3 = io_req_bits_uop_br_type_0 == 4'h5; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_19; // @[functional-unit.scala:188:48] assign _pc_sel_T_19 = _GEN_3; // @[functional-unit.scala:188:48] wire _is_br_T_4; // @[package.scala:16:47] assign _is_br_T_4 = _GEN_3; // @[package.scala:16:47] wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:188:48, :194:37] wire _GEN_4 = io_req_bits_uop_br_type_0 == 4'h6; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_21; // @[functional-unit.scala:188:48] assign _pc_sel_T_21 = _GEN_4; // @[functional-unit.scala:188:48] wire _is_br_T_5; // @[package.scala:16:47] assign _is_br_T_5 = _GEN_4; // @[package.scala:16:47] wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:188:48, :195:37] wire _GEN_5 = io_req_bits_uop_br_type_0 == 4'h7; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_23; // @[functional-unit.scala:188:48] assign _pc_sel_T_23 = _GEN_5; // @[functional-unit.scala:188:48] wire _is_jal_T; // @[micro-op.scala:118:34] assign _is_jal_T = _GEN_5; // @[functional-unit.scala:188:48] wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:188:48] wire _GEN_6 = io_req_bits_uop_br_type_0 == 4'h8; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_25; // @[functional-unit.scala:188:48] assign _pc_sel_T_25 = _GEN_6; // @[functional-unit.scala:188:48] wire _is_jalr_T; // @[micro-op.scala:119:34] assign _is_jalr_T = _GEN_6; // @[functional-unit.scala:188:48] wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:188:48] assign brinfo_bits_pc_sel = pc_sel; // @[functional-unit.scala:188:48, :252:20] wire _is_taken_T = io_req_bits_uop_br_type_0 != 4'h3; // @[functional-unit.scala:133:7, :201:33] wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:133:7, :200:31, :201:33] wire _is_taken_T_2 = |pc_sel; // @[functional-unit.scala:188:48, :202:28] wire is_taken = _is_taken_T_1 & _is_taken_T_2; // @[functional-unit.scala:200:31, :201:43, :202:28] assign brinfo_bits_taken = is_taken; // @[functional-unit.scala:201:43, :252:20] wire [20:0] _target_offset_T = io_req_bits_imm_data_0[20:0]; // @[functional-unit.scala:133:7, :208:33] wire [20:0] target_offset = _target_offset_T; // @[functional-unit.scala:208:{33,40}] assign brinfo_bits_target_offset = target_offset; // @[functional-unit.scala:208:40, :252:20] wire mispredict; // @[functional-unit.scala:223:28] assign brinfo_bits_mispredict = mispredict; // @[functional-unit.scala:223:28, :252:20] wire _is_br_T_6 = _is_br_T | _is_br_T_1; // @[package.scala:16:47, :81:59] wire _is_br_T_7 = _is_br_T_6 | _is_br_T_2; // @[package.scala:16:47, :81:59] wire _is_br_T_8 = _is_br_T_7 | _is_br_T_3; // @[package.scala:16:47, :81:59] wire _is_br_T_9 = _is_br_T_8 | _is_br_T_4; // @[package.scala:16:47, :81:59] wire _is_br_T_10 = _is_br_T_9 | _is_br_T_5; // @[package.scala:16:47, :81:59] wire _is_br_T_11 = io_req_valid_0 & _is_br_T_10; // @[package.scala:81:59] wire _is_br_T_12 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :225:53] wire is_br = _is_br_T_11 & _is_br_T_12; // @[functional-unit.scala:225:{37,50,53}] wire is_jal = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:133:7, :226:37] wire is_jalr = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:133:7, :227:37] wire [63:0] _jalr_target_xlen_T_3; // @[functional-unit.scala:231:58] wire [63:0] jalr_target_xlen; // @[functional-unit.scala:230:30] wire [63:0] _jalr_target_a_T = jalr_target_xlen; // @[functional-unit.scala:215:16, :230:30] wire [64:0] _jalr_target_xlen_T = {jalr_target_base[63], jalr_target_base} + {{44{target_offset[20]}}, target_offset}; // @[functional-unit.scala:208:40, :229:47, :231:41] wire [63:0] _jalr_target_xlen_T_1 = _jalr_target_xlen_T[63:0]; // @[functional-unit.scala:231:41] wire [63:0] _jalr_target_xlen_T_2 = _jalr_target_xlen_T_1; // @[functional-unit.scala:231:41] assign _jalr_target_xlen_T_3 = _jalr_target_xlen_T_2; // @[functional-unit.scala:231:{41,58}] assign jalr_target_xlen = _jalr_target_xlen_T_3; // @[functional-unit.scala:230:30, :231:58] wire [24:0] jalr_target_a = _jalr_target_a_T[63:39]; // @[functional-unit.scala:215:{16,23}] wire _jalr_target_msb_T = jalr_target_a == 25'h0; // @[functional-unit.scala:215:23, :216:21] wire _jalr_target_msb_T_1 = &jalr_target_a; // @[functional-unit.scala:215:23, :216:34] wire _jalr_target_msb_T_2 = _jalr_target_msb_T | _jalr_target_msb_T_1; // @[functional-unit.scala:216:{21,29,34}] wire _jalr_target_msb_T_3 = jalr_target_xlen[39]; // @[functional-unit.scala:216:46, :230:30] wire _jalr_target_msb_T_4 = jalr_target_xlen[38]; // @[functional-unit.scala:216:62, :230:30] wire _jalr_target_msb_T_5 = ~_jalr_target_msb_T_4; // @[functional-unit.scala:216:{59,62}] wire jalr_target_msb = _jalr_target_msb_T_2 ? _jalr_target_msb_T_3 : _jalr_target_msb_T_5; // @[functional-unit.scala:216:{18,29,46,59}] wire [38:0] _jalr_target_T = jalr_target_xlen[38:0]; // @[functional-unit.scala:217:16, :230:30] wire [39:0] _jalr_target_T_1 = {jalr_target_msb, _jalr_target_T}; // @[functional-unit.scala:216:18, :217:{8,16}] wire [39:0] _jalr_target_T_2 = _jalr_target_T_1; // @[functional-unit.scala:217:8, :232:79] wire [39:0] _jalr_target_T_3 = _jalr_target_T_2 & 40'hFFFFFFFFFE; // @[functional-unit.scala:232:{79,86}] wire [39:0] _jalr_target_T_4 = _jalr_target_T_3; // @[functional-unit.scala:232:86] wire [39:0] jalr_target = _jalr_target_T_4; // @[functional-unit.scala:232:{86,94}] assign brinfo_bits_jalr_target = jalr_target; // @[functional-unit.scala:232:94, :252:20] wire [1:0] cfi_idx = _cfi_idx_T_3[2:1]; // @[functional-unit.scala:234:{30,120}] wire _brinfo_valid_T = is_br | is_jalr; // @[functional-unit.scala:225:50, :227:37, :237:15, :255:34] wire _mispredict_T = ~io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :242:21] wire _mispredict_T_2 = |jalr_target; // @[functional-unit.scala:232:94, :246:50] wire _mispredict_T_6 = |cfi_idx; // @[functional-unit.scala:234:120, :248:66] assign mispredict = _brinfo_valid_T & (pc_sel == 2'h2 | (pc_sel == 2'h1 ? _mispredict_T : ~(|pc_sel) & io_req_bits_uop_taken_0)); // @[functional-unit.scala:133:7, :188:48, :202:28, :223:28, :237:27, :238:{18,32}, :239:18, :241:{18,32}, :242:{18,21}, :244:{18,31}, :245:18, :255:34] assign io_brinfo_valid = brinfo_valid; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_inst = brinfo_bits_uop_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_inst = brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rvc = brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_pc = brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_0 = brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_1 = brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_2 = brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_3 = brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_0 = brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_1 = brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_2 = brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_3 = brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_4 = brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_5 = brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_6 = brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_7 = brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_8 = brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_9 = brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued = brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_agen = brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_dgen = brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_speculative_child = brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_speculative_child = brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_bypass_hint = brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_bypass_hint = brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p3_bypass_hint = brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dis_col_sel = brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_mask = brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_tag = brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_type = brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfb = brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fence = brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fencei = brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfence = brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_amo = brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_eret = brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sys_pc2epc = brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rocc = brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_mov = brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ftq_idx = brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_edge_inst = brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pc_lob = brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_taken = brinfo_bits_uop_taken; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_rename = brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_sel = brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pimm = brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_packed = brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op1_sel = brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op2_sel = brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ldst = brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wen = brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren1 = brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren2 = brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren3 = brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap12 = brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap23 = brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagIn = brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagOut = brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fromint = brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_toint = brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fastpipe = brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fma = brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_div = brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_sqrt = brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wflags = brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_vec = brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rob_idx = brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldq_idx = brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stq_idx = brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rxq_idx = brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pdst = brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1 = brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2 = brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3 = brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred = brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1_busy = brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2_busy = brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3_busy = brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred_busy = brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stale_pdst = brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exception = brinfo_bits_uop_exception; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exc_cause = brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_cmd = brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_size = brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_signed = brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_ldq = brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_stq = brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_unique = brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_flush_on_commit = brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_csr_cmd = brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst_is_rs1 = brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst = brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1 = brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2 = brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs3 = brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dst_rtype = brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1_rtype = brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2_rtype = brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_frs3_en = brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_dw = brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_op = brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_val = brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_rm = brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_typ = brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_pf_if = brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ae_if = brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ma_if = brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_debug_if = brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_xcpt_if = brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_fsrc = brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_tsrc = brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_mispredict = brinfo_bits_mispredict; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_taken = brinfo_bits_taken; // @[functional-unit.scala:133:7, :252:20] wire [2:0] _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:258:36] assign io_brinfo_bits_cfi_type = brinfo_bits_cfi_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_pc_sel = brinfo_bits_pc_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_jalr_target = brinfo_bits_jalr_target; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_target_offset = brinfo_bits_target_offset; // @[functional-unit.scala:133:7, :252:20] assign brinfo_valid = _brinfo_valid_T; // @[functional-unit.scala:252:20, :255:34] wire [2:0] _brinfo_bits_cfi_type_T = {2'h0, is_br}; // @[functional-unit.scala:225:50, :259:36] assign _brinfo_bits_cfi_type_T_1 = is_jalr ? 3'h3 : _brinfo_bits_cfi_type_T; // @[functional-unit.scala:227:37, :258:36, :259:36] assign brinfo_bits_cfi_type = _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:252:20, :258:36] wire _alu_out_T = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _alu_out_T_1 = _alu_out_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _alu_out_T_2 = _alu_out_T_1; // @[micro-op.scala:121:{42,52}] wire [63:0] _alu_out_T_4 = io_req_bits_uop_ldst_is_rs1_0 ? io_req_bits_rs1_data_0 : io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :286:10] wire [63:0] _alu_out_T_5 = io_req_bits_uop_is_mov_0 ? io_req_bits_rs2_data_0 : _alu_io_out; // @[functional-unit.scala:133:7, :173:19, :287:10] wire [63:0] alu_out = _alu_out_T_5; // @[functional-unit.scala:285:20, :287:10] wire _io_resp_bits_data_T = |io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_data_T_2 = _io_resp_bits_data_T_1; // @[micro-op.scala:120:{42,52}] wire _io_resp_bits_data_T_3 = pc_sel == 2'h1; // @[functional-unit.scala:188:48, :290:62] assign _io_resp_bits_data_T_4 = _io_resp_bits_data_T_2 ? {63'h0, _io_resp_bits_data_T_3} : alu_out; // @[OneHot.scala:58:35] assign io_resp_bits_data_0 = _io_resp_bits_data_T_4; // @[functional-unit.scala:133:7, :290:27] wire _io_resp_bits_predicated_T = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_predicated_T_1 = _io_resp_bits_predicated_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_predicated_T_2 = _io_resp_bits_predicated_T_1; // @[micro-op.scala:121:{42,52}] ALU alu ( // @[functional-unit.scala:173:19] .clock (clock), .reset (reset), .io_dw (_alu_io_dw_T_1), // @[functional-unit.scala:178:20] .io_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:133:7] .io_in2 (op2_data), // @[functional-unit.scala:164:45] .io_in1 (op1_data[63:0]), // @[functional-unit.scala:155:45, :175:14] .io_out (_alu_io_out) ); // @[functional-unit.scala:173:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:133:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_15( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_22 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller */ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) /* Negotiated sizes */ def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) /* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */ val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8*fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j*8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c || g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U | right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /** Trait that will connect a PLIC to a subsystem */ trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode :=* ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }

module PLICFanIn_2( // @[Plic.scala:338:7] input clock, // @[Plic.scala:338:7] input reset, // @[Plic.scala:338:7] input io_prio_0, // @[Plic.scala:339:14] input io_ip, // @[Plic.scala:339:14] output io_dev, // @[Plic.scala:339:14] output io_max // @[Plic.scala:339:14] ); wire io_prio_0_0 = io_prio_0; // @[Plic.scala:338:7] wire io_ip_0 = io_ip; // @[Plic.scala:338:7] wire [1:0] effectivePriority_0 = 2'h2; // @[Plic.scala:355:32] wire _effectivePriority_T = io_ip_0; // @[Plic.scala:338:7, :355:55] wire maxDev; // @[Misc.scala:35:36] wire io_dev_0; // @[Plic.scala:338:7] wire io_max_0; // @[Plic.scala:338:7] wire [1:0] effectivePriority_1 = {_effectivePriority_T, io_prio_0_0}; // @[Plic.scala:338:7, :355:{55,100}] wire [1:0] maxPri = effectivePriority_1 != 2'h3 ? 2'h2 : effectivePriority_1; // @[Misc.scala:35:9] assign maxDev = &effectivePriority_1; // @[Misc.scala:35:36] assign io_dev_0 = maxDev; // @[Misc.scala:35:36] assign io_max_0 = maxPri[0]; // @[Misc.scala:35:9] assign io_dev = io_dev_0; // @[Plic.scala:338:7] assign io_max = io_max_0; // @[Plic.scala:338:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_40( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_354 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_356 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_357 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File OutputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class OutputCreditAlloc extends Bundle { val alloc = Bool() val tail = Bool() } class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams { val occupied = Bool() def available = !occupied val flow = new FlowRoutingBundle } class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams { val alloc = Bool() val flow = new FlowRoutingBundle } class AbstractOutputUnitIO( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Bundle with HasRouterInputParams { val nodeId = cParam.srcId val nVirtualChannels = cParam.nVirtualChannels val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val credit_available = Output(Vec(nVirtualChannels, Bool())) val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus)) val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc)) val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc)) } abstract class AbstractOutputUnit( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams { val nodeId = cParam.srcId def io: AbstractOutputUnitIO } class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = new Channel(cParam.asInstanceOf[ChannelParams]) } val io = IO(new OutputUnitIO) class OutputState(val bufferSize: Int) extends Bundle { val occupied = Bool() val c = UInt(log2Up(1+bufferSize).W) val flow = new FlowRoutingBundle } val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) })) (states zip io.channel_status).map { case (s,a) => a.occupied := s.occupied a.flow := s.flow } io.out.flit := io.in states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) { when (io.out.vc_free(i)) { assert(s.occupied) s.occupied := false.B } } } (states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) { when (a.alloc) { s.occupied := true.B s.flow := a.flow } } } (io.credit_available zip states).zipWithIndex.map { case ((c,s),i) => c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U) } states.zipWithIndex.map { case (s,i) => val free = io.out.credit_return(i) val alloc = io.credit_alloc(i).alloc if (cParam.virtualChannelParams(i).traversable) { s.c := s.c +& free - alloc } } when (reset.asBool) { states.foreach(_.occupied := false.B) states.foreach(s => s.c := s.bufferSize.U) } }

module OutputUnit( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [5:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [5:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_8, // @[OutputUnit.scala:58:14] output io_credit_available_9, // @[OutputUnit.scala:58:14] output io_credit_available_12, // @[OutputUnit.scala:58:14] output io_credit_available_13, // @[OutputUnit.scala:58:14] output io_credit_available_16, // @[OutputUnit.scala:58:14] output io_credit_available_17, // @[OutputUnit.scala:58:14] output io_credit_available_20, // @[OutputUnit.scala:58:14] output io_credit_available_21, // @[OutputUnit.scala:58:14] output io_channel_status_8_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_9_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_12_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_13_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_16_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_17_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_20_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_21_occupied, // @[OutputUnit.scala:58:14] input io_allocs_8_alloc, // @[OutputUnit.scala:58:14] input io_allocs_9_alloc, // @[OutputUnit.scala:58:14] input io_allocs_12_alloc, // @[OutputUnit.scala:58:14] input io_allocs_13_alloc, // @[OutputUnit.scala:58:14] input io_allocs_16_alloc, // @[OutputUnit.scala:58:14] input io_allocs_17_alloc, // @[OutputUnit.scala:58:14] input io_allocs_20_alloc, // @[OutputUnit.scala:58:14] input io_allocs_21_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_8_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_9_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_12_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_13_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_16_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_17_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_20_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_21_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [5:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [5:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [21:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [21:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_21_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_21_c; // @[OutputUnit.scala:66:19] reg states_20_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_20_c; // @[OutputUnit.scala:66:19] reg states_17_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_17_c; // @[OutputUnit.scala:66:19] reg states_16_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_16_c; // @[OutputUnit.scala:66:19] reg states_13_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_13_c; // @[OutputUnit.scala:66:19] reg states_12_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_12_c; // @[OutputUnit.scala:66:19] reg states_9_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_9_c; // @[OutputUnit.scala:66:19] reg states_8_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_8_c; // @[OutputUnit.scala:66:19]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = |(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2461 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2461; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2461; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2535 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2535; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2535; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2535; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2535; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2532 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2532; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2532; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2387 = _T_2461 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2387 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2387 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2387 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2387 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2387 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2433 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2433 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2535 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2402 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2402 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2402 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2474 = _T_2532 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2474 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2474 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2474 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2474 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2474 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2505 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2505 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2487 = _T_2535 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2487 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2487 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2487 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2541 = _T_2535 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2541 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2550 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2550 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Tail.scala: //****************************************************************************** // Copyright (c) 2021-2022, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE for license details. //------------------------------------------------------------------------------ /** * - Tail.scala is the top of the system * - Input for FFT: `val signalIn` in class TailIO * - signalIn is a vector of K complex numbers (specified by TailParams) * - Connection: signalIn -> Deserialize -> FFT -> Unscramble -> OUTPUT */ package fftgenerator import chisel3._ import chisel3.util._ import dsptools.numbers._ import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS} import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink.{TLRegisterNode, TLFragmenter} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import craft._ import dsptools._ import dsptools.numbers.implicits._ import dspjunctions._ import dspblocks._ import scala.math._ import scala.math.sqrt import scala.collection.mutable.ListBuffer import fixedpoint._ import fixedpoint.{fromIntToBinaryPoint} trait TailParams[T <: Data] extends DeserializeParams[T] with FFTConfig[T] with UnscrambleParams[T] { // Number of lanes in FFT. Should be same as N. val lanes: Int // n-point FFT val n: Int val S: Int } case class FixedTailParams( IOWidth: Int = 16, binaryPoint: Int = 8, lanes: Int = 2, n: Int = 2, S: Int = 256, pipelineDepth: Int = 0, // not configurable since this is an mmio device and not on-pipeline baseAddress: Int = 0x2000, ) extends TailParams[FixedPoint] { val proto = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoIn = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoOut = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val genIn = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val genOut = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoInDes = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val protoOutDes = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val inA = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val inB = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) val outC = DspComplex(FixedPoint(IOWidth.W, binaryPoint.BP),FixedPoint(IOWidth.W, binaryPoint.BP)) } class TailIO[T <: Data](params: TailParams[T]) extends Bundle { val signalIn = Flipped(Decoupled(params.protoIn.cloneType)) // (decoupled: adds ready-valid (vector of k complex numbers)) // Outputs // -- Signal Output val signalOut = Decoupled((Vec(params.lanes, params.protoOut.cloneType))) } object TailIO { def apply[T <: Data](params: TailParams[T]): TailIO[T] = new TailIO(params) } class Tail[T <: Data : RealBits : BinaryRepresentation : Real](val params: TailParams[T]) extends Module { val io = IO(TailIO(params)) // Instantiate the modules val DeserializeModule = Module(new Deserialize(params)).io val FFTModule = Module(new FFT(params)).io val UnscrambleModule = Module(new Unscramble(params)).io DeserializeModule.in.bits := io.signalIn.bits DeserializeModule.in.valid := io.signalIn.valid // signalIn.valid = new point being passed in io.signalIn.ready := DeserializeModule.in.ready // Connect Deserialize to FFT for (j <- 0 until params.lanes) FFTModule.in.bits(j) := DeserializeModule.out.bits(j) FFTModule.in.valid := DeserializeModule.out.valid FFTModule.in.sync := DeserializeModule.out.sync /* Connect FFT to Unscramble * FFT outputs values with bits reversed (Ex: input of 001 becomes output of 100) * Unscramble fixes the bit order */ for (j <- 0 until params.lanes) UnscrambleModule.in.bits(j) := FFTModule.out.bits(j) UnscrambleModule.in.valid := FFTModule.out.valid UnscrambleModule.in.sync := FFTModule.out.sync for (j <- 0 until params.lanes) io.signalOut.bits(j) := UnscrambleModule.out.bits(j) io.signalOut.valid := UnscrambleModule.out.valid UnscrambleModule.out.ready := io.signalOut.ready } class LazyTail(val config: FixedTailParams)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("fft-generator", Seq("cpu")) // add an entry to the DeviceTree in the BootROM so that it can be read by a Linux driver (9.2 chipyard docs) val node = TLRegisterNode( address = Seq(AddressSet(config.baseAddress, 0xff)), // (base address + size) of regmap device = device, beatBytes = 8, // specifies interface width in bytes -- since we're connected to a 64bit bus, want an 8byte width (default is 4) concurrency = 1 // size of the internal queue for TileLink requests, must be >0 for decoupled requests and responses (9.4 chipyard docs) ) lazy val module = new LazyModuleImp(this) { val tail = Module(new Tail(config)) val inputWire = Wire(Decoupled(UInt((config.IOWidth * 2).W))) inputWire.ready := tail.io.signalIn.ready tail.io.signalIn.bits := inputWire.bits.asTypeOf(config.protoIn) tail.io.signalIn.valid := inputWire.valid val outputRegs = tail.io.signalOut.bits.map(b => RegEnable(b.asUInt, 0.U, tail.io.signalOut.valid)) var regMap = new ListBuffer[(Int, Seq[freechips.rocketchip.regmapper.RegField])]() regMap += (0x00 -> Seq(RegField.w(config.IOWidth * 2, inputWire))) for (i <- 0 until config.n) { regMap += (0x00 + (i+1) * 8 -> Seq(RegField.r(config.IOWidth * 2, outputRegs(i)))) } tail.io.signalOut.ready := true.B node.regmap((regMap.toList):_*) } } trait CanHavePeripheryFFT extends BaseSubsystem { if (!p(FFTEnableKey).isEmpty) { // instantiate tail chain val pbus = locateTLBusWrapper(PBUS) val domain = pbus.generateSynchronousDomain.suggestName("fft_domain") val tailChain = domain { LazyModule(new LazyTail(p(FFTEnableKey).get)) } // connect memory interfaces to pbus pbus.coupleTo("tailWrite") { domain { tailChain.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ } } } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module ClockSinkDomain_1( // @[ClockDomain.scala:14:9] output auto_fragmenter_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_fragmenter_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_fragmenter_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_fragmenter_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_fragmenter_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [10:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [13:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _tailChain_auto_in_a_ready; // @[Tail.scala:148:40] wire _tailChain_auto_in_d_valid; // @[Tail.scala:148:40] wire [2:0] _tailChain_auto_in_d_bits_opcode; // @[Tail.scala:148:40] wire [1:0] _tailChain_auto_in_d_bits_size; // @[Tail.scala:148:40] wire [10:0] _tailChain_auto_in_d_bits_source; // @[Tail.scala:148:40] wire [63:0] _tailChain_auto_in_d_bits_data; // @[Tail.scala:148:40] LazyTail tailChain ( // @[Tail.scala:148:40] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_a_ready (_tailChain_auto_in_a_ready), .auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_in_d_valid (_tailChain_auto_in_d_valid), .auto_in_d_bits_opcode (_tailChain_auto_in_d_bits_opcode), .auto_in_d_bits_size (_tailChain_auto_in_d_bits_size), .auto_in_d_bits_source (_tailChain_auto_in_d_bits_source), .auto_in_d_bits_data (_tailChain_auto_in_d_bits_data) ); // @[Tail.scala:148:40] TLFragmenter_1 fragmenter ( // @[Fragmenter.scala:345:34] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_anon_in_a_ready (auto_fragmenter_anon_in_a_ready), .auto_anon_in_a_valid (auto_fragmenter_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_fragmenter_anon_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_fragmenter_anon_in_a_bits_param), .auto_anon_in_a_bits_size (auto_fragmenter_anon_in_a_bits_size), .auto_anon_in_a_bits_source (auto_fragmenter_anon_in_a_bits_source), .auto_anon_in_a_bits_address (auto_fragmenter_anon_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_fragmenter_anon_in_a_bits_mask), .auto_anon_in_a_bits_data (auto_fragmenter_anon_in_a_bits_data), .auto_anon_in_a_bits_corrupt (auto_fragmenter_anon_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_fragmenter_anon_in_d_ready), .auto_anon_in_d_valid (auto_fragmenter_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_fragmenter_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (auto_fragmenter_anon_in_d_bits_size), .auto_anon_in_d_bits_source (auto_fragmenter_anon_in_d_bits_source), .auto_anon_in_d_bits_data (auto_fragmenter_anon_in_d_bits_data), .auto_anon_out_a_ready (_tailChain_auto_in_a_ready), // @[Tail.scala:148:40] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_tailChain_auto_in_d_valid), // @[Tail.scala:148:40] .auto_anon_out_d_bits_opcode (_tailChain_auto_in_d_bits_opcode), // @[Tail.scala:148:40] .auto_anon_out_d_bits_size (_tailChain_auto_in_d_bits_size), // @[Tail.scala:148:40] .auto_anon_out_d_bits_source (_tailChain_auto_in_d_bits_source), // @[Tail.scala:148:40] .auto_anon_out_d_bits_data (_tailChain_auto_in_d_bits_data) // @[Tail.scala:148:40] ); // @[Fragmenter.scala:345:34] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_31( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [514:0] _c_sizes_set_T_1 = 515'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [159:0] c_opcodes_set = 160'h0; // @[Monitor.scala:740:34] wire [159:0] c_sizes_set = 160'h0; // @[Monitor.scala:741:34] wire [39:0] c_set = 40'h0; // @[Monitor.scala:738:34] wire [39:0] c_set_wo_ready = 40'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 6'h28; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [5:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [5:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 6'h28; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [39:0] inflight; // @[Monitor.scala:614:27] reg [159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [159:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [39:0] a_set; // @[Monitor.scala:626:34] wire [39:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [159:0] _a_opcode_lookup_T_6 = {156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [159:0] _a_size_lookup_T_6 = {156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_2 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[159:0] : 160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[159:0] : 160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [39:0] d_clr; // @[Monitor.scala:664:34] wire [39:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[39:0] : 40'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[159:0] : 160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[159:0] : 160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [39:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [39:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [39:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [39:0] inflight_1; // @[Monitor.scala:726:35] wire [39:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [159:0] _c_opcode_lookup_T_6 = {156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [159:0] _c_size_lookup_T_6 = {156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [39:0] d_clr_1; // @[Monitor.scala:774:34] wire [39:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[39:0] : 40'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[39:0] : 40'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[159:0] : 160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[159:0] : 160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [39:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [39:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a32d64s5k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_11 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }

module MulAddRecFNToRaw_preMul_e8_s24_72( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SingleVCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} // Allocates 1 VC per cycle abstract class SingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends VCAllocator(vP)(p) { // get single input val mask = RegInit(0.U(allInParams.size.W)) val in_arb_reqs = Wire(Vec(allInParams.size, MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))) val in_arb_vals = Wire(Vec(allInParams.size, Bool())) val in_arb_filter = PriorityEncoderOH(Cat(in_arb_vals.asUInt, in_arb_vals.asUInt & ~mask)) val in_arb_sel = (in_arb_filter(allInParams.size-1,0) | (in_arb_filter >> allInParams.size)) when (in_arb_vals.orR) { mask := Mux1H(in_arb_sel, (0 until allInParams.size).map { w => ~(0.U((w+1).W)) }) } for (i <- 0 until allInParams.size) { (0 until allOutParams.size).map { m => (0 until allOutParams(m).nVirtualChannels).map { n => in_arb_reqs(i)(m)(n) := io.req(i).bits.vc_sel(m)(n) && !io.channel_status(m)(n).occupied } } in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).toSeq.orR } // Input arbitration io.req.foreach(_.ready := false.B) val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow).toSeq) val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc).toSeq) val in_vc_sel = Mux1H(in_arb_sel, in_arb_reqs) in_alloc := Mux(in_arb_vals.orR, inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).toSeq.orR), 0.U.asTypeOf(in_alloc)) // send allocation to inputunits for (i <- 0 until allInParams.size) { io.req(i).ready := in_arb_sel(i) for (m <- 0 until allOutParams.size) { (0 until allOutParams(m).nVirtualChannels).map { n => io.resp(i).vc_sel(m)(n) := in_alloc(m)(n) } } assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U) } // send allocation to output units for (i <- 0 until allOutParams.size) { (0 until allOutParams(i).nVirtualChannels).map { j => io.out_allocs(i)(j).alloc := in_alloc(i)(j) io.out_allocs(i)(j).flow := in_flow } } } File VCAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.{DecodeLogic} import constellation.channel._ import constellation.noc.{HasNoCParams} import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo, ChannelRoutingInfo} class VCAllocReq( val inParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams with HasNoCParams { val flow = new FlowRoutingBundle val in_vc = UInt(log2Ceil(inParam.nVirtualChannels).W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class VCAllocResp(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } case class VCAllocatorParams( routerParams: RouterParams, inParams: Seq[ChannelParams], outParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], egressParams: Seq[EgressChannelParams]) abstract class VCAllocator(val vP: VCAllocatorParams)(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val routerParams = vP.routerParams val inParams = vP.inParams val outParams = vP.outParams val ingressParams = vP.ingressParams val egressParams = vP.egressParams val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new VCAllocReq(u, outParams, egressParams))) }) val resp = MixedVec(allInParams.map { u => Output(new VCAllocResp(outParams, egressParams)) }) val channel_status = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Input(new OutputChannelStatus)) }) val out_allocs = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputChannelAlloc)) }) }) val nOutChannels = allOutParams.map(_.nVirtualChannels).sum def inputAllocPolicy( flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool): MixedVec[Vec[Bool]] def outputAllocPolicy( out: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool): Vec[Bool] } File ISLIP.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.random.{LFSR} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{ChannelRoutingInfo, FlowRoutingBundle} trait ISLIP { this: VCAllocator => def islip(in: UInt, fire: Bool): UInt = { val w = in.getWidth if (w > 1) { val mask = RegInit(0.U(w.W)) val full = Cat(in, in & ~mask) val oh = PriorityEncoderOH(full) val sel = (oh(w-1,0) | (oh >> w)) when (fire) { mask := MuxCase(0.U, (0 until w).map { i => sel(i) -> ~(0.U((i+1).W)) }) } sel } else { in } } def inputAllocPolicy(flow: FlowRoutingBundle, vc_sel: MixedVec[Vec[Bool]], inId: UInt, inVId: UInt, fire: Bool) = { islip(vc_sel.asUInt, fire).asTypeOf(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool())})) } def outputAllocPolicy(channel: ChannelRoutingInfo, flows: Seq[FlowRoutingBundle], reqs: Seq[Bool], fire: Bool) = { islip(VecInit(reqs).asUInt, fire).asTypeOf(Vec(allInParams.size, Bool())) } } class ISLIPMultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends MultiVCAllocator(vP)(p) with ISLIP class RotatingSingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) extends SingleVCAllocator(vP)(p) with ISLIP

module RotatingSingleVCAllocator_1( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_4_ready, // @[VCAllocator.scala:49:14] input io_req_4_valid, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_4_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_3_ready, // @[VCAllocator.scala:49:14] input io_req_3_valid, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_2_ready, // @[VCAllocator.scala:49:14] input io_req_2_valid, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_4_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_2, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_1, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_2, // @[VCAllocator.scala:49:14] input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_2_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_2_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_2_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_4; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [4:0] mask; // @[SingleVCAllocator.scala:16:21] wire [4:0] _in_arb_filter_T_3 = {in_arb_vals_4, in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [9:0] in_arb_filter = _in_arb_filter_T_3[0] ? 10'h1 : _in_arb_filter_T_3[1] ? 10'h2 : _in_arb_filter_T_3[2] ? 10'h4 : _in_arb_filter_T_3[3] ? 10'h8 : _in_arb_filter_T_3[4] ? 10'h10 : in_arb_vals_0 ? 10'h20 : in_arb_vals_1 ? 10'h40 : in_arb_vals_2 ? 10'h80 : in_arb_vals_3 ? 10'h100 : {in_arb_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] in_arb_sel = in_arb_filter[4:0] | in_arb_filter[9:5]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3 | in_arb_vals_4; // @[package.scala:81:59] wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_1 = io_req_0_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_2 = io_req_0_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_1_0 | in_arb_reqs_0_1_1 | in_arb_reqs_0_1_2 | in_arb_reqs_0_2_0 | in_arb_reqs_0_2_1 | in_arb_reqs_0_2_2 | in_arb_reqs_0_3_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_1 = io_req_1_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_2 = io_req_1_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_1 = io_req_1_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_2 = io_req_1_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_1_0 | in_arb_reqs_1_1_1 | in_arb_reqs_1_1_2 | in_arb_reqs_1_2_0 | in_arb_reqs_1_2_1 | in_arb_reqs_1_2_2 | in_arb_reqs_1_3_0); // @[package.scala:81:59] wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_1 = io_req_2_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_2_2 = io_req_2_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_1_0 | in_arb_reqs_2_1_1 | in_arb_reqs_2_1_2 | in_arb_reqs_2_2_0 | in_arb_reqs_2_2_1 | in_arb_reqs_2_2_2 | in_arb_reqs_2_3_0); // @[package.scala:81:59] wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_1 = io_req_3_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_1_2 = io_req_3_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_1 = io_req_3_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_2_2 = io_req_3_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_3_3_0 = io_req_3_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 | in_arb_reqs_3_0_1 | in_arb_reqs_3_0_2 | in_arb_reqs_3_1_0 | in_arb_reqs_3_1_1 | in_arb_reqs_3_1_2 | in_arb_reqs_3_2_0 | in_arb_reqs_3_2_1 | in_arb_reqs_3_2_2 | in_arb_reqs_3_3_0); // @[package.scala:81:59] wire in_arb_reqs_4_0_0 = io_req_4_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_0_1 = io_req_4_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_0_2 = io_req_4_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_0 = io_req_4_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_1 = io_req_4_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_1_2 = io_req_4_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_0 = io_req_4_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_1 = io_req_4_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_2_2 = io_req_4_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_4_3_0 = io_req_4_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_4 = io_req_4_valid & (in_arb_reqs_4_0_0 | in_arb_reqs_4_0_1 | in_arb_reqs_4_0_2 | in_arb_reqs_4_1_0 | in_arb_reqs_4_1_1 | in_arb_reqs_4_1_2 | in_arb_reqs_4_2_0 | in_arb_reqs_4_2_1 | in_arb_reqs_4_2_2 | in_arb_reqs_4_3_0); // @[package.scala:81:59] wire _in_vc_sel_T_13 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[3] & in_arb_reqs_3_0_0 | in_arb_sel[4] & in_arb_reqs_4_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_22 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[2] & in_arb_reqs_2_0_1 | in_arb_sel[3] & in_arb_reqs_3_0_1 | in_arb_sel[4] & in_arb_reqs_4_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[2] & in_arb_reqs_2_0_2 | in_arb_sel[3] & in_arb_reqs_3_0_2 | in_arb_sel[4] & in_arb_reqs_4_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_40 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0 | in_arb_sel[4] & in_arb_reqs_4_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_49 = in_arb_sel[0] & in_arb_reqs_0_1_1 | in_arb_sel[1] & in_arb_reqs_1_1_1 | in_arb_sel[2] & in_arb_reqs_2_1_1 | in_arb_sel[3] & in_arb_reqs_3_1_1 | in_arb_sel[4] & in_arb_reqs_4_1_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_58 = in_arb_sel[0] & in_arb_reqs_0_1_2 | in_arb_sel[1] & in_arb_reqs_1_1_2 | in_arb_sel[2] & in_arb_reqs_2_1_2 | in_arb_sel[3] & in_arb_reqs_3_1_2 | in_arb_sel[4] & in_arb_reqs_4_1_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_67 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0 | in_arb_sel[4] & in_arb_reqs_4_2_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_76 = in_arb_sel[0] & in_arb_reqs_0_2_1 | in_arb_sel[1] & in_arb_reqs_1_2_1 | in_arb_sel[2] & in_arb_reqs_2_2_1 | in_arb_sel[3] & in_arb_reqs_3_2_1 | in_arb_sel[4] & in_arb_reqs_4_2_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_85 = in_arb_sel[0] & in_arb_reqs_0_2_2 | in_arb_sel[1] & in_arb_reqs_1_2_2 | in_arb_sel[2] & in_arb_reqs_2_2_2 | in_arb_sel[3] & in_arb_reqs_3_2_2 | in_arb_sel[4] & in_arb_reqs_4_2_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_94 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[1] & in_arb_reqs_1_3_0 | in_arb_sel[2] & in_arb_reqs_2_3_0 | in_arb_sel[3] & in_arb_reqs_3_3_0 | in_arb_sel[4] & in_arb_reqs_4_3_0; // @[Mux.scala:30:73, :32:36] reg [9:0] mask_1; // @[ISLIP.scala:17:25] wire [9:0] _full_T_1 = {_in_vc_sel_T_94, _in_vc_sel_T_85, _in_vc_sel_T_76, _in_vc_sel_T_67, _in_vc_sel_T_58, _in_vc_sel_T_49, _in_vc_sel_T_40, _in_vc_sel_T_31, _in_vc_sel_T_22, _in_vc_sel_T_13} & ~mask_1; // @[Mux.scala:30:73] wire [19:0] oh = _full_T_1[0] ? 20'h1 : _full_T_1[1] ? 20'h2 : _full_T_1[2] ? 20'h4 : _full_T_1[3] ? 20'h8 : _full_T_1[4] ? 20'h10 : _full_T_1[5] ? 20'h20 : _full_T_1[6] ? 20'h40 : _full_T_1[7] ? 20'h80 : _full_T_1[8] ? 20'h100 : _full_T_1[9] ? 20'h200 : _in_vc_sel_T_13 ? 20'h400 : _in_vc_sel_T_22 ? 20'h800 : _in_vc_sel_T_31 ? 20'h1000 : _in_vc_sel_T_40 ? 20'h2000 : _in_vc_sel_T_49 ? 20'h4000 : _in_vc_sel_T_58 ? 20'h8000 : _in_vc_sel_T_67 ? 20'h10000 : _in_vc_sel_T_76 ? 20'h20000 : _in_vc_sel_T_85 ? 20'h40000 : {_in_vc_sel_T_94, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] sel = oh[9:0] | oh[19:10]; // @[Mux.scala:50:70] wire in_alloc_3_0 = _GEN & sel[9]; // @[package.scala:81:59] wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_2_1 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_2_2 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_1_1 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_1_2 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w4_d3_i0_38( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_343 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_346 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }

module PE_218( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_26 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_27 = _source_ok_T_26 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_67 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire _source_ok_T_66 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }

module RouteComputer( // @[RouteComputer.scala:29:7] input [3:0] io_req_6_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_6_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_6_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2 // @[RouteComputer.scala:40:14] ); wire [3:0] _GEN = ~io_req_6_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_6_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_6_vc_sel_1_0 = |{&{_GEN_0[0], _GEN[0], _GEN[1], io_req_6_bits_flow_egress_node[2]}, &{_GEN_0[0], _GEN[0], _GEN[1], io_req_6_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_6_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_6_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_6_vc_sel_0_0 = |{&{_GEN_0[0], io_req_6_bits_flow_egress_node[0], _GEN[2], _GEN[3]}, &{_GEN_0[0], _GEN_0[1], io_req_6_bits_flow_egress_node[1]}, &{_GEN_0[0], io_req_6_bits_flow_egress_node[0], io_req_6_bits_flow_egress_node[2], io_req_6_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_6_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_6_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_2 = |{&{io_req_4_bits_flow_egress_node[2], ~(io_req_4_bits_flow_egress_node[3])}, io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_2 = |{&{io_req_2_bits_flow_egress_node[2], ~(io_req_2_bits_flow_egress_node[3])}, io_req_2_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}, :114:{19,36}] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLInterconnectCoupler_cbus_to_debug( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [9:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [9:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire [9:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [13:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [9:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [9:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [11:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [9:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [13:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [9:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [9:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] TLFragmenter_Debug fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7] ); // @[Fragmenter.scala:345:34] assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_274( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a32d64s1k3z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_source = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [2:0] auto_in_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_61 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }

module Repeater_TLBundleD_a32d256s5k5z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_sink, // @[Repeater.scala:13:14] input io_enq_bits_denied, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_sink, // @[Repeater.scala:13:14] output io_deq_bits_denied, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[Repeater.scala:10:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [1:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_sink; // @[Repeater.scala:26:21] wire _io_deq_bits_T_denied; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [1:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_sink_0; // @[Repeater.scala:10:7] wire io_deq_bits_denied_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [1:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [4:0] saved_sink; // @[Repeater.scala:21:18] reg saved_denied; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_sink = full ? saved_sink : io_enq_bits_sink_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_denied = full ? saved_denied : io_enq_bits_denied_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_sink_0 = _io_deq_bits_T_sink; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_denied_0 = _io_deq_bits_T_denied; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_sink <= io_enq_bits_sink_0; // @[Repeater.scala:10:7, :21:18] saved_denied <= io_enq_bits_denied_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_sink = io_deq_bits_sink_0; // @[Repeater.scala:10:7] assign io_deq_bits_denied = io_deq_bits_denied_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File NoC.scala: package constellation.noc import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody} import freechips.rocketchip.util.ElaborationArtefacts import freechips.rocketchip.prci._ import constellation.router._ import constellation.channel._ import constellation.routing.{RoutingRelation, ChannelRoutingInfo} import constellation.topology.{PhysicalTopology, UnidirectionalLine} class NoCTerminalIO( val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle { val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) }) val egress = MixedVec(egressParams.map { u => new EgressChannel(u) }) } class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined = nocParams.inlineNoC val internalParams = InternalNoCParams(nocParams) val allChannelParams = internalParams.channelParams val allIngressParams = internalParams.ingressParams val allEgressParams = internalParams.egressParams val allRouterParams = internalParams.routerParams val iP = p.alterPartial({ case InternalNoCKey => internalParams }) val nNodes = nocParams.topology.nNodes val nocName = nocParams.nocName val skipValidationChecks = nocParams.skipValidationChecks val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) } val router_sink_domains = Seq.tabulate(nNodes) { i => val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters( name = Some(s"${nocName}_router_$i") ))) router_sink_domain.clockNode := clockSourceNodes(i) router_sink_domain } val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) { val inParams = allChannelParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val outParams = allChannelParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val ingressParams = allIngressParams.filter(_.destId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val egressParams = allEgressParams.filter(_.srcId == i).map( _.copy(payloadBits=allRouterParams(i).user.payloadBits) ) val noIn = inParams.size + ingressParams.size == 0 val noOut = outParams.size + egressParams.size == 0 if (noIn || noOut) { println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated") None } else { Some(LazyModule(new Router( routerParams = allRouterParams(i), preDiplomaticInParams = inParams, preDiplomaticIngressParams = ingressParams, outDests = outParams.map(_.destId), egressIds = egressParams.map(_.egressId) )(iP))) } }}.flatten val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) } val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) } // Generate channels between routers diplomatically Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) { val routerI = routers.find(_.nodeId == i) val routerJ = routers.find(_.nodeId == j) if (routerI.isDefined && routerJ.isDefined) { val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j) val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i) require (sourceNodes.size == destNodes.size) (sourceNodes zip destNodes).foreach { case (src, dst) => val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get router_sink_domains(j) { implicit val p: Parameters = iP (dst := ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits) := channelParam.channelGen(p)(src) ) } } } }} // Generate terminal channels diplomatically routers.foreach { dst => router_sink_domains(dst.nodeId) { implicit val p: Parameters = iP dst.ingressNodes.foreach(n => { val ingressId = n.destParams.ingressId require(dst.payloadBits <= allIngressParams(ingressId).payloadBits) (n := IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits) := ingressNodes(ingressId) ) }) dst.egressNodes.foreach(n => { val egressId = n.egressId require(dst.payloadBits <= allEgressParams(egressId).payloadBits) (egressNodes(egressId) := EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits) := n ) }) }} val debugNodes = routers.map { r => val sink = BundleBridgeSink[DebugBundle]() sink := r.debugNode sink } val ctrlNodes = if (nocParams.hasCtrl) { (0 until nNodes).map { i => routers.find(_.nodeId == i).map { r => val sink = BundleBridgeSink[RouterCtrlBundle]() sink := r.ctrlNode.get sink } } } else { Nil } println(s"Constellation: $nocName Finished parameter validation") lazy val module = new Impl class Impl extends LazyModuleImp(this) { println(s"Constellation: $nocName Starting NoC RTL generation") val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) { val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters()))) val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil }) (io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l } (io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r } (io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r } if (nocParams.hasCtrl) { ctrlNodes.zipWithIndex.map { case (c,i) => if (c.isDefined) { io.router_ctrl(i) <> c.get.in(0)._1 } else { io.router_ctrl(i) <> DontCare } } } // TODO: These assume a single clock-domain across the entire noc val debug_va_stall_ctr = RegInit(0.U(64.W)) val debug_sa_stall_ctr = RegInit(0.U(64.W)) val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_) debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_) dontTouch(debug_va_stall_ctr) dontTouch(debug_sa_stall_ctr) dontTouch(debug_any_stall_ctr) def prepend(s: String) = Seq(nocName, s).mkString(".") ElaborationArtefacts.add(prepend("noc.graphml"), graphML) val adjList = routers.map { r => val outs = r.outParams.map(o => s"${o.destId}").mkString(" ") val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ") val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}") (Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.adjlist"), adjList) val xys = routers.map(r => { val n = r.nodeId val ids = (Seq(r.nodeId.toString) ++ r.egressParams.map(e => s"e${e.egressId}") ++ r.ingressParams.map(i => s"i${i.ingressId}") ) val plotter = nocParams.topology.plotter val coords = (Seq(plotter.node(r.nodeId)) ++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) } ++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) } ) (ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n") }).mkString("\n") ElaborationArtefacts.add(prepend("noc.xy"), xys) val edgeProps = routers.map { r => val outs = r.outParams.map { o => (Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val egresses = r.egressParams.map { e => (Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } val ingresses = r.ingressParams.map { i => (Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None)) .mkString(" ") } (outs ++ egresses ++ ingresses).mkString("\n") }.mkString("\n") ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps) println(s"Constellation: $nocName Finished NoC RTL generation") } }

module TLNoC_2_router_7ClockSinkDomain( // @[ClockDomain.scala:14:9] output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_54 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_egress_nodes_out_2_flit_ready (auto_routers_egress_nodes_out_2_flit_ready), .auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid), .auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head), .auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLBuffer_a28d64s4k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_57 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (2'h0), // @[Decoupled.scala:362:21] .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_denied (1'h0), // @[Decoupled.scala:362:21] .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:362:21] .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }

module OptimizationBarrier_TLBEntryData_10( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_63( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_76 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a29d64s9k1z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [8:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [8:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_19 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s9k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s9k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [1:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [1:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [1:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [6:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [80:0] inflight; // @[Monitor.scala:614:27] reg [323:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [323:0] inflight_sizes; // @[Monitor.scala:618:33] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_1 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_4 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [80:0] inflight_1; // @[Monitor.scala:726:35] reg [323:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [127:0] _GEN_6 = {121'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [11:0] inflight_2; // @[Monitor.scala:828:27] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [11:0] d_set = _GEN_8 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }

module AsyncValidSync_87( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_100 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords * 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. */ object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /** Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. */ case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /** the base address of DM */ def atzero = (baseAddress == 0) /** The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm */ def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /** Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above */ case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ***************************************** // Module Interfaces // // ***************************************** /** Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} */ class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** resume request */ val resumereq = Bool() /** hart select */ val hartsel = UInt(10.W) /** reset acknowledge */ val ackhavereset = Bool() /** hart array enable */ val hasel = Bool() /** hart array mask */ val hamask = Vec(nComponents, Bool()) /** halt-on-reset mask */ val hrmask = Vec(nComponents, Bool()) } /** structure for top-level Debug Module signals which aren't the bus interfaces. */ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** debug availability status for all harts */ val debugUnavail = Input(Vec(nComponents, Bool())) /** reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM */ val ndreset = Output(Bool()) /** reset signal for the DM itself */ val dmactive = Output(Bool()) /** dmactive acknowlege */ val dmactiveAck = Input(Bool()) } // ***************************************** // Debug Module // // ***************************************** /** Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. */ // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /** structure for top-level Debug Module signals which aren't the bus interfaces. */ val ctrl = (new DebugCtrlBundle(nComponents)) /** control signals for Inner, generated in Outer */ val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /** debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** authentication support */ val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /** whether the hart is selected */ def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive || ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive || ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((ii*haWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(ii*haWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(ii*haWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) || (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn | (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /** conrol signals for Inner, generated in Outer */ val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /** debug interruption generated in Inner */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Authentication signal from core */ val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /** dmiNode address set */ val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /** dm reset signal passed in from Outer */ val dmactive = Input(Bool()) /** conrol signals for Inner * * it's generated by Outer and comes in */ val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /** debug unavail signal passed in from Outer*/ val debugUnavail = Input(Vec(nComponents, Bool())) /** debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Output(Vec(nComponents, Bool())) /** interface for trigger */ val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug Authentication signals from core */ val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /** all harts halted status */ val haltedBitRegs = Reg(UInt(nComponents.W)) /** all harts resume request status */ val resumeReqRegs = Reg(UInt(nComponents.W)) /** all harts have reset status */ val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /** all harts resume ack status */ val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive || ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive || ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive || ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync | // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive || ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive || ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive || ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _) hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive || ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt | hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii*32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive || ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive || ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND*/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) || (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) || (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) || (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result || (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand || regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive || ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /** reset signal for DM */ val dmactive = Input(Bool()) /** conrol signals for Inner * * generated in Outer */ val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /** debug available status */ val debugUnavail = Input(Vec(getNComponents(), Bool())) /** debug interruption*/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(getNComponents(), Bool())) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /** Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. */ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug control signals generated in Outer */ val ctrl = new DebugCtrlBundle(nComponents) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) /** hart reset request generated by hartreset-logic in Outer */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File SBA.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug.systembusaccess import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.{AMBAProt, AMBAProtField} import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal} import freechips.rocketchip.diplomacy.TransferSizes import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType} import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters} import freechips.rocketchip.util.property object SystemBusAccessState extends scala.Enumeration { type SystemBusAccessState = Value val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value } object SBErrorCode extends scala.Enumeration { type SBErrorCode = Value val NoError = Value(0) val Timeout = Value(1) val BadAddr = Value(2) val AlgnError = Value(3) val BadAccess = Value(4) val OtherError = Value(7) } object SystemBusAccessModule { def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = { import SBErrorCode._ val cfg = p(DebugModuleKey).get val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn") val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn") val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn") // --- SBCS Status Register --- val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg") val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields())) SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) SBCSFieldsRegReset.sbaccess := 2.U SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData") val SBCSWrDataVal = WireInit(0.U(32.W)) val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields())) val sberrorWrEn = WireInit(false.B) val sbreadondataWrEn = WireInit(false.B) val sbautoincrementWrEn= WireInit(false.B) val sbaccessWrEn = WireInit(false.B) val sbreadonaddrWrEn = WireInit(false.B) val sbbusyerrorWrEn = WireInit(false.B) val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq( RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))), RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))), RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))), WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn, RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn, RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn, RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))), WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn, RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))), WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn, RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))), RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))), WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn, RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(6), RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))), )) // --- System Bus Address Registers --- // ADDR0 Register is required // Instantiate ADDR1-3 registers as needed depending on system bus address width val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33) val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65) val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97) val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3) val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W))) SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")} val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val autoIncrementedAddr = WireInit(0.U(128.W)) autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess) autoIncrementedAddr.suggestName("autoIncrementedAddr") val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) => if(hasAddr(i)) { when (~dmactive || ~dmAuthenticated) { a := 0.U(32.W) }.otherwise { a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i), Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32*i+31,32*i), a)) } RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i), Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true))))) } else { a := DontCare Seq.empty[RegField] } } sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0), Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)), Cat(SBADDRESSFieldsReg.reverse)) anyAddressWrEn := SBADDRESSWrEn.reduce(_ || _) // --- System Bus Data Registers --- // DATA0 Register is required // DATA1-3 Registers may not be needed depending on implementation val hasSBData1 = (cfg.maxSupportedSBAccess > 32) val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128) val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3) val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W)))) SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }} val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) } val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} )) SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) } val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} )) val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} )) SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) } val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) => if(hasData(i)) { // For data registers, load enable per-byte for (j <- 0 to 3) { when (~dmactive || ~dmAuthenticated) { d(j) := 0.U(8.W) }.otherwise { d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8*j+7,8*j), Mux(sb2tl.module.io.rdLoad(4*i+j), sb2tl.module.io.dataOut, d(j))) } } SBDATARdData(i) := Cat(d.reverse) RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i), Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true))))) } else { for (j <- 0 to 3) { d(j) := DontCare } Seq.empty[RegField] } } sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse)) anyDataRdEn := SBDATARdEn.reduce(_ || _) anyDataWrEn := SBDATAWrEn.reduce(_ || _) val tryWrEn = SBDATAWrEn(0) val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) || (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata) val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) || (SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) || (SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) || (SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) || (SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) || (SBCSFieldsReg.sbaccess > 4.U) val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0)) val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) || (SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U) sbAccessError.suggestName("sbAccessError") sbAlignmentError.suggestName("sbAlignmentError") sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U) when (~dmactive || ~dmAuthenticated) { SBCSFieldsReg := SBCSFieldsRegReset }.otherwise { SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy Mux((anyDataRdEn || anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr) SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata) SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018 } // sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it val sbErrorReg = Reg(Vec(4, UInt(1.W))) when(~dmactive || ~dmAuthenticated) { for (i <- 0 until 3) sbErrorReg(i) := 0.U }.otherwise { for (i <- 0 until 3) sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) || (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed Mux((tryWrEn || tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error Mux((tryWrEn || tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL } SBCSRdData := SBCSFieldsReg SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B SBCSRdData.sbbusy := sbBusy SBCSRdData.sberror := sbErrorReg.asUInt when (~dmAuthenticated) { // Read value must be 0 if not authenticated SBCSRdData := 0.U.asTypeOf(new SBCSFields()) } property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set") property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access") property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set") property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set") property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value") (sbcsfields, sbaddrfields, sbdatafields) } } class SBToTL(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1("debug")), requestFields = Seq(AMBAProtField())))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val rdEn = Input(Bool()) val wrEn = Input(Bool()) val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths val dataIn = Input(UInt(128.W)) val sizeIn = Input(UInt(3.W)) val rdLegal = Output(Bool()) val wrLegal = Output(Bool()) val rdDone = Output(Bool()) val wrDone = Output(Bool()) val respError = Output(Bool()) val dataOut = Output(UInt(8.W)) val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool())) val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W)) }) val rf_reset = IO(Input(Reset())) import SystemBusAccessState._ val (tl, edge) = node.out(0) val sbState = RegInit(0.U) // --- Drive payloads on bus to TileLink --- val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request d.ready := (sbState === SBReadResponse.id.U) || (sbState === SBWriteResponse.id.U) val muxedData = WireInit(0.U(8.W)) val requestValid = tl.a.valid val requestReady = tl.a.ready val responseValid = d.valid val responseReady = d.ready val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W)) val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W))) vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8*i+7,8*i) } muxedData := vecData(counter(log2Ceil(vecData.size)-1,0)) // Need an additional check to determine if address is safe for Get/Put val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8))) val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn) val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData) io.rdLegal := rdLegal_addr io.wrLegal := wrLegal_addr io.sbStateOut := sbState when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits } .otherwise { tl.a.bits := pfbits } tl.a.bits.user.lift(AMBAProt).foreach { x => x.bufferable := false.B x.modifiable := false.B x.readalloc := false.B x.writealloc := false.B x.privileged := true.B x.secure := true.B x.fetch := false.B } val respError = d.bits.denied || d.bits.corrupt io.respError := respError val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady val txLast = counter === ((1.U << io.sizeIn) - 1.U) counter := Mux((wrTxValid || rdTxValid) && txLast, 0.U, Mux((wrTxValid || rdTxValid) , counter+1.U, counter)) for (i <- 0 until (cfg.maxSupportedSBAccess/8)) { io.rdLoad(i) := rdTxValid && (counter === i.U) } // --- State Machine to interface with TileLink --- when (sbState === Idle.id.U){ sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U, Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState)) }.elsewhen (sbState === SBReadRequest.id.U){ sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState) }.elsewhen (sbState === SBWriteRequest.id.U){ sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState) }.elsewhen (sbState === SBReadResponse.id.U){ sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState) }.elsewhen (sbState === SBWriteResponse.id.U){ sbState := Mux(responseValid && responseReady, Idle.id.U, sbState) } io.rdDone := rdTxValid && txLast io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady io.dataOut := d.bits.data tl.a.valid := (sbState === SBReadRequest.id.U) || (sbState === SBWriteRequest.id.U) // Tie off unused channels tl.b.ready := false.B tl.c.valid := false.B tl.e.valid := false.B assert (sbState === Idle.id.U || sbState === SBReadRequest.id.U || sbState === SBWriteRequest.id.U || sbState === SBReadResponse.id.U || sbState === SBWriteResponse.id.U, "SBA state machine in undefined state") property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle") property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req") property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req") property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp") property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp") property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal") property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal") } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLDebugModuleInner( // @[Debug.scala:790:9] input clock, // @[Debug.scala:790:9] input reset, // @[Debug.scala:790:9] input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_dmactive, // @[Debug.scala:803:16] input io_innerCtrl_valid, // @[Debug.scala:803:16] input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16] input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16] input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16] input io_innerCtrl_bits_hasel, // @[Debug.scala:803:16] input io_innerCtrl_bits_hamask_0, // @[Debug.scala:803:16] input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16] output io_hgDebugInt_0, // @[Debug.scala:803:16] input io_hartIsInReset_0, // @[Debug.scala:803:16] input io_tl_clock, // @[Debug.scala:803:16] input io_tl_reset // @[Debug.scala:803:16] ); wire out_front_1_valid; // @[RegisterRouter.scala:87:24] wire out_front_1_ready; // @[RegisterRouter.scala:87:24] wire out_1_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_1_bits_index; // @[RegisterRouter.scala:73:18] wire in_1_bits_read; // @[RegisterRouter.scala:73:18] wire [7:0] _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:71] wire [2:0] _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:71] wire [15:0] _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:71] wire [7:0] _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:74] wire [2:0] _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:74] wire [15:0] _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:74] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [6:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire SBDATAWrEn_0; // @[SBA.scala:150:35] wire [31:0] SBDATARdData_1; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_0; // @[SBA.scala:145:35] wire SBADDRESSWrEn_0; // @[SBA.scala:108:38] wire [7:0] _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:65] wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41] wire [31:0] _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52] wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52] wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52] wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52] wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52] wire auto_sb2tlOpt_out_a_ready_0 = auto_sb2tlOpt_out_a_ready; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_valid_0 = auto_sb2tlOpt_out_d_valid; // @[Debug.scala:790:9] wire [2:0] auto_sb2tlOpt_out_d_bits_opcode_0 = auto_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] auto_sb2tlOpt_out_d_bits_param_0 = auto_sb2tlOpt_out_d_bits_param; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_d_bits_size_0 = auto_sb2tlOpt_out_d_bits_size; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_sink_0 = auto_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_denied_0 = auto_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_d_bits_data_0 = auto_sb2tlOpt_out_d_bits_data; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_corrupt_0 = auto_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[Debug.scala:790:9] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[Debug.scala:790:9] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[Debug.scala:790:9] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[Debug.scala:790:9] wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_a_bits_param_0 = auto_dmi_in_a_bits_param; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_a_bits_size_0 = auto_dmi_in_a_bits_size; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_source_0 = auto_dmi_in_a_bits_source; // @[Debug.scala:790:9] wire [8:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:790:9] wire [3:0] auto_dmi_in_a_bits_mask_0 = auto_dmi_in_a_bits_mask; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:790:9] wire auto_dmi_in_a_bits_corrupt_0 = auto_dmi_in_a_bits_corrupt; // @[Debug.scala:790:9] wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:790:9] wire io_dmactive_0 = io_dmactive; // @[Debug.scala:790:9] wire io_innerCtrl_valid_0 = io_innerCtrl_valid; // @[Debug.scala:790:9] wire io_innerCtrl_bits_resumereq_0 = io_innerCtrl_bits_resumereq; // @[Debug.scala:790:9] wire [9:0] io_innerCtrl_bits_hartsel_0 = io_innerCtrl_bits_hartsel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_ackhavereset_0 = io_innerCtrl_bits_ackhavereset; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hasel_0 = io_innerCtrl_bits_hasel; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hamask_0_0 = io_innerCtrl_bits_hamask_0; // @[Debug.scala:790:9] wire io_innerCtrl_bits_hrmask_0_0 = io_innerCtrl_bits_hrmask_0; // @[Debug.scala:790:9] wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:790:9] wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:790:9] wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_addr = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_ready = 1'h0; // @[Debug.scala:790:9] wire auto_custom_in_valid = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9] wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_addr = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_ready = 1'h0; // @[MixedNode.scala:551:17] wire customNodeIn_valid = 1'h0; // @[MixedNode.scala:551:17] wire _dmiProgramBufferRdEn_WIRE_0 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_1 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_2 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_3 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_4 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_5 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_6 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_7 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_8 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_9 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_10 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_11 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_12 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_13 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_14 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_15 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_16 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_17 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_18 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_19 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_20 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_21 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_22 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_23 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_24 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_25 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_26 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_27 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_28 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_29 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_30 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_31 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_32 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_33 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_34 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_35 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_36 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_37 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_38 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_39 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_40 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_41 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_42 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_43 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_44 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_45 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_46 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_47 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_48 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_49 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_50 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_51 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_52 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_53 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_54 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_55 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_56 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_57 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_58 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_59 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_60 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_61 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_62 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferRdEn_WIRE_63 = 1'h0; // @[Debug.scala:887:48] wire _dmiProgramBufferWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_32 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_33 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_34 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_35 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_36 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_37 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_38 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_39 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_40 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_41 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_42 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_43 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_44 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_45 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_46 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_47 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_48 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_49 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_50 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_51 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_52 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_53 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_54 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_55 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_56 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_57 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_58 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_59 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_60 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_61 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_62 = 1'h0; // @[Debug.scala:889:53] wire _dmiProgramBufferWrEnMaybe_WIRE_63 = 1'h0; // @[Debug.scala:889:53] wire _dmiAbstractDataRdEn_WIRE_0 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_1 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_2 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_3 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_4 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_5 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_6 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_7 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_8 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_9 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_10 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_11 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_12 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_13 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_14 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_15 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_16 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_17 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_18 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_19 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_20 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_21 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_22 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_23 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_24 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_25 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_26 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_27 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_28 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_29 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_30 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataRdEn_WIRE_31 = 1'h0; // @[Debug.scala:891:47] wire _dmiAbstractDataWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:893:52] wire _dmiAbstractDataWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:893:52] wire _hamaskFull_WIRE_0 = 1'h0; // @[Debug.scala:903:38] wire _hamaskWrSel_WIRE_0 = 1'h0; // @[Debug.scala:933:39] wire _hrReset_WIRE_0 = 1'h0; // @[Debug.scala:945:38] wire hrReset_0 = 1'h0; // @[Debug.scala:945:30] wire _hrDebugIntReg_WIRE_0 = 1'h0; // @[Debug.scala:961:42] wire _DMSTATUSRdData_WIRE_impebreak = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhavereset = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyresumeack = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allnonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anynonexistent = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyunavail = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyrunning = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_allhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_anyhalted = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authenticated = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_authbusy = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_hasresethaltreq = 1'h0; // @[Debug.scala:978:47] wire _DMSTATUSRdData_WIRE_confstrptrvalid = 1'h0; // @[Debug.scala:978:47] wire DMSTATUSRdData_impebreak = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyunavail = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_authbusy = 1'h0; // @[Debug.scala:978:34] wire DMSTATUSRdData_confstrptrvalid = 1'h0; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anynonexistent_T = 1'h0; // @[Debug.scala:988:57] wire _DMSTATUSRdData_allnonexistent_T = 1'h0; // @[Debug.scala:991:57] wire _DMSTATUSRdData_anyunavail_T = 1'h0; // @[package.scala:74:72] wire _DMCS2RdData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1025:47] wire _DMCS2RdData_WIRE_hgselect = 1'h0; // @[Debug.scala:1025:47] wire DMCS2RdData_hgwrite = 1'h0; // @[Debug.scala:1025:34] wire DMCS2RdData_hgselect = 1'h0; // @[Debug.scala:1025:34] wire _DMCS2WrData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1026:47] wire _DMCS2WrData_WIRE_hgselect = 1'h0; // @[Debug.scala:1026:47] wire DMCS2WrData_hgwrite = 1'h0; // @[Debug.scala:1026:34] wire DMCS2WrData_hgselect = 1'h0; // @[Debug.scala:1026:34] wire hgselectWrEn = 1'h0; // @[Debug.scala:1027:34] wire hgwriteWrEn = 1'h0; // @[Debug.scala:1028:34] wire haltgroupWrEn = 1'h0; // @[Debug.scala:1029:34] wire exttriggerWrEn = 1'h0; // @[Debug.scala:1030:34] wire _hgDebugInt_WIRE_0 = 1'h0; // @[Debug.scala:1031:42] wire hgDebugInt_0 = 1'h0; // @[Debug.scala:1031:34] wire _selectedHaltedStatus_T = 1'h0; // @[Debug.scala:1172:53] wire _selectedHaltedStatus_T_1 = 1'h0; // @[Debug.scala:1172:59] wire _selectedHaltedStatus_T_2 = 1'h0; // @[Debug.scala:1172:114] wire _selectedHaltedStatus_WIRE = 1'h0; wire _ABSTRACTCSReset_WIRE_busy = 1'h0; // @[Debug.scala:1179:48] wire _ABSTRACTCSReset_WIRE_reserved2 = 1'h0; // @[Debug.scala:1179:48] wire ABSTRACTCSReset_busy = 1'h0; // @[Debug.scala:1179:35] wire ABSTRACTCSReset_reserved2 = 1'h0; // @[Debug.scala:1179:35] wire _ABSTRACTCSWrData_WIRE_busy = 1'h0; // @[Debug.scala:1184:52] wire _ABSTRACTCSWrData_WIRE_reserved2 = 1'h0; // @[Debug.scala:1184:52] wire ABSTRACTCSWrData_busy = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSWrData_reserved2 = 1'h0; // @[Debug.scala:1184:39] wire ABSTRACTCSRdData_reserved2 = 1'h0; // @[Debug.scala:1185:39] wire ABSTRACTCSRdEn = 1'h0; // @[Debug.scala:1187:34] wire ABSTRACTAUTORdEn = 1'h0; // @[Debug.scala:1239:36] wire _dmiAbstractDataAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1257:53] wire _dmiAbstractDataAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1257:53] wire _dmiProgramBufferAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_32 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_33 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_34 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_35 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_36 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_37 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_38 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_39 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_40 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_41 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_42 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_43 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_44 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_45 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_46 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_47 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_48 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_49 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_50 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_51 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_52 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_53 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_54 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_55 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_56 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_57 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_58 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_59 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_60 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_61 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_62 = 1'h0; // @[Debug.scala:1260:54] wire _dmiProgramBufferAccessVec_WIRE_63 = 1'h0; // @[Debug.scala:1260:54] wire _autoexecData_WIRE_0 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_1 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_2 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_3 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_4 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_5 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_6 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecData_WIRE_7 = 1'h0; // @[Debug.scala:1267:41] wire _autoexecProg_WIRE_0 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_1 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_2 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_3 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_4 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_5 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_6 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_7 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_8 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_9 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_10 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_11 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_12 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_13 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_14 = 1'h0; // @[Debug.scala:1268:41] wire _autoexecProg_WIRE_15 = 1'h0; // @[Debug.scala:1268:41] wire authRdEnMaybe = 1'h0; // @[Debug.scala:1356:33] wire authWrEnMaybe = 1'h0; // @[Debug.scala:1357:33] wire _SBCSFieldsRegReset_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbbusy = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbreadondata = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:49:51] wire _SBCSFieldsRegReset_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:49:51] wire SBCSFieldsRegReset_sbbusyerror = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadonaddr = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbautoincrement = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbreadondata = 1'h0; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess128 = 1'h0; // @[SBA.scala:49:38] wire _SBCSRdData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbbusy = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:60:51] wire _SBCSRdData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:60:51] wire SBCSRdData_sbaccess128 = 1'h0; // @[SBA.scala:60:38] wire _SBCSWrData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbbusy = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_1 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_2 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_3 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_4 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_7 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_8 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_10 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_11 = 1'h0; // @[SBA.scala:63:61] wire _SBCSWrData_T_12 = 1'h0; // @[SBA.scala:63:61] wire SBCSWrData_sbbusy = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess128 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess64 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess32 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess16 = 1'h0; // @[SBA.scala:63:38] wire SBCSWrData_sbaccess8 = 1'h0; // @[SBA.scala:63:38] wire _SBADDRESSRdEn_WIRE_0 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_1 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_2 = 1'h0; // @[SBA.scala:107:46] wire _SBADDRESSRdEn_WIRE_3 = 1'h0; // @[SBA.scala:107:46] wire SBADDRESSRdEn_1 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_2 = 1'h0; // @[SBA.scala:107:38] wire SBADDRESSRdEn_3 = 1'h0; // @[SBA.scala:107:38] wire _SBADDRESSWrEn_WIRE_0 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_1 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_2 = 1'h0; // @[SBA.scala:108:46] wire _SBADDRESSWrEn_WIRE_3 = 1'h0; // @[SBA.scala:108:46] wire SBADDRESSWrEn_1 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_2 = 1'h0; // @[SBA.scala:108:38] wire SBADDRESSWrEn_3 = 1'h0; // @[SBA.scala:108:38] wire _SBDATARdEn_WIRE_0 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_1 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_2 = 1'h0; // @[SBA.scala:149:43] wire _SBDATARdEn_WIRE_3 = 1'h0; // @[SBA.scala:149:43] wire SBDATARdEn_2 = 1'h0; // @[SBA.scala:149:35] wire SBDATARdEn_3 = 1'h0; // @[SBA.scala:149:35] wire _SBDATAWrEn_WIRE_0 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_1 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_2 = 1'h0; // @[SBA.scala:150:43] wire _SBDATAWrEn_WIRE_3 = 1'h0; // @[SBA.scala:150:43] wire SBDATAWrEn_2 = 1'h0; // @[SBA.scala:150:35] wire SBDATAWrEn_3 = 1'h0; // @[SBA.scala:150:35] wire _sbAccessError_T_1 = 1'h0; // @[SBA.scala:182:88] wire _sbAccessError_T_2 = 1'h0; // @[SBA.scala:182:58] wire _sbAccessError_T_4 = 1'h0; // @[SBA.scala:183:88] wire _sbAccessError_T_5 = 1'h0; // @[SBA.scala:183:58] wire _sbAccessError_T_6 = 1'h0; // @[SBA.scala:182:97] wire _sbAccessError_T_8 = 1'h0; // @[SBA.scala:184:88] wire _sbAccessError_T_9 = 1'h0; // @[SBA.scala:184:58] wire _sbAccessError_T_10 = 1'h0; // @[SBA.scala:183:97] wire _sbAccessError_T_12 = 1'h0; // @[SBA.scala:185:88] wire _sbAccessError_T_13 = 1'h0; // @[SBA.scala:185:58] wire _sbAccessError_T_14 = 1'h0; // @[SBA.scala:184:97] wire _SBCSRdData_WIRE_1_sbbusyerror = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbbusy = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadonaddr = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbautoincrement = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbreadondata = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess128 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess64 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess32 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess16 = 1'h0; // @[SBA.scala:243:33] wire _SBCSRdData_WIRE_1_sbaccess8 = 1'h0; // @[SBA.scala:243:33] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_204 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_205 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire _jalAbstract_WIRE_imm3 = 1'h0; // @[Debug.scala:1497:66] wire _jalAbstract_WIRE_imm1 = 1'h0; // @[Debug.scala:1497:66] wire jalAbstract_imm3 = 1'h0; // @[Debug.scala:1497:32] wire jalAbstract_imm1 = 1'h0; // @[Debug.scala:1497:32] wire _immBits_T = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_1 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_2 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_6 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_7 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_8 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_9 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_10 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_11 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_12 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_13 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_14 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_15 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_16 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_17 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_18 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_19 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_T_20 = 1'h0; // @[Debug.scala:1575:48] wire _immBits_WIRE_0 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_1 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_2 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_6 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_7 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_8 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_9 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_10 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_11 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_12 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_13 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_14 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_15 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_16 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_17 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_18 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_19 = 1'h0; // @[Debug.scala:1575:39] wire _immBits_WIRE_20 = 1'h0; // @[Debug.scala:1575:39] wire immBits_0 = 1'h0; // @[Debug.scala:1575:31] wire immBits_1 = 1'h0; // @[Debug.scala:1575:31] wire immBits_2 = 1'h0; // @[Debug.scala:1575:31] wire immBits_6 = 1'h0; // @[Debug.scala:1575:31] wire immBits_7 = 1'h0; // @[Debug.scala:1575:31] wire immBits_8 = 1'h0; // @[Debug.scala:1575:31] wire immBits_9 = 1'h0; // @[Debug.scala:1575:31] wire immBits_10 = 1'h0; // @[Debug.scala:1575:31] wire immBits_11 = 1'h0; // @[Debug.scala:1575:31] wire immBits_12 = 1'h0; // @[Debug.scala:1575:31] wire immBits_13 = 1'h0; // @[Debug.scala:1575:31] wire immBits_14 = 1'h0; // @[Debug.scala:1575:31] wire immBits_15 = 1'h0; // @[Debug.scala:1575:31] wire immBits_16 = 1'h0; // @[Debug.scala:1575:31] wire immBits_17 = 1'h0; // @[Debug.scala:1575:31] wire immBits_18 = 1'h0; // @[Debug.scala:1575:31] wire immBits_19 = 1'h0; // @[Debug.scala:1575:31] wire immBits_20 = 1'h0; // @[Debug.scala:1575:31] wire _flags_WIRE_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_resume = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_1_go = 1'h0; // @[Debug.scala:1517:87] wire _flags_WIRE_2_0_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_0_go = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_resume = 1'h0; // @[Debug.scala:1517:33] wire _flags_WIRE_2_1_go = 1'h0; // @[Debug.scala:1517:33] wire flags_1_resume = 1'h0; // @[Debug.scala:1517:25] wire flags_1_go = 1'h0; // @[Debug.scala:1517:25] wire componentSel = 1'h0; // @[Debug.scala:1523:34] wire _out_rifireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_419 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_423 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_427 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_431 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_435 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_439 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_443 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_447 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_451 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_455 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_459 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_463 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_467 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_519 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_421 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_425 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_429 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_433 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_437 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_441 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_445 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_449 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_453 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_457 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_461 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_465 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_469 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_521 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_5 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] autoIncrementedAddr_hi = 64'h0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_hi = 64'h0; // @[SBA.scala:132:14] wire [63:0] sb2tlOpt_io_addrIn_hi_1 = 64'h0; // @[SBA.scala:133:10] wire [63:0] sb2tlOpt_io_dataIn_hi = 64'h0; // @[SBA.scala:175:59] wire [63:0] sb2tlOpt_io_dataIn_hi_1 = 64'h0; // @[SBA.scala:175:85] wire [63:0] _out_out_bits_data_WIRE_3_11 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_12 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_13 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_14 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_15 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_16 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_17 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_18 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_19 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_20 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_21 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_22 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_23 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_24 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_25 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_26 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_27 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_28 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_29 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_30 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_31 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_32 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_33 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_34 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_35 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_36 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_37 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_38 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_39 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_40 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_41 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_42 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_43 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_44 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_45 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_46 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_47 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_48 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_49 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_50 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_51 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_52 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_53 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_54 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_55 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_56 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_57 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_58 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_59 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_60 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_61 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_62 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_63 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_64 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_65 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_66 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_67 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_68 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_69 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_70 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_71 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_72 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_73 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_74 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_75 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_76 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_77 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_78 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_79 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_80 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_81 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_82 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_83 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_84 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_85 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_86 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_87 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_88 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_89 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_90 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_91 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_92 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_93 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_94 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_95 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_97 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_98 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_99 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_100 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_101 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_102 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_116 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_117 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_118 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_119 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_120 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_121 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_122 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_123 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_124 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_125 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_126 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_127 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] auto_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:790:9] wire [2:0] _ABSTRACTCSReset_WIRE_reserved0 = 3'h0; // @[Debug.scala:1179:48] wire [2:0] _ABSTRACTCSReset_WIRE_cmderr = 3'h0; // @[Debug.scala:1179:48] wire [2:0] ABSTRACTCSReset_reserved0 = 3'h0; // @[Debug.scala:1179:35] wire [2:0] ABSTRACTCSReset_cmderr = 3'h0; // @[Debug.scala:1179:35] wire [2:0] _ABSTRACTCSWrData_WIRE_reserved0 = 3'h0; // @[Debug.scala:1184:52] wire [2:0] _ABSTRACTCSWrData_WIRE_cmderr = 3'h0; // @[Debug.scala:1184:52] wire [2:0] ABSTRACTCSWrData_reserved0 = 3'h0; // @[Debug.scala:1184:39] wire [2:0] ABSTRACTCSRdData_reserved0 = 3'h0; // @[Debug.scala:1185:39] wire [2:0] _SBCSFieldsRegReset_WIRE_sbversion = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sbaccess = 3'h0; // @[SBA.scala:49:51] wire [2:0] _SBCSFieldsRegReset_WIRE_sberror = 3'h0; // @[SBA.scala:49:51] wire [2:0] SBCSFieldsRegReset_sberror = 3'h0; // @[SBA.scala:49:38] wire [2:0] _SBCSRdData_WIRE_sbversion = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sbaccess = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSRdData_WIRE_sberror = 3'h0; // @[SBA.scala:60:51] wire [2:0] _SBCSWrData_WIRE_sbversion = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sbaccess = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_WIRE_sberror = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_6 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_9 = 3'h0; // @[SBA.scala:63:61] wire [2:0] _SBCSWrData_T_14 = 3'h0; // @[SBA.scala:63:61] wire [2:0] SBCSWrData_sbversion = 3'h0; // @[SBA.scala:63:38] wire [2:0] _SBCSRdData_WIRE_1_sbversion = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sbaccess = 3'h0; // @[SBA.scala:243:33] wire [2:0] _SBCSRdData_WIRE_1_sberror = 3'h0; // @[SBA.scala:243:33] wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [2:0] jalAbstract_imm0_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] jalAbstract_imm1_hi_hi = 3'h0; // @[package.scala:45:27] wire [2:0] nop_funct3 = 3'h0; // @[Debug.scala:1623:19] wire [2:0] _nop_WIRE_funct3 = 3'h0; // @[Debug.scala:1624:46] wire [2:0] isa_funct3 = 3'h0; // @[Debug.scala:1629:19] wire [2:0] _isa_WIRE_funct3 = 3'h0; // @[Debug.scala:1630:47] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire auto_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:790:9] wire io_innerCtrl_ready = 1'h1; // @[Debug.scala:790:9] wire hamaskFull_0 = 1'h1; // @[Debug.scala:903:30] wire DMSTATUSRdData_authenticated = 1'h1; // @[Debug.scala:978:34] wire DMSTATUSRdData_hasresethaltreq = 1'h1; // @[Debug.scala:978:34] wire _DMSTATUSRdData_anyhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T = 1'h1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T = 1'h1; // @[package.scala:79:37] wire SBCSFieldsRegReset_sbaccess64 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess32 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess16 = 1'h1; // @[SBA.scala:49:38] wire SBCSFieldsRegReset_sbaccess8 = 1'h1; // @[SBA.scala:49:38] wire SBCSRdData_sbaccess64 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess32 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess16 = 1'h1; // @[SBA.scala:60:38] wire SBCSRdData_sbaccess8 = 1'h1; // @[SBA.scala:60:38] wire _sbAccessError_T_16 = 1'h1; // @[SBA.scala:186:88] wire _out_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_T_439 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _immBits_T_3 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_4 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_T_5 = 1'h1; // @[Debug.scala:1575:48] wire _immBits_WIRE_3 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_4 = 1'h1; // @[Debug.scala:1575:39] wire _immBits_WIRE_5 = 1'h1; // @[Debug.scala:1575:39] wire immBits_3 = 1'h1; // @[Debug.scala:1575:31] wire immBits_4 = 1'h1; // @[Debug.scala:1575:31] wire immBits_5 = 1'h1; // @[Debug.scala:1575:31] wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_16 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_17 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_18 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_19 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_20 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_21 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_22 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_23 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_24 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_25 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_26 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_27 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_28 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_29 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_30 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_31 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_34 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_35 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_36 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_37 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_38 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_39 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_40 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_41 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_42 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_43 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_44 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_45 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_46 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_47 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_48 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_49 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_50 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_51 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_52 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_53 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_54 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_55 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_56 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_57 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_58 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_59 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_60 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_61 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_62 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_63 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_64 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_65 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_66 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_67 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_68 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_69 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_70 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_71 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_72 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_73 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_74 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_75 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_76 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_77 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_78 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_79 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_80 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_81 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_82 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_83 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_84 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_85 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_86 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_87 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_88 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_89 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_90 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_91 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_92 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_93 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_94 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_95 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_97 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_98 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_99 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_100 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_101 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_102 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_116 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_117 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_118 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_119 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_120 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_121 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_122 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_123 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_124 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_125 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_126 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_127 = 1'h1; // @[MuxLiteral.scala:49:48] wire [31:0] SBCSWrDataVal = 32'h0; // @[SBA.scala:62:38] wire [31:0] _SBCSWrData_WIRE_1 = 32'h0; // @[SBA.scala:63:61] wire [31:0] _SBADDRESSWrData_WIRE_0 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_1 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_2 = 32'h0; // @[SBA.scala:106:46] wire [31:0] _SBADDRESSWrData_WIRE_3 = 32'h0; // @[SBA.scala:106:46] wire [31:0] SBADDRESSWrData_1 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_2 = 32'h0; // @[SBA.scala:106:38] wire [31:0] SBADDRESSWrData_3 = 32'h0; // @[SBA.scala:106:38] wire [31:0] _SBDATARdData_WIRE_0 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_1 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_2 = 32'h0; // @[SBA.scala:145:43] wire [31:0] _SBDATARdData_WIRE_3 = 32'h0; // @[SBA.scala:145:43] wire [31:0] SBDATARdData_2 = 32'h0; // @[SBA.scala:145:35] wire [31:0] SBDATARdData_3 = 32'h0; // @[SBA.scala:145:35] wire [31:0] _SBDATAWrData_WIRE_0 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_1 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_2 = 32'h0; // @[SBA.scala:147:43] wire [31:0] _SBDATAWrData_WIRE_3 = 32'h0; // @[SBA.scala:147:43] wire [31:0] SBDATAWrData_2 = 32'h0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_3 = 32'h0; // @[SBA.scala:147:35] wire [31:0] sb2tlOpt_io_dataIn_hi_lo = 32'h0; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_hi_hi = 32'h0; // @[SBA.scala:175:85] wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_2 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_12 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_13 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_14 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_15 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_16 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_18 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_20 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_21 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_25 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_26 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_27 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_28 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_29 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_30 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_31 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_48 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_49 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_50 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_51 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_52 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_53 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_54 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_55 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_58 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_59 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_62 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_63 = 32'h0; // @[MuxLiteral.scala:49:48] wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_420 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_578 = 32'h0; // @[RegisterRouter.scala:87:24] wire [5:0] _SBCSFieldsRegReset_WIRE_reserved0 = 6'h0; // @[SBA.scala:49:51] wire [5:0] SBCSFieldsRegReset_reserved0 = 6'h0; // @[SBA.scala:49:38] wire [5:0] _SBCSRdData_WIRE_reserved0 = 6'h0; // @[SBA.scala:60:51] wire [5:0] SBCSRdData_reserved0 = 6'h0; // @[SBA.scala:60:38] wire [5:0] _SBCSWrData_WIRE_reserved0 = 6'h0; // @[SBA.scala:63:61] wire [5:0] _SBCSWrData_T_13 = 6'h0; // @[SBA.scala:63:61] wire [5:0] SBCSWrData_reserved0 = 6'h0; // @[SBA.scala:63:38] wire [5:0] _SBCSRdData_WIRE_1_reserved0 = 6'h0; // @[SBA.scala:243:33] wire [5:0] _flags_WIRE_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_1_reserved = 6'h0; // @[Debug.scala:1517:87] wire [5:0] _flags_WIRE_2_0_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] _flags_WIRE_2_1_reserved = 6'h0; // @[Debug.scala:1517:33] wire [5:0] flags_0_reserved = 6'h0; // @[Debug.scala:1517:25] wire [5:0] flags_1_reserved = 6'h0; // @[Debug.scala:1517:25] wire [3:0] _DMSTATUSRdData_WIRE_version = 4'h0; // @[Debug.scala:978:47] wire [3:0] _DMCS2RdData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1025:47] wire [3:0] DMCS2RdData_exttrigger = 4'h0; // @[Debug.scala:1025:34] wire [3:0] _DMCS2WrData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1026:47] wire [3:0] DMCS2WrData_exttrigger = 4'h0; // @[Debug.scala:1026:34] wire [3:0] _ABSTRACTCSReset_WIRE_reserved3 = 4'h0; // @[Debug.scala:1179:48] wire [3:0] _ABSTRACTCSReset_WIRE_datacount = 4'h0; // @[Debug.scala:1179:48] wire [3:0] ABSTRACTCSReset_reserved3 = 4'h0; // @[Debug.scala:1179:35] wire [3:0] _ABSTRACTCSWrData_WIRE_reserved3 = 4'h0; // @[Debug.scala:1184:52] wire [3:0] _ABSTRACTCSWrData_WIRE_datacount = 4'h0; // @[Debug.scala:1184:52] wire [3:0] ABSTRACTCSWrData_reserved3 = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSWrData_datacount = 4'h0; // @[Debug.scala:1184:39] wire [3:0] ABSTRACTCSRdData_reserved3 = 4'h0; // @[Debug.scala:1185:39] wire [3:0] _ABSTRACTAUTOReset_WIRE_reserved0 = 4'h0; // @[Debug.scala:1234:54] wire [3:0] ABSTRACTAUTOReset_reserved0 = 4'h0; // @[Debug.scala:1234:41] wire [3:0] _ABSTRACTAUTOWrData_WIRE_reserved0 = 4'h0; // @[Debug.scala:1236:54] wire [3:0] ABSTRACTAUTOWrData_reserved0 = 4'h0; // @[Debug.scala:1236:41] wire [3:0] ABSTRACTAUTORdData_reserved0 = 4'h0; // @[Debug.scala:1237:41] wire [3:0] jalAbstract_imm2_lo = 4'h0; // @[package.scala:45:27] wire [3:0] jalAbstract_imm2_hi = 4'h0; // @[package.scala:45:27] wire [7:0] _out_T_1223 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1224 = 8'h8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_86 = 8'h8; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_85 = 5'h8; // @[RegisterRouter.scala:87:24] wire [3:0] ABSTRACTCSReset_datacount = 4'h8; // @[Debug.scala:1179:35] wire [3:0] ABSTRACTCSRdData_datacount = 4'h8; // @[Debug.scala:1185:39] wire [3:0] _out_T_1214 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1215 = 4'h8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_85 = 4'h8; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReset_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:54] wire [15:0] ABSTRACTAUTOReset_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:41] wire [15:0] _ABSTRACTAUTOWrData_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1236:54] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_lo_hi = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_lo = 16'h0; // @[SBA.scala:175:85] wire [15:0] sb2tlOpt_io_dataIn_hi_hi_hi = 16'h0; // @[SBA.scala:175:85] wire [95:0] _sb2tlOpt_io_addrIn_T = 96'h0; // @[SBA.scala:132:14] wire [2:0] SBCSFieldsRegReset_sbversion = 3'h1; // @[SBA.scala:49:38] wire [2:0] SBCSRdData_sbversion = 3'h1; // @[SBA.scala:60:38] wire [10:0] _ABSTRACTCSReset_WIRE_reserved1 = 11'h0; // @[Debug.scala:1179:48] wire [10:0] ABSTRACTCSReset_reserved1 = 11'h0; // @[Debug.scala:1179:35] wire [10:0] _ABSTRACTCSWrData_WIRE_reserved1 = 11'h0; // @[Debug.scala:1184:52] wire [10:0] ABSTRACTCSWrData_reserved1 = 11'h0; // @[Debug.scala:1184:39] wire [10:0] ABSTRACTCSRdData_reserved1 = 11'h0; // @[Debug.scala:1185:39] wire [4:0] ABSTRACTCSReset_progbufsize = 5'h10; // @[Debug.scala:1179:35] wire [4:0] ABSTRACTCSRdData_progbufsize = 5'h10; // @[Debug.scala:1185:39] wire [7:0] _COMMANDReset_WIRE_cmdtype = 8'h0; // @[Debug.scala:1276:45] wire [7:0] COMMANDReset_cmdtype = 8'h0; // @[Debug.scala:1276:32] wire [7:0] _jalAbstract_WIRE_imm2 = 8'h0; // @[Debug.scala:1497:66] wire [7:0] jalAbstract_imm2 = 8'h0; // @[Debug.scala:1497:32] wire [7:0] _jalAbstract_imm2_T = 8'h0; // @[package.scala:45:27] wire [6:0] SBCSFieldsRegReset_sbasize = 7'h20; // @[SBA.scala:49:38] wire [6:0] SBCSRdData_sbasize = 7'h20; // @[SBA.scala:60:38] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] _DMSTATUSRdData_WIRE_reserved1 = 2'h0; // @[Debug.scala:978:47] wire [1:0] DMSTATUSRdData_reserved1 = 2'h0; // @[Debug.scala:978:34] wire [1:0] _haltedBitRegs_T_4 = 2'h0; // @[Debug.scala:1330:43] wire [1:0] _haltedBitRegs_T_6 = 2'h0; // @[Debug.scala:1330:69] wire [1:0] _resumeReqRegs_T_3 = 2'h0; // @[Debug.scala:1338:43] wire [1:0] _resumeReqRegs_T_5 = 2'h0; // @[Debug.scala:1338:69] wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [1:0] jalAbstract_imm0_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm0_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm1_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] jalAbstract_imm2_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_3_96 = 64'h380006F; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_3_10 = 64'h100073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_349 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4404 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4405 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_9 = 64'h100026237B200073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_592 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6965 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6966 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_8 = 64'h7B20247310802423; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_866 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9839 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9840 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_7 = 64'hF140247330000067; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_1055 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11815 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11816 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_6 = 64'h100022237B202473; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_258 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3452 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3453 = 64'h4086300147413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_5 = 64'h4086300147413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_391 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4836 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4837 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_4 = 64'hFE0408E300347413; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_641 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7469 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7470 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_3 = 64'h4004440310802023; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_950 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10719 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10720 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_2 = 64'hF14024737B241073; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_202 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2860 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2861 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_1 = 64'hFF0000F0440006F; // @[MuxLiteral.scala:49:48] wire [63:0] out_prepend_511 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6103 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6104 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_0 = 64'h380006F00C0006F; // @[MuxLiteral.scala:49:48] wire [55:0] out_prepend_1054 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11806 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11807 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1055 = 56'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1053 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11797 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11798 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1054 = 48'h22237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1052 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11788 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11789 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1053 = 40'h237B202473; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1051 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11779 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11780 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1052 = 32'h7B202473; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1050 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11770 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11771 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1051 = 24'h202473; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1049 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11761 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11762 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1050 = 16'h2473; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4341 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4342 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_343 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6328 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6329 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_533 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10656 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10657 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_944 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11752 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11753 = 8'h73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1049 = 8'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_949 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10710 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10711 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_950 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_948 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10701 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10702 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_949 = 48'h24737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_947 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10692 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10693 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_948 = 40'h737B241073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_946 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10683 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10684 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_947 = 32'h7B241073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_945 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10674 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10675 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_946 = 24'h241073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_944 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10665 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10666 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_945 = 16'h1073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_865 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9830 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9831 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_866 = 56'h40247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_864 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9821 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9822 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_865 = 48'h247330000067; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_863 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9812 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9813 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_864 = 40'h7330000067; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_862 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9803 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9804 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_863 = 32'h30000067; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_861 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9794 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9795 = 24'h67; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_862 = 24'h67; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_860 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9785 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9786 = 16'h67; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_861 = 16'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9776 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9777 = 8'h67; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_860 = 8'h67; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_640 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7460 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7461 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_641 = 56'h4440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_639 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7451 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7452 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_640 = 48'h440310802023; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_638 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7442 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7443 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_639 = 40'h310802023; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_637 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7433 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7434 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_638 = 32'h10802023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_636 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7424 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7425 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_637 = 24'h802023; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_635 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7415 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7416 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_636 = 16'h2023; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6902 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6903 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_586 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7406 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7407 = 8'h23; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_635 = 8'h23; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_591 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6956 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6957 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_592 = 56'h20247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_590 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6947 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6948 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_591 = 48'h247310802423; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_589 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6938 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6939 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_590 = 40'h7310802423; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_588 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6929 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6930 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_589 = 32'h10802423; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_587 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6920 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6921 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_588 = 24'h802423; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_586 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6911 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6912 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_587 = 16'h2423; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5142 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_5143 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6821 = 42'h0; // @[RegisterRouter.scala:87:24] wire [41:0] _out_T_6822 = 42'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_420 = 33'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_578 = 33'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _jalAbstract_WIRE_imm0 = 10'h0; // @[Debug.scala:1497:66] wire [9:0] _jalAbstract_imm1_T = 10'h0; // @[package.scala:45:27] wire [9:0] _out_T_5133 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_5134 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6812 = 10'h0; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_6813 = 10'h0; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_535 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6355 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6356 = 32'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_534 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6346 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6347 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_535 = 24'h100073; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_343 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4350 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4351 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_344 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_533 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6337 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6338 = 16'h73; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_534 = 16'h73; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_510 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6094 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6095 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_511 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_509 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6085 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6086 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_510 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_508 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6076 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6077 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_509 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_507 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6067 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6068 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_508 = 32'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_506 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6058 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6059 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_507 = 24'hC0006F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_196 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2806 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2807 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_197 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_505 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6049 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6050 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_506 = 16'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2797 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2798 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_196 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6040 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6041 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_505 = 8'h6F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5943 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5944 = 32'h380006F; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_390 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4827 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4828 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_391 = 56'h408E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_389 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4818 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4819 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_390 = 48'h8E300347413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_388 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4809 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4810 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_389 = 40'hE300347413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_387 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4800 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4801 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_388 = 32'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_386 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4791 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4792 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_387 = 24'h347413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_252 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3398 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3399 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_253 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_385 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4782 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4783 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_386 = 16'h7413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3389 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3390 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_252 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4773 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4774 = 8'h13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_385 = 8'h13; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_348 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4395 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4396 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_349 = 56'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_347 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4386 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4387 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_348 = 48'h26237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_346 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4377 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4378 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_347 = 40'h237B200073; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_345 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4368 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4369 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_346 = 32'h7B200073; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_344 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4359 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4360 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_345 = 24'h200073; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_257 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3443 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3444 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_258 = 56'h4086300147413; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_256 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3434 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3435 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_257 = 48'h86300147413; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_255 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3425 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3426 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_256 = 40'h6300147413; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_254 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3416 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3417 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_255 = 32'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_253 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3407 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3408 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_254 = 24'h147413; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_201 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2851 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2852 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_202 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_200 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2842 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2843 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_201 = 48'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_199 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2833 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2834 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_200 = 40'hF0440006F; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_198 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2824 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2825 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_199 = 32'h440006F; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_197 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2815 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2816 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_198 = 24'h40006F; // @[RegisterRouter.scala:87:24] wire [8:0] out_maskMatch_1 = 9'h100; // @[RegisterRouter.scala:87:24] wire [11:0] hi = 12'h38; // @[Debug.scala:1697:55] wire [10:0] hi_hi = 11'h1C; // @[Debug.scala:1697:55] wire [19:0] lo = 20'h6F; // @[Debug.scala:1697:55] wire [12:0] lo_hi = 13'h0; // @[Debug.scala:1697:55] wire [31:0] _abstractGeneratedMem_0_T_3 = 32'h13; // @[Debug.scala:1642:15] wire [31:0] _abstractGeneratedMem_1_T = 32'h13; // @[Debug.scala:1645:15] wire [19:0] abstractGeneratedMem_0_hi_2 = 20'h0; // @[Debug.scala:1642:15] wire [19:0] abstractGeneratedMem_1_hi = 20'h0; // @[Debug.scala:1645:15] wire [16:0] abstractGeneratedMem_0_hi_hi_2 = 17'h0; // @[Debug.scala:1642:15] wire [16:0] abstractGeneratedMem_1_hi_hi = 17'h0; // @[Debug.scala:1645:15] wire [11:0] abstractGeneratedMem_0_lo_2 = 12'h13; // @[Debug.scala:1642:15] wire [11:0] abstractGeneratedMem_1_lo = 12'h13; // @[Debug.scala:1645:15] wire [6:0] abstractGeneratedMem_0_inst_1_opcode = 7'h23; // @[Debug.scala:1601:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_opcode = 7'h23; // @[Debug.scala:1604:55] wire [4:0] _DMCS2RdData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1025:47] wire [4:0] DMCS2RdData_haltgroup = 5'h0; // @[Debug.scala:1025:34] wire [4:0] _DMCS2WrData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1026:47] wire [4:0] DMCS2WrData_haltgroup = 5'h0; // @[Debug.scala:1026:34] wire [4:0] _ABSTRACTCSReset_WIRE_progbufsize = 5'h0; // @[Debug.scala:1179:48] wire [4:0] _ABSTRACTCSWrData_WIRE_progbufsize = 5'h0; // @[Debug.scala:1184:52] wire [4:0] ABSTRACTCSWrData_progbufsize = 5'h0; // @[Debug.scala:1184:39] wire [4:0] _jalAbstract_WIRE_rd = 5'h0; // @[Debug.scala:1497:66] wire [4:0] jalAbstract_rd = 5'h0; // @[Debug.scala:1497:32] wire [4:0] jalAbstract_imm0_hi = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_lo = 5'h0; // @[package.scala:45:27] wire [4:0] jalAbstract_imm1_hi = 5'h0; // @[package.scala:45:27] wire [4:0] nop_rs1 = 5'h0; // @[Debug.scala:1623:19] wire [4:0] nop_rd = 5'h0; // @[Debug.scala:1623:19] wire [4:0] _nop_WIRE_rs1 = 5'h0; // @[Debug.scala:1624:46] wire [4:0] _nop_WIRE_rd = 5'h0; // @[Debug.scala:1624:46] wire [4:0] isa_rs1 = 5'h0; // @[Debug.scala:1629:19] wire [4:0] isa_rd = 5'h0; // @[Debug.scala:1629:19] wire [4:0] _isa_WIRE_rs1 = 5'h0; // @[Debug.scala:1630:47] wire [4:0] _isa_WIRE_rd = 5'h0; // @[Debug.scala:1630:47] wire [4:0] abstractGeneratedMem_0_inst_rs1 = 5'h0; // @[Debug.scala:1589:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rs1 = 5'h0; // @[Debug.scala:1592:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rd = 5'h0; // @[Debug.scala:1592:55] wire [4:0] abstractGeneratedMem_0_inst_1_rs1 = 5'h0; // @[Debug.scala:1601:22] wire [4:0] abstractGeneratedMem_0_inst_1_immlo = 5'h0; // @[Debug.scala:1601:22] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs2 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs1 = 5'h0; // @[Debug.scala:1604:55] wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immlo = 5'h0; // @[Debug.scala:1604:55] wire [2:0] SBCSFieldsRegReset_sbaccess = 3'h2; // @[SBA.scala:49:38] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_funct3 = 3'h2; // @[Debug.scala:1592:55] wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_funct3 = 3'h2; // @[Debug.scala:1604:55] wire [6:0] _SBCSFieldsRegReset_WIRE_sbasize = 7'h0; // @[SBA.scala:49:51] wire [6:0] _SBCSRdData_WIRE_sbasize = 7'h0; // @[SBA.scala:60:51] wire [6:0] _SBCSWrData_WIRE_sbasize = 7'h0; // @[SBA.scala:63:61] wire [6:0] _SBCSWrData_T_5 = 7'h0; // @[SBA.scala:63:61] wire [6:0] SBCSWrData_sbasize = 7'h0; // @[SBA.scala:63:38] wire [6:0] _SBCSRdData_WIRE_1_sbasize = 7'h0; // @[SBA.scala:243:33] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immhi = 7'h0; // @[Debug.scala:1604:55] wire [6:0] abstractGeneratedMem_0_inst_1_immhi = 7'h1C; // @[Debug.scala:1601:22] wire [16:0] abstractGeneratedMem_0_hi_hi = 17'h7000; // @[Debug.scala:1597:12] wire [6:0] abstractGeneratedMem_0_inst_opcode = 7'h3; // @[Debug.scala:1589:22] wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_opcode = 7'h3; // @[Debug.scala:1592:55] wire [11:0] _ABSTRACTAUTOReset_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1234:54] wire [11:0] ABSTRACTAUTOReset_autoexecdata = 12'h0; // @[Debug.scala:1234:41] wire [11:0] _ABSTRACTAUTOWrData_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1236:54] wire [11:0] nop_imm = 12'h0; // @[Debug.scala:1623:19] wire [11:0] _nop_WIRE_imm = 12'h0; // @[Debug.scala:1624:46] wire [11:0] isa_imm = 12'h0; // @[Debug.scala:1629:19] wire [11:0] _isa_WIRE_imm = 12'h0; // @[Debug.scala:1630:47] wire [11:0] _abstractGeneratedMem_0_inst_opcode_WIRE_imm = 12'h0; // @[Debug.scala:1592:55] wire [11:0] abstractGeneratedMem_0_inst_imm = 12'h380; // @[Debug.scala:1589:22] wire [6:0] isa_opcode = 7'h1B; // @[Debug.scala:1629:19] wire [6:0] _isa_WIRE_opcode = 7'h1B; // @[Debug.scala:1630:47] wire [6:0] nop_opcode = 7'h13; // @[Debug.scala:1623:19] wire [6:0] _nop_WIRE_opcode = 7'h13; // @[Debug.scala:1624:46] wire [9:0] jalAbstract_imm0 = 10'h1C; // @[Debug.scala:1497:32] wire [9:0] _jalAbstract_imm0_T = 10'h1C; // @[package.scala:45:27] wire [4:0] jalAbstract_imm0_lo = 5'h1C; // @[package.scala:45:27] wire [2:0] out_prepend_25 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_456 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_457 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] _out_prepend_T_26 = 3'h7; // @[RegisterRouter.scala:87:24] wire [2:0] jalAbstract_imm0_lo_hi = 3'h7; // @[package.scala:45:27] wire [1:0] out_prepend_24 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_447 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_448 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] _out_prepend_T_25 = 2'h3; // @[RegisterRouter.scala:87:24] wire [1:0] jalAbstract_imm0_lo_hi_hi = 2'h3; // @[package.scala:45:27] wire [20:0] immWire = 21'h38; // @[Debug.scala:1574:31] wire [6:0] _jalAbstract_WIRE_opcode = 7'h6F; // @[Debug.scala:1497:66] wire [6:0] jalAbstract_opcode = 7'h6F; // @[Debug.scala:1497:32] wire [7:0] out_prepend_64 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_991 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_992 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_65 = 8'hA2; // @[RegisterRouter.scala:87:24] wire [6:0] out_prepend_63 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_982 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_983 = 7'h22; // @[RegisterRouter.scala:87:24] wire [6:0] _out_prepend_T_64 = 7'h22; // @[RegisterRouter.scala:87:24] wire [5:0] out_prepend_62 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_973 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_974 = 6'h22; // @[RegisterRouter.scala:87:24] wire [5:0] _out_prepend_T_63 = 6'h22; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_61 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_964 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_965 = 5'h2; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_62 = 5'h2; // @[RegisterRouter.scala:87:24] wire [3:0] DMSTATUSRdData_version = 4'h2; // @[Debug.scala:978:34] wire [3:0] _out_T_955 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_956 = 4'h2; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_61 = 4'h2; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_28 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_483 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_484 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_29 = 12'h40F; // @[RegisterRouter.scala:87:24] wire [4:0] out_prepend_27 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_474 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_475 = 5'hF; // @[RegisterRouter.scala:87:24] wire [4:0] _out_prepend_T_28 = 5'hF; // @[RegisterRouter.scala:87:24] wire [3:0] out_prepend_26 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_465 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_466 = 4'hF; // @[RegisterRouter.scala:87:24] wire [3:0] _out_prepend_T_27 = 4'hF; // @[RegisterRouter.scala:87:24] wire [6:0] out_maskMatch = 7'h40; // @[RegisterRouter.scala:87:24] wire [1:0] _haltedBitRegs_T_3 = 2'h2; // @[Debug.scala:1330:45] wire [1:0] _resumeReqRegs_T_2 = 2'h2; // @[Debug.scala:1338:45] wire [1:0] hartHaltedIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] hartResumingIdIndex = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _haltedBitRegs_T = 2'h1; // @[Debug.scala:1327:43] wire [23:0] _COMMANDReset_WIRE_control = 24'h0; // @[Debug.scala:1276:45] wire [23:0] COMMANDReset_control = 24'h0; // @[Debug.scala:1276:32] wire [20:0] _DMCS2RdData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1025:47] wire [20:0] DMCS2RdData_reserved0 = 21'h0; // @[Debug.scala:1025:34] wire [20:0] _DMCS2WrData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1026:47] wire [20:0] DMCS2WrData_reserved0 = 21'h0; // @[Debug.scala:1026:34] wire [8:0] _DMSTATUSRdData_WIRE_reserved0 = 9'h0; // @[Debug.scala:978:47] wire [8:0] DMSTATUSRdData_reserved0 = 9'h0; // @[Debug.scala:978:34] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[Debug.scala:790:9] wire [11:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[Debug.scala:790:9] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[Debug.scala:790:9] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17] wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:790:9] wire [2:0] dmiNodeIn_a_bits_param = auto_dmi_in_a_bits_param_0; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_a_bits_size = auto_dmi_in_a_bits_size_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_source = auto_dmi_in_a_bits_source_0; // @[Debug.scala:790:9] wire [8:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:790:9] wire [3:0] dmiNodeIn_a_bits_mask = auto_dmi_in_a_bits_mask_0; // @[Debug.scala:790:9] wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:790:9] wire dmiNodeIn_a_bits_corrupt = auto_dmi_in_a_bits_corrupt_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:790:9] wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] dmiNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire dmiNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire _resumereq_T = io_innerCtrl_valid_0; // @[Decoupled.scala:51:35] wire hrDebugInt_0; // @[Debug.scala:946:26] wire [2:0] auto_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:790:9] wire [3:0] auto_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:790:9] wire [31:0] auto_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:790:9] wire [7:0] auto_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_a_valid_0; // @[Debug.scala:790:9] wire auto_sb2tlOpt_out_d_ready_0; // @[Debug.scala:790:9] wire auto_tl_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_tl_in_d_bits_size_0; // @[Debug.scala:790:9] wire [10:0] auto_tl_in_d_bits_source_0; // @[Debug.scala:790:9] wire [63:0] auto_tl_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_tl_in_d_valid_0; // @[Debug.scala:790:9] wire auto_dmi_in_a_ready_0; // @[Debug.scala:790:9] wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:790:9] wire [1:0] auto_dmi_in_d_bits_size_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_bits_source_0; // @[Debug.scala:790:9] wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:790:9] wire auto_dmi_in_d_valid_0; // @[Debug.scala:790:9] wire io_hgDebugInt_0_0; // @[Debug.scala:790:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:790:9] wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = dmiNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire in_bits_extra_tlrr_extra_source = dmiNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [3:0] in_bits_mask = dmiNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_size_0 = dmiNodeIn_d_bits_size; // @[Debug.scala:790:9] wire dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_dmi_in_d_bits_source_0 = dmiNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:790:9] wire in_1_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[Debug.scala:790:9] wire in_1_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_1_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_1_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_1_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_1_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_1_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_1_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[Debug.scala:790:9] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[Debug.scala:790:9] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[Debug.scala:790:9] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[Debug.scala:790:9] wire [63:0] out_1_bits_data; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_bits_data_0 = tlNodeIn_d_bits_data; // @[Debug.scala:790:9] reg haltedBitRegs; // @[Debug.scala:861:31] wire _DMSTATUSRdData_anyhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :995:77] wire _DMSTATUSRdData_anyrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :996:77] wire _DMSTATUSRdData_allhalted_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1001:79] wire _DMSTATUSRdData_allrunning_T_1 = haltedBitRegs; // @[Debug.scala:861:31, :1002:79] wire _haltedStatus_0_T = haltedBitRegs; // @[Debug.scala:861:31, :1163:43] wire _hartHalted_T = haltedBitRegs; // @[Debug.scala:861:31, :1734:37] reg resumeReqRegs; // @[Debug.scala:863:31] wire _flags_resume_T = resumeReqRegs; // @[Debug.scala:863:31, :1524:80] reg haveResetBitRegs; // @[Debug.scala:865:31] wire _DMSTATUSRdData_anyhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :997:58] wire _DMSTATUSRdData_allhavereset_T = haveResetBitRegs; // @[Debug.scala:865:31, :1003:60] wire resumeAcks; // @[Debug.scala:869:32] wire _DMSTATUSRdData_anyresumeack_T = resumeAcks; // @[Debug.scala:869:32, :998:52] wire _DMSTATUSRdData_allresumeack_T = resumeAcks; // @[Debug.scala:869:32, :1004:54] wire out_f_woready_681; // @[RegisterRouter.scala:87:24] wire hartHaltedWrEn; // @[Debug.scala:875:36] wire [9:0] _out_T_6805; // @[RegisterRouter.scala:87:24] wire [9:0] hartHaltedId; // @[Debug.scala:876:36] wire out_f_woready_682; // @[RegisterRouter.scala:87:24] wire hartGoingWrEn; // @[Debug.scala:877:36] wire [9:0] _out_T_6814; // @[RegisterRouter.scala:87:24] wire [9:0] hartGoingId; // @[Debug.scala:878:36] wire out_f_woready_498; // @[RegisterRouter.scala:87:24] wire hartResumingWrEn; // @[Debug.scala:879:36] wire [9:0] _out_T_5126; // @[RegisterRouter.scala:87:24] wire [9:0] hartResumingId; // @[Debug.scala:880:36] wire out_f_woready_499; // @[RegisterRouter.scala:87:24] wire hartExceptionWrEn; // @[Debug.scala:881:36] wire [9:0] _out_T_5135; // @[RegisterRouter.scala:87:24] wire [9:0] hartExceptionId; // @[Debug.scala:882:36] wire out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_roready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferRdEn_0; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_1; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_2; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_3; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_4; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_5; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_6; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_7; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_8; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_9; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_10; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_11; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_12; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_13; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_14; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_15; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_16; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_17; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_18; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_19; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_20; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_21; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_22; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_23; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_24; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_25; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_26; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_27; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_28; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_29; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_30; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_31; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_32; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_33; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_34; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_35; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_36; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_37; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_38; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_39; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_40; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_41; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_42; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_43; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_44; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_45; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_46; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_47; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_48; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_49; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_50; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_51; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_52; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_53; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_54; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_55; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_56; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_57; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_58; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_59; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_60; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_61; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_62; // @[Debug.scala:887:40] wire dmiProgramBufferRdEn_63; // @[Debug.scala:887:40] wire _dmiProgramBufferAccessLegal_T; // @[Debug.scala:1746:50] wire dmiProgramBufferAccessLegal; // @[Debug.scala:888:47] wire out_f_woready_101; // @[RegisterRouter.scala:87:24] wire out_f_woready_102; // @[RegisterRouter.scala:87:24] wire out_f_woready_103; // @[RegisterRouter.scala:87:24] wire out_f_woready_104; // @[RegisterRouter.scala:87:24] wire out_f_woready_73; // @[RegisterRouter.scala:87:24] wire out_f_woready_74; // @[RegisterRouter.scala:87:24] wire out_f_woready_75; // @[RegisterRouter.scala:87:24] wire out_f_woready_76; // @[RegisterRouter.scala:87:24] wire out_f_woready_105; // @[RegisterRouter.scala:87:24] wire out_f_woready_106; // @[RegisterRouter.scala:87:24] wire out_f_woready_107; // @[RegisterRouter.scala:87:24] wire out_f_woready_108; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_141; // @[RegisterRouter.scala:87:24] wire out_f_woready_142; // @[RegisterRouter.scala:87:24] wire out_f_woready_143; // @[RegisterRouter.scala:87:24] wire out_f_woready_144; // @[RegisterRouter.scala:87:24] wire out_f_woready_55; // @[RegisterRouter.scala:87:24] wire out_f_woready_56; // @[RegisterRouter.scala:87:24] wire out_f_woready_57; // @[RegisterRouter.scala:87:24] wire out_f_woready_58; // @[RegisterRouter.scala:87:24] wire out_f_woready_69; // @[RegisterRouter.scala:87:24] wire out_f_woready_70; // @[RegisterRouter.scala:87:24] wire out_f_woready_71; // @[RegisterRouter.scala:87:24] wire out_f_woready_72; // @[RegisterRouter.scala:87:24] wire out_f_woready_124; // @[RegisterRouter.scala:87:24] wire out_f_woready_125; // @[RegisterRouter.scala:87:24] wire out_f_woready_126; // @[RegisterRouter.scala:87:24] wire out_f_woready_127; // @[RegisterRouter.scala:87:24] wire out_f_woready_136; // @[RegisterRouter.scala:87:24] wire out_f_woready_137; // @[RegisterRouter.scala:87:24] wire out_f_woready_138; // @[RegisterRouter.scala:87:24] wire out_f_woready_139; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_48; // @[RegisterRouter.scala:87:24] wire out_f_woready_49; // @[RegisterRouter.scala:87:24] wire out_f_woready_50; // @[RegisterRouter.scala:87:24] wire out_f_woready_51; // @[RegisterRouter.scala:87:24] wire out_f_woready_132; // @[RegisterRouter.scala:87:24] wire out_f_woready_133; // @[RegisterRouter.scala:87:24] wire out_f_woready_134; // @[RegisterRouter.scala:87:24] wire out_f_woready_135; // @[RegisterRouter.scala:87:24] wire out_f_woready_116; // @[RegisterRouter.scala:87:24] wire out_f_woready_117; // @[RegisterRouter.scala:87:24] wire out_f_woready_118; // @[RegisterRouter.scala:87:24] wire out_f_woready_119; // @[RegisterRouter.scala:87:24] wire out_f_woready_77; // @[RegisterRouter.scala:87:24] wire out_f_woready_78; // @[RegisterRouter.scala:87:24] wire out_f_woready_79; // @[RegisterRouter.scala:87:24] wire out_f_woready_80; // @[RegisterRouter.scala:87:24] wire out_f_woready_59; // @[RegisterRouter.scala:87:24] wire out_f_woready_60; // @[RegisterRouter.scala:87:24] wire out_f_woready_61; // @[RegisterRouter.scala:87:24] wire out_f_woready_62; // @[RegisterRouter.scala:87:24] wire out_f_woready_25; // @[RegisterRouter.scala:87:24] wire out_f_woready_26; // @[RegisterRouter.scala:87:24] wire out_f_woready_27; // @[RegisterRouter.scala:87:24] wire out_f_woready_28; // @[RegisterRouter.scala:87:24] wire dmiProgramBufferWrEnMaybe_0; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_1; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_2; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_3; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_4; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_5; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_6; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_7; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_8; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_9; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_10; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_11; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_12; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_13; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_14; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_15; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_16; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_17; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_18; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_19; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_20; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_21; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_22; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_23; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_24; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_25; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_26; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_27; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_28; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_29; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_30; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_31; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_32; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_33; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_34; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_35; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_36; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_37; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_38; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_39; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_40; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_41; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_42; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_43; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_44; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_45; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_46; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_47; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_48; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_49; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_50; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_51; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_52; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_53; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_54; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_55; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_56; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_57; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_58; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_59; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_60; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_61; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_62; // @[Debug.scala:889:45] wire dmiProgramBufferWrEnMaybe_63; // @[Debug.scala:889:45] wire out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_roready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataRdEn_0; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_1; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_2; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_3; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_4; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_5; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_6; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_7; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_8; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_9; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_10; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_11; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_12; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_13; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_14; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_15; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_16; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_17; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_18; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_19; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_20; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_21; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_22; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_23; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_24; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_25; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_26; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_27; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_28; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_29; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_30; // @[Debug.scala:891:39] wire dmiAbstractDataRdEn_31; // @[Debug.scala:891:39] wire _dmiAbstractDataAccessLegal_T; // @[Debug.scala:1745:50] wire dmiAbstractDataAccessLegal; // @[Debug.scala:892:46] wire out_f_woready_21; // @[RegisterRouter.scala:87:24] wire out_f_woready_22; // @[RegisterRouter.scala:87:24] wire out_f_woready_23; // @[RegisterRouter.scala:87:24] wire out_f_woready_24; // @[RegisterRouter.scala:87:24] wire out_f_woready; // @[RegisterRouter.scala:87:24] wire out_f_woready_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_64; // @[RegisterRouter.scala:87:24] wire out_f_woready_65; // @[RegisterRouter.scala:87:24] wire out_f_woready_66; // @[RegisterRouter.scala:87:24] wire out_f_woready_67; // @[RegisterRouter.scala:87:24] wire out_f_woready_120; // @[RegisterRouter.scala:87:24] wire out_f_woready_121; // @[RegisterRouter.scala:87:24] wire out_f_woready_122; // @[RegisterRouter.scala:87:24] wire out_f_woready_123; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire out_f_woready_18; // @[RegisterRouter.scala:87:24] wire out_f_woready_19; // @[RegisterRouter.scala:87:24] wire out_f_woready_20; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_29; // @[RegisterRouter.scala:87:24] wire out_f_woready_30; // @[RegisterRouter.scala:87:24] wire out_f_woready_31; // @[RegisterRouter.scala:87:24] wire out_f_woready_32; // @[RegisterRouter.scala:87:24] wire out_f_woready_128; // @[RegisterRouter.scala:87:24] wire out_f_woready_129; // @[RegisterRouter.scala:87:24] wire out_f_woready_130; // @[RegisterRouter.scala:87:24] wire out_f_woready_131; // @[RegisterRouter.scala:87:24] wire dmiAbstractDataWrEnMaybe_0; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_1; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_2; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_3; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_4; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_5; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_6; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_7; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_8; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_9; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_10; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_11; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_12; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_13; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_14; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_15; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_16; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_17; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_18; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_19; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_20; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_21; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_22; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_23; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_24; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_25; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_26; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_27; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_28; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_29; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_30; // @[Debug.scala:893:44] wire dmiAbstractDataWrEnMaybe_31; // @[Debug.scala:893:44] wire _hamaskWrSel_0_T_1; // @[Debug.scala:935:78] wire hamaskWrSel_0; // @[Debug.scala:933:31] wire _hamaskWrSel_0_T = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:790:9, :935:61] assign _hamaskWrSel_0_T_1 = _hamaskWrSel_0_T; // @[Debug.scala:935:{61,78}] assign hamaskWrSel_0 = _hamaskWrSel_0_T_1; // @[Debug.scala:933:31, :935:78] assign io_hgDebugInt_0_0 = hrDebugInt_0; // @[Debug.scala:790:9, :946:26] reg hrmaskReg_0; // @[Debug.scala:947:29] wire _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] wire hartIsInResetSync_0; // @[Debug.scala:948:33] assign hartIsInResetSync_0 = _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24] reg hrDebugIntReg_0; // @[Debug.scala:961:34] assign hrDebugInt_0 = hrDebugIntReg_0; // @[Debug.scala:946:26, :961:34] wire _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:991:75] wire DMSTATUSRdData_allhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhavereset; // @[Debug.scala:978:34] wire DMSTATUSRdData_allresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyresumeack; // @[Debug.scala:978:34] wire DMSTATUSRdData_allnonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34] wire DMSTATUSRdData_allunavail; // @[Debug.scala:978:34] wire DMSTATUSRdData_allrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyrunning; // @[Debug.scala:978:34] wire DMSTATUSRdData_allhalted; // @[Debug.scala:978:34] wire DMSTATUSRdData_anyhalted; // @[Debug.scala:978:34] wire resumereq = _resumereq_T & io_innerCtrl_bits_resumereq_0; // @[Decoupled.scala:51:35] assign DMSTATUSRdData_anynonexistent = _DMSTATUSRdData_anynonexistent_T; // @[Debug.scala:978:34, :988:57] wire _DMSTATUSRdData_allnonexistent_T_1 = ~hamaskFull_0; // @[Debug.scala:903:30, :991:78] assign _DMSTATUSRdData_allnonexistent_T_2 = _DMSTATUSRdData_allnonexistent_T & _DMSTATUSRdData_allnonexistent_T_1; // @[Debug.scala:991:{57,75,78}] assign DMSTATUSRdData_allnonexistent = _DMSTATUSRdData_allnonexistent_T_2; // @[Debug.scala:978:34, :991:75] wire _DMSTATUSRdData_anyhalted_T_2 = _DMSTATUSRdData_anyhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhalted_T_3 = _DMSTATUSRdData_anyhalted_T_2 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhalted = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhalted_T_3; // @[package.scala:74:72] wire _DMSTATUSRdData_anyrunning_T_2 = ~_DMSTATUSRdData_anyrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_anyrunning_T_3 = _DMSTATUSRdData_anyrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_anyrunning_T_4 = _DMSTATUSRdData_anyrunning_T_3 & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyrunning = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyrunning_T_4; // @[package.scala:74:72] wire _DMSTATUSRdData_anyhavereset_T_1 = _DMSTATUSRdData_anyhavereset_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyhavereset = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyhavereset_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_anyresumeack_T_1 = _DMSTATUSRdData_anyresumeack_T & hamaskFull_0; // @[package.scala:74:72] assign DMSTATUSRdData_anyresumeack = ~DMSTATUSRdData_allnonexistent & _DMSTATUSRdData_anyresumeack_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allunavail_T = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allunavail_T_1 = _DMSTATUSRdData_allunavail_T; // @[package.scala:75:75, :79:37] wire _GEN = ~DMSTATUSRdData_allnonexistent & ~DMSTATUSRdData_anynonexistent; // @[Debug.scala:978:34, :993:{13,45}, :999:{15,47}, :1000:39] assign DMSTATUSRdData_allunavail = _GEN & _DMSTATUSRdData_allunavail_T_1; // @[package.scala:75:75] wire _DMSTATUSRdData_allhalted_T_2 = _DMSTATUSRdData_allhalted_T_1; // @[package.scala:74:72] wire _DMSTATUSRdData_allhalted_T_3 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhalted_T_4 = _DMSTATUSRdData_allhalted_T_2 | _DMSTATUSRdData_allhalted_T_3; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allhalted = _GEN & _DMSTATUSRdData_allhalted_T_4; // @[package.scala:75:75] wire _DMSTATUSRdData_allrunning_T_2 = ~_DMSTATUSRdData_allrunning_T_1; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_3 = _DMSTATUSRdData_allrunning_T_2; // @[package.scala:74:72, :79:37] wire _DMSTATUSRdData_allrunning_T_4 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allrunning_T_5 = _DMSTATUSRdData_allrunning_T_3 | _DMSTATUSRdData_allrunning_T_4; // @[package.scala:74:72, :75:75, :79:37] assign DMSTATUSRdData_allrunning = _GEN & _DMSTATUSRdData_allrunning_T_5; // @[package.scala:75:75] wire _DMSTATUSRdData_allhavereset_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allhavereset_T_2 = _DMSTATUSRdData_allhavereset_T | _DMSTATUSRdData_allhavereset_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allhavereset = _GEN & _DMSTATUSRdData_allhavereset_T_2; // @[package.scala:75:75] wire _DMSTATUSRdData_allresumeack_T_1 = ~hamaskFull_0; // @[package.scala:79:37] wire _DMSTATUSRdData_allresumeack_T_2 = _DMSTATUSRdData_allresumeack_T | _DMSTATUSRdData_allresumeack_T_1; // @[package.scala:75:75, :79:37] assign DMSTATUSRdData_allresumeack = _GEN & _DMSTATUSRdData_allresumeack_T_2; // @[package.scala:75:75] wire _haveResetBitRegs_T = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50] wire _haveResetBitRegs_T_1 = haveResetBitRegs & _haveResetBitRegs_T; // @[Debug.scala:865:31, :1017:{47,50}] wire _haveResetBitRegs_T_2 = _haveResetBitRegs_T_1 | hartIsInResetSync_0; // @[Debug.scala:948:33, :1017:{47,74}] wire _haveResetBitRegs_T_3 = haveResetBitRegs | hartIsInResetSync_0; // @[Debug.scala:865:31, :948:33, :1019:46] wire [31:0] haltedStatus_0; // @[Debug.scala:1159:30] wire [31:0] selectedHaltedStatus = haltedStatus_0; // @[Debug.scala:1159:30, :1172:35] assign haltedStatus_0 = {31'h0, _haltedStatus_0_T}; // @[Debug.scala:1159:30, :1163:{26,43}] wire haltedSummary = |haltedStatus_0; // @[Debug.scala:1159:30, :1169:48] wire [31:0] _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] HALTSUM1RdData_haltsum1; // @[Debug.scala:1170:48] wire [31:0] _out_T_1598 = HALTSUM1RdData_haltsum1; // @[RegisterRouter.scala:87:24] assign _HALTSUM1RdData_T = _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48] assign _HALTSUM1RdData_WIRE = {31'h0, haltedSummary}; // @[Debug.scala:1169:48, :1170:48] assign HALTSUM1RdData_haltsum1 = _HALTSUM1RdData_T; // @[Debug.scala:1170:48] wire [31:0] _HALTSUM0RdData_WIRE = selectedHaltedStatus; // @[Debug.scala:1172:35, :1173:55] wire [31:0] _HALTSUM0RdData_T; // @[Debug.scala:1173:55] wire [31:0] HALTSUM0RdData_haltsum0; // @[Debug.scala:1173:55] wire [31:0] _out_T_946 = HALTSUM0RdData_haltsum0; // @[RegisterRouter.scala:87:24] assign _HALTSUM0RdData_T = _HALTSUM0RdData_WIRE; // @[Debug.scala:1173:55] assign HALTSUM0RdData_haltsum0 = _HALTSUM0RdData_T; // @[Debug.scala:1173:55] reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34] wire [2:0] ABSTRACTCSRdData_cmderr = ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34, :1185:39] wire [2:0] _out_T_1225; // @[RegisterRouter.scala:87:24] wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39] wire abstractCommandBusy; // @[Debug.scala:1220:39] wire ABSTRACTCSRdData_busy; // @[Debug.scala:1185:39] wire out_f_woready_111; // @[RegisterRouter.scala:87:24] wire ABSTRACTCSWrEnMaybe; // @[Debug.scala:1188:39] wire _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1742:44] wire ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39] wire ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala:1188:39, :1190:39, :1191:51] wire _errorBusy_T_16; // @[Debug.scala:1752:74] wire errorBusy; // @[Debug.scala:1195:36] wire errorException; // @[Debug.scala:1196:36] wire errorUnsupported; // @[Debug.scala:1197:36] wire errorHaltResume; // @[Debug.scala:1198:36] wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39, :1214:58] wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala:1183:34, :1214:{56,58}] wire _abstractCommandBusy_T; // @[Debug.scala:1740:42] assign ABSTRACTCSRdData_busy = abstractCommandBusy; // @[Debug.scala:1185:39, :1220:39] reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36] wire [15:0] ABSTRACTAUTORdData_autoexecprogbuf = ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36, :1237:41] reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36] wire [11:0] ABSTRACTAUTORdData_autoexecdata = ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36, :1237:41] wire [15:0] _out_T_642; // @[RegisterRouter.scala:87:24] wire [15:0] _ABSTRACTAUTOReg_autoexecprogbuf_T = ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41, :1249:79] wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala:1236:41] wire [11:0] _out_T_631 = ABSTRACTAUTORdData_autoexecdata; // @[RegisterRouter.scala:87:24] wire out_f_woready_52; // @[RegisterRouter.scala:87:24] wire autoexecdataWrEnMaybe; // @[Debug.scala:1240:41] wire out_f_woready_54; // @[RegisterRouter.scala:87:24] wire autoexecprogbufWrEnMaybe; // @[Debug.scala:1241:44] wire _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1744:44] wire ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41] wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = {4'h0, ABSTRACTAUTOWrData_autoexecdata[7:0]}; // @[Debug.scala:1236:41, :1252:73] wire dmiAbstractDataAccessVec_0; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45] wire dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45] assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 | dmiAbstractDataRdEn_1; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 | dmiAbstractDataRdEn_2; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 | dmiAbstractDataRdEn_3; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 | dmiAbstractDataRdEn_4; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_5 = dmiAbstractDataWrEnMaybe_5 | dmiAbstractDataRdEn_5; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_6 = dmiAbstractDataWrEnMaybe_6 | dmiAbstractDataRdEn_6; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_7 = dmiAbstractDataWrEnMaybe_7 | dmiAbstractDataRdEn_7; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 | dmiAbstractDataRdEn_8; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_9 = dmiAbstractDataWrEnMaybe_9 | dmiAbstractDataRdEn_9; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_10 = dmiAbstractDataWrEnMaybe_10 | dmiAbstractDataRdEn_10; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_11 = dmiAbstractDataWrEnMaybe_11 | dmiAbstractDataRdEn_11; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 | dmiAbstractDataRdEn_12; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_13 = dmiAbstractDataWrEnMaybe_13 | dmiAbstractDataRdEn_13; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_14 = dmiAbstractDataWrEnMaybe_14 | dmiAbstractDataRdEn_14; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_15 = dmiAbstractDataWrEnMaybe_15 | dmiAbstractDataRdEn_15; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 | dmiAbstractDataRdEn_16; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_17 = dmiAbstractDataWrEnMaybe_17 | dmiAbstractDataRdEn_17; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_18 = dmiAbstractDataWrEnMaybe_18 | dmiAbstractDataRdEn_18; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_19 = dmiAbstractDataWrEnMaybe_19 | dmiAbstractDataRdEn_19; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 | dmiAbstractDataRdEn_20; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_21 = dmiAbstractDataWrEnMaybe_21 | dmiAbstractDataRdEn_21; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_22 = dmiAbstractDataWrEnMaybe_22 | dmiAbstractDataRdEn_22; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_23 = dmiAbstractDataWrEnMaybe_23 | dmiAbstractDataRdEn_23; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 | dmiAbstractDataRdEn_24; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_25 = dmiAbstractDataWrEnMaybe_25 | dmiAbstractDataRdEn_25; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_26 = dmiAbstractDataWrEnMaybe_26 | dmiAbstractDataRdEn_26; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_27 = dmiAbstractDataWrEnMaybe_27 | dmiAbstractDataRdEn_27; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 | dmiAbstractDataRdEn_28; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_29 = dmiAbstractDataWrEnMaybe_29 | dmiAbstractDataRdEn_29; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_30 = dmiAbstractDataWrEnMaybe_30 | dmiAbstractDataRdEn_30; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] assign dmiAbstractDataAccessVec_31 = dmiAbstractDataWrEnMaybe_31 | dmiAbstractDataRdEn_31; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105] wire dmiProgramBufferAccessVec_0; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46] wire dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46] assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 | dmiProgramBufferRdEn_1; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 | dmiProgramBufferRdEn_2; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 | dmiProgramBufferRdEn_3; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 | dmiProgramBufferRdEn_5; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 | dmiProgramBufferRdEn_6; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 | dmiProgramBufferRdEn_7; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 | dmiProgramBufferRdEn_9; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 | dmiProgramBufferRdEn_10; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 | dmiProgramBufferRdEn_11; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 | dmiProgramBufferRdEn_13; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 | dmiProgramBufferRdEn_14; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 | dmiProgramBufferRdEn_15; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 | dmiProgramBufferRdEn_17; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 | dmiProgramBufferRdEn_18; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 | dmiProgramBufferRdEn_19; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 | dmiProgramBufferRdEn_21; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 | dmiProgramBufferRdEn_22; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 | dmiProgramBufferRdEn_23; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 | dmiProgramBufferRdEn_25; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 | dmiProgramBufferRdEn_26; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 | dmiProgramBufferRdEn_27; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 | dmiProgramBufferRdEn_29; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 | dmiProgramBufferRdEn_30; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 | dmiProgramBufferRdEn_31; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 | dmiProgramBufferRdEn_33; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 | dmiProgramBufferRdEn_34; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 | dmiProgramBufferRdEn_35; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 | dmiProgramBufferRdEn_37; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 | dmiProgramBufferRdEn_38; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 | dmiProgramBufferRdEn_39; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 | dmiProgramBufferRdEn_41; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 | dmiProgramBufferRdEn_42; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 | dmiProgramBufferRdEn_43; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 | dmiProgramBufferRdEn_45; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 | dmiProgramBufferRdEn_46; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 | dmiProgramBufferRdEn_47; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 | dmiProgramBufferRdEn_49; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 | dmiProgramBufferRdEn_50; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 | dmiProgramBufferRdEn_51; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 | dmiProgramBufferRdEn_53; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 | dmiProgramBufferRdEn_54; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 | dmiProgramBufferRdEn_55; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 | dmiProgramBufferRdEn_57; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 | dmiProgramBufferRdEn_58; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 | dmiProgramBufferRdEn_59; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 | dmiProgramBufferRdEn_61; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 | dmiProgramBufferRdEn_62; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 | dmiProgramBufferRdEn_63; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108] wire _dmiAbstractDataAccess_T = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_1 = _dmiAbstractDataAccess_T | dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_2 = _dmiAbstractDataAccess_T_1 | dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_3 = _dmiAbstractDataAccess_T_2 | dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_4 = _dmiAbstractDataAccess_T_3 | dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_5 = _dmiAbstractDataAccess_T_4 | dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_6 = _dmiAbstractDataAccess_T_5 | dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_7 = _dmiAbstractDataAccess_T_6 | dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_8 = _dmiAbstractDataAccess_T_7 | dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_9 = _dmiAbstractDataAccess_T_8 | dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_10 = _dmiAbstractDataAccess_T_9 | dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_11 = _dmiAbstractDataAccess_T_10 | dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_12 = _dmiAbstractDataAccess_T_11 | dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_13 = _dmiAbstractDataAccess_T_12 | dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_14 = _dmiAbstractDataAccess_T_13 | dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_15 = _dmiAbstractDataAccess_T_14 | dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_16 = _dmiAbstractDataAccess_T_15 | dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_17 = _dmiAbstractDataAccess_T_16 | dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_18 = _dmiAbstractDataAccess_T_17 | dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_19 = _dmiAbstractDataAccess_T_18 | dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_20 = _dmiAbstractDataAccess_T_19 | dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_21 = _dmiAbstractDataAccess_T_20 | dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_22 = _dmiAbstractDataAccess_T_21 | dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_23 = _dmiAbstractDataAccess_T_22 | dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_24 = _dmiAbstractDataAccess_T_23 | dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_25 = _dmiAbstractDataAccess_T_24 | dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_26 = _dmiAbstractDataAccess_T_25 | dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_27 = _dmiAbstractDataAccess_T_26 | dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_28 = _dmiAbstractDataAccess_T_27 | dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45, :1263:68] wire _dmiAbstractDataAccess_T_29 = _dmiAbstractDataAccess_T_28 | dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45, :1263:68] wire dmiAbstractDataAccess = _dmiAbstractDataAccess_T_29 | dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45, :1263:68] wire _dmiProgramBufferAccess_T = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_1 = _dmiProgramBufferAccess_T | dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_2 = _dmiProgramBufferAccess_T_1 | dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_3 = _dmiProgramBufferAccess_T_2 | dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_4 = _dmiProgramBufferAccess_T_3 | dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_5 = _dmiProgramBufferAccess_T_4 | dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_6 = _dmiProgramBufferAccess_T_5 | dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_7 = _dmiProgramBufferAccess_T_6 | dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_8 = _dmiProgramBufferAccess_T_7 | dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_9 = _dmiProgramBufferAccess_T_8 | dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_10 = _dmiProgramBufferAccess_T_9 | dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_11 = _dmiProgramBufferAccess_T_10 | dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_12 = _dmiProgramBufferAccess_T_11 | dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_13 = _dmiProgramBufferAccess_T_12 | dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_14 = _dmiProgramBufferAccess_T_13 | dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_15 = _dmiProgramBufferAccess_T_14 | dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_16 = _dmiProgramBufferAccess_T_15 | dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_17 = _dmiProgramBufferAccess_T_16 | dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_18 = _dmiProgramBufferAccess_T_17 | dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_19 = _dmiProgramBufferAccess_T_18 | dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_20 = _dmiProgramBufferAccess_T_19 | dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_21 = _dmiProgramBufferAccess_T_20 | dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_22 = _dmiProgramBufferAccess_T_21 | dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_23 = _dmiProgramBufferAccess_T_22 | dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_24 = _dmiProgramBufferAccess_T_23 | dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_25 = _dmiProgramBufferAccess_T_24 | dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_26 = _dmiProgramBufferAccess_T_25 | dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_27 = _dmiProgramBufferAccess_T_26 | dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_28 = _dmiProgramBufferAccess_T_27 | dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_29 = _dmiProgramBufferAccess_T_28 | dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_30 = _dmiProgramBufferAccess_T_29 | dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_31 = _dmiProgramBufferAccess_T_30 | dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_32 = _dmiProgramBufferAccess_T_31 | dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_33 = _dmiProgramBufferAccess_T_32 | dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_34 = _dmiProgramBufferAccess_T_33 | dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_35 = _dmiProgramBufferAccess_T_34 | dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_36 = _dmiProgramBufferAccess_T_35 | dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_37 = _dmiProgramBufferAccess_T_36 | dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_38 = _dmiProgramBufferAccess_T_37 | dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_39 = _dmiProgramBufferAccess_T_38 | dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_40 = _dmiProgramBufferAccess_T_39 | dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_41 = _dmiProgramBufferAccess_T_40 | dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_42 = _dmiProgramBufferAccess_T_41 | dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_43 = _dmiProgramBufferAccess_T_42 | dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_44 = _dmiProgramBufferAccess_T_43 | dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_45 = _dmiProgramBufferAccess_T_44 | dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_46 = _dmiProgramBufferAccess_T_45 | dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_47 = _dmiProgramBufferAccess_T_46 | dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_48 = _dmiProgramBufferAccess_T_47 | dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_49 = _dmiProgramBufferAccess_T_48 | dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_50 = _dmiProgramBufferAccess_T_49 | dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_51 = _dmiProgramBufferAccess_T_50 | dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_52 = _dmiProgramBufferAccess_T_51 | dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_53 = _dmiProgramBufferAccess_T_52 | dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_54 = _dmiProgramBufferAccess_T_53 | dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_55 = _dmiProgramBufferAccess_T_54 | dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_56 = _dmiProgramBufferAccess_T_55 | dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_57 = _dmiProgramBufferAccess_T_56 | dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_58 = _dmiProgramBufferAccess_T_57 | dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_58 | dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_60 = _dmiProgramBufferAccess_T_59 | dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46, :1264:69] wire _dmiProgramBufferAccess_T_61 = _dmiProgramBufferAccess_T_60 | dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46, :1264:69] wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_61 | dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46, :1264:69] wire _autoexecData_0_T; // @[Debug.scala:1269:140] wire _autoexecData_1_T; // @[Debug.scala:1269:140] wire _autoexecData_2_T; // @[Debug.scala:1269:140] wire _autoexecData_3_T; // @[Debug.scala:1269:140] wire _autoexecData_4_T; // @[Debug.scala:1269:140] wire _autoexecData_5_T; // @[Debug.scala:1269:140] wire _autoexecData_6_T; // @[Debug.scala:1269:140] wire _autoexecData_7_T; // @[Debug.scala:1269:140] wire autoexecData_0; // @[Debug.scala:1267:33] wire autoexecData_1; // @[Debug.scala:1267:33] wire autoexecData_2; // @[Debug.scala:1267:33] wire autoexecData_3; // @[Debug.scala:1267:33] wire autoexecData_4; // @[Debug.scala:1267:33] wire autoexecData_5; // @[Debug.scala:1267:33] wire autoexecData_6; // @[Debug.scala:1267:33] wire autoexecData_7; // @[Debug.scala:1267:33] wire _autoexecProg_0_T; // @[Debug.scala:1270:144] wire _autoexecProg_1_T; // @[Debug.scala:1270:144] wire _autoexecProg_2_T; // @[Debug.scala:1270:144] wire _autoexecProg_3_T; // @[Debug.scala:1270:144] wire _autoexecProg_4_T; // @[Debug.scala:1270:144] wire _autoexecProg_5_T; // @[Debug.scala:1270:144] wire _autoexecProg_6_T; // @[Debug.scala:1270:144] wire _autoexecProg_7_T; // @[Debug.scala:1270:144] wire _autoexecProg_8_T; // @[Debug.scala:1270:144] wire _autoexecProg_9_T; // @[Debug.scala:1270:144] wire _autoexecProg_10_T; // @[Debug.scala:1270:144] wire _autoexecProg_11_T; // @[Debug.scala:1270:144] wire _autoexecProg_12_T; // @[Debug.scala:1270:144] wire _autoexecProg_13_T; // @[Debug.scala:1270:144] wire _autoexecProg_14_T; // @[Debug.scala:1270:144] wire _autoexecProg_15_T; // @[Debug.scala:1270:144] wire autoexecProg_0; // @[Debug.scala:1268:33] wire autoexecProg_1; // @[Debug.scala:1268:33] wire autoexecProg_2; // @[Debug.scala:1268:33] wire autoexecProg_3; // @[Debug.scala:1268:33] wire autoexecProg_4; // @[Debug.scala:1268:33] wire autoexecProg_5; // @[Debug.scala:1268:33] wire autoexecProg_6; // @[Debug.scala:1268:33] wire autoexecProg_7; // @[Debug.scala:1268:33] wire autoexecProg_8; // @[Debug.scala:1268:33] wire autoexecProg_9; // @[Debug.scala:1268:33] wire autoexecProg_10; // @[Debug.scala:1268:33] wire autoexecProg_11; // @[Debug.scala:1268:33] wire autoexecProg_12; // @[Debug.scala:1268:33] wire autoexecProg_13; // @[Debug.scala:1268:33] wire autoexecProg_14; // @[Debug.scala:1268:33] wire autoexecProg_15; // @[Debug.scala:1268:33] assign _autoexecData_0_T = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_0 = _autoexecData_0_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_1_T = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_1 = _autoexecData_1_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_2_T = dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_2 = _autoexecData_2_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_3_T = dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_3 = _autoexecData_3_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_4_T = dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_4 = _autoexecData_4_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_5_T = dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_5 = _autoexecData_5_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_6_T = dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_6 = _autoexecData_6_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecData_7_T = dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}] assign autoexecData_7 = _autoexecData_7_T; // @[Debug.scala:1267:33, :1269:140] assign _autoexecProg_0_T = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_0 = _autoexecProg_0_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_1_T = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_1 = _autoexecProg_1_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_2_T = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_2 = _autoexecProg_2_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_3_T = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_3 = _autoexecProg_3_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_4_T = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_4 = _autoexecProg_4_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_5_T = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_5 = _autoexecProg_5_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_6_T = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_6 = _autoexecProg_6_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_7_T = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_7 = _autoexecProg_7_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_8_T = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_8 = _autoexecProg_8_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_9_T = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_9 = _autoexecProg_9_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_10_T = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_10 = _autoexecProg_10_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_11_T = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_11 = _autoexecProg_11_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_12_T = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_12 = _autoexecProg_12_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_13_T = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_13 = _autoexecProg_13_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_14_T = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_14 = _autoexecProg_14_T; // @[Debug.scala:1268:33, :1270:144] assign _autoexecProg_15_T = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}] assign autoexecProg_15 = _autoexecProg_15_T; // @[Debug.scala:1268:33, :1270:144] wire _autoexec_T = autoexecData_0 | autoexecData_1; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_1 = _autoexec_T | autoexecData_2; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_2 = _autoexec_T_1 | autoexecData_3; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_3 = _autoexec_T_2 | autoexecData_4; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_4 = _autoexec_T_3 | autoexecData_5; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_5 = _autoexec_T_4 | autoexecData_6; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_6 = _autoexec_T_5 | autoexecData_7; // @[Debug.scala:1267:33, :1272:42] wire _autoexec_T_7 = autoexecProg_0 | autoexecProg_1; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_8 = _autoexec_T_7 | autoexecProg_2; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_9 = _autoexec_T_8 | autoexecProg_3; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_10 = _autoexec_T_9 | autoexecProg_4; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_11 = _autoexec_T_10 | autoexecProg_5; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_12 = _autoexec_T_11 | autoexecProg_6; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_13 = _autoexec_T_12 | autoexecProg_7; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_14 = _autoexec_T_13 | autoexecProg_8; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_15 = _autoexec_T_14 | autoexecProg_9; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_16 = _autoexec_T_15 | autoexecProg_10; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_17 = _autoexec_T_16 | autoexecProg_11; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_18 = _autoexec_T_17 | autoexecProg_12; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_19 = _autoexec_T_18 | autoexecProg_13; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_20 = _autoexec_T_19 | autoexecProg_14; // @[Debug.scala:1268:33, :1272:73] wire _autoexec_T_21 = _autoexec_T_20 | autoexecProg_15; // @[Debug.scala:1268:33, :1272:73] wire autoexec = _autoexec_T_6 | _autoexec_T_21; // @[Debug.scala:1272:{42,48,73}] reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25] reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25] wire [31:0] COMMANDWrDataVal; // @[Debug.scala:1279:39] wire [31:0] _COMMANDWrData_WIRE_1 = COMMANDWrDataVal; // @[Debug.scala:1279:39, :1280:65] wire [7:0] _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire [23:0] _COMMANDWrData_T; // @[Debug.scala:1280:65] wire [7:0] COMMANDWrData_cmdtype = _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:{39,65}] wire [23:0] COMMANDWrData_control = _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:{39,65}] assign _COMMANDWrData_T = _COMMANDWrData_WIRE_1[23:0]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_control = _COMMANDWrData_T; // @[Debug.scala:1280:65] assign _COMMANDWrData_T_1 = _COMMANDWrData_WIRE_1[31:24]; // @[Debug.scala:1280:65] assign _COMMANDWrData_WIRE_cmdtype = _COMMANDWrData_T_1; // @[Debug.scala:1280:65] wire out_f_woready_140; // @[RegisterRouter.scala:87:24] wire COMMANDWrEnMaybe; // @[Debug.scala:1281:39] wire _COMMANDWrEnLegal_T; // @[Debug.scala:1743:44] wire COMMANDWrEnLegal; // @[Debug.scala:1282:39] wire out_f_roready_140; // @[RegisterRouter.scala:87:24] wire COMMANDRdEn; // @[Debug.scala:1283:32] wire COMMANDWrEn = COMMANDWrEnMaybe & COMMANDWrEnLegal; // @[Debug.scala:1281:39, :1282:39, :1285:40] reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36] wire [7:0] _out_T_308 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9474 = abstractDataMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36] wire [7:0] _out_T_77 = abstractDataMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36] wire [7:0] _out_T_761 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7912 = abstractDataMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36] wire [7:0] _out_T_1325 = abstractDataMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36] wire [7:0] _out_T_264 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10874 = abstractDataMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36] wire [7:0] _out_T_132 = abstractDataMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36] wire [7:0] _out_T_396 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2207 = abstractDataMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36] wire [7:0] _out_T_1413 = abstractDataMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36] reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36] wire [7:0] abstractDataNxt_0; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_1; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_2; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_3; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_4; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_5; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_6; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_7; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_8; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_9; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_10; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_11; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_12; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_13; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_14; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_15; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_16; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_17; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_18; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_19; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_20; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_21; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_22; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_23; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_24; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_25; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_26; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_27; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_28; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_29; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_30; // @[Debug.scala:1301:41] wire [7:0] abstractDataNxt_31; // @[Debug.scala:1301:41] reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34] wire [7:0] _out_T_1128 = programBufferMem_0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10426 = programBufferMem_0; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34] wire [7:0] _out_T_860 = programBufferMem_4; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34] wire [7:0] _out_T_1172 = programBufferMem_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6582 = programBufferMem_8; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34] wire [7:0] _out_T_220 = programBufferMem_12; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34] wire [7:0] _out_T_1556 = programBufferMem_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3679 = programBufferMem_16; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34] wire [7:0] _out_T_662 = programBufferMem_20; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34] wire [7:0] _out_T_816 = programBufferMem_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11898 = programBufferMem_24; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34] wire [7:0] _out_T_1369 = programBufferMem_28; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34] wire [7:0] _out_T_1501 = programBufferMem_32; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8594 = programBufferMem_32; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34] wire [7:0] _out_T_176 = programBufferMem_36; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34] wire [7:0] _out_T_587 = programBufferMem_40; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5954 = programBufferMem_40; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34] wire [7:0] _out_T_1457 = programBufferMem_44; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34] wire [7:0] _out_T_1281 = programBufferMem_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2943 = programBufferMem_48; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34] wire [7:0] _out_T_904 = programBufferMem_52; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34] wire [7:0] _out_T_706 = programBufferMem_56; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12562 = programBufferMem_56; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34] wire [7:0] _out_T_352 = programBufferMem_60; // @[RegisterRouter.scala:87:24] reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34] reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34] wire [7:0] programBufferNxt_0; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_1; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_2; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_3; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_4; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_5; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_6; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_7; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_8; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_9; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_10; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_11; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_12; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_13; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_14; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_15; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_16; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_17; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_18; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_19; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_20; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_21; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_22; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_23; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_24; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_25; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_26; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_27; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_28; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_29; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_30; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_31; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_32; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_33; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_34; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_35; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_36; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_37; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_38; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_39; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_40; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_41; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_42; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_43; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_44; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_45; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_46; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_47; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_48; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_49; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_50; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_51; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_52; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_53; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_54; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_55; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_56; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_57; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_58; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_59; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_60; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_61; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_62; // @[Debug.scala:1307:39] wire [7:0] programBufferNxt_63; // @[Debug.scala:1307:39] wire _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42] wire _resumeReqRegs_T_1 = resumeReqRegs & _resumeReqRegs_T; // @[Debug.scala:863:31, :1320:{40,42}] wire [1023:0] hartselIndex = 1024'h1 << io_innerCtrl_bits_hartsel_0; // @[OneHot.scala:58:35] wire _haltedBitRegs_T_1 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1327:66] wire [1:0] _haltedBitRegs_T_2 = {1'h0, _haltedBitRegs_T[0] & _haltedBitRegs_T_1}; // @[Debug.scala:1327:{43,64,66}] wire _haltedBitRegs_T_5 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1330:71] wire _haltedBitRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1333:44] wire _haltedBitRegs_T_8 = haltedBitRegs & _haltedBitRegs_T_7; // @[Debug.scala:861:31, :1333:{42,44}] wire _resumeReqRegs_T_4 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1338:71] wire _resumeReqRegs_T_6 = resumeReqRegs | hamaskWrSel_0; // @[Debug.scala:863:31, :933:31, :1342:43] wire _resumeReqRegs_T_7 = ~hartIsInResetSync_0; // @[Debug.scala:948:33, :1320:42, :1342:67] wire _resumeReqRegs_T_8 = _resumeReqRegs_T_6 & _resumeReqRegs_T_7; // @[Debug.scala:1342:{43,65,67}] wire _resumeAcks_T = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24] wire _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala:933:31, :1017:50, :1349:41] wire _resumeAcks_T_2 = _resumeAcks_T & _resumeAcks_T_1; // @[Debug.scala:1349:{24,39,41}] wire _resumeAcks_T_3 = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24, :1351:23] assign resumeAcks = resumereq ? _resumeAcks_T_2 : _resumeAcks_T_3; // @[Debug.scala:869:32, :983:39, :1347:24, :1349:{20,39}, :1351:{20,23}] wire _anyAddressWrEn_T_2; // @[SBA.scala:134:54] wire anyAddressWrEn; // @[SBA.scala:42:34] wire _anyDataRdEn_T_2; // @[SBA.scala:176:51] wire anyDataRdEn; // @[SBA.scala:43:34] wire _anyDataWrEn_T_2; // @[SBA.scala:177:51] wire anyDataWrEn; // @[SBA.scala:44:34] reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28] wire SBCSRdData_sbbusyerror = SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28] reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28] wire SBCSRdData_sbreadonaddr = SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :60:38] reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28] wire [2:0] SBCSRdData_sbaccess = SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28] wire SBCSRdData_sbautoincrement = SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :60:38] reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28] wire SBCSRdData_sbreadondata = SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :60:38] wire _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:51:67] wire SBCSFieldsRegReset_sbbusy; // @[SBA.scala:49:38] assign _SBCSFieldsRegReset_sbbusy_T = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67] assign SBCSFieldsRegReset_sbbusy = _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:49:38, :51:67] wire sbBusy; // @[SBA.scala:203:46] wire SBCSRdData_sbbusy; // @[SBA.scala:60:38] wire [2:0] SBCSRdData_sberror; // @[SBA.scala:60:38] wire _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_529; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_496; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_485; // @[RegisterRouter.scala:87:24] wire SBCSWrData_sbbusyerror; // @[SBA.scala:63:38] wire SBCSWrData_sbreadonaddr; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sbaccess; // @[SBA.scala:63:38] wire SBCSWrData_sbautoincrement; // @[SBA.scala:63:38] wire SBCSWrData_sbreadondata; // @[SBA.scala:63:38] wire [2:0] SBCSWrData_sberror; // @[SBA.scala:63:38] wire out_f_woready_39; // @[RegisterRouter.scala:87:24] wire sberrorWrEn; // @[SBA.scala:65:38] wire out_f_woready_40; // @[RegisterRouter.scala:87:24] wire sbreadondataWrEn; // @[SBA.scala:66:38] wire out_f_woready_41; // @[RegisterRouter.scala:87:24] wire sbautoincrementWrEn; // @[SBA.scala:67:38] wire out_f_woready_42; // @[RegisterRouter.scala:87:24] wire sbaccessWrEn; // @[SBA.scala:68:38] wire out_f_woready_43; // @[RegisterRouter.scala:87:24] wire sbreadonaddrWrEn; // @[SBA.scala:69:38] wire out_f_woready_45; // @[RegisterRouter.scala:87:24] wire sbbusyerrorWrEn; // @[SBA.scala:70:38] reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33] wire [31:0] _out_T_750 = SBADDRESSFieldsReg_0; // @[RegisterRouter.scala:87:24] wire [31:0] SBADDRESSWrData_0; // @[SBA.scala:106:38] wire out_f_roready_63; // @[RegisterRouter.scala:87:24] wire SBADDRESSRdEn_0; // @[SBA.scala:107:38] wire out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _anyAddressWrEn_T = SBADDRESSWrEn_0; // @[SBA.scala:108:38, :134:54] wire [127:0] _autoIncrementedAddr_T_3; // @[SBA.scala:111:60] wire [127:0] autoIncrementedAddr; // @[SBA.scala:110:39] wire [63:0] _GEN_0 = {32'h0, SBADDRESSFieldsReg_0}; // @[SBA.scala:104:33, :111:31] wire [63:0] autoIncrementedAddr_lo; // @[SBA.scala:111:31] assign autoIncrementedAddr_lo = _GEN_0; // @[SBA.scala:111:31] wire [63:0] sb2tlOpt_io_addrIn_lo; // @[SBA.scala:133:10] assign sb2tlOpt_io_addrIn_lo = _GEN_0; // @[SBA.scala:111:31, :133:10] wire [127:0] _autoIncrementedAddr_T = {64'h0, autoIncrementedAddr_lo}; // @[SBA.scala:111:31] wire [7:0] _autoIncrementedAddr_T_1 = 8'h1 << SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :111:67] wire [128:0] _autoIncrementedAddr_T_2 = {1'h0, _autoIncrementedAddr_T} + {121'h0, _autoIncrementedAddr_T_1}; // @[SBA.scala:111:{31,60,67}] assign _autoIncrementedAddr_T_3 = _autoIncrementedAddr_T_2[127:0]; // @[SBA.scala:111:60] assign autoIncrementedAddr = _autoIncrementedAddr_T_3; // @[SBA.scala:110:39, :111:60] wire _GEN_1 = SBCSRdData_sberror == 3'h0; // @[SBA.scala:60:38, :119:40] wire _SBADDRESSFieldsReg_0_T; // @[SBA.scala:119:40] assign _SBADDRESSFieldsReg_0_T = _GEN_1; // @[SBA.scala:119:40] wire _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_0_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_0_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_1_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_2_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:97] assign _SBDATAFieldsReg_1_3_T_4 = _GEN_1; // @[SBA.scala:119:40, :160:97] wire _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:118] assign _sb2tlOpt_io_wrEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :199:118] wire _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:118] assign _sb2tlOpt_io_rdEn_T_5 = _GEN_1; // @[SBA.scala:119:40, :200:118] wire _SBADDRESSFieldsReg_0_T_1 = SBADDRESSWrEn_0 & _SBADDRESSFieldsReg_0_T; // @[SBA.scala:108:38, :119:{37,40}] wire _SBADDRESSFieldsReg_0_T_2 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63] wire _SBADDRESSFieldsReg_0_T_3 = _SBADDRESSFieldsReg_0_T_1 & _SBADDRESSFieldsReg_0_T_2; // @[SBA.scala:119:{37,60,63}] wire _SBADDRESSFieldsReg_0_T_4 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88] wire _SBADDRESSFieldsReg_0_T_5 = _SBADDRESSFieldsReg_0_T_3 & _SBADDRESSFieldsReg_0_T_4; // @[SBA.scala:119:{60,85,88}] wire _GEN_2 = _sb2tlOpt_io_rdDone | _sb2tlOpt_io_wrDone; // @[SBA.scala:120:44] wire _SBADDRESSFieldsReg_0_T_6; // @[SBA.scala:120:44] assign _SBADDRESSFieldsReg_0_T_6 = _GEN_2; // @[SBA.scala:120:44] wire _sbErrorReg_0_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_0_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_1_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_1_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _sbErrorReg_2_T_12; // @[SBA.scala:229:54] assign _sbErrorReg_2_T_12 = _GEN_2; // @[SBA.scala:120:44, :229:54] wire _SBADDRESSFieldsReg_0_T_7 = _SBADDRESSFieldsReg_0_T_6 & SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :120:{44,71}] wire [31:0] _SBADDRESSFieldsReg_0_T_8 = autoIncrementedAddr[31:0]; // @[SBA.scala:110:39, :120:124] wire [31:0] _SBADDRESSFieldsReg_0_T_9 = _SBADDRESSFieldsReg_0_T_7 ? _SBADDRESSFieldsReg_0_T_8 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :120:{19,71,124}] wire [31:0] _SBADDRESSFieldsReg_0_T_10 = _SBADDRESSFieldsReg_0_T_5 ? SBADDRESSWrData_0 : _SBADDRESSFieldsReg_0_T_9; // @[SBA.scala:106:38, :119:{19,85}, :120:19] wire [127:0] _sb2tlOpt_io_addrIn_T_1 = {96'h0, SBADDRESSWrData_0}; // @[SBA.scala:106:38, :132:10] wire [127:0] _sb2tlOpt_io_addrIn_T_2 = {64'h0, sb2tlOpt_io_addrIn_lo}; // @[SBA.scala:133:10] wire [127:0] _sb2tlOpt_io_addrIn_T_3 = SBADDRESSWrEn_0 ? _sb2tlOpt_io_addrIn_T_1 : _sb2tlOpt_io_addrIn_T_2; // @[SBA.scala:108:38, :131:34, :132:10, :133:10] wire _anyAddressWrEn_T_1 = _anyAddressWrEn_T; // @[SBA.scala:134:54] assign _anyAddressWrEn_T_2 = _anyAddressWrEn_T_1; // @[SBA.scala:134:54] assign anyAddressWrEn = _anyAddressWrEn_T_2; // @[SBA.scala:42:34, :134:54] reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30] reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30] wire [31:0] _SBDATARdData_0_T; // @[SBA.scala:165:31] wire [31:0] _SBDATARdData_1_T; // @[SBA.scala:165:31] wire [31:0] _out_T_805 = SBDATARdData_0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_121 = SBDATARdData_1; // @[RegisterRouter.scala:87:24] wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35] wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35] wire out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_roready_4; // @[RegisterRouter.scala:87:24] wire SBDATARdEn_0; // @[SBA.scala:149:35] wire SBDATARdEn_1; // @[SBA.scala:149:35] wire out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _sb2tlOpt_io_wrEn_T = SBDATAWrEn_0; // @[SBA.scala:150:35, :199:49] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire SBDATAWrEn_1; // @[SBA.scala:150:35] wire _SBDATAFieldsReg_0_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_0_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_0_T_3 = _SBDATAFieldsReg_0_0_T_1 & _SBDATAFieldsReg_0_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_0_T_5 = _SBDATAFieldsReg_0_0_T_3 & _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_0_T_6 = SBDATAWrData_0[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_0_T_7 = _sb2tlOpt_io_rdLoad_0 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_0_T_8 = _SBDATAFieldsReg_0_0_T_5 ? _SBDATAFieldsReg_0_0_T_6 : _SBDATAFieldsReg_0_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_1_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_1_T_3 = _SBDATAFieldsReg_0_1_T_1 & _SBDATAFieldsReg_0_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_1_T_5 = _SBDATAFieldsReg_0_1_T_3 & _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_1_T_6 = SBDATAWrData_0[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_1_T_7 = _sb2tlOpt_io_rdLoad_1 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_1_T_8 = _SBDATAFieldsReg_0_1_T_5 ? _SBDATAFieldsReg_0_1_T_6 : _SBDATAFieldsReg_0_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_2_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_2_T_3 = _SBDATAFieldsReg_0_2_T_1 & _SBDATAFieldsReg_0_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_2_T_5 = _SBDATAFieldsReg_0_2_T_3 & _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_2_T_6 = SBDATAWrData_0[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_2_T_7 = _sb2tlOpt_io_rdLoad_2 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_2_T_8 = _SBDATAFieldsReg_0_2_T_5 ? _SBDATAFieldsReg_0_2_T_6 : _SBDATAFieldsReg_0_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_0_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_0_3_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_0_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_0_3_T_3 = _SBDATAFieldsReg_0_3_T_1 & _SBDATAFieldsReg_0_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_0_3_T_5 = _SBDATAFieldsReg_0_3_T_3 & _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_0_3_T_6 = SBDATAWrData_0[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_0_3_T_7 = _sb2tlOpt_io_rdLoad_3 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_0_3_T_8 = _SBDATAFieldsReg_0_3_T_5 ? _SBDATAFieldsReg_0_3_T_6 : _SBDATAFieldsReg_0_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_3 = {SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_lo; // @[SBA.scala:165:31] assign SBDATARdData_0_lo = _GEN_3; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_lo = _GEN_3; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_4 = {SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_0_hi; // @[SBA.scala:165:31] assign SBDATARdData_0_hi = _GEN_4; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_lo_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_lo_hi = _GEN_4; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_0_T = {SBDATARdData_0_hi, SBDATARdData_0_lo}; // @[SBA.scala:165:31] assign SBDATARdData_0 = _SBDATARdData_0_T; // @[SBA.scala:145:35, :165:31] wire _SBDATAFieldsReg_1_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_0_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_0_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_0_T_3 = _SBDATAFieldsReg_1_0_T_1 & _SBDATAFieldsReg_1_0_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_0_T_5 = _SBDATAFieldsReg_1_0_T_3 & _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_0_T_6 = SBDATAWrData_1[7:0]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_0_T_7 = _sb2tlOpt_io_rdLoad_4 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_0; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_0_T_8 = _SBDATAFieldsReg_1_0_T_5 ? _SBDATAFieldsReg_1_0_T_6 : _SBDATAFieldsReg_1_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_1_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_1_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_1_T_3 = _SBDATAFieldsReg_1_1_T_1 & _SBDATAFieldsReg_1_1_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_1_T_5 = _SBDATAFieldsReg_1_1_T_3 & _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_1_T_6 = SBDATAWrData_1[15:8]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_1_T_7 = _sb2tlOpt_io_rdLoad_5 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_1; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_1_T_8 = _SBDATAFieldsReg_1_1_T_5 ? _SBDATAFieldsReg_1_1_T_6 : _SBDATAFieldsReg_1_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_2_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_2_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_2_T_3 = _SBDATAFieldsReg_1_2_T_1 & _SBDATAFieldsReg_1_2_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_2_T_5 = _SBDATAFieldsReg_1_2_T_3 & _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_2_T_6 = SBDATAWrData_1[23:16]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_2_T_7 = _sb2tlOpt_io_rdLoad_6 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_2; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_2_T_8 = _SBDATAFieldsReg_1_2_T_5 ? _SBDATAFieldsReg_1_2_T_6 : _SBDATAFieldsReg_1_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire _SBDATAFieldsReg_1_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42] wire _SBDATAFieldsReg_1_3_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_3_T; // @[SBA.scala:150:35, :160:{39,42}] wire _SBDATAFieldsReg_1_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67] wire _SBDATAFieldsReg_1_3_T_3 = _SBDATAFieldsReg_1_3_T_1 & _SBDATAFieldsReg_1_3_T_2; // @[SBA.scala:160:{39,64,67}] wire _SBDATAFieldsReg_1_3_T_5 = _SBDATAFieldsReg_1_3_T_3 & _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:{64,94,97}] wire [7:0] _SBDATAFieldsReg_1_3_T_6 = SBDATAWrData_1[31:24]; // @[SBA.scala:147:35, :160:133] wire [7:0] _SBDATAFieldsReg_1_3_T_7 = _sb2tlOpt_io_rdLoad_7 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_3; // @[SBA.scala:143:30, :161:24] wire [7:0] _SBDATAFieldsReg_1_3_T_8 = _SBDATAFieldsReg_1_3_T_5 ? _SBDATAFieldsReg_1_3_T_6 : _SBDATAFieldsReg_1_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24] wire [15:0] _GEN_5 = {SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_lo; // @[SBA.scala:165:31] assign SBDATARdData_1_lo = _GEN_5; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_lo; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_lo = _GEN_5; // @[SBA.scala:165:31, :175:85] wire [15:0] _GEN_6 = {SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2}; // @[SBA.scala:143:30, :165:31] wire [15:0] SBDATARdData_1_hi; // @[SBA.scala:165:31] assign SBDATARdData_1_hi = _GEN_6; // @[SBA.scala:165:31] wire [15:0] sb2tlOpt_io_dataIn_lo_hi_hi; // @[SBA.scala:175:85] assign sb2tlOpt_io_dataIn_lo_hi_hi = _GEN_6; // @[SBA.scala:165:31, :175:85] assign _SBDATARdData_1_T = {SBDATARdData_1_hi, SBDATARdData_1_lo}; // @[SBA.scala:165:31] assign SBDATARdData_1 = _SBDATARdData_1_T; // @[SBA.scala:145:35, :165:31] wire [63:0] sb2tlOpt_io_dataIn_lo = {SBDATAWrData_1, SBDATAWrData_0}; // @[SBA.scala:147:35, :175:59] wire [127:0] _sb2tlOpt_io_dataIn_T = {64'h0, sb2tlOpt_io_dataIn_lo}; // @[SBA.scala:175:59] wire [31:0] sb2tlOpt_io_dataIn_lo_lo = {sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo}; // @[SBA.scala:175:85] wire [31:0] sb2tlOpt_io_dataIn_lo_hi = {sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo}; // @[SBA.scala:175:85] wire [63:0] sb2tlOpt_io_dataIn_lo_1 = {sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo}; // @[SBA.scala:175:85] wire [127:0] _sb2tlOpt_io_dataIn_T_1 = {64'h0, sb2tlOpt_io_dataIn_lo_1}; // @[SBA.scala:175:85] wire _sb2tlOpt_io_wrEn_T_10; // @[SBA.scala:199:156] wire [127:0] _sb2tlOpt_io_dataIn_T_2 = _sb2tlOpt_io_wrEn_T_10 ? _sb2tlOpt_io_dataIn_T : _sb2tlOpt_io_dataIn_T_1; // @[SBA.scala:175:{34,59,85}, :199:156] wire _anyDataRdEn_T = SBDATARdEn_0 | SBDATARdEn_1; // @[SBA.scala:149:35, :176:51] wire _anyDataRdEn_T_1 = _anyDataRdEn_T; // @[SBA.scala:176:51] assign _anyDataRdEn_T_2 = _anyDataRdEn_T_1; // @[SBA.scala:176:51] assign anyDataRdEn = _anyDataRdEn_T_2; // @[SBA.scala:43:34, :176:51] wire _anyDataWrEn_T = SBDATAWrEn_0 | SBDATAWrEn_1; // @[SBA.scala:150:35, :177:51] wire _anyDataWrEn_T_1 = _anyDataWrEn_T; // @[SBA.scala:177:51] assign _anyDataWrEn_T_2 = _anyDataWrEn_T_1; // @[SBA.scala:177:51] assign anyDataWrEn = _anyDataWrEn_T_2; // @[SBA.scala:44:34, :177:51] wire _tryRdEn_T = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :108:38, :180:37] wire _tryRdEn_T_1 = SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :149:35, :180:86] wire tryRdEn = _tryRdEn_T | _tryRdEn_T_1; // @[SBA.scala:180:{37,68,86}] wire _sb2tlOpt_io_rdEn_T = tryRdEn; // @[SBA.scala:180:68, :200:49] wire _sbAccessError_T = SBCSFieldsReg_sbaccess == 3'h0; // @[SBA.scala:47:28, :182:49] wire _T_204 = SBCSFieldsReg_sbaccess == 3'h1; // @[SBA.scala:47:28, :183:49] wire _sbAccessError_T_3; // @[SBA.scala:183:49] assign _sbAccessError_T_3 = _T_204; // @[SBA.scala:183:49] wire _sbAlignmentError_T; // @[SBA.scala:191:52] assign _sbAlignmentError_T = _T_204; // @[SBA.scala:183:49, :191:52] wire _T_211 = SBCSFieldsReg_sbaccess == 3'h2; // @[SBA.scala:47:28, :184:49] wire _sbAccessError_T_7; // @[SBA.scala:184:49] assign _sbAccessError_T_7 = _T_211; // @[SBA.scala:184:49] wire _sbAlignmentError_T_4; // @[SBA.scala:192:52] assign _sbAlignmentError_T_4 = _T_211; // @[SBA.scala:184:49, :192:52] wire _T_218 = SBCSFieldsReg_sbaccess == 3'h3; // @[SBA.scala:47:28, :185:49] wire _sbAccessError_T_11; // @[SBA.scala:185:49] assign _sbAccessError_T_11 = _T_218; // @[SBA.scala:185:49] wire _sbAlignmentError_T_9; // @[SBA.scala:193:52] assign _sbAlignmentError_T_9 = _T_218; // @[SBA.scala:185:49, :193:52] wire _T_225 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49] wire _sbAccessError_T_15; // @[SBA.scala:186:49] assign _sbAccessError_T_15 = _T_225; // @[SBA.scala:186:49] wire _sbAlignmentError_T_14; // @[SBA.scala:194:52] assign _sbAlignmentError_T_14 = _T_225; // @[SBA.scala:186:49, :194:52] wire _sbAccessError_T_17 = _sbAccessError_T_15; // @[SBA.scala:186:{49,58}] wire _sbAccessError_T_18 = _sbAccessError_T_17; // @[SBA.scala:185:97, :186:58] wire _sbAccessError_T_19 = SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:124] wire sbAccessError = _sbAccessError_T_18 | _sbAccessError_T_19; // @[SBA.scala:185:97, :186:{97,124}] wire [31:0] _compareAddr_T; // @[SBA.scala:189:23] wire [31:0] compareAddr; // @[SBA.scala:188:27] assign _compareAddr_T = SBADDRESSWrEn_0 ? SBADDRESSWrData_0 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :106:38, :108:38, :189:23] assign compareAddr = _compareAddr_T; // @[SBA.scala:188:27, :189:23] wire _sbAlignmentError_T_1 = compareAddr[0]; // @[SBA.scala:188:27, :191:76] wire _sbAlignmentError_T_2 = _sbAlignmentError_T_1; // @[SBA.scala:191:{76,82}] wire _sbAlignmentError_T_3 = _sbAlignmentError_T & _sbAlignmentError_T_2; // @[SBA.scala:191:{52,61,82}] wire [1:0] _sbAlignmentError_T_5 = compareAddr[1:0]; // @[SBA.scala:188:27, :192:76] wire _sbAlignmentError_T_6 = |_sbAlignmentError_T_5; // @[SBA.scala:192:{76,82}] wire _sbAlignmentError_T_7 = _sbAlignmentError_T_4 & _sbAlignmentError_T_6; // @[SBA.scala:192:{52,61,82}] wire _sbAlignmentError_T_8 = _sbAlignmentError_T_3 | _sbAlignmentError_T_7; // @[SBA.scala:191:{61,91}, :192:61] wire [2:0] _sbAlignmentError_T_10 = compareAddr[2:0]; // @[SBA.scala:188:27, :193:76] wire _sbAlignmentError_T_11 = |_sbAlignmentError_T_10; // @[SBA.scala:193:{76,82}] wire _sbAlignmentError_T_12 = _sbAlignmentError_T_9 & _sbAlignmentError_T_11; // @[SBA.scala:193:{52,61,82}] wire _sbAlignmentError_T_13 = _sbAlignmentError_T_8 | _sbAlignmentError_T_12; // @[SBA.scala:191:91, :192:91, :193:61] wire [3:0] _sbAlignmentError_T_15 = compareAddr[3:0]; // @[SBA.scala:188:27, :194:76] wire _sbAlignmentError_T_16 = |_sbAlignmentError_T_15; // @[SBA.scala:194:{76,82}] wire _sbAlignmentError_T_17 = _sbAlignmentError_T_14 & _sbAlignmentError_T_16; // @[SBA.scala:194:{52,61,82}] wire sbAlignmentError = _sbAlignmentError_T_13 | _sbAlignmentError_T_17; // @[SBA.scala:192:91, :193:91, :194:61] wire _sb2tlOpt_io_wrEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :199:63] wire _sb2tlOpt_io_wrEn_T_2 = _sb2tlOpt_io_wrEn_T & _sb2tlOpt_io_wrEn_T_1; // @[SBA.scala:199:{49,60,63}] wire _sb2tlOpt_io_wrEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :199:88] wire _sb2tlOpt_io_wrEn_T_4 = _sb2tlOpt_io_wrEn_T_2 & _sb2tlOpt_io_wrEn_T_3; // @[SBA.scala:199:{60,85,88}] wire _sb2tlOpt_io_wrEn_T_6 = _sb2tlOpt_io_wrEn_T_4 & _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:{85,115,118}] wire _sb2tlOpt_io_wrEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141] wire _sb2tlOpt_io_wrEn_T_8 = _sb2tlOpt_io_wrEn_T_6 & _sb2tlOpt_io_wrEn_T_7; // @[SBA.scala:199:{115,138,141}] wire _sb2tlOpt_io_wrEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159] assign _sb2tlOpt_io_wrEn_T_10 = _sb2tlOpt_io_wrEn_T_8 & _sb2tlOpt_io_wrEn_T_9; // @[SBA.scala:199:{138,156,159}] wire _sb2tlOpt_io_rdEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :200:63] wire _sb2tlOpt_io_rdEn_T_2 = _sb2tlOpt_io_rdEn_T & _sb2tlOpt_io_rdEn_T_1; // @[SBA.scala:200:{49,60,63}] wire _sb2tlOpt_io_rdEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :200:88] wire _sb2tlOpt_io_rdEn_T_4 = _sb2tlOpt_io_rdEn_T_2 & _sb2tlOpt_io_rdEn_T_3; // @[SBA.scala:200:{60,85,88}] wire _sb2tlOpt_io_rdEn_T_6 = _sb2tlOpt_io_rdEn_T_4 & _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:{85,115,118}] wire _sb2tlOpt_io_rdEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141, :200:141] wire _sb2tlOpt_io_rdEn_T_8 = _sb2tlOpt_io_rdEn_T_6 & _sb2tlOpt_io_rdEn_T_7; // @[SBA.scala:200:{115,138,141}] wire _sb2tlOpt_io_rdEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159, :200:159] wire _sb2tlOpt_io_rdEn_T_10 = _sb2tlOpt_io_rdEn_T_8 & _sb2tlOpt_io_rdEn_T_9; // @[SBA.scala:200:{138,156,159}] assign sbBusy = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67, :203:46] assign SBCSRdData_sbbusy = sbBusy; // @[SBA.scala:60:38, :203:46] wire _SBCSFieldsReg_sbbusyerror_T = sbbusyerrorWrEn & SBCSWrData_sbbusyerror; // @[SBA.scala:63:38, :70:38, :208:60] wire _SBCSFieldsReg_sbbusyerror_T_1 = anyAddressWrEn & sbBusy; // @[SBA.scala:42:34, :203:46, :209:59] wire _SBCSFieldsReg_sbbusyerror_T_2 = anyDataRdEn | anyDataWrEn; // @[SBA.scala:43:34, :44:34, :210:57] wire _SBCSFieldsReg_sbbusyerror_T_3 = _SBCSFieldsReg_sbbusyerror_T_2 & sbBusy; // @[SBA.scala:203:46, :210:{57,73}] wire _SBCSFieldsReg_sbbusyerror_T_4 = _SBCSFieldsReg_sbbusyerror_T_3 | SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :210:{43,73}] wire _SBCSFieldsReg_sbbusyerror_T_5 = _SBCSFieldsReg_sbbusyerror_T_1 | _SBCSFieldsReg_sbbusyerror_T_4; // @[SBA.scala:209:{43,59}, :210:43] wire _SBCSFieldsReg_sbbusyerror_T_6 = ~_SBCSFieldsReg_sbbusyerror_T & _SBCSFieldsReg_sbbusyerror_T_5; // @[SBA.scala:208:{43,60}, :209:43] wire _SBCSFieldsReg_sbreadonaddr_T = sbreadonaddrWrEn ? SBCSWrData_sbreadonaddr : SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :63:38, :69:38, :211:43] wire _SBCSFieldsReg_sbautoincrement_T = sbautoincrementWrEn ? SBCSWrData_sbautoincrement : SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :63:38, :67:38, :212:43] wire _SBCSFieldsReg_sbreadondata_T = sbreadondataWrEn ? SBCSWrData_sbreadondata : SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :63:38, :66:38, :213:43] wire [2:0] _SBCSFieldsReg_sbaccess_T = sbaccessWrEn ? SBCSWrData_sbaccess : SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :63:38, :68:38, :214:43] reg sbErrorReg_0; // @[SBA.scala:219:25] reg sbErrorReg_1; // @[SBA.scala:219:25] reg sbErrorReg_2; // @[SBA.scala:219:25] wire _sbErrorReg_0_T = SBCSWrData_sberror[0]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_0_T_1 = _sbErrorReg_0_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_0_T_2 = sberrorWrEn & _sbErrorReg_0_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_0_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_0_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_0_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_0_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_0_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_0_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_0_T_7 = _sbErrorReg_0_T_4 | _sbErrorReg_0_T_6; // @[SBA.scala:226:{52,81,106}] wire _GEN_7 = SBDATAWrEn_0 | tryRdEn; // @[SBA.scala:150:35, :180:68, :227:39] wire _sbErrorReg_0_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_0_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_0_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_0_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_1_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_1_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_1_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_1_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_2_T_8; // @[SBA.scala:227:39] assign _sbErrorReg_2_T_8 = _GEN_7; // @[SBA.scala:227:39] wire _sbErrorReg_2_T_10; // @[SBA.scala:228:39] assign _sbErrorReg_2_T_10 = _GEN_7; // @[SBA.scala:227:39, :228:39] wire _sbErrorReg_0_T_9 = _sbErrorReg_0_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_0_T_11 = _sbErrorReg_0_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_0_T_13 = _sbErrorReg_0_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_0_T_14 = _sbErrorReg_0_T_13 | sbErrorReg_0; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_0_T_15 = ~_sbErrorReg_0_T_11 & _sbErrorReg_0_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_0_T_16 = _sbErrorReg_0_T_9 | _sbErrorReg_0_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_0_T_17 = ~_sbErrorReg_0_T_7 & _sbErrorReg_0_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_0_T_18 = ~_sbErrorReg_0_T_2 & _sbErrorReg_0_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_1_T = SBCSWrData_sberror[1]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_1_T_1 = _sbErrorReg_1_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_1_T_2 = sberrorWrEn & _sbErrorReg_1_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_1_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_1_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_1_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_1_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_1_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_1_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_1_T_7 = _sbErrorReg_1_T_4 | _sbErrorReg_1_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_1_T_9 = _sbErrorReg_1_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_1_T_11 = _sbErrorReg_1_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_1_T_13 = _sbErrorReg_1_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_1_T_14 = _sbErrorReg_1_T_13 | sbErrorReg_1; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_1_T_15 = ~_sbErrorReg_1_T_11 & _sbErrorReg_1_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_1_T_16 = _sbErrorReg_1_T_9 | _sbErrorReg_1_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_1_T_17 = _sbErrorReg_1_T_7 | _sbErrorReg_1_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_1_T_18 = ~_sbErrorReg_1_T_2 & _sbErrorReg_1_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire _sbErrorReg_2_T = SBCSWrData_sberror[2]; // @[SBA.scala:63:38, :225:63] wire _sbErrorReg_2_T_1 = _sbErrorReg_2_T; // @[SBA.scala:225:{63,67}] wire _sbErrorReg_2_T_2 = sberrorWrEn & _sbErrorReg_2_T_1; // @[SBA.scala:65:38, :225:{42,67}] wire _sbErrorReg_2_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55] wire _sbErrorReg_2_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_2_T_3; // @[SBA.scala:199:156, :226:{52,55}] wire _sbErrorReg_2_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109] wire _sbErrorReg_2_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_2_T_5; // @[SBA.scala:200:156, :226:{106,109}] wire _sbErrorReg_2_T_7 = _sbErrorReg_2_T_4 | _sbErrorReg_2_T_6; // @[SBA.scala:226:{52,81,106}] wire _sbErrorReg_2_T_9 = _sbErrorReg_2_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}] wire _sbErrorReg_2_T_11 = _sbErrorReg_2_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}] wire _sbErrorReg_2_T_13 = _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}] wire _sbErrorReg_2_T_14 = _sbErrorReg_2_T_13 | sbErrorReg_2; // @[SBA.scala:219:25, :229:{29,81}] wire _sbErrorReg_2_T_15 = _sbErrorReg_2_T_11 | _sbErrorReg_2_T_14; // @[SBA.scala:228:{29,51}, :229:29] wire _sbErrorReg_2_T_16 = ~_sbErrorReg_2_T_9 & _sbErrorReg_2_T_15; // @[SBA.scala:227:{29,51}, :228:29] wire _sbErrorReg_2_T_17 = ~_sbErrorReg_2_T_7 & _sbErrorReg_2_T_16; // @[SBA.scala:226:{29,81}, :227:29] wire _sbErrorReg_2_T_18 = ~_sbErrorReg_2_T_2 & _sbErrorReg_2_T_17; // @[SBA.scala:225:{29,42}, :226:29] wire [1:0] SBCSRdData_sberror_lo = {sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:42] wire [1:0] SBCSRdData_sberror_hi = {1'h0, sbErrorReg_2}; // @[SBA.scala:219:25, :240:42] wire [3:0] _SBCSRdData_sberror_T = {SBCSRdData_sberror_hi, SBCSRdData_sberror_lo}; // @[SBA.scala:240:42] assign SBCSRdData_sberror = _SBCSRdData_sberror_T[2:0]; // @[SBA.scala:60:38, :240:{28,42}] wire [31:0] _T_237 = {COMMANDReg_cmdtype, COMMANDReg_control}; // @[Debug.scala:1277:25, :1435:40] wire [31:0] _out_T_1545; // @[RegisterRouter.scala:87:24] assign _out_T_1545 = _T_237; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] wire [31:0] _accessRegisterCommandReg_T; // @[Debug.scala:1533:56] assign _accessRegisterCommandReg_T = _T_237; // @[Debug.scala:1435:40, :1533:56] assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] _in_bits_index_T; // @[Edges.scala:192:34] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [6:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [3:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T = dmiNodeIn_a_bits_address[8:2]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_112 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_741 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_796 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_939 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1536 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1591 = out_front_bits_data; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [6:0] _GEN_8 = out_front_bits_index & 7'h40; // @[RegisterRouter.scala:87:24] wire [6:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN_8; // @[RegisterRouter.scala:87:24] wire [6:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN_8; // @[RegisterRouter.scala:87:24] wire _GEN_9 = out_findex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_14; // @[RegisterRouter.scala:87:24] assign _out_T_14 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_16; // @[RegisterRouter.scala:87:24] assign _out_T_16 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_18; // @[RegisterRouter.scala:87:24] assign _out_T_18 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_20; // @[RegisterRouter.scala:87:24] assign _out_T_20 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_22; // @[RegisterRouter.scala:87:24] assign _out_T_22 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_24; // @[RegisterRouter.scala:87:24] assign _out_T_24 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_T_26 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_28; // @[RegisterRouter.scala:87:24] assign _out_T_28 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_30; // @[RegisterRouter.scala:87:24] assign _out_T_30 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_32; // @[RegisterRouter.scala:87:24] assign _out_T_32 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_34; // @[RegisterRouter.scala:87:24] assign _out_T_34 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_36; // @[RegisterRouter.scala:87:24] assign _out_T_36 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_38; // @[RegisterRouter.scala:87:24] assign _out_T_38 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_42; // @[RegisterRouter.scala:87:24] assign _out_T_42 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_44; // @[RegisterRouter.scala:87:24] assign _out_T_44 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_46; // @[RegisterRouter.scala:87:24] assign _out_T_46 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_48; // @[RegisterRouter.scala:87:24] assign _out_T_48 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_50; // @[RegisterRouter.scala:87:24] assign _out_T_50 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_52; // @[RegisterRouter.scala:87:24] assign _out_T_52 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_54; // @[RegisterRouter.scala:87:24] assign _out_T_54 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_56; // @[RegisterRouter.scala:87:24] assign _out_T_56 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_58; // @[RegisterRouter.scala:87:24] assign _out_T_58 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_60; // @[RegisterRouter.scala:87:24] assign _out_T_60 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_62; // @[RegisterRouter.scala:87:24] assign _out_T_62 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_64; // @[RegisterRouter.scala:87:24] assign _out_T_64 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _out_T_66; // @[RegisterRouter.scala:87:24] assign _out_T_66 = _GEN_9; // @[RegisterRouter.scala:87:24] wire _GEN_10 = out_bindex == 7'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_15; // @[RegisterRouter.scala:87:24] assign _out_T_15 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_17; // @[RegisterRouter.scala:87:24] assign _out_T_17 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_19; // @[RegisterRouter.scala:87:24] assign _out_T_19 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_21; // @[RegisterRouter.scala:87:24] assign _out_T_21 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_23; // @[RegisterRouter.scala:87:24] assign _out_T_23 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_25; // @[RegisterRouter.scala:87:24] assign _out_T_25 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_27; // @[RegisterRouter.scala:87:24] assign _out_T_27 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_29; // @[RegisterRouter.scala:87:24] assign _out_T_29 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_31; // @[RegisterRouter.scala:87:24] assign _out_T_31 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_33; // @[RegisterRouter.scala:87:24] assign _out_T_33 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_35; // @[RegisterRouter.scala:87:24] assign _out_T_35 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_37; // @[RegisterRouter.scala:87:24] assign _out_T_37 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_39; // @[RegisterRouter.scala:87:24] assign _out_T_39 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_43; // @[RegisterRouter.scala:87:24] assign _out_T_43 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_45; // @[RegisterRouter.scala:87:24] assign _out_T_45 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_47; // @[RegisterRouter.scala:87:24] assign _out_T_47 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_49; // @[RegisterRouter.scala:87:24] assign _out_T_49 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_51; // @[RegisterRouter.scala:87:24] assign _out_T_51 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_53; // @[RegisterRouter.scala:87:24] assign _out_T_53 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_55; // @[RegisterRouter.scala:87:24] assign _out_T_55 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_57; // @[RegisterRouter.scala:87:24] assign _out_T_57 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_59; // @[RegisterRouter.scala:87:24] assign _out_T_59 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_61; // @[RegisterRouter.scala:87:24] assign _out_T_61 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_63; // @[RegisterRouter.scala:87:24] assign _out_T_63 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_65; // @[RegisterRouter.scala:87:24] assign _out_T_65 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_T_67; // @[RegisterRouter.scala:87:24] assign _out_T_67 = _GEN_10; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_5 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_61 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_9 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_41 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_35 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_8 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_4 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_47 = _out_T_15; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_10 = _out_T_17; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_56 = _out_T_19; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_42 = _out_T_21; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_24 = _out_T_23; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_37 = _out_T_25; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_46 = _out_T_27; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_57 = _out_T_29; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_6 = _out_T_31; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_60 = _out_T_33; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_38 = _out_T_35; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_33 = _out_T_37; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_45 = _out_T_39; // @[MuxLiteral.scala:49:48] wire _out_T_40 = out_findex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_bindex == 7'h40; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_41; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_17 = _out_T_43; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_32 = _out_T_45; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_34 = _out_T_47; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_22 = _out_T_49; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_44 = _out_T_51; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_7 = _out_T_53; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_39 = _out_T_55; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_11 = _out_T_57; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_43 = _out_T_59; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_40 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_23 = _out_T_63; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_36 = _out_T_65; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_19 = _out_T_67; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_145; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_145; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire out_roready_18; // @[RegisterRouter.scala:87:24] wire out_roready_19; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_21; // @[RegisterRouter.scala:87:24] wire out_roready_22; // @[RegisterRouter.scala:87:24] wire out_roready_23; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire out_roready_25; // @[RegisterRouter.scala:87:24] wire out_roready_26; // @[RegisterRouter.scala:87:24] wire out_roready_27; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_29; // @[RegisterRouter.scala:87:24] wire out_roready_30; // @[RegisterRouter.scala:87:24] wire out_roready_31; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_33; // @[RegisterRouter.scala:87:24] wire out_roready_34; // @[RegisterRouter.scala:87:24] wire out_roready_35; // @[RegisterRouter.scala:87:24] wire out_roready_36; // @[RegisterRouter.scala:87:24] wire out_roready_37; // @[RegisterRouter.scala:87:24] wire out_roready_38; // @[RegisterRouter.scala:87:24] wire out_roready_39; // @[RegisterRouter.scala:87:24] wire out_roready_40; // @[RegisterRouter.scala:87:24] wire out_roready_41; // @[RegisterRouter.scala:87:24] wire out_roready_42; // @[RegisterRouter.scala:87:24] wire out_roready_43; // @[RegisterRouter.scala:87:24] wire out_roready_44; // @[RegisterRouter.scala:87:24] wire out_roready_45; // @[RegisterRouter.scala:87:24] wire out_roready_46; // @[RegisterRouter.scala:87:24] wire out_roready_47; // @[RegisterRouter.scala:87:24] wire out_roready_48; // @[RegisterRouter.scala:87:24] wire out_roready_49; // @[RegisterRouter.scala:87:24] wire out_roready_50; // @[RegisterRouter.scala:87:24] wire out_roready_51; // @[RegisterRouter.scala:87:24] wire out_roready_52; // @[RegisterRouter.scala:87:24] wire out_roready_53; // @[RegisterRouter.scala:87:24] wire out_roready_54; // @[RegisterRouter.scala:87:24] wire out_roready_55; // @[RegisterRouter.scala:87:24] wire out_roready_56; // @[RegisterRouter.scala:87:24] wire out_roready_57; // @[RegisterRouter.scala:87:24] wire out_roready_58; // @[RegisterRouter.scala:87:24] wire out_roready_59; // @[RegisterRouter.scala:87:24] wire out_roready_60; // @[RegisterRouter.scala:87:24] wire out_roready_61; // @[RegisterRouter.scala:87:24] wire out_roready_62; // @[RegisterRouter.scala:87:24] wire out_roready_63; // @[RegisterRouter.scala:87:24] wire out_roready_64; // @[RegisterRouter.scala:87:24] wire out_roready_65; // @[RegisterRouter.scala:87:24] wire out_roready_66; // @[RegisterRouter.scala:87:24] wire out_roready_67; // @[RegisterRouter.scala:87:24] wire out_roready_68; // @[RegisterRouter.scala:87:24] wire out_roready_69; // @[RegisterRouter.scala:87:24] wire out_roready_70; // @[RegisterRouter.scala:87:24] wire out_roready_71; // @[RegisterRouter.scala:87:24] wire out_roready_72; // @[RegisterRouter.scala:87:24] wire out_roready_73; // @[RegisterRouter.scala:87:24] wire out_roready_74; // @[RegisterRouter.scala:87:24] wire out_roready_75; // @[RegisterRouter.scala:87:24] wire out_roready_76; // @[RegisterRouter.scala:87:24] wire out_roready_77; // @[RegisterRouter.scala:87:24] wire out_roready_78; // @[RegisterRouter.scala:87:24] wire out_roready_79; // @[RegisterRouter.scala:87:24] wire out_roready_80; // @[RegisterRouter.scala:87:24] wire out_roready_81; // @[RegisterRouter.scala:87:24] wire out_roready_82; // @[RegisterRouter.scala:87:24] wire out_roready_83; // @[RegisterRouter.scala:87:24] wire out_roready_84; // @[RegisterRouter.scala:87:24] wire out_roready_85; // @[RegisterRouter.scala:87:24] wire out_roready_86; // @[RegisterRouter.scala:87:24] wire out_roready_87; // @[RegisterRouter.scala:87:24] wire out_roready_88; // @[RegisterRouter.scala:87:24] wire out_roready_89; // @[RegisterRouter.scala:87:24] wire out_roready_90; // @[RegisterRouter.scala:87:24] wire out_roready_91; // @[RegisterRouter.scala:87:24] wire out_roready_92; // @[RegisterRouter.scala:87:24] wire out_roready_93; // @[RegisterRouter.scala:87:24] wire out_roready_94; // @[RegisterRouter.scala:87:24] wire out_roready_95; // @[RegisterRouter.scala:87:24] wire out_roready_96; // @[RegisterRouter.scala:87:24] wire out_roready_97; // @[RegisterRouter.scala:87:24] wire out_roready_98; // @[RegisterRouter.scala:87:24] wire out_roready_99; // @[RegisterRouter.scala:87:24] wire out_roready_100; // @[RegisterRouter.scala:87:24] wire out_roready_101; // @[RegisterRouter.scala:87:24] wire out_roready_102; // @[RegisterRouter.scala:87:24] wire out_roready_103; // @[RegisterRouter.scala:87:24] wire out_roready_104; // @[RegisterRouter.scala:87:24] wire out_roready_105; // @[RegisterRouter.scala:87:24] wire out_roready_106; // @[RegisterRouter.scala:87:24] wire out_roready_107; // @[RegisterRouter.scala:87:24] wire out_roready_108; // @[RegisterRouter.scala:87:24] wire out_roready_109; // @[RegisterRouter.scala:87:24] wire out_roready_110; // @[RegisterRouter.scala:87:24] wire out_roready_111; // @[RegisterRouter.scala:87:24] wire out_roready_112; // @[RegisterRouter.scala:87:24] wire out_roready_113; // @[RegisterRouter.scala:87:24] wire out_roready_114; // @[RegisterRouter.scala:87:24] wire out_roready_115; // @[RegisterRouter.scala:87:24] wire out_roready_116; // @[RegisterRouter.scala:87:24] wire out_roready_117; // @[RegisterRouter.scala:87:24] wire out_roready_118; // @[RegisterRouter.scala:87:24] wire out_roready_119; // @[RegisterRouter.scala:87:24] wire out_roready_120; // @[RegisterRouter.scala:87:24] wire out_roready_121; // @[RegisterRouter.scala:87:24] wire out_roready_122; // @[RegisterRouter.scala:87:24] wire out_roready_123; // @[RegisterRouter.scala:87:24] wire out_roready_124; // @[RegisterRouter.scala:87:24] wire out_roready_125; // @[RegisterRouter.scala:87:24] wire out_roready_126; // @[RegisterRouter.scala:87:24] wire out_roready_127; // @[RegisterRouter.scala:87:24] wire out_roready_128; // @[RegisterRouter.scala:87:24] wire out_roready_129; // @[RegisterRouter.scala:87:24] wire out_roready_130; // @[RegisterRouter.scala:87:24] wire out_roready_131; // @[RegisterRouter.scala:87:24] wire out_roready_132; // @[RegisterRouter.scala:87:24] wire out_roready_133; // @[RegisterRouter.scala:87:24] wire out_roready_134; // @[RegisterRouter.scala:87:24] wire out_roready_135; // @[RegisterRouter.scala:87:24] wire out_roready_136; // @[RegisterRouter.scala:87:24] wire out_roready_137; // @[RegisterRouter.scala:87:24] wire out_roready_138; // @[RegisterRouter.scala:87:24] wire out_roready_139; // @[RegisterRouter.scala:87:24] wire out_roready_140; // @[RegisterRouter.scala:87:24] wire out_roready_141; // @[RegisterRouter.scala:87:24] wire out_roready_142; // @[RegisterRouter.scala:87:24] wire out_roready_143; // @[RegisterRouter.scala:87:24] wire out_roready_144; // @[RegisterRouter.scala:87:24] wire out_roready_145; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire out_woready_18; // @[RegisterRouter.scala:87:24] wire out_woready_19; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_21; // @[RegisterRouter.scala:87:24] wire out_woready_22; // @[RegisterRouter.scala:87:24] wire out_woready_23; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire out_woready_25; // @[RegisterRouter.scala:87:24] wire out_woready_26; // @[RegisterRouter.scala:87:24] wire out_woready_27; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_29; // @[RegisterRouter.scala:87:24] wire out_woready_30; // @[RegisterRouter.scala:87:24] wire out_woready_31; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_33; // @[RegisterRouter.scala:87:24] wire out_woready_34; // @[RegisterRouter.scala:87:24] wire out_woready_35; // @[RegisterRouter.scala:87:24] wire out_woready_36; // @[RegisterRouter.scala:87:24] wire out_woready_37; // @[RegisterRouter.scala:87:24] wire out_woready_38; // @[RegisterRouter.scala:87:24] wire out_woready_39; // @[RegisterRouter.scala:87:24] wire out_woready_40; // @[RegisterRouter.scala:87:24] wire out_woready_41; // @[RegisterRouter.scala:87:24] wire out_woready_42; // @[RegisterRouter.scala:87:24] wire out_woready_43; // @[RegisterRouter.scala:87:24] wire out_woready_44; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_46; // @[RegisterRouter.scala:87:24] wire out_woready_47; // @[RegisterRouter.scala:87:24] wire out_woready_48; // @[RegisterRouter.scala:87:24] wire out_woready_49; // @[RegisterRouter.scala:87:24] wire out_woready_50; // @[RegisterRouter.scala:87:24] wire out_woready_51; // @[RegisterRouter.scala:87:24] wire out_woready_52; // @[RegisterRouter.scala:87:24] wire out_woready_53; // @[RegisterRouter.scala:87:24] wire out_woready_54; // @[RegisterRouter.scala:87:24] wire out_woready_55; // @[RegisterRouter.scala:87:24] wire out_woready_56; // @[RegisterRouter.scala:87:24] wire out_woready_57; // @[RegisterRouter.scala:87:24] wire out_woready_58; // @[RegisterRouter.scala:87:24] wire out_woready_59; // @[RegisterRouter.scala:87:24] wire out_woready_60; // @[RegisterRouter.scala:87:24] wire out_woready_61; // @[RegisterRouter.scala:87:24] wire out_woready_62; // @[RegisterRouter.scala:87:24] wire out_woready_63; // @[RegisterRouter.scala:87:24] wire out_woready_64; // @[RegisterRouter.scala:87:24] wire out_woready_65; // @[RegisterRouter.scala:87:24] wire out_woready_66; // @[RegisterRouter.scala:87:24] wire out_woready_67; // @[RegisterRouter.scala:87:24] wire out_woready_68; // @[RegisterRouter.scala:87:24] wire out_woready_69; // @[RegisterRouter.scala:87:24] wire out_woready_70; // @[RegisterRouter.scala:87:24] wire out_woready_71; // @[RegisterRouter.scala:87:24] wire out_woready_72; // @[RegisterRouter.scala:87:24] wire out_woready_73; // @[RegisterRouter.scala:87:24] wire out_woready_74; // @[RegisterRouter.scala:87:24] wire out_woready_75; // @[RegisterRouter.scala:87:24] wire out_woready_76; // @[RegisterRouter.scala:87:24] wire out_woready_77; // @[RegisterRouter.scala:87:24] wire out_woready_78; // @[RegisterRouter.scala:87:24] wire out_woready_79; // @[RegisterRouter.scala:87:24] wire out_woready_80; // @[RegisterRouter.scala:87:24] wire out_woready_81; // @[RegisterRouter.scala:87:24] wire out_woready_82; // @[RegisterRouter.scala:87:24] wire out_woready_83; // @[RegisterRouter.scala:87:24] wire out_woready_84; // @[RegisterRouter.scala:87:24] wire out_woready_85; // @[RegisterRouter.scala:87:24] wire out_woready_86; // @[RegisterRouter.scala:87:24] wire out_woready_87; // @[RegisterRouter.scala:87:24] wire out_woready_88; // @[RegisterRouter.scala:87:24] wire out_woready_89; // @[RegisterRouter.scala:87:24] wire out_woready_90; // @[RegisterRouter.scala:87:24] wire out_woready_91; // @[RegisterRouter.scala:87:24] wire out_woready_92; // @[RegisterRouter.scala:87:24] wire out_woready_93; // @[RegisterRouter.scala:87:24] wire out_woready_94; // @[RegisterRouter.scala:87:24] wire out_woready_95; // @[RegisterRouter.scala:87:24] wire out_woready_96; // @[RegisterRouter.scala:87:24] wire out_woready_97; // @[RegisterRouter.scala:87:24] wire out_woready_98; // @[RegisterRouter.scala:87:24] wire out_woready_99; // @[RegisterRouter.scala:87:24] wire out_woready_100; // @[RegisterRouter.scala:87:24] wire out_woready_101; // @[RegisterRouter.scala:87:24] wire out_woready_102; // @[RegisterRouter.scala:87:24] wire out_woready_103; // @[RegisterRouter.scala:87:24] wire out_woready_104; // @[RegisterRouter.scala:87:24] wire out_woready_105; // @[RegisterRouter.scala:87:24] wire out_woready_106; // @[RegisterRouter.scala:87:24] wire out_woready_107; // @[RegisterRouter.scala:87:24] wire out_woready_108; // @[RegisterRouter.scala:87:24] wire out_woready_109; // @[RegisterRouter.scala:87:24] wire out_woready_110; // @[RegisterRouter.scala:87:24] wire out_woready_111; // @[RegisterRouter.scala:87:24] wire out_woready_112; // @[RegisterRouter.scala:87:24] wire out_woready_113; // @[RegisterRouter.scala:87:24] wire out_woready_114; // @[RegisterRouter.scala:87:24] wire out_woready_115; // @[RegisterRouter.scala:87:24] wire out_woready_116; // @[RegisterRouter.scala:87:24] wire out_woready_117; // @[RegisterRouter.scala:87:24] wire out_woready_118; // @[RegisterRouter.scala:87:24] wire out_woready_119; // @[RegisterRouter.scala:87:24] wire out_woready_120; // @[RegisterRouter.scala:87:24] wire out_woready_121; // @[RegisterRouter.scala:87:24] wire out_woready_122; // @[RegisterRouter.scala:87:24] wire out_woready_123; // @[RegisterRouter.scala:87:24] wire out_woready_124; // @[RegisterRouter.scala:87:24] wire out_woready_125; // @[RegisterRouter.scala:87:24] wire out_woready_126; // @[RegisterRouter.scala:87:24] wire out_woready_127; // @[RegisterRouter.scala:87:24] wire out_woready_128; // @[RegisterRouter.scala:87:24] wire out_woready_129; // @[RegisterRouter.scala:87:24] wire out_woready_130; // @[RegisterRouter.scala:87:24] wire out_woready_131; // @[RegisterRouter.scala:87:24] wire out_woready_132; // @[RegisterRouter.scala:87:24] wire out_woready_133; // @[RegisterRouter.scala:87:24] wire out_woready_134; // @[RegisterRouter.scala:87:24] wire out_woready_135; // @[RegisterRouter.scala:87:24] wire out_woready_136; // @[RegisterRouter.scala:87:24] wire out_woready_137; // @[RegisterRouter.scala:87:24] wire out_woready_138; // @[RegisterRouter.scala:87:24] wire out_woready_139; // @[RegisterRouter.scala:87:24] wire out_woready_140; // @[RegisterRouter.scala:87:24] wire out_woready_141; // @[RegisterRouter.scala:87:24] wire out_woready_142; // @[RegisterRouter.scala:87:24] wire out_woready_143; // @[RegisterRouter.scala:87:24] wire out_woready_144; // @[RegisterRouter.scala:87:24] wire out_woready_145; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_4 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_5 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_6 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_7 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo = {_out_frontMask_T_5, _out_frontMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi = {_out_frontMask_T_7, _out_frontMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_63 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_68 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_81 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_140 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_145 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_4 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_5 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_6 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_7 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo = {_out_backMask_T_5, _out_backMask_T_4}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi = {_out_backMask_T_7, _out_backMask_T_6}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_63 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_68 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_81 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_140 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_145 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_48 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_55 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_64 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_69 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_101 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_116 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_141 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_48 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_55 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_64 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_69 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_101 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_116 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_141 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_69 = out_f_rivalid; // @[RegisterRouter.scala:87:24] assign out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_4 = out_f_roready; // @[RegisterRouter.scala:87:24] wire _out_T_70 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_wivalid; // @[RegisterRouter.scala:87:24] assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_4 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_68 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_123 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_167 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_211 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_255 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_299 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_343 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_387 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_578 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_622 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_653 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_697 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_752 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_807 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_851 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_895 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1119 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1163 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1272 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1316 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1360 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1404 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1448 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1492 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1547 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_4 = out_f_woready ? _out_T_68 : abstractDataMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_74 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_78 = _out_T_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = _out_T_78; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_18 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_49 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_56 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_65 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_70 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_102 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_117 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_142 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_18 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_49 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_56 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_65 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_70 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_102 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_117 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_142 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_80 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_5 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire _out_T_81 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_5 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_79 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_134 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_178 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_222 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_266 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_310 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_354 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_398 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_589 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_633 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_664 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_708 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_763 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_818 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_862 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_906 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1130 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1174 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1283 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1327 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1371 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1415 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1459 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1503 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1558 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_5 = out_f_woready_1 ? _out_T_79 : abstractDataMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_85 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend = {abstractDataMem_5, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_88 = out_prepend; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_89 = _out_T_88; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = _out_T_89; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_19 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_50 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_57 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_66 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_71 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_103 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_118 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_143 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_19 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_50 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_57 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_66 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_71 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_103 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_118 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_143 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_91 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_6 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire _out_T_92 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_6 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_90 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_145 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_189 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_233 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_277 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_321 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_365 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_409 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_600 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_675 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_719 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_774 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_829 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_873 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_917 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1141 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1185 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1294 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1338 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1382 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1426 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1470 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1514 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1569 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_6 = out_f_woready_2 ? _out_T_90 : abstractDataMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_95 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_96 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1 = {abstractDataMem_6, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_99 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_100 = _out_T_99; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = _out_T_100; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_20 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_51 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_58 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_67 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_72 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_104 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_119 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_144 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_20 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_51 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_58 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_67 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_72 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_104 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_119 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_144 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_102 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_7 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire _out_T_103 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_7 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_101 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_156 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_200 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_244 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_288 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_332 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_376 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_420 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_611 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_686 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_730 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_785 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_840 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_884 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_928 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1152 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1196 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1305 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1349 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1393 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1437 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1481 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1525 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1580 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_7 = out_f_woready_3 ? _out_T_101 : abstractDataMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_107 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_2 = {abstractDataMem_7, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_110 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_111 = _out_T_110; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_5 = _out_T_111; // @[MuxLiteral.scala:49:48] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_1 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_1 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_woready_4; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_1 = out_f_woready_4 ? _out_T_112 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_117 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_118 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_122 = _out_T_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_61 = _out_T_122; // @[MuxLiteral.scala:49:48] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_124 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_20 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire _out_T_125 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_20 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_woready_5; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_20 = out_f_woready_5 ? _out_T_123 : abstractDataMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_128 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_129 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_133 = _out_T_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_3 = _out_T_133; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_135 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_21 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_136 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_21 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_woready_6; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_21 = out_f_woready_6 ? _out_T_134 : abstractDataMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_139 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_140 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_3 = {abstractDataMem_21, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_143 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_144 = _out_T_143; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_4 = _out_T_144; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_146 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_22 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire _out_T_147 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_22 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_woready_7; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_22 = out_f_woready_7 ? _out_T_145 : abstractDataMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_150 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_4 = {abstractDataMem_22, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_154 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_155 = _out_T_154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_5 = _out_T_155; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_157 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_23 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_23 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_woready_8; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_23 = out_f_woready_8 ? _out_T_156 : abstractDataMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_161 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_5 = {abstractDataMem_23, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_165 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_166 = _out_T_165; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_9 = _out_T_166; // @[MuxLiteral.scala:49:48] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_168 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_36 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_169 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_36 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_woready_9; // @[RegisterRouter.scala:87:24] assign programBufferNxt_36 = out_f_woready_9 ? _out_T_167 : programBufferMem_36; // @[RegisterRouter.scala:87:24] wire _out_T_172 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_173 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_177 = _out_T_176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_6 = _out_T_177; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_179 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_37 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire _out_T_180 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_37 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign programBufferNxt_37 = out_f_woready_10 ? _out_T_178 : programBufferMem_37; // @[RegisterRouter.scala:87:24] wire _out_T_183 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_184 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_6 = {programBufferMem_37, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_187 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_188 = _out_T_187; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_7 = _out_T_188; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_190 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_38 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire _out_T_191 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_38 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign programBufferNxt_38 = out_f_woready_11 ? _out_T_189 : programBufferMem_38; // @[RegisterRouter.scala:87:24] wire _out_T_194 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_195 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_7 = {programBufferMem_38, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_198 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_199 = _out_T_198; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_8 = _out_T_199; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_201 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_39 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire _out_T_202 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_203 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_39 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_204 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign programBufferNxt_39 = out_f_woready_12 ? _out_T_200 : programBufferMem_39; // @[RegisterRouter.scala:87:24] wire _out_T_205 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_206 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_207 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_208 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_8 = {programBufferMem_39, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_209 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_210 = _out_T_209; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_41 = _out_T_210; // @[MuxLiteral.scala:49:48] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_212 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_12 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire _out_T_213 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_214 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_12 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_215 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign programBufferNxt_12 = out_f_woready_13 ? _out_T_211 : programBufferMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_216 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_217 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_218 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_219 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_221 = _out_T_220; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_9 = _out_T_221; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_223 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_13 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire _out_T_224 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_225 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_13 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_226 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign programBufferNxt_13 = out_f_woready_14 ? _out_T_222 : programBufferMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_227 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_228 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_229 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_230 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_9 = {programBufferMem_13, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_231 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_232 = _out_T_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_10 = _out_T_232; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_234 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_14 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire _out_T_235 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_236 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_14 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_237 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign programBufferNxt_14 = out_f_woready_15 ? _out_T_233 : programBufferMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_238 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_239 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_240 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_241 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_10 = {programBufferMem_14, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_242 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_243 = _out_T_242; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_11 = _out_T_243; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_245 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_15 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire _out_T_246 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_247 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_15 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_248 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign programBufferNxt_15 = out_f_woready_16 ? _out_T_244 : programBufferMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_249 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_250 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_251 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_252 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_11 = {programBufferMem_15, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_253 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_254 = _out_T_253; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_35 = _out_T_254; // @[MuxLiteral.scala:49:48] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_256 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_16 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire _out_T_257 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_258 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_16 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_259 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_16 = out_f_woready_17 ? _out_T_255 : abstractDataMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_260 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_261 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_262 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_263 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_265 = _out_T_264; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_12 = _out_T_265; // @[RegisterRouter.scala:87:24] wire out_rimask_18 = |_out_rimask_T_18; // @[RegisterRouter.scala:87:24] wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24] wire out_romask_18 = |_out_romask_T_18; // @[RegisterRouter.scala:87:24] wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_267 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_17 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire _out_T_268 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_269 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_17 = out_f_woready_18; // @[RegisterRouter.scala:87:24] wire _out_T_270 = out_f_woready_18; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_17 = out_f_woready_18 ? _out_T_266 : abstractDataMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_271 = ~out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_272 = ~out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_273 = ~out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_274 = ~out_womask_18; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_12 = {abstractDataMem_17, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_275 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_276 = _out_T_275; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_13 = _out_T_276; // @[RegisterRouter.scala:87:24] wire out_rimask_19 = |_out_rimask_T_19; // @[RegisterRouter.scala:87:24] wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24] wire out_romask_19 = |_out_romask_T_19; // @[RegisterRouter.scala:87:24] wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_278 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_18 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire _out_T_279 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_280 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_18 = out_f_woready_19; // @[RegisterRouter.scala:87:24] wire _out_T_281 = out_f_woready_19; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_18 = out_f_woready_19 ? _out_T_277 : abstractDataMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_282 = ~out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_283 = ~out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_284 = ~out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_285 = ~out_womask_19; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_13 = {abstractDataMem_18, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_286 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_287 = _out_T_286; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_14 = _out_T_287; // @[RegisterRouter.scala:87:24] wire out_rimask_20 = |_out_rimask_T_20; // @[RegisterRouter.scala:87:24] wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24] wire out_romask_20 = |_out_romask_T_20; // @[RegisterRouter.scala:87:24] wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_289 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_19 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire _out_T_290 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_291 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_19 = out_f_woready_20; // @[RegisterRouter.scala:87:24] wire _out_T_292 = out_f_woready_20; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_19 = out_f_woready_20 ? _out_T_288 : abstractDataMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_293 = ~out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_294 = ~out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_295 = ~out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_296 = ~out_womask_20; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_14 = {abstractDataMem_19, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_297 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_298 = _out_T_297; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_8 = _out_T_298; // @[MuxLiteral.scala:49:48] wire out_rimask_21 = |_out_rimask_T_21; // @[RegisterRouter.scala:87:24] wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24] wire out_romask_21 = |_out_romask_T_21; // @[RegisterRouter.scala:87:24] wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_300 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_0 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire _out_T_301 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_302 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_0 = out_f_woready_21; // @[RegisterRouter.scala:87:24] wire _out_T_303 = out_f_woready_21; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_0 = out_f_woready_21 ? _out_T_299 : abstractDataMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_304 = ~out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_305 = ~out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_306 = ~out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_307 = ~out_womask_21; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_309 = _out_T_308; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_15 = _out_T_309; // @[RegisterRouter.scala:87:24] wire out_rimask_22 = |_out_rimask_T_22; // @[RegisterRouter.scala:87:24] wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24] wire out_romask_22 = |_out_romask_T_22; // @[RegisterRouter.scala:87:24] wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_311 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_1 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire _out_T_312 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_313 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_1 = out_f_woready_22; // @[RegisterRouter.scala:87:24] wire _out_T_314 = out_f_woready_22; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_1 = out_f_woready_22 ? _out_T_310 : abstractDataMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_315 = ~out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_316 = ~out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_317 = ~out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_318 = ~out_womask_22; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_15 = {abstractDataMem_1, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_319 = out_prepend_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_320 = _out_T_319; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_16 = _out_T_320; // @[RegisterRouter.scala:87:24] wire out_rimask_23 = |_out_rimask_T_23; // @[RegisterRouter.scala:87:24] wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24] wire out_romask_23 = |_out_romask_T_23; // @[RegisterRouter.scala:87:24] wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_322 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_2 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire _out_T_323 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_324 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_2 = out_f_woready_23; // @[RegisterRouter.scala:87:24] wire _out_T_325 = out_f_woready_23; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_2 = out_f_woready_23 ? _out_T_321 : abstractDataMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_326 = ~out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_327 = ~out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_328 = ~out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_329 = ~out_womask_23; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_16 = {abstractDataMem_2, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_330 = out_prepend_16; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_331 = _out_T_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_17 = _out_T_331; // @[RegisterRouter.scala:87:24] wire out_rimask_24 = |_out_rimask_T_24; // @[RegisterRouter.scala:87:24] wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24] wire out_romask_24 = |_out_romask_T_24; // @[RegisterRouter.scala:87:24] wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_333 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_3 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire _out_T_334 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_335 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_3 = out_f_woready_24; // @[RegisterRouter.scala:87:24] wire _out_T_336 = out_f_woready_24; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_3 = out_f_woready_24 ? _out_T_332 : abstractDataMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_337 = ~out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_338 = ~out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_339 = ~out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_340 = ~out_womask_24; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_17 = {abstractDataMem_3, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_341 = out_prepend_17; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_342 = _out_T_341; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_4 = _out_T_342; // @[MuxLiteral.scala:49:48] wire out_rimask_25 = |_out_rimask_T_25; // @[RegisterRouter.scala:87:24] wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24] wire out_romask_25 = |_out_romask_T_25; // @[RegisterRouter.scala:87:24] wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_344 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_60 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire _out_T_345 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_346 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_60 = out_f_woready_25; // @[RegisterRouter.scala:87:24] wire _out_T_347 = out_f_woready_25; // @[RegisterRouter.scala:87:24] assign programBufferNxt_60 = out_f_woready_25 ? _out_T_343 : programBufferMem_60; // @[RegisterRouter.scala:87:24] wire _out_T_348 = ~out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_349 = ~out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_350 = ~out_romask_25; // @[RegisterRouter.scala:87:24] wire _out_T_351 = ~out_womask_25; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_353 = _out_T_352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_18 = _out_T_353; // @[RegisterRouter.scala:87:24] wire out_rimask_26 = |_out_rimask_T_26; // @[RegisterRouter.scala:87:24] wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24] wire out_romask_26 = |_out_romask_T_26; // @[RegisterRouter.scala:87:24] wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_355 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_61 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire _out_T_356 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_357 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_61 = out_f_woready_26; // @[RegisterRouter.scala:87:24] wire _out_T_358 = out_f_woready_26; // @[RegisterRouter.scala:87:24] assign programBufferNxt_61 = out_f_woready_26 ? _out_T_354 : programBufferMem_61; // @[RegisterRouter.scala:87:24] wire _out_T_359 = ~out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_360 = ~out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_361 = ~out_romask_26; // @[RegisterRouter.scala:87:24] wire _out_T_362 = ~out_womask_26; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_18 = {programBufferMem_61, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_363 = out_prepend_18; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_364 = _out_T_363; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_19 = _out_T_364; // @[RegisterRouter.scala:87:24] wire out_rimask_27 = |_out_rimask_T_27; // @[RegisterRouter.scala:87:24] wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24] wire out_romask_27 = |_out_romask_T_27; // @[RegisterRouter.scala:87:24] wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_366 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_62 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire _out_T_367 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_368 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_62 = out_f_woready_27; // @[RegisterRouter.scala:87:24] wire _out_T_369 = out_f_woready_27; // @[RegisterRouter.scala:87:24] assign programBufferNxt_62 = out_f_woready_27 ? _out_T_365 : programBufferMem_62; // @[RegisterRouter.scala:87:24] wire _out_T_370 = ~out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_371 = ~out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_372 = ~out_romask_27; // @[RegisterRouter.scala:87:24] wire _out_T_373 = ~out_womask_27; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_19 = {programBufferMem_62, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_374 = out_prepend_19; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_375 = _out_T_374; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_20 = _out_T_375; // @[RegisterRouter.scala:87:24] wire out_rimask_28 = |_out_rimask_T_28; // @[RegisterRouter.scala:87:24] wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24] wire out_romask_28 = |_out_romask_T_28; // @[RegisterRouter.scala:87:24] wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_377 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_63 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire _out_T_378 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_379 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_63 = out_f_woready_28; // @[RegisterRouter.scala:87:24] wire _out_T_380 = out_f_woready_28; // @[RegisterRouter.scala:87:24] assign programBufferNxt_63 = out_f_woready_28 ? _out_T_376 : programBufferMem_63; // @[RegisterRouter.scala:87:24] wire _out_T_381 = ~out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_382 = ~out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_383 = ~out_romask_28; // @[RegisterRouter.scala:87:24] wire _out_T_384 = ~out_womask_28; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_20 = {programBufferMem_63, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_385 = out_prepend_20; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_386 = _out_T_385; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_47 = _out_T_386; // @[MuxLiteral.scala:49:48] wire out_rimask_29 = |_out_rimask_T_29; // @[RegisterRouter.scala:87:24] wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24] wire out_romask_29 = |_out_romask_T_29; // @[RegisterRouter.scala:87:24] wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_388 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_24 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire _out_T_389 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_390 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_24 = out_f_woready_29; // @[RegisterRouter.scala:87:24] wire _out_T_391 = out_f_woready_29; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_24 = out_f_woready_29 ? _out_T_387 : abstractDataMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_392 = ~out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_393 = ~out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_394 = ~out_romask_29; // @[RegisterRouter.scala:87:24] wire _out_T_395 = ~out_womask_29; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_397 = _out_T_396; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_21 = _out_T_397; // @[RegisterRouter.scala:87:24] wire out_rimask_30 = |_out_rimask_T_30; // @[RegisterRouter.scala:87:24] wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24] wire out_romask_30 = |_out_romask_T_30; // @[RegisterRouter.scala:87:24] wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_399 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_25 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire _out_T_400 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_401 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_25 = out_f_woready_30; // @[RegisterRouter.scala:87:24] wire _out_T_402 = out_f_woready_30; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_25 = out_f_woready_30 ? _out_T_398 : abstractDataMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_403 = ~out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_404 = ~out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_405 = ~out_romask_30; // @[RegisterRouter.scala:87:24] wire _out_T_406 = ~out_womask_30; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_21 = {abstractDataMem_25, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_407 = out_prepend_21; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_408 = _out_T_407; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_22 = _out_T_408; // @[RegisterRouter.scala:87:24] wire out_rimask_31 = |_out_rimask_T_31; // @[RegisterRouter.scala:87:24] wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24] wire out_romask_31 = |_out_romask_T_31; // @[RegisterRouter.scala:87:24] wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_410 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_26 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire _out_T_411 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_412 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_26 = out_f_woready_31; // @[RegisterRouter.scala:87:24] wire _out_T_413 = out_f_woready_31; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_26 = out_f_woready_31 ? _out_T_409 : abstractDataMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_414 = ~out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_415 = ~out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_416 = ~out_romask_31; // @[RegisterRouter.scala:87:24] wire _out_T_417 = ~out_womask_31; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_22 = {abstractDataMem_26, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_418 = out_prepend_22; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_419 = _out_T_418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_23 = _out_T_419; // @[RegisterRouter.scala:87:24] wire out_rimask_32 = |_out_rimask_T_32; // @[RegisterRouter.scala:87:24] wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24] wire out_romask_32 = |_out_romask_T_32; // @[RegisterRouter.scala:87:24] wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_421 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_27 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire _out_T_422 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_423 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_27 = out_f_woready_32; // @[RegisterRouter.scala:87:24] wire _out_T_424 = out_f_woready_32; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_27 = out_f_woready_32 ? _out_T_420 : abstractDataMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_425 = ~out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_426 = ~out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_427 = ~out_romask_32; // @[RegisterRouter.scala:87:24] wire _out_T_428 = ~out_womask_32; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_23 = {abstractDataMem_27, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_429 = out_prepend_23; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_430 = _out_T_429; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_10 = _out_T_430; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_33 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_33 = _out_rimask_T_33; // @[RegisterRouter.scala:87:24] wire out_wimask_33 = _out_wimask_T_33; // @[RegisterRouter.scala:87:24] wire _out_romask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_33 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_33 = _out_romask_T_33; // @[RegisterRouter.scala:87:24] wire out_womask_33 = _out_womask_T_33; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_432 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_433 = out_f_roready_33; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24] wire out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_T_431 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_434 = ~out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_435 = ~out_wimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_436 = ~out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_437 = ~out_womask_33; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_34 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_34 = _out_rimask_T_34; // @[RegisterRouter.scala:87:24] wire out_wimask_34 = _out_wimask_T_34; // @[RegisterRouter.scala:87:24] wire _out_romask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_34 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_34 = _out_romask_T_34; // @[RegisterRouter.scala:87:24] wire out_womask_34 = _out_womask_T_34; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_441 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_442 = out_f_roready_34; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24] wire out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_T_440 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_443 = ~out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_444 = ~out_wimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_445 = ~out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_446 = ~out_womask_34; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_35 = out_frontMask[2]; // @[RegisterRouter.scala:87:24] wire out_rimask_35 = _out_rimask_T_35; // @[RegisterRouter.scala:87:24] wire out_wimask_35 = _out_wimask_T_35; // @[RegisterRouter.scala:87:24] wire _out_romask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_35 = out_backMask[2]; // @[RegisterRouter.scala:87:24] wire out_romask_35 = _out_romask_T_35; // @[RegisterRouter.scala:87:24] wire out_womask_35 = _out_womask_T_35; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_450 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_451 = out_f_roready_35; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24] wire out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_T_449 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24] wire _out_T_452 = ~out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_453 = ~out_wimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_454 = ~out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_455 = ~out_womask_35; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_36 = out_frontMask[3]; // @[RegisterRouter.scala:87:24] wire out_rimask_36 = _out_rimask_T_36; // @[RegisterRouter.scala:87:24] wire out_wimask_36 = _out_wimask_T_36; // @[RegisterRouter.scala:87:24] wire _out_romask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_36 = out_backMask[3]; // @[RegisterRouter.scala:87:24] wire out_romask_36 = _out_romask_T_36; // @[RegisterRouter.scala:87:24] wire out_womask_36 = _out_womask_T_36; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_459 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_460 = out_f_roready_36; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24] wire out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_T_458 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24] wire _out_T_461 = ~out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_462 = ~out_wimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_463 = ~out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_464 = ~out_womask_36; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_37 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_83 = out_frontMask[4]; // @[RegisterRouter.scala:87:24] wire out_rimask_37 = _out_rimask_T_37; // @[RegisterRouter.scala:87:24] wire out_wimask_37 = _out_wimask_T_37; // @[RegisterRouter.scala:87:24] wire _out_romask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_37 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_83 = out_backMask[4]; // @[RegisterRouter.scala:87:24] wire out_romask_37 = _out_romask_T_37; // @[RegisterRouter.scala:87:24] wire out_womask_37 = _out_womask_T_37; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_468 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_469 = out_f_roready_37; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24] wire out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24] wire _out_T_467 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_957 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24] wire _out_T_470 = ~out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_471 = ~out_wimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_472 = ~out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_473 = ~out_womask_37; // @[RegisterRouter.scala:87:24] wire [6:0] _out_rimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_wimask_T_38 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_rimask_38 = |_out_rimask_T_38; // @[RegisterRouter.scala:87:24] wire out_wimask_38 = &_out_wimask_T_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_romask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire [6:0] _out_womask_T_38 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24] wire out_romask_38 = |_out_romask_T_38; // @[RegisterRouter.scala:87:24] wire out_womask_38 = &_out_womask_T_38; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_477 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_478 = out_f_roready_38; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24] wire out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24] wire [6:0] _out_T_476 = out_front_bits_data[11:5]; // @[RegisterRouter.scala:87:24] wire _out_T_479 = ~out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_480 = ~out_wimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_481 = ~out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_482 = ~out_womask_38; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_39 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_rimask_39 = |_out_rimask_T_39; // @[RegisterRouter.scala:87:24] wire out_wimask_39 = &_out_wimask_T_39; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_39 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24] wire out_romask_39 = |_out_romask_T_39; // @[RegisterRouter.scala:87:24] wire out_womask_39 = &_out_womask_T_39; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_486 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_487 = out_f_roready_39; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_488 = out_f_wivalid_39; // @[RegisterRouter.scala:87:24] assign out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24] assign sberrorWrEn = out_f_woready_39; // @[RegisterRouter.scala:87:24] wire _out_T_489 = out_f_woready_39; // @[RegisterRouter.scala:87:24] assign _out_T_485 = out_front_bits_data[14:12]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sberror = _out_T_485; // @[RegisterRouter.scala:87:24] wire _out_T_490 = ~out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_491 = ~out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_492 = ~out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_493 = ~out_womask_39; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_29 = {SBCSRdData_sberror, 12'h40F}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_494 = out_prepend_29; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_495 = _out_T_494; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_30 = _out_T_495; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_40 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_94 = out_frontMask[15]; // @[RegisterRouter.scala:87:24] wire out_rimask_40 = _out_rimask_T_40; // @[RegisterRouter.scala:87:24] wire out_wimask_40 = _out_wimask_T_40; // @[RegisterRouter.scala:87:24] wire _out_romask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_40 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_94 = out_backMask[15]; // @[RegisterRouter.scala:87:24] wire out_romask_40 = _out_romask_T_40; // @[RegisterRouter.scala:87:24] wire out_womask_40 = _out_womask_T_40; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_497 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_498 = out_f_roready_40; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_499 = out_f_wivalid_40; // @[RegisterRouter.scala:87:24] assign out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24] assign sbreadondataWrEn = out_f_woready_40; // @[RegisterRouter.scala:87:24] wire _out_T_500 = out_f_woready_40; // @[RegisterRouter.scala:87:24] assign _out_T_496 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] wire _out_T_1056 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadondata = _out_T_496; // @[RegisterRouter.scala:87:24] wire _out_T_501 = ~out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_502 = ~out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_503 = ~out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_504 = ~out_womask_40; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_30 = {SBCSRdData_sbreadondata, _out_prepend_T_30}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_505 = out_prepend_30; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_506 = _out_T_505; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_31 = _out_T_506; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_41 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_95 = out_frontMask[16]; // @[RegisterRouter.scala:87:24] wire out_rimask_41 = _out_rimask_T_41; // @[RegisterRouter.scala:87:24] wire out_wimask_41 = _out_wimask_T_41; // @[RegisterRouter.scala:87:24] wire _out_romask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_41 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_95 = out_backMask[16]; // @[RegisterRouter.scala:87:24] wire out_romask_41 = _out_romask_T_41; // @[RegisterRouter.scala:87:24] wire out_womask_41 = _out_womask_T_41; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_508 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_509 = out_f_roready_41; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_510 = out_f_wivalid_41; // @[RegisterRouter.scala:87:24] assign out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24] assign sbautoincrementWrEn = out_f_woready_41; // @[RegisterRouter.scala:87:24] wire _out_T_511 = out_f_woready_41; // @[RegisterRouter.scala:87:24] assign _out_T_507 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] wire _out_T_1065 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbautoincrement = _out_T_507; // @[RegisterRouter.scala:87:24] wire _out_T_512 = ~out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_513 = ~out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_514 = ~out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_515 = ~out_womask_41; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_31 = {SBCSRdData_sbautoincrement, _out_prepend_T_31}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_516 = out_prepend_31; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_517 = _out_T_516; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_32 = _out_T_517; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_42 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_rimask_42 = |_out_rimask_T_42; // @[RegisterRouter.scala:87:24] wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_42 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24] wire out_romask_42 = |_out_romask_T_42; // @[RegisterRouter.scala:87:24] wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_519 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_520 = out_f_roready_42; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_521 = out_f_wivalid_42; // @[RegisterRouter.scala:87:24] assign out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24] assign sbaccessWrEn = out_f_woready_42; // @[RegisterRouter.scala:87:24] wire _out_T_522 = out_f_woready_42; // @[RegisterRouter.scala:87:24] assign _out_T_518 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbaccess = _out_T_518; // @[RegisterRouter.scala:87:24] wire _out_T_523 = ~out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_524 = ~out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_525 = ~out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_526 = ~out_womask_42; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_32 = {SBCSRdData_sbaccess, _out_prepend_T_32}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_527 = out_prepend_32; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_528 = _out_T_527; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_33 = _out_T_528; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_43 = out_frontMask[20]; // @[RegisterRouter.scala:87:24] wire out_rimask_43 = _out_rimask_T_43; // @[RegisterRouter.scala:87:24] wire out_wimask_43 = _out_wimask_T_43; // @[RegisterRouter.scala:87:24] wire _out_romask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_43 = out_backMask[20]; // @[RegisterRouter.scala:87:24] wire out_romask_43 = _out_romask_T_43; // @[RegisterRouter.scala:87:24] wire out_womask_43 = _out_womask_T_43; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_530 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_531 = out_f_roready_43; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_532 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24] assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24] assign sbreadonaddrWrEn = out_f_woready_43; // @[RegisterRouter.scala:87:24] wire _out_T_533 = out_f_woready_43; // @[RegisterRouter.scala:87:24] assign _out_T_529 = out_front_bits_data[20]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbreadonaddr = _out_T_529; // @[RegisterRouter.scala:87:24] wire _out_T_534 = ~out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_535 = ~out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_536 = ~out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_537 = ~out_womask_43; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_33 = {SBCSRdData_sbreadonaddr, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_538 = out_prepend_33; // @[RegisterRouter.scala:87:24] wire [20:0] _out_T_539 = _out_T_538; // @[RegisterRouter.scala:87:24] wire [20:0] _out_prepend_T_34 = _out_T_539; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_44 = out_frontMask[21]; // @[RegisterRouter.scala:87:24] wire out_rimask_44 = _out_rimask_T_44; // @[RegisterRouter.scala:87:24] wire out_wimask_44 = _out_wimask_T_44; // @[RegisterRouter.scala:87:24] wire _out_romask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_44 = out_backMask[21]; // @[RegisterRouter.scala:87:24] wire out_romask_44 = _out_romask_T_44; // @[RegisterRouter.scala:87:24] wire out_womask_44 = _out_womask_T_44; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_541 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_542 = out_f_roready_44; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24] wire out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24] wire _out_T_540 = out_front_bits_data[21]; // @[RegisterRouter.scala:87:24] wire _out_T_543 = ~out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_544 = ~out_wimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_545 = ~out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_546 = ~out_womask_44; // @[RegisterRouter.scala:87:24] wire [21:0] out_prepend_34 = {SBCSRdData_sbbusy, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_547 = out_prepend_34; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_548 = _out_T_547; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_35 = _out_T_548; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_45 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_100 = out_frontMask[22]; // @[RegisterRouter.scala:87:24] wire out_rimask_45 = _out_rimask_T_45; // @[RegisterRouter.scala:87:24] wire out_wimask_45 = _out_wimask_T_45; // @[RegisterRouter.scala:87:24] wire _out_romask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_45 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_100 = out_backMask[22]; // @[RegisterRouter.scala:87:24] wire out_romask_45 = _out_romask_T_45; // @[RegisterRouter.scala:87:24] wire out_womask_45 = _out_womask_T_45; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_550 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_551 = out_f_roready_45; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_552 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24] assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24] assign sbbusyerrorWrEn = out_f_woready_45; // @[RegisterRouter.scala:87:24] wire _out_T_553 = out_f_woready_45; // @[RegisterRouter.scala:87:24] assign _out_T_549 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] wire _out_T_1110 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24] assign SBCSWrData_sbbusyerror = _out_T_549; // @[RegisterRouter.scala:87:24] wire _out_T_554 = ~out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_555 = ~out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_556 = ~out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_557 = ~out_womask_45; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_35 = {SBCSRdData_sbbusyerror, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_558 = out_prepend_35; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_559 = _out_T_558; // @[RegisterRouter.scala:87:24] wire [22:0] _out_prepend_T_36 = _out_T_559; // @[RegisterRouter.scala:87:24] wire [5:0] _out_rimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_wimask_T_46 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_rimask_46 = |_out_rimask_T_46; // @[RegisterRouter.scala:87:24] wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_romask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire [5:0] _out_womask_T_46 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24] wire out_romask_46 = |_out_romask_T_46; // @[RegisterRouter.scala:87:24] wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_561 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_562 = out_f_roready_46; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24] wire out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24] wire [5:0] _out_T_560 = out_front_bits_data[28:23]; // @[RegisterRouter.scala:87:24] wire _out_T_563 = ~out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_564 = ~out_wimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_565 = ~out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_566 = ~out_womask_46; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_36 = {1'h0, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_567 = {5'h0, out_prepend_36}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_568 = _out_T_567; // @[RegisterRouter.scala:87:24] wire [28:0] _out_prepend_T_37 = _out_T_568; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_47 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_rimask_47 = |_out_rimask_T_47; // @[RegisterRouter.scala:87:24] wire out_wimask_47 = &_out_wimask_T_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_47 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24] wire out_romask_47 = |_out_romask_T_47; // @[RegisterRouter.scala:87:24] wire out_womask_47 = &_out_womask_T_47; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_570 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_571 = out_f_roready_47; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24] wire out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24] wire [2:0] _out_T_569 = out_front_bits_data[31:29]; // @[RegisterRouter.scala:87:24] wire _out_T_572 = ~out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_573 = ~out_wimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_574 = ~out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_575 = ~out_womask_47; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_37 = {3'h1, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_576 = out_prepend_37; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_577 = _out_T_576; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_56 = _out_T_577; // @[MuxLiteral.scala:49:48] wire out_rimask_48 = |_out_rimask_T_48; // @[RegisterRouter.scala:87:24] wire out_wimask_48 = &_out_wimask_T_48; // @[RegisterRouter.scala:87:24] wire out_romask_48 = |_out_romask_T_48; // @[RegisterRouter.scala:87:24] wire out_womask_48 = &_out_womask_T_48; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_48 = out_rivalid_48 & out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_579 = out_f_rivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_roready_48 = out_roready_48 & out_romask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_40 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire _out_T_580 = out_f_roready_48; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_48 = out_wivalid_48 & out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_581 = out_f_wivalid_48; // @[RegisterRouter.scala:87:24] assign out_f_woready_48 = out_woready_48 & out_womask_48; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_40 = out_f_woready_48; // @[RegisterRouter.scala:87:24] wire _out_T_582 = out_f_woready_48; // @[RegisterRouter.scala:87:24] assign programBufferNxt_40 = out_f_woready_48 ? _out_T_578 : programBufferMem_40; // @[RegisterRouter.scala:87:24] wire _out_T_583 = ~out_rimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_584 = ~out_wimask_48; // @[RegisterRouter.scala:87:24] wire _out_T_585 = ~out_romask_48; // @[RegisterRouter.scala:87:24] wire _out_T_586 = ~out_womask_48; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_588 = _out_T_587; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_38 = _out_T_588; // @[RegisterRouter.scala:87:24] wire out_rimask_49 = |_out_rimask_T_49; // @[RegisterRouter.scala:87:24] wire out_wimask_49 = &_out_wimask_T_49; // @[RegisterRouter.scala:87:24] wire out_romask_49 = |_out_romask_T_49; // @[RegisterRouter.scala:87:24] wire out_womask_49 = &_out_womask_T_49; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_49 = out_rivalid_49 & out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_590 = out_f_rivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_roready_49 = out_roready_49 & out_romask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_41 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire _out_T_591 = out_f_roready_49; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_49 = out_wivalid_49 & out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_592 = out_f_wivalid_49; // @[RegisterRouter.scala:87:24] assign out_f_woready_49 = out_woready_49 & out_womask_49; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_41 = out_f_woready_49; // @[RegisterRouter.scala:87:24] wire _out_T_593 = out_f_woready_49; // @[RegisterRouter.scala:87:24] assign programBufferNxt_41 = out_f_woready_49 ? _out_T_589 : programBufferMem_41; // @[RegisterRouter.scala:87:24] wire _out_T_594 = ~out_rimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_595 = ~out_wimask_49; // @[RegisterRouter.scala:87:24] wire _out_T_596 = ~out_romask_49; // @[RegisterRouter.scala:87:24] wire _out_T_597 = ~out_womask_49; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_38 = {programBufferMem_41, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_598 = out_prepend_38; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_599 = _out_T_598; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_39 = _out_T_599; // @[RegisterRouter.scala:87:24] wire out_rimask_50 = |_out_rimask_T_50; // @[RegisterRouter.scala:87:24] wire out_wimask_50 = &_out_wimask_T_50; // @[RegisterRouter.scala:87:24] wire out_romask_50 = |_out_romask_T_50; // @[RegisterRouter.scala:87:24] wire out_womask_50 = &_out_womask_T_50; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_50 = out_rivalid_50 & out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_601 = out_f_rivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_roready_50 = out_roready_50 & out_romask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_42 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire _out_T_602 = out_f_roready_50; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_50 = out_wivalid_50 & out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_603 = out_f_wivalid_50; // @[RegisterRouter.scala:87:24] assign out_f_woready_50 = out_woready_50 & out_womask_50; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_42 = out_f_woready_50; // @[RegisterRouter.scala:87:24] wire _out_T_604 = out_f_woready_50; // @[RegisterRouter.scala:87:24] assign programBufferNxt_42 = out_f_woready_50 ? _out_T_600 : programBufferMem_42; // @[RegisterRouter.scala:87:24] wire _out_T_605 = ~out_rimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_606 = ~out_wimask_50; // @[RegisterRouter.scala:87:24] wire _out_T_607 = ~out_romask_50; // @[RegisterRouter.scala:87:24] wire _out_T_608 = ~out_womask_50; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_39 = {programBufferMem_42, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_609 = out_prepend_39; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_610 = _out_T_609; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_40 = _out_T_610; // @[RegisterRouter.scala:87:24] wire out_rimask_51 = |_out_rimask_T_51; // @[RegisterRouter.scala:87:24] wire out_wimask_51 = &_out_wimask_T_51; // @[RegisterRouter.scala:87:24] wire out_romask_51 = |_out_romask_T_51; // @[RegisterRouter.scala:87:24] wire out_womask_51 = &_out_womask_T_51; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_51 = out_rivalid_51 & out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_612 = out_f_rivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_roready_51 = out_roready_51 & out_romask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_43 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire _out_T_613 = out_f_roready_51; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_51 = out_wivalid_51 & out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_614 = out_f_wivalid_51; // @[RegisterRouter.scala:87:24] assign out_f_woready_51 = out_woready_51 & out_womask_51; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_43 = out_f_woready_51; // @[RegisterRouter.scala:87:24] wire _out_T_615 = out_f_woready_51; // @[RegisterRouter.scala:87:24] assign programBufferNxt_43 = out_f_woready_51 ? _out_T_611 : programBufferMem_43; // @[RegisterRouter.scala:87:24] wire _out_T_616 = ~out_rimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_617 = ~out_wimask_51; // @[RegisterRouter.scala:87:24] wire _out_T_618 = ~out_romask_51; // @[RegisterRouter.scala:87:24] wire _out_T_619 = ~out_womask_51; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_40 = {programBufferMem_43, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_620 = out_prepend_40; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_621 = _out_T_620; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_42 = _out_T_621; // @[MuxLiteral.scala:49:48] wire out_rimask_52 = |_out_rimask_T_52; // @[RegisterRouter.scala:87:24] wire out_wimask_52 = &_out_wimask_T_52; // @[RegisterRouter.scala:87:24] wire out_romask_52 = |_out_romask_T_52; // @[RegisterRouter.scala:87:24] wire out_womask_52 = &_out_womask_T_52; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_52 = out_rivalid_52 & out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_623 = out_f_rivalid_52; // @[RegisterRouter.scala:87:24] wire out_f_roready_52 = out_roready_52 & out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_624 = out_f_roready_52; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_52 = out_wivalid_52 & out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_625 = out_f_wivalid_52; // @[RegisterRouter.scala:87:24] assign out_f_woready_52 = out_woready_52 & out_womask_52; // @[RegisterRouter.scala:87:24] assign autoexecdataWrEnMaybe = out_f_woready_52; // @[RegisterRouter.scala:87:24] wire _out_T_626 = out_f_woready_52; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecdata = {4'h0, _out_T_622}; // @[RegisterRouter.scala:87:24] wire _out_T_627 = ~out_rimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_628 = ~out_wimask_52; // @[RegisterRouter.scala:87:24] wire _out_T_629 = ~out_romask_52; // @[RegisterRouter.scala:87:24] wire _out_T_630 = ~out_womask_52; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_632 = _out_T_631[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_41 = _out_T_632; // @[RegisterRouter.scala:87:24] wire out_rimask_53 = |_out_rimask_T_53; // @[RegisterRouter.scala:87:24] wire out_wimask_53 = &_out_wimask_T_53; // @[RegisterRouter.scala:87:24] wire out_romask_53 = |_out_romask_T_53; // @[RegisterRouter.scala:87:24] wire out_womask_53 = &_out_womask_T_53; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_53 = out_rivalid_53 & out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_634 = out_f_rivalid_53; // @[RegisterRouter.scala:87:24] wire out_f_roready_53 = out_roready_53 & out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_635 = out_f_roready_53; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_53 = out_wivalid_53 & out_wimask_53; // @[RegisterRouter.scala:87:24] wire out_f_woready_53 = out_woready_53 & out_womask_53; // @[RegisterRouter.scala:87:24] wire _out_T_636 = ~out_rimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_637 = ~out_wimask_53; // @[RegisterRouter.scala:87:24] wire _out_T_638 = ~out_romask_53; // @[RegisterRouter.scala:87:24] wire _out_T_639 = ~out_womask_53; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_41 = {1'h0, _out_prepend_T_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_640 = {7'h0, out_prepend_41}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_641 = _out_T_640; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_42 = _out_T_641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_54 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_54 = |_out_rimask_T_54; // @[RegisterRouter.scala:87:24] wire out_wimask_54 = &_out_wimask_T_54; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_54 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24] wire out_romask_54 = |_out_romask_T_54; // @[RegisterRouter.scala:87:24] wire out_womask_54 = &_out_womask_T_54; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_54 = out_rivalid_54 & out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_643 = out_f_rivalid_54; // @[RegisterRouter.scala:87:24] wire out_f_roready_54 = out_roready_54 & out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_644 = out_f_roready_54; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_54 = out_wivalid_54 & out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_645 = out_f_wivalid_54; // @[RegisterRouter.scala:87:24] assign out_f_woready_54 = out_woready_54 & out_womask_54; // @[RegisterRouter.scala:87:24] assign autoexecprogbufWrEnMaybe = out_f_woready_54; // @[RegisterRouter.scala:87:24] wire _out_T_646 = out_f_woready_54; // @[RegisterRouter.scala:87:24] assign _out_T_642 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24] assign ABSTRACTAUTOWrData_autoexecprogbuf = _out_T_642; // @[RegisterRouter.scala:87:24] wire _out_T_647 = ~out_rimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_648 = ~out_wimask_54; // @[RegisterRouter.scala:87:24] wire _out_T_649 = ~out_romask_54; // @[RegisterRouter.scala:87:24] wire _out_T_650 = ~out_womask_54; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_42 = {ABSTRACTAUTORdData_autoexecprogbuf, _out_prepend_T_42}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_651 = out_prepend_42; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_652 = _out_T_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_24 = _out_T_652; // @[MuxLiteral.scala:49:48] wire out_rimask_55 = |_out_rimask_T_55; // @[RegisterRouter.scala:87:24] wire out_wimask_55 = &_out_wimask_T_55; // @[RegisterRouter.scala:87:24] wire out_romask_55 = |_out_romask_T_55; // @[RegisterRouter.scala:87:24] wire out_womask_55 = &_out_womask_T_55; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_55 = out_rivalid_55 & out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_654 = out_f_rivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_roready_55 = out_roready_55 & out_romask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_20 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire _out_T_655 = out_f_roready_55; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_55 = out_wivalid_55 & out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_656 = out_f_wivalid_55; // @[RegisterRouter.scala:87:24] assign out_f_woready_55 = out_woready_55 & out_womask_55; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_20 = out_f_woready_55; // @[RegisterRouter.scala:87:24] wire _out_T_657 = out_f_woready_55; // @[RegisterRouter.scala:87:24] assign programBufferNxt_20 = out_f_woready_55 ? _out_T_653 : programBufferMem_20; // @[RegisterRouter.scala:87:24] wire _out_T_658 = ~out_rimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_659 = ~out_wimask_55; // @[RegisterRouter.scala:87:24] wire _out_T_660 = ~out_romask_55; // @[RegisterRouter.scala:87:24] wire _out_T_661 = ~out_womask_55; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_663 = _out_T_662; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_43 = _out_T_663; // @[RegisterRouter.scala:87:24] wire out_rimask_56 = |_out_rimask_T_56; // @[RegisterRouter.scala:87:24] wire out_wimask_56 = &_out_wimask_T_56; // @[RegisterRouter.scala:87:24] wire out_romask_56 = |_out_romask_T_56; // @[RegisterRouter.scala:87:24] wire out_womask_56 = &_out_womask_T_56; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_56 = out_rivalid_56 & out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_665 = out_f_rivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_roready_56 = out_roready_56 & out_romask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_21 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire _out_T_666 = out_f_roready_56; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_56 = out_wivalid_56 & out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_667 = out_f_wivalid_56; // @[RegisterRouter.scala:87:24] assign out_f_woready_56 = out_woready_56 & out_womask_56; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_21 = out_f_woready_56; // @[RegisterRouter.scala:87:24] wire _out_T_668 = out_f_woready_56; // @[RegisterRouter.scala:87:24] assign programBufferNxt_21 = out_f_woready_56 ? _out_T_664 : programBufferMem_21; // @[RegisterRouter.scala:87:24] wire _out_T_669 = ~out_rimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_670 = ~out_wimask_56; // @[RegisterRouter.scala:87:24] wire _out_T_671 = ~out_romask_56; // @[RegisterRouter.scala:87:24] wire _out_T_672 = ~out_womask_56; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_43 = {programBufferMem_21, _out_prepend_T_43}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_673 = out_prepend_43; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_674 = _out_T_673; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_44 = _out_T_674; // @[RegisterRouter.scala:87:24] wire out_rimask_57 = |_out_rimask_T_57; // @[RegisterRouter.scala:87:24] wire out_wimask_57 = &_out_wimask_T_57; // @[RegisterRouter.scala:87:24] wire out_romask_57 = |_out_romask_T_57; // @[RegisterRouter.scala:87:24] wire out_womask_57 = &_out_womask_T_57; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_57 = out_rivalid_57 & out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_676 = out_f_rivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_roready_57 = out_roready_57 & out_romask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_22 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire _out_T_677 = out_f_roready_57; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_57 = out_wivalid_57 & out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_678 = out_f_wivalid_57; // @[RegisterRouter.scala:87:24] assign out_f_woready_57 = out_woready_57 & out_womask_57; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_22 = out_f_woready_57; // @[RegisterRouter.scala:87:24] wire _out_T_679 = out_f_woready_57; // @[RegisterRouter.scala:87:24] assign programBufferNxt_22 = out_f_woready_57 ? _out_T_675 : programBufferMem_22; // @[RegisterRouter.scala:87:24] wire _out_T_680 = ~out_rimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_681 = ~out_wimask_57; // @[RegisterRouter.scala:87:24] wire _out_T_682 = ~out_romask_57; // @[RegisterRouter.scala:87:24] wire _out_T_683 = ~out_womask_57; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_44 = {programBufferMem_22, _out_prepend_T_44}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_684 = out_prepend_44; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_685 = _out_T_684; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_45 = _out_T_685; // @[RegisterRouter.scala:87:24] wire out_rimask_58 = |_out_rimask_T_58; // @[RegisterRouter.scala:87:24] wire out_wimask_58 = &_out_wimask_T_58; // @[RegisterRouter.scala:87:24] wire out_romask_58 = |_out_romask_T_58; // @[RegisterRouter.scala:87:24] wire out_womask_58 = &_out_womask_T_58; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_58 = out_rivalid_58 & out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_687 = out_f_rivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_roready_58 = out_roready_58 & out_romask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_23 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire _out_T_688 = out_f_roready_58; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_58 = out_wivalid_58 & out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_689 = out_f_wivalid_58; // @[RegisterRouter.scala:87:24] assign out_f_woready_58 = out_woready_58 & out_womask_58; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_23 = out_f_woready_58; // @[RegisterRouter.scala:87:24] wire _out_T_690 = out_f_woready_58; // @[RegisterRouter.scala:87:24] assign programBufferNxt_23 = out_f_woready_58 ? _out_T_686 : programBufferMem_23; // @[RegisterRouter.scala:87:24] wire _out_T_691 = ~out_rimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_692 = ~out_wimask_58; // @[RegisterRouter.scala:87:24] wire _out_T_693 = ~out_romask_58; // @[RegisterRouter.scala:87:24] wire _out_T_694 = ~out_womask_58; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_45 = {programBufferMem_23, _out_prepend_T_45}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_695 = out_prepend_45; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_696 = _out_T_695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_37 = _out_T_696; // @[MuxLiteral.scala:49:48] wire out_rimask_59 = |_out_rimask_T_59; // @[RegisterRouter.scala:87:24] wire out_wimask_59 = &_out_wimask_T_59; // @[RegisterRouter.scala:87:24] wire out_romask_59 = |_out_romask_T_59; // @[RegisterRouter.scala:87:24] wire out_womask_59 = &_out_womask_T_59; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_59 = out_rivalid_59 & out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_698 = out_f_rivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_roready_59 = out_roready_59 & out_romask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_56 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire _out_T_699 = out_f_roready_59; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_59 = out_wivalid_59 & out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_700 = out_f_wivalid_59; // @[RegisterRouter.scala:87:24] assign out_f_woready_59 = out_woready_59 & out_womask_59; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_56 = out_f_woready_59; // @[RegisterRouter.scala:87:24] wire _out_T_701 = out_f_woready_59; // @[RegisterRouter.scala:87:24] assign programBufferNxt_56 = out_f_woready_59 ? _out_T_697 : programBufferMem_56; // @[RegisterRouter.scala:87:24] wire _out_T_702 = ~out_rimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_703 = ~out_wimask_59; // @[RegisterRouter.scala:87:24] wire _out_T_704 = ~out_romask_59; // @[RegisterRouter.scala:87:24] wire _out_T_705 = ~out_womask_59; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_707 = _out_T_706; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_46 = _out_T_707; // @[RegisterRouter.scala:87:24] wire out_rimask_60 = |_out_rimask_T_60; // @[RegisterRouter.scala:87:24] wire out_wimask_60 = &_out_wimask_T_60; // @[RegisterRouter.scala:87:24] wire out_romask_60 = |_out_romask_T_60; // @[RegisterRouter.scala:87:24] wire out_womask_60 = &_out_womask_T_60; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_60 = out_rivalid_60 & out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_709 = out_f_rivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_roready_60 = out_roready_60 & out_romask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_57 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire _out_T_710 = out_f_roready_60; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_60 = out_wivalid_60 & out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_711 = out_f_wivalid_60; // @[RegisterRouter.scala:87:24] assign out_f_woready_60 = out_woready_60 & out_womask_60; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_57 = out_f_woready_60; // @[RegisterRouter.scala:87:24] wire _out_T_712 = out_f_woready_60; // @[RegisterRouter.scala:87:24] assign programBufferNxt_57 = out_f_woready_60 ? _out_T_708 : programBufferMem_57; // @[RegisterRouter.scala:87:24] wire _out_T_713 = ~out_rimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_714 = ~out_wimask_60; // @[RegisterRouter.scala:87:24] wire _out_T_715 = ~out_romask_60; // @[RegisterRouter.scala:87:24] wire _out_T_716 = ~out_womask_60; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_46 = {programBufferMem_57, _out_prepend_T_46}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_717 = out_prepend_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_718 = _out_T_717; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_47 = _out_T_718; // @[RegisterRouter.scala:87:24] wire out_rimask_61 = |_out_rimask_T_61; // @[RegisterRouter.scala:87:24] wire out_wimask_61 = &_out_wimask_T_61; // @[RegisterRouter.scala:87:24] wire out_romask_61 = |_out_romask_T_61; // @[RegisterRouter.scala:87:24] wire out_womask_61 = &_out_womask_T_61; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_61 = out_rivalid_61 & out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_720 = out_f_rivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_roready_61 = out_roready_61 & out_romask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_58 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire _out_T_721 = out_f_roready_61; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_61 = out_wivalid_61 & out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_722 = out_f_wivalid_61; // @[RegisterRouter.scala:87:24] assign out_f_woready_61 = out_woready_61 & out_womask_61; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_58 = out_f_woready_61; // @[RegisterRouter.scala:87:24] wire _out_T_723 = out_f_woready_61; // @[RegisterRouter.scala:87:24] assign programBufferNxt_58 = out_f_woready_61 ? _out_T_719 : programBufferMem_58; // @[RegisterRouter.scala:87:24] wire _out_T_724 = ~out_rimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_725 = ~out_wimask_61; // @[RegisterRouter.scala:87:24] wire _out_T_726 = ~out_romask_61; // @[RegisterRouter.scala:87:24] wire _out_T_727 = ~out_womask_61; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_47 = {programBufferMem_58, _out_prepend_T_47}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_728 = out_prepend_47; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_729 = _out_T_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_48 = _out_T_729; // @[RegisterRouter.scala:87:24] wire out_rimask_62 = |_out_rimask_T_62; // @[RegisterRouter.scala:87:24] wire out_wimask_62 = &_out_wimask_T_62; // @[RegisterRouter.scala:87:24] wire out_romask_62 = |_out_romask_T_62; // @[RegisterRouter.scala:87:24] wire out_womask_62 = &_out_womask_T_62; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_62 = out_rivalid_62 & out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_731 = out_f_rivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_roready_62 = out_roready_62 & out_romask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_59 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire _out_T_732 = out_f_roready_62; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_62 = out_wivalid_62 & out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_733 = out_f_wivalid_62; // @[RegisterRouter.scala:87:24] assign out_f_woready_62 = out_woready_62 & out_womask_62; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_59 = out_f_woready_62; // @[RegisterRouter.scala:87:24] wire _out_T_734 = out_f_woready_62; // @[RegisterRouter.scala:87:24] assign programBufferNxt_59 = out_f_woready_62 ? _out_T_730 : programBufferMem_59; // @[RegisterRouter.scala:87:24] wire _out_T_735 = ~out_rimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_736 = ~out_wimask_62; // @[RegisterRouter.scala:87:24] wire _out_T_737 = ~out_romask_62; // @[RegisterRouter.scala:87:24] wire _out_T_738 = ~out_womask_62; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_48 = {programBufferMem_59, _out_prepend_T_48}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_739 = out_prepend_48; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_740 = _out_T_739; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_46 = _out_T_740; // @[MuxLiteral.scala:49:48] wire out_rimask_63 = |_out_rimask_T_63; // @[RegisterRouter.scala:87:24] wire out_wimask_63 = &_out_wimask_T_63; // @[RegisterRouter.scala:87:24] wire out_romask_63 = |_out_romask_T_63; // @[RegisterRouter.scala:87:24] wire out_womask_63 = &_out_womask_T_63; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_63 = out_rivalid_63 & out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_742 = out_f_rivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_roready_63 = out_roready_63 & out_romask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSRdEn_0 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire _out_T_743 = out_f_roready_63; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_63 = out_wivalid_63 & out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_744 = out_f_wivalid_63; // @[RegisterRouter.scala:87:24] assign out_f_woready_63 = out_woready_63 & out_womask_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrEn_0 = out_f_woready_63; // @[RegisterRouter.scala:87:24] wire _out_T_745 = out_f_woready_63; // @[RegisterRouter.scala:87:24] assign SBADDRESSWrData_0 = out_f_woready_63 ? _out_T_741 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_746 = ~out_rimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_747 = ~out_wimask_63; // @[RegisterRouter.scala:87:24] wire _out_T_748 = ~out_romask_63; // @[RegisterRouter.scala:87:24] wire _out_T_749 = ~out_womask_63; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_751 = _out_T_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_57 = _out_T_751; // @[MuxLiteral.scala:49:48] wire out_rimask_64 = |_out_rimask_T_64; // @[RegisterRouter.scala:87:24] wire out_wimask_64 = &_out_wimask_T_64; // @[RegisterRouter.scala:87:24] wire out_romask_64 = |_out_romask_T_64; // @[RegisterRouter.scala:87:24] wire out_womask_64 = &_out_womask_T_64; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_64 = out_rivalid_64 & out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_753 = out_f_rivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_roready_64 = out_roready_64 & out_romask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_8 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire _out_T_754 = out_f_roready_64; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_64 = out_wivalid_64 & out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_755 = out_f_wivalid_64; // @[RegisterRouter.scala:87:24] assign out_f_woready_64 = out_woready_64 & out_womask_64; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_8 = out_f_woready_64; // @[RegisterRouter.scala:87:24] wire _out_T_756 = out_f_woready_64; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_8 = out_f_woready_64 ? _out_T_752 : abstractDataMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_757 = ~out_rimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_758 = ~out_wimask_64; // @[RegisterRouter.scala:87:24] wire _out_T_759 = ~out_romask_64; // @[RegisterRouter.scala:87:24] wire _out_T_760 = ~out_womask_64; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_762 = _out_T_761; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_49 = _out_T_762; // @[RegisterRouter.scala:87:24] wire out_rimask_65 = |_out_rimask_T_65; // @[RegisterRouter.scala:87:24] wire out_wimask_65 = &_out_wimask_T_65; // @[RegisterRouter.scala:87:24] wire out_romask_65 = |_out_romask_T_65; // @[RegisterRouter.scala:87:24] wire out_womask_65 = &_out_womask_T_65; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_65 = out_rivalid_65 & out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_764 = out_f_rivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_roready_65 = out_roready_65 & out_romask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_9 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire _out_T_765 = out_f_roready_65; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_65 = out_wivalid_65 & out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_766 = out_f_wivalid_65; // @[RegisterRouter.scala:87:24] assign out_f_woready_65 = out_woready_65 & out_womask_65; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_9 = out_f_woready_65; // @[RegisterRouter.scala:87:24] wire _out_T_767 = out_f_woready_65; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_9 = out_f_woready_65 ? _out_T_763 : abstractDataMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_768 = ~out_rimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_769 = ~out_wimask_65; // @[RegisterRouter.scala:87:24] wire _out_T_770 = ~out_romask_65; // @[RegisterRouter.scala:87:24] wire _out_T_771 = ~out_womask_65; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_49 = {abstractDataMem_9, _out_prepend_T_49}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_772 = out_prepend_49; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_773 = _out_T_772; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_50 = _out_T_773; // @[RegisterRouter.scala:87:24] wire out_rimask_66 = |_out_rimask_T_66; // @[RegisterRouter.scala:87:24] wire out_wimask_66 = &_out_wimask_T_66; // @[RegisterRouter.scala:87:24] wire out_romask_66 = |_out_romask_T_66; // @[RegisterRouter.scala:87:24] wire out_womask_66 = &_out_womask_T_66; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_66 = out_rivalid_66 & out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_775 = out_f_rivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_roready_66 = out_roready_66 & out_romask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_10 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire _out_T_776 = out_f_roready_66; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_66 = out_wivalid_66 & out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_777 = out_f_wivalid_66; // @[RegisterRouter.scala:87:24] assign out_f_woready_66 = out_woready_66 & out_womask_66; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_10 = out_f_woready_66; // @[RegisterRouter.scala:87:24] wire _out_T_778 = out_f_woready_66; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_10 = out_f_woready_66 ? _out_T_774 : abstractDataMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_779 = ~out_rimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_780 = ~out_wimask_66; // @[RegisterRouter.scala:87:24] wire _out_T_781 = ~out_romask_66; // @[RegisterRouter.scala:87:24] wire _out_T_782 = ~out_womask_66; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_50 = {abstractDataMem_10, _out_prepend_T_50}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_783 = out_prepend_50; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_784 = _out_T_783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_51 = _out_T_784; // @[RegisterRouter.scala:87:24] wire out_rimask_67 = |_out_rimask_T_67; // @[RegisterRouter.scala:87:24] wire out_wimask_67 = &_out_wimask_T_67; // @[RegisterRouter.scala:87:24] wire out_romask_67 = |_out_romask_T_67; // @[RegisterRouter.scala:87:24] wire out_womask_67 = &_out_womask_T_67; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_67 = out_rivalid_67 & out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_786 = out_f_rivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_roready_67 = out_roready_67 & out_romask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_11 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire _out_T_787 = out_f_roready_67; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_67 = out_wivalid_67 & out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_788 = out_f_wivalid_67; // @[RegisterRouter.scala:87:24] assign out_f_woready_67 = out_woready_67 & out_womask_67; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_11 = out_f_woready_67; // @[RegisterRouter.scala:87:24] wire _out_T_789 = out_f_woready_67; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_11 = out_f_woready_67 ? _out_T_785 : abstractDataMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_790 = ~out_rimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_791 = ~out_wimask_67; // @[RegisterRouter.scala:87:24] wire _out_T_792 = ~out_romask_67; // @[RegisterRouter.scala:87:24] wire _out_T_793 = ~out_womask_67; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_51 = {abstractDataMem_11, _out_prepend_T_51}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_794 = out_prepend_51; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_795 = _out_T_794; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_6 = _out_T_795; // @[MuxLiteral.scala:49:48] wire out_rimask_68 = |_out_rimask_T_68; // @[RegisterRouter.scala:87:24] wire out_wimask_68 = &_out_wimask_T_68; // @[RegisterRouter.scala:87:24] wire out_romask_68 = |_out_romask_T_68; // @[RegisterRouter.scala:87:24] wire out_womask_68 = &_out_womask_T_68; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_68 = out_rivalid_68 & out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_797 = out_f_rivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_roready_68 = out_roready_68 & out_romask_68; // @[RegisterRouter.scala:87:24] assign SBDATARdEn_0 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire _out_T_798 = out_f_roready_68; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_68 = out_wivalid_68 & out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_799 = out_f_wivalid_68; // @[RegisterRouter.scala:87:24] assign out_f_woready_68 = out_woready_68 & out_womask_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrEn_0 = out_f_woready_68; // @[RegisterRouter.scala:87:24] wire _out_T_800 = out_f_woready_68; // @[RegisterRouter.scala:87:24] assign SBDATAWrData_0 = out_f_woready_68 ? _out_T_796 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_801 = ~out_rimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_802 = ~out_wimask_68; // @[RegisterRouter.scala:87:24] wire _out_T_803 = ~out_romask_68; // @[RegisterRouter.scala:87:24] wire _out_T_804 = ~out_womask_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_806 = _out_T_805; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_60 = _out_T_806; // @[MuxLiteral.scala:49:48] wire out_rimask_69 = |_out_rimask_T_69; // @[RegisterRouter.scala:87:24] wire out_wimask_69 = &_out_wimask_T_69; // @[RegisterRouter.scala:87:24] wire out_romask_69 = |_out_romask_T_69; // @[RegisterRouter.scala:87:24] wire out_womask_69 = &_out_womask_T_69; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_69 = out_rivalid_69 & out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_808 = out_f_rivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_roready_69 = out_roready_69 & out_romask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_24 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire _out_T_809 = out_f_roready_69; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_69 = out_wivalid_69 & out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_810 = out_f_wivalid_69; // @[RegisterRouter.scala:87:24] assign out_f_woready_69 = out_woready_69 & out_womask_69; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_24 = out_f_woready_69; // @[RegisterRouter.scala:87:24] wire _out_T_811 = out_f_woready_69; // @[RegisterRouter.scala:87:24] assign programBufferNxt_24 = out_f_woready_69 ? _out_T_807 : programBufferMem_24; // @[RegisterRouter.scala:87:24] wire _out_T_812 = ~out_rimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_813 = ~out_wimask_69; // @[RegisterRouter.scala:87:24] wire _out_T_814 = ~out_romask_69; // @[RegisterRouter.scala:87:24] wire _out_T_815 = ~out_womask_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_817 = _out_T_816; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_52 = _out_T_817; // @[RegisterRouter.scala:87:24] wire out_rimask_70 = |_out_rimask_T_70; // @[RegisterRouter.scala:87:24] wire out_wimask_70 = &_out_wimask_T_70; // @[RegisterRouter.scala:87:24] wire out_romask_70 = |_out_romask_T_70; // @[RegisterRouter.scala:87:24] wire out_womask_70 = &_out_womask_T_70; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_70 = out_rivalid_70 & out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_819 = out_f_rivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_roready_70 = out_roready_70 & out_romask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_25 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire _out_T_820 = out_f_roready_70; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_70 = out_wivalid_70 & out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_821 = out_f_wivalid_70; // @[RegisterRouter.scala:87:24] assign out_f_woready_70 = out_woready_70 & out_womask_70; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_25 = out_f_woready_70; // @[RegisterRouter.scala:87:24] wire _out_T_822 = out_f_woready_70; // @[RegisterRouter.scala:87:24] assign programBufferNxt_25 = out_f_woready_70 ? _out_T_818 : programBufferMem_25; // @[RegisterRouter.scala:87:24] wire _out_T_823 = ~out_rimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_824 = ~out_wimask_70; // @[RegisterRouter.scala:87:24] wire _out_T_825 = ~out_romask_70; // @[RegisterRouter.scala:87:24] wire _out_T_826 = ~out_womask_70; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_52 = {programBufferMem_25, _out_prepend_T_52}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_827 = out_prepend_52; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_828 = _out_T_827; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_53 = _out_T_828; // @[RegisterRouter.scala:87:24] wire out_rimask_71 = |_out_rimask_T_71; // @[RegisterRouter.scala:87:24] wire out_wimask_71 = &_out_wimask_T_71; // @[RegisterRouter.scala:87:24] wire out_romask_71 = |_out_romask_T_71; // @[RegisterRouter.scala:87:24] wire out_womask_71 = &_out_womask_T_71; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_71 = out_rivalid_71 & out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_830 = out_f_rivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_roready_71 = out_roready_71 & out_romask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_26 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire _out_T_831 = out_f_roready_71; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_71 = out_wivalid_71 & out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_832 = out_f_wivalid_71; // @[RegisterRouter.scala:87:24] assign out_f_woready_71 = out_woready_71 & out_womask_71; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_26 = out_f_woready_71; // @[RegisterRouter.scala:87:24] wire _out_T_833 = out_f_woready_71; // @[RegisterRouter.scala:87:24] assign programBufferNxt_26 = out_f_woready_71 ? _out_T_829 : programBufferMem_26; // @[RegisterRouter.scala:87:24] wire _out_T_834 = ~out_rimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_835 = ~out_wimask_71; // @[RegisterRouter.scala:87:24] wire _out_T_836 = ~out_romask_71; // @[RegisterRouter.scala:87:24] wire _out_T_837 = ~out_womask_71; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_53 = {programBufferMem_26, _out_prepend_T_53}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_838 = out_prepend_53; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_839 = _out_T_838; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_54 = _out_T_839; // @[RegisterRouter.scala:87:24] wire out_rimask_72 = |_out_rimask_T_72; // @[RegisterRouter.scala:87:24] wire out_wimask_72 = &_out_wimask_T_72; // @[RegisterRouter.scala:87:24] wire out_romask_72 = |_out_romask_T_72; // @[RegisterRouter.scala:87:24] wire out_womask_72 = &_out_womask_T_72; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_72 = out_rivalid_72 & out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_841 = out_f_rivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_roready_72 = out_roready_72 & out_romask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_27 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire _out_T_842 = out_f_roready_72; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_72 = out_wivalid_72 & out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_843 = out_f_wivalid_72; // @[RegisterRouter.scala:87:24] assign out_f_woready_72 = out_woready_72 & out_womask_72; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_27 = out_f_woready_72; // @[RegisterRouter.scala:87:24] wire _out_T_844 = out_f_woready_72; // @[RegisterRouter.scala:87:24] assign programBufferNxt_27 = out_f_woready_72 ? _out_T_840 : programBufferMem_27; // @[RegisterRouter.scala:87:24] wire _out_T_845 = ~out_rimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_846 = ~out_wimask_72; // @[RegisterRouter.scala:87:24] wire _out_T_847 = ~out_romask_72; // @[RegisterRouter.scala:87:24] wire _out_T_848 = ~out_womask_72; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_54 = {programBufferMem_27, _out_prepend_T_54}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_849 = out_prepend_54; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_850 = _out_T_849; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_38 = _out_T_850; // @[MuxLiteral.scala:49:48] wire out_rimask_73 = |_out_rimask_T_73; // @[RegisterRouter.scala:87:24] wire out_wimask_73 = &_out_wimask_T_73; // @[RegisterRouter.scala:87:24] wire out_romask_73 = |_out_romask_T_73; // @[RegisterRouter.scala:87:24] wire out_womask_73 = &_out_womask_T_73; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_73 = out_rivalid_73 & out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_852 = out_f_rivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_roready_73 = out_roready_73 & out_romask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_4 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire _out_T_853 = out_f_roready_73; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_73 = out_wivalid_73 & out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_854 = out_f_wivalid_73; // @[RegisterRouter.scala:87:24] assign out_f_woready_73 = out_woready_73 & out_womask_73; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_4 = out_f_woready_73; // @[RegisterRouter.scala:87:24] wire _out_T_855 = out_f_woready_73; // @[RegisterRouter.scala:87:24] assign programBufferNxt_4 = out_f_woready_73 ? _out_T_851 : programBufferMem_4; // @[RegisterRouter.scala:87:24] wire _out_T_856 = ~out_rimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_857 = ~out_wimask_73; // @[RegisterRouter.scala:87:24] wire _out_T_858 = ~out_romask_73; // @[RegisterRouter.scala:87:24] wire _out_T_859 = ~out_womask_73; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_861 = _out_T_860; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_55 = _out_T_861; // @[RegisterRouter.scala:87:24] wire out_rimask_74 = |_out_rimask_T_74; // @[RegisterRouter.scala:87:24] wire out_wimask_74 = &_out_wimask_T_74; // @[RegisterRouter.scala:87:24] wire out_romask_74 = |_out_romask_T_74; // @[RegisterRouter.scala:87:24] wire out_womask_74 = &_out_womask_T_74; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_74 = out_rivalid_74 & out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_863 = out_f_rivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_roready_74 = out_roready_74 & out_romask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_5 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire _out_T_864 = out_f_roready_74; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_74 = out_wivalid_74 & out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_865 = out_f_wivalid_74; // @[RegisterRouter.scala:87:24] assign out_f_woready_74 = out_woready_74 & out_womask_74; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_5 = out_f_woready_74; // @[RegisterRouter.scala:87:24] wire _out_T_866 = out_f_woready_74; // @[RegisterRouter.scala:87:24] assign programBufferNxt_5 = out_f_woready_74 ? _out_T_862 : programBufferMem_5; // @[RegisterRouter.scala:87:24] wire _out_T_867 = ~out_rimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_868 = ~out_wimask_74; // @[RegisterRouter.scala:87:24] wire _out_T_869 = ~out_romask_74; // @[RegisterRouter.scala:87:24] wire _out_T_870 = ~out_womask_74; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_55 = {programBufferMem_5, _out_prepend_T_55}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_871 = out_prepend_55; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_872 = _out_T_871; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_56 = _out_T_872; // @[RegisterRouter.scala:87:24] wire out_rimask_75 = |_out_rimask_T_75; // @[RegisterRouter.scala:87:24] wire out_wimask_75 = &_out_wimask_T_75; // @[RegisterRouter.scala:87:24] wire out_romask_75 = |_out_romask_T_75; // @[RegisterRouter.scala:87:24] wire out_womask_75 = &_out_womask_T_75; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_75 = out_rivalid_75 & out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_874 = out_f_rivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_roready_75 = out_roready_75 & out_romask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_6 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire _out_T_875 = out_f_roready_75; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_75 = out_wivalid_75 & out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_876 = out_f_wivalid_75; // @[RegisterRouter.scala:87:24] assign out_f_woready_75 = out_woready_75 & out_womask_75; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_6 = out_f_woready_75; // @[RegisterRouter.scala:87:24] wire _out_T_877 = out_f_woready_75; // @[RegisterRouter.scala:87:24] assign programBufferNxt_6 = out_f_woready_75 ? _out_T_873 : programBufferMem_6; // @[RegisterRouter.scala:87:24] wire _out_T_878 = ~out_rimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_879 = ~out_wimask_75; // @[RegisterRouter.scala:87:24] wire _out_T_880 = ~out_romask_75; // @[RegisterRouter.scala:87:24] wire _out_T_881 = ~out_womask_75; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_56 = {programBufferMem_6, _out_prepend_T_56}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_882 = out_prepend_56; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_883 = _out_T_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_57 = _out_T_883; // @[RegisterRouter.scala:87:24] wire out_rimask_76 = |_out_rimask_T_76; // @[RegisterRouter.scala:87:24] wire out_wimask_76 = &_out_wimask_T_76; // @[RegisterRouter.scala:87:24] wire out_romask_76 = |_out_romask_T_76; // @[RegisterRouter.scala:87:24] wire out_womask_76 = &_out_womask_T_76; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_76 = out_rivalid_76 & out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_885 = out_f_rivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_roready_76 = out_roready_76 & out_romask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_7 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire _out_T_886 = out_f_roready_76; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_76 = out_wivalid_76 & out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_887 = out_f_wivalid_76; // @[RegisterRouter.scala:87:24] assign out_f_woready_76 = out_woready_76 & out_womask_76; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_7 = out_f_woready_76; // @[RegisterRouter.scala:87:24] wire _out_T_888 = out_f_woready_76; // @[RegisterRouter.scala:87:24] assign programBufferNxt_7 = out_f_woready_76 ? _out_T_884 : programBufferMem_7; // @[RegisterRouter.scala:87:24] wire _out_T_889 = ~out_rimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_890 = ~out_wimask_76; // @[RegisterRouter.scala:87:24] wire _out_T_891 = ~out_romask_76; // @[RegisterRouter.scala:87:24] wire _out_T_892 = ~out_womask_76; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_57 = {programBufferMem_7, _out_prepend_T_57}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_893 = out_prepend_57; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_894 = _out_T_893; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_33 = _out_T_894; // @[MuxLiteral.scala:49:48] wire out_rimask_77 = |_out_rimask_T_77; // @[RegisterRouter.scala:87:24] wire out_wimask_77 = &_out_wimask_T_77; // @[RegisterRouter.scala:87:24] wire out_romask_77 = |_out_romask_T_77; // @[RegisterRouter.scala:87:24] wire out_womask_77 = &_out_womask_T_77; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_77 = out_rivalid_77 & out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_896 = out_f_rivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_roready_77 = out_roready_77 & out_romask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_52 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire _out_T_897 = out_f_roready_77; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_77 = out_wivalid_77 & out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_898 = out_f_wivalid_77; // @[RegisterRouter.scala:87:24] assign out_f_woready_77 = out_woready_77 & out_womask_77; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_52 = out_f_woready_77; // @[RegisterRouter.scala:87:24] wire _out_T_899 = out_f_woready_77; // @[RegisterRouter.scala:87:24] assign programBufferNxt_52 = out_f_woready_77 ? _out_T_895 : programBufferMem_52; // @[RegisterRouter.scala:87:24] wire _out_T_900 = ~out_rimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_901 = ~out_wimask_77; // @[RegisterRouter.scala:87:24] wire _out_T_902 = ~out_romask_77; // @[RegisterRouter.scala:87:24] wire _out_T_903 = ~out_womask_77; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_905 = _out_T_904; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_58 = _out_T_905; // @[RegisterRouter.scala:87:24] wire out_rimask_78 = |_out_rimask_T_78; // @[RegisterRouter.scala:87:24] wire out_wimask_78 = &_out_wimask_T_78; // @[RegisterRouter.scala:87:24] wire out_romask_78 = |_out_romask_T_78; // @[RegisterRouter.scala:87:24] wire out_womask_78 = &_out_womask_T_78; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_78 = out_rivalid_78 & out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_907 = out_f_rivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_roready_78 = out_roready_78 & out_romask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_53 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire _out_T_908 = out_f_roready_78; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_78 = out_wivalid_78 & out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_909 = out_f_wivalid_78; // @[RegisterRouter.scala:87:24] assign out_f_woready_78 = out_woready_78 & out_womask_78; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_53 = out_f_woready_78; // @[RegisterRouter.scala:87:24] wire _out_T_910 = out_f_woready_78; // @[RegisterRouter.scala:87:24] assign programBufferNxt_53 = out_f_woready_78 ? _out_T_906 : programBufferMem_53; // @[RegisterRouter.scala:87:24] wire _out_T_911 = ~out_rimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_912 = ~out_wimask_78; // @[RegisterRouter.scala:87:24] wire _out_T_913 = ~out_romask_78; // @[RegisterRouter.scala:87:24] wire _out_T_914 = ~out_womask_78; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_58 = {programBufferMem_53, _out_prepend_T_58}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_915 = out_prepend_58; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_916 = _out_T_915; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_59 = _out_T_916; // @[RegisterRouter.scala:87:24] wire out_rimask_79 = |_out_rimask_T_79; // @[RegisterRouter.scala:87:24] wire out_wimask_79 = &_out_wimask_T_79; // @[RegisterRouter.scala:87:24] wire out_romask_79 = |_out_romask_T_79; // @[RegisterRouter.scala:87:24] wire out_womask_79 = &_out_womask_T_79; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_79 = out_rivalid_79 & out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_918 = out_f_rivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_roready_79 = out_roready_79 & out_romask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_54 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire _out_T_919 = out_f_roready_79; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_79 = out_wivalid_79 & out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_920 = out_f_wivalid_79; // @[RegisterRouter.scala:87:24] assign out_f_woready_79 = out_woready_79 & out_womask_79; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_54 = out_f_woready_79; // @[RegisterRouter.scala:87:24] wire _out_T_921 = out_f_woready_79; // @[RegisterRouter.scala:87:24] assign programBufferNxt_54 = out_f_woready_79 ? _out_T_917 : programBufferMem_54; // @[RegisterRouter.scala:87:24] wire _out_T_922 = ~out_rimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_923 = ~out_wimask_79; // @[RegisterRouter.scala:87:24] wire _out_T_924 = ~out_romask_79; // @[RegisterRouter.scala:87:24] wire _out_T_925 = ~out_womask_79; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_59 = {programBufferMem_54, _out_prepend_T_59}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_926 = out_prepend_59; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_927 = _out_T_926; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_60 = _out_T_927; // @[RegisterRouter.scala:87:24] wire out_rimask_80 = |_out_rimask_T_80; // @[RegisterRouter.scala:87:24] wire out_wimask_80 = &_out_wimask_T_80; // @[RegisterRouter.scala:87:24] wire out_romask_80 = |_out_romask_T_80; // @[RegisterRouter.scala:87:24] wire out_womask_80 = &_out_womask_T_80; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_80 = out_rivalid_80 & out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_929 = out_f_rivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_roready_80 = out_roready_80 & out_romask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_55 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire _out_T_930 = out_f_roready_80; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_80 = out_wivalid_80 & out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_931 = out_f_wivalid_80; // @[RegisterRouter.scala:87:24] assign out_f_woready_80 = out_woready_80 & out_womask_80; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_55 = out_f_woready_80; // @[RegisterRouter.scala:87:24] wire _out_T_932 = out_f_woready_80; // @[RegisterRouter.scala:87:24] assign programBufferNxt_55 = out_f_woready_80 ? _out_T_928 : programBufferMem_55; // @[RegisterRouter.scala:87:24] wire _out_T_933 = ~out_rimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_934 = ~out_wimask_80; // @[RegisterRouter.scala:87:24] wire _out_T_935 = ~out_romask_80; // @[RegisterRouter.scala:87:24] wire _out_T_936 = ~out_womask_80; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_60 = {programBufferMem_55, _out_prepend_T_60}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_937 = out_prepend_60; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_938 = _out_T_937; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_45 = _out_T_938; // @[MuxLiteral.scala:49:48] wire out_rimask_81 = |_out_rimask_T_81; // @[RegisterRouter.scala:87:24] wire out_wimask_81 = &_out_wimask_T_81; // @[RegisterRouter.scala:87:24] wire out_romask_81 = |_out_romask_T_81; // @[RegisterRouter.scala:87:24] wire out_womask_81 = &_out_womask_T_81; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_81 = out_rivalid_81 & out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_940 = out_f_rivalid_81; // @[RegisterRouter.scala:87:24] wire out_f_roready_81 = out_roready_81 & out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_941 = out_f_roready_81; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_81 = out_wivalid_81 & out_wimask_81; // @[RegisterRouter.scala:87:24] wire out_f_woready_81 = out_woready_81 & out_womask_81; // @[RegisterRouter.scala:87:24] wire _out_T_942 = ~out_rimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_943 = ~out_wimask_81; // @[RegisterRouter.scala:87:24] wire _out_T_944 = ~out_romask_81; // @[RegisterRouter.scala:87:24] wire _out_T_945 = ~out_womask_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_947 = _out_T_946; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_947; // @[MuxLiteral.scala:49:48] wire [3:0] _out_rimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_82 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_109 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_82 = |_out_rimask_T_82; // @[RegisterRouter.scala:87:24] wire out_wimask_82 = &_out_wimask_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_82 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_109 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24] wire out_romask_82 = |_out_romask_T_82; // @[RegisterRouter.scala:87:24] wire out_womask_82 = &_out_womask_T_82; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_82 = out_rivalid_82 & out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_949 = out_f_rivalid_82; // @[RegisterRouter.scala:87:24] wire out_f_roready_82 = out_roready_82 & out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_950 = out_f_roready_82; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_82 = out_wivalid_82 & out_wimask_82; // @[RegisterRouter.scala:87:24] wire out_f_woready_82 = out_woready_82 & out_womask_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_948 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1207 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24] wire _out_T_951 = ~out_rimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_952 = ~out_wimask_82; // @[RegisterRouter.scala:87:24] wire _out_T_953 = ~out_romask_82; // @[RegisterRouter.scala:87:24] wire _out_T_954 = ~out_womask_82; // @[RegisterRouter.scala:87:24] wire out_rimask_83 = _out_rimask_T_83; // @[RegisterRouter.scala:87:24] wire out_wimask_83 = _out_wimask_T_83; // @[RegisterRouter.scala:87:24] wire out_romask_83 = _out_romask_T_83; // @[RegisterRouter.scala:87:24] wire out_womask_83 = _out_womask_T_83; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_83 = out_rivalid_83 & out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_958 = out_f_rivalid_83; // @[RegisterRouter.scala:87:24] wire out_f_roready_83 = out_roready_83 & out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_959 = out_f_roready_83; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_83 = out_wivalid_83 & out_wimask_83; // @[RegisterRouter.scala:87:24] wire out_f_woready_83 = out_woready_83 & out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_T_960 = ~out_rimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_961 = ~out_wimask_83; // @[RegisterRouter.scala:87:24] wire _out_T_962 = ~out_romask_83; // @[RegisterRouter.scala:87:24] wire _out_T_963 = ~out_womask_83; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_84 = out_frontMask[5]; // @[RegisterRouter.scala:87:24] wire out_rimask_84 = _out_rimask_T_84; // @[RegisterRouter.scala:87:24] wire out_wimask_84 = _out_wimask_T_84; // @[RegisterRouter.scala:87:24] wire _out_romask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_84 = out_backMask[5]; // @[RegisterRouter.scala:87:24] wire out_romask_84 = _out_romask_T_84; // @[RegisterRouter.scala:87:24] wire out_womask_84 = _out_womask_T_84; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_84 = out_rivalid_84 & out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_967 = out_f_rivalid_84; // @[RegisterRouter.scala:87:24] wire out_f_roready_84 = out_roready_84 & out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_968 = out_f_roready_84; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_84 = out_wivalid_84 & out_wimask_84; // @[RegisterRouter.scala:87:24] wire out_f_woready_84 = out_woready_84 & out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_T_966 = out_front_bits_data[5]; // @[RegisterRouter.scala:87:24] wire _out_T_969 = ~out_rimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_970 = ~out_wimask_84; // @[RegisterRouter.scala:87:24] wire _out_T_971 = ~out_romask_84; // @[RegisterRouter.scala:87:24] wire _out_T_972 = ~out_womask_84; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_85 = out_frontMask[6]; // @[RegisterRouter.scala:87:24] wire out_rimask_85 = _out_rimask_T_85; // @[RegisterRouter.scala:87:24] wire out_wimask_85 = _out_wimask_T_85; // @[RegisterRouter.scala:87:24] wire _out_romask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_85 = out_backMask[6]; // @[RegisterRouter.scala:87:24] wire out_romask_85 = _out_romask_T_85; // @[RegisterRouter.scala:87:24] wire out_womask_85 = _out_womask_T_85; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_85 = out_rivalid_85 & out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_976 = out_f_rivalid_85; // @[RegisterRouter.scala:87:24] wire out_f_roready_85 = out_roready_85 & out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_977 = out_f_roready_85; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_85 = out_wivalid_85 & out_wimask_85; // @[RegisterRouter.scala:87:24] wire out_f_woready_85 = out_woready_85 & out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_T_975 = out_front_bits_data[6]; // @[RegisterRouter.scala:87:24] wire _out_T_978 = ~out_rimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_979 = ~out_wimask_85; // @[RegisterRouter.scala:87:24] wire _out_T_980 = ~out_romask_85; // @[RegisterRouter.scala:87:24] wire _out_T_981 = ~out_womask_85; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_86 = out_frontMask[7]; // @[RegisterRouter.scala:87:24] wire out_rimask_86 = _out_rimask_T_86; // @[RegisterRouter.scala:87:24] wire out_wimask_86 = _out_wimask_T_86; // @[RegisterRouter.scala:87:24] wire _out_romask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_86 = out_backMask[7]; // @[RegisterRouter.scala:87:24] wire out_romask_86 = _out_romask_T_86; // @[RegisterRouter.scala:87:24] wire out_womask_86 = _out_womask_T_86; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_86 = out_rivalid_86 & out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_985 = out_f_rivalid_86; // @[RegisterRouter.scala:87:24] wire out_f_roready_86 = out_roready_86 & out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_986 = out_f_roready_86; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_86 = out_wivalid_86 & out_wimask_86; // @[RegisterRouter.scala:87:24] wire out_f_woready_86 = out_woready_86 & out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_T_984 = out_front_bits_data[7]; // @[RegisterRouter.scala:87:24] wire _out_T_987 = ~out_rimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_988 = ~out_wimask_86; // @[RegisterRouter.scala:87:24] wire _out_T_989 = ~out_romask_86; // @[RegisterRouter.scala:87:24] wire _out_T_990 = ~out_womask_86; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_87 = out_frontMask[8]; // @[RegisterRouter.scala:87:24] wire out_rimask_87 = _out_rimask_T_87; // @[RegisterRouter.scala:87:24] wire out_wimask_87 = _out_wimask_T_87; // @[RegisterRouter.scala:87:24] wire _out_romask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_87 = out_backMask[8]; // @[RegisterRouter.scala:87:24] wire out_romask_87 = _out_romask_T_87; // @[RegisterRouter.scala:87:24] wire out_womask_87 = _out_womask_T_87; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_87 = out_rivalid_87 & out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_994 = out_f_rivalid_87; // @[RegisterRouter.scala:87:24] wire out_f_roready_87 = out_roready_87 & out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_995 = out_f_roready_87; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_87 = out_wivalid_87 & out_wimask_87; // @[RegisterRouter.scala:87:24] wire out_f_woready_87 = out_woready_87 & out_womask_87; // @[RegisterRouter.scala:87:24] wire _out_T_993 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24] wire _out_T_996 = ~out_rimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_997 = ~out_wimask_87; // @[RegisterRouter.scala:87:24] wire _out_T_998 = ~out_romask_87; // @[RegisterRouter.scala:87:24] wire _out_T_999 = ~out_womask_87; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend_65 = {DMSTATUSRdData_anyhalted, 8'hA2}; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1000 = out_prepend_65; // @[RegisterRouter.scala:87:24] wire [8:0] _out_T_1001 = _out_T_1000; // @[RegisterRouter.scala:87:24] wire [8:0] _out_prepend_T_66 = _out_T_1001; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_88 = out_frontMask[9]; // @[RegisterRouter.scala:87:24] wire out_rimask_88 = _out_rimask_T_88; // @[RegisterRouter.scala:87:24] wire out_wimask_88 = _out_wimask_T_88; // @[RegisterRouter.scala:87:24] wire _out_romask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_88 = out_backMask[9]; // @[RegisterRouter.scala:87:24] wire out_romask_88 = _out_romask_T_88; // @[RegisterRouter.scala:87:24] wire out_womask_88 = _out_womask_T_88; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_88 = out_rivalid_88 & out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1003 = out_f_rivalid_88; // @[RegisterRouter.scala:87:24] wire out_f_roready_88 = out_roready_88 & out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1004 = out_f_roready_88; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_88 = out_wivalid_88 & out_wimask_88; // @[RegisterRouter.scala:87:24] wire out_f_woready_88 = out_woready_88 & out_womask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1002 = out_front_bits_data[9]; // @[RegisterRouter.scala:87:24] wire _out_T_1005 = ~out_rimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1006 = ~out_wimask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1007 = ~out_romask_88; // @[RegisterRouter.scala:87:24] wire _out_T_1008 = ~out_womask_88; // @[RegisterRouter.scala:87:24] wire [9:0] out_prepend_66 = {DMSTATUSRdData_allhalted, _out_prepend_T_66}; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1009 = out_prepend_66; // @[RegisterRouter.scala:87:24] wire [9:0] _out_T_1010 = _out_T_1009; // @[RegisterRouter.scala:87:24] wire [9:0] _out_prepend_T_67 = _out_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_89 = out_frontMask[10]; // @[RegisterRouter.scala:87:24] wire out_rimask_89 = _out_rimask_T_89; // @[RegisterRouter.scala:87:24] wire out_wimask_89 = _out_wimask_T_89; // @[RegisterRouter.scala:87:24] wire _out_romask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_89 = out_backMask[10]; // @[RegisterRouter.scala:87:24] wire out_romask_89 = _out_romask_T_89; // @[RegisterRouter.scala:87:24] wire out_womask_89 = _out_womask_T_89; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_89 = out_rivalid_89 & out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1012 = out_f_rivalid_89; // @[RegisterRouter.scala:87:24] wire out_f_roready_89 = out_roready_89 & out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1013 = out_f_roready_89; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_89 = out_wivalid_89 & out_wimask_89; // @[RegisterRouter.scala:87:24] wire out_f_woready_89 = out_woready_89 & out_womask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1011 = out_front_bits_data[10]; // @[RegisterRouter.scala:87:24] wire _out_T_1014 = ~out_rimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1015 = ~out_wimask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1016 = ~out_romask_89; // @[RegisterRouter.scala:87:24] wire _out_T_1017 = ~out_womask_89; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_67 = {DMSTATUSRdData_anyrunning, _out_prepend_T_67}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1018 = out_prepend_67; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1019 = _out_T_1018; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_68 = _out_T_1019; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_90 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_112 = out_frontMask[11]; // @[RegisterRouter.scala:87:24] wire out_rimask_90 = _out_rimask_T_90; // @[RegisterRouter.scala:87:24] wire out_wimask_90 = _out_wimask_T_90; // @[RegisterRouter.scala:87:24] wire _out_romask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_90 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_112 = out_backMask[11]; // @[RegisterRouter.scala:87:24] wire out_romask_90 = _out_romask_T_90; // @[RegisterRouter.scala:87:24] wire out_womask_90 = _out_womask_T_90; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_90 = out_rivalid_90 & out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1021 = out_f_rivalid_90; // @[RegisterRouter.scala:87:24] wire out_f_roready_90 = out_roready_90 & out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1022 = out_f_roready_90; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_90 = out_wivalid_90 & out_wimask_90; // @[RegisterRouter.scala:87:24] wire out_f_woready_90 = out_woready_90 & out_womask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1020 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1236 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24] wire _out_T_1023 = ~out_rimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1024 = ~out_wimask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1025 = ~out_romask_90; // @[RegisterRouter.scala:87:24] wire _out_T_1026 = ~out_womask_90; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_68 = {DMSTATUSRdData_allrunning, _out_prepend_T_68}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1027 = out_prepend_68; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1028 = _out_T_1027; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_69 = _out_T_1028; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_91 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_113 = out_frontMask[12]; // @[RegisterRouter.scala:87:24] wire out_rimask_91 = _out_rimask_T_91; // @[RegisterRouter.scala:87:24] wire out_wimask_91 = _out_wimask_T_91; // @[RegisterRouter.scala:87:24] wire _out_romask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_91 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_113 = out_backMask[12]; // @[RegisterRouter.scala:87:24] wire out_romask_91 = _out_romask_T_91; // @[RegisterRouter.scala:87:24] wire out_womask_91 = _out_womask_T_91; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_91 = out_rivalid_91 & out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1030 = out_f_rivalid_91; // @[RegisterRouter.scala:87:24] wire out_f_roready_91 = out_roready_91 & out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1031 = out_f_roready_91; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_91 = out_wivalid_91 & out_wimask_91; // @[RegisterRouter.scala:87:24] wire out_f_woready_91 = out_woready_91 & out_womask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1029 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1245 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24] wire _out_T_1032 = ~out_rimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1033 = ~out_wimask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1034 = ~out_romask_91; // @[RegisterRouter.scala:87:24] wire _out_T_1035 = ~out_womask_91; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_69 = {1'h0, _out_prepend_T_69}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1036 = out_prepend_69; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1037 = _out_T_1036; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_70 = _out_T_1037; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_92 = out_frontMask[13]; // @[RegisterRouter.scala:87:24] wire out_rimask_92 = _out_rimask_T_92; // @[RegisterRouter.scala:87:24] wire out_wimask_92 = _out_wimask_T_92; // @[RegisterRouter.scala:87:24] wire _out_romask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_92 = out_backMask[13]; // @[RegisterRouter.scala:87:24] wire out_romask_92 = _out_romask_T_92; // @[RegisterRouter.scala:87:24] wire out_womask_92 = _out_womask_T_92; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_92 = out_rivalid_92 & out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1039 = out_f_rivalid_92; // @[RegisterRouter.scala:87:24] wire out_f_roready_92 = out_roready_92 & out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1040 = out_f_roready_92; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_92 = out_wivalid_92 & out_wimask_92; // @[RegisterRouter.scala:87:24] wire out_f_woready_92 = out_woready_92 & out_womask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1038 = out_front_bits_data[13]; // @[RegisterRouter.scala:87:24] wire _out_T_1041 = ~out_rimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1042 = ~out_wimask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1043 = ~out_romask_92; // @[RegisterRouter.scala:87:24] wire _out_T_1044 = ~out_womask_92; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_70 = {DMSTATUSRdData_allunavail, _out_prepend_T_70}; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1045 = out_prepend_70; // @[RegisterRouter.scala:87:24] wire [13:0] _out_T_1046 = _out_T_1045; // @[RegisterRouter.scala:87:24] wire [13:0] _out_prepend_T_71 = _out_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_93 = out_frontMask[14]; // @[RegisterRouter.scala:87:24] wire out_rimask_93 = _out_rimask_T_93; // @[RegisterRouter.scala:87:24] wire out_wimask_93 = _out_wimask_T_93; // @[RegisterRouter.scala:87:24] wire _out_romask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_93 = out_backMask[14]; // @[RegisterRouter.scala:87:24] wire out_romask_93 = _out_romask_T_93; // @[RegisterRouter.scala:87:24] wire out_womask_93 = _out_womask_T_93; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_93 = out_rivalid_93 & out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1048 = out_f_rivalid_93; // @[RegisterRouter.scala:87:24] wire out_f_roready_93 = out_roready_93 & out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1049 = out_f_roready_93; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_93 = out_wivalid_93 & out_wimask_93; // @[RegisterRouter.scala:87:24] wire out_f_woready_93 = out_woready_93 & out_womask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1047 = out_front_bits_data[14]; // @[RegisterRouter.scala:87:24] wire _out_T_1050 = ~out_rimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1051 = ~out_wimask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1052 = ~out_romask_93; // @[RegisterRouter.scala:87:24] wire _out_T_1053 = ~out_womask_93; // @[RegisterRouter.scala:87:24] wire [14:0] out_prepend_71 = {DMSTATUSRdData_anynonexistent, _out_prepend_T_71}; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1054 = out_prepend_71; // @[RegisterRouter.scala:87:24] wire [14:0] _out_T_1055 = _out_T_1054; // @[RegisterRouter.scala:87:24] wire [14:0] _out_prepend_T_72 = _out_T_1055; // @[RegisterRouter.scala:87:24] wire out_rimask_94 = _out_rimask_T_94; // @[RegisterRouter.scala:87:24] wire out_wimask_94 = _out_wimask_T_94; // @[RegisterRouter.scala:87:24] wire out_romask_94 = _out_romask_T_94; // @[RegisterRouter.scala:87:24] wire out_womask_94 = _out_womask_T_94; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_94 = out_rivalid_94 & out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1057 = out_f_rivalid_94; // @[RegisterRouter.scala:87:24] wire out_f_roready_94 = out_roready_94 & out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1058 = out_f_roready_94; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_94 = out_wivalid_94 & out_wimask_94; // @[RegisterRouter.scala:87:24] wire out_f_woready_94 = out_woready_94 & out_womask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1059 = ~out_rimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1060 = ~out_wimask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1061 = ~out_romask_94; // @[RegisterRouter.scala:87:24] wire _out_T_1062 = ~out_womask_94; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_72 = {DMSTATUSRdData_allnonexistent, _out_prepend_T_72}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1063 = out_prepend_72; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1064 = _out_T_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_73 = _out_T_1064; // @[RegisterRouter.scala:87:24] wire out_rimask_95 = _out_rimask_T_95; // @[RegisterRouter.scala:87:24] wire out_wimask_95 = _out_wimask_T_95; // @[RegisterRouter.scala:87:24] wire out_romask_95 = _out_romask_T_95; // @[RegisterRouter.scala:87:24] wire out_womask_95 = _out_womask_T_95; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_95 = out_rivalid_95 & out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1066 = out_f_rivalid_95; // @[RegisterRouter.scala:87:24] wire out_f_roready_95 = out_roready_95 & out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1067 = out_f_roready_95; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_95 = out_wivalid_95 & out_wimask_95; // @[RegisterRouter.scala:87:24] wire out_f_woready_95 = out_woready_95 & out_womask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1068 = ~out_rimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1069 = ~out_wimask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1070 = ~out_romask_95; // @[RegisterRouter.scala:87:24] wire _out_T_1071 = ~out_womask_95; // @[RegisterRouter.scala:87:24] wire [16:0] out_prepend_73 = {DMSTATUSRdData_anyresumeack, _out_prepend_T_73}; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1072 = out_prepend_73; // @[RegisterRouter.scala:87:24] wire [16:0] _out_T_1073 = _out_T_1072; // @[RegisterRouter.scala:87:24] wire [16:0] _out_prepend_T_74 = _out_T_1073; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_96 = out_frontMask[17]; // @[RegisterRouter.scala:87:24] wire out_rimask_96 = _out_rimask_T_96; // @[RegisterRouter.scala:87:24] wire out_wimask_96 = _out_wimask_T_96; // @[RegisterRouter.scala:87:24] wire _out_romask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_96 = out_backMask[17]; // @[RegisterRouter.scala:87:24] wire out_romask_96 = _out_romask_T_96; // @[RegisterRouter.scala:87:24] wire out_womask_96 = _out_womask_T_96; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_96 = out_rivalid_96 & out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1075 = out_f_rivalid_96; // @[RegisterRouter.scala:87:24] wire out_f_roready_96 = out_roready_96 & out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1076 = out_f_roready_96; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_96 = out_wivalid_96 & out_wimask_96; // @[RegisterRouter.scala:87:24] wire out_f_woready_96 = out_woready_96 & out_womask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1074 = out_front_bits_data[17]; // @[RegisterRouter.scala:87:24] wire _out_T_1077 = ~out_rimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1078 = ~out_wimask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1079 = ~out_romask_96; // @[RegisterRouter.scala:87:24] wire _out_T_1080 = ~out_womask_96; // @[RegisterRouter.scala:87:24] wire [17:0] out_prepend_74 = {DMSTATUSRdData_allresumeack, _out_prepend_T_74}; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1081 = out_prepend_74; // @[RegisterRouter.scala:87:24] wire [17:0] _out_T_1082 = _out_T_1081; // @[RegisterRouter.scala:87:24] wire [17:0] _out_prepend_T_75 = _out_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_97 = out_frontMask[18]; // @[RegisterRouter.scala:87:24] wire out_rimask_97 = _out_rimask_T_97; // @[RegisterRouter.scala:87:24] wire out_wimask_97 = _out_wimask_T_97; // @[RegisterRouter.scala:87:24] wire _out_romask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_97 = out_backMask[18]; // @[RegisterRouter.scala:87:24] wire out_romask_97 = _out_romask_T_97; // @[RegisterRouter.scala:87:24] wire out_womask_97 = _out_womask_T_97; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_97 = out_rivalid_97 & out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1084 = out_f_rivalid_97; // @[RegisterRouter.scala:87:24] wire out_f_roready_97 = out_roready_97 & out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1085 = out_f_roready_97; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_97 = out_wivalid_97 & out_wimask_97; // @[RegisterRouter.scala:87:24] wire out_f_woready_97 = out_woready_97 & out_womask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1083 = out_front_bits_data[18]; // @[RegisterRouter.scala:87:24] wire _out_T_1086 = ~out_rimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1087 = ~out_wimask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1088 = ~out_romask_97; // @[RegisterRouter.scala:87:24] wire _out_T_1089 = ~out_womask_97; // @[RegisterRouter.scala:87:24] wire [18:0] out_prepend_75 = {DMSTATUSRdData_anyhavereset, _out_prepend_T_75}; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1090 = out_prepend_75; // @[RegisterRouter.scala:87:24] wire [18:0] _out_T_1091 = _out_T_1090; // @[RegisterRouter.scala:87:24] wire [18:0] _out_prepend_T_76 = _out_T_1091; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_98 = out_frontMask[19]; // @[RegisterRouter.scala:87:24] wire out_rimask_98 = _out_rimask_T_98; // @[RegisterRouter.scala:87:24] wire out_wimask_98 = _out_wimask_T_98; // @[RegisterRouter.scala:87:24] wire _out_romask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_98 = out_backMask[19]; // @[RegisterRouter.scala:87:24] wire out_romask_98 = _out_romask_T_98; // @[RegisterRouter.scala:87:24] wire out_womask_98 = _out_womask_T_98; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_98 = out_rivalid_98 & out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1093 = out_f_rivalid_98; // @[RegisterRouter.scala:87:24] wire out_f_roready_98 = out_roready_98 & out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1094 = out_f_roready_98; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_98 = out_wivalid_98 & out_wimask_98; // @[RegisterRouter.scala:87:24] wire out_f_woready_98 = out_woready_98 & out_womask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1092 = out_front_bits_data[19]; // @[RegisterRouter.scala:87:24] wire _out_T_1095 = ~out_rimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1096 = ~out_wimask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1097 = ~out_romask_98; // @[RegisterRouter.scala:87:24] wire _out_T_1098 = ~out_womask_98; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_76 = {DMSTATUSRdData_allhavereset, _out_prepend_T_76}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1099 = out_prepend_76; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_1100 = _out_T_1099; // @[RegisterRouter.scala:87:24] wire [19:0] _out_prepend_T_77 = _out_T_1100; // @[RegisterRouter.scala:87:24] wire [1:0] _out_rimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_wimask_T_99 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_rimask_99 = |_out_rimask_T_99; // @[RegisterRouter.scala:87:24] wire out_wimask_99 = &_out_wimask_T_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_romask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire [1:0] _out_womask_T_99 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24] wire out_romask_99 = |_out_romask_T_99; // @[RegisterRouter.scala:87:24] wire out_womask_99 = &_out_womask_T_99; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_99 = out_rivalid_99 & out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1102 = out_f_rivalid_99; // @[RegisterRouter.scala:87:24] wire out_f_roready_99 = out_roready_99 & out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1103 = out_f_roready_99; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_99 = out_wivalid_99 & out_wimask_99; // @[RegisterRouter.scala:87:24] wire out_f_woready_99 = out_woready_99 & out_womask_99; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_1101 = out_front_bits_data[21:20]; // @[RegisterRouter.scala:87:24] wire _out_T_1104 = ~out_rimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1105 = ~out_wimask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1106 = ~out_romask_99; // @[RegisterRouter.scala:87:24] wire _out_T_1107 = ~out_womask_99; // @[RegisterRouter.scala:87:24] wire [20:0] out_prepend_77 = {1'h0, _out_prepend_T_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1108 = {1'h0, out_prepend_77}; // @[RegisterRouter.scala:87:24] wire [21:0] _out_T_1109 = _out_T_1108; // @[RegisterRouter.scala:87:24] wire [21:0] _out_prepend_T_78 = _out_T_1109; // @[RegisterRouter.scala:87:24] wire out_rimask_100 = _out_rimask_T_100; // @[RegisterRouter.scala:87:24] wire out_wimask_100 = _out_wimask_T_100; // @[RegisterRouter.scala:87:24] wire out_romask_100 = _out_romask_T_100; // @[RegisterRouter.scala:87:24] wire out_womask_100 = _out_womask_T_100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_100 = out_rivalid_100 & out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1111 = out_f_rivalid_100; // @[RegisterRouter.scala:87:24] wire out_f_roready_100 = out_roready_100 & out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1112 = out_f_roready_100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_100 = out_wivalid_100 & out_wimask_100; // @[RegisterRouter.scala:87:24] wire out_f_woready_100 = out_woready_100 & out_womask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1113 = ~out_rimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1114 = ~out_wimask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1115 = ~out_romask_100; // @[RegisterRouter.scala:87:24] wire _out_T_1116 = ~out_womask_100; // @[RegisterRouter.scala:87:24] wire [22:0] out_prepend_78 = {1'h0, _out_prepend_T_78}; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1117 = out_prepend_78; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_1118 = _out_T_1117; // @[RegisterRouter.scala:87:24] wire out_rimask_101 = |_out_rimask_T_101; // @[RegisterRouter.scala:87:24] wire out_wimask_101 = &_out_wimask_T_101; // @[RegisterRouter.scala:87:24] wire out_romask_101 = |_out_romask_T_101; // @[RegisterRouter.scala:87:24] wire out_womask_101 = &_out_womask_T_101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_101 = out_rivalid_101 & out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1120 = out_f_rivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_roready_101 = out_roready_101 & out_romask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_0 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1121 = out_f_roready_101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_101 = out_wivalid_101 & out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1122 = out_f_wivalid_101; // @[RegisterRouter.scala:87:24] assign out_f_woready_101 = out_woready_101 & out_womask_101; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_0 = out_f_woready_101; // @[RegisterRouter.scala:87:24] wire _out_T_1123 = out_f_woready_101; // @[RegisterRouter.scala:87:24] assign programBufferNxt_0 = out_f_woready_101 ? _out_T_1119 : programBufferMem_0; // @[RegisterRouter.scala:87:24] wire _out_T_1124 = ~out_rimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1125 = ~out_wimask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1126 = ~out_romask_101; // @[RegisterRouter.scala:87:24] wire _out_T_1127 = ~out_womask_101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1129 = _out_T_1128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_79 = _out_T_1129; // @[RegisterRouter.scala:87:24] wire out_rimask_102 = |_out_rimask_T_102; // @[RegisterRouter.scala:87:24] wire out_wimask_102 = &_out_wimask_T_102; // @[RegisterRouter.scala:87:24] wire out_romask_102 = |_out_romask_T_102; // @[RegisterRouter.scala:87:24] wire out_womask_102 = &_out_womask_T_102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_102 = out_rivalid_102 & out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1131 = out_f_rivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_roready_102 = out_roready_102 & out_romask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_1 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1132 = out_f_roready_102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_102 = out_wivalid_102 & out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1133 = out_f_wivalid_102; // @[RegisterRouter.scala:87:24] assign out_f_woready_102 = out_woready_102 & out_womask_102; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_1 = out_f_woready_102; // @[RegisterRouter.scala:87:24] wire _out_T_1134 = out_f_woready_102; // @[RegisterRouter.scala:87:24] assign programBufferNxt_1 = out_f_woready_102 ? _out_T_1130 : programBufferMem_1; // @[RegisterRouter.scala:87:24] wire _out_T_1135 = ~out_rimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1136 = ~out_wimask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1137 = ~out_romask_102; // @[RegisterRouter.scala:87:24] wire _out_T_1138 = ~out_womask_102; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_79 = {programBufferMem_1, _out_prepend_T_79}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1139 = out_prepend_79; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1140 = _out_T_1139; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_80 = _out_T_1140; // @[RegisterRouter.scala:87:24] wire out_rimask_103 = |_out_rimask_T_103; // @[RegisterRouter.scala:87:24] wire out_wimask_103 = &_out_wimask_T_103; // @[RegisterRouter.scala:87:24] wire out_romask_103 = |_out_romask_T_103; // @[RegisterRouter.scala:87:24] wire out_womask_103 = &_out_womask_T_103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_103 = out_rivalid_103 & out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1142 = out_f_rivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_roready_103 = out_roready_103 & out_romask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_2 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1143 = out_f_roready_103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_103 = out_wivalid_103 & out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1144 = out_f_wivalid_103; // @[RegisterRouter.scala:87:24] assign out_f_woready_103 = out_woready_103 & out_womask_103; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_2 = out_f_woready_103; // @[RegisterRouter.scala:87:24] wire _out_T_1145 = out_f_woready_103; // @[RegisterRouter.scala:87:24] assign programBufferNxt_2 = out_f_woready_103 ? _out_T_1141 : programBufferMem_2; // @[RegisterRouter.scala:87:24] wire _out_T_1146 = ~out_rimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1147 = ~out_wimask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1148 = ~out_romask_103; // @[RegisterRouter.scala:87:24] wire _out_T_1149 = ~out_womask_103; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_80 = {programBufferMem_2, _out_prepend_T_80}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1150 = out_prepend_80; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1151 = _out_T_1150; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_81 = _out_T_1151; // @[RegisterRouter.scala:87:24] wire out_rimask_104 = |_out_rimask_T_104; // @[RegisterRouter.scala:87:24] wire out_wimask_104 = &_out_wimask_T_104; // @[RegisterRouter.scala:87:24] wire out_romask_104 = |_out_romask_T_104; // @[RegisterRouter.scala:87:24] wire out_womask_104 = &_out_womask_T_104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_104 = out_rivalid_104 & out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1153 = out_f_rivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_roready_104 = out_roready_104 & out_romask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_3 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1154 = out_f_roready_104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_104 = out_wivalid_104 & out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1155 = out_f_wivalid_104; // @[RegisterRouter.scala:87:24] assign out_f_woready_104 = out_woready_104 & out_womask_104; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_3 = out_f_woready_104; // @[RegisterRouter.scala:87:24] wire _out_T_1156 = out_f_woready_104; // @[RegisterRouter.scala:87:24] assign programBufferNxt_3 = out_f_woready_104 ? _out_T_1152 : programBufferMem_3; // @[RegisterRouter.scala:87:24] wire _out_T_1157 = ~out_rimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1158 = ~out_wimask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1159 = ~out_romask_104; // @[RegisterRouter.scala:87:24] wire _out_T_1160 = ~out_womask_104; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_81 = {programBufferMem_3, _out_prepend_T_81}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1161 = out_prepend_81; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1162 = _out_T_1161; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_32 = _out_T_1162; // @[MuxLiteral.scala:49:48] wire out_rimask_105 = |_out_rimask_T_105; // @[RegisterRouter.scala:87:24] wire out_wimask_105 = &_out_wimask_T_105; // @[RegisterRouter.scala:87:24] wire out_romask_105 = |_out_romask_T_105; // @[RegisterRouter.scala:87:24] wire out_womask_105 = &_out_womask_T_105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_105 = out_rivalid_105 & out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1164 = out_f_rivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_roready_105 = out_roready_105 & out_romask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_8 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1165 = out_f_roready_105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_105 = out_wivalid_105 & out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1166 = out_f_wivalid_105; // @[RegisterRouter.scala:87:24] assign out_f_woready_105 = out_woready_105 & out_womask_105; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_8 = out_f_woready_105; // @[RegisterRouter.scala:87:24] wire _out_T_1167 = out_f_woready_105; // @[RegisterRouter.scala:87:24] assign programBufferNxt_8 = out_f_woready_105 ? _out_T_1163 : programBufferMem_8; // @[RegisterRouter.scala:87:24] wire _out_T_1168 = ~out_rimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1169 = ~out_wimask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1170 = ~out_romask_105; // @[RegisterRouter.scala:87:24] wire _out_T_1171 = ~out_womask_105; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1173 = _out_T_1172; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_82 = _out_T_1173; // @[RegisterRouter.scala:87:24] wire out_rimask_106 = |_out_rimask_T_106; // @[RegisterRouter.scala:87:24] wire out_wimask_106 = &_out_wimask_T_106; // @[RegisterRouter.scala:87:24] wire out_romask_106 = |_out_romask_T_106; // @[RegisterRouter.scala:87:24] wire out_womask_106 = &_out_womask_T_106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_106 = out_rivalid_106 & out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1175 = out_f_rivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_roready_106 = out_roready_106 & out_romask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_9 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1176 = out_f_roready_106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_106 = out_wivalid_106 & out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1177 = out_f_wivalid_106; // @[RegisterRouter.scala:87:24] assign out_f_woready_106 = out_woready_106 & out_womask_106; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_9 = out_f_woready_106; // @[RegisterRouter.scala:87:24] wire _out_T_1178 = out_f_woready_106; // @[RegisterRouter.scala:87:24] assign programBufferNxt_9 = out_f_woready_106 ? _out_T_1174 : programBufferMem_9; // @[RegisterRouter.scala:87:24] wire _out_T_1179 = ~out_rimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1180 = ~out_wimask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1181 = ~out_romask_106; // @[RegisterRouter.scala:87:24] wire _out_T_1182 = ~out_womask_106; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_82 = {programBufferMem_9, _out_prepend_T_82}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1183 = out_prepend_82; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1184 = _out_T_1183; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_83 = _out_T_1184; // @[RegisterRouter.scala:87:24] wire out_rimask_107 = |_out_rimask_T_107; // @[RegisterRouter.scala:87:24] wire out_wimask_107 = &_out_wimask_T_107; // @[RegisterRouter.scala:87:24] wire out_romask_107 = |_out_romask_T_107; // @[RegisterRouter.scala:87:24] wire out_womask_107 = &_out_womask_T_107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_107 = out_rivalid_107 & out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1186 = out_f_rivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_roready_107 = out_roready_107 & out_romask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_10 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1187 = out_f_roready_107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_107 = out_wivalid_107 & out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1188 = out_f_wivalid_107; // @[RegisterRouter.scala:87:24] assign out_f_woready_107 = out_woready_107 & out_womask_107; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_10 = out_f_woready_107; // @[RegisterRouter.scala:87:24] wire _out_T_1189 = out_f_woready_107; // @[RegisterRouter.scala:87:24] assign programBufferNxt_10 = out_f_woready_107 ? _out_T_1185 : programBufferMem_10; // @[RegisterRouter.scala:87:24] wire _out_T_1190 = ~out_rimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1191 = ~out_wimask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1192 = ~out_romask_107; // @[RegisterRouter.scala:87:24] wire _out_T_1193 = ~out_womask_107; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_83 = {programBufferMem_10, _out_prepend_T_83}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1194 = out_prepend_83; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1195 = _out_T_1194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_84 = _out_T_1195; // @[RegisterRouter.scala:87:24] wire out_rimask_108 = |_out_rimask_T_108; // @[RegisterRouter.scala:87:24] wire out_wimask_108 = &_out_wimask_T_108; // @[RegisterRouter.scala:87:24] wire out_romask_108 = |_out_romask_T_108; // @[RegisterRouter.scala:87:24] wire out_womask_108 = &_out_womask_T_108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_108 = out_rivalid_108 & out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1197 = out_f_rivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_roready_108 = out_roready_108 & out_romask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_11 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1198 = out_f_roready_108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_108 = out_wivalid_108 & out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1199 = out_f_wivalid_108; // @[RegisterRouter.scala:87:24] assign out_f_woready_108 = out_woready_108 & out_womask_108; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_11 = out_f_woready_108; // @[RegisterRouter.scala:87:24] wire _out_T_1200 = out_f_woready_108; // @[RegisterRouter.scala:87:24] assign programBufferNxt_11 = out_f_woready_108 ? _out_T_1196 : programBufferMem_11; // @[RegisterRouter.scala:87:24] wire _out_T_1201 = ~out_rimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1202 = ~out_wimask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1203 = ~out_romask_108; // @[RegisterRouter.scala:87:24] wire _out_T_1204 = ~out_womask_108; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_84 = {programBufferMem_11, _out_prepend_T_84}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1205 = out_prepend_84; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1206 = _out_T_1205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_34 = _out_T_1206; // @[MuxLiteral.scala:49:48] wire out_rimask_109 = |_out_rimask_T_109; // @[RegisterRouter.scala:87:24] wire out_wimask_109 = &_out_wimask_T_109; // @[RegisterRouter.scala:87:24] wire out_romask_109 = |_out_romask_T_109; // @[RegisterRouter.scala:87:24] wire out_womask_109 = &_out_womask_T_109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_109 = out_rivalid_109 & out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1208 = out_f_rivalid_109; // @[RegisterRouter.scala:87:24] wire out_f_roready_109 = out_roready_109 & out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1209 = out_f_roready_109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_109 = out_wivalid_109 & out_wimask_109; // @[RegisterRouter.scala:87:24] wire out_f_woready_109 = out_woready_109 & out_womask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1210 = ~out_rimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1211 = ~out_wimask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1212 = ~out_romask_109; // @[RegisterRouter.scala:87:24] wire _out_T_1213 = ~out_womask_109; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_110 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_rimask_110 = |_out_rimask_T_110; // @[RegisterRouter.scala:87:24] wire out_wimask_110 = &_out_wimask_T_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_110 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24] wire out_romask_110 = |_out_romask_T_110; // @[RegisterRouter.scala:87:24] wire out_womask_110 = &_out_womask_T_110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_110 = out_rivalid_110 & out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1217 = out_f_rivalid_110; // @[RegisterRouter.scala:87:24] wire out_f_roready_110 = out_roready_110 & out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1218 = out_f_roready_110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_110 = out_wivalid_110 & out_wimask_110; // @[RegisterRouter.scala:87:24] wire out_f_woready_110 = out_woready_110 & out_womask_110; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_1216 = out_front_bits_data[7:4]; // @[RegisterRouter.scala:87:24] wire _out_T_1219 = ~out_rimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1220 = ~out_wimask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1221 = ~out_romask_110; // @[RegisterRouter.scala:87:24] wire _out_T_1222 = ~out_womask_110; // @[RegisterRouter.scala:87:24] wire [2:0] _out_rimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_wimask_T_111 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_111 = |_out_rimask_T_111; // @[RegisterRouter.scala:87:24] wire out_wimask_111 = &_out_wimask_T_111; // @[RegisterRouter.scala:87:24] wire [2:0] _out_romask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire [2:0] _out_womask_T_111 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24] wire out_romask_111 = |_out_romask_T_111; // @[RegisterRouter.scala:87:24] wire out_womask_111 = &_out_womask_T_111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_111 = out_rivalid_111 & out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1226 = out_f_rivalid_111; // @[RegisterRouter.scala:87:24] wire out_f_roready_111 = out_roready_111 & out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1227 = out_f_roready_111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_111 = out_wivalid_111 & out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1228 = out_f_wivalid_111; // @[RegisterRouter.scala:87:24] assign out_f_woready_111 = out_woready_111 & out_womask_111; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrEnMaybe = out_f_woready_111; // @[RegisterRouter.scala:87:24] wire _out_T_1229 = out_f_woready_111; // @[RegisterRouter.scala:87:24] assign _out_T_1225 = out_front_bits_data[10:8]; // @[RegisterRouter.scala:87:24] assign ABSTRACTCSWrData_cmderr = _out_T_1225; // @[RegisterRouter.scala:87:24] wire _out_T_1230 = ~out_rimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1231 = ~out_wimask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1232 = ~out_romask_111; // @[RegisterRouter.scala:87:24] wire _out_T_1233 = ~out_womask_111; // @[RegisterRouter.scala:87:24] wire [10:0] out_prepend_86 = {ABSTRACTCSRdData_cmderr, 8'h8}; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1234 = out_prepend_86; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1235 = _out_T_1234; // @[RegisterRouter.scala:87:24] wire [10:0] _out_prepend_T_87 = _out_T_1235; // @[RegisterRouter.scala:87:24] wire out_rimask_112 = _out_rimask_T_112; // @[RegisterRouter.scala:87:24] wire out_wimask_112 = _out_wimask_T_112; // @[RegisterRouter.scala:87:24] wire out_romask_112 = _out_romask_T_112; // @[RegisterRouter.scala:87:24] wire out_womask_112 = _out_womask_T_112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_112 = out_rivalid_112 & out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1237 = out_f_rivalid_112; // @[RegisterRouter.scala:87:24] wire out_f_roready_112 = out_roready_112 & out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1238 = out_f_roready_112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_112 = out_wivalid_112 & out_wimask_112; // @[RegisterRouter.scala:87:24] wire out_f_woready_112 = out_woready_112 & out_womask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1239 = ~out_rimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1240 = ~out_wimask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1241 = ~out_romask_112; // @[RegisterRouter.scala:87:24] wire _out_T_1242 = ~out_womask_112; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend_87 = {1'h0, _out_prepend_T_87}; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1243 = out_prepend_87; // @[RegisterRouter.scala:87:24] wire [11:0] _out_T_1244 = _out_T_1243; // @[RegisterRouter.scala:87:24] wire [11:0] _out_prepend_T_88 = _out_T_1244; // @[RegisterRouter.scala:87:24] wire out_rimask_113 = _out_rimask_T_113; // @[RegisterRouter.scala:87:24] wire out_wimask_113 = _out_wimask_T_113; // @[RegisterRouter.scala:87:24] wire out_romask_113 = _out_romask_T_113; // @[RegisterRouter.scala:87:24] wire out_womask_113 = _out_womask_T_113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_113 = out_rivalid_113 & out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1246 = out_f_rivalid_113; // @[RegisterRouter.scala:87:24] wire out_f_roready_113 = out_roready_113 & out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1247 = out_f_roready_113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_113 = out_wivalid_113 & out_wimask_113; // @[RegisterRouter.scala:87:24] wire out_f_woready_113 = out_woready_113 & out_womask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1248 = ~out_rimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1249 = ~out_wimask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1250 = ~out_romask_113; // @[RegisterRouter.scala:87:24] wire _out_T_1251 = ~out_womask_113; // @[RegisterRouter.scala:87:24] wire [12:0] out_prepend_88 = {ABSTRACTCSRdData_busy, _out_prepend_T_88}; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1252 = out_prepend_88; // @[RegisterRouter.scala:87:24] wire [12:0] _out_T_1253 = _out_T_1252; // @[RegisterRouter.scala:87:24] wire [12:0] _out_prepend_T_89 = _out_T_1253; // @[RegisterRouter.scala:87:24] wire [10:0] _out_rimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_wimask_T_114 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_rimask_114 = |_out_rimask_T_114; // @[RegisterRouter.scala:87:24] wire out_wimask_114 = &_out_wimask_T_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_romask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire [10:0] _out_womask_T_114 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24] wire out_romask_114 = |_out_romask_T_114; // @[RegisterRouter.scala:87:24] wire out_womask_114 = &_out_womask_T_114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_114 = out_rivalid_114 & out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1255 = out_f_rivalid_114; // @[RegisterRouter.scala:87:24] wire out_f_roready_114 = out_roready_114 & out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1256 = out_f_roready_114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_114 = out_wivalid_114 & out_wimask_114; // @[RegisterRouter.scala:87:24] wire out_f_woready_114 = out_woready_114 & out_womask_114; // @[RegisterRouter.scala:87:24] wire [10:0] _out_T_1254 = out_front_bits_data[23:13]; // @[RegisterRouter.scala:87:24] wire _out_T_1257 = ~out_rimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1258 = ~out_wimask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1259 = ~out_romask_114; // @[RegisterRouter.scala:87:24] wire _out_T_1260 = ~out_womask_114; // @[RegisterRouter.scala:87:24] wire [13:0] out_prepend_89 = {1'h0, _out_prepend_T_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1261 = {10'h0, out_prepend_89}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1262 = _out_T_1261; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_90 = _out_T_1262; // @[RegisterRouter.scala:87:24] wire [4:0] _out_rimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_wimask_T_115 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_115 = |_out_rimask_T_115; // @[RegisterRouter.scala:87:24] wire out_wimask_115 = &_out_wimask_T_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_romask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire [4:0] _out_womask_T_115 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24] wire out_romask_115 = |_out_romask_T_115; // @[RegisterRouter.scala:87:24] wire out_womask_115 = &_out_womask_T_115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_115 = out_rivalid_115 & out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1264 = out_f_rivalid_115; // @[RegisterRouter.scala:87:24] wire out_f_roready_115 = out_roready_115 & out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1265 = out_f_roready_115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_115 = out_wivalid_115 & out_wimask_115; // @[RegisterRouter.scala:87:24] wire out_f_woready_115 = out_woready_115 & out_womask_115; // @[RegisterRouter.scala:87:24] wire [4:0] _out_T_1263 = out_front_bits_data[28:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1266 = ~out_rimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1267 = ~out_wimask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1268 = ~out_romask_115; // @[RegisterRouter.scala:87:24] wire _out_T_1269 = ~out_womask_115; // @[RegisterRouter.scala:87:24] wire [28:0] out_prepend_90 = {5'h10, _out_prepend_T_90}; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1270 = out_prepend_90; // @[RegisterRouter.scala:87:24] wire [28:0] _out_T_1271 = _out_T_1270; // @[RegisterRouter.scala:87:24] wire out_rimask_116 = |_out_rimask_T_116; // @[RegisterRouter.scala:87:24] wire out_wimask_116 = &_out_wimask_T_116; // @[RegisterRouter.scala:87:24] wire out_romask_116 = |_out_romask_T_116; // @[RegisterRouter.scala:87:24] wire out_womask_116 = &_out_womask_T_116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_116 = out_rivalid_116 & out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1273 = out_f_rivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_roready_116 = out_roready_116 & out_romask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_48 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1274 = out_f_roready_116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_116 = out_wivalid_116 & out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1275 = out_f_wivalid_116; // @[RegisterRouter.scala:87:24] assign out_f_woready_116 = out_woready_116 & out_womask_116; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_48 = out_f_woready_116; // @[RegisterRouter.scala:87:24] wire _out_T_1276 = out_f_woready_116; // @[RegisterRouter.scala:87:24] assign programBufferNxt_48 = out_f_woready_116 ? _out_T_1272 : programBufferMem_48; // @[RegisterRouter.scala:87:24] wire _out_T_1277 = ~out_rimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1278 = ~out_wimask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1279 = ~out_romask_116; // @[RegisterRouter.scala:87:24] wire _out_T_1280 = ~out_womask_116; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1282 = _out_T_1281; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_91 = _out_T_1282; // @[RegisterRouter.scala:87:24] wire out_rimask_117 = |_out_rimask_T_117; // @[RegisterRouter.scala:87:24] wire out_wimask_117 = &_out_wimask_T_117; // @[RegisterRouter.scala:87:24] wire out_romask_117 = |_out_romask_T_117; // @[RegisterRouter.scala:87:24] wire out_womask_117 = &_out_womask_T_117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_117 = out_rivalid_117 & out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1284 = out_f_rivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_roready_117 = out_roready_117 & out_romask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_49 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1285 = out_f_roready_117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_117 = out_wivalid_117 & out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1286 = out_f_wivalid_117; // @[RegisterRouter.scala:87:24] assign out_f_woready_117 = out_woready_117 & out_womask_117; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_49 = out_f_woready_117; // @[RegisterRouter.scala:87:24] wire _out_T_1287 = out_f_woready_117; // @[RegisterRouter.scala:87:24] assign programBufferNxt_49 = out_f_woready_117 ? _out_T_1283 : programBufferMem_49; // @[RegisterRouter.scala:87:24] wire _out_T_1288 = ~out_rimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1289 = ~out_wimask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1290 = ~out_romask_117; // @[RegisterRouter.scala:87:24] wire _out_T_1291 = ~out_womask_117; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_91 = {programBufferMem_49, _out_prepend_T_91}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1292 = out_prepend_91; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1293 = _out_T_1292; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_92 = _out_T_1293; // @[RegisterRouter.scala:87:24] wire out_rimask_118 = |_out_rimask_T_118; // @[RegisterRouter.scala:87:24] wire out_wimask_118 = &_out_wimask_T_118; // @[RegisterRouter.scala:87:24] wire out_romask_118 = |_out_romask_T_118; // @[RegisterRouter.scala:87:24] wire out_womask_118 = &_out_womask_T_118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_118 = out_rivalid_118 & out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1295 = out_f_rivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_50 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1296 = out_f_roready_118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_118 = out_wivalid_118 & out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1297 = out_f_wivalid_118; // @[RegisterRouter.scala:87:24] assign out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_50 = out_f_woready_118; // @[RegisterRouter.scala:87:24] wire _out_T_1298 = out_f_woready_118; // @[RegisterRouter.scala:87:24] assign programBufferNxt_50 = out_f_woready_118 ? _out_T_1294 : programBufferMem_50; // @[RegisterRouter.scala:87:24] wire _out_T_1299 = ~out_rimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1300 = ~out_wimask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1301 = ~out_romask_118; // @[RegisterRouter.scala:87:24] wire _out_T_1302 = ~out_womask_118; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_92 = {programBufferMem_50, _out_prepend_T_92}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1303 = out_prepend_92; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1304 = _out_T_1303; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_93 = _out_T_1304; // @[RegisterRouter.scala:87:24] wire out_rimask_119 = |_out_rimask_T_119; // @[RegisterRouter.scala:87:24] wire out_wimask_119 = &_out_wimask_T_119; // @[RegisterRouter.scala:87:24] wire out_romask_119 = |_out_romask_T_119; // @[RegisterRouter.scala:87:24] wire out_womask_119 = &_out_womask_T_119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_119 = out_rivalid_119 & out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1306 = out_f_rivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_roready_119 = out_roready_119 & out_romask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_51 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1307 = out_f_roready_119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_119 = out_wivalid_119 & out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1308 = out_f_wivalid_119; // @[RegisterRouter.scala:87:24] assign out_f_woready_119 = out_woready_119 & out_womask_119; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_51 = out_f_woready_119; // @[RegisterRouter.scala:87:24] wire _out_T_1309 = out_f_woready_119; // @[RegisterRouter.scala:87:24] assign programBufferNxt_51 = out_f_woready_119 ? _out_T_1305 : programBufferMem_51; // @[RegisterRouter.scala:87:24] wire _out_T_1310 = ~out_rimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1311 = ~out_wimask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1312 = ~out_romask_119; // @[RegisterRouter.scala:87:24] wire _out_T_1313 = ~out_womask_119; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_93 = {programBufferMem_51, _out_prepend_T_93}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1314 = out_prepend_93; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1315 = _out_T_1314; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_44 = _out_T_1315; // @[MuxLiteral.scala:49:48] wire out_rimask_120 = |_out_rimask_T_120; // @[RegisterRouter.scala:87:24] wire out_wimask_120 = &_out_wimask_T_120; // @[RegisterRouter.scala:87:24] wire out_romask_120 = |_out_romask_T_120; // @[RegisterRouter.scala:87:24] wire out_womask_120 = &_out_womask_T_120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_120 = out_rivalid_120 & out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1317 = out_f_rivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_roready_120 = out_roready_120 & out_romask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_12 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1318 = out_f_roready_120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_120 = out_wivalid_120 & out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1319 = out_f_wivalid_120; // @[RegisterRouter.scala:87:24] assign out_f_woready_120 = out_woready_120 & out_womask_120; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_12 = out_f_woready_120; // @[RegisterRouter.scala:87:24] wire _out_T_1320 = out_f_woready_120; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_12 = out_f_woready_120 ? _out_T_1316 : abstractDataMem_12; // @[RegisterRouter.scala:87:24] wire _out_T_1321 = ~out_rimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1322 = ~out_wimask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1323 = ~out_romask_120; // @[RegisterRouter.scala:87:24] wire _out_T_1324 = ~out_womask_120; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1326 = _out_T_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_94 = _out_T_1326; // @[RegisterRouter.scala:87:24] wire out_rimask_121 = |_out_rimask_T_121; // @[RegisterRouter.scala:87:24] wire out_wimask_121 = &_out_wimask_T_121; // @[RegisterRouter.scala:87:24] wire out_romask_121 = |_out_romask_T_121; // @[RegisterRouter.scala:87:24] wire out_womask_121 = &_out_womask_T_121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_121 = out_rivalid_121 & out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1328 = out_f_rivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_roready_121 = out_roready_121 & out_romask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_13 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1329 = out_f_roready_121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_121 = out_wivalid_121 & out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1330 = out_f_wivalid_121; // @[RegisterRouter.scala:87:24] assign out_f_woready_121 = out_woready_121 & out_womask_121; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_13 = out_f_woready_121; // @[RegisterRouter.scala:87:24] wire _out_T_1331 = out_f_woready_121; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_13 = out_f_woready_121 ? _out_T_1327 : abstractDataMem_13; // @[RegisterRouter.scala:87:24] wire _out_T_1332 = ~out_rimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1333 = ~out_wimask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1334 = ~out_romask_121; // @[RegisterRouter.scala:87:24] wire _out_T_1335 = ~out_womask_121; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_94 = {abstractDataMem_13, _out_prepend_T_94}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1336 = out_prepend_94; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1337 = _out_T_1336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_95 = _out_T_1337; // @[RegisterRouter.scala:87:24] wire out_rimask_122 = |_out_rimask_T_122; // @[RegisterRouter.scala:87:24] wire out_wimask_122 = &_out_wimask_T_122; // @[RegisterRouter.scala:87:24] wire out_romask_122 = |_out_romask_T_122; // @[RegisterRouter.scala:87:24] wire out_womask_122 = &_out_womask_T_122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_122 = out_rivalid_122 & out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1339 = out_f_rivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_roready_122 = out_roready_122 & out_romask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_14 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1340 = out_f_roready_122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_122 = out_wivalid_122 & out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1341 = out_f_wivalid_122; // @[RegisterRouter.scala:87:24] assign out_f_woready_122 = out_woready_122 & out_womask_122; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_14 = out_f_woready_122; // @[RegisterRouter.scala:87:24] wire _out_T_1342 = out_f_woready_122; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_14 = out_f_woready_122 ? _out_T_1338 : abstractDataMem_14; // @[RegisterRouter.scala:87:24] wire _out_T_1343 = ~out_rimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1344 = ~out_wimask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1345 = ~out_romask_122; // @[RegisterRouter.scala:87:24] wire _out_T_1346 = ~out_womask_122; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_95 = {abstractDataMem_14, _out_prepend_T_95}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1347 = out_prepend_95; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1348 = _out_T_1347; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_96 = _out_T_1348; // @[RegisterRouter.scala:87:24] wire out_rimask_123 = |_out_rimask_T_123; // @[RegisterRouter.scala:87:24] wire out_wimask_123 = &_out_wimask_T_123; // @[RegisterRouter.scala:87:24] wire out_romask_123 = |_out_romask_T_123; // @[RegisterRouter.scala:87:24] wire out_womask_123 = &_out_womask_T_123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_123 = out_rivalid_123 & out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1350 = out_f_rivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_roready_123 = out_roready_123 & out_romask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_15 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1351 = out_f_roready_123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_123 = out_wivalid_123 & out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1352 = out_f_wivalid_123; // @[RegisterRouter.scala:87:24] assign out_f_woready_123 = out_woready_123 & out_womask_123; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_15 = out_f_woready_123; // @[RegisterRouter.scala:87:24] wire _out_T_1353 = out_f_woready_123; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_15 = out_f_woready_123 ? _out_T_1349 : abstractDataMem_15; // @[RegisterRouter.scala:87:24] wire _out_T_1354 = ~out_rimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1355 = ~out_wimask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1356 = ~out_romask_123; // @[RegisterRouter.scala:87:24] wire _out_T_1357 = ~out_womask_123; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_96 = {abstractDataMem_15, _out_prepend_T_96}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1358 = out_prepend_96; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1359 = _out_T_1358; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_7 = _out_T_1359; // @[MuxLiteral.scala:49:48] wire out_rimask_124 = |_out_rimask_T_124; // @[RegisterRouter.scala:87:24] wire out_wimask_124 = &_out_wimask_T_124; // @[RegisterRouter.scala:87:24] wire out_romask_124 = |_out_romask_T_124; // @[RegisterRouter.scala:87:24] wire out_womask_124 = &_out_womask_T_124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_124 = out_rivalid_124 & out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1361 = out_f_rivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_roready_124 = out_roready_124 & out_romask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_28 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1362 = out_f_roready_124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_124 = out_wivalid_124 & out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1363 = out_f_wivalid_124; // @[RegisterRouter.scala:87:24] assign out_f_woready_124 = out_woready_124 & out_womask_124; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_28 = out_f_woready_124; // @[RegisterRouter.scala:87:24] wire _out_T_1364 = out_f_woready_124; // @[RegisterRouter.scala:87:24] assign programBufferNxt_28 = out_f_woready_124 ? _out_T_1360 : programBufferMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1365 = ~out_rimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1366 = ~out_wimask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1367 = ~out_romask_124; // @[RegisterRouter.scala:87:24] wire _out_T_1368 = ~out_womask_124; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1370 = _out_T_1369; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_97 = _out_T_1370; // @[RegisterRouter.scala:87:24] wire out_rimask_125 = |_out_rimask_T_125; // @[RegisterRouter.scala:87:24] wire out_wimask_125 = &_out_wimask_T_125; // @[RegisterRouter.scala:87:24] wire out_romask_125 = |_out_romask_T_125; // @[RegisterRouter.scala:87:24] wire out_womask_125 = &_out_womask_T_125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_125 = out_rivalid_125 & out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1372 = out_f_rivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_roready_125 = out_roready_125 & out_romask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_29 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1373 = out_f_roready_125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_125 = out_wivalid_125 & out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1374 = out_f_wivalid_125; // @[RegisterRouter.scala:87:24] assign out_f_woready_125 = out_woready_125 & out_womask_125; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_29 = out_f_woready_125; // @[RegisterRouter.scala:87:24] wire _out_T_1375 = out_f_woready_125; // @[RegisterRouter.scala:87:24] assign programBufferNxt_29 = out_f_woready_125 ? _out_T_1371 : programBufferMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1376 = ~out_rimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1377 = ~out_wimask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1378 = ~out_romask_125; // @[RegisterRouter.scala:87:24] wire _out_T_1379 = ~out_womask_125; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_97 = {programBufferMem_29, _out_prepend_T_97}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1380 = out_prepend_97; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1381 = _out_T_1380; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_98 = _out_T_1381; // @[RegisterRouter.scala:87:24] wire out_rimask_126 = |_out_rimask_T_126; // @[RegisterRouter.scala:87:24] wire out_wimask_126 = &_out_wimask_T_126; // @[RegisterRouter.scala:87:24] wire out_romask_126 = |_out_romask_T_126; // @[RegisterRouter.scala:87:24] wire out_womask_126 = &_out_womask_T_126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_126 = out_rivalid_126 & out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1383 = out_f_rivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_roready_126 = out_roready_126 & out_romask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_30 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1384 = out_f_roready_126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_126 = out_wivalid_126 & out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1385 = out_f_wivalid_126; // @[RegisterRouter.scala:87:24] assign out_f_woready_126 = out_woready_126 & out_womask_126; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_30 = out_f_woready_126; // @[RegisterRouter.scala:87:24] wire _out_T_1386 = out_f_woready_126; // @[RegisterRouter.scala:87:24] assign programBufferNxt_30 = out_f_woready_126 ? _out_T_1382 : programBufferMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1387 = ~out_rimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1388 = ~out_wimask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1389 = ~out_romask_126; // @[RegisterRouter.scala:87:24] wire _out_T_1390 = ~out_womask_126; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_98 = {programBufferMem_30, _out_prepend_T_98}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1391 = out_prepend_98; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1392 = _out_T_1391; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_99 = _out_T_1392; // @[RegisterRouter.scala:87:24] wire out_rimask_127 = |_out_rimask_T_127; // @[RegisterRouter.scala:87:24] wire out_wimask_127 = &_out_wimask_T_127; // @[RegisterRouter.scala:87:24] wire out_romask_127 = |_out_romask_T_127; // @[RegisterRouter.scala:87:24] wire out_womask_127 = &_out_womask_T_127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_127 = out_rivalid_127 & out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1394 = out_f_rivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_roready_127 = out_roready_127 & out_romask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_31 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1395 = out_f_roready_127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_127 = out_wivalid_127 & out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1396 = out_f_wivalid_127; // @[RegisterRouter.scala:87:24] assign out_f_woready_127 = out_woready_127 & out_womask_127; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_31 = out_f_woready_127; // @[RegisterRouter.scala:87:24] wire _out_T_1397 = out_f_woready_127; // @[RegisterRouter.scala:87:24] assign programBufferNxt_31 = out_f_woready_127 ? _out_T_1393 : programBufferMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1398 = ~out_rimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1399 = ~out_wimask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1400 = ~out_romask_127; // @[RegisterRouter.scala:87:24] wire _out_T_1401 = ~out_womask_127; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_99 = {programBufferMem_31, _out_prepend_T_99}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1402 = out_prepend_99; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1403 = _out_T_1402; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_39 = _out_T_1403; // @[MuxLiteral.scala:49:48] wire out_rimask_128 = |_out_rimask_T_128; // @[RegisterRouter.scala:87:24] wire out_wimask_128 = &_out_wimask_T_128; // @[RegisterRouter.scala:87:24] wire out_romask_128 = |_out_romask_T_128; // @[RegisterRouter.scala:87:24] wire out_womask_128 = &_out_womask_T_128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_128 = out_rivalid_128 & out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1405 = out_f_rivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_roready_128 = out_roready_128 & out_romask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_28 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1406 = out_f_roready_128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_128 = out_wivalid_128 & out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1407 = out_f_wivalid_128; // @[RegisterRouter.scala:87:24] assign out_f_woready_128 = out_woready_128 & out_womask_128; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_28 = out_f_woready_128; // @[RegisterRouter.scala:87:24] wire _out_T_1408 = out_f_woready_128; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_28 = out_f_woready_128 ? _out_T_1404 : abstractDataMem_28; // @[RegisterRouter.scala:87:24] wire _out_T_1409 = ~out_rimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1410 = ~out_wimask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1411 = ~out_romask_128; // @[RegisterRouter.scala:87:24] wire _out_T_1412 = ~out_womask_128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1414 = _out_T_1413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_100 = _out_T_1414; // @[RegisterRouter.scala:87:24] wire out_rimask_129 = |_out_rimask_T_129; // @[RegisterRouter.scala:87:24] wire out_wimask_129 = &_out_wimask_T_129; // @[RegisterRouter.scala:87:24] wire out_romask_129 = |_out_romask_T_129; // @[RegisterRouter.scala:87:24] wire out_womask_129 = &_out_womask_T_129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_129 = out_rivalid_129 & out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1416 = out_f_rivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_roready_129 = out_roready_129 & out_romask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_29 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1417 = out_f_roready_129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_129 = out_wivalid_129 & out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1418 = out_f_wivalid_129; // @[RegisterRouter.scala:87:24] assign out_f_woready_129 = out_woready_129 & out_womask_129; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_29 = out_f_woready_129; // @[RegisterRouter.scala:87:24] wire _out_T_1419 = out_f_woready_129; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_29 = out_f_woready_129 ? _out_T_1415 : abstractDataMem_29; // @[RegisterRouter.scala:87:24] wire _out_T_1420 = ~out_rimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1421 = ~out_wimask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1422 = ~out_romask_129; // @[RegisterRouter.scala:87:24] wire _out_T_1423 = ~out_womask_129; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_100 = {abstractDataMem_29, _out_prepend_T_100}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1424 = out_prepend_100; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1425 = _out_T_1424; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_101 = _out_T_1425; // @[RegisterRouter.scala:87:24] wire out_rimask_130 = |_out_rimask_T_130; // @[RegisterRouter.scala:87:24] wire out_wimask_130 = &_out_wimask_T_130; // @[RegisterRouter.scala:87:24] wire out_romask_130 = |_out_romask_T_130; // @[RegisterRouter.scala:87:24] wire out_womask_130 = &_out_womask_T_130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_130 = out_rivalid_130 & out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1427 = out_f_rivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_roready_130 = out_roready_130 & out_romask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_30 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1428 = out_f_roready_130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_130 = out_wivalid_130 & out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1429 = out_f_wivalid_130; // @[RegisterRouter.scala:87:24] assign out_f_woready_130 = out_woready_130 & out_womask_130; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_30 = out_f_woready_130; // @[RegisterRouter.scala:87:24] wire _out_T_1430 = out_f_woready_130; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_30 = out_f_woready_130 ? _out_T_1426 : abstractDataMem_30; // @[RegisterRouter.scala:87:24] wire _out_T_1431 = ~out_rimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1432 = ~out_wimask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1433 = ~out_romask_130; // @[RegisterRouter.scala:87:24] wire _out_T_1434 = ~out_womask_130; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_101 = {abstractDataMem_30, _out_prepend_T_101}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1435 = out_prepend_101; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1436 = _out_T_1435; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_102 = _out_T_1436; // @[RegisterRouter.scala:87:24] wire out_rimask_131 = |_out_rimask_T_131; // @[RegisterRouter.scala:87:24] wire out_wimask_131 = &_out_wimask_T_131; // @[RegisterRouter.scala:87:24] wire out_romask_131 = |_out_romask_T_131; // @[RegisterRouter.scala:87:24] wire out_womask_131 = &_out_womask_T_131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_131 = out_rivalid_131 & out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1438 = out_f_rivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_roready_131 = out_roready_131 & out_romask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataRdEn_31 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1439 = out_f_roready_131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_131 = out_wivalid_131 & out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1440 = out_f_wivalid_131; // @[RegisterRouter.scala:87:24] assign out_f_woready_131 = out_woready_131 & out_womask_131; // @[RegisterRouter.scala:87:24] assign dmiAbstractDataWrEnMaybe_31 = out_f_woready_131; // @[RegisterRouter.scala:87:24] wire _out_T_1441 = out_f_woready_131; // @[RegisterRouter.scala:87:24] assign abstractDataNxt_31 = out_f_woready_131 ? _out_T_1437 : abstractDataMem_31; // @[RegisterRouter.scala:87:24] wire _out_T_1442 = ~out_rimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1443 = ~out_wimask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1444 = ~out_romask_131; // @[RegisterRouter.scala:87:24] wire _out_T_1445 = ~out_womask_131; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_102 = {abstractDataMem_31, _out_prepend_T_102}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1446 = out_prepend_102; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1447 = _out_T_1446; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_11 = _out_T_1447; // @[MuxLiteral.scala:49:48] wire out_rimask_132 = |_out_rimask_T_132; // @[RegisterRouter.scala:87:24] wire out_wimask_132 = &_out_wimask_T_132; // @[RegisterRouter.scala:87:24] wire out_romask_132 = |_out_romask_T_132; // @[RegisterRouter.scala:87:24] wire out_womask_132 = &_out_womask_T_132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_132 = out_rivalid_132 & out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1449 = out_f_rivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_roready_132 = out_roready_132 & out_romask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_44 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1450 = out_f_roready_132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_132 = out_wivalid_132 & out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1451 = out_f_wivalid_132; // @[RegisterRouter.scala:87:24] assign out_f_woready_132 = out_woready_132 & out_womask_132; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_44 = out_f_woready_132; // @[RegisterRouter.scala:87:24] wire _out_T_1452 = out_f_woready_132; // @[RegisterRouter.scala:87:24] assign programBufferNxt_44 = out_f_woready_132 ? _out_T_1448 : programBufferMem_44; // @[RegisterRouter.scala:87:24] wire _out_T_1453 = ~out_rimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1454 = ~out_wimask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1455 = ~out_romask_132; // @[RegisterRouter.scala:87:24] wire _out_T_1456 = ~out_womask_132; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1458 = _out_T_1457; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_103 = _out_T_1458; // @[RegisterRouter.scala:87:24] wire out_rimask_133 = |_out_rimask_T_133; // @[RegisterRouter.scala:87:24] wire out_wimask_133 = &_out_wimask_T_133; // @[RegisterRouter.scala:87:24] wire out_romask_133 = |_out_romask_T_133; // @[RegisterRouter.scala:87:24] wire out_womask_133 = &_out_womask_T_133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_133 = out_rivalid_133 & out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1460 = out_f_rivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_roready_133 = out_roready_133 & out_romask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_45 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1461 = out_f_roready_133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_133 = out_wivalid_133 & out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1462 = out_f_wivalid_133; // @[RegisterRouter.scala:87:24] assign out_f_woready_133 = out_woready_133 & out_womask_133; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_45 = out_f_woready_133; // @[RegisterRouter.scala:87:24] wire _out_T_1463 = out_f_woready_133; // @[RegisterRouter.scala:87:24] assign programBufferNxt_45 = out_f_woready_133 ? _out_T_1459 : programBufferMem_45; // @[RegisterRouter.scala:87:24] wire _out_T_1464 = ~out_rimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1465 = ~out_wimask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1466 = ~out_romask_133; // @[RegisterRouter.scala:87:24] wire _out_T_1467 = ~out_womask_133; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_103 = {programBufferMem_45, _out_prepend_T_103}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1468 = out_prepend_103; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1469 = _out_T_1468; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_104 = _out_T_1469; // @[RegisterRouter.scala:87:24] wire out_rimask_134 = |_out_rimask_T_134; // @[RegisterRouter.scala:87:24] wire out_wimask_134 = &_out_wimask_T_134; // @[RegisterRouter.scala:87:24] wire out_romask_134 = |_out_romask_T_134; // @[RegisterRouter.scala:87:24] wire out_womask_134 = &_out_womask_T_134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_134 = out_rivalid_134 & out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1471 = out_f_rivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_roready_134 = out_roready_134 & out_romask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_46 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1472 = out_f_roready_134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_134 = out_wivalid_134 & out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1473 = out_f_wivalid_134; // @[RegisterRouter.scala:87:24] assign out_f_woready_134 = out_woready_134 & out_womask_134; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_46 = out_f_woready_134; // @[RegisterRouter.scala:87:24] wire _out_T_1474 = out_f_woready_134; // @[RegisterRouter.scala:87:24] assign programBufferNxt_46 = out_f_woready_134 ? _out_T_1470 : programBufferMem_46; // @[RegisterRouter.scala:87:24] wire _out_T_1475 = ~out_rimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1476 = ~out_wimask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1477 = ~out_romask_134; // @[RegisterRouter.scala:87:24] wire _out_T_1478 = ~out_womask_134; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_104 = {programBufferMem_46, _out_prepend_T_104}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1479 = out_prepend_104; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1480 = _out_T_1479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_105 = _out_T_1480; // @[RegisterRouter.scala:87:24] wire out_rimask_135 = |_out_rimask_T_135; // @[RegisterRouter.scala:87:24] wire out_wimask_135 = &_out_wimask_T_135; // @[RegisterRouter.scala:87:24] wire out_romask_135 = |_out_romask_T_135; // @[RegisterRouter.scala:87:24] wire out_womask_135 = &_out_womask_T_135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_135 = out_rivalid_135 & out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1482 = out_f_rivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_roready_135 = out_roready_135 & out_romask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_47 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1483 = out_f_roready_135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_135 = out_wivalid_135 & out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1484 = out_f_wivalid_135; // @[RegisterRouter.scala:87:24] assign out_f_woready_135 = out_woready_135 & out_womask_135; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_47 = out_f_woready_135; // @[RegisterRouter.scala:87:24] wire _out_T_1485 = out_f_woready_135; // @[RegisterRouter.scala:87:24] assign programBufferNxt_47 = out_f_woready_135 ? _out_T_1481 : programBufferMem_47; // @[RegisterRouter.scala:87:24] wire _out_T_1486 = ~out_rimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1487 = ~out_wimask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1488 = ~out_romask_135; // @[RegisterRouter.scala:87:24] wire _out_T_1489 = ~out_womask_135; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_105 = {programBufferMem_47, _out_prepend_T_105}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1490 = out_prepend_105; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1491 = _out_T_1490; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_43 = _out_T_1491; // @[MuxLiteral.scala:49:48] wire out_rimask_136 = |_out_rimask_T_136; // @[RegisterRouter.scala:87:24] wire out_wimask_136 = &_out_wimask_T_136; // @[RegisterRouter.scala:87:24] wire out_romask_136 = |_out_romask_T_136; // @[RegisterRouter.scala:87:24] wire out_womask_136 = &_out_womask_T_136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_136 = out_rivalid_136 & out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1493 = out_f_rivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_roready_136 = out_roready_136 & out_romask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_32 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1494 = out_f_roready_136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_136 = out_wivalid_136 & out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1495 = out_f_wivalid_136; // @[RegisterRouter.scala:87:24] assign out_f_woready_136 = out_woready_136 & out_womask_136; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_32 = out_f_woready_136; // @[RegisterRouter.scala:87:24] wire _out_T_1496 = out_f_woready_136; // @[RegisterRouter.scala:87:24] assign programBufferNxt_32 = out_f_woready_136 ? _out_T_1492 : programBufferMem_32; // @[RegisterRouter.scala:87:24] wire _out_T_1497 = ~out_rimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1498 = ~out_wimask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1499 = ~out_romask_136; // @[RegisterRouter.scala:87:24] wire _out_T_1500 = ~out_womask_136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1502 = _out_T_1501; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_106 = _out_T_1502; // @[RegisterRouter.scala:87:24] wire out_rimask_137 = |_out_rimask_T_137; // @[RegisterRouter.scala:87:24] wire out_wimask_137 = &_out_wimask_T_137; // @[RegisterRouter.scala:87:24] wire out_romask_137 = |_out_romask_T_137; // @[RegisterRouter.scala:87:24] wire out_womask_137 = &_out_womask_T_137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_137 = out_rivalid_137 & out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1504 = out_f_rivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_roready_137 = out_roready_137 & out_romask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_33 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1505 = out_f_roready_137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_137 = out_wivalid_137 & out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1506 = out_f_wivalid_137; // @[RegisterRouter.scala:87:24] assign out_f_woready_137 = out_woready_137 & out_womask_137; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_33 = out_f_woready_137; // @[RegisterRouter.scala:87:24] wire _out_T_1507 = out_f_woready_137; // @[RegisterRouter.scala:87:24] assign programBufferNxt_33 = out_f_woready_137 ? _out_T_1503 : programBufferMem_33; // @[RegisterRouter.scala:87:24] wire _out_T_1508 = ~out_rimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1509 = ~out_wimask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1510 = ~out_romask_137; // @[RegisterRouter.scala:87:24] wire _out_T_1511 = ~out_womask_137; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_106 = {programBufferMem_33, _out_prepend_T_106}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1512 = out_prepend_106; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1513 = _out_T_1512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_107 = _out_T_1513; // @[RegisterRouter.scala:87:24] wire out_rimask_138 = |_out_rimask_T_138; // @[RegisterRouter.scala:87:24] wire out_wimask_138 = &_out_wimask_T_138; // @[RegisterRouter.scala:87:24] wire out_romask_138 = |_out_romask_T_138; // @[RegisterRouter.scala:87:24] wire out_womask_138 = &_out_womask_T_138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_138 = out_rivalid_138 & out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1515 = out_f_rivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_roready_138 = out_roready_138 & out_romask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_34 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1516 = out_f_roready_138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_138 = out_wivalid_138 & out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1517 = out_f_wivalid_138; // @[RegisterRouter.scala:87:24] assign out_f_woready_138 = out_woready_138 & out_womask_138; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_34 = out_f_woready_138; // @[RegisterRouter.scala:87:24] wire _out_T_1518 = out_f_woready_138; // @[RegisterRouter.scala:87:24] assign programBufferNxt_34 = out_f_woready_138 ? _out_T_1514 : programBufferMem_34; // @[RegisterRouter.scala:87:24] wire _out_T_1519 = ~out_rimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1520 = ~out_wimask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1521 = ~out_romask_138; // @[RegisterRouter.scala:87:24] wire _out_T_1522 = ~out_womask_138; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_107 = {programBufferMem_34, _out_prepend_T_107}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1523 = out_prepend_107; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1524 = _out_T_1523; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_108 = _out_T_1524; // @[RegisterRouter.scala:87:24] wire out_rimask_139 = |_out_rimask_T_139; // @[RegisterRouter.scala:87:24] wire out_wimask_139 = &_out_wimask_T_139; // @[RegisterRouter.scala:87:24] wire out_romask_139 = |_out_romask_T_139; // @[RegisterRouter.scala:87:24] wire out_womask_139 = &_out_womask_T_139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_139 = out_rivalid_139 & out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1526 = out_f_rivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_roready_139 = out_roready_139 & out_romask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_35 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1527 = out_f_roready_139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_139 = out_wivalid_139 & out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1528 = out_f_wivalid_139; // @[RegisterRouter.scala:87:24] assign out_f_woready_139 = out_woready_139 & out_womask_139; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_35 = out_f_woready_139; // @[RegisterRouter.scala:87:24] wire _out_T_1529 = out_f_woready_139; // @[RegisterRouter.scala:87:24] assign programBufferNxt_35 = out_f_woready_139 ? _out_T_1525 : programBufferMem_35; // @[RegisterRouter.scala:87:24] wire _out_T_1530 = ~out_rimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1531 = ~out_wimask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1532 = ~out_romask_139; // @[RegisterRouter.scala:87:24] wire _out_T_1533 = ~out_womask_139; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_108 = {programBufferMem_35, _out_prepend_T_108}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1534 = out_prepend_108; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1535 = _out_T_1534; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_40 = _out_T_1535; // @[MuxLiteral.scala:49:48] wire out_rimask_140 = |_out_rimask_T_140; // @[RegisterRouter.scala:87:24] wire out_wimask_140 = &_out_wimask_T_140; // @[RegisterRouter.scala:87:24] wire out_romask_140 = |_out_romask_T_140; // @[RegisterRouter.scala:87:24] wire out_womask_140 = &_out_womask_T_140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_140 = out_rivalid_140 & out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1537 = out_f_rivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_roready_140 = out_roready_140 & out_romask_140; // @[RegisterRouter.scala:87:24] assign COMMANDRdEn = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1538 = out_f_roready_140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_140 = out_wivalid_140 & out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1539 = out_f_wivalid_140; // @[RegisterRouter.scala:87:24] assign out_f_woready_140 = out_woready_140 & out_womask_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrEnMaybe = out_f_woready_140; // @[RegisterRouter.scala:87:24] wire _out_T_1540 = out_f_woready_140; // @[RegisterRouter.scala:87:24] assign COMMANDWrDataVal = out_f_woready_140 ? _out_T_1536 : 32'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1541 = ~out_rimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1542 = ~out_wimask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1543 = ~out_romask_140; // @[RegisterRouter.scala:87:24] wire _out_T_1544 = ~out_womask_140; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1546 = _out_T_1545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_23 = _out_T_1546; // @[MuxLiteral.scala:49:48] wire out_rimask_141 = |_out_rimask_T_141; // @[RegisterRouter.scala:87:24] wire out_wimask_141 = &_out_wimask_T_141; // @[RegisterRouter.scala:87:24] wire out_romask_141 = |_out_romask_T_141; // @[RegisterRouter.scala:87:24] wire out_womask_141 = &_out_womask_T_141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_141 = out_rivalid_141 & out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1548 = out_f_rivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_roready_141 = out_roready_141 & out_romask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_16 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1549 = out_f_roready_141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_141 = out_wivalid_141 & out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1550 = out_f_wivalid_141; // @[RegisterRouter.scala:87:24] assign out_f_woready_141 = out_woready_141 & out_womask_141; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_16 = out_f_woready_141; // @[RegisterRouter.scala:87:24] wire _out_T_1551 = out_f_woready_141; // @[RegisterRouter.scala:87:24] assign programBufferNxt_16 = out_f_woready_141 ? _out_T_1547 : programBufferMem_16; // @[RegisterRouter.scala:87:24] wire _out_T_1552 = ~out_rimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1553 = ~out_wimask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1554 = ~out_romask_141; // @[RegisterRouter.scala:87:24] wire _out_T_1555 = ~out_womask_141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1557 = _out_T_1556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_109 = _out_T_1557; // @[RegisterRouter.scala:87:24] wire out_rimask_142 = |_out_rimask_T_142; // @[RegisterRouter.scala:87:24] wire out_wimask_142 = &_out_wimask_T_142; // @[RegisterRouter.scala:87:24] wire out_romask_142 = |_out_romask_T_142; // @[RegisterRouter.scala:87:24] wire out_womask_142 = &_out_womask_T_142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_142 = out_rivalid_142 & out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1559 = out_f_rivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_roready_142 = out_roready_142 & out_romask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_17 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1560 = out_f_roready_142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_142 = out_wivalid_142 & out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1561 = out_f_wivalid_142; // @[RegisterRouter.scala:87:24] assign out_f_woready_142 = out_woready_142 & out_womask_142; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_17 = out_f_woready_142; // @[RegisterRouter.scala:87:24] wire _out_T_1562 = out_f_woready_142; // @[RegisterRouter.scala:87:24] assign programBufferNxt_17 = out_f_woready_142 ? _out_T_1558 : programBufferMem_17; // @[RegisterRouter.scala:87:24] wire _out_T_1563 = ~out_rimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1564 = ~out_wimask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1565 = ~out_romask_142; // @[RegisterRouter.scala:87:24] wire _out_T_1566 = ~out_womask_142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_109 = {programBufferMem_17, _out_prepend_T_109}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1567 = out_prepend_109; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1568 = _out_T_1567; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_110 = _out_T_1568; // @[RegisterRouter.scala:87:24] wire out_rimask_143 = |_out_rimask_T_143; // @[RegisterRouter.scala:87:24] wire out_wimask_143 = &_out_wimask_T_143; // @[RegisterRouter.scala:87:24] wire out_romask_143 = |_out_romask_T_143; // @[RegisterRouter.scala:87:24] wire out_womask_143 = &_out_womask_T_143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_143 = out_rivalid_143 & out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1570 = out_f_rivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_roready_143 = out_roready_143 & out_romask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_18 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1571 = out_f_roready_143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_143 = out_wivalid_143 & out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1572 = out_f_wivalid_143; // @[RegisterRouter.scala:87:24] assign out_f_woready_143 = out_woready_143 & out_womask_143; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_18 = out_f_woready_143; // @[RegisterRouter.scala:87:24] wire _out_T_1573 = out_f_woready_143; // @[RegisterRouter.scala:87:24] assign programBufferNxt_18 = out_f_woready_143 ? _out_T_1569 : programBufferMem_18; // @[RegisterRouter.scala:87:24] wire _out_T_1574 = ~out_rimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1575 = ~out_wimask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1576 = ~out_romask_143; // @[RegisterRouter.scala:87:24] wire _out_T_1577 = ~out_womask_143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_110 = {programBufferMem_18, _out_prepend_T_110}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1578 = out_prepend_110; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1579 = _out_T_1578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_111 = _out_T_1579; // @[RegisterRouter.scala:87:24] wire out_rimask_144 = |_out_rimask_T_144; // @[RegisterRouter.scala:87:24] wire out_wimask_144 = &_out_wimask_T_144; // @[RegisterRouter.scala:87:24] wire out_romask_144 = |_out_romask_T_144; // @[RegisterRouter.scala:87:24] wire out_womask_144 = &_out_womask_T_144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_144 = out_rivalid_144 & out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1581 = out_f_rivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_roready_144 = out_roready_144 & out_romask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferRdEn_19 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1582 = out_f_roready_144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_144 = out_wivalid_144 & out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1583 = out_f_wivalid_144; // @[RegisterRouter.scala:87:24] assign out_f_woready_144 = out_woready_144 & out_womask_144; // @[RegisterRouter.scala:87:24] assign dmiProgramBufferWrEnMaybe_19 = out_f_woready_144; // @[RegisterRouter.scala:87:24] wire _out_T_1584 = out_f_woready_144; // @[RegisterRouter.scala:87:24] assign programBufferNxt_19 = out_f_woready_144 ? _out_T_1580 : programBufferMem_19; // @[RegisterRouter.scala:87:24] wire _out_T_1585 = ~out_rimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1586 = ~out_wimask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1587 = ~out_romask_144; // @[RegisterRouter.scala:87:24] wire _out_T_1588 = ~out_womask_144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_111 = {programBufferMem_19, _out_prepend_T_111}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1589 = out_prepend_111; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1590 = _out_T_1589; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_36 = _out_T_1590; // @[MuxLiteral.scala:49:48] wire out_rimask_145 = |_out_rimask_T_145; // @[RegisterRouter.scala:87:24] wire out_wimask_145 = &_out_wimask_T_145; // @[RegisterRouter.scala:87:24] wire out_romask_145 = |_out_romask_T_145; // @[RegisterRouter.scala:87:24] wire out_womask_145 = &_out_womask_T_145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_145 = out_rivalid_145 & out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1592 = out_f_rivalid_145; // @[RegisterRouter.scala:87:24] wire out_f_roready_145 = out_roready_145 & out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1593 = out_f_roready_145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_145 = out_wivalid_145 & out_wimask_145; // @[RegisterRouter.scala:87:24] wire out_f_woready_145 = out_woready_145 & out_womask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1594 = ~out_rimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1595 = ~out_wimask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1596 = ~out_romask_145; // @[RegisterRouter.scala:87:24] wire _out_T_1597 = ~out_womask_145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1599 = _out_T_1598; // @[RegisterRouter.scala:87:24] wire [31:0] _out_out_bits_data_WIRE_1_19 = _out_T_1599; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_lo = {out_iindex_lo_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi = {_out_iindex_T_5, _out_iindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex_hi = {out_iindex_hi_hi, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_iindex = {out_iindex_hi, out_iindex_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_lo = {out_oindex_lo_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi = {_out_oindex_T_5, _out_oindex_T_4}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex_hi = {out_oindex_hi_hi, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [5:0] out_oindex = {out_oindex_hi, out_oindex_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_frontSel_T = 64'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire out_frontSel_8 = _out_frontSel_T[8]; // @[OneHot.scala:58:35] wire out_frontSel_9 = _out_frontSel_T[9]; // @[OneHot.scala:58:35] wire out_frontSel_10 = _out_frontSel_T[10]; // @[OneHot.scala:58:35] wire out_frontSel_11 = _out_frontSel_T[11]; // @[OneHot.scala:58:35] wire out_frontSel_12 = _out_frontSel_T[12]; // @[OneHot.scala:58:35] wire out_frontSel_13 = _out_frontSel_T[13]; // @[OneHot.scala:58:35] wire out_frontSel_14 = _out_frontSel_T[14]; // @[OneHot.scala:58:35] wire out_frontSel_15 = _out_frontSel_T[15]; // @[OneHot.scala:58:35] wire out_frontSel_16 = _out_frontSel_T[16]; // @[OneHot.scala:58:35] wire out_frontSel_17 = _out_frontSel_T[17]; // @[OneHot.scala:58:35] wire out_frontSel_18 = _out_frontSel_T[18]; // @[OneHot.scala:58:35] wire out_frontSel_19 = _out_frontSel_T[19]; // @[OneHot.scala:58:35] wire out_frontSel_20 = _out_frontSel_T[20]; // @[OneHot.scala:58:35] wire out_frontSel_21 = _out_frontSel_T[21]; // @[OneHot.scala:58:35] wire out_frontSel_22 = _out_frontSel_T[22]; // @[OneHot.scala:58:35] wire out_frontSel_23 = _out_frontSel_T[23]; // @[OneHot.scala:58:35] wire out_frontSel_24 = _out_frontSel_T[24]; // @[OneHot.scala:58:35] wire out_frontSel_25 = _out_frontSel_T[25]; // @[OneHot.scala:58:35] wire out_frontSel_26 = _out_frontSel_T[26]; // @[OneHot.scala:58:35] wire out_frontSel_27 = _out_frontSel_T[27]; // @[OneHot.scala:58:35] wire out_frontSel_28 = _out_frontSel_T[28]; // @[OneHot.scala:58:35] wire out_frontSel_29 = _out_frontSel_T[29]; // @[OneHot.scala:58:35] wire out_frontSel_30 = _out_frontSel_T[30]; // @[OneHot.scala:58:35] wire out_frontSel_31 = _out_frontSel_T[31]; // @[OneHot.scala:58:35] wire out_frontSel_32 = _out_frontSel_T[32]; // @[OneHot.scala:58:35] wire out_frontSel_33 = _out_frontSel_T[33]; // @[OneHot.scala:58:35] wire out_frontSel_34 = _out_frontSel_T[34]; // @[OneHot.scala:58:35] wire out_frontSel_35 = _out_frontSel_T[35]; // @[OneHot.scala:58:35] wire out_frontSel_36 = _out_frontSel_T[36]; // @[OneHot.scala:58:35] wire out_frontSel_37 = _out_frontSel_T[37]; // @[OneHot.scala:58:35] wire out_frontSel_38 = _out_frontSel_T[38]; // @[OneHot.scala:58:35] wire out_frontSel_39 = _out_frontSel_T[39]; // @[OneHot.scala:58:35] wire out_frontSel_40 = _out_frontSel_T[40]; // @[OneHot.scala:58:35] wire out_frontSel_41 = _out_frontSel_T[41]; // @[OneHot.scala:58:35] wire out_frontSel_42 = _out_frontSel_T[42]; // @[OneHot.scala:58:35] wire out_frontSel_43 = _out_frontSel_T[43]; // @[OneHot.scala:58:35] wire out_frontSel_44 = _out_frontSel_T[44]; // @[OneHot.scala:58:35] wire out_frontSel_45 = _out_frontSel_T[45]; // @[OneHot.scala:58:35] wire out_frontSel_46 = _out_frontSel_T[46]; // @[OneHot.scala:58:35] wire out_frontSel_47 = _out_frontSel_T[47]; // @[OneHot.scala:58:35] wire out_frontSel_48 = _out_frontSel_T[48]; // @[OneHot.scala:58:35] wire out_frontSel_49 = _out_frontSel_T[49]; // @[OneHot.scala:58:35] wire out_frontSel_50 = _out_frontSel_T[50]; // @[OneHot.scala:58:35] wire out_frontSel_51 = _out_frontSel_T[51]; // @[OneHot.scala:58:35] wire out_frontSel_52 = _out_frontSel_T[52]; // @[OneHot.scala:58:35] wire out_frontSel_53 = _out_frontSel_T[53]; // @[OneHot.scala:58:35] wire out_frontSel_54 = _out_frontSel_T[54]; // @[OneHot.scala:58:35] wire out_frontSel_55 = _out_frontSel_T[55]; // @[OneHot.scala:58:35] wire out_frontSel_56 = _out_frontSel_T[56]; // @[OneHot.scala:58:35] wire out_frontSel_57 = _out_frontSel_T[57]; // @[OneHot.scala:58:35] wire out_frontSel_58 = _out_frontSel_T[58]; // @[OneHot.scala:58:35] wire out_frontSel_59 = _out_frontSel_T[59]; // @[OneHot.scala:58:35] wire out_frontSel_60 = _out_frontSel_T[60]; // @[OneHot.scala:58:35] wire out_frontSel_61 = _out_frontSel_T[61]; // @[OneHot.scala:58:35] wire out_frontSel_62 = _out_frontSel_T[62]; // @[OneHot.scala:58:35] wire out_frontSel_63 = _out_frontSel_T[63]; // @[OneHot.scala:58:35] wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire out_backSel_8 = _out_backSel_T[8]; // @[OneHot.scala:58:35] wire out_backSel_9 = _out_backSel_T[9]; // @[OneHot.scala:58:35] wire out_backSel_10 = _out_backSel_T[10]; // @[OneHot.scala:58:35] wire out_backSel_11 = _out_backSel_T[11]; // @[OneHot.scala:58:35] wire out_backSel_12 = _out_backSel_T[12]; // @[OneHot.scala:58:35] wire out_backSel_13 = _out_backSel_T[13]; // @[OneHot.scala:58:35] wire out_backSel_14 = _out_backSel_T[14]; // @[OneHot.scala:58:35] wire out_backSel_15 = _out_backSel_T[15]; // @[OneHot.scala:58:35] wire out_backSel_16 = _out_backSel_T[16]; // @[OneHot.scala:58:35] wire out_backSel_17 = _out_backSel_T[17]; // @[OneHot.scala:58:35] wire out_backSel_18 = _out_backSel_T[18]; // @[OneHot.scala:58:35] wire out_backSel_19 = _out_backSel_T[19]; // @[OneHot.scala:58:35] wire out_backSel_20 = _out_backSel_T[20]; // @[OneHot.scala:58:35] wire out_backSel_21 = _out_backSel_T[21]; // @[OneHot.scala:58:35] wire out_backSel_22 = _out_backSel_T[22]; // @[OneHot.scala:58:35] wire out_backSel_23 = _out_backSel_T[23]; // @[OneHot.scala:58:35] wire out_backSel_24 = _out_backSel_T[24]; // @[OneHot.scala:58:35] wire out_backSel_25 = _out_backSel_T[25]; // @[OneHot.scala:58:35] wire out_backSel_26 = _out_backSel_T[26]; // @[OneHot.scala:58:35] wire out_backSel_27 = _out_backSel_T[27]; // @[OneHot.scala:58:35] wire out_backSel_28 = _out_backSel_T[28]; // @[OneHot.scala:58:35] wire out_backSel_29 = _out_backSel_T[29]; // @[OneHot.scala:58:35] wire out_backSel_30 = _out_backSel_T[30]; // @[OneHot.scala:58:35] wire out_backSel_31 = _out_backSel_T[31]; // @[OneHot.scala:58:35] wire out_backSel_32 = _out_backSel_T[32]; // @[OneHot.scala:58:35] wire out_backSel_33 = _out_backSel_T[33]; // @[OneHot.scala:58:35] wire out_backSel_34 = _out_backSel_T[34]; // @[OneHot.scala:58:35] wire out_backSel_35 = _out_backSel_T[35]; // @[OneHot.scala:58:35] wire out_backSel_36 = _out_backSel_T[36]; // @[OneHot.scala:58:35] wire out_backSel_37 = _out_backSel_T[37]; // @[OneHot.scala:58:35] wire out_backSel_38 = _out_backSel_T[38]; // @[OneHot.scala:58:35] wire out_backSel_39 = _out_backSel_T[39]; // @[OneHot.scala:58:35] wire out_backSel_40 = _out_backSel_T[40]; // @[OneHot.scala:58:35] wire out_backSel_41 = _out_backSel_T[41]; // @[OneHot.scala:58:35] wire out_backSel_42 = _out_backSel_T[42]; // @[OneHot.scala:58:35] wire out_backSel_43 = _out_backSel_T[43]; // @[OneHot.scala:58:35] wire out_backSel_44 = _out_backSel_T[44]; // @[OneHot.scala:58:35] wire out_backSel_45 = _out_backSel_T[45]; // @[OneHot.scala:58:35] wire out_backSel_46 = _out_backSel_T[46]; // @[OneHot.scala:58:35] wire out_backSel_47 = _out_backSel_T[47]; // @[OneHot.scala:58:35] wire out_backSel_48 = _out_backSel_T[48]; // @[OneHot.scala:58:35] wire out_backSel_49 = _out_backSel_T[49]; // @[OneHot.scala:58:35] wire out_backSel_50 = _out_backSel_T[50]; // @[OneHot.scala:58:35] wire out_backSel_51 = _out_backSel_T[51]; // @[OneHot.scala:58:35] wire out_backSel_52 = _out_backSel_T[52]; // @[OneHot.scala:58:35] wire out_backSel_53 = _out_backSel_T[53]; // @[OneHot.scala:58:35] wire out_backSel_54 = _out_backSel_T[54]; // @[OneHot.scala:58:35] wire out_backSel_55 = _out_backSel_T[55]; // @[OneHot.scala:58:35] wire out_backSel_56 = _out_backSel_T[56]; // @[OneHot.scala:58:35] wire out_backSel_57 = _out_backSel_T[57]; // @[OneHot.scala:58:35] wire out_backSel_58 = _out_backSel_T[58]; // @[OneHot.scala:58:35] wire out_backSel_59 = _out_backSel_T[59]; // @[OneHot.scala:58:35] wire out_backSel_60 = _out_backSel_T[60]; // @[OneHot.scala:58:35] wire out_backSel_61 = _out_backSel_T[61]; // @[OneHot.scala:58:35] wire out_backSel_62 = _out_backSel_T[62]; // @[OneHot.scala:58:35] wire out_backSel_63 = _out_backSel_T[63]; // @[OneHot.scala:58:35] wire _GEN_11 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_rivalid_81 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_21 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_22 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_23 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_24 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_rivalid_64 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_65 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_66 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_67 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_rivalid_120 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_121 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_122 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_123 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = _out_rifireMux_T_1 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_35 = _out_rifireMux_T_34 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_18 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_19 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_rivalid_20 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_36 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_38 = _out_rifireMux_T_1 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_39 = _out_rifireMux_T_38 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_42 = _out_rifireMux_T_1 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_43 = _out_rifireMux_T_42 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_rivalid_29 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_30 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_31 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_rivalid_32 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_44 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_46 = _out_rifireMux_T_1 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_47 = _out_rifireMux_T_46 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_rivalid_128 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_129 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_130 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_rivalid_131 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_50 = _out_rifireMux_T_1 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_51 = _out_rifireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_54 = _out_rifireMux_T_1 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_55 = _out_rifireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_58 = _out_rifireMux_T_1 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_59 = _out_rifireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_62 = _out_rifireMux_T_1 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_63 = _out_rifireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = _out_rifireMux_T_1 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_67 = _out_rifireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_70 = _out_rifireMux_T_1 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_71 = _out_rifireMux_T_70 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_rivalid_82 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_83 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_84 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_85 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_86 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_87 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_88 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_89 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_90 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_91 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_92 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_93 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_94 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_95 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_96 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_97 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_98 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_99 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_rivalid_100 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_72 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_74 = _out_rifireMux_T_1 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_75 = _out_rifireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_78 = _out_rifireMux_T_1 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_79 = _out_rifireMux_T_78 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_rivalid_145 = _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_80 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_82 = _out_rifireMux_T_1 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_83 = _out_rifireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_86 = _out_rifireMux_T_1 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_87 = _out_rifireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_90 = _out_rifireMux_T_1 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_91 = _out_rifireMux_T_90 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_rivalid_109 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_110 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_111 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_112 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_113 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_114 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_rivalid_115 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_92 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_94 = _out_rifireMux_T_1 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_95 = _out_rifireMux_T_94 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_rivalid_140 = _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_96 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_98 = _out_rifireMux_T_1 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_99 = _out_rifireMux_T_98 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_rivalid_52 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_53 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_rivalid_54 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_100 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_102 = _out_rifireMux_T_1 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_103 = _out_rifireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_106 = _out_rifireMux_T_1 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_107 = _out_rifireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_110 = _out_rifireMux_T_1 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_111 = _out_rifireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_114 = _out_rifireMux_T_1 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_115 = _out_rifireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_118 = _out_rifireMux_T_1 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_119 = _out_rifireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_122 = _out_rifireMux_T_1 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_123 = _out_rifireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_126 = _out_rifireMux_T_1 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_127 = _out_rifireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_130 = _out_rifireMux_T_1 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_131 = _out_rifireMux_T_130 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_rivalid_101 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_102 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_103 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_rivalid_104 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_132 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_134 = _out_rifireMux_T_1 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_135 = _out_rifireMux_T_134 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_rivalid_73 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_74 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_75 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_rivalid_76 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_136 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_138 = _out_rifireMux_T_1 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_139 = _out_rifireMux_T_138 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_rivalid_105 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_106 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_107 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_rivalid_108 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_140 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_142 = _out_rifireMux_T_1 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_143 = _out_rifireMux_T_142 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_144 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_146 = _out_rifireMux_T_1 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_147 = _out_rifireMux_T_146 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_rivalid_141 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_142 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_143 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_rivalid_144 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_148 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_150 = _out_rifireMux_T_1 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_151 = _out_rifireMux_T_150 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_rivalid_55 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_56 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_57 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_rivalid_58 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_152 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_154 = _out_rifireMux_T_1 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_155 = _out_rifireMux_T_154 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_rivalid_69 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_70 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_71 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_rivalid_72 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_156 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_158 = _out_rifireMux_T_1 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_159 = _out_rifireMux_T_158 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_rivalid_124 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_125 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_126 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_rivalid_127 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_160 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_162 = _out_rifireMux_T_1 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_163 = _out_rifireMux_T_162 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_rivalid_136 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_137 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_138 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_rivalid_139 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_164 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_166 = _out_rifireMux_T_1 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_167 = _out_rifireMux_T_166 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_168 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_170 = _out_rifireMux_T_1 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_171 = _out_rifireMux_T_170 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_rivalid_48 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_49 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_50 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_rivalid_51 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_172 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_174 = _out_rifireMux_T_1 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_175 = _out_rifireMux_T_174 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_rivalid_132 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_133 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_134 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_rivalid_135 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_176 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_178 = _out_rifireMux_T_1 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_179 = _out_rifireMux_T_178 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_rivalid_116 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_117 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_118 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_rivalid_119 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_180 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_182 = _out_rifireMux_T_1 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_183 = _out_rifireMux_T_182 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_rivalid_77 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_78 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_79 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_rivalid_80 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_184 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_186 = _out_rifireMux_T_1 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_187 = _out_rifireMux_T_186 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_rivalid_59 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_60 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_61 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_rivalid_62 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_188 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_190 = _out_rifireMux_T_1 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_191 = _out_rifireMux_T_190 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_rivalid_25 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_26 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_27 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_rivalid_28 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_192 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_194 = _out_rifireMux_T_1 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_195 = _out_rifireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_198 = _out_rifireMux_T_1 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_199 = _out_rifireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_202 = _out_rifireMux_T_1 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_203 = _out_rifireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_206 = _out_rifireMux_T_1 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_207 = _out_rifireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_210 = _out_rifireMux_T_1 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_211 = _out_rifireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_214 = _out_rifireMux_T_1 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_215 = _out_rifireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_218 = _out_rifireMux_T_1 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_219 = _out_rifireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_222 = _out_rifireMux_T_1 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_223 = _out_rifireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_226 = _out_rifireMux_T_1 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_227 = _out_rifireMux_T_226 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_rivalid_33 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_34 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_35 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_36 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_37 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_38 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_39 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_40 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_41 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_42 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_43 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_44 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_45 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_46 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_rivalid_47 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_228 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_230 = _out_rifireMux_T_1 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_231 = _out_rifireMux_T_230 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_rivalid_63 = _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_232 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_234 = _out_rifireMux_T_1 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_235 = _out_rifireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_238 = _out_rifireMux_T_1 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_239 = _out_rifireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_242 = _out_rifireMux_T_1 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_243 = _out_rifireMux_T_242 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_rivalid_68 = _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_244 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_246 = _out_rifireMux_T_1 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_247 = _out_rifireMux_T_246 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_248 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_250 = _out_rifireMux_T_1 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_251 = _out_rifireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_254 = _out_rifireMux_T_1 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_255 = _out_rifireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_81 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_21 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_22 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_23 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_24 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_30; // @[RegisterRouter.scala:87:24] assign out_wivalid_64 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_65 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_66 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_67 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_52; // @[RegisterRouter.scala:87:24] assign out_wivalid_120 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_121 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_122 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_123 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = ~_out_T_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = _out_wifireMux_T_2 & out_frontSel_8; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_36 = _out_wifireMux_T_35 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_18 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_19 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_20 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_37 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_39 = _out_wifireMux_T_2 & out_frontSel_9; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_40 = _out_wifireMux_T_39 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_43 = _out_wifireMux_T_2 & out_frontSel_10; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_44 = _out_wifireMux_T_43 & _out_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_29 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_30 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_31 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_32 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_45 = ~_out_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_47 = _out_wifireMux_T_2 & out_frontSel_11; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_48 = _out_wifireMux_T_47 & _out_T_56; // @[RegisterRouter.scala:87:24] assign out_wivalid_128 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_129 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_130 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_131 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = ~_out_T_56; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_51 = _out_wifireMux_T_2 & out_frontSel_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_52 = _out_wifireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_55 = _out_wifireMux_T_2 & out_frontSel_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_56 = _out_wifireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_59 = _out_wifireMux_T_2 & out_frontSel_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_60 = _out_wifireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_63 = _out_wifireMux_T_2 & out_frontSel_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_64 = _out_wifireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = _out_wifireMux_T_2 & out_frontSel_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_68 = _out_wifireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_71 = _out_wifireMux_T_2 & out_frontSel_17; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_72 = _out_wifireMux_T_71 & _out_T_42; // @[RegisterRouter.scala:87:24] assign out_wivalid_82 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_83 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_84 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_85 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_86 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_87 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_88 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_89 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_90 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_91 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_92 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_93 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_94 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_95 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_96 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_97 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_98 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_99 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_wivalid_100 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_73 = ~_out_T_42; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_75 = _out_wifireMux_T_2 & out_frontSel_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_76 = _out_wifireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_79 = _out_wifireMux_T_2 & out_frontSel_19; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_80 = _out_wifireMux_T_79 & _out_T_66; // @[RegisterRouter.scala:87:24] assign out_wivalid_145 = _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_81 = ~_out_T_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_83 = _out_wifireMux_T_2 & out_frontSel_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_84 = _out_wifireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_87 = _out_wifireMux_T_2 & out_frontSel_21; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_88 = _out_wifireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_91 = _out_wifireMux_T_2 & out_frontSel_22; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_92 = _out_wifireMux_T_91 & _out_T_48; // @[RegisterRouter.scala:87:24] assign out_wivalid_109 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_110 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_111 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_112 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_113 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_114 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_wivalid_115 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_93 = ~_out_T_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_95 = _out_wifireMux_T_2 & out_frontSel_23; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_96 = _out_wifireMux_T_95 & _out_T_62; // @[RegisterRouter.scala:87:24] assign out_wivalid_140 = _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_97 = ~_out_T_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_99 = _out_wifireMux_T_2 & out_frontSel_24; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_100 = _out_wifireMux_T_99 & _out_T_22; // @[RegisterRouter.scala:87:24] assign out_wivalid_52 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_53 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_wivalid_54 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_101 = ~_out_T_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_103 = _out_wifireMux_T_2 & out_frontSel_25; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_104 = _out_wifireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_107 = _out_wifireMux_T_2 & out_frontSel_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_108 = _out_wifireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_111 = _out_wifireMux_T_2 & out_frontSel_27; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_112 = _out_wifireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_115 = _out_wifireMux_T_2 & out_frontSel_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_116 = _out_wifireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_119 = _out_wifireMux_T_2 & out_frontSel_29; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_120 = _out_wifireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_123 = _out_wifireMux_T_2 & out_frontSel_30; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_124 = _out_wifireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_127 = _out_wifireMux_T_2 & out_frontSel_31; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_128 = _out_wifireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_131 = _out_wifireMux_T_2 & out_frontSel_32; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_132 = _out_wifireMux_T_131 & _out_T_44; // @[RegisterRouter.scala:87:24] assign out_wivalid_101 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_102 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_103 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_wivalid_104 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_133 = ~_out_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_135 = _out_wifireMux_T_2 & out_frontSel_33; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_136 = _out_wifireMux_T_135 & _out_T_36; // @[RegisterRouter.scala:87:24] assign out_wivalid_73 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_74 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_75 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_wivalid_76 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_137 = ~_out_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_139 = _out_wifireMux_T_2 & out_frontSel_34; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_140 = _out_wifireMux_T_139 & _out_T_46; // @[RegisterRouter.scala:87:24] assign out_wivalid_105 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_106 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_107 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_wivalid_108 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_141 = ~_out_T_46; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_143 = _out_wifireMux_T_2 & out_frontSel_35; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_144 = _out_wifireMux_T_143 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_145 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_147 = _out_wifireMux_T_2 & out_frontSel_36; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_148 = _out_wifireMux_T_147 & _out_T_64; // @[RegisterRouter.scala:87:24] assign out_wivalid_141 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_142 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_143 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_wivalid_144 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_149 = ~_out_T_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_151 = _out_wifireMux_T_2 & out_frontSel_37; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_152 = _out_wifireMux_T_151 & _out_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_55 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_56 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_57 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_wivalid_58 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_153 = ~_out_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_155 = _out_wifireMux_T_2 & out_frontSel_38; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_156 = _out_wifireMux_T_155 & _out_T_34; // @[RegisterRouter.scala:87:24] assign out_wivalid_69 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_70 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_71 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_wivalid_72 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_157 = ~_out_T_34; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_159 = _out_wifireMux_T_2 & out_frontSel_39; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_160 = _out_wifireMux_T_159 & _out_T_54; // @[RegisterRouter.scala:87:24] assign out_wivalid_124 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_125 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_126 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_wivalid_127 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_161 = ~_out_T_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_163 = _out_wifireMux_T_2 & out_frontSel_40; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_164 = _out_wifireMux_T_163 & _out_T_60; // @[RegisterRouter.scala:87:24] assign out_wivalid_136 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_137 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_138 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_wivalid_139 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_165 = ~_out_T_60; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_167 = _out_wifireMux_T_2 & out_frontSel_41; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_168 = _out_wifireMux_T_167 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_169 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_171 = _out_wifireMux_T_2 & out_frontSel_42; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_172 = _out_wifireMux_T_171 & _out_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_48 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_49 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_50 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_wivalid_51 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_173 = ~_out_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_175 = _out_wifireMux_T_2 & out_frontSel_43; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_176 = _out_wifireMux_T_175 & _out_T_58; // @[RegisterRouter.scala:87:24] assign out_wivalid_132 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_133 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_134 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_wivalid_135 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_177 = ~_out_T_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_179 = _out_wifireMux_T_2 & out_frontSel_44; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_180 = _out_wifireMux_T_179 & _out_T_50; // @[RegisterRouter.scala:87:24] assign out_wivalid_116 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_117 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_118 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_wivalid_119 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_181 = ~_out_T_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_183 = _out_wifireMux_T_2 & out_frontSel_45; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_184 = _out_wifireMux_T_183 & _out_T_38; // @[RegisterRouter.scala:87:24] assign out_wivalid_77 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_78 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_79 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_wivalid_80 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_185 = ~_out_T_38; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_187 = _out_wifireMux_T_2 & out_frontSel_46; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_188 = _out_wifireMux_T_187 & _out_T_26; // @[RegisterRouter.scala:87:24] assign out_wivalid_59 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_60 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_61 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_wivalid_62 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_189 = ~_out_T_26; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_191 = _out_wifireMux_T_2 & out_frontSel_47; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_192 = _out_wifireMux_T_191 & _out_T_14; // @[RegisterRouter.scala:87:24] assign out_wivalid_25 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_26 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_27 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_wivalid_28 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_193 = ~_out_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_195 = _out_wifireMux_T_2 & out_frontSel_48; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_196 = _out_wifireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_199 = _out_wifireMux_T_2 & out_frontSel_49; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_200 = _out_wifireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_203 = _out_wifireMux_T_2 & out_frontSel_50; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_204 = _out_wifireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_207 = _out_wifireMux_T_2 & out_frontSel_51; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_208 = _out_wifireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_211 = _out_wifireMux_T_2 & out_frontSel_52; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_212 = _out_wifireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_215 = _out_wifireMux_T_2 & out_frontSel_53; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_216 = _out_wifireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_219 = _out_wifireMux_T_2 & out_frontSel_54; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_220 = _out_wifireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_223 = _out_wifireMux_T_2 & out_frontSel_55; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_224 = _out_wifireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_227 = _out_wifireMux_T_2 & out_frontSel_56; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_228 = _out_wifireMux_T_227 & _out_T_18; // @[RegisterRouter.scala:87:24] assign out_wivalid_33 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_34 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_35 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_36 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_37 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_38 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_39 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_40 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_41 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_42 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_43 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_44 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_45 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_46 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_wivalid_47 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_229 = ~_out_T_18; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_231 = _out_wifireMux_T_2 & out_frontSel_57; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_232 = _out_wifireMux_T_231 & _out_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_63 = _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_233 = ~_out_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_235 = _out_wifireMux_T_2 & out_frontSel_58; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_236 = _out_wifireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_239 = _out_wifireMux_T_2 & out_frontSel_59; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_240 = _out_wifireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_243 = _out_wifireMux_T_2 & out_frontSel_60; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_244 = _out_wifireMux_T_243 & _out_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_68 = _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_245 = ~_out_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_247 = _out_wifireMux_T_2 & out_frontSel_61; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_248 = _out_wifireMux_T_247 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_249 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_251 = _out_wifireMux_T_2 & out_frontSel_62; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_252 = _out_wifireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_255 = _out_wifireMux_T_2 & out_frontSel_63; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_256 = _out_wifireMux_T_255; // @[RegisterRouter.scala:87:24] wire _GEN_12 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_roready_81 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_21 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_22 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_23 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_24 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_64 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_65 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_66 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_67 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_roready_120 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_121 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_122 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_123 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = _out_rofireMux_T_1 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_35 = _out_rofireMux_T_34 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_18 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_19 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_36 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_38 = _out_rofireMux_T_1 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_39 = _out_rofireMux_T_38 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_42 = _out_rofireMux_T_1 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_43 = _out_rofireMux_T_42 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_roready_29 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_30 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_31 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_44 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_46 = _out_rofireMux_T_1 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_47 = _out_rofireMux_T_46 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_roready_128 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_129 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_130 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_131 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_50 = _out_rofireMux_T_1 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_51 = _out_rofireMux_T_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_54 = _out_rofireMux_T_1 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_55 = _out_rofireMux_T_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_58 = _out_rofireMux_T_1 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_59 = _out_rofireMux_T_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_62 = _out_rofireMux_T_1 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_63 = _out_rofireMux_T_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = _out_rofireMux_T_1 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_67 = _out_rofireMux_T_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_70 = _out_rofireMux_T_1 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_71 = _out_rofireMux_T_70 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_roready_82 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_83 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_84 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_85 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_86 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_87 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_88 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_89 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_90 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_91 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_92 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_93 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_94 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_95 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_96 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_97 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_98 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_99 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] assign out_roready_100 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_72 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_74 = _out_rofireMux_T_1 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_75 = _out_rofireMux_T_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_78 = _out_rofireMux_T_1 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_79 = _out_rofireMux_T_78 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_roready_145 = _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_80 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_82 = _out_rofireMux_T_1 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_83 = _out_rofireMux_T_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_86 = _out_rofireMux_T_1 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_87 = _out_rofireMux_T_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_90 = _out_rofireMux_T_1 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_91 = _out_rofireMux_T_90 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_roready_109 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_110 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_111 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_112 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_113 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_114 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] assign out_roready_115 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_92 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_94 = _out_rofireMux_T_1 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_95 = _out_rofireMux_T_94 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_roready_140 = _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_96 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_98 = _out_rofireMux_T_1 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_99 = _out_rofireMux_T_98 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_52 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_53 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] assign out_roready_54 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_100 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_102 = _out_rofireMux_T_1 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_103 = _out_rofireMux_T_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_106 = _out_rofireMux_T_1 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_107 = _out_rofireMux_T_106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_110 = _out_rofireMux_T_1 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_111 = _out_rofireMux_T_110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_114 = _out_rofireMux_T_1 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_115 = _out_rofireMux_T_114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_118 = _out_rofireMux_T_1 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_119 = _out_rofireMux_T_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_122 = _out_rofireMux_T_1 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_123 = _out_rofireMux_T_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_126 = _out_rofireMux_T_1 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_127 = _out_rofireMux_T_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_130 = _out_rofireMux_T_1 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_131 = _out_rofireMux_T_130 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_roready_101 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_102 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_103 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] assign out_roready_104 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_132 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_134 = _out_rofireMux_T_1 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_135 = _out_rofireMux_T_134 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_roready_73 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_74 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_75 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] assign out_roready_76 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_136 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_138 = _out_rofireMux_T_1 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_139 = _out_rofireMux_T_138 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_roready_105 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_106 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_107 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] assign out_roready_108 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_140 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_142 = _out_rofireMux_T_1 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_143 = _out_rofireMux_T_142 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_144 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_146 = _out_rofireMux_T_1 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_147 = _out_rofireMux_T_146 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_roready_141 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_142 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_143 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] assign out_roready_144 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_148 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_150 = _out_rofireMux_T_1 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_151 = _out_rofireMux_T_150 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_roready_55 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_56 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_57 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] assign out_roready_58 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_152 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_154 = _out_rofireMux_T_1 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_155 = _out_rofireMux_T_154 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_roready_69 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_70 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_71 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] assign out_roready_72 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_156 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_158 = _out_rofireMux_T_1 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_159 = _out_rofireMux_T_158 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_roready_124 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_125 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_126 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] assign out_roready_127 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_160 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_162 = _out_rofireMux_T_1 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_163 = _out_rofireMux_T_162 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_roready_136 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_137 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_138 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] assign out_roready_139 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_164 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_166 = _out_rofireMux_T_1 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_167 = _out_rofireMux_T_166 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_168 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_170 = _out_rofireMux_T_1 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_171 = _out_rofireMux_T_170 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_roready_48 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_49 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_50 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] assign out_roready_51 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_172 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_174 = _out_rofireMux_T_1 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_175 = _out_rofireMux_T_174 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_roready_132 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_133 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_134 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] assign out_roready_135 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_176 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_178 = _out_rofireMux_T_1 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_179 = _out_rofireMux_T_178 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_roready_116 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_117 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_118 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] assign out_roready_119 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_180 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_182 = _out_rofireMux_T_1 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_183 = _out_rofireMux_T_182 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_roready_77 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_78 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_79 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] assign out_roready_80 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_184 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_186 = _out_rofireMux_T_1 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_187 = _out_rofireMux_T_186 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_59 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_60 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_61 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] assign out_roready_62 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_188 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_190 = _out_rofireMux_T_1 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_191 = _out_rofireMux_T_190 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_25 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_26 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_27 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_192 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_194 = _out_rofireMux_T_1 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_195 = _out_rofireMux_T_194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_198 = _out_rofireMux_T_1 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_199 = _out_rofireMux_T_198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_202 = _out_rofireMux_T_1 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_203 = _out_rofireMux_T_202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_206 = _out_rofireMux_T_1 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_207 = _out_rofireMux_T_206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_210 = _out_rofireMux_T_1 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_211 = _out_rofireMux_T_210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_214 = _out_rofireMux_T_1 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_215 = _out_rofireMux_T_214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_218 = _out_rofireMux_T_1 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_219 = _out_rofireMux_T_218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_222 = _out_rofireMux_T_1 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_223 = _out_rofireMux_T_222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_226 = _out_rofireMux_T_1 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_227 = _out_rofireMux_T_226 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_33 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_34 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_35 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_36 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_37 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_38 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_39 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_40 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_41 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_42 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_43 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_44 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_45 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_46 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] assign out_roready_47 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_228 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_230 = _out_rofireMux_T_1 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_231 = _out_rofireMux_T_230 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_roready_63 = _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_232 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_234 = _out_rofireMux_T_1 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_235 = _out_rofireMux_T_234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_238 = _out_rofireMux_T_1 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_239 = _out_rofireMux_T_238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_242 = _out_rofireMux_T_1 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_243 = _out_rofireMux_T_242 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_roready_68 = _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_244 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_246 = _out_rofireMux_T_1 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_247 = _out_rofireMux_T_246 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_248 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_250 = _out_rofireMux_T_1 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_251 = _out_rofireMux_T_250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_254 = _out_rofireMux_T_1 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_255 = _out_rofireMux_T_254; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_41; // @[RegisterRouter.scala:87:24] assign out_woready_81 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_41; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_21 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_22 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_23 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_24 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_31; // @[RegisterRouter.scala:87:24] assign out_woready_64 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_65 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_66 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_67 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_53; // @[RegisterRouter.scala:87:24] assign out_woready_120 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_121 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_122 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_123 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = ~_out_T_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = _out_wofireMux_T_2 & out_backSel_8; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_36 = _out_wofireMux_T_35 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_18 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_19 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_37 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_39 = _out_wofireMux_T_2 & out_backSel_9; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_40 = _out_wofireMux_T_39 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_43 = _out_wofireMux_T_2 & out_backSel_10; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_44 = _out_wofireMux_T_43 & _out_T_17; // @[RegisterRouter.scala:87:24] assign out_woready_29 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_30 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_31 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_45 = ~_out_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_47 = _out_wofireMux_T_2 & out_backSel_11; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_48 = _out_wofireMux_T_47 & _out_T_57; // @[RegisterRouter.scala:87:24] assign out_woready_128 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_129 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_130 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] assign out_woready_131 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = ~_out_T_57; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_51 = _out_wofireMux_T_2 & out_backSel_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_52 = _out_wofireMux_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_55 = _out_wofireMux_T_2 & out_backSel_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_56 = _out_wofireMux_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_59 = _out_wofireMux_T_2 & out_backSel_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_60 = _out_wofireMux_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_63 = _out_wofireMux_T_2 & out_backSel_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_64 = _out_wofireMux_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = _out_wofireMux_T_2 & out_backSel_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_68 = _out_wofireMux_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_71 = _out_wofireMux_T_2 & out_backSel_17; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_72 = _out_wofireMux_T_71 & _out_T_43; // @[RegisterRouter.scala:87:24] assign out_woready_82 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_83 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_84 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_85 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_86 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_87 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_88 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_89 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_90 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_91 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_92 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_93 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_94 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_95 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_96 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_97 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_98 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_99 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] assign out_woready_100 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_73 = ~_out_T_43; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_75 = _out_wofireMux_T_2 & out_backSel_18; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_76 = _out_wofireMux_T_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_79 = _out_wofireMux_T_2 & out_backSel_19; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_80 = _out_wofireMux_T_79 & _out_T_67; // @[RegisterRouter.scala:87:24] assign out_woready_145 = _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_81 = ~_out_T_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_83 = _out_wofireMux_T_2 & out_backSel_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_84 = _out_wofireMux_T_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_87 = _out_wofireMux_T_2 & out_backSel_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_88 = _out_wofireMux_T_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_91 = _out_wofireMux_T_2 & out_backSel_22; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_92 = _out_wofireMux_T_91 & _out_T_49; // @[RegisterRouter.scala:87:24] assign out_woready_109 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_110 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_111 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_112 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_113 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_114 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] assign out_woready_115 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_93 = ~_out_T_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_95 = _out_wofireMux_T_2 & out_backSel_23; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_96 = _out_wofireMux_T_95 & _out_T_63; // @[RegisterRouter.scala:87:24] assign out_woready_140 = _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_97 = ~_out_T_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_99 = _out_wofireMux_T_2 & out_backSel_24; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_100 = _out_wofireMux_T_99 & _out_T_23; // @[RegisterRouter.scala:87:24] assign out_woready_52 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_53 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] assign out_woready_54 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_101 = ~_out_T_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_103 = _out_wofireMux_T_2 & out_backSel_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_104 = _out_wofireMux_T_103; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_107 = _out_wofireMux_T_2 & out_backSel_26; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_108 = _out_wofireMux_T_107; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_111 = _out_wofireMux_T_2 & out_backSel_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_112 = _out_wofireMux_T_111; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_115 = _out_wofireMux_T_2 & out_backSel_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_116 = _out_wofireMux_T_115; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_119 = _out_wofireMux_T_2 & out_backSel_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_120 = _out_wofireMux_T_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_123 = _out_wofireMux_T_2 & out_backSel_30; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_124 = _out_wofireMux_T_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_127 = _out_wofireMux_T_2 & out_backSel_31; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_128 = _out_wofireMux_T_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_131 = _out_wofireMux_T_2 & out_backSel_32; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_132 = _out_wofireMux_T_131 & _out_T_45; // @[RegisterRouter.scala:87:24] assign out_woready_101 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_102 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_103 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] assign out_woready_104 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_133 = ~_out_T_45; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_135 = _out_wofireMux_T_2 & out_backSel_33; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_136 = _out_wofireMux_T_135 & _out_T_37; // @[RegisterRouter.scala:87:24] assign out_woready_73 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_74 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_75 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] assign out_woready_76 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_137 = ~_out_T_37; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_139 = _out_wofireMux_T_2 & out_backSel_34; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_140 = _out_wofireMux_T_139 & _out_T_47; // @[RegisterRouter.scala:87:24] assign out_woready_105 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_106 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_107 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] assign out_woready_108 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_141 = ~_out_T_47; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_143 = _out_wofireMux_T_2 & out_backSel_35; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_144 = _out_wofireMux_T_143 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_145 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_147 = _out_wofireMux_T_2 & out_backSel_36; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_148 = _out_wofireMux_T_147 & _out_T_65; // @[RegisterRouter.scala:87:24] assign out_woready_141 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_142 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_143 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] assign out_woready_144 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_149 = ~_out_T_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_151 = _out_wofireMux_T_2 & out_backSel_37; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_152 = _out_wofireMux_T_151 & _out_T_25; // @[RegisterRouter.scala:87:24] assign out_woready_55 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_56 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_57 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] assign out_woready_58 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_153 = ~_out_T_25; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_155 = _out_wofireMux_T_2 & out_backSel_38; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_156 = _out_wofireMux_T_155 & _out_T_35; // @[RegisterRouter.scala:87:24] assign out_woready_69 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_70 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_71 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] assign out_woready_72 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_157 = ~_out_T_35; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_159 = _out_wofireMux_T_2 & out_backSel_39; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_160 = _out_wofireMux_T_159 & _out_T_55; // @[RegisterRouter.scala:87:24] assign out_woready_124 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_125 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_126 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] assign out_woready_127 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_161 = ~_out_T_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_163 = _out_wofireMux_T_2 & out_backSel_40; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_164 = _out_wofireMux_T_163 & _out_T_61; // @[RegisterRouter.scala:87:24] assign out_woready_136 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_137 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_138 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] assign out_woready_139 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_165 = ~_out_T_61; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_167 = _out_wofireMux_T_2 & out_backSel_41; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_168 = _out_wofireMux_T_167 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_169 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_171 = _out_wofireMux_T_2 & out_backSel_42; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_172 = _out_wofireMux_T_171 & _out_T_21; // @[RegisterRouter.scala:87:24] assign out_woready_48 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_49 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_50 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] assign out_woready_51 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_173 = ~_out_T_21; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_175 = _out_wofireMux_T_2 & out_backSel_43; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_176 = _out_wofireMux_T_175 & _out_T_59; // @[RegisterRouter.scala:87:24] assign out_woready_132 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_133 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_134 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] assign out_woready_135 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_177 = ~_out_T_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_179 = _out_wofireMux_T_2 & out_backSel_44; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_180 = _out_wofireMux_T_179 & _out_T_51; // @[RegisterRouter.scala:87:24] assign out_woready_116 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_117 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_118 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] assign out_woready_119 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_181 = ~_out_T_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_183 = _out_wofireMux_T_2 & out_backSel_45; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_184 = _out_wofireMux_T_183 & _out_T_39; // @[RegisterRouter.scala:87:24] assign out_woready_77 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_78 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_79 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] assign out_woready_80 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_185 = ~_out_T_39; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_187 = _out_wofireMux_T_2 & out_backSel_46; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_188 = _out_wofireMux_T_187 & _out_T_27; // @[RegisterRouter.scala:87:24] assign out_woready_59 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_60 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_61 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] assign out_woready_62 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_189 = ~_out_T_27; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_191 = _out_wofireMux_T_2 & out_backSel_47; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_192 = _out_wofireMux_T_191 & _out_T_15; // @[RegisterRouter.scala:87:24] assign out_woready_25 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_26 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_27 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_193 = ~_out_T_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_195 = _out_wofireMux_T_2 & out_backSel_48; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_196 = _out_wofireMux_T_195; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_199 = _out_wofireMux_T_2 & out_backSel_49; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_200 = _out_wofireMux_T_199; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_203 = _out_wofireMux_T_2 & out_backSel_50; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_204 = _out_wofireMux_T_203; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_207 = _out_wofireMux_T_2 & out_backSel_51; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_208 = _out_wofireMux_T_207; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_211 = _out_wofireMux_T_2 & out_backSel_52; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_212 = _out_wofireMux_T_211; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_215 = _out_wofireMux_T_2 & out_backSel_53; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_216 = _out_wofireMux_T_215; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_219 = _out_wofireMux_T_2 & out_backSel_54; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_220 = _out_wofireMux_T_219; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_223 = _out_wofireMux_T_2 & out_backSel_55; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_224 = _out_wofireMux_T_223; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_227 = _out_wofireMux_T_2 & out_backSel_56; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_228 = _out_wofireMux_T_227 & _out_T_19; // @[RegisterRouter.scala:87:24] assign out_woready_33 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_34 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_35 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_36 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_37 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_38 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_39 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_40 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_41 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_42 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_43 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_44 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_46 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] assign out_woready_47 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_229 = ~_out_T_19; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_231 = _out_wofireMux_T_2 & out_backSel_57; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_232 = _out_wofireMux_T_231 & _out_T_29; // @[RegisterRouter.scala:87:24] assign out_woready_63 = _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_233 = ~_out_T_29; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_235 = _out_wofireMux_T_2 & out_backSel_58; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_236 = _out_wofireMux_T_235; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_239 = _out_wofireMux_T_2 & out_backSel_59; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_240 = _out_wofireMux_T_239; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_243 = _out_wofireMux_T_2 & out_backSel_60; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_244 = _out_wofireMux_T_243 & _out_T_33; // @[RegisterRouter.scala:87:24] assign out_woready_68 = _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_245 = ~_out_T_33; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_247 = _out_wofireMux_T_2 & out_backSel_61; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_248 = _out_wofireMux_T_247 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_249 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_251 = _out_wofireMux_T_2 & out_backSel_62; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_252 = _out_wofireMux_T_251; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_255 = _out_wofireMux_T_2 & out_backSel_63; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_256 = _out_wofireMux_T_255; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _GEN_13 = {{1'h1}, {1'h1}, {_out_out_bits_data_WIRE_61}, {_out_out_bits_data_WIRE_60}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_57}, {_out_out_bits_data_WIRE_56}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_47}, {_out_out_bits_data_WIRE_46}, {_out_out_bits_data_WIRE_45}, {_out_out_bits_data_WIRE_44}, {_out_out_bits_data_WIRE_43}, {_out_out_bits_data_WIRE_42}, {_out_out_bits_data_WIRE_41}, {_out_out_bits_data_WIRE_40}, {_out_out_bits_data_WIRE_39}, {_out_out_bits_data_WIRE_38}, {_out_out_bits_data_WIRE_37}, {_out_out_bits_data_WIRE_36}, {_out_out_bits_data_WIRE_35}, {_out_out_bits_data_WIRE_34}, {_out_out_bits_data_WIRE_33}, {_out_out_bits_data_WIRE_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_24}, {_out_out_bits_data_WIRE_23}, {_out_out_bits_data_WIRE_22}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_19}, {1'h1}, {_out_out_bits_data_WIRE_17}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_11}, {_out_out_bits_data_WIRE_10}, {_out_out_bits_data_WIRE_9}, {_out_out_bits_data_WIRE_8}, {_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_13[out_oindex]; // @[MuxLiteral.scala:49:10] wire [31:0] _out_out_bits_data_WIRE_1_17 = {9'h0, _out_T_1118}; // @[MuxLiteral.scala:49:48] wire [31:0] _out_out_bits_data_WIRE_1_22 = {3'h0, _out_T_1271}; // @[MuxLiteral.scala:49:48] wire [63:0][31:0] _GEN_14 = {{32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_61}, {_out_out_bits_data_WIRE_1_60}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_57}, {_out_out_bits_data_WIRE_1_56}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_47}, {_out_out_bits_data_WIRE_1_46}, {_out_out_bits_data_WIRE_1_45}, {_out_out_bits_data_WIRE_1_44}, {_out_out_bits_data_WIRE_1_43}, {_out_out_bits_data_WIRE_1_42}, {_out_out_bits_data_WIRE_1_41}, {_out_out_bits_data_WIRE_1_40}, {_out_out_bits_data_WIRE_1_39}, {_out_out_bits_data_WIRE_1_38}, {_out_out_bits_data_WIRE_1_37}, {_out_out_bits_data_WIRE_1_36}, {_out_out_bits_data_WIRE_1_35}, {_out_out_bits_data_WIRE_1_34}, {_out_out_bits_data_WIRE_1_33}, {_out_out_bits_data_WIRE_1_32}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_24}, {_out_out_bits_data_WIRE_1_23}, {_out_out_bits_data_WIRE_1_22}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_19}, {32'h0}, {_out_out_bits_data_WIRE_1_17}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_11}, {_out_out_bits_data_WIRE_1_10}, {_out_out_bits_data_WIRE_1_9}, {_out_out_bits_data_WIRE_1_8}, {_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [31:0] _out_out_bits_data_T_3 = _GEN_14[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign dmiNodeIn_d_bits_size = dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_source = dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg goReg; // @[Debug.scala:1494:27] wire flags_0_go = goReg; // @[Debug.scala:1494:27, :1517:25] wire goAbstract; // @[Debug.scala:1495:32] wire goCustom; // @[Debug.scala:1496:32] wire flags_0_resume; // @[Debug.scala:1517:25] assign flags_0_resume = _flags_resume_T; // @[Debug.scala:1517:25, :1524:80] wire [31:0] _accessRegisterCommandWr_T = {COMMANDWrData_cmdtype, COMMANDWrData_control}; // @[Debug.scala:1280:39, :1531:59] wire [31:0] _accessRegisterCommandWr_WIRE_1 = _accessRegisterCommandWr_T; // @[Debug.scala:1531:{59,74}] wire [7:0] _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] wire [7:0] accessRegisterCommandWr_cmdtype = _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:{44,74}] wire [2:0] _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved0 = _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] wire [2:0] accessRegisterCommandWr_size = _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_reserved1 = _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_postexec = _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:{44,74}] wire _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_transfer = _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:{44,74}] wire [15:0] _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] wire accessRegisterCommandWr_write = _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:{44,74}] wire [15:0] accessRegisterCommandWr_regno = _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:{44,74}] assign _accessRegisterCommandWr_T_1 = _accessRegisterCommandWr_WIRE_1[15:0]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_regno = _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_2 = _accessRegisterCommandWr_WIRE_1[16]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_write = _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_3 = _accessRegisterCommandWr_WIRE_1[17]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_transfer = _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_4 = _accessRegisterCommandWr_WIRE_1[18]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_postexec = _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_5 = _accessRegisterCommandWr_WIRE_1[19]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved1 = _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_6 = _accessRegisterCommandWr_WIRE_1[22:20]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_size = _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_7 = _accessRegisterCommandWr_WIRE_1[23]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_reserved0 = _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_T_8 = _accessRegisterCommandWr_WIRE_1[31:24]; // @[Debug.scala:1531:74] assign _accessRegisterCommandWr_WIRE_cmdtype = _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74] wire [31:0] _accessRegisterCommandReg_WIRE_1 = _accessRegisterCommandReg_T; // @[Debug.scala:1533:{56,71}] wire [7:0] _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] wire [7:0] accessRegisterCommandReg_cmdtype = _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:{44,71}] wire [2:0] _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved0 = _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_reserved1 = _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:{44,71}] wire _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:{44,71}] wire [15:0] _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] wire accessRegisterCommandReg_write = _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:{44,71}] wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:{44,71}] assign _accessRegisterCommandReg_T_1 = _accessRegisterCommandReg_WIRE_1[15:0]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_regno = _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_2 = _accessRegisterCommandReg_WIRE_1[16]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_write = _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_3 = _accessRegisterCommandReg_WIRE_1[17]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_transfer = _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_4 = _accessRegisterCommandReg_WIRE_1[18]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_postexec = _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_5 = _accessRegisterCommandReg_WIRE_1[19]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved1 = _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_6 = _accessRegisterCommandReg_WIRE_1[22:20]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_size = _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_7 = _accessRegisterCommandReg_WIRE_1[23]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_reserved0 = _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_T_8 = _accessRegisterCommandReg_WIRE_1[31:24]; // @[Debug.scala:1533:71] assign _accessRegisterCommandReg_WIRE_cmdtype = _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71] wire [2:0] abstractGeneratedMem_0_inst_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1589:22] wire [2:0] abstractGeneratedMem_0_inst_1_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1601:22] reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35] wire [31:0] _out_T_8286 = abstractGeneratedMem_0; // @[RegisterRouter.scala:87:24] reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35] wire [4:0] abstractGeneratedMem_0_inst_rd; // @[Debug.scala:1589:22] wire [15:0] _GEN_15 = {11'h0, accessRegisterCommandReg_regno[4:0]}; // @[Debug.scala:1533:44, :1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rd_T; // @[Debug.scala:1593:54] assign _abstractGeneratedMem_0_inst_rd_T = _GEN_15; // @[Debug.scala:1593:54] wire [15:0] _abstractGeneratedMem_0_inst_rs2_T; // @[Debug.scala:1608:54] assign _abstractGeneratedMem_0_inst_rs2_T = _GEN_15; // @[Debug.scala:1593:54, :1608:54] assign abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala:1589:22, :1593:{19,54}] wire [11:0] abstractGeneratedMem_0_lo = {abstractGeneratedMem_0_inst_rd, 7'h3}; // @[Debug.scala:1589:22, :1597:12] wire [19:0] abstractGeneratedMem_0_hi = {17'h7000, abstractGeneratedMem_0_inst_funct3}; // @[Debug.scala:1589:22, :1597:12] wire [31:0] _abstractGeneratedMem_0_T = {abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo}; // @[Debug.scala:1597:12] wire [4:0] abstractGeneratedMem_0_inst_1_rs2; // @[Debug.scala:1601:22] assign abstractGeneratedMem_0_inst_1_rs2 = _abstractGeneratedMem_0_inst_rs2_T[4:0]; // @[Debug.scala:1601:22, :1608:{19,54}] wire [7:0] abstractGeneratedMem_0_lo_hi = {abstractGeneratedMem_0_inst_1_funct3, 5'h0}; // @[Debug.scala:1601:22, :1610:12] wire [14:0] abstractGeneratedMem_0_lo_1 = {abstractGeneratedMem_0_lo_hi, 7'h23}; // @[Debug.scala:1610:12] wire [11:0] abstractGeneratedMem_0_hi_hi_1 = {7'h1C, abstractGeneratedMem_0_inst_1_rs2}; // @[Debug.scala:1601:22, :1610:12] wire [16:0] abstractGeneratedMem_0_hi_1 = {abstractGeneratedMem_0_hi_hi_1, 5'h0}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_1 = {abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1}; // @[Debug.scala:1610:12] wire [31:0] _abstractGeneratedMem_0_T_2 = accessRegisterCommandReg_write ? _abstractGeneratedMem_0_T : _abstractGeneratedMem_0_T_1; // @[Debug.scala:1533:44, :1597:12, :1610:12, :1641:14] wire [31:0] _abstractGeneratedMem_0_T_4 = accessRegisterCommandReg_transfer ? _abstractGeneratedMem_0_T_2 : 32'h13; // @[Debug.scala:1533:44, :1640:39, :1641:14] wire [31:0] _abstractGeneratedMem_1_T_1 = accessRegisterCommandReg_postexec ? 32'h13 : 32'h100073; // @[Debug.scala:1533:44, :1644:39] wire [6:0] _GEN_16 = {6'h0, flags_0_resume}; // @[Debug.scala:1517:25, :1702:60] wire [6:0] hi_1; // @[Debug.scala:1702:60] assign hi_1 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_2; // @[Debug.scala:1702:60] assign hi_2 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_3; // @[Debug.scala:1702:60] assign hi_3 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_4; // @[Debug.scala:1702:60] assign hi_4 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_5; // @[Debug.scala:1702:60] assign hi_5 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_6; // @[Debug.scala:1702:60] assign hi_6 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_7; // @[Debug.scala:1702:60] assign hi_7 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_8; // @[Debug.scala:1702:60] assign hi_8 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_9; // @[Debug.scala:1702:60] assign hi_9 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_10; // @[Debug.scala:1702:60] assign hi_10 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_11; // @[Debug.scala:1702:60] assign hi_11 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_12; // @[Debug.scala:1702:60] assign hi_12 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_13; // @[Debug.scala:1702:60] assign hi_13 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_14; // @[Debug.scala:1702:60] assign hi_14 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_15; // @[Debug.scala:1702:60] assign hi_15 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_16; // @[Debug.scala:1702:60] assign hi_16 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_17; // @[Debug.scala:1702:60] assign hi_17 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_18; // @[Debug.scala:1702:60] assign hi_18 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_19; // @[Debug.scala:1702:60] assign hi_19 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_20; // @[Debug.scala:1702:60] assign hi_20 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_21; // @[Debug.scala:1702:60] assign hi_21 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_22; // @[Debug.scala:1702:60] assign hi_22 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_23; // @[Debug.scala:1702:60] assign hi_23 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_24; // @[Debug.scala:1702:60] assign hi_24 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_25; // @[Debug.scala:1702:60] assign hi_25 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_26; // @[Debug.scala:1702:60] assign hi_26 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_27; // @[Debug.scala:1702:60] assign hi_27 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_28; // @[Debug.scala:1702:60] assign hi_28 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_29; // @[Debug.scala:1702:60] assign hi_29 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_30; // @[Debug.scala:1702:60] assign hi_30 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_31; // @[Debug.scala:1702:60] assign hi_31 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_32; // @[Debug.scala:1702:60] assign hi_32 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_33; // @[Debug.scala:1702:60] assign hi_33 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_34; // @[Debug.scala:1702:60] assign hi_34 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_35; // @[Debug.scala:1702:60] assign hi_35 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_36; // @[Debug.scala:1702:60] assign hi_36 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_37; // @[Debug.scala:1702:60] assign hi_37 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_38; // @[Debug.scala:1702:60] assign hi_38 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_39; // @[Debug.scala:1702:60] assign hi_39 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_40; // @[Debug.scala:1702:60] assign hi_40 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_41; // @[Debug.scala:1702:60] assign hi_41 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_42; // @[Debug.scala:1702:60] assign hi_42 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_43; // @[Debug.scala:1702:60] assign hi_43 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_44; // @[Debug.scala:1702:60] assign hi_44 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_45; // @[Debug.scala:1702:60] assign hi_45 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_46; // @[Debug.scala:1702:60] assign hi_46 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_47; // @[Debug.scala:1702:60] assign hi_47 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_48; // @[Debug.scala:1702:60] assign hi_48 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_49; // @[Debug.scala:1702:60] assign hi_49 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_50; // @[Debug.scala:1702:60] assign hi_50 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_51; // @[Debug.scala:1702:60] assign hi_51 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_52; // @[Debug.scala:1702:60] assign hi_52 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_53; // @[Debug.scala:1702:60] assign hi_53 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_54; // @[Debug.scala:1702:60] assign hi_54 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_55; // @[Debug.scala:1702:60] assign hi_55 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_56; // @[Debug.scala:1702:60] assign hi_56 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_57; // @[Debug.scala:1702:60] assign hi_57 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_58; // @[Debug.scala:1702:60] assign hi_58 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_59; // @[Debug.scala:1702:60] assign hi_59 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_60; // @[Debug.scala:1702:60] assign hi_60 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_61; // @[Debug.scala:1702:60] assign hi_61 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_62; // @[Debug.scala:1702:60] assign hi_62 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_63; // @[Debug.scala:1702:60] assign hi_63 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_64; // @[Debug.scala:1702:60] assign hi_64 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_65; // @[Debug.scala:1702:60] assign hi_65 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_66; // @[Debug.scala:1702:60] assign hi_66 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_67; // @[Debug.scala:1702:60] assign hi_67 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_68; // @[Debug.scala:1702:60] assign hi_68 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_69; // @[Debug.scala:1702:60] assign hi_69 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_70; // @[Debug.scala:1702:60] assign hi_70 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_71; // @[Debug.scala:1702:60] assign hi_71 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_72; // @[Debug.scala:1702:60] assign hi_72 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_73; // @[Debug.scala:1702:60] assign hi_73 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_74; // @[Debug.scala:1702:60] assign hi_74 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_75; // @[Debug.scala:1702:60] assign hi_75 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_76; // @[Debug.scala:1702:60] assign hi_76 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_77; // @[Debug.scala:1702:60] assign hi_77 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_78; // @[Debug.scala:1702:60] assign hi_78 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_79; // @[Debug.scala:1702:60] assign hi_79 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_80; // @[Debug.scala:1702:60] assign hi_80 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_81; // @[Debug.scala:1702:60] assign hi_81 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_82; // @[Debug.scala:1702:60] assign hi_82 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_83; // @[Debug.scala:1702:60] assign hi_83 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_84; // @[Debug.scala:1702:60] assign hi_84 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_85; // @[Debug.scala:1702:60] assign hi_85 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_86; // @[Debug.scala:1702:60] assign hi_86 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_87; // @[Debug.scala:1702:60] assign hi_87 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_88; // @[Debug.scala:1702:60] assign hi_88 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_89; // @[Debug.scala:1702:60] assign hi_89 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_90; // @[Debug.scala:1702:60] assign hi_90 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_91; // @[Debug.scala:1702:60] assign hi_91 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_92; // @[Debug.scala:1702:60] assign hi_92 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_93; // @[Debug.scala:1702:60] assign hi_93 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_94; // @[Debug.scala:1702:60] assign hi_94 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_95; // @[Debug.scala:1702:60] assign hi_95 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_96; // @[Debug.scala:1702:60] assign hi_96 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_97; // @[Debug.scala:1702:60] assign hi_97 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_98; // @[Debug.scala:1702:60] assign hi_98 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_99; // @[Debug.scala:1702:60] assign hi_99 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_100; // @[Debug.scala:1702:60] assign hi_100 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_101; // @[Debug.scala:1702:60] assign hi_101 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_102; // @[Debug.scala:1702:60] assign hi_102 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_103; // @[Debug.scala:1702:60] assign hi_103 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_104; // @[Debug.scala:1702:60] assign hi_104 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_105; // @[Debug.scala:1702:60] assign hi_105 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_106; // @[Debug.scala:1702:60] assign hi_106 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_107; // @[Debug.scala:1702:60] assign hi_107 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_108; // @[Debug.scala:1702:60] assign hi_108 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_109; // @[Debug.scala:1702:60] assign hi_109 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_110; // @[Debug.scala:1702:60] assign hi_110 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_111; // @[Debug.scala:1702:60] assign hi_111 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_112; // @[Debug.scala:1702:60] assign hi_112 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_113; // @[Debug.scala:1702:60] assign hi_113 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_114; // @[Debug.scala:1702:60] assign hi_114 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_115; // @[Debug.scala:1702:60] assign hi_115 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_116; // @[Debug.scala:1702:60] assign hi_116 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_117; // @[Debug.scala:1702:60] assign hi_117 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_118; // @[Debug.scala:1702:60] assign hi_118 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_119; // @[Debug.scala:1702:60] assign hi_119 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_120; // @[Debug.scala:1702:60] assign hi_120 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_121; // @[Debug.scala:1702:60] assign hi_121 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_122; // @[Debug.scala:1702:60] assign hi_122 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_123; // @[Debug.scala:1702:60] assign hi_123 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_124; // @[Debug.scala:1702:60] assign hi_124 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_125; // @[Debug.scala:1702:60] assign hi_125 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_126; // @[Debug.scala:1702:60] assign hi_126 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_127; // @[Debug.scala:1702:60] assign hi_127 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_128; // @[Debug.scala:1702:60] assign hi_128 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_129; // @[Debug.scala:1702:60] assign hi_129 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_130; // @[Debug.scala:1702:60] assign hi_130 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_131; // @[Debug.scala:1702:60] assign hi_131 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_132; // @[Debug.scala:1702:60] assign hi_132 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_133; // @[Debug.scala:1702:60] assign hi_133 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_134; // @[Debug.scala:1702:60] assign hi_134 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_135; // @[Debug.scala:1702:60] assign hi_135 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_136; // @[Debug.scala:1702:60] assign hi_136 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_137; // @[Debug.scala:1702:60] assign hi_137 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_138; // @[Debug.scala:1702:60] assign hi_138 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_139; // @[Debug.scala:1702:60] assign hi_139 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_140; // @[Debug.scala:1702:60] assign hi_140 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_141; // @[Debug.scala:1702:60] assign hi_141 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_142; // @[Debug.scala:1702:60] assign hi_142 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_143; // @[Debug.scala:1702:60] assign hi_143 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_144; // @[Debug.scala:1702:60] assign hi_144 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_145; // @[Debug.scala:1702:60] assign hi_145 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_146; // @[Debug.scala:1702:60] assign hi_146 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_147; // @[Debug.scala:1702:60] assign hi_147 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_148; // @[Debug.scala:1702:60] assign hi_148 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_149; // @[Debug.scala:1702:60] assign hi_149 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_150; // @[Debug.scala:1702:60] assign hi_150 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_151; // @[Debug.scala:1702:60] assign hi_151 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_152; // @[Debug.scala:1702:60] assign hi_152 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_153; // @[Debug.scala:1702:60] assign hi_153 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_154; // @[Debug.scala:1702:60] assign hi_154 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_155; // @[Debug.scala:1702:60] assign hi_155 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_156; // @[Debug.scala:1702:60] assign hi_156 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_157; // @[Debug.scala:1702:60] assign hi_157 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_158; // @[Debug.scala:1702:60] assign hi_158 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_159; // @[Debug.scala:1702:60] assign hi_159 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_160; // @[Debug.scala:1702:60] assign hi_160 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_161; // @[Debug.scala:1702:60] assign hi_161 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_162; // @[Debug.scala:1702:60] assign hi_162 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_163; // @[Debug.scala:1702:60] assign hi_163 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_164; // @[Debug.scala:1702:60] assign hi_164 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_165; // @[Debug.scala:1702:60] assign hi_165 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_166; // @[Debug.scala:1702:60] assign hi_166 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_167; // @[Debug.scala:1702:60] assign hi_167 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_168; // @[Debug.scala:1702:60] assign hi_168 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_169; // @[Debug.scala:1702:60] assign hi_169 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_170; // @[Debug.scala:1702:60] assign hi_170 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_171; // @[Debug.scala:1702:60] assign hi_171 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_172; // @[Debug.scala:1702:60] assign hi_172 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_173; // @[Debug.scala:1702:60] assign hi_173 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_174; // @[Debug.scala:1702:60] assign hi_174 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_175; // @[Debug.scala:1702:60] assign hi_175 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_176; // @[Debug.scala:1702:60] assign hi_176 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_177; // @[Debug.scala:1702:60] assign hi_177 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_178; // @[Debug.scala:1702:60] assign hi_178 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_179; // @[Debug.scala:1702:60] assign hi_179 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_180; // @[Debug.scala:1702:60] assign hi_180 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_181; // @[Debug.scala:1702:60] assign hi_181 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_182; // @[Debug.scala:1702:60] assign hi_182 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_183; // @[Debug.scala:1702:60] assign hi_183 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_184; // @[Debug.scala:1702:60] assign hi_184 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_185; // @[Debug.scala:1702:60] assign hi_185 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_186; // @[Debug.scala:1702:60] assign hi_186 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_187; // @[Debug.scala:1702:60] assign hi_187 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_188; // @[Debug.scala:1702:60] assign hi_188 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_189; // @[Debug.scala:1702:60] assign hi_189 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_190; // @[Debug.scala:1702:60] assign hi_190 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_191; // @[Debug.scala:1702:60] assign hi_191 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_192; // @[Debug.scala:1702:60] assign hi_192 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_193; // @[Debug.scala:1702:60] assign hi_193 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_194; // @[Debug.scala:1702:60] assign hi_194 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_195; // @[Debug.scala:1702:60] assign hi_195 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_196; // @[Debug.scala:1702:60] assign hi_196 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_197; // @[Debug.scala:1702:60] assign hi_197 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_198; // @[Debug.scala:1702:60] assign hi_198 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_199; // @[Debug.scala:1702:60] assign hi_199 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_200; // @[Debug.scala:1702:60] assign hi_200 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_201; // @[Debug.scala:1702:60] assign hi_201 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_202; // @[Debug.scala:1702:60] assign hi_202 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_203; // @[Debug.scala:1702:60] assign hi_203 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_204; // @[Debug.scala:1702:60] assign hi_204 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_205; // @[Debug.scala:1702:60] assign hi_205 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_206; // @[Debug.scala:1702:60] assign hi_206 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_207; // @[Debug.scala:1702:60] assign hi_207 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_208; // @[Debug.scala:1702:60] assign hi_208 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_209; // @[Debug.scala:1702:60] assign hi_209 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_210; // @[Debug.scala:1702:60] assign hi_210 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_211; // @[Debug.scala:1702:60] assign hi_211 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_212; // @[Debug.scala:1702:60] assign hi_212 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_213; // @[Debug.scala:1702:60] assign hi_213 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_214; // @[Debug.scala:1702:60] assign hi_214 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_215; // @[Debug.scala:1702:60] assign hi_215 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_216; // @[Debug.scala:1702:60] assign hi_216 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_217; // @[Debug.scala:1702:60] assign hi_217 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_218; // @[Debug.scala:1702:60] assign hi_218 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_219; // @[Debug.scala:1702:60] assign hi_219 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_220; // @[Debug.scala:1702:60] assign hi_220 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_221; // @[Debug.scala:1702:60] assign hi_221 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_222; // @[Debug.scala:1702:60] assign hi_222 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_223; // @[Debug.scala:1702:60] assign hi_223 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_224; // @[Debug.scala:1702:60] assign hi_224 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_225; // @[Debug.scala:1702:60] assign hi_225 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_226; // @[Debug.scala:1702:60] assign hi_226 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_227; // @[Debug.scala:1702:60] assign hi_227 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_228; // @[Debug.scala:1702:60] assign hi_228 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_229; // @[Debug.scala:1702:60] assign hi_229 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_230; // @[Debug.scala:1702:60] assign hi_230 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_231; // @[Debug.scala:1702:60] assign hi_231 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_232; // @[Debug.scala:1702:60] assign hi_232 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_233; // @[Debug.scala:1702:60] assign hi_233 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_234; // @[Debug.scala:1702:60] assign hi_234 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_235; // @[Debug.scala:1702:60] assign hi_235 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_236; // @[Debug.scala:1702:60] assign hi_236 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_237; // @[Debug.scala:1702:60] assign hi_237 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_238; // @[Debug.scala:1702:60] assign hi_238 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_239; // @[Debug.scala:1702:60] assign hi_239 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_240; // @[Debug.scala:1702:60] assign hi_240 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_241; // @[Debug.scala:1702:60] assign hi_241 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_242; // @[Debug.scala:1702:60] assign hi_242 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_243; // @[Debug.scala:1702:60] assign hi_243 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_244; // @[Debug.scala:1702:60] assign hi_244 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_245; // @[Debug.scala:1702:60] assign hi_245 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_246; // @[Debug.scala:1702:60] assign hi_246 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_247; // @[Debug.scala:1702:60] assign hi_247 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_248; // @[Debug.scala:1702:60] assign hi_248 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_249; // @[Debug.scala:1702:60] assign hi_249 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_250; // @[Debug.scala:1702:60] assign hi_250 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_251; // @[Debug.scala:1702:60] assign hi_251 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_252; // @[Debug.scala:1702:60] assign hi_252 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_253; // @[Debug.scala:1702:60] assign hi_253 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_254; // @[Debug.scala:1702:60] assign hi_254 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_255; // @[Debug.scala:1702:60] assign hi_255 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_256; // @[Debug.scala:1702:60] assign hi_256 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_257; // @[Debug.scala:1702:60] assign hi_257 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_258; // @[Debug.scala:1702:60] assign hi_258 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_259; // @[Debug.scala:1702:60] assign hi_259 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_260; // @[Debug.scala:1702:60] assign hi_260 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_261; // @[Debug.scala:1702:60] assign hi_261 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_262; // @[Debug.scala:1702:60] assign hi_262 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_263; // @[Debug.scala:1702:60] assign hi_263 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_264; // @[Debug.scala:1702:60] assign hi_264 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_265; // @[Debug.scala:1702:60] assign hi_265 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_266; // @[Debug.scala:1702:60] assign hi_266 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_267; // @[Debug.scala:1702:60] assign hi_267 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_268; // @[Debug.scala:1702:60] assign hi_268 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_269; // @[Debug.scala:1702:60] assign hi_269 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_270; // @[Debug.scala:1702:60] assign hi_270 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_271; // @[Debug.scala:1702:60] assign hi_271 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_272; // @[Debug.scala:1702:60] assign hi_272 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_273; // @[Debug.scala:1702:60] assign hi_273 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_274; // @[Debug.scala:1702:60] assign hi_274 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_275; // @[Debug.scala:1702:60] assign hi_275 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_276; // @[Debug.scala:1702:60] assign hi_276 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_277; // @[Debug.scala:1702:60] assign hi_277 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_278; // @[Debug.scala:1702:60] assign hi_278 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_279; // @[Debug.scala:1702:60] assign hi_279 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_280; // @[Debug.scala:1702:60] assign hi_280 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_281; // @[Debug.scala:1702:60] assign hi_281 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_282; // @[Debug.scala:1702:60] assign hi_282 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_283; // @[Debug.scala:1702:60] assign hi_283 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_284; // @[Debug.scala:1702:60] assign hi_284 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_285; // @[Debug.scala:1702:60] assign hi_285 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_286; // @[Debug.scala:1702:60] assign hi_286 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_287; // @[Debug.scala:1702:60] assign hi_287 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_288; // @[Debug.scala:1702:60] assign hi_288 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_289; // @[Debug.scala:1702:60] assign hi_289 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_290; // @[Debug.scala:1702:60] assign hi_290 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_291; // @[Debug.scala:1702:60] assign hi_291 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_292; // @[Debug.scala:1702:60] assign hi_292 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_293; // @[Debug.scala:1702:60] assign hi_293 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_294; // @[Debug.scala:1702:60] assign hi_294 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_295; // @[Debug.scala:1702:60] assign hi_295 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_296; // @[Debug.scala:1702:60] assign hi_296 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_297; // @[Debug.scala:1702:60] assign hi_297 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_298; // @[Debug.scala:1702:60] assign hi_298 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_299; // @[Debug.scala:1702:60] assign hi_299 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_300; // @[Debug.scala:1702:60] assign hi_300 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_301; // @[Debug.scala:1702:60] assign hi_301 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_302; // @[Debug.scala:1702:60] assign hi_302 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_303; // @[Debug.scala:1702:60] assign hi_303 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_304; // @[Debug.scala:1702:60] assign hi_304 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_305; // @[Debug.scala:1702:60] assign hi_305 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_306; // @[Debug.scala:1702:60] assign hi_306 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_307; // @[Debug.scala:1702:60] assign hi_307 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_308; // @[Debug.scala:1702:60] assign hi_308 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_309; // @[Debug.scala:1702:60] assign hi_309 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_310; // @[Debug.scala:1702:60] assign hi_310 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_311; // @[Debug.scala:1702:60] assign hi_311 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_312; // @[Debug.scala:1702:60] assign hi_312 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_313; // @[Debug.scala:1702:60] assign hi_313 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_314; // @[Debug.scala:1702:60] assign hi_314 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_315; // @[Debug.scala:1702:60] assign hi_315 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_316; // @[Debug.scala:1702:60] assign hi_316 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_317; // @[Debug.scala:1702:60] assign hi_317 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_318; // @[Debug.scala:1702:60] assign hi_318 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_319; // @[Debug.scala:1702:60] assign hi_319 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_320; // @[Debug.scala:1702:60] assign hi_320 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_321; // @[Debug.scala:1702:60] assign hi_321 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_322; // @[Debug.scala:1702:60] assign hi_322 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_323; // @[Debug.scala:1702:60] assign hi_323 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_324; // @[Debug.scala:1702:60] assign hi_324 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_325; // @[Debug.scala:1702:60] assign hi_325 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_326; // @[Debug.scala:1702:60] assign hi_326 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_327; // @[Debug.scala:1702:60] assign hi_327 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_328; // @[Debug.scala:1702:60] assign hi_328 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_329; // @[Debug.scala:1702:60] assign hi_329 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_330; // @[Debug.scala:1702:60] assign hi_330 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_331; // @[Debug.scala:1702:60] assign hi_331 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_332; // @[Debug.scala:1702:60] assign hi_332 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_333; // @[Debug.scala:1702:60] assign hi_333 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_334; // @[Debug.scala:1702:60] assign hi_334 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_335; // @[Debug.scala:1702:60] assign hi_335 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_336; // @[Debug.scala:1702:60] assign hi_336 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_337; // @[Debug.scala:1702:60] assign hi_337 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_338; // @[Debug.scala:1702:60] assign hi_338 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_339; // @[Debug.scala:1702:60] assign hi_339 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_340; // @[Debug.scala:1702:60] assign hi_340 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_341; // @[Debug.scala:1702:60] assign hi_341 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_342; // @[Debug.scala:1702:60] assign hi_342 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_343; // @[Debug.scala:1702:60] assign hi_343 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_344; // @[Debug.scala:1702:60] assign hi_344 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_345; // @[Debug.scala:1702:60] assign hi_345 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_346; // @[Debug.scala:1702:60] assign hi_346 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_347; // @[Debug.scala:1702:60] assign hi_347 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_348; // @[Debug.scala:1702:60] assign hi_348 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_349; // @[Debug.scala:1702:60] assign hi_349 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_350; // @[Debug.scala:1702:60] assign hi_350 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_351; // @[Debug.scala:1702:60] assign hi_351 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_352; // @[Debug.scala:1702:60] assign hi_352 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_353; // @[Debug.scala:1702:60] assign hi_353 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_354; // @[Debug.scala:1702:60] assign hi_354 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_355; // @[Debug.scala:1702:60] assign hi_355 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_356; // @[Debug.scala:1702:60] assign hi_356 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_357; // @[Debug.scala:1702:60] assign hi_357 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_358; // @[Debug.scala:1702:60] assign hi_358 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_359; // @[Debug.scala:1702:60] assign hi_359 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_360; // @[Debug.scala:1702:60] assign hi_360 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_361; // @[Debug.scala:1702:60] assign hi_361 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_362; // @[Debug.scala:1702:60] assign hi_362 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_363; // @[Debug.scala:1702:60] assign hi_363 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_364; // @[Debug.scala:1702:60] assign hi_364 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_365; // @[Debug.scala:1702:60] assign hi_365 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_366; // @[Debug.scala:1702:60] assign hi_366 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_367; // @[Debug.scala:1702:60] assign hi_367 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_368; // @[Debug.scala:1702:60] assign hi_368 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_369; // @[Debug.scala:1702:60] assign hi_369 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_370; // @[Debug.scala:1702:60] assign hi_370 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_371; // @[Debug.scala:1702:60] assign hi_371 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_372; // @[Debug.scala:1702:60] assign hi_372 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_373; // @[Debug.scala:1702:60] assign hi_373 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_374; // @[Debug.scala:1702:60] assign hi_374 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_375; // @[Debug.scala:1702:60] assign hi_375 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_376; // @[Debug.scala:1702:60] assign hi_376 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_377; // @[Debug.scala:1702:60] assign hi_377 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_378; // @[Debug.scala:1702:60] assign hi_378 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_379; // @[Debug.scala:1702:60] assign hi_379 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_380; // @[Debug.scala:1702:60] assign hi_380 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_381; // @[Debug.scala:1702:60] assign hi_381 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_382; // @[Debug.scala:1702:60] assign hi_382 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_383; // @[Debug.scala:1702:60] assign hi_383 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_384; // @[Debug.scala:1702:60] assign hi_384 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_385; // @[Debug.scala:1702:60] assign hi_385 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_386; // @[Debug.scala:1702:60] assign hi_386 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_387; // @[Debug.scala:1702:60] assign hi_387 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_388; // @[Debug.scala:1702:60] assign hi_388 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_389; // @[Debug.scala:1702:60] assign hi_389 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_390; // @[Debug.scala:1702:60] assign hi_390 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_391; // @[Debug.scala:1702:60] assign hi_391 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_392; // @[Debug.scala:1702:60] assign hi_392 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_393; // @[Debug.scala:1702:60] assign hi_393 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_394; // @[Debug.scala:1702:60] assign hi_394 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_395; // @[Debug.scala:1702:60] assign hi_395 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_396; // @[Debug.scala:1702:60] assign hi_396 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_397; // @[Debug.scala:1702:60] assign hi_397 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_398; // @[Debug.scala:1702:60] assign hi_398 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_399; // @[Debug.scala:1702:60] assign hi_399 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_400; // @[Debug.scala:1702:60] assign hi_400 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_401; // @[Debug.scala:1702:60] assign hi_401 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_402; // @[Debug.scala:1702:60] assign hi_402 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_403; // @[Debug.scala:1702:60] assign hi_403 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_404; // @[Debug.scala:1702:60] assign hi_404 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_405; // @[Debug.scala:1702:60] assign hi_405 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_406; // @[Debug.scala:1702:60] assign hi_406 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_407; // @[Debug.scala:1702:60] assign hi_407 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_408; // @[Debug.scala:1702:60] assign hi_408 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_409; // @[Debug.scala:1702:60] assign hi_409 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_410; // @[Debug.scala:1702:60] assign hi_410 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_411; // @[Debug.scala:1702:60] assign hi_411 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_412; // @[Debug.scala:1702:60] assign hi_412 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_413; // @[Debug.scala:1702:60] assign hi_413 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_414; // @[Debug.scala:1702:60] assign hi_414 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_415; // @[Debug.scala:1702:60] assign hi_415 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_416; // @[Debug.scala:1702:60] assign hi_416 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_417; // @[Debug.scala:1702:60] assign hi_417 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_418; // @[Debug.scala:1702:60] assign hi_418 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_419; // @[Debug.scala:1702:60] assign hi_419 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_420; // @[Debug.scala:1702:60] assign hi_420 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_421; // @[Debug.scala:1702:60] assign hi_421 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_422; // @[Debug.scala:1702:60] assign hi_422 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_423; // @[Debug.scala:1702:60] assign hi_423 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_424; // @[Debug.scala:1702:60] assign hi_424 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_425; // @[Debug.scala:1702:60] assign hi_425 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_426; // @[Debug.scala:1702:60] assign hi_426 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_427; // @[Debug.scala:1702:60] assign hi_427 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_428; // @[Debug.scala:1702:60] assign hi_428 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_429; // @[Debug.scala:1702:60] assign hi_429 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_430; // @[Debug.scala:1702:60] assign hi_430 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_431; // @[Debug.scala:1702:60] assign hi_431 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_432; // @[Debug.scala:1702:60] assign hi_432 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_433; // @[Debug.scala:1702:60] assign hi_433 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_434; // @[Debug.scala:1702:60] assign hi_434 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_435; // @[Debug.scala:1702:60] assign hi_435 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_436; // @[Debug.scala:1702:60] assign hi_436 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_437; // @[Debug.scala:1702:60] assign hi_437 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_438; // @[Debug.scala:1702:60] assign hi_438 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_439; // @[Debug.scala:1702:60] assign hi_439 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_440; // @[Debug.scala:1702:60] assign hi_440 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_441; // @[Debug.scala:1702:60] assign hi_441 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_442; // @[Debug.scala:1702:60] assign hi_442 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_443; // @[Debug.scala:1702:60] assign hi_443 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_444; // @[Debug.scala:1702:60] assign hi_444 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_445; // @[Debug.scala:1702:60] assign hi_445 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_446; // @[Debug.scala:1702:60] assign hi_446 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_447; // @[Debug.scala:1702:60] assign hi_447 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_448; // @[Debug.scala:1702:60] assign hi_448 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_449; // @[Debug.scala:1702:60] assign hi_449 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_450; // @[Debug.scala:1702:60] assign hi_450 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_451; // @[Debug.scala:1702:60] assign hi_451 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_452; // @[Debug.scala:1702:60] assign hi_452 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_453; // @[Debug.scala:1702:60] assign hi_453 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_454; // @[Debug.scala:1702:60] assign hi_454 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_455; // @[Debug.scala:1702:60] assign hi_455 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_456; // @[Debug.scala:1702:60] assign hi_456 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_457; // @[Debug.scala:1702:60] assign hi_457 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_458; // @[Debug.scala:1702:60] assign hi_458 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_459; // @[Debug.scala:1702:60] assign hi_459 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_460; // @[Debug.scala:1702:60] assign hi_460 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_461; // @[Debug.scala:1702:60] assign hi_461 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_462; // @[Debug.scala:1702:60] assign hi_462 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_463; // @[Debug.scala:1702:60] assign hi_463 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_464; // @[Debug.scala:1702:60] assign hi_464 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_465; // @[Debug.scala:1702:60] assign hi_465 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_466; // @[Debug.scala:1702:60] assign hi_466 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_467; // @[Debug.scala:1702:60] assign hi_467 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_468; // @[Debug.scala:1702:60] assign hi_468 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_469; // @[Debug.scala:1702:60] assign hi_469 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_470; // @[Debug.scala:1702:60] assign hi_470 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_471; // @[Debug.scala:1702:60] assign hi_471 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_472; // @[Debug.scala:1702:60] assign hi_472 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_473; // @[Debug.scala:1702:60] assign hi_473 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_474; // @[Debug.scala:1702:60] assign hi_474 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_475; // @[Debug.scala:1702:60] assign hi_475 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_476; // @[Debug.scala:1702:60] assign hi_476 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_477; // @[Debug.scala:1702:60] assign hi_477 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_478; // @[Debug.scala:1702:60] assign hi_478 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_479; // @[Debug.scala:1702:60] assign hi_479 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_480; // @[Debug.scala:1702:60] assign hi_480 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_481; // @[Debug.scala:1702:60] assign hi_481 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_482; // @[Debug.scala:1702:60] assign hi_482 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_483; // @[Debug.scala:1702:60] assign hi_483 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_484; // @[Debug.scala:1702:60] assign hi_484 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_485; // @[Debug.scala:1702:60] assign hi_485 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_486; // @[Debug.scala:1702:60] assign hi_486 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_487; // @[Debug.scala:1702:60] assign hi_487 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_488; // @[Debug.scala:1702:60] assign hi_488 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_489; // @[Debug.scala:1702:60] assign hi_489 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_490; // @[Debug.scala:1702:60] assign hi_490 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_491; // @[Debug.scala:1702:60] assign hi_491 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_492; // @[Debug.scala:1702:60] assign hi_492 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_493; // @[Debug.scala:1702:60] assign hi_493 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_494; // @[Debug.scala:1702:60] assign hi_494 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_495; // @[Debug.scala:1702:60] assign hi_495 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_496; // @[Debug.scala:1702:60] assign hi_496 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_497; // @[Debug.scala:1702:60] assign hi_497 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_498; // @[Debug.scala:1702:60] assign hi_498 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_499; // @[Debug.scala:1702:60] assign hi_499 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_500; // @[Debug.scala:1702:60] assign hi_500 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_501; // @[Debug.scala:1702:60] assign hi_501 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_502; // @[Debug.scala:1702:60] assign hi_502 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_503; // @[Debug.scala:1702:60] assign hi_503 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_504; // @[Debug.scala:1702:60] assign hi_504 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_505; // @[Debug.scala:1702:60] assign hi_505 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_506; // @[Debug.scala:1702:60] assign hi_506 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_507; // @[Debug.scala:1702:60] assign hi_507 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_508; // @[Debug.scala:1702:60] assign hi_508 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_509; // @[Debug.scala:1702:60] assign hi_509 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_510; // @[Debug.scala:1702:60] assign hi_510 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_511; // @[Debug.scala:1702:60] assign hi_511 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_512; // @[Debug.scala:1702:60] assign hi_512 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_513; // @[Debug.scala:1702:60] assign hi_513 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_514; // @[Debug.scala:1702:60] assign hi_514 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_515; // @[Debug.scala:1702:60] assign hi_515 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_516; // @[Debug.scala:1702:60] assign hi_516 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_517; // @[Debug.scala:1702:60] assign hi_517 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_518; // @[Debug.scala:1702:60] assign hi_518 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_519; // @[Debug.scala:1702:60] assign hi_519 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_520; // @[Debug.scala:1702:60] assign hi_520 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_521; // @[Debug.scala:1702:60] assign hi_521 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_522; // @[Debug.scala:1702:60] assign hi_522 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_523; // @[Debug.scala:1702:60] assign hi_523 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_524; // @[Debug.scala:1702:60] assign hi_524 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_525; // @[Debug.scala:1702:60] assign hi_525 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_526; // @[Debug.scala:1702:60] assign hi_526 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_527; // @[Debug.scala:1702:60] assign hi_527 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_528; // @[Debug.scala:1702:60] assign hi_528 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_529; // @[Debug.scala:1702:60] assign hi_529 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_530; // @[Debug.scala:1702:60] assign hi_530 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_531; // @[Debug.scala:1702:60] assign hi_531 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_532; // @[Debug.scala:1702:60] assign hi_532 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_533; // @[Debug.scala:1702:60] assign hi_533 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_534; // @[Debug.scala:1702:60] assign hi_534 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_535; // @[Debug.scala:1702:60] assign hi_535 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_536; // @[Debug.scala:1702:60] assign hi_536 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_537; // @[Debug.scala:1702:60] assign hi_537 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_538; // @[Debug.scala:1702:60] assign hi_538 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_539; // @[Debug.scala:1702:60] assign hi_539 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_540; // @[Debug.scala:1702:60] assign hi_540 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_541; // @[Debug.scala:1702:60] assign hi_541 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_542; // @[Debug.scala:1702:60] assign hi_542 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_543; // @[Debug.scala:1702:60] assign hi_543 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_544; // @[Debug.scala:1702:60] assign hi_544 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_545; // @[Debug.scala:1702:60] assign hi_545 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_546; // @[Debug.scala:1702:60] assign hi_546 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_547; // @[Debug.scala:1702:60] assign hi_547 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_548; // @[Debug.scala:1702:60] assign hi_548 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_549; // @[Debug.scala:1702:60] assign hi_549 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_550; // @[Debug.scala:1702:60] assign hi_550 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_551; // @[Debug.scala:1702:60] assign hi_551 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_552; // @[Debug.scala:1702:60] assign hi_552 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_553; // @[Debug.scala:1702:60] assign hi_553 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_554; // @[Debug.scala:1702:60] assign hi_554 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_555; // @[Debug.scala:1702:60] assign hi_555 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_556; // @[Debug.scala:1702:60] assign hi_556 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_557; // @[Debug.scala:1702:60] assign hi_557 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_558; // @[Debug.scala:1702:60] assign hi_558 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_559; // @[Debug.scala:1702:60] assign hi_559 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_560; // @[Debug.scala:1702:60] assign hi_560 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_561; // @[Debug.scala:1702:60] assign hi_561 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_562; // @[Debug.scala:1702:60] assign hi_562 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_563; // @[Debug.scala:1702:60] assign hi_563 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_564; // @[Debug.scala:1702:60] assign hi_564 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_565; // @[Debug.scala:1702:60] assign hi_565 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_566; // @[Debug.scala:1702:60] assign hi_566 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_567; // @[Debug.scala:1702:60] assign hi_567 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_568; // @[Debug.scala:1702:60] assign hi_568 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_569; // @[Debug.scala:1702:60] assign hi_569 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_570; // @[Debug.scala:1702:60] assign hi_570 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_571; // @[Debug.scala:1702:60] assign hi_571 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_572; // @[Debug.scala:1702:60] assign hi_572 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_573; // @[Debug.scala:1702:60] assign hi_573 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_574; // @[Debug.scala:1702:60] assign hi_574 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_575; // @[Debug.scala:1702:60] assign hi_575 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_576; // @[Debug.scala:1702:60] assign hi_576 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_577; // @[Debug.scala:1702:60] assign hi_577 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_578; // @[Debug.scala:1702:60] assign hi_578 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_579; // @[Debug.scala:1702:60] assign hi_579 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_580; // @[Debug.scala:1702:60] assign hi_580 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_581; // @[Debug.scala:1702:60] assign hi_581 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_582; // @[Debug.scala:1702:60] assign hi_582 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_583; // @[Debug.scala:1702:60] assign hi_583 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_584; // @[Debug.scala:1702:60] assign hi_584 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_585; // @[Debug.scala:1702:60] assign hi_585 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_586; // @[Debug.scala:1702:60] assign hi_586 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_587; // @[Debug.scala:1702:60] assign hi_587 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_588; // @[Debug.scala:1702:60] assign hi_588 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_589; // @[Debug.scala:1702:60] assign hi_589 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_590; // @[Debug.scala:1702:60] assign hi_590 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_591; // @[Debug.scala:1702:60] assign hi_591 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_592; // @[Debug.scala:1702:60] assign hi_592 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_593; // @[Debug.scala:1702:60] assign hi_593 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_594; // @[Debug.scala:1702:60] assign hi_594 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_595; // @[Debug.scala:1702:60] assign hi_595 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_596; // @[Debug.scala:1702:60] assign hi_596 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_597; // @[Debug.scala:1702:60] assign hi_597 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_598; // @[Debug.scala:1702:60] assign hi_598 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_599; // @[Debug.scala:1702:60] assign hi_599 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_600; // @[Debug.scala:1702:60] assign hi_600 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_601; // @[Debug.scala:1702:60] assign hi_601 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_602; // @[Debug.scala:1702:60] assign hi_602 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_603; // @[Debug.scala:1702:60] assign hi_603 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_604; // @[Debug.scala:1702:60] assign hi_604 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_605; // @[Debug.scala:1702:60] assign hi_605 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_606; // @[Debug.scala:1702:60] assign hi_606 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_607; // @[Debug.scala:1702:60] assign hi_607 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_608; // @[Debug.scala:1702:60] assign hi_608 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_609; // @[Debug.scala:1702:60] assign hi_609 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_610; // @[Debug.scala:1702:60] assign hi_610 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_611; // @[Debug.scala:1702:60] assign hi_611 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_612; // @[Debug.scala:1702:60] assign hi_612 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_613; // @[Debug.scala:1702:60] assign hi_613 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_614; // @[Debug.scala:1702:60] assign hi_614 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_615; // @[Debug.scala:1702:60] assign hi_615 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_616; // @[Debug.scala:1702:60] assign hi_616 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_617; // @[Debug.scala:1702:60] assign hi_617 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_618; // @[Debug.scala:1702:60] assign hi_618 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_619; // @[Debug.scala:1702:60] assign hi_619 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_620; // @[Debug.scala:1702:60] assign hi_620 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_621; // @[Debug.scala:1702:60] assign hi_621 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_622; // @[Debug.scala:1702:60] assign hi_622 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_623; // @[Debug.scala:1702:60] assign hi_623 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_624; // @[Debug.scala:1702:60] assign hi_624 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_625; // @[Debug.scala:1702:60] assign hi_625 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_626; // @[Debug.scala:1702:60] assign hi_626 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_627; // @[Debug.scala:1702:60] assign hi_627 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_628; // @[Debug.scala:1702:60] assign hi_628 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_629; // @[Debug.scala:1702:60] assign hi_629 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_630; // @[Debug.scala:1702:60] assign hi_630 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_631; // @[Debug.scala:1702:60] assign hi_631 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_632; // @[Debug.scala:1702:60] assign hi_632 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_633; // @[Debug.scala:1702:60] assign hi_633 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_634; // @[Debug.scala:1702:60] assign hi_634 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_635; // @[Debug.scala:1702:60] assign hi_635 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_636; // @[Debug.scala:1702:60] assign hi_636 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_637; // @[Debug.scala:1702:60] assign hi_637 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_638; // @[Debug.scala:1702:60] assign hi_638 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_639; // @[Debug.scala:1702:60] assign hi_639 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_640; // @[Debug.scala:1702:60] assign hi_640 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_641; // @[Debug.scala:1702:60] assign hi_641 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_642; // @[Debug.scala:1702:60] assign hi_642 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_643; // @[Debug.scala:1702:60] assign hi_643 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_644; // @[Debug.scala:1702:60] assign hi_644 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_645; // @[Debug.scala:1702:60] assign hi_645 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_646; // @[Debug.scala:1702:60] assign hi_646 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_647; // @[Debug.scala:1702:60] assign hi_647 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_648; // @[Debug.scala:1702:60] assign hi_648 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_649; // @[Debug.scala:1702:60] assign hi_649 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_650; // @[Debug.scala:1702:60] assign hi_650 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_651; // @[Debug.scala:1702:60] assign hi_651 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_652; // @[Debug.scala:1702:60] assign hi_652 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_653; // @[Debug.scala:1702:60] assign hi_653 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_654; // @[Debug.scala:1702:60] assign hi_654 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_655; // @[Debug.scala:1702:60] assign hi_655 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_656; // @[Debug.scala:1702:60] assign hi_656 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_657; // @[Debug.scala:1702:60] assign hi_657 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_658; // @[Debug.scala:1702:60] assign hi_658 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_659; // @[Debug.scala:1702:60] assign hi_659 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_660; // @[Debug.scala:1702:60] assign hi_660 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_661; // @[Debug.scala:1702:60] assign hi_661 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_662; // @[Debug.scala:1702:60] assign hi_662 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_663; // @[Debug.scala:1702:60] assign hi_663 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_664; // @[Debug.scala:1702:60] assign hi_664 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_665; // @[Debug.scala:1702:60] assign hi_665 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_666; // @[Debug.scala:1702:60] assign hi_666 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_667; // @[Debug.scala:1702:60] assign hi_667 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_668; // @[Debug.scala:1702:60] assign hi_668 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_669; // @[Debug.scala:1702:60] assign hi_669 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_670; // @[Debug.scala:1702:60] assign hi_670 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_671; // @[Debug.scala:1702:60] assign hi_671 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_672; // @[Debug.scala:1702:60] assign hi_672 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_673; // @[Debug.scala:1702:60] assign hi_673 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_674; // @[Debug.scala:1702:60] assign hi_674 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_675; // @[Debug.scala:1702:60] assign hi_675 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_676; // @[Debug.scala:1702:60] assign hi_676 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_677; // @[Debug.scala:1702:60] assign hi_677 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_678; // @[Debug.scala:1702:60] assign hi_678 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_679; // @[Debug.scala:1702:60] assign hi_679 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_680; // @[Debug.scala:1702:60] assign hi_680 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_681; // @[Debug.scala:1702:60] assign hi_681 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_682; // @[Debug.scala:1702:60] assign hi_682 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_683; // @[Debug.scala:1702:60] assign hi_683 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_684; // @[Debug.scala:1702:60] assign hi_684 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_685; // @[Debug.scala:1702:60] assign hi_685 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_686; // @[Debug.scala:1702:60] assign hi_686 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_687; // @[Debug.scala:1702:60] assign hi_687 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_688; // @[Debug.scala:1702:60] assign hi_688 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_689; // @[Debug.scala:1702:60] assign hi_689 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_690; // @[Debug.scala:1702:60] assign hi_690 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_691; // @[Debug.scala:1702:60] assign hi_691 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_692; // @[Debug.scala:1702:60] assign hi_692 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_693; // @[Debug.scala:1702:60] assign hi_693 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_694; // @[Debug.scala:1702:60] assign hi_694 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_695; // @[Debug.scala:1702:60] assign hi_695 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_696; // @[Debug.scala:1702:60] assign hi_696 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_697; // @[Debug.scala:1702:60] assign hi_697 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_698; // @[Debug.scala:1702:60] assign hi_698 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_699; // @[Debug.scala:1702:60] assign hi_699 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_700; // @[Debug.scala:1702:60] assign hi_700 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_701; // @[Debug.scala:1702:60] assign hi_701 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_702; // @[Debug.scala:1702:60] assign hi_702 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_703; // @[Debug.scala:1702:60] assign hi_703 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_704; // @[Debug.scala:1702:60] assign hi_704 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_705; // @[Debug.scala:1702:60] assign hi_705 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_706; // @[Debug.scala:1702:60] assign hi_706 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_707; // @[Debug.scala:1702:60] assign hi_707 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_708; // @[Debug.scala:1702:60] assign hi_708 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_709; // @[Debug.scala:1702:60] assign hi_709 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_710; // @[Debug.scala:1702:60] assign hi_710 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_711; // @[Debug.scala:1702:60] assign hi_711 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_712; // @[Debug.scala:1702:60] assign hi_712 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_713; // @[Debug.scala:1702:60] assign hi_713 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_714; // @[Debug.scala:1702:60] assign hi_714 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_715; // @[Debug.scala:1702:60] assign hi_715 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_716; // @[Debug.scala:1702:60] assign hi_716 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_717; // @[Debug.scala:1702:60] assign hi_717 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_718; // @[Debug.scala:1702:60] assign hi_718 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_719; // @[Debug.scala:1702:60] assign hi_719 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_720; // @[Debug.scala:1702:60] assign hi_720 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_721; // @[Debug.scala:1702:60] assign hi_721 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_722; // @[Debug.scala:1702:60] assign hi_722 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_723; // @[Debug.scala:1702:60] assign hi_723 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_724; // @[Debug.scala:1702:60] assign hi_724 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_725; // @[Debug.scala:1702:60] assign hi_725 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_726; // @[Debug.scala:1702:60] assign hi_726 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_727; // @[Debug.scala:1702:60] assign hi_727 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_728; // @[Debug.scala:1702:60] assign hi_728 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_729; // @[Debug.scala:1702:60] assign hi_729 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_730; // @[Debug.scala:1702:60] assign hi_730 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_731; // @[Debug.scala:1702:60] assign hi_731 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_732; // @[Debug.scala:1702:60] assign hi_732 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_733; // @[Debug.scala:1702:60] assign hi_733 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_734; // @[Debug.scala:1702:60] assign hi_734 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_735; // @[Debug.scala:1702:60] assign hi_735 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_736; // @[Debug.scala:1702:60] assign hi_736 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_737; // @[Debug.scala:1702:60] assign hi_737 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_738; // @[Debug.scala:1702:60] assign hi_738 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_739; // @[Debug.scala:1702:60] assign hi_739 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_740; // @[Debug.scala:1702:60] assign hi_740 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_741; // @[Debug.scala:1702:60] assign hi_741 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_742; // @[Debug.scala:1702:60] assign hi_742 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_743; // @[Debug.scala:1702:60] assign hi_743 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_744; // @[Debug.scala:1702:60] assign hi_744 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_745; // @[Debug.scala:1702:60] assign hi_745 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_746; // @[Debug.scala:1702:60] assign hi_746 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_747; // @[Debug.scala:1702:60] assign hi_747 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_748; // @[Debug.scala:1702:60] assign hi_748 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_749; // @[Debug.scala:1702:60] assign hi_749 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_750; // @[Debug.scala:1702:60] assign hi_750 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_751; // @[Debug.scala:1702:60] assign hi_751 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_752; // @[Debug.scala:1702:60] assign hi_752 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_753; // @[Debug.scala:1702:60] assign hi_753 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_754; // @[Debug.scala:1702:60] assign hi_754 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_755; // @[Debug.scala:1702:60] assign hi_755 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_756; // @[Debug.scala:1702:60] assign hi_756 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_757; // @[Debug.scala:1702:60] assign hi_757 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_758; // @[Debug.scala:1702:60] assign hi_758 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_759; // @[Debug.scala:1702:60] assign hi_759 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_760; // @[Debug.scala:1702:60] assign hi_760 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_761; // @[Debug.scala:1702:60] assign hi_761 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_762; // @[Debug.scala:1702:60] assign hi_762 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_763; // @[Debug.scala:1702:60] assign hi_763 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_764; // @[Debug.scala:1702:60] assign hi_764 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_765; // @[Debug.scala:1702:60] assign hi_765 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_766; // @[Debug.scala:1702:60] assign hi_766 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_767; // @[Debug.scala:1702:60] assign hi_767 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_768; // @[Debug.scala:1702:60] assign hi_768 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_769; // @[Debug.scala:1702:60] assign hi_769 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_770; // @[Debug.scala:1702:60] assign hi_770 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_771; // @[Debug.scala:1702:60] assign hi_771 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_772; // @[Debug.scala:1702:60] assign hi_772 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_773; // @[Debug.scala:1702:60] assign hi_773 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_774; // @[Debug.scala:1702:60] assign hi_774 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_775; // @[Debug.scala:1702:60] assign hi_775 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_776; // @[Debug.scala:1702:60] assign hi_776 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_777; // @[Debug.scala:1702:60] assign hi_777 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_778; // @[Debug.scala:1702:60] assign hi_778 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_779; // @[Debug.scala:1702:60] assign hi_779 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_780; // @[Debug.scala:1702:60] assign hi_780 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_781; // @[Debug.scala:1702:60] assign hi_781 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_782; // @[Debug.scala:1702:60] assign hi_782 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_783; // @[Debug.scala:1702:60] assign hi_783 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_784; // @[Debug.scala:1702:60] assign hi_784 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_785; // @[Debug.scala:1702:60] assign hi_785 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_786; // @[Debug.scala:1702:60] assign hi_786 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_787; // @[Debug.scala:1702:60] assign hi_787 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_788; // @[Debug.scala:1702:60] assign hi_788 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_789; // @[Debug.scala:1702:60] assign hi_789 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_790; // @[Debug.scala:1702:60] assign hi_790 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_791; // @[Debug.scala:1702:60] assign hi_791 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_792; // @[Debug.scala:1702:60] assign hi_792 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_793; // @[Debug.scala:1702:60] assign hi_793 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_794; // @[Debug.scala:1702:60] assign hi_794 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_795; // @[Debug.scala:1702:60] assign hi_795 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_796; // @[Debug.scala:1702:60] assign hi_796 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_797; // @[Debug.scala:1702:60] assign hi_797 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_798; // @[Debug.scala:1702:60] assign hi_798 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_799; // @[Debug.scala:1702:60] assign hi_799 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_800; // @[Debug.scala:1702:60] assign hi_800 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_801; // @[Debug.scala:1702:60] assign hi_801 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_802; // @[Debug.scala:1702:60] assign hi_802 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_803; // @[Debug.scala:1702:60] assign hi_803 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_804; // @[Debug.scala:1702:60] assign hi_804 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_805; // @[Debug.scala:1702:60] assign hi_805 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_806; // @[Debug.scala:1702:60] assign hi_806 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_807; // @[Debug.scala:1702:60] assign hi_807 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_808; // @[Debug.scala:1702:60] assign hi_808 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_809; // @[Debug.scala:1702:60] assign hi_809 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_810; // @[Debug.scala:1702:60] assign hi_810 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_811; // @[Debug.scala:1702:60] assign hi_811 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_812; // @[Debug.scala:1702:60] assign hi_812 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_813; // @[Debug.scala:1702:60] assign hi_813 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_814; // @[Debug.scala:1702:60] assign hi_814 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_815; // @[Debug.scala:1702:60] assign hi_815 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_816; // @[Debug.scala:1702:60] assign hi_816 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_817; // @[Debug.scala:1702:60] assign hi_817 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_818; // @[Debug.scala:1702:60] assign hi_818 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_819; // @[Debug.scala:1702:60] assign hi_819 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_820; // @[Debug.scala:1702:60] assign hi_820 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_821; // @[Debug.scala:1702:60] assign hi_821 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_822; // @[Debug.scala:1702:60] assign hi_822 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_823; // @[Debug.scala:1702:60] assign hi_823 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_824; // @[Debug.scala:1702:60] assign hi_824 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_825; // @[Debug.scala:1702:60] assign hi_825 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_826; // @[Debug.scala:1702:60] assign hi_826 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_827; // @[Debug.scala:1702:60] assign hi_827 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_828; // @[Debug.scala:1702:60] assign hi_828 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_829; // @[Debug.scala:1702:60] assign hi_829 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_830; // @[Debug.scala:1702:60] assign hi_830 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_831; // @[Debug.scala:1702:60] assign hi_831 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_832; // @[Debug.scala:1702:60] assign hi_832 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_833; // @[Debug.scala:1702:60] assign hi_833 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_834; // @[Debug.scala:1702:60] assign hi_834 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_835; // @[Debug.scala:1702:60] assign hi_835 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_836; // @[Debug.scala:1702:60] assign hi_836 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_837; // @[Debug.scala:1702:60] assign hi_837 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_838; // @[Debug.scala:1702:60] assign hi_838 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_839; // @[Debug.scala:1702:60] assign hi_839 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_840; // @[Debug.scala:1702:60] assign hi_840 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_841; // @[Debug.scala:1702:60] assign hi_841 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_842; // @[Debug.scala:1702:60] assign hi_842 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_843; // @[Debug.scala:1702:60] assign hi_843 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_844; // @[Debug.scala:1702:60] assign hi_844 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_845; // @[Debug.scala:1702:60] assign hi_845 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_846; // @[Debug.scala:1702:60] assign hi_846 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_847; // @[Debug.scala:1702:60] assign hi_847 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_848; // @[Debug.scala:1702:60] assign hi_848 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_849; // @[Debug.scala:1702:60] assign hi_849 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_850; // @[Debug.scala:1702:60] assign hi_850 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_851; // @[Debug.scala:1702:60] assign hi_851 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_852; // @[Debug.scala:1702:60] assign hi_852 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_853; // @[Debug.scala:1702:60] assign hi_853 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_854; // @[Debug.scala:1702:60] assign hi_854 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_855; // @[Debug.scala:1702:60] assign hi_855 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_856; // @[Debug.scala:1702:60] assign hi_856 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_857; // @[Debug.scala:1702:60] assign hi_857 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_858; // @[Debug.scala:1702:60] assign hi_858 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_859; // @[Debug.scala:1702:60] assign hi_859 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_860; // @[Debug.scala:1702:60] assign hi_860 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_861; // @[Debug.scala:1702:60] assign hi_861 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_862; // @[Debug.scala:1702:60] assign hi_862 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_863; // @[Debug.scala:1702:60] assign hi_863 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_864; // @[Debug.scala:1702:60] assign hi_864 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_865; // @[Debug.scala:1702:60] assign hi_865 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_866; // @[Debug.scala:1702:60] assign hi_866 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_867; // @[Debug.scala:1702:60] assign hi_867 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_868; // @[Debug.scala:1702:60] assign hi_868 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_869; // @[Debug.scala:1702:60] assign hi_869 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_870; // @[Debug.scala:1702:60] assign hi_870 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_871; // @[Debug.scala:1702:60] assign hi_871 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_872; // @[Debug.scala:1702:60] assign hi_872 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_873; // @[Debug.scala:1702:60] assign hi_873 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_874; // @[Debug.scala:1702:60] assign hi_874 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_875; // @[Debug.scala:1702:60] assign hi_875 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_876; // @[Debug.scala:1702:60] assign hi_876 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_877; // @[Debug.scala:1702:60] assign hi_877 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_878; // @[Debug.scala:1702:60] assign hi_878 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_879; // @[Debug.scala:1702:60] assign hi_879 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_880; // @[Debug.scala:1702:60] assign hi_880 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_881; // @[Debug.scala:1702:60] assign hi_881 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_882; // @[Debug.scala:1702:60] assign hi_882 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_883; // @[Debug.scala:1702:60] assign hi_883 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_884; // @[Debug.scala:1702:60] assign hi_884 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_885; // @[Debug.scala:1702:60] assign hi_885 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_886; // @[Debug.scala:1702:60] assign hi_886 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_887; // @[Debug.scala:1702:60] assign hi_887 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_888; // @[Debug.scala:1702:60] assign hi_888 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_889; // @[Debug.scala:1702:60] assign hi_889 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_890; // @[Debug.scala:1702:60] assign hi_890 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_891; // @[Debug.scala:1702:60] assign hi_891 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_892; // @[Debug.scala:1702:60] assign hi_892 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_893; // @[Debug.scala:1702:60] assign hi_893 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_894; // @[Debug.scala:1702:60] assign hi_894 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_895; // @[Debug.scala:1702:60] assign hi_895 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_896; // @[Debug.scala:1702:60] assign hi_896 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_897; // @[Debug.scala:1702:60] assign hi_897 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_898; // @[Debug.scala:1702:60] assign hi_898 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_899; // @[Debug.scala:1702:60] assign hi_899 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_900; // @[Debug.scala:1702:60] assign hi_900 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_901; // @[Debug.scala:1702:60] assign hi_901 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_902; // @[Debug.scala:1702:60] assign hi_902 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_903; // @[Debug.scala:1702:60] assign hi_903 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_904; // @[Debug.scala:1702:60] assign hi_904 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_905; // @[Debug.scala:1702:60] assign hi_905 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_906; // @[Debug.scala:1702:60] assign hi_906 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_907; // @[Debug.scala:1702:60] assign hi_907 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_908; // @[Debug.scala:1702:60] assign hi_908 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_909; // @[Debug.scala:1702:60] assign hi_909 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_910; // @[Debug.scala:1702:60] assign hi_910 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_911; // @[Debug.scala:1702:60] assign hi_911 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_912; // @[Debug.scala:1702:60] assign hi_912 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_913; // @[Debug.scala:1702:60] assign hi_913 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_914; // @[Debug.scala:1702:60] assign hi_914 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_915; // @[Debug.scala:1702:60] assign hi_915 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_916; // @[Debug.scala:1702:60] assign hi_916 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_917; // @[Debug.scala:1702:60] assign hi_917 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_918; // @[Debug.scala:1702:60] assign hi_918 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_919; // @[Debug.scala:1702:60] assign hi_919 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_920; // @[Debug.scala:1702:60] assign hi_920 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_921; // @[Debug.scala:1702:60] assign hi_921 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_922; // @[Debug.scala:1702:60] assign hi_922 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_923; // @[Debug.scala:1702:60] assign hi_923 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_924; // @[Debug.scala:1702:60] assign hi_924 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_925; // @[Debug.scala:1702:60] assign hi_925 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_926; // @[Debug.scala:1702:60] assign hi_926 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_927; // @[Debug.scala:1702:60] assign hi_927 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_928; // @[Debug.scala:1702:60] assign hi_928 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_929; // @[Debug.scala:1702:60] assign hi_929 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_930; // @[Debug.scala:1702:60] assign hi_930 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_931; // @[Debug.scala:1702:60] assign hi_931 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_932; // @[Debug.scala:1702:60] assign hi_932 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_933; // @[Debug.scala:1702:60] assign hi_933 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_934; // @[Debug.scala:1702:60] assign hi_934 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_935; // @[Debug.scala:1702:60] assign hi_935 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_936; // @[Debug.scala:1702:60] assign hi_936 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_937; // @[Debug.scala:1702:60] assign hi_937 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_938; // @[Debug.scala:1702:60] assign hi_938 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_939; // @[Debug.scala:1702:60] assign hi_939 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_940; // @[Debug.scala:1702:60] assign hi_940 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_941; // @[Debug.scala:1702:60] assign hi_941 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_942; // @[Debug.scala:1702:60] assign hi_942 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_943; // @[Debug.scala:1702:60] assign hi_943 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_944; // @[Debug.scala:1702:60] assign hi_944 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_945; // @[Debug.scala:1702:60] assign hi_945 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_946; // @[Debug.scala:1702:60] assign hi_946 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_947; // @[Debug.scala:1702:60] assign hi_947 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_948; // @[Debug.scala:1702:60] assign hi_948 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_949; // @[Debug.scala:1702:60] assign hi_949 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_950; // @[Debug.scala:1702:60] assign hi_950 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_951; // @[Debug.scala:1702:60] assign hi_951 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_952; // @[Debug.scala:1702:60] assign hi_952 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_953; // @[Debug.scala:1702:60] assign hi_953 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_954; // @[Debug.scala:1702:60] assign hi_954 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_955; // @[Debug.scala:1702:60] assign hi_955 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_956; // @[Debug.scala:1702:60] assign hi_956 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_957; // @[Debug.scala:1702:60] assign hi_957 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_958; // @[Debug.scala:1702:60] assign hi_958 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_959; // @[Debug.scala:1702:60] assign hi_959 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_960; // @[Debug.scala:1702:60] assign hi_960 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_961; // @[Debug.scala:1702:60] assign hi_961 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_962; // @[Debug.scala:1702:60] assign hi_962 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_963; // @[Debug.scala:1702:60] assign hi_963 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_964; // @[Debug.scala:1702:60] assign hi_964 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_965; // @[Debug.scala:1702:60] assign hi_965 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_966; // @[Debug.scala:1702:60] assign hi_966 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_967; // @[Debug.scala:1702:60] assign hi_967 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_968; // @[Debug.scala:1702:60] assign hi_968 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_969; // @[Debug.scala:1702:60] assign hi_969 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_970; // @[Debug.scala:1702:60] assign hi_970 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_971; // @[Debug.scala:1702:60] assign hi_971 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_972; // @[Debug.scala:1702:60] assign hi_972 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_973; // @[Debug.scala:1702:60] assign hi_973 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_974; // @[Debug.scala:1702:60] assign hi_974 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_975; // @[Debug.scala:1702:60] assign hi_975 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_976; // @[Debug.scala:1702:60] assign hi_976 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_977; // @[Debug.scala:1702:60] assign hi_977 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_978; // @[Debug.scala:1702:60] assign hi_978 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_979; // @[Debug.scala:1702:60] assign hi_979 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_980; // @[Debug.scala:1702:60] assign hi_980 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_981; // @[Debug.scala:1702:60] assign hi_981 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_982; // @[Debug.scala:1702:60] assign hi_982 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_983; // @[Debug.scala:1702:60] assign hi_983 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_984; // @[Debug.scala:1702:60] assign hi_984 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_985; // @[Debug.scala:1702:60] assign hi_985 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_986; // @[Debug.scala:1702:60] assign hi_986 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_987; // @[Debug.scala:1702:60] assign hi_987 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_988; // @[Debug.scala:1702:60] assign hi_988 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_989; // @[Debug.scala:1702:60] assign hi_989 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_990; // @[Debug.scala:1702:60] assign hi_990 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_991; // @[Debug.scala:1702:60] assign hi_991 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_992; // @[Debug.scala:1702:60] assign hi_992 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_993; // @[Debug.scala:1702:60] assign hi_993 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_994; // @[Debug.scala:1702:60] assign hi_994 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_995; // @[Debug.scala:1702:60] assign hi_995 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_996; // @[Debug.scala:1702:60] assign hi_996 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_997; // @[Debug.scala:1702:60] assign hi_997 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_998; // @[Debug.scala:1702:60] assign hi_998 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_999; // @[Debug.scala:1702:60] assign hi_999 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1000; // @[Debug.scala:1702:60] assign hi_1000 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1001; // @[Debug.scala:1702:60] assign hi_1001 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1002; // @[Debug.scala:1702:60] assign hi_1002 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1003; // @[Debug.scala:1702:60] assign hi_1003 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1004; // @[Debug.scala:1702:60] assign hi_1004 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1005; // @[Debug.scala:1702:60] assign hi_1005 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1006; // @[Debug.scala:1702:60] assign hi_1006 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1007; // @[Debug.scala:1702:60] assign hi_1007 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1008; // @[Debug.scala:1702:60] assign hi_1008 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1009; // @[Debug.scala:1702:60] assign hi_1009 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1010; // @[Debug.scala:1702:60] assign hi_1010 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1011; // @[Debug.scala:1702:60] assign hi_1011 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1012; // @[Debug.scala:1702:60] assign hi_1012 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1013; // @[Debug.scala:1702:60] assign hi_1013 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1014; // @[Debug.scala:1702:60] assign hi_1014 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1015; // @[Debug.scala:1702:60] assign hi_1015 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1016; // @[Debug.scala:1702:60] assign hi_1016 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1017; // @[Debug.scala:1702:60] assign hi_1017 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1018; // @[Debug.scala:1702:60] assign hi_1018 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1019; // @[Debug.scala:1702:60] assign hi_1019 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1020; // @[Debug.scala:1702:60] assign hi_1020 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1021; // @[Debug.scala:1702:60] assign hi_1021 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1022; // @[Debug.scala:1702:60] assign hi_1022 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1023; // @[Debug.scala:1702:60] assign hi_1023 = _GEN_16; // @[Debug.scala:1702:60] wire [6:0] hi_1024; // @[Debug.scala:1702:60] assign hi_1024 = _GEN_16; // @[Debug.scala:1702:60] wire [7:0] _out_T_6436 = {hi_1, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6184 = {hi_9, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8824 = {hi_17, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12272 = {hi_25, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4125 = {hi_33, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4197 = {hi_41, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6256 = {hi_49, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8968 = {hi_57, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11984 = {hi_65, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4989 = {hi_73, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1917 = {hi_81, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11032 = {hi_89, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8304 = {hi_97, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5655 = {hi_105, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2509 = {hi_113, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10208 = {hi_121, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7478 = {hi_129, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9632 = {hi_137, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11464 = {hi_145, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3981 = {hi_153, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6830 = {hi_161, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7118 = {hi_169, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9704 = {hi_177, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11392 = {hi_185, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3245 = {hi_193, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2581 = {hi_201, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10064 = {hi_209, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8448 = {hi_217, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5439 = {hi_225, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3101 = {hi_233, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10728 = {hi_241, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7694 = {hi_249, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4845 = {hi_257, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6974 = {hi_265, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9256 = {hi_273, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12416 = {hi_281, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3533 = {hi_289, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5061 = {hi_297, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6740 = {hi_305, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9184 = {hi_313, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11680 = {hi_321, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5583 = {hi_329, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2133 = {hi_337, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10960 = {hi_345, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7838 = {hi_353, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6112 = {hi_361, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2653 = {hi_369, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10136 = {hi_377, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7190 = {hi_385, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9920 = {hi_393, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12344 = {hi_401, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3605 = {hi_409, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7046 = {hi_417, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7622 = {hi_425, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9992 = {hi_433, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11608 = {hi_441, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2869 = {hi_449, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2725 = {hi_457, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10800 = {hi_465, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7766 = {hi_473, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5511 = {hi_481, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3173 = {hi_489, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11536 = {hi_497, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7262 = {hi_505, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4917 = {hi_513, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5799 = {hi_521, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9560 = {hi_529, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12056 = {hi_537, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3029 = {hi_545, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5295 = {hi_553, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8520 = {hi_561, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9848 = {hi_569, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12488 = {hi_577, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4629 = {hi_585, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2437 = {hi_593, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10280 = {hi_601, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7334 = {hi_609, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6364 = {hi_617, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4413 = {hi_625, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11104 = {hi_633, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8214 = {hi_641, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9400 = {hi_649, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11824 = {hi_657, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3837 = {hi_665, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5871 = {hi_673, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8376 = {hi_681, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11176 = {hi_689, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12648 = {hi_697, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3461 = {hi_705, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2293 = {hi_713, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10352 = {hi_721, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7998 = {hi_729, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4701 = {hi_737, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4053 = {hi_745, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12720 = {hi_753, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8896 = {hi_761, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5367 = {hi_769, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5727 = {hi_777, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9040 = {hi_785, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12936 = {hi_793, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3317 = {hi_801, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5151 = {hi_809, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8070 = {hi_817, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10584 = {hi_825, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12792 = {hi_833, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4485 = {hi_841, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2061 = {hi_849, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11248 = {hi_857, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7550 = {hi_865, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6508 = {hi_873, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3765 = {hi_881, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12128 = {hi_889, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8680 = {hi_897, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9112 = {hi_905, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12200 = {hi_913, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4269 = {hi_921, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6668 = {hi_929, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8142 = {hi_937, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11320 = {hi_945, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2365 = {hi_953, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4557 = {hi_961, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1989 = {hi_969, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10512 = {hi_977, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8752 = {hi_985, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5223 = {hi_993, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3909 = {hi_1001, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12864 = {hi_1009, flags_0_go}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9328 = {hi_1017, flags_0_go}; // @[RegisterRouter.scala:87:24] wire _out_in_ready_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_1_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T_1; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T_1 = in_1_valid; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] _in_bits_index_T_1; // @[Edges.scala:192:34] wire out_front_1_bits_read = in_1_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_1_bits_index = in_1_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_1_bits_data = in_1_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_1_bits_mask = in_1_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_1_bits_extra_tlrr_extra_source = in_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_1_bits_extra_tlrr_extra_size = in_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T_1 = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_1_bits_read = _in_bits_read_T_1; // @[RegisterRouter.scala:73:18, :74:36] assign _in_bits_index_T_1 = tlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34] assign in_1_bits_index = _in_bits_index_T_1; // @[RegisterRouter.scala:73:18] wire _out_front_ready_T_1 = out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_1_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_data = out_1_bits_data; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_source = out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T_1 = out_front_1_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T_1 = out_front_1_valid; // @[RegisterRouter.scala:87:24] assign out_1_bits_read = out_front_1_bits_read; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_source = out_front_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_1_bits_extra_tlrr_extra_size = out_front_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN_17 = out_front_1_bits_index & 9'h100; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex_1; // @[RegisterRouter.scala:87:24] assign out_findex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex_1; // @[RegisterRouter.scala:87:24] assign out_bindex_1 = _GEN_17; // @[RegisterRouter.scala:87:24] wire _GEN_18 = out_findex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1600; // @[RegisterRouter.scala:87:24] assign _out_T_1600 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1602; // @[RegisterRouter.scala:87:24] assign _out_T_1602 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1604; // @[RegisterRouter.scala:87:24] assign _out_T_1604 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1606; // @[RegisterRouter.scala:87:24] assign _out_T_1606 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1608; // @[RegisterRouter.scala:87:24] assign _out_T_1608 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1610; // @[RegisterRouter.scala:87:24] assign _out_T_1610 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1612; // @[RegisterRouter.scala:87:24] assign _out_T_1612 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1614; // @[RegisterRouter.scala:87:24] assign _out_T_1614 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1616; // @[RegisterRouter.scala:87:24] assign _out_T_1616 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1618; // @[RegisterRouter.scala:87:24] assign _out_T_1618 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1620; // @[RegisterRouter.scala:87:24] assign _out_T_1620 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1622; // @[RegisterRouter.scala:87:24] assign _out_T_1622 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1626; // @[RegisterRouter.scala:87:24] assign _out_T_1626 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1628; // @[RegisterRouter.scala:87:24] assign _out_T_1628 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1630; // @[RegisterRouter.scala:87:24] assign _out_T_1630 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1632; // @[RegisterRouter.scala:87:24] assign _out_T_1632 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1634; // @[RegisterRouter.scala:87:24] assign _out_T_1634 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1636; // @[RegisterRouter.scala:87:24] assign _out_T_1636 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1638; // @[RegisterRouter.scala:87:24] assign _out_T_1638 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1642; // @[RegisterRouter.scala:87:24] assign _out_T_1642 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1644; // @[RegisterRouter.scala:87:24] assign _out_T_1644 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1646; // @[RegisterRouter.scala:87:24] assign _out_T_1646 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1648; // @[RegisterRouter.scala:87:24] assign _out_T_1648 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1650; // @[RegisterRouter.scala:87:24] assign _out_T_1650 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1652; // @[RegisterRouter.scala:87:24] assign _out_T_1652 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1654; // @[RegisterRouter.scala:87:24] assign _out_T_1654 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1656; // @[RegisterRouter.scala:87:24] assign _out_T_1656 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1658; // @[RegisterRouter.scala:87:24] assign _out_T_1658 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1660; // @[RegisterRouter.scala:87:24] assign _out_T_1660 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1662; // @[RegisterRouter.scala:87:24] assign _out_T_1662 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1664; // @[RegisterRouter.scala:87:24] assign _out_T_1664 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1668; // @[RegisterRouter.scala:87:24] assign _out_T_1668 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1670; // @[RegisterRouter.scala:87:24] assign _out_T_1670 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1672; // @[RegisterRouter.scala:87:24] assign _out_T_1672 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1674; // @[RegisterRouter.scala:87:24] assign _out_T_1674 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1676; // @[RegisterRouter.scala:87:24] assign _out_T_1676 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1680; // @[RegisterRouter.scala:87:24] assign _out_T_1680 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1682; // @[RegisterRouter.scala:87:24] assign _out_T_1682 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1684; // @[RegisterRouter.scala:87:24] assign _out_T_1684 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1686; // @[RegisterRouter.scala:87:24] assign _out_T_1686 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1688; // @[RegisterRouter.scala:87:24] assign _out_T_1688 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1690; // @[RegisterRouter.scala:87:24] assign _out_T_1690 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1692; // @[RegisterRouter.scala:87:24] assign _out_T_1692 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1694; // @[RegisterRouter.scala:87:24] assign _out_T_1694 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1696; // @[RegisterRouter.scala:87:24] assign _out_T_1696 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1698; // @[RegisterRouter.scala:87:24] assign _out_T_1698 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1700; // @[RegisterRouter.scala:87:24] assign _out_T_1700 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1702; // @[RegisterRouter.scala:87:24] assign _out_T_1702 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1704; // @[RegisterRouter.scala:87:24] assign _out_T_1704 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1706; // @[RegisterRouter.scala:87:24] assign _out_T_1706 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1708; // @[RegisterRouter.scala:87:24] assign _out_T_1708 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1710; // @[RegisterRouter.scala:87:24] assign _out_T_1710 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1712; // @[RegisterRouter.scala:87:24] assign _out_T_1712 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1714; // @[RegisterRouter.scala:87:24] assign _out_T_1714 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1718; // @[RegisterRouter.scala:87:24] assign _out_T_1718 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1720; // @[RegisterRouter.scala:87:24] assign _out_T_1720 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1722; // @[RegisterRouter.scala:87:24] assign _out_T_1722 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1726; // @[RegisterRouter.scala:87:24] assign _out_T_1726 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1728; // @[RegisterRouter.scala:87:24] assign _out_T_1728 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1730; // @[RegisterRouter.scala:87:24] assign _out_T_1730 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1732; // @[RegisterRouter.scala:87:24] assign _out_T_1732 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1734; // @[RegisterRouter.scala:87:24] assign _out_T_1734 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1736; // @[RegisterRouter.scala:87:24] assign _out_T_1736 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1738; // @[RegisterRouter.scala:87:24] assign _out_T_1738 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1740; // @[RegisterRouter.scala:87:24] assign _out_T_1740 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1744; // @[RegisterRouter.scala:87:24] assign _out_T_1744 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1746; // @[RegisterRouter.scala:87:24] assign _out_T_1746 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1748; // @[RegisterRouter.scala:87:24] assign _out_T_1748 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1750; // @[RegisterRouter.scala:87:24] assign _out_T_1750 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1752; // @[RegisterRouter.scala:87:24] assign _out_T_1752 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1754; // @[RegisterRouter.scala:87:24] assign _out_T_1754 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1758; // @[RegisterRouter.scala:87:24] assign _out_T_1758 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1760; // @[RegisterRouter.scala:87:24] assign _out_T_1760 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1762; // @[RegisterRouter.scala:87:24] assign _out_T_1762 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1764; // @[RegisterRouter.scala:87:24] assign _out_T_1764 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1766; // @[RegisterRouter.scala:87:24] assign _out_T_1766 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1768; // @[RegisterRouter.scala:87:24] assign _out_T_1768 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1770; // @[RegisterRouter.scala:87:24] assign _out_T_1770 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1772; // @[RegisterRouter.scala:87:24] assign _out_T_1772 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1774; // @[RegisterRouter.scala:87:24] assign _out_T_1774 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1776; // @[RegisterRouter.scala:87:24] assign _out_T_1776 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1778; // @[RegisterRouter.scala:87:24] assign _out_T_1778 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1780; // @[RegisterRouter.scala:87:24] assign _out_T_1780 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1782; // @[RegisterRouter.scala:87:24] assign _out_T_1782 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1784; // @[RegisterRouter.scala:87:24] assign _out_T_1784 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1786; // @[RegisterRouter.scala:87:24] assign _out_T_1786 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1788; // @[RegisterRouter.scala:87:24] assign _out_T_1788 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1790; // @[RegisterRouter.scala:87:24] assign _out_T_1790 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1792; // @[RegisterRouter.scala:87:24] assign _out_T_1792 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1794; // @[RegisterRouter.scala:87:24] assign _out_T_1794 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1796; // @[RegisterRouter.scala:87:24] assign _out_T_1796 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1798; // @[RegisterRouter.scala:87:24] assign _out_T_1798 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1800; // @[RegisterRouter.scala:87:24] assign _out_T_1800 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1802; // @[RegisterRouter.scala:87:24] assign _out_T_1802 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1804; // @[RegisterRouter.scala:87:24] assign _out_T_1804 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1806; // @[RegisterRouter.scala:87:24] assign _out_T_1806 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1808; // @[RegisterRouter.scala:87:24] assign _out_T_1808 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1810; // @[RegisterRouter.scala:87:24] assign _out_T_1810 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1812; // @[RegisterRouter.scala:87:24] assign _out_T_1812 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1814; // @[RegisterRouter.scala:87:24] assign _out_T_1814 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1816; // @[RegisterRouter.scala:87:24] assign _out_T_1816 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1818; // @[RegisterRouter.scala:87:24] assign _out_T_1818 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1820; // @[RegisterRouter.scala:87:24] assign _out_T_1820 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1824; // @[RegisterRouter.scala:87:24] assign _out_T_1824 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1826; // @[RegisterRouter.scala:87:24] assign _out_T_1826 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1828; // @[RegisterRouter.scala:87:24] assign _out_T_1828 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1830; // @[RegisterRouter.scala:87:24] assign _out_T_1830 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1832; // @[RegisterRouter.scala:87:24] assign _out_T_1832 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1834; // @[RegisterRouter.scala:87:24] assign _out_T_1834 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1836; // @[RegisterRouter.scala:87:24] assign _out_T_1836 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1838; // @[RegisterRouter.scala:87:24] assign _out_T_1838 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1840; // @[RegisterRouter.scala:87:24] assign _out_T_1840 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1842; // @[RegisterRouter.scala:87:24] assign _out_T_1842 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1844; // @[RegisterRouter.scala:87:24] assign _out_T_1844 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1848; // @[RegisterRouter.scala:87:24] assign _out_T_1848 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1850; // @[RegisterRouter.scala:87:24] assign _out_T_1850 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1852; // @[RegisterRouter.scala:87:24] assign _out_T_1852 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1854; // @[RegisterRouter.scala:87:24] assign _out_T_1854 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1856; // @[RegisterRouter.scala:87:24] assign _out_T_1856 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1858; // @[RegisterRouter.scala:87:24] assign _out_T_1858 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1860; // @[RegisterRouter.scala:87:24] assign _out_T_1860 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1862; // @[RegisterRouter.scala:87:24] assign _out_T_1862 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1864; // @[RegisterRouter.scala:87:24] assign _out_T_1864 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1866; // @[RegisterRouter.scala:87:24] assign _out_T_1866 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1868; // @[RegisterRouter.scala:87:24] assign _out_T_1868 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1870; // @[RegisterRouter.scala:87:24] assign _out_T_1870 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1872; // @[RegisterRouter.scala:87:24] assign _out_T_1872 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1874; // @[RegisterRouter.scala:87:24] assign _out_T_1874 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1878; // @[RegisterRouter.scala:87:24] assign _out_T_1878 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1880; // @[RegisterRouter.scala:87:24] assign _out_T_1880 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1882; // @[RegisterRouter.scala:87:24] assign _out_T_1882 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1884; // @[RegisterRouter.scala:87:24] assign _out_T_1884 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1886; // @[RegisterRouter.scala:87:24] assign _out_T_1886 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1888; // @[RegisterRouter.scala:87:24] assign _out_T_1888 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1890; // @[RegisterRouter.scala:87:24] assign _out_T_1890 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1892; // @[RegisterRouter.scala:87:24] assign _out_T_1892 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1894; // @[RegisterRouter.scala:87:24] assign _out_T_1894 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1896; // @[RegisterRouter.scala:87:24] assign _out_T_1896 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1898; // @[RegisterRouter.scala:87:24] assign _out_T_1898 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1900; // @[RegisterRouter.scala:87:24] assign _out_T_1900 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1902; // @[RegisterRouter.scala:87:24] assign _out_T_1902 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1904; // @[RegisterRouter.scala:87:24] assign _out_T_1904 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1906; // @[RegisterRouter.scala:87:24] assign _out_T_1906 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _out_T_1908; // @[RegisterRouter.scala:87:24] assign _out_T_1908 = _GEN_18; // @[RegisterRouter.scala:87:24] wire _GEN_19 = out_bindex_1 == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1601; // @[RegisterRouter.scala:87:24] assign _out_T_1601 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1603; // @[RegisterRouter.scala:87:24] assign _out_T_1603 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1605; // @[RegisterRouter.scala:87:24] assign _out_T_1605 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1607; // @[RegisterRouter.scala:87:24] assign _out_T_1607 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1609; // @[RegisterRouter.scala:87:24] assign _out_T_1609 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1611; // @[RegisterRouter.scala:87:24] assign _out_T_1611 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1613; // @[RegisterRouter.scala:87:24] assign _out_T_1613 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1615; // @[RegisterRouter.scala:87:24] assign _out_T_1615 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1617; // @[RegisterRouter.scala:87:24] assign _out_T_1617 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1619; // @[RegisterRouter.scala:87:24] assign _out_T_1619 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1621; // @[RegisterRouter.scala:87:24] assign _out_T_1621 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1623; // @[RegisterRouter.scala:87:24] assign _out_T_1623 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1627; // @[RegisterRouter.scala:87:24] assign _out_T_1627 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1629; // @[RegisterRouter.scala:87:24] assign _out_T_1629 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1631; // @[RegisterRouter.scala:87:24] assign _out_T_1631 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1633; // @[RegisterRouter.scala:87:24] assign _out_T_1633 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1635; // @[RegisterRouter.scala:87:24] assign _out_T_1635 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1637; // @[RegisterRouter.scala:87:24] assign _out_T_1637 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1639; // @[RegisterRouter.scala:87:24] assign _out_T_1639 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1643; // @[RegisterRouter.scala:87:24] assign _out_T_1643 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1645; // @[RegisterRouter.scala:87:24] assign _out_T_1645 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1647; // @[RegisterRouter.scala:87:24] assign _out_T_1647 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1649; // @[RegisterRouter.scala:87:24] assign _out_T_1649 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1651; // @[RegisterRouter.scala:87:24] assign _out_T_1651 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1653; // @[RegisterRouter.scala:87:24] assign _out_T_1653 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1655; // @[RegisterRouter.scala:87:24] assign _out_T_1655 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1657; // @[RegisterRouter.scala:87:24] assign _out_T_1657 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1659; // @[RegisterRouter.scala:87:24] assign _out_T_1659 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1661; // @[RegisterRouter.scala:87:24] assign _out_T_1661 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1663; // @[RegisterRouter.scala:87:24] assign _out_T_1663 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1665; // @[RegisterRouter.scala:87:24] assign _out_T_1665 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1669; // @[RegisterRouter.scala:87:24] assign _out_T_1669 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1671; // @[RegisterRouter.scala:87:24] assign _out_T_1671 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1673; // @[RegisterRouter.scala:87:24] assign _out_T_1673 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1675; // @[RegisterRouter.scala:87:24] assign _out_T_1675 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1677; // @[RegisterRouter.scala:87:24] assign _out_T_1677 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1681; // @[RegisterRouter.scala:87:24] assign _out_T_1681 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1683; // @[RegisterRouter.scala:87:24] assign _out_T_1683 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1685; // @[RegisterRouter.scala:87:24] assign _out_T_1685 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1687; // @[RegisterRouter.scala:87:24] assign _out_T_1687 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1689; // @[RegisterRouter.scala:87:24] assign _out_T_1689 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1691; // @[RegisterRouter.scala:87:24] assign _out_T_1691 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1693; // @[RegisterRouter.scala:87:24] assign _out_T_1693 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1695; // @[RegisterRouter.scala:87:24] assign _out_T_1695 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1697; // @[RegisterRouter.scala:87:24] assign _out_T_1697 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1699; // @[RegisterRouter.scala:87:24] assign _out_T_1699 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1701; // @[RegisterRouter.scala:87:24] assign _out_T_1701 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1703; // @[RegisterRouter.scala:87:24] assign _out_T_1703 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1705; // @[RegisterRouter.scala:87:24] assign _out_T_1705 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1707; // @[RegisterRouter.scala:87:24] assign _out_T_1707 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1709; // @[RegisterRouter.scala:87:24] assign _out_T_1709 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1711; // @[RegisterRouter.scala:87:24] assign _out_T_1711 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1713; // @[RegisterRouter.scala:87:24] assign _out_T_1713 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1715; // @[RegisterRouter.scala:87:24] assign _out_T_1715 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1719; // @[RegisterRouter.scala:87:24] assign _out_T_1719 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1721; // @[RegisterRouter.scala:87:24] assign _out_T_1721 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1723; // @[RegisterRouter.scala:87:24] assign _out_T_1723 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1727; // @[RegisterRouter.scala:87:24] assign _out_T_1727 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1729; // @[RegisterRouter.scala:87:24] assign _out_T_1729 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1731; // @[RegisterRouter.scala:87:24] assign _out_T_1731 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1733; // @[RegisterRouter.scala:87:24] assign _out_T_1733 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1735; // @[RegisterRouter.scala:87:24] assign _out_T_1735 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1737; // @[RegisterRouter.scala:87:24] assign _out_T_1737 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1739; // @[RegisterRouter.scala:87:24] assign _out_T_1739 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1741; // @[RegisterRouter.scala:87:24] assign _out_T_1741 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1745; // @[RegisterRouter.scala:87:24] assign _out_T_1745 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1747; // @[RegisterRouter.scala:87:24] assign _out_T_1747 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1749; // @[RegisterRouter.scala:87:24] assign _out_T_1749 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1751; // @[RegisterRouter.scala:87:24] assign _out_T_1751 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1753; // @[RegisterRouter.scala:87:24] assign _out_T_1753 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1755; // @[RegisterRouter.scala:87:24] assign _out_T_1755 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1759; // @[RegisterRouter.scala:87:24] assign _out_T_1759 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1761; // @[RegisterRouter.scala:87:24] assign _out_T_1761 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1763; // @[RegisterRouter.scala:87:24] assign _out_T_1763 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1765; // @[RegisterRouter.scala:87:24] assign _out_T_1765 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1767; // @[RegisterRouter.scala:87:24] assign _out_T_1767 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1769; // @[RegisterRouter.scala:87:24] assign _out_T_1769 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1771; // @[RegisterRouter.scala:87:24] assign _out_T_1771 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1773; // @[RegisterRouter.scala:87:24] assign _out_T_1773 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1775; // @[RegisterRouter.scala:87:24] assign _out_T_1775 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1777; // @[RegisterRouter.scala:87:24] assign _out_T_1777 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1779; // @[RegisterRouter.scala:87:24] assign _out_T_1779 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1781; // @[RegisterRouter.scala:87:24] assign _out_T_1781 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1783; // @[RegisterRouter.scala:87:24] assign _out_T_1783 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1785; // @[RegisterRouter.scala:87:24] assign _out_T_1785 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1787; // @[RegisterRouter.scala:87:24] assign _out_T_1787 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1789; // @[RegisterRouter.scala:87:24] assign _out_T_1789 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1791; // @[RegisterRouter.scala:87:24] assign _out_T_1791 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1793; // @[RegisterRouter.scala:87:24] assign _out_T_1793 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1795; // @[RegisterRouter.scala:87:24] assign _out_T_1795 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1797; // @[RegisterRouter.scala:87:24] assign _out_T_1797 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1799; // @[RegisterRouter.scala:87:24] assign _out_T_1799 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1801; // @[RegisterRouter.scala:87:24] assign _out_T_1801 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1803; // @[RegisterRouter.scala:87:24] assign _out_T_1803 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1805; // @[RegisterRouter.scala:87:24] assign _out_T_1805 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1807; // @[RegisterRouter.scala:87:24] assign _out_T_1807 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1809; // @[RegisterRouter.scala:87:24] assign _out_T_1809 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1811; // @[RegisterRouter.scala:87:24] assign _out_T_1811 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1813; // @[RegisterRouter.scala:87:24] assign _out_T_1813 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1815; // @[RegisterRouter.scala:87:24] assign _out_T_1815 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1817; // @[RegisterRouter.scala:87:24] assign _out_T_1817 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1819; // @[RegisterRouter.scala:87:24] assign _out_T_1819 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1821; // @[RegisterRouter.scala:87:24] assign _out_T_1821 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1825; // @[RegisterRouter.scala:87:24] assign _out_T_1825 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1827; // @[RegisterRouter.scala:87:24] assign _out_T_1827 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1829; // @[RegisterRouter.scala:87:24] assign _out_T_1829 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1831; // @[RegisterRouter.scala:87:24] assign _out_T_1831 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1833; // @[RegisterRouter.scala:87:24] assign _out_T_1833 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1835; // @[RegisterRouter.scala:87:24] assign _out_T_1835 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1837; // @[RegisterRouter.scala:87:24] assign _out_T_1837 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1839; // @[RegisterRouter.scala:87:24] assign _out_T_1839 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1841; // @[RegisterRouter.scala:87:24] assign _out_T_1841 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1843; // @[RegisterRouter.scala:87:24] assign _out_T_1843 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1845; // @[RegisterRouter.scala:87:24] assign _out_T_1845 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1849; // @[RegisterRouter.scala:87:24] assign _out_T_1849 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1851; // @[RegisterRouter.scala:87:24] assign _out_T_1851 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1853; // @[RegisterRouter.scala:87:24] assign _out_T_1853 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1855; // @[RegisterRouter.scala:87:24] assign _out_T_1855 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1857; // @[RegisterRouter.scala:87:24] assign _out_T_1857 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1859; // @[RegisterRouter.scala:87:24] assign _out_T_1859 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1861; // @[RegisterRouter.scala:87:24] assign _out_T_1861 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1863; // @[RegisterRouter.scala:87:24] assign _out_T_1863 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1865; // @[RegisterRouter.scala:87:24] assign _out_T_1865 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1867; // @[RegisterRouter.scala:87:24] assign _out_T_1867 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1869; // @[RegisterRouter.scala:87:24] assign _out_T_1869 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1871; // @[RegisterRouter.scala:87:24] assign _out_T_1871 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1873; // @[RegisterRouter.scala:87:24] assign _out_T_1873 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1875; // @[RegisterRouter.scala:87:24] assign _out_T_1875 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1879; // @[RegisterRouter.scala:87:24] assign _out_T_1879 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1881; // @[RegisterRouter.scala:87:24] assign _out_T_1881 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1883; // @[RegisterRouter.scala:87:24] assign _out_T_1883 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1885; // @[RegisterRouter.scala:87:24] assign _out_T_1885 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1887; // @[RegisterRouter.scala:87:24] assign _out_T_1887 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1889; // @[RegisterRouter.scala:87:24] assign _out_T_1889 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1891; // @[RegisterRouter.scala:87:24] assign _out_T_1891 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1893; // @[RegisterRouter.scala:87:24] assign _out_T_1893 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1895; // @[RegisterRouter.scala:87:24] assign _out_T_1895 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1897; // @[RegisterRouter.scala:87:24] assign _out_T_1897 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1899; // @[RegisterRouter.scala:87:24] assign _out_T_1899 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1901; // @[RegisterRouter.scala:87:24] assign _out_T_1901 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1903; // @[RegisterRouter.scala:87:24] assign _out_T_1903 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1905; // @[RegisterRouter.scala:87:24] assign _out_T_1905 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1907; // @[RegisterRouter.scala:87:24] assign _out_T_1907 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_T_1909; // @[RegisterRouter.scala:87:24] assign _out_T_1909 = _GEN_19; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_138 = _out_T_1601; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_249 = _out_T_1603; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_234 = _out_T_1605; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_170 = _out_T_1607; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_115 = _out_T_1609; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_217 = _out_T_1611; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_247 = _out_T_1613; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_202 = _out_T_1615; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_142 = _out_T_1617; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_153 = _out_T_1619; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_174 = _out_T_1621; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_185 = _out_T_1623; // @[MuxLiteral.scala:49:48] wire _GEN_20 = out_findex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1624; // @[RegisterRouter.scala:87:24] assign _out_T_1624 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1640; // @[RegisterRouter.scala:87:24] assign _out_T_1640 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1666; // @[RegisterRouter.scala:87:24] assign _out_T_1666 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1678; // @[RegisterRouter.scala:87:24] assign _out_T_1678 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1716; // @[RegisterRouter.scala:87:24] assign _out_T_1716 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1724; // @[RegisterRouter.scala:87:24] assign _out_T_1724 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1742; // @[RegisterRouter.scala:87:24] assign _out_T_1742 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1756; // @[RegisterRouter.scala:87:24] assign _out_T_1756 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1822; // @[RegisterRouter.scala:87:24] assign _out_T_1822 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1846; // @[RegisterRouter.scala:87:24] assign _out_T_1846 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _out_T_1876; // @[RegisterRouter.scala:87:24] assign _out_T_1876 = _GEN_20; // @[RegisterRouter.scala:87:24] wire _GEN_21 = out_bindex_1 == 9'h100; // @[RegisterRouter.scala:87:24] wire _out_T_1625; // @[RegisterRouter.scala:87:24] assign _out_T_1625 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1641; // @[RegisterRouter.scala:87:24] assign _out_T_1641 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1667; // @[RegisterRouter.scala:87:24] assign _out_T_1667 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1679; // @[RegisterRouter.scala:87:24] assign _out_T_1679 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1717; // @[RegisterRouter.scala:87:24] assign _out_T_1717 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1725; // @[RegisterRouter.scala:87:24] assign _out_T_1725 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1743; // @[RegisterRouter.scala:87:24] assign _out_T_1743 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1757; // @[RegisterRouter.scala:87:24] assign _out_T_1757 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1823; // @[RegisterRouter.scala:87:24] assign _out_T_1823 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1847; // @[RegisterRouter.scala:87:24] assign _out_T_1847 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_T_1877; // @[RegisterRouter.scala:87:24] assign _out_T_1877 = _GEN_21; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_1 = _out_T_1625; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_184 = _out_T_1627; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_110 = _out_T_1629; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_196 = _out_T_1631; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_157 = _out_T_1633; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_189 = _out_T_1635; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_152 = _out_T_1637; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_228 = _out_T_1639; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_5 = _out_T_1641; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_216 = _out_T_1643; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_164 = _out_T_1645; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_179 = _out_T_1647; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_106 = _out_T_1649; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_238 = _out_T_1651; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_211 = _out_T_1653; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_253 = _out_T_1655; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_147 = _out_T_1657; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_221 = _out_T_1659; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_132 = _out_T_1661; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_133 = _out_T_1663; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_243 = _out_T_1665; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_9 = _out_T_1667; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_206 = _out_T_1669; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_233 = _out_T_1671; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_248 = _out_T_1673; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_201 = _out_T_1675; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_220 = _out_T_1677; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_4 = _out_T_1679; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_160 = _out_T_1681; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_192 = _out_T_1683; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_137 = _out_T_1685; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_165 = _out_T_1687; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_33 = _out_T_1689; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_229 = _out_T_1691; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_252 = _out_T_1693; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_197 = _out_T_1695; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_224 = _out_T_1697; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_156 = _out_T_1699; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_188 = _out_T_1701; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_169 = _out_T_1703; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_141 = _out_T_1705; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_225 = _out_T_1707; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_193 = _out_T_1709; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_212 = _out_T_1711; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_96 = _out_T_1713; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_109 = _out_T_1715; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_0 = _out_T_1717; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_173 = _out_T_1719; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_129 = _out_T_1721; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_134 = _out_T_1723; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_10 = _out_T_1725; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_205 = _out_T_1727; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_128 = _out_T_1729; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_237 = _out_T_1731; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_105 = _out_T_1733; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_244 = _out_T_1735; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_166 = _out_T_1737; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_32 = _out_T_1739; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_148 = _out_T_1741; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_8 = _out_T_1743; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_161 = _out_T_1745; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_180 = _out_T_1747; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_149 = _out_T_1749; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_176 = _out_T_1751; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_191 = _out_T_1753; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_204 = _out_T_1755; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_3 = _out_T_1757; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_144 = _out_T_1759; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_236 = _out_T_1761; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_181 = _out_T_1763; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_159 = _out_T_1765; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_187 = _out_T_1767; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_172 = _out_T_1769; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_113 = _out_T_1771; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_219 = _out_T_1773; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_230 = _out_T_1775; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_245 = _out_T_1777; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_208 = _out_T_1779; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_103 = _out_T_1781; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_140 = _out_T_1783; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_213 = _out_T_1785; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_155 = _out_T_1787; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_198 = _out_T_1789; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_108 = _out_T_1791; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_240 = _out_T_1793; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_251 = _out_T_1795; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_130 = _out_T_1797; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_223 = _out_T_1799; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_135 = _out_T_1801; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_226 = _out_T_1803; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_241 = _out_T_1805; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_167 = _out_T_1807; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_162 = _out_T_1809; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_255 = _out_T_1811; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_209 = _out_T_1813; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_112 = _out_T_1815; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_194 = _out_T_1817; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_145 = _out_T_1819; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_150 = _out_T_1821; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_7 = _out_T_1823; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_199 = _out_T_1825; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_177 = _out_T_1827; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_182 = _out_T_1829; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_154 = _out_T_1831; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_175 = _out_T_1833; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_143 = _out_T_1835; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_203 = _out_T_1837; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_218 = _out_T_1839; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_104 = _out_T_1841; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_250 = _out_T_1843; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_231 = _out_T_1845; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_2 = _out_T_1847; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_158 = _out_T_1849; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_186 = _out_T_1851; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_114 = _out_T_1853; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_171 = _out_T_1855; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_139 = _out_T_1857; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_207 = _out_T_1859; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_214 = _out_T_1861; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_235 = _out_T_1863; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_246 = _out_T_1865; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_151 = _out_T_1867; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_146 = _out_T_1869; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_190 = _out_T_1871; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_183 = _out_T_1873; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_168 = _out_T_1875; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_6 = _out_T_1877; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_210 = _out_T_1879; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_107 = _out_T_1881; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_136 = _out_T_1883; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_195 = _out_T_1885; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_239 = _out_T_1887; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_242 = _out_T_1889; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_131 = _out_T_1891; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_178 = _out_T_1893; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_163 = _out_T_1895; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_200 = _out_T_1897; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_111 = _out_T_1899; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_215 = _out_T_1901; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_222 = _out_T_1903; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_232 = _out_T_1905; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2_254 = _out_T_1907; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2_227 = _out_T_1909; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_rivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_47; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_48; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_49; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_50; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_51; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_52; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_53; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_54; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_55; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_56; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_57; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_58; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_59; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_60; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_61; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_62; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_63; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_64; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_65; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_66; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_67; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_68; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_69; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_70; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_71; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_72; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_73; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_74; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_75; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_76; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_77; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_78; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_79; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_80; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_81; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_82; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_83; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_84; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_85; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_86; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_87; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_88; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_89; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_90; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_91; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_92; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_93; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_94; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_95; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_96; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_97; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_98; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_99; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_210; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_211; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_212; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_213; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_214; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_215; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_216; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_217; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_218; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_219; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_220; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_221; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_222; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_223; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_224; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_225; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_226; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_227; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_228; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_229; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_230; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_231; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_232; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_233; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_234; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_235; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_236; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_237; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_238; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_239; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_240; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_241; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_242; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_243; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_244; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_245; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_246; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_247; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_248; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_249; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_250; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_251; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_252; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_253; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_254; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_255; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_256; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_257; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_258; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_259; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_260; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_261; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_262; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_263; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_264; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_265; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_266; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_267; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_268; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_269; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_270; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_271; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_272; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_273; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_274; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_275; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_276; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_277; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_278; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_279; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_280; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_281; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_282; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_283; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_284; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_285; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_286; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_287; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_288; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_289; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_290; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_291; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_292; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_293; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_294; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_295; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_296; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_297; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_298; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_299; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_300; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_301; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_302; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_303; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_304; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_305; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_306; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_307; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_308; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_309; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_310; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_311; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_312; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_313; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_314; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_315; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_316; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_317; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_318; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_319; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_320; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_321; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_322; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_323; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_324; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_325; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_326; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_327; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_328; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_329; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_330; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_331; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_332; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_333; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_334; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_335; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_336; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_337; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_338; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_339; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_340; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_341; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_342; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_343; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_344; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_345; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_346; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_347; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_348; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_349; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_350; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_351; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_352; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_353; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_354; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_355; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_356; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_357; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_358; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_359; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_360; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_361; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_362; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_363; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_364; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_365; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_366; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_367; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_368; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_369; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_370; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_371; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_372; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_373; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_374; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_375; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_376; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_377; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_378; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_379; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_380; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_381; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_382; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_383; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_384; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_385; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_386; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_387; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_388; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_389; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_390; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_391; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_392; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_393; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_394; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_395; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_396; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_397; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_398; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_399; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_400; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_401; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_402; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_403; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_404; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_405; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_406; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_407; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_408; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_409; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_410; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_411; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_412; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_413; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_414; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_415; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_416; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_417; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_418; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_419; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_420; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_421; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_422; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_423; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_424; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_425; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_426; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_427; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_428; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_429; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_430; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_431; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_432; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_433; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_434; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_435; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_436; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_437; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_438; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_439; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_440; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_441; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_442; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_443; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_444; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_445; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_446; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_447; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_448; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_449; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_450; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_451; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_452; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_453; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_454; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_455; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_456; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_457; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_458; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_459; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_460; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_461; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_462; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_463; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_464; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_465; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_466; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_467; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_468; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_469; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_470; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_471; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_472; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_473; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_474; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_475; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_476; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_477; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_478; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_479; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_480; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_481; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_482; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_483; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_484; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_485; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_486; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_487; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_488; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_489; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_490; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_491; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_492; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_493; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_494; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_495; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_496; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_497; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_498; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_499; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_500; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_501; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_502; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_503; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_504; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_505; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_506; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_507; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_508; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_509; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_510; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_511; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_512; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_513; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_514; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_515; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_516; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_517; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_518; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_519; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_520; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_521; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_522; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_523; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_524; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_525; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_526; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_527; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_528; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_529; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_530; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_531; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_532; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_533; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_534; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_535; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_536; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_537; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_538; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_539; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_540; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_541; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_542; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_543; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_544; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_545; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_546; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_547; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_548; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_549; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_550; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_551; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_552; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_553; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_554; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_555; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_556; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_557; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_558; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_559; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_560; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_561; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_562; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_563; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_564; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_565; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_566; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_567; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_568; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_569; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_570; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_571; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_572; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_573; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_574; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_575; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_576; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_577; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_578; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_579; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_580; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_581; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_582; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_583; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_584; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_585; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_586; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_587; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_588; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_589; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_590; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_591; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_592; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_593; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_594; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_595; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_596; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_597; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_598; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_599; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_600; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_601; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_602; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_603; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_604; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_605; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_606; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_607; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_608; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_609; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_610; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_611; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_612; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_613; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_614; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_615; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_616; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_617; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_618; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_619; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_620; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_621; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_622; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_623; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_624; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_625; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_626; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_627; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_628; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_629; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_630; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_631; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_632; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_633; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_634; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_635; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_636; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_637; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_638; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_639; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_640; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_641; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_642; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_643; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_644; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_645; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_646; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_647; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_648; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_649; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_650; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_651; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_652; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_653; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_654; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_655; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_656; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_657; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_658; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_659; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_660; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_661; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_662; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_663; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_664; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_665; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_666; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_667; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_668; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_669; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_670; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_671; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_672; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_673; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_674; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_675; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_676; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_677; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_678; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_679; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_680; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_681; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_682; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_683; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_684; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_685; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_686; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_687; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_688; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_689; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_690; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_691; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_692; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_693; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_694; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_695; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_696; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_697; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_698; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_699; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_700; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_701; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_702; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_703; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_704; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_705; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_706; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_707; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_708; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_709; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_710; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_711; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_712; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_713; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_714; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_715; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_716; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_717; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_718; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_719; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_720; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_721; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_722; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_723; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_724; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_725; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_726; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_727; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_728; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_729; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_730; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_731; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_732; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_733; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_734; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_735; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_736; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_737; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_738; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_739; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_740; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_741; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_742; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_743; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_744; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_745; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_746; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_747; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_748; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_749; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_750; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_751; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_752; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_753; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_754; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_755; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_756; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_757; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_758; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_759; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_760; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_761; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_762; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_763; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_764; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_765; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_766; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_767; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_768; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_769; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_770; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_771; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_772; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_773; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_774; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_775; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_776; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_777; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_778; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_779; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_780; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_781; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_782; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_783; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_784; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_785; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_786; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_787; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_788; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_789; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_790; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_791; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_792; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_793; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_794; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_795; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_796; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_797; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_798; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_799; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_800; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_801; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_802; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_803; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_804; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_805; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_806; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_807; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_808; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_809; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_810; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_811; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_812; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_813; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_814; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_815; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_816; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_817; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_818; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_819; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_820; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_821; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_822; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_823; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_824; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_825; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_826; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_827; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_828; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_829; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_830; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_831; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_832; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_833; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_834; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_835; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_836; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_837; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_838; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_839; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_840; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_841; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_842; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_843; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_844; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_845; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_846; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_847; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_848; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_849; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_850; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_851; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_852; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_853; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_854; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_855; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_856; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_857; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_858; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_859; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_860; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_861; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_862; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_863; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_864; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_865; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_866; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_867; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_868; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_869; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_870; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_871; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_872; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_873; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_874; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_875; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_876; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_877; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_878; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_879; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_880; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_881; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_882; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_883; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_884; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_885; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_886; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_887; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_888; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_889; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_890; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_891; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_892; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_893; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_894; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_895; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_896; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_897; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_898; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_899; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_900; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_901; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_902; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_903; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_904; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_905; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_906; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_907; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_908; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_909; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_910; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_911; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_912; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_913; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_914; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_915; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_916; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_917; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_918; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_919; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_920; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_921; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_922; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_923; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_924; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_925; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_926; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_927; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_928; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_929; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_930; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_931; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_932; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_933; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_934; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_935; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_936; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_937; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_938; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_939; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_940; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_941; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_942; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_943; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_944; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_945; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_946; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_947; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_948; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_949; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_950; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_951; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_952; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_953; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_954; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_955; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_956; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_957; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_958; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_959; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_960; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_961; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_962; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_963; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_964; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_965; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_966; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_967; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_968; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_969; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_970; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_971; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_972; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_973; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_974; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_975; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_976; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_977; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_978; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_979; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_980; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_981; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_982; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_983; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_984; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_985; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_986; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_987; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_988; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_989; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_990; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_991; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_992; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_993; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_994; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_995; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_996; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_997; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_998; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_999; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1000; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1001; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1002; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1003; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1004; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1005; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1006; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1007; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1008; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1009; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1010; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1011; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1012; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1013; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1014; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1015; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1016; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1017; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1018; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1019; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1020; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1021; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1022; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1023; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1024; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1025; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1026; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1027; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1028; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1029; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1030; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1031; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1032; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1033; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1034; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1035; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1036; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1037; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1038; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1039; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1040; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1041; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1042; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1043; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1044; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1045; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1046; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1047; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1048; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1049; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1050; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1051; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1052; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1053; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1054; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1055; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1056; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1057; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1058; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1059; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1060; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1061; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1062; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1063; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1064; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1065; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1066; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1067; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1068; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1069; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1070; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1071; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1072; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1073; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1074; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1075; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1076; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1077; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1078; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1079; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1080; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1081; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1082; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1083; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1084; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1085; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1086; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1087; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1088; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1089; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1090; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1091; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1092; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1093; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1094; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1095; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1096; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1097; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1098; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1099; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1100; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1101; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1102; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1103; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1104; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1105; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1106; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1107; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1108; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1109; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1110; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1111; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1112; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1113; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1114; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1115; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1116; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1117; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1118; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1119; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1120; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1121; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1122; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1123; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1124; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1125; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1126; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1127; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1128; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1129; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1130; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1131; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1132; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1133; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1134; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1135; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1136; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1137; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1138; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1139; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1140; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1141; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1142; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1143; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1144; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1145; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1146; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1147; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1148; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1149; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1150; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1151; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1152; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1153; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1154; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1155; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1156; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1157; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1158; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1159; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1160; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1161; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1162; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1163; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1164; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1165; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1166; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1167; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1168; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1169; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1170; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1171; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1172; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1173; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1174; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1175; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1176; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1177; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1178; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1179; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1180; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1181; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1182; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1183; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1184; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1185; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1186; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1187; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1188; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1189; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1190; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1191; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1192; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1193; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1194; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1195; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1196; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1197; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1198; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1199; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1200; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1201; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1202; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1203; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1204; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1205; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1206; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1207; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1208; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1209; // @[RegisterRouter.scala:87:24] wire out_wivalid_1_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_0; // @[RegisterRouter.scala:87:24] wire out_roready_1_1; // @[RegisterRouter.scala:87:24] wire out_roready_1_2; // @[RegisterRouter.scala:87:24] wire out_roready_1_3; // @[RegisterRouter.scala:87:24] wire out_roready_1_4; // @[RegisterRouter.scala:87:24] wire out_roready_1_5; // @[RegisterRouter.scala:87:24] wire out_roready_1_6; // @[RegisterRouter.scala:87:24] wire out_roready_1_7; // @[RegisterRouter.scala:87:24] wire out_roready_1_8; // @[RegisterRouter.scala:87:24] wire out_roready_1_9; // @[RegisterRouter.scala:87:24] wire out_roready_1_10; // @[RegisterRouter.scala:87:24] wire out_roready_1_11; // @[RegisterRouter.scala:87:24] wire out_roready_1_12; // @[RegisterRouter.scala:87:24] wire out_roready_1_13; // @[RegisterRouter.scala:87:24] wire out_roready_1_14; // @[RegisterRouter.scala:87:24] wire out_roready_1_15; // @[RegisterRouter.scala:87:24] wire out_roready_1_16; // @[RegisterRouter.scala:87:24] wire out_roready_1_17; // @[RegisterRouter.scala:87:24] wire out_roready_1_18; // @[RegisterRouter.scala:87:24] wire out_roready_1_19; // @[RegisterRouter.scala:87:24] wire out_roready_1_20; // @[RegisterRouter.scala:87:24] wire out_roready_1_21; // @[RegisterRouter.scala:87:24] wire out_roready_1_22; // @[RegisterRouter.scala:87:24] wire out_roready_1_23; // @[RegisterRouter.scala:87:24] wire out_roready_1_24; // @[RegisterRouter.scala:87:24] wire out_roready_1_25; // @[RegisterRouter.scala:87:24] wire out_roready_1_26; // @[RegisterRouter.scala:87:24] wire out_roready_1_27; // @[RegisterRouter.scala:87:24] wire out_roready_1_28; // @[RegisterRouter.scala:87:24] wire out_roready_1_29; // @[RegisterRouter.scala:87:24] wire out_roready_1_30; // @[RegisterRouter.scala:87:24] wire out_roready_1_31; // @[RegisterRouter.scala:87:24] wire out_roready_1_32; // @[RegisterRouter.scala:87:24] wire out_roready_1_33; // @[RegisterRouter.scala:87:24] wire out_roready_1_34; // @[RegisterRouter.scala:87:24] wire out_roready_1_35; // @[RegisterRouter.scala:87:24] wire out_roready_1_36; // @[RegisterRouter.scala:87:24] wire out_roready_1_37; // @[RegisterRouter.scala:87:24] wire out_roready_1_38; // @[RegisterRouter.scala:87:24] wire out_roready_1_39; // @[RegisterRouter.scala:87:24] wire out_roready_1_40; // @[RegisterRouter.scala:87:24] wire out_roready_1_41; // @[RegisterRouter.scala:87:24] wire out_roready_1_42; // @[RegisterRouter.scala:87:24] wire out_roready_1_43; // @[RegisterRouter.scala:87:24] wire out_roready_1_44; // @[RegisterRouter.scala:87:24] wire out_roready_1_45; // @[RegisterRouter.scala:87:24] wire out_roready_1_46; // @[RegisterRouter.scala:87:24] wire out_roready_1_47; // @[RegisterRouter.scala:87:24] wire out_roready_1_48; // @[RegisterRouter.scala:87:24] wire out_roready_1_49; // @[RegisterRouter.scala:87:24] wire out_roready_1_50; // @[RegisterRouter.scala:87:24] wire out_roready_1_51; // @[RegisterRouter.scala:87:24] wire out_roready_1_52; // @[RegisterRouter.scala:87:24] wire out_roready_1_53; // @[RegisterRouter.scala:87:24] wire out_roready_1_54; // @[RegisterRouter.scala:87:24] wire out_roready_1_55; // @[RegisterRouter.scala:87:24] wire out_roready_1_56; // @[RegisterRouter.scala:87:24] wire out_roready_1_57; // @[RegisterRouter.scala:87:24] wire out_roready_1_58; // @[RegisterRouter.scala:87:24] wire out_roready_1_59; // @[RegisterRouter.scala:87:24] wire out_roready_1_60; // @[RegisterRouter.scala:87:24] wire out_roready_1_61; // @[RegisterRouter.scala:87:24] wire out_roready_1_62; // @[RegisterRouter.scala:87:24] wire out_roready_1_63; // @[RegisterRouter.scala:87:24] wire out_roready_1_64; // @[RegisterRouter.scala:87:24] wire out_roready_1_65; // @[RegisterRouter.scala:87:24] wire out_roready_1_66; // @[RegisterRouter.scala:87:24] wire out_roready_1_67; // @[RegisterRouter.scala:87:24] wire out_roready_1_68; // @[RegisterRouter.scala:87:24] wire out_roready_1_69; // @[RegisterRouter.scala:87:24] wire out_roready_1_70; // @[RegisterRouter.scala:87:24] wire out_roready_1_71; // @[RegisterRouter.scala:87:24] wire out_roready_1_72; // @[RegisterRouter.scala:87:24] wire out_roready_1_73; // @[RegisterRouter.scala:87:24] wire out_roready_1_74; // @[RegisterRouter.scala:87:24] wire out_roready_1_75; // @[RegisterRouter.scala:87:24] wire out_roready_1_76; // @[RegisterRouter.scala:87:24] wire out_roready_1_77; // @[RegisterRouter.scala:87:24] wire out_roready_1_78; // @[RegisterRouter.scala:87:24] wire out_roready_1_79; // @[RegisterRouter.scala:87:24] wire out_roready_1_80; // @[RegisterRouter.scala:87:24] wire out_roready_1_81; // @[RegisterRouter.scala:87:24] wire out_roready_1_82; // @[RegisterRouter.scala:87:24] wire out_roready_1_83; // @[RegisterRouter.scala:87:24] wire out_roready_1_84; // @[RegisterRouter.scala:87:24] wire out_roready_1_85; // @[RegisterRouter.scala:87:24] wire out_roready_1_86; // @[RegisterRouter.scala:87:24] wire out_roready_1_87; // @[RegisterRouter.scala:87:24] wire out_roready_1_88; // @[RegisterRouter.scala:87:24] wire out_roready_1_89; // @[RegisterRouter.scala:87:24] wire out_roready_1_90; // @[RegisterRouter.scala:87:24] wire out_roready_1_91; // @[RegisterRouter.scala:87:24] wire out_roready_1_92; // @[RegisterRouter.scala:87:24] wire out_roready_1_93; // @[RegisterRouter.scala:87:24] wire out_roready_1_94; // @[RegisterRouter.scala:87:24] wire out_roready_1_95; // @[RegisterRouter.scala:87:24] wire out_roready_1_96; // @[RegisterRouter.scala:87:24] wire out_roready_1_97; // @[RegisterRouter.scala:87:24] wire out_roready_1_98; // @[RegisterRouter.scala:87:24] wire out_roready_1_99; // @[RegisterRouter.scala:87:24] wire out_roready_1_100; // @[RegisterRouter.scala:87:24] wire out_roready_1_101; // @[RegisterRouter.scala:87:24] wire out_roready_1_102; // @[RegisterRouter.scala:87:24] wire out_roready_1_103; // @[RegisterRouter.scala:87:24] wire out_roready_1_104; // @[RegisterRouter.scala:87:24] wire out_roready_1_105; // @[RegisterRouter.scala:87:24] wire out_roready_1_106; // @[RegisterRouter.scala:87:24] wire out_roready_1_107; // @[RegisterRouter.scala:87:24] wire out_roready_1_108; // @[RegisterRouter.scala:87:24] wire out_roready_1_109; // @[RegisterRouter.scala:87:24] wire out_roready_1_110; // @[RegisterRouter.scala:87:24] wire out_roready_1_111; // @[RegisterRouter.scala:87:24] wire out_roready_1_112; // @[RegisterRouter.scala:87:24] wire out_roready_1_113; // @[RegisterRouter.scala:87:24] wire out_roready_1_114; // @[RegisterRouter.scala:87:24] wire out_roready_1_115; // @[RegisterRouter.scala:87:24] wire out_roready_1_116; // @[RegisterRouter.scala:87:24] wire out_roready_1_117; // @[RegisterRouter.scala:87:24] wire out_roready_1_118; // @[RegisterRouter.scala:87:24] wire out_roready_1_119; // @[RegisterRouter.scala:87:24] wire out_roready_1_120; // @[RegisterRouter.scala:87:24] wire out_roready_1_121; // @[RegisterRouter.scala:87:24] wire out_roready_1_122; // @[RegisterRouter.scala:87:24] wire out_roready_1_123; // @[RegisterRouter.scala:87:24] wire out_roready_1_124; // @[RegisterRouter.scala:87:24] wire out_roready_1_125; // @[RegisterRouter.scala:87:24] wire out_roready_1_126; // @[RegisterRouter.scala:87:24] wire out_roready_1_127; // @[RegisterRouter.scala:87:24] wire out_roready_1_128; // @[RegisterRouter.scala:87:24] wire out_roready_1_129; // @[RegisterRouter.scala:87:24] wire out_roready_1_130; // @[RegisterRouter.scala:87:24] wire out_roready_1_131; // @[RegisterRouter.scala:87:24] wire out_roready_1_132; // @[RegisterRouter.scala:87:24] wire out_roready_1_133; // @[RegisterRouter.scala:87:24] wire out_roready_1_134; // @[RegisterRouter.scala:87:24] wire out_roready_1_135; // @[RegisterRouter.scala:87:24] wire out_roready_1_136; // @[RegisterRouter.scala:87:24] wire out_roready_1_137; // @[RegisterRouter.scala:87:24] wire out_roready_1_138; // @[RegisterRouter.scala:87:24] wire out_roready_1_139; // @[RegisterRouter.scala:87:24] wire out_roready_1_140; // @[RegisterRouter.scala:87:24] wire out_roready_1_141; // @[RegisterRouter.scala:87:24] wire out_roready_1_142; // @[RegisterRouter.scala:87:24] wire out_roready_1_143; // @[RegisterRouter.scala:87:24] wire out_roready_1_144; // @[RegisterRouter.scala:87:24] wire out_roready_1_145; // @[RegisterRouter.scala:87:24] wire out_roready_1_146; // @[RegisterRouter.scala:87:24] wire out_roready_1_147; // @[RegisterRouter.scala:87:24] wire out_roready_1_148; // @[RegisterRouter.scala:87:24] wire out_roready_1_149; // @[RegisterRouter.scala:87:24] wire out_roready_1_150; // @[RegisterRouter.scala:87:24] wire out_roready_1_151; // @[RegisterRouter.scala:87:24] wire out_roready_1_152; // @[RegisterRouter.scala:87:24] wire out_roready_1_153; // @[RegisterRouter.scala:87:24] wire out_roready_1_154; // @[RegisterRouter.scala:87:24] wire out_roready_1_155; // @[RegisterRouter.scala:87:24] wire out_roready_1_156; // @[RegisterRouter.scala:87:24] wire out_roready_1_157; // @[RegisterRouter.scala:87:24] wire out_roready_1_158; // @[RegisterRouter.scala:87:24] wire out_roready_1_159; // @[RegisterRouter.scala:87:24] wire out_roready_1_160; // @[RegisterRouter.scala:87:24] wire out_roready_1_161; // @[RegisterRouter.scala:87:24] wire out_roready_1_162; // @[RegisterRouter.scala:87:24] wire out_roready_1_163; // @[RegisterRouter.scala:87:24] wire out_roready_1_164; // @[RegisterRouter.scala:87:24] wire out_roready_1_165; // @[RegisterRouter.scala:87:24] wire out_roready_1_166; // @[RegisterRouter.scala:87:24] wire out_roready_1_167; // @[RegisterRouter.scala:87:24] wire out_roready_1_168; // @[RegisterRouter.scala:87:24] wire out_roready_1_169; // @[RegisterRouter.scala:87:24] wire out_roready_1_170; // @[RegisterRouter.scala:87:24] wire out_roready_1_171; // @[RegisterRouter.scala:87:24] wire out_roready_1_172; // @[RegisterRouter.scala:87:24] wire out_roready_1_173; // @[RegisterRouter.scala:87:24] wire out_roready_1_174; // @[RegisterRouter.scala:87:24] wire out_roready_1_175; // @[RegisterRouter.scala:87:24] wire out_roready_1_176; // @[RegisterRouter.scala:87:24] wire out_roready_1_177; // @[RegisterRouter.scala:87:24] wire out_roready_1_178; // @[RegisterRouter.scala:87:24] wire out_roready_1_179; // @[RegisterRouter.scala:87:24] wire out_roready_1_180; // @[RegisterRouter.scala:87:24] wire out_roready_1_181; // @[RegisterRouter.scala:87:24] wire out_roready_1_182; // @[RegisterRouter.scala:87:24] wire out_roready_1_183; // @[RegisterRouter.scala:87:24] wire out_roready_1_184; // @[RegisterRouter.scala:87:24] wire out_roready_1_185; // @[RegisterRouter.scala:87:24] wire out_roready_1_186; // @[RegisterRouter.scala:87:24] wire out_roready_1_187; // @[RegisterRouter.scala:87:24] wire out_roready_1_188; // @[RegisterRouter.scala:87:24] wire out_roready_1_189; // @[RegisterRouter.scala:87:24] wire out_roready_1_190; // @[RegisterRouter.scala:87:24] wire out_roready_1_191; // @[RegisterRouter.scala:87:24] wire out_roready_1_192; // @[RegisterRouter.scala:87:24] wire out_roready_1_193; // @[RegisterRouter.scala:87:24] wire out_roready_1_194; // @[RegisterRouter.scala:87:24] wire out_roready_1_195; // @[RegisterRouter.scala:87:24] wire out_roready_1_196; // @[RegisterRouter.scala:87:24] wire out_roready_1_197; // @[RegisterRouter.scala:87:24] wire out_roready_1_198; // @[RegisterRouter.scala:87:24] wire out_roready_1_199; // @[RegisterRouter.scala:87:24] wire out_roready_1_200; // @[RegisterRouter.scala:87:24] wire out_roready_1_201; // @[RegisterRouter.scala:87:24] wire out_roready_1_202; // @[RegisterRouter.scala:87:24] wire out_roready_1_203; // @[RegisterRouter.scala:87:24] wire out_roready_1_204; // @[RegisterRouter.scala:87:24] wire out_roready_1_205; // @[RegisterRouter.scala:87:24] wire out_roready_1_206; // @[RegisterRouter.scala:87:24] wire out_roready_1_207; // @[RegisterRouter.scala:87:24] wire out_roready_1_208; // @[RegisterRouter.scala:87:24] wire out_roready_1_209; // @[RegisterRouter.scala:87:24] wire out_roready_1_210; // @[RegisterRouter.scala:87:24] wire out_roready_1_211; // @[RegisterRouter.scala:87:24] wire out_roready_1_212; // @[RegisterRouter.scala:87:24] wire out_roready_1_213; // @[RegisterRouter.scala:87:24] wire out_roready_1_214; // @[RegisterRouter.scala:87:24] wire out_roready_1_215; // @[RegisterRouter.scala:87:24] wire out_roready_1_216; // @[RegisterRouter.scala:87:24] wire out_roready_1_217; // @[RegisterRouter.scala:87:24] wire out_roready_1_218; // @[RegisterRouter.scala:87:24] wire out_roready_1_219; // @[RegisterRouter.scala:87:24] wire out_roready_1_220; // @[RegisterRouter.scala:87:24] wire out_roready_1_221; // @[RegisterRouter.scala:87:24] wire out_roready_1_222; // @[RegisterRouter.scala:87:24] wire out_roready_1_223; // @[RegisterRouter.scala:87:24] wire out_roready_1_224; // @[RegisterRouter.scala:87:24] wire out_roready_1_225; // @[RegisterRouter.scala:87:24] wire out_roready_1_226; // @[RegisterRouter.scala:87:24] wire out_roready_1_227; // @[RegisterRouter.scala:87:24] wire out_roready_1_228; // @[RegisterRouter.scala:87:24] wire out_roready_1_229; // @[RegisterRouter.scala:87:24] wire out_roready_1_230; // @[RegisterRouter.scala:87:24] wire out_roready_1_231; // @[RegisterRouter.scala:87:24] wire out_roready_1_232; // @[RegisterRouter.scala:87:24] wire out_roready_1_233; // @[RegisterRouter.scala:87:24] wire out_roready_1_234; // @[RegisterRouter.scala:87:24] wire out_roready_1_235; // @[RegisterRouter.scala:87:24] wire out_roready_1_236; // @[RegisterRouter.scala:87:24] wire out_roready_1_237; // @[RegisterRouter.scala:87:24] wire out_roready_1_238; // @[RegisterRouter.scala:87:24] wire out_roready_1_239; // @[RegisterRouter.scala:87:24] wire out_roready_1_240; // @[RegisterRouter.scala:87:24] wire out_roready_1_241; // @[RegisterRouter.scala:87:24] wire out_roready_1_242; // @[RegisterRouter.scala:87:24] wire out_roready_1_243; // @[RegisterRouter.scala:87:24] wire out_roready_1_244; // @[RegisterRouter.scala:87:24] wire out_roready_1_245; // @[RegisterRouter.scala:87:24] wire out_roready_1_246; // @[RegisterRouter.scala:87:24] wire out_roready_1_247; // @[RegisterRouter.scala:87:24] wire out_roready_1_248; // @[RegisterRouter.scala:87:24] wire out_roready_1_249; // @[RegisterRouter.scala:87:24] wire out_roready_1_250; // @[RegisterRouter.scala:87:24] wire out_roready_1_251; // @[RegisterRouter.scala:87:24] wire out_roready_1_252; // @[RegisterRouter.scala:87:24] wire out_roready_1_253; // @[RegisterRouter.scala:87:24] wire out_roready_1_254; // @[RegisterRouter.scala:87:24] wire out_roready_1_255; // @[RegisterRouter.scala:87:24] wire out_roready_1_256; // @[RegisterRouter.scala:87:24] wire out_roready_1_257; // @[RegisterRouter.scala:87:24] wire out_roready_1_258; // @[RegisterRouter.scala:87:24] wire out_roready_1_259; // @[RegisterRouter.scala:87:24] wire out_roready_1_260; // @[RegisterRouter.scala:87:24] wire out_roready_1_261; // @[RegisterRouter.scala:87:24] wire out_roready_1_262; // @[RegisterRouter.scala:87:24] wire out_roready_1_263; // @[RegisterRouter.scala:87:24] wire out_roready_1_264; // @[RegisterRouter.scala:87:24] wire out_roready_1_265; // @[RegisterRouter.scala:87:24] wire out_roready_1_266; // @[RegisterRouter.scala:87:24] wire out_roready_1_267; // @[RegisterRouter.scala:87:24] wire out_roready_1_268; // @[RegisterRouter.scala:87:24] wire out_roready_1_269; // @[RegisterRouter.scala:87:24] wire out_roready_1_270; // @[RegisterRouter.scala:87:24] wire out_roready_1_271; // @[RegisterRouter.scala:87:24] wire out_roready_1_272; // @[RegisterRouter.scala:87:24] wire out_roready_1_273; // @[RegisterRouter.scala:87:24] wire out_roready_1_274; // @[RegisterRouter.scala:87:24] wire out_roready_1_275; // @[RegisterRouter.scala:87:24] wire out_roready_1_276; // @[RegisterRouter.scala:87:24] wire out_roready_1_277; // @[RegisterRouter.scala:87:24] wire out_roready_1_278; // @[RegisterRouter.scala:87:24] wire out_roready_1_279; // @[RegisterRouter.scala:87:24] wire out_roready_1_280; // @[RegisterRouter.scala:87:24] wire out_roready_1_281; // @[RegisterRouter.scala:87:24] wire out_roready_1_282; // @[RegisterRouter.scala:87:24] wire out_roready_1_283; // @[RegisterRouter.scala:87:24] wire out_roready_1_284; // @[RegisterRouter.scala:87:24] wire out_roready_1_285; // @[RegisterRouter.scala:87:24] wire out_roready_1_286; // @[RegisterRouter.scala:87:24] wire out_roready_1_287; // @[RegisterRouter.scala:87:24] wire out_roready_1_288; // @[RegisterRouter.scala:87:24] wire out_roready_1_289; // @[RegisterRouter.scala:87:24] wire out_roready_1_290; // @[RegisterRouter.scala:87:24] wire out_roready_1_291; // @[RegisterRouter.scala:87:24] wire out_roready_1_292; // @[RegisterRouter.scala:87:24] wire out_roready_1_293; // @[RegisterRouter.scala:87:24] wire out_roready_1_294; // @[RegisterRouter.scala:87:24] wire out_roready_1_295; // @[RegisterRouter.scala:87:24] wire out_roready_1_296; // @[RegisterRouter.scala:87:24] wire out_roready_1_297; // @[RegisterRouter.scala:87:24] wire out_roready_1_298; // @[RegisterRouter.scala:87:24] wire out_roready_1_299; // @[RegisterRouter.scala:87:24] wire out_roready_1_300; // @[RegisterRouter.scala:87:24] wire out_roready_1_301; // @[RegisterRouter.scala:87:24] wire out_roready_1_302; // @[RegisterRouter.scala:87:24] wire out_roready_1_303; // @[RegisterRouter.scala:87:24] wire out_roready_1_304; // @[RegisterRouter.scala:87:24] wire out_roready_1_305; // @[RegisterRouter.scala:87:24] wire out_roready_1_306; // @[RegisterRouter.scala:87:24] wire out_roready_1_307; // @[RegisterRouter.scala:87:24] wire out_roready_1_308; // @[RegisterRouter.scala:87:24] wire out_roready_1_309; // @[RegisterRouter.scala:87:24] wire out_roready_1_310; // @[RegisterRouter.scala:87:24] wire out_roready_1_311; // @[RegisterRouter.scala:87:24] wire out_roready_1_312; // @[RegisterRouter.scala:87:24] wire out_roready_1_313; // @[RegisterRouter.scala:87:24] wire out_roready_1_314; // @[RegisterRouter.scala:87:24] wire out_roready_1_315; // @[RegisterRouter.scala:87:24] wire out_roready_1_316; // @[RegisterRouter.scala:87:24] wire out_roready_1_317; // @[RegisterRouter.scala:87:24] wire out_roready_1_318; // @[RegisterRouter.scala:87:24] wire out_roready_1_319; // @[RegisterRouter.scala:87:24] wire out_roready_1_320; // @[RegisterRouter.scala:87:24] wire out_roready_1_321; // @[RegisterRouter.scala:87:24] wire out_roready_1_322; // @[RegisterRouter.scala:87:24] wire out_roready_1_323; // @[RegisterRouter.scala:87:24] wire out_roready_1_324; // @[RegisterRouter.scala:87:24] wire out_roready_1_325; // @[RegisterRouter.scala:87:24] wire out_roready_1_326; // @[RegisterRouter.scala:87:24] wire out_roready_1_327; // @[RegisterRouter.scala:87:24] wire out_roready_1_328; // @[RegisterRouter.scala:87:24] wire out_roready_1_329; // @[RegisterRouter.scala:87:24] wire out_roready_1_330; // @[RegisterRouter.scala:87:24] wire out_roready_1_331; // @[RegisterRouter.scala:87:24] wire out_roready_1_332; // @[RegisterRouter.scala:87:24] wire out_roready_1_333; // @[RegisterRouter.scala:87:24] wire out_roready_1_334; // @[RegisterRouter.scala:87:24] wire out_roready_1_335; // @[RegisterRouter.scala:87:24] wire out_roready_1_336; // @[RegisterRouter.scala:87:24] wire out_roready_1_337; // @[RegisterRouter.scala:87:24] wire out_roready_1_338; // @[RegisterRouter.scala:87:24] wire out_roready_1_339; // @[RegisterRouter.scala:87:24] wire out_roready_1_340; // @[RegisterRouter.scala:87:24] wire out_roready_1_341; // @[RegisterRouter.scala:87:24] wire out_roready_1_342; // @[RegisterRouter.scala:87:24] wire out_roready_1_343; // @[RegisterRouter.scala:87:24] wire out_roready_1_344; // @[RegisterRouter.scala:87:24] wire out_roready_1_345; // @[RegisterRouter.scala:87:24] wire out_roready_1_346; // @[RegisterRouter.scala:87:24] wire out_roready_1_347; // @[RegisterRouter.scala:87:24] wire out_roready_1_348; // @[RegisterRouter.scala:87:24] wire out_roready_1_349; // @[RegisterRouter.scala:87:24] wire out_roready_1_350; // @[RegisterRouter.scala:87:24] wire out_roready_1_351; // @[RegisterRouter.scala:87:24] wire out_roready_1_352; // @[RegisterRouter.scala:87:24] wire out_roready_1_353; // @[RegisterRouter.scala:87:24] wire out_roready_1_354; // @[RegisterRouter.scala:87:24] wire out_roready_1_355; // @[RegisterRouter.scala:87:24] wire out_roready_1_356; // @[RegisterRouter.scala:87:24] wire out_roready_1_357; // @[RegisterRouter.scala:87:24] wire out_roready_1_358; // @[RegisterRouter.scala:87:24] wire out_roready_1_359; // @[RegisterRouter.scala:87:24] wire out_roready_1_360; // @[RegisterRouter.scala:87:24] wire out_roready_1_361; // @[RegisterRouter.scala:87:24] wire out_roready_1_362; // @[RegisterRouter.scala:87:24] wire out_roready_1_363; // @[RegisterRouter.scala:87:24] wire out_roready_1_364; // @[RegisterRouter.scala:87:24] wire out_roready_1_365; // @[RegisterRouter.scala:87:24] wire out_roready_1_366; // @[RegisterRouter.scala:87:24] wire out_roready_1_367; // @[RegisterRouter.scala:87:24] wire out_roready_1_368; // @[RegisterRouter.scala:87:24] wire out_roready_1_369; // @[RegisterRouter.scala:87:24] wire out_roready_1_370; // @[RegisterRouter.scala:87:24] wire out_roready_1_371; // @[RegisterRouter.scala:87:24] wire out_roready_1_372; // @[RegisterRouter.scala:87:24] wire out_roready_1_373; // @[RegisterRouter.scala:87:24] wire out_roready_1_374; // @[RegisterRouter.scala:87:24] wire out_roready_1_375; // @[RegisterRouter.scala:87:24] wire out_roready_1_376; // @[RegisterRouter.scala:87:24] wire out_roready_1_377; // @[RegisterRouter.scala:87:24] wire out_roready_1_378; // @[RegisterRouter.scala:87:24] wire out_roready_1_379; // @[RegisterRouter.scala:87:24] wire out_roready_1_380; // @[RegisterRouter.scala:87:24] wire out_roready_1_381; // @[RegisterRouter.scala:87:24] wire out_roready_1_382; // @[RegisterRouter.scala:87:24] wire out_roready_1_383; // @[RegisterRouter.scala:87:24] wire out_roready_1_384; // @[RegisterRouter.scala:87:24] wire out_roready_1_385; // @[RegisterRouter.scala:87:24] wire out_roready_1_386; // @[RegisterRouter.scala:87:24] wire out_roready_1_387; // @[RegisterRouter.scala:87:24] wire out_roready_1_388; // @[RegisterRouter.scala:87:24] wire out_roready_1_389; // @[RegisterRouter.scala:87:24] wire out_roready_1_390; // @[RegisterRouter.scala:87:24] wire out_roready_1_391; // @[RegisterRouter.scala:87:24] wire out_roready_1_392; // @[RegisterRouter.scala:87:24] wire out_roready_1_393; // @[RegisterRouter.scala:87:24] wire out_roready_1_394; // @[RegisterRouter.scala:87:24] wire out_roready_1_395; // @[RegisterRouter.scala:87:24] wire out_roready_1_396; // @[RegisterRouter.scala:87:24] wire out_roready_1_397; // @[RegisterRouter.scala:87:24] wire out_roready_1_398; // @[RegisterRouter.scala:87:24] wire out_roready_1_399; // @[RegisterRouter.scala:87:24] wire out_roready_1_400; // @[RegisterRouter.scala:87:24] wire out_roready_1_401; // @[RegisterRouter.scala:87:24] wire out_roready_1_402; // @[RegisterRouter.scala:87:24] wire out_roready_1_403; // @[RegisterRouter.scala:87:24] wire out_roready_1_404; // @[RegisterRouter.scala:87:24] wire out_roready_1_405; // @[RegisterRouter.scala:87:24] wire out_roready_1_406; // @[RegisterRouter.scala:87:24] wire out_roready_1_407; // @[RegisterRouter.scala:87:24] wire out_roready_1_408; // @[RegisterRouter.scala:87:24] wire out_roready_1_409; // @[RegisterRouter.scala:87:24] wire out_roready_1_410; // @[RegisterRouter.scala:87:24] wire out_roready_1_411; // @[RegisterRouter.scala:87:24] wire out_roready_1_412; // @[RegisterRouter.scala:87:24] wire out_roready_1_413; // @[RegisterRouter.scala:87:24] wire out_roready_1_414; // @[RegisterRouter.scala:87:24] wire out_roready_1_415; // @[RegisterRouter.scala:87:24] wire out_roready_1_416; // @[RegisterRouter.scala:87:24] wire out_roready_1_417; // @[RegisterRouter.scala:87:24] wire out_roready_1_418; // @[RegisterRouter.scala:87:24] wire out_roready_1_419; // @[RegisterRouter.scala:87:24] wire out_roready_1_420; // @[RegisterRouter.scala:87:24] wire out_roready_1_421; // @[RegisterRouter.scala:87:24] wire out_roready_1_422; // @[RegisterRouter.scala:87:24] wire out_roready_1_423; // @[RegisterRouter.scala:87:24] wire out_roready_1_424; // @[RegisterRouter.scala:87:24] wire out_roready_1_425; // @[RegisterRouter.scala:87:24] wire out_roready_1_426; // @[RegisterRouter.scala:87:24] wire out_roready_1_427; // @[RegisterRouter.scala:87:24] wire out_roready_1_428; // @[RegisterRouter.scala:87:24] wire out_roready_1_429; // @[RegisterRouter.scala:87:24] wire out_roready_1_430; // @[RegisterRouter.scala:87:24] wire out_roready_1_431; // @[RegisterRouter.scala:87:24] wire out_roready_1_432; // @[RegisterRouter.scala:87:24] wire out_roready_1_433; // @[RegisterRouter.scala:87:24] wire out_roready_1_434; // @[RegisterRouter.scala:87:24] wire out_roready_1_435; // @[RegisterRouter.scala:87:24] wire out_roready_1_436; // @[RegisterRouter.scala:87:24] wire out_roready_1_437; // @[RegisterRouter.scala:87:24] wire out_roready_1_438; // @[RegisterRouter.scala:87:24] wire out_roready_1_439; // @[RegisterRouter.scala:87:24] wire out_roready_1_440; // @[RegisterRouter.scala:87:24] wire out_roready_1_441; // @[RegisterRouter.scala:87:24] wire out_roready_1_442; // @[RegisterRouter.scala:87:24] wire out_roready_1_443; // @[RegisterRouter.scala:87:24] wire out_roready_1_444; // @[RegisterRouter.scala:87:24] wire out_roready_1_445; // @[RegisterRouter.scala:87:24] wire out_roready_1_446; // @[RegisterRouter.scala:87:24] wire out_roready_1_447; // @[RegisterRouter.scala:87:24] wire out_roready_1_448; // @[RegisterRouter.scala:87:24] wire out_roready_1_449; // @[RegisterRouter.scala:87:24] wire out_roready_1_450; // @[RegisterRouter.scala:87:24] wire out_roready_1_451; // @[RegisterRouter.scala:87:24] wire out_roready_1_452; // @[RegisterRouter.scala:87:24] wire out_roready_1_453; // @[RegisterRouter.scala:87:24] wire out_roready_1_454; // @[RegisterRouter.scala:87:24] wire out_roready_1_455; // @[RegisterRouter.scala:87:24] wire out_roready_1_456; // @[RegisterRouter.scala:87:24] wire out_roready_1_457; // @[RegisterRouter.scala:87:24] wire out_roready_1_458; // @[RegisterRouter.scala:87:24] wire out_roready_1_459; // @[RegisterRouter.scala:87:24] wire out_roready_1_460; // @[RegisterRouter.scala:87:24] wire out_roready_1_461; // @[RegisterRouter.scala:87:24] wire out_roready_1_462; // @[RegisterRouter.scala:87:24] wire out_roready_1_463; // @[RegisterRouter.scala:87:24] wire out_roready_1_464; // @[RegisterRouter.scala:87:24] wire out_roready_1_465; // @[RegisterRouter.scala:87:24] wire out_roready_1_466; // @[RegisterRouter.scala:87:24] wire out_roready_1_467; // @[RegisterRouter.scala:87:24] wire out_roready_1_468; // @[RegisterRouter.scala:87:24] wire out_roready_1_469; // @[RegisterRouter.scala:87:24] wire out_roready_1_470; // @[RegisterRouter.scala:87:24] wire out_roready_1_471; // @[RegisterRouter.scala:87:24] wire out_roready_1_472; // @[RegisterRouter.scala:87:24] wire out_roready_1_473; // @[RegisterRouter.scala:87:24] wire out_roready_1_474; // @[RegisterRouter.scala:87:24] wire out_roready_1_475; // @[RegisterRouter.scala:87:24] wire out_roready_1_476; // @[RegisterRouter.scala:87:24] wire out_roready_1_477; // @[RegisterRouter.scala:87:24] wire out_roready_1_478; // @[RegisterRouter.scala:87:24] wire out_roready_1_479; // @[RegisterRouter.scala:87:24] wire out_roready_1_480; // @[RegisterRouter.scala:87:24] wire out_roready_1_481; // @[RegisterRouter.scala:87:24] wire out_roready_1_482; // @[RegisterRouter.scala:87:24] wire out_roready_1_483; // @[RegisterRouter.scala:87:24] wire out_roready_1_484; // @[RegisterRouter.scala:87:24] wire out_roready_1_485; // @[RegisterRouter.scala:87:24] wire out_roready_1_486; // @[RegisterRouter.scala:87:24] wire out_roready_1_487; // @[RegisterRouter.scala:87:24] wire out_roready_1_488; // @[RegisterRouter.scala:87:24] wire out_roready_1_489; // @[RegisterRouter.scala:87:24] wire out_roready_1_490; // @[RegisterRouter.scala:87:24] wire out_roready_1_491; // @[RegisterRouter.scala:87:24] wire out_roready_1_492; // @[RegisterRouter.scala:87:24] wire out_roready_1_493; // @[RegisterRouter.scala:87:24] wire out_roready_1_494; // @[RegisterRouter.scala:87:24] wire out_roready_1_495; // @[RegisterRouter.scala:87:24] wire out_roready_1_496; // @[RegisterRouter.scala:87:24] wire out_roready_1_497; // @[RegisterRouter.scala:87:24] wire out_roready_1_498; // @[RegisterRouter.scala:87:24] wire out_roready_1_499; // @[RegisterRouter.scala:87:24] wire out_roready_1_500; // @[RegisterRouter.scala:87:24] wire out_roready_1_501; // @[RegisterRouter.scala:87:24] wire out_roready_1_502; // @[RegisterRouter.scala:87:24] wire out_roready_1_503; // @[RegisterRouter.scala:87:24] wire out_roready_1_504; // @[RegisterRouter.scala:87:24] wire out_roready_1_505; // @[RegisterRouter.scala:87:24] wire out_roready_1_506; // @[RegisterRouter.scala:87:24] wire out_roready_1_507; // @[RegisterRouter.scala:87:24] wire out_roready_1_508; // @[RegisterRouter.scala:87:24] wire out_roready_1_509; // @[RegisterRouter.scala:87:24] wire out_roready_1_510; // @[RegisterRouter.scala:87:24] wire out_roready_1_511; // @[RegisterRouter.scala:87:24] wire out_roready_1_512; // @[RegisterRouter.scala:87:24] wire out_roready_1_513; // @[RegisterRouter.scala:87:24] wire out_roready_1_514; // @[RegisterRouter.scala:87:24] wire out_roready_1_515; // @[RegisterRouter.scala:87:24] wire out_roready_1_516; // @[RegisterRouter.scala:87:24] wire out_roready_1_517; // @[RegisterRouter.scala:87:24] wire out_roready_1_518; // @[RegisterRouter.scala:87:24] wire out_roready_1_519; // @[RegisterRouter.scala:87:24] wire out_roready_1_520; // @[RegisterRouter.scala:87:24] wire out_roready_1_521; // @[RegisterRouter.scala:87:24] wire out_roready_1_522; // @[RegisterRouter.scala:87:24] wire out_roready_1_523; // @[RegisterRouter.scala:87:24] wire out_roready_1_524; // @[RegisterRouter.scala:87:24] wire out_roready_1_525; // @[RegisterRouter.scala:87:24] wire out_roready_1_526; // @[RegisterRouter.scala:87:24] wire out_roready_1_527; // @[RegisterRouter.scala:87:24] wire out_roready_1_528; // @[RegisterRouter.scala:87:24] wire out_roready_1_529; // @[RegisterRouter.scala:87:24] wire out_roready_1_530; // @[RegisterRouter.scala:87:24] wire out_roready_1_531; // @[RegisterRouter.scala:87:24] wire out_roready_1_532; // @[RegisterRouter.scala:87:24] wire out_roready_1_533; // @[RegisterRouter.scala:87:24] wire out_roready_1_534; // @[RegisterRouter.scala:87:24] wire out_roready_1_535; // @[RegisterRouter.scala:87:24] wire out_roready_1_536; // @[RegisterRouter.scala:87:24] wire out_roready_1_537; // @[RegisterRouter.scala:87:24] wire out_roready_1_538; // @[RegisterRouter.scala:87:24] wire out_roready_1_539; // @[RegisterRouter.scala:87:24] wire out_roready_1_540; // @[RegisterRouter.scala:87:24] wire out_roready_1_541; // @[RegisterRouter.scala:87:24] wire out_roready_1_542; // @[RegisterRouter.scala:87:24] wire out_roready_1_543; // @[RegisterRouter.scala:87:24] wire out_roready_1_544; // @[RegisterRouter.scala:87:24] wire out_roready_1_545; // @[RegisterRouter.scala:87:24] wire out_roready_1_546; // @[RegisterRouter.scala:87:24] wire out_roready_1_547; // @[RegisterRouter.scala:87:24] wire out_roready_1_548; // @[RegisterRouter.scala:87:24] wire out_roready_1_549; // @[RegisterRouter.scala:87:24] wire out_roready_1_550; // @[RegisterRouter.scala:87:24] wire out_roready_1_551; // @[RegisterRouter.scala:87:24] wire out_roready_1_552; // @[RegisterRouter.scala:87:24] wire out_roready_1_553; // @[RegisterRouter.scala:87:24] wire out_roready_1_554; // @[RegisterRouter.scala:87:24] wire out_roready_1_555; // @[RegisterRouter.scala:87:24] wire out_roready_1_556; // @[RegisterRouter.scala:87:24] wire out_roready_1_557; // @[RegisterRouter.scala:87:24] wire out_roready_1_558; // @[RegisterRouter.scala:87:24] wire out_roready_1_559; // @[RegisterRouter.scala:87:24] wire out_roready_1_560; // @[RegisterRouter.scala:87:24] wire out_roready_1_561; // @[RegisterRouter.scala:87:24] wire out_roready_1_562; // @[RegisterRouter.scala:87:24] wire out_roready_1_563; // @[RegisterRouter.scala:87:24] wire out_roready_1_564; // @[RegisterRouter.scala:87:24] wire out_roready_1_565; // @[RegisterRouter.scala:87:24] wire out_roready_1_566; // @[RegisterRouter.scala:87:24] wire out_roready_1_567; // @[RegisterRouter.scala:87:24] wire out_roready_1_568; // @[RegisterRouter.scala:87:24] wire out_roready_1_569; // @[RegisterRouter.scala:87:24] wire out_roready_1_570; // @[RegisterRouter.scala:87:24] wire out_roready_1_571; // @[RegisterRouter.scala:87:24] wire out_roready_1_572; // @[RegisterRouter.scala:87:24] wire out_roready_1_573; // @[RegisterRouter.scala:87:24] wire out_roready_1_574; // @[RegisterRouter.scala:87:24] wire out_roready_1_575; // @[RegisterRouter.scala:87:24] wire out_roready_1_576; // @[RegisterRouter.scala:87:24] wire out_roready_1_577; // @[RegisterRouter.scala:87:24] wire out_roready_1_578; // @[RegisterRouter.scala:87:24] wire out_roready_1_579; // @[RegisterRouter.scala:87:24] wire out_roready_1_580; // @[RegisterRouter.scala:87:24] wire out_roready_1_581; // @[RegisterRouter.scala:87:24] wire out_roready_1_582; // @[RegisterRouter.scala:87:24] wire out_roready_1_583; // @[RegisterRouter.scala:87:24] wire out_roready_1_584; // @[RegisterRouter.scala:87:24] wire out_roready_1_585; // @[RegisterRouter.scala:87:24] wire out_roready_1_586; // @[RegisterRouter.scala:87:24] wire out_roready_1_587; // @[RegisterRouter.scala:87:24] wire out_roready_1_588; // @[RegisterRouter.scala:87:24] wire out_roready_1_589; // @[RegisterRouter.scala:87:24] wire out_roready_1_590; // @[RegisterRouter.scala:87:24] wire out_roready_1_591; // @[RegisterRouter.scala:87:24] wire out_roready_1_592; // @[RegisterRouter.scala:87:24] wire out_roready_1_593; // @[RegisterRouter.scala:87:24] wire out_roready_1_594; // @[RegisterRouter.scala:87:24] wire out_roready_1_595; // @[RegisterRouter.scala:87:24] wire out_roready_1_596; // @[RegisterRouter.scala:87:24] wire out_roready_1_597; // @[RegisterRouter.scala:87:24] wire out_roready_1_598; // @[RegisterRouter.scala:87:24] wire out_roready_1_599; // @[RegisterRouter.scala:87:24] wire out_roready_1_600; // @[RegisterRouter.scala:87:24] wire out_roready_1_601; // @[RegisterRouter.scala:87:24] wire out_roready_1_602; // @[RegisterRouter.scala:87:24] wire out_roready_1_603; // @[RegisterRouter.scala:87:24] wire out_roready_1_604; // @[RegisterRouter.scala:87:24] wire out_roready_1_605; // @[RegisterRouter.scala:87:24] wire out_roready_1_606; // @[RegisterRouter.scala:87:24] wire out_roready_1_607; // @[RegisterRouter.scala:87:24] wire out_roready_1_608; // @[RegisterRouter.scala:87:24] wire out_roready_1_609; // @[RegisterRouter.scala:87:24] wire out_roready_1_610; // @[RegisterRouter.scala:87:24] wire out_roready_1_611; // @[RegisterRouter.scala:87:24] wire out_roready_1_612; // @[RegisterRouter.scala:87:24] wire out_roready_1_613; // @[RegisterRouter.scala:87:24] wire out_roready_1_614; // @[RegisterRouter.scala:87:24] wire out_roready_1_615; // @[RegisterRouter.scala:87:24] wire out_roready_1_616; // @[RegisterRouter.scala:87:24] wire out_roready_1_617; // @[RegisterRouter.scala:87:24] wire out_roready_1_618; // @[RegisterRouter.scala:87:24] wire out_roready_1_619; // @[RegisterRouter.scala:87:24] wire out_roready_1_620; // @[RegisterRouter.scala:87:24] wire out_roready_1_621; // @[RegisterRouter.scala:87:24] wire out_roready_1_622; // @[RegisterRouter.scala:87:24] wire out_roready_1_623; // @[RegisterRouter.scala:87:24] wire out_roready_1_624; // @[RegisterRouter.scala:87:24] wire out_roready_1_625; // @[RegisterRouter.scala:87:24] wire out_roready_1_626; // @[RegisterRouter.scala:87:24] wire out_roready_1_627; // @[RegisterRouter.scala:87:24] wire out_roready_1_628; // @[RegisterRouter.scala:87:24] wire out_roready_1_629; // @[RegisterRouter.scala:87:24] wire out_roready_1_630; // @[RegisterRouter.scala:87:24] wire out_roready_1_631; // @[RegisterRouter.scala:87:24] wire out_roready_1_632; // @[RegisterRouter.scala:87:24] wire out_roready_1_633; // @[RegisterRouter.scala:87:24] wire out_roready_1_634; // @[RegisterRouter.scala:87:24] wire out_roready_1_635; // @[RegisterRouter.scala:87:24] wire out_roready_1_636; // @[RegisterRouter.scala:87:24] wire out_roready_1_637; // @[RegisterRouter.scala:87:24] wire out_roready_1_638; // @[RegisterRouter.scala:87:24] wire out_roready_1_639; // @[RegisterRouter.scala:87:24] wire out_roready_1_640; // @[RegisterRouter.scala:87:24] wire out_roready_1_641; // @[RegisterRouter.scala:87:24] wire out_roready_1_642; // @[RegisterRouter.scala:87:24] wire out_roready_1_643; // @[RegisterRouter.scala:87:24] wire out_roready_1_644; // @[RegisterRouter.scala:87:24] wire out_roready_1_645; // @[RegisterRouter.scala:87:24] wire out_roready_1_646; // @[RegisterRouter.scala:87:24] wire out_roready_1_647; // @[RegisterRouter.scala:87:24] wire out_roready_1_648; // @[RegisterRouter.scala:87:24] wire out_roready_1_649; // @[RegisterRouter.scala:87:24] wire out_roready_1_650; // @[RegisterRouter.scala:87:24] wire out_roready_1_651; // @[RegisterRouter.scala:87:24] wire out_roready_1_652; // @[RegisterRouter.scala:87:24] wire out_roready_1_653; // @[RegisterRouter.scala:87:24] wire out_roready_1_654; // @[RegisterRouter.scala:87:24] wire out_roready_1_655; // @[RegisterRouter.scala:87:24] wire out_roready_1_656; // @[RegisterRouter.scala:87:24] wire out_roready_1_657; // @[RegisterRouter.scala:87:24] wire out_roready_1_658; // @[RegisterRouter.scala:87:24] wire out_roready_1_659; // @[RegisterRouter.scala:87:24] wire out_roready_1_660; // @[RegisterRouter.scala:87:24] wire out_roready_1_661; // @[RegisterRouter.scala:87:24] wire out_roready_1_662; // @[RegisterRouter.scala:87:24] wire out_roready_1_663; // @[RegisterRouter.scala:87:24] wire out_roready_1_664; // @[RegisterRouter.scala:87:24] wire out_roready_1_665; // @[RegisterRouter.scala:87:24] wire out_roready_1_666; // @[RegisterRouter.scala:87:24] wire out_roready_1_667; // @[RegisterRouter.scala:87:24] wire out_roready_1_668; // @[RegisterRouter.scala:87:24] wire out_roready_1_669; // @[RegisterRouter.scala:87:24] wire out_roready_1_670; // @[RegisterRouter.scala:87:24] wire out_roready_1_671; // @[RegisterRouter.scala:87:24] wire out_roready_1_672; // @[RegisterRouter.scala:87:24] wire out_roready_1_673; // @[RegisterRouter.scala:87:24] wire out_roready_1_674; // @[RegisterRouter.scala:87:24] wire out_roready_1_675; // @[RegisterRouter.scala:87:24] wire out_roready_1_676; // @[RegisterRouter.scala:87:24] wire out_roready_1_677; // @[RegisterRouter.scala:87:24] wire out_roready_1_678; // @[RegisterRouter.scala:87:24] wire out_roready_1_679; // @[RegisterRouter.scala:87:24] wire out_roready_1_680; // @[RegisterRouter.scala:87:24] wire out_roready_1_681; // @[RegisterRouter.scala:87:24] wire out_roready_1_682; // @[RegisterRouter.scala:87:24] wire out_roready_1_683; // @[RegisterRouter.scala:87:24] wire out_roready_1_684; // @[RegisterRouter.scala:87:24] wire out_roready_1_685; // @[RegisterRouter.scala:87:24] wire out_roready_1_686; // @[RegisterRouter.scala:87:24] wire out_roready_1_687; // @[RegisterRouter.scala:87:24] wire out_roready_1_688; // @[RegisterRouter.scala:87:24] wire out_roready_1_689; // @[RegisterRouter.scala:87:24] wire out_roready_1_690; // @[RegisterRouter.scala:87:24] wire out_roready_1_691; // @[RegisterRouter.scala:87:24] wire out_roready_1_692; // @[RegisterRouter.scala:87:24] wire out_roready_1_693; // @[RegisterRouter.scala:87:24] wire out_roready_1_694; // @[RegisterRouter.scala:87:24] wire out_roready_1_695; // @[RegisterRouter.scala:87:24] wire out_roready_1_696; // @[RegisterRouter.scala:87:24] wire out_roready_1_697; // @[RegisterRouter.scala:87:24] wire out_roready_1_698; // @[RegisterRouter.scala:87:24] wire out_roready_1_699; // @[RegisterRouter.scala:87:24] wire out_roready_1_700; // @[RegisterRouter.scala:87:24] wire out_roready_1_701; // @[RegisterRouter.scala:87:24] wire out_roready_1_702; // @[RegisterRouter.scala:87:24] wire out_roready_1_703; // @[RegisterRouter.scala:87:24] wire out_roready_1_704; // @[RegisterRouter.scala:87:24] wire out_roready_1_705; // @[RegisterRouter.scala:87:24] wire out_roready_1_706; // @[RegisterRouter.scala:87:24] wire out_roready_1_707; // @[RegisterRouter.scala:87:24] wire out_roready_1_708; // @[RegisterRouter.scala:87:24] wire out_roready_1_709; // @[RegisterRouter.scala:87:24] wire out_roready_1_710; // @[RegisterRouter.scala:87:24] wire out_roready_1_711; // @[RegisterRouter.scala:87:24] wire out_roready_1_712; // @[RegisterRouter.scala:87:24] wire out_roready_1_713; // @[RegisterRouter.scala:87:24] wire out_roready_1_714; // @[RegisterRouter.scala:87:24] wire out_roready_1_715; // @[RegisterRouter.scala:87:24] wire out_roready_1_716; // @[RegisterRouter.scala:87:24] wire out_roready_1_717; // @[RegisterRouter.scala:87:24] wire out_roready_1_718; // @[RegisterRouter.scala:87:24] wire out_roready_1_719; // @[RegisterRouter.scala:87:24] wire out_roready_1_720; // @[RegisterRouter.scala:87:24] wire out_roready_1_721; // @[RegisterRouter.scala:87:24] wire out_roready_1_722; // @[RegisterRouter.scala:87:24] wire out_roready_1_723; // @[RegisterRouter.scala:87:24] wire out_roready_1_724; // @[RegisterRouter.scala:87:24] wire out_roready_1_725; // @[RegisterRouter.scala:87:24] wire out_roready_1_726; // @[RegisterRouter.scala:87:24] wire out_roready_1_727; // @[RegisterRouter.scala:87:24] wire out_roready_1_728; // @[RegisterRouter.scala:87:24] wire out_roready_1_729; // @[RegisterRouter.scala:87:24] wire out_roready_1_730; // @[RegisterRouter.scala:87:24] wire out_roready_1_731; // @[RegisterRouter.scala:87:24] wire out_roready_1_732; // @[RegisterRouter.scala:87:24] wire out_roready_1_733; // @[RegisterRouter.scala:87:24] wire out_roready_1_734; // @[RegisterRouter.scala:87:24] wire out_roready_1_735; // @[RegisterRouter.scala:87:24] wire out_roready_1_736; // @[RegisterRouter.scala:87:24] wire out_roready_1_737; // @[RegisterRouter.scala:87:24] wire out_roready_1_738; // @[RegisterRouter.scala:87:24] wire out_roready_1_739; // @[RegisterRouter.scala:87:24] wire out_roready_1_740; // @[RegisterRouter.scala:87:24] wire out_roready_1_741; // @[RegisterRouter.scala:87:24] wire out_roready_1_742; // @[RegisterRouter.scala:87:24] wire out_roready_1_743; // @[RegisterRouter.scala:87:24] wire out_roready_1_744; // @[RegisterRouter.scala:87:24] wire out_roready_1_745; // @[RegisterRouter.scala:87:24] wire out_roready_1_746; // @[RegisterRouter.scala:87:24] wire out_roready_1_747; // @[RegisterRouter.scala:87:24] wire out_roready_1_748; // @[RegisterRouter.scala:87:24] wire out_roready_1_749; // @[RegisterRouter.scala:87:24] wire out_roready_1_750; // @[RegisterRouter.scala:87:24] wire out_roready_1_751; // @[RegisterRouter.scala:87:24] wire out_roready_1_752; // @[RegisterRouter.scala:87:24] wire out_roready_1_753; // @[RegisterRouter.scala:87:24] wire out_roready_1_754; // @[RegisterRouter.scala:87:24] wire out_roready_1_755; // @[RegisterRouter.scala:87:24] wire out_roready_1_756; // @[RegisterRouter.scala:87:24] wire out_roready_1_757; // @[RegisterRouter.scala:87:24] wire out_roready_1_758; // @[RegisterRouter.scala:87:24] wire out_roready_1_759; // @[RegisterRouter.scala:87:24] wire out_roready_1_760; // @[RegisterRouter.scala:87:24] wire out_roready_1_761; // @[RegisterRouter.scala:87:24] wire out_roready_1_762; // @[RegisterRouter.scala:87:24] wire out_roready_1_763; // @[RegisterRouter.scala:87:24] wire out_roready_1_764; // @[RegisterRouter.scala:87:24] wire out_roready_1_765; // @[RegisterRouter.scala:87:24] wire out_roready_1_766; // @[RegisterRouter.scala:87:24] wire out_roready_1_767; // @[RegisterRouter.scala:87:24] wire out_roready_1_768; // @[RegisterRouter.scala:87:24] wire out_roready_1_769; // @[RegisterRouter.scala:87:24] wire out_roready_1_770; // @[RegisterRouter.scala:87:24] wire out_roready_1_771; // @[RegisterRouter.scala:87:24] wire out_roready_1_772; // @[RegisterRouter.scala:87:24] wire out_roready_1_773; // @[RegisterRouter.scala:87:24] wire out_roready_1_774; // @[RegisterRouter.scala:87:24] wire out_roready_1_775; // @[RegisterRouter.scala:87:24] wire out_roready_1_776; // @[RegisterRouter.scala:87:24] wire out_roready_1_777; // @[RegisterRouter.scala:87:24] wire out_roready_1_778; // @[RegisterRouter.scala:87:24] wire out_roready_1_779; // @[RegisterRouter.scala:87:24] wire out_roready_1_780; // @[RegisterRouter.scala:87:24] wire out_roready_1_781; // @[RegisterRouter.scala:87:24] wire out_roready_1_782; // @[RegisterRouter.scala:87:24] wire out_roready_1_783; // @[RegisterRouter.scala:87:24] wire out_roready_1_784; // @[RegisterRouter.scala:87:24] wire out_roready_1_785; // @[RegisterRouter.scala:87:24] wire out_roready_1_786; // @[RegisterRouter.scala:87:24] wire out_roready_1_787; // @[RegisterRouter.scala:87:24] wire out_roready_1_788; // @[RegisterRouter.scala:87:24] wire out_roready_1_789; // @[RegisterRouter.scala:87:24] wire out_roready_1_790; // @[RegisterRouter.scala:87:24] wire out_roready_1_791; // @[RegisterRouter.scala:87:24] wire out_roready_1_792; // @[RegisterRouter.scala:87:24] wire out_roready_1_793; // @[RegisterRouter.scala:87:24] wire out_roready_1_794; // @[RegisterRouter.scala:87:24] wire out_roready_1_795; // @[RegisterRouter.scala:87:24] wire out_roready_1_796; // @[RegisterRouter.scala:87:24] wire out_roready_1_797; // @[RegisterRouter.scala:87:24] wire out_roready_1_798; // @[RegisterRouter.scala:87:24] wire out_roready_1_799; // @[RegisterRouter.scala:87:24] wire out_roready_1_800; // @[RegisterRouter.scala:87:24] wire out_roready_1_801; // @[RegisterRouter.scala:87:24] wire out_roready_1_802; // @[RegisterRouter.scala:87:24] wire out_roready_1_803; // @[RegisterRouter.scala:87:24] wire out_roready_1_804; // @[RegisterRouter.scala:87:24] wire out_roready_1_805; // @[RegisterRouter.scala:87:24] wire out_roready_1_806; // @[RegisterRouter.scala:87:24] wire out_roready_1_807; // @[RegisterRouter.scala:87:24] wire out_roready_1_808; // @[RegisterRouter.scala:87:24] wire out_roready_1_809; // @[RegisterRouter.scala:87:24] wire out_roready_1_810; // @[RegisterRouter.scala:87:24] wire out_roready_1_811; // @[RegisterRouter.scala:87:24] wire out_roready_1_812; // @[RegisterRouter.scala:87:24] wire out_roready_1_813; // @[RegisterRouter.scala:87:24] wire out_roready_1_814; // @[RegisterRouter.scala:87:24] wire out_roready_1_815; // @[RegisterRouter.scala:87:24] wire out_roready_1_816; // @[RegisterRouter.scala:87:24] wire out_roready_1_817; // @[RegisterRouter.scala:87:24] wire out_roready_1_818; // @[RegisterRouter.scala:87:24] wire out_roready_1_819; // @[RegisterRouter.scala:87:24] wire out_roready_1_820; // @[RegisterRouter.scala:87:24] wire out_roready_1_821; // @[RegisterRouter.scala:87:24] wire out_roready_1_822; // @[RegisterRouter.scala:87:24] wire out_roready_1_823; // @[RegisterRouter.scala:87:24] wire out_roready_1_824; // @[RegisterRouter.scala:87:24] wire out_roready_1_825; // @[RegisterRouter.scala:87:24] wire out_roready_1_826; // @[RegisterRouter.scala:87:24] wire out_roready_1_827; // @[RegisterRouter.scala:87:24] wire out_roready_1_828; // @[RegisterRouter.scala:87:24] wire out_roready_1_829; // @[RegisterRouter.scala:87:24] wire out_roready_1_830; // @[RegisterRouter.scala:87:24] wire out_roready_1_831; // @[RegisterRouter.scala:87:24] wire out_roready_1_832; // @[RegisterRouter.scala:87:24] wire out_roready_1_833; // @[RegisterRouter.scala:87:24] wire out_roready_1_834; // @[RegisterRouter.scala:87:24] wire out_roready_1_835; // @[RegisterRouter.scala:87:24] wire out_roready_1_836; // @[RegisterRouter.scala:87:24] wire out_roready_1_837; // @[RegisterRouter.scala:87:24] wire out_roready_1_838; // @[RegisterRouter.scala:87:24] wire out_roready_1_839; // @[RegisterRouter.scala:87:24] wire out_roready_1_840; // @[RegisterRouter.scala:87:24] wire out_roready_1_841; // @[RegisterRouter.scala:87:24] wire out_roready_1_842; // @[RegisterRouter.scala:87:24] wire out_roready_1_843; // @[RegisterRouter.scala:87:24] wire out_roready_1_844; // @[RegisterRouter.scala:87:24] wire out_roready_1_845; // @[RegisterRouter.scala:87:24] wire out_roready_1_846; // @[RegisterRouter.scala:87:24] wire out_roready_1_847; // @[RegisterRouter.scala:87:24] wire out_roready_1_848; // @[RegisterRouter.scala:87:24] wire out_roready_1_849; // @[RegisterRouter.scala:87:24] wire out_roready_1_850; // @[RegisterRouter.scala:87:24] wire out_roready_1_851; // @[RegisterRouter.scala:87:24] wire out_roready_1_852; // @[RegisterRouter.scala:87:24] wire out_roready_1_853; // @[RegisterRouter.scala:87:24] wire out_roready_1_854; // @[RegisterRouter.scala:87:24] wire out_roready_1_855; // @[RegisterRouter.scala:87:24] wire out_roready_1_856; // @[RegisterRouter.scala:87:24] wire out_roready_1_857; // @[RegisterRouter.scala:87:24] wire out_roready_1_858; // @[RegisterRouter.scala:87:24] wire out_roready_1_859; // @[RegisterRouter.scala:87:24] wire out_roready_1_860; // @[RegisterRouter.scala:87:24] wire out_roready_1_861; // @[RegisterRouter.scala:87:24] wire out_roready_1_862; // @[RegisterRouter.scala:87:24] wire out_roready_1_863; // @[RegisterRouter.scala:87:24] wire out_roready_1_864; // @[RegisterRouter.scala:87:24] wire out_roready_1_865; // @[RegisterRouter.scala:87:24] wire out_roready_1_866; // @[RegisterRouter.scala:87:24] wire out_roready_1_867; // @[RegisterRouter.scala:87:24] wire out_roready_1_868; // @[RegisterRouter.scala:87:24] wire out_roready_1_869; // @[RegisterRouter.scala:87:24] wire out_roready_1_870; // @[RegisterRouter.scala:87:24] wire out_roready_1_871; // @[RegisterRouter.scala:87:24] wire out_roready_1_872; // @[RegisterRouter.scala:87:24] wire out_roready_1_873; // @[RegisterRouter.scala:87:24] wire out_roready_1_874; // @[RegisterRouter.scala:87:24] wire out_roready_1_875; // @[RegisterRouter.scala:87:24] wire out_roready_1_876; // @[RegisterRouter.scala:87:24] wire out_roready_1_877; // @[RegisterRouter.scala:87:24] wire out_roready_1_878; // @[RegisterRouter.scala:87:24] wire out_roready_1_879; // @[RegisterRouter.scala:87:24] wire out_roready_1_880; // @[RegisterRouter.scala:87:24] wire out_roready_1_881; // @[RegisterRouter.scala:87:24] wire out_roready_1_882; // @[RegisterRouter.scala:87:24] wire out_roready_1_883; // @[RegisterRouter.scala:87:24] wire out_roready_1_884; // @[RegisterRouter.scala:87:24] wire out_roready_1_885; // @[RegisterRouter.scala:87:24] wire out_roready_1_886; // @[RegisterRouter.scala:87:24] wire out_roready_1_887; // @[RegisterRouter.scala:87:24] wire out_roready_1_888; // @[RegisterRouter.scala:87:24] wire out_roready_1_889; // @[RegisterRouter.scala:87:24] wire out_roready_1_890; // @[RegisterRouter.scala:87:24] wire out_roready_1_891; // @[RegisterRouter.scala:87:24] wire out_roready_1_892; // @[RegisterRouter.scala:87:24] wire out_roready_1_893; // @[RegisterRouter.scala:87:24] wire out_roready_1_894; // @[RegisterRouter.scala:87:24] wire out_roready_1_895; // @[RegisterRouter.scala:87:24] wire out_roready_1_896; // @[RegisterRouter.scala:87:24] wire out_roready_1_897; // @[RegisterRouter.scala:87:24] wire out_roready_1_898; // @[RegisterRouter.scala:87:24] wire out_roready_1_899; // @[RegisterRouter.scala:87:24] wire out_roready_1_900; // @[RegisterRouter.scala:87:24] wire out_roready_1_901; // @[RegisterRouter.scala:87:24] wire out_roready_1_902; // @[RegisterRouter.scala:87:24] wire out_roready_1_903; // @[RegisterRouter.scala:87:24] wire out_roready_1_904; // @[RegisterRouter.scala:87:24] wire out_roready_1_905; // @[RegisterRouter.scala:87:24] wire out_roready_1_906; // @[RegisterRouter.scala:87:24] wire out_roready_1_907; // @[RegisterRouter.scala:87:24] wire out_roready_1_908; // @[RegisterRouter.scala:87:24] wire out_roready_1_909; // @[RegisterRouter.scala:87:24] wire out_roready_1_910; // @[RegisterRouter.scala:87:24] wire out_roready_1_911; // @[RegisterRouter.scala:87:24] wire out_roready_1_912; // @[RegisterRouter.scala:87:24] wire out_roready_1_913; // @[RegisterRouter.scala:87:24] wire out_roready_1_914; // @[RegisterRouter.scala:87:24] wire out_roready_1_915; // @[RegisterRouter.scala:87:24] wire out_roready_1_916; // @[RegisterRouter.scala:87:24] wire out_roready_1_917; // @[RegisterRouter.scala:87:24] wire out_roready_1_918; // @[RegisterRouter.scala:87:24] wire out_roready_1_919; // @[RegisterRouter.scala:87:24] wire out_roready_1_920; // @[RegisterRouter.scala:87:24] wire out_roready_1_921; // @[RegisterRouter.scala:87:24] wire out_roready_1_922; // @[RegisterRouter.scala:87:24] wire out_roready_1_923; // @[RegisterRouter.scala:87:24] wire out_roready_1_924; // @[RegisterRouter.scala:87:24] wire out_roready_1_925; // @[RegisterRouter.scala:87:24] wire out_roready_1_926; // @[RegisterRouter.scala:87:24] wire out_roready_1_927; // @[RegisterRouter.scala:87:24] wire out_roready_1_928; // @[RegisterRouter.scala:87:24] wire out_roready_1_929; // @[RegisterRouter.scala:87:24] wire out_roready_1_930; // @[RegisterRouter.scala:87:24] wire out_roready_1_931; // @[RegisterRouter.scala:87:24] wire out_roready_1_932; // @[RegisterRouter.scala:87:24] wire out_roready_1_933; // @[RegisterRouter.scala:87:24] wire out_roready_1_934; // @[RegisterRouter.scala:87:24] wire out_roready_1_935; // @[RegisterRouter.scala:87:24] wire out_roready_1_936; // @[RegisterRouter.scala:87:24] wire out_roready_1_937; // @[RegisterRouter.scala:87:24] wire out_roready_1_938; // @[RegisterRouter.scala:87:24] wire out_roready_1_939; // @[RegisterRouter.scala:87:24] wire out_roready_1_940; // @[RegisterRouter.scala:87:24] wire out_roready_1_941; // @[RegisterRouter.scala:87:24] wire out_roready_1_942; // @[RegisterRouter.scala:87:24] wire out_roready_1_943; // @[RegisterRouter.scala:87:24] wire out_roready_1_944; // @[RegisterRouter.scala:87:24] wire out_roready_1_945; // @[RegisterRouter.scala:87:24] wire out_roready_1_946; // @[RegisterRouter.scala:87:24] wire out_roready_1_947; // @[RegisterRouter.scala:87:24] wire out_roready_1_948; // @[RegisterRouter.scala:87:24] wire out_roready_1_949; // @[RegisterRouter.scala:87:24] wire out_roready_1_950; // @[RegisterRouter.scala:87:24] wire out_roready_1_951; // @[RegisterRouter.scala:87:24] wire out_roready_1_952; // @[RegisterRouter.scala:87:24] wire out_roready_1_953; // @[RegisterRouter.scala:87:24] wire out_roready_1_954; // @[RegisterRouter.scala:87:24] wire out_roready_1_955; // @[RegisterRouter.scala:87:24] wire out_roready_1_956; // @[RegisterRouter.scala:87:24] wire out_roready_1_957; // @[RegisterRouter.scala:87:24] wire out_roready_1_958; // @[RegisterRouter.scala:87:24] wire out_roready_1_959; // @[RegisterRouter.scala:87:24] wire out_roready_1_960; // @[RegisterRouter.scala:87:24] wire out_roready_1_961; // @[RegisterRouter.scala:87:24] wire out_roready_1_962; // @[RegisterRouter.scala:87:24] wire out_roready_1_963; // @[RegisterRouter.scala:87:24] wire out_roready_1_964; // @[RegisterRouter.scala:87:24] wire out_roready_1_965; // @[RegisterRouter.scala:87:24] wire out_roready_1_966; // @[RegisterRouter.scala:87:24] wire out_roready_1_967; // @[RegisterRouter.scala:87:24] wire out_roready_1_968; // @[RegisterRouter.scala:87:24] wire out_roready_1_969; // @[RegisterRouter.scala:87:24] wire out_roready_1_970; // @[RegisterRouter.scala:87:24] wire out_roready_1_971; // @[RegisterRouter.scala:87:24] wire out_roready_1_972; // @[RegisterRouter.scala:87:24] wire out_roready_1_973; // @[RegisterRouter.scala:87:24] wire out_roready_1_974; // @[RegisterRouter.scala:87:24] wire out_roready_1_975; // @[RegisterRouter.scala:87:24] wire out_roready_1_976; // @[RegisterRouter.scala:87:24] wire out_roready_1_977; // @[RegisterRouter.scala:87:24] wire out_roready_1_978; // @[RegisterRouter.scala:87:24] wire out_roready_1_979; // @[RegisterRouter.scala:87:24] wire out_roready_1_980; // @[RegisterRouter.scala:87:24] wire out_roready_1_981; // @[RegisterRouter.scala:87:24] wire out_roready_1_982; // @[RegisterRouter.scala:87:24] wire out_roready_1_983; // @[RegisterRouter.scala:87:24] wire out_roready_1_984; // @[RegisterRouter.scala:87:24] wire out_roready_1_985; // @[RegisterRouter.scala:87:24] wire out_roready_1_986; // @[RegisterRouter.scala:87:24] wire out_roready_1_987; // @[RegisterRouter.scala:87:24] wire out_roready_1_988; // @[RegisterRouter.scala:87:24] wire out_roready_1_989; // @[RegisterRouter.scala:87:24] wire out_roready_1_990; // @[RegisterRouter.scala:87:24] wire out_roready_1_991; // @[RegisterRouter.scala:87:24] wire out_roready_1_992; // @[RegisterRouter.scala:87:24] wire out_roready_1_993; // @[RegisterRouter.scala:87:24] wire out_roready_1_994; // @[RegisterRouter.scala:87:24] wire out_roready_1_995; // @[RegisterRouter.scala:87:24] wire out_roready_1_996; // @[RegisterRouter.scala:87:24] wire out_roready_1_997; // @[RegisterRouter.scala:87:24] wire out_roready_1_998; // @[RegisterRouter.scala:87:24] wire out_roready_1_999; // @[RegisterRouter.scala:87:24] wire out_roready_1_1000; // @[RegisterRouter.scala:87:24] wire out_roready_1_1001; // @[RegisterRouter.scala:87:24] wire out_roready_1_1002; // @[RegisterRouter.scala:87:24] wire out_roready_1_1003; // @[RegisterRouter.scala:87:24] wire out_roready_1_1004; // @[RegisterRouter.scala:87:24] wire out_roready_1_1005; // @[RegisterRouter.scala:87:24] wire out_roready_1_1006; // @[RegisterRouter.scala:87:24] wire out_roready_1_1007; // @[RegisterRouter.scala:87:24] wire out_roready_1_1008; // @[RegisterRouter.scala:87:24] wire out_roready_1_1009; // @[RegisterRouter.scala:87:24] wire out_roready_1_1010; // @[RegisterRouter.scala:87:24] wire out_roready_1_1011; // @[RegisterRouter.scala:87:24] wire out_roready_1_1012; // @[RegisterRouter.scala:87:24] wire out_roready_1_1013; // @[RegisterRouter.scala:87:24] wire out_roready_1_1014; // @[RegisterRouter.scala:87:24] wire out_roready_1_1015; // @[RegisterRouter.scala:87:24] wire out_roready_1_1016; // @[RegisterRouter.scala:87:24] wire out_roready_1_1017; // @[RegisterRouter.scala:87:24] wire out_roready_1_1018; // @[RegisterRouter.scala:87:24] wire out_roready_1_1019; // @[RegisterRouter.scala:87:24] wire out_roready_1_1020; // @[RegisterRouter.scala:87:24] wire out_roready_1_1021; // @[RegisterRouter.scala:87:24] wire out_roready_1_1022; // @[RegisterRouter.scala:87:24] wire out_roready_1_1023; // @[RegisterRouter.scala:87:24] wire out_roready_1_1024; // @[RegisterRouter.scala:87:24] wire out_roready_1_1025; // @[RegisterRouter.scala:87:24] wire out_roready_1_1026; // @[RegisterRouter.scala:87:24] wire out_roready_1_1027; // @[RegisterRouter.scala:87:24] wire out_roready_1_1028; // @[RegisterRouter.scala:87:24] wire out_roready_1_1029; // @[RegisterRouter.scala:87:24] wire out_roready_1_1030; // @[RegisterRouter.scala:87:24] wire out_roready_1_1031; // @[RegisterRouter.scala:87:24] wire out_roready_1_1032; // @[RegisterRouter.scala:87:24] wire out_roready_1_1033; // @[RegisterRouter.scala:87:24] wire out_roready_1_1034; // @[RegisterRouter.scala:87:24] wire out_roready_1_1035; // @[RegisterRouter.scala:87:24] wire out_roready_1_1036; // @[RegisterRouter.scala:87:24] wire out_roready_1_1037; // @[RegisterRouter.scala:87:24] wire out_roready_1_1038; // @[RegisterRouter.scala:87:24] wire out_roready_1_1039; // @[RegisterRouter.scala:87:24] wire out_roready_1_1040; // @[RegisterRouter.scala:87:24] wire out_roready_1_1041; // @[RegisterRouter.scala:87:24] wire out_roready_1_1042; // @[RegisterRouter.scala:87:24] wire out_roready_1_1043; // @[RegisterRouter.scala:87:24] wire out_roready_1_1044; // @[RegisterRouter.scala:87:24] wire out_roready_1_1045; // @[RegisterRouter.scala:87:24] wire out_roready_1_1046; // @[RegisterRouter.scala:87:24] wire out_roready_1_1047; // @[RegisterRouter.scala:87:24] wire out_roready_1_1048; // @[RegisterRouter.scala:87:24] wire out_roready_1_1049; // @[RegisterRouter.scala:87:24] wire out_roready_1_1050; // @[RegisterRouter.scala:87:24] wire out_roready_1_1051; // @[RegisterRouter.scala:87:24] wire out_roready_1_1052; // @[RegisterRouter.scala:87:24] wire out_roready_1_1053; // @[RegisterRouter.scala:87:24] wire out_roready_1_1054; // @[RegisterRouter.scala:87:24] wire out_roready_1_1055; // @[RegisterRouter.scala:87:24] wire out_roready_1_1056; // @[RegisterRouter.scala:87:24] wire out_roready_1_1057; // @[RegisterRouter.scala:87:24] wire out_roready_1_1058; // @[RegisterRouter.scala:87:24] wire out_roready_1_1059; // @[RegisterRouter.scala:87:24] wire out_roready_1_1060; // @[RegisterRouter.scala:87:24] wire out_roready_1_1061; // @[RegisterRouter.scala:87:24] wire out_roready_1_1062; // @[RegisterRouter.scala:87:24] wire out_roready_1_1063; // @[RegisterRouter.scala:87:24] wire out_roready_1_1064; // @[RegisterRouter.scala:87:24] wire out_roready_1_1065; // @[RegisterRouter.scala:87:24] wire out_roready_1_1066; // @[RegisterRouter.scala:87:24] wire out_roready_1_1067; // @[RegisterRouter.scala:87:24] wire out_roready_1_1068; // @[RegisterRouter.scala:87:24] wire out_roready_1_1069; // @[RegisterRouter.scala:87:24] wire out_roready_1_1070; // @[RegisterRouter.scala:87:24] wire out_roready_1_1071; // @[RegisterRouter.scala:87:24] wire out_roready_1_1072; // @[RegisterRouter.scala:87:24] wire out_roready_1_1073; // @[RegisterRouter.scala:87:24] wire out_roready_1_1074; // @[RegisterRouter.scala:87:24] wire out_roready_1_1075; // @[RegisterRouter.scala:87:24] wire out_roready_1_1076; // @[RegisterRouter.scala:87:24] wire out_roready_1_1077; // @[RegisterRouter.scala:87:24] wire out_roready_1_1078; // @[RegisterRouter.scala:87:24] wire out_roready_1_1079; // @[RegisterRouter.scala:87:24] wire out_roready_1_1080; // @[RegisterRouter.scala:87:24] wire out_roready_1_1081; // @[RegisterRouter.scala:87:24] wire out_roready_1_1082; // @[RegisterRouter.scala:87:24] wire out_roready_1_1083; // @[RegisterRouter.scala:87:24] wire out_roready_1_1084; // @[RegisterRouter.scala:87:24] wire out_roready_1_1085; // @[RegisterRouter.scala:87:24] wire out_roready_1_1086; // @[RegisterRouter.scala:87:24] wire out_roready_1_1087; // @[RegisterRouter.scala:87:24] wire out_roready_1_1088; // @[RegisterRouter.scala:87:24] wire out_roready_1_1089; // @[RegisterRouter.scala:87:24] wire out_roready_1_1090; // @[RegisterRouter.scala:87:24] wire out_roready_1_1091; // @[RegisterRouter.scala:87:24] wire out_roready_1_1092; // @[RegisterRouter.scala:87:24] wire out_roready_1_1093; // @[RegisterRouter.scala:87:24] wire out_roready_1_1094; // @[RegisterRouter.scala:87:24] wire out_roready_1_1095; // @[RegisterRouter.scala:87:24] wire out_roready_1_1096; // @[RegisterRouter.scala:87:24] wire out_roready_1_1097; // @[RegisterRouter.scala:87:24] wire out_roready_1_1098; // @[RegisterRouter.scala:87:24] wire out_roready_1_1099; // @[RegisterRouter.scala:87:24] wire out_roready_1_1100; // @[RegisterRouter.scala:87:24] wire out_roready_1_1101; // @[RegisterRouter.scala:87:24] wire out_roready_1_1102; // @[RegisterRouter.scala:87:24] wire out_roready_1_1103; // @[RegisterRouter.scala:87:24] wire out_roready_1_1104; // @[RegisterRouter.scala:87:24] wire out_roready_1_1105; // @[RegisterRouter.scala:87:24] wire out_roready_1_1106; // @[RegisterRouter.scala:87:24] wire out_roready_1_1107; // @[RegisterRouter.scala:87:24] wire out_roready_1_1108; // @[RegisterRouter.scala:87:24] wire out_roready_1_1109; // @[RegisterRouter.scala:87:24] wire out_roready_1_1110; // @[RegisterRouter.scala:87:24] wire out_roready_1_1111; // @[RegisterRouter.scala:87:24] wire out_roready_1_1112; // @[RegisterRouter.scala:87:24] wire out_roready_1_1113; // @[RegisterRouter.scala:87:24] wire out_roready_1_1114; // @[RegisterRouter.scala:87:24] wire out_roready_1_1115; // @[RegisterRouter.scala:87:24] wire out_roready_1_1116; // @[RegisterRouter.scala:87:24] wire out_roready_1_1117; // @[RegisterRouter.scala:87:24] wire out_roready_1_1118; // @[RegisterRouter.scala:87:24] wire out_roready_1_1119; // @[RegisterRouter.scala:87:24] wire out_roready_1_1120; // @[RegisterRouter.scala:87:24] wire out_roready_1_1121; // @[RegisterRouter.scala:87:24] wire out_roready_1_1122; // @[RegisterRouter.scala:87:24] wire out_roready_1_1123; // @[RegisterRouter.scala:87:24] wire out_roready_1_1124; // @[RegisterRouter.scala:87:24] wire out_roready_1_1125; // @[RegisterRouter.scala:87:24] wire out_roready_1_1126; // @[RegisterRouter.scala:87:24] wire out_roready_1_1127; // @[RegisterRouter.scala:87:24] wire out_roready_1_1128; // @[RegisterRouter.scala:87:24] wire out_roready_1_1129; // @[RegisterRouter.scala:87:24] wire out_roready_1_1130; // @[RegisterRouter.scala:87:24] wire out_roready_1_1131; // @[RegisterRouter.scala:87:24] wire out_roready_1_1132; // @[RegisterRouter.scala:87:24] wire out_roready_1_1133; // @[RegisterRouter.scala:87:24] wire out_roready_1_1134; // @[RegisterRouter.scala:87:24] wire out_roready_1_1135; // @[RegisterRouter.scala:87:24] wire out_roready_1_1136; // @[RegisterRouter.scala:87:24] wire out_roready_1_1137; // @[RegisterRouter.scala:87:24] wire out_roready_1_1138; // @[RegisterRouter.scala:87:24] wire out_roready_1_1139; // @[RegisterRouter.scala:87:24] wire out_roready_1_1140; // @[RegisterRouter.scala:87:24] wire out_roready_1_1141; // @[RegisterRouter.scala:87:24] wire out_roready_1_1142; // @[RegisterRouter.scala:87:24] wire out_roready_1_1143; // @[RegisterRouter.scala:87:24] wire out_roready_1_1144; // @[RegisterRouter.scala:87:24] wire out_roready_1_1145; // @[RegisterRouter.scala:87:24] wire out_roready_1_1146; // @[RegisterRouter.scala:87:24] wire out_roready_1_1147; // @[RegisterRouter.scala:87:24] wire out_roready_1_1148; // @[RegisterRouter.scala:87:24] wire out_roready_1_1149; // @[RegisterRouter.scala:87:24] wire out_roready_1_1150; // @[RegisterRouter.scala:87:24] wire out_roready_1_1151; // @[RegisterRouter.scala:87:24] wire out_roready_1_1152; // @[RegisterRouter.scala:87:24] wire out_roready_1_1153; // @[RegisterRouter.scala:87:24] wire out_roready_1_1154; // @[RegisterRouter.scala:87:24] wire out_roready_1_1155; // @[RegisterRouter.scala:87:24] wire out_roready_1_1156; // @[RegisterRouter.scala:87:24] wire out_roready_1_1157; // @[RegisterRouter.scala:87:24] wire out_roready_1_1158; // @[RegisterRouter.scala:87:24] wire out_roready_1_1159; // @[RegisterRouter.scala:87:24] wire out_roready_1_1160; // @[RegisterRouter.scala:87:24] wire out_roready_1_1161; // @[RegisterRouter.scala:87:24] wire out_roready_1_1162; // @[RegisterRouter.scala:87:24] wire out_roready_1_1163; // @[RegisterRouter.scala:87:24] wire out_roready_1_1164; // @[RegisterRouter.scala:87:24] wire out_roready_1_1165; // @[RegisterRouter.scala:87:24] wire out_roready_1_1166; // @[RegisterRouter.scala:87:24] wire out_roready_1_1167; // @[RegisterRouter.scala:87:24] wire out_roready_1_1168; // @[RegisterRouter.scala:87:24] wire out_roready_1_1169; // @[RegisterRouter.scala:87:24] wire out_roready_1_1170; // @[RegisterRouter.scala:87:24] wire out_roready_1_1171; // @[RegisterRouter.scala:87:24] wire out_roready_1_1172; // @[RegisterRouter.scala:87:24] wire out_roready_1_1173; // @[RegisterRouter.scala:87:24] wire out_roready_1_1174; // @[RegisterRouter.scala:87:24] wire out_roready_1_1175; // @[RegisterRouter.scala:87:24] wire out_roready_1_1176; // @[RegisterRouter.scala:87:24] wire out_roready_1_1177; // @[RegisterRouter.scala:87:24] wire out_roready_1_1178; // @[RegisterRouter.scala:87:24] wire out_roready_1_1179; // @[RegisterRouter.scala:87:24] wire out_roready_1_1180; // @[RegisterRouter.scala:87:24] wire out_roready_1_1181; // @[RegisterRouter.scala:87:24] wire out_roready_1_1182; // @[RegisterRouter.scala:87:24] wire out_roready_1_1183; // @[RegisterRouter.scala:87:24] wire out_roready_1_1184; // @[RegisterRouter.scala:87:24] wire out_roready_1_1185; // @[RegisterRouter.scala:87:24] wire out_roready_1_1186; // @[RegisterRouter.scala:87:24] wire out_roready_1_1187; // @[RegisterRouter.scala:87:24] wire out_roready_1_1188; // @[RegisterRouter.scala:87:24] wire out_roready_1_1189; // @[RegisterRouter.scala:87:24] wire out_roready_1_1190; // @[RegisterRouter.scala:87:24] wire out_roready_1_1191; // @[RegisterRouter.scala:87:24] wire out_roready_1_1192; // @[RegisterRouter.scala:87:24] wire out_roready_1_1193; // @[RegisterRouter.scala:87:24] wire out_roready_1_1194; // @[RegisterRouter.scala:87:24] wire out_roready_1_1195; // @[RegisterRouter.scala:87:24] wire out_roready_1_1196; // @[RegisterRouter.scala:87:24] wire out_roready_1_1197; // @[RegisterRouter.scala:87:24] wire out_roready_1_1198; // @[RegisterRouter.scala:87:24] wire out_roready_1_1199; // @[RegisterRouter.scala:87:24] wire out_roready_1_1200; // @[RegisterRouter.scala:87:24] wire out_roready_1_1201; // @[RegisterRouter.scala:87:24] wire out_roready_1_1202; // @[RegisterRouter.scala:87:24] wire out_roready_1_1203; // @[RegisterRouter.scala:87:24] wire out_roready_1_1204; // @[RegisterRouter.scala:87:24] wire out_roready_1_1205; // @[RegisterRouter.scala:87:24] wire out_roready_1_1206; // @[RegisterRouter.scala:87:24] wire out_roready_1_1207; // @[RegisterRouter.scala:87:24] wire out_roready_1_1208; // @[RegisterRouter.scala:87:24] wire out_roready_1_1209; // @[RegisterRouter.scala:87:24] wire out_roready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_0; // @[RegisterRouter.scala:87:24] wire out_woready_1_1; // @[RegisterRouter.scala:87:24] wire out_woready_1_2; // @[RegisterRouter.scala:87:24] wire out_woready_1_3; // @[RegisterRouter.scala:87:24] wire out_woready_1_4; // @[RegisterRouter.scala:87:24] wire out_woready_1_5; // @[RegisterRouter.scala:87:24] wire out_woready_1_6; // @[RegisterRouter.scala:87:24] wire out_woready_1_7; // @[RegisterRouter.scala:87:24] wire out_woready_1_8; // @[RegisterRouter.scala:87:24] wire out_woready_1_9; // @[RegisterRouter.scala:87:24] wire out_woready_1_10; // @[RegisterRouter.scala:87:24] wire out_woready_1_11; // @[RegisterRouter.scala:87:24] wire out_woready_1_12; // @[RegisterRouter.scala:87:24] wire out_woready_1_13; // @[RegisterRouter.scala:87:24] wire out_woready_1_14; // @[RegisterRouter.scala:87:24] wire out_woready_1_15; // @[RegisterRouter.scala:87:24] wire out_woready_1_16; // @[RegisterRouter.scala:87:24] wire out_woready_1_17; // @[RegisterRouter.scala:87:24] wire out_woready_1_18; // @[RegisterRouter.scala:87:24] wire out_woready_1_19; // @[RegisterRouter.scala:87:24] wire out_woready_1_20; // @[RegisterRouter.scala:87:24] wire out_woready_1_21; // @[RegisterRouter.scala:87:24] wire out_woready_1_22; // @[RegisterRouter.scala:87:24] wire out_woready_1_23; // @[RegisterRouter.scala:87:24] wire out_woready_1_24; // @[RegisterRouter.scala:87:24] wire out_woready_1_25; // @[RegisterRouter.scala:87:24] wire out_woready_1_26; // @[RegisterRouter.scala:87:24] wire out_woready_1_27; // @[RegisterRouter.scala:87:24] wire out_woready_1_28; // @[RegisterRouter.scala:87:24] wire out_woready_1_29; // @[RegisterRouter.scala:87:24] wire out_woready_1_30; // @[RegisterRouter.scala:87:24] wire out_woready_1_31; // @[RegisterRouter.scala:87:24] wire out_woready_1_32; // @[RegisterRouter.scala:87:24] wire out_woready_1_33; // @[RegisterRouter.scala:87:24] wire out_woready_1_34; // @[RegisterRouter.scala:87:24] wire out_woready_1_35; // @[RegisterRouter.scala:87:24] wire out_woready_1_36; // @[RegisterRouter.scala:87:24] wire out_woready_1_37; // @[RegisterRouter.scala:87:24] wire out_woready_1_38; // @[RegisterRouter.scala:87:24] wire out_woready_1_39; // @[RegisterRouter.scala:87:24] wire out_woready_1_40; // @[RegisterRouter.scala:87:24] wire out_woready_1_41; // @[RegisterRouter.scala:87:24] wire out_woready_1_42; // @[RegisterRouter.scala:87:24] wire out_woready_1_43; // @[RegisterRouter.scala:87:24] wire out_woready_1_44; // @[RegisterRouter.scala:87:24] wire out_woready_1_45; // @[RegisterRouter.scala:87:24] wire out_woready_1_46; // @[RegisterRouter.scala:87:24] wire out_woready_1_47; // @[RegisterRouter.scala:87:24] wire out_woready_1_48; // @[RegisterRouter.scala:87:24] wire out_woready_1_49; // @[RegisterRouter.scala:87:24] wire out_woready_1_50; // @[RegisterRouter.scala:87:24] wire out_woready_1_51; // @[RegisterRouter.scala:87:24] wire out_woready_1_52; // @[RegisterRouter.scala:87:24] wire out_woready_1_53; // @[RegisterRouter.scala:87:24] wire out_woready_1_54; // @[RegisterRouter.scala:87:24] wire out_woready_1_55; // @[RegisterRouter.scala:87:24] wire out_woready_1_56; // @[RegisterRouter.scala:87:24] wire out_woready_1_57; // @[RegisterRouter.scala:87:24] wire out_woready_1_58; // @[RegisterRouter.scala:87:24] wire out_woready_1_59; // @[RegisterRouter.scala:87:24] wire out_woready_1_60; // @[RegisterRouter.scala:87:24] wire out_woready_1_61; // @[RegisterRouter.scala:87:24] wire out_woready_1_62; // @[RegisterRouter.scala:87:24] wire out_woready_1_63; // @[RegisterRouter.scala:87:24] wire out_woready_1_64; // @[RegisterRouter.scala:87:24] wire out_woready_1_65; // @[RegisterRouter.scala:87:24] wire out_woready_1_66; // @[RegisterRouter.scala:87:24] wire out_woready_1_67; // @[RegisterRouter.scala:87:24] wire out_woready_1_68; // @[RegisterRouter.scala:87:24] wire out_woready_1_69; // @[RegisterRouter.scala:87:24] wire out_woready_1_70; // @[RegisterRouter.scala:87:24] wire out_woready_1_71; // @[RegisterRouter.scala:87:24] wire out_woready_1_72; // @[RegisterRouter.scala:87:24] wire out_woready_1_73; // @[RegisterRouter.scala:87:24] wire out_woready_1_74; // @[RegisterRouter.scala:87:24] wire out_woready_1_75; // @[RegisterRouter.scala:87:24] wire out_woready_1_76; // @[RegisterRouter.scala:87:24] wire out_woready_1_77; // @[RegisterRouter.scala:87:24] wire out_woready_1_78; // @[RegisterRouter.scala:87:24] wire out_woready_1_79; // @[RegisterRouter.scala:87:24] wire out_woready_1_80; // @[RegisterRouter.scala:87:24] wire out_woready_1_81; // @[RegisterRouter.scala:87:24] wire out_woready_1_82; // @[RegisterRouter.scala:87:24] wire out_woready_1_83; // @[RegisterRouter.scala:87:24] wire out_woready_1_84; // @[RegisterRouter.scala:87:24] wire out_woready_1_85; // @[RegisterRouter.scala:87:24] wire out_woready_1_86; // @[RegisterRouter.scala:87:24] wire out_woready_1_87; // @[RegisterRouter.scala:87:24] wire out_woready_1_88; // @[RegisterRouter.scala:87:24] wire out_woready_1_89; // @[RegisterRouter.scala:87:24] wire out_woready_1_90; // @[RegisterRouter.scala:87:24] wire out_woready_1_91; // @[RegisterRouter.scala:87:24] wire out_woready_1_92; // @[RegisterRouter.scala:87:24] wire out_woready_1_93; // @[RegisterRouter.scala:87:24] wire out_woready_1_94; // @[RegisterRouter.scala:87:24] wire out_woready_1_95; // @[RegisterRouter.scala:87:24] wire out_woready_1_96; // @[RegisterRouter.scala:87:24] wire out_woready_1_97; // @[RegisterRouter.scala:87:24] wire out_woready_1_98; // @[RegisterRouter.scala:87:24] wire out_woready_1_99; // @[RegisterRouter.scala:87:24] wire out_woready_1_100; // @[RegisterRouter.scala:87:24] wire out_woready_1_101; // @[RegisterRouter.scala:87:24] wire out_woready_1_102; // @[RegisterRouter.scala:87:24] wire out_woready_1_103; // @[RegisterRouter.scala:87:24] wire out_woready_1_104; // @[RegisterRouter.scala:87:24] wire out_woready_1_105; // @[RegisterRouter.scala:87:24] wire out_woready_1_106; // @[RegisterRouter.scala:87:24] wire out_woready_1_107; // @[RegisterRouter.scala:87:24] wire out_woready_1_108; // @[RegisterRouter.scala:87:24] wire out_woready_1_109; // @[RegisterRouter.scala:87:24] wire out_woready_1_110; // @[RegisterRouter.scala:87:24] wire out_woready_1_111; // @[RegisterRouter.scala:87:24] wire out_woready_1_112; // @[RegisterRouter.scala:87:24] wire out_woready_1_113; // @[RegisterRouter.scala:87:24] wire out_woready_1_114; // @[RegisterRouter.scala:87:24] wire out_woready_1_115; // @[RegisterRouter.scala:87:24] wire out_woready_1_116; // @[RegisterRouter.scala:87:24] wire out_woready_1_117; // @[RegisterRouter.scala:87:24] wire out_woready_1_118; // @[RegisterRouter.scala:87:24] wire out_woready_1_119; // @[RegisterRouter.scala:87:24] wire out_woready_1_120; // @[RegisterRouter.scala:87:24] wire out_woready_1_121; // @[RegisterRouter.scala:87:24] wire out_woready_1_122; // @[RegisterRouter.scala:87:24] wire out_woready_1_123; // @[RegisterRouter.scala:87:24] wire out_woready_1_124; // @[RegisterRouter.scala:87:24] wire out_woready_1_125; // @[RegisterRouter.scala:87:24] wire out_woready_1_126; // @[RegisterRouter.scala:87:24] wire out_woready_1_127; // @[RegisterRouter.scala:87:24] wire out_woready_1_128; // @[RegisterRouter.scala:87:24] wire out_woready_1_129; // @[RegisterRouter.scala:87:24] wire out_woready_1_130; // @[RegisterRouter.scala:87:24] wire out_woready_1_131; // @[RegisterRouter.scala:87:24] wire out_woready_1_132; // @[RegisterRouter.scala:87:24] wire out_woready_1_133; // @[RegisterRouter.scala:87:24] wire out_woready_1_134; // @[RegisterRouter.scala:87:24] wire out_woready_1_135; // @[RegisterRouter.scala:87:24] wire out_woready_1_136; // @[RegisterRouter.scala:87:24] wire out_woready_1_137; // @[RegisterRouter.scala:87:24] wire out_woready_1_138; // @[RegisterRouter.scala:87:24] wire out_woready_1_139; // @[RegisterRouter.scala:87:24] wire out_woready_1_140; // @[RegisterRouter.scala:87:24] wire out_woready_1_141; // @[RegisterRouter.scala:87:24] wire out_woready_1_142; // @[RegisterRouter.scala:87:24] wire out_woready_1_143; // @[RegisterRouter.scala:87:24] wire out_woready_1_144; // @[RegisterRouter.scala:87:24] wire out_woready_1_145; // @[RegisterRouter.scala:87:24] wire out_woready_1_146; // @[RegisterRouter.scala:87:24] wire out_woready_1_147; // @[RegisterRouter.scala:87:24] wire out_woready_1_148; // @[RegisterRouter.scala:87:24] wire out_woready_1_149; // @[RegisterRouter.scala:87:24] wire out_woready_1_150; // @[RegisterRouter.scala:87:24] wire out_woready_1_151; // @[RegisterRouter.scala:87:24] wire out_woready_1_152; // @[RegisterRouter.scala:87:24] wire out_woready_1_153; // @[RegisterRouter.scala:87:24] wire out_woready_1_154; // @[RegisterRouter.scala:87:24] wire out_woready_1_155; // @[RegisterRouter.scala:87:24] wire out_woready_1_156; // @[RegisterRouter.scala:87:24] wire out_woready_1_157; // @[RegisterRouter.scala:87:24] wire out_woready_1_158; // @[RegisterRouter.scala:87:24] wire out_woready_1_159; // @[RegisterRouter.scala:87:24] wire out_woready_1_160; // @[RegisterRouter.scala:87:24] wire out_woready_1_161; // @[RegisterRouter.scala:87:24] wire out_woready_1_162; // @[RegisterRouter.scala:87:24] wire out_woready_1_163; // @[RegisterRouter.scala:87:24] wire out_woready_1_164; // @[RegisterRouter.scala:87:24] wire out_woready_1_165; // @[RegisterRouter.scala:87:24] wire out_woready_1_166; // @[RegisterRouter.scala:87:24] wire out_woready_1_167; // @[RegisterRouter.scala:87:24] wire out_woready_1_168; // @[RegisterRouter.scala:87:24] wire out_woready_1_169; // @[RegisterRouter.scala:87:24] wire out_woready_1_170; // @[RegisterRouter.scala:87:24] wire out_woready_1_171; // @[RegisterRouter.scala:87:24] wire out_woready_1_172; // @[RegisterRouter.scala:87:24] wire out_woready_1_173; // @[RegisterRouter.scala:87:24] wire out_woready_1_174; // @[RegisterRouter.scala:87:24] wire out_woready_1_175; // @[RegisterRouter.scala:87:24] wire out_woready_1_176; // @[RegisterRouter.scala:87:24] wire out_woready_1_177; // @[RegisterRouter.scala:87:24] wire out_woready_1_178; // @[RegisterRouter.scala:87:24] wire out_woready_1_179; // @[RegisterRouter.scala:87:24] wire out_woready_1_180; // @[RegisterRouter.scala:87:24] wire out_woready_1_181; // @[RegisterRouter.scala:87:24] wire out_woready_1_182; // @[RegisterRouter.scala:87:24] wire out_woready_1_183; // @[RegisterRouter.scala:87:24] wire out_woready_1_184; // @[RegisterRouter.scala:87:24] wire out_woready_1_185; // @[RegisterRouter.scala:87:24] wire out_woready_1_186; // @[RegisterRouter.scala:87:24] wire out_woready_1_187; // @[RegisterRouter.scala:87:24] wire out_woready_1_188; // @[RegisterRouter.scala:87:24] wire out_woready_1_189; // @[RegisterRouter.scala:87:24] wire out_woready_1_190; // @[RegisterRouter.scala:87:24] wire out_woready_1_191; // @[RegisterRouter.scala:87:24] wire out_woready_1_192; // @[RegisterRouter.scala:87:24] wire out_woready_1_193; // @[RegisterRouter.scala:87:24] wire out_woready_1_194; // @[RegisterRouter.scala:87:24] wire out_woready_1_195; // @[RegisterRouter.scala:87:24] wire out_woready_1_196; // @[RegisterRouter.scala:87:24] wire out_woready_1_197; // @[RegisterRouter.scala:87:24] wire out_woready_1_198; // @[RegisterRouter.scala:87:24] wire out_woready_1_199; // @[RegisterRouter.scala:87:24] wire out_woready_1_200; // @[RegisterRouter.scala:87:24] wire out_woready_1_201; // @[RegisterRouter.scala:87:24] wire out_woready_1_202; // @[RegisterRouter.scala:87:24] wire out_woready_1_203; // @[RegisterRouter.scala:87:24] wire out_woready_1_204; // @[RegisterRouter.scala:87:24] wire out_woready_1_205; // @[RegisterRouter.scala:87:24] wire out_woready_1_206; // @[RegisterRouter.scala:87:24] wire out_woready_1_207; // @[RegisterRouter.scala:87:24] wire out_woready_1_208; // @[RegisterRouter.scala:87:24] wire out_woready_1_209; // @[RegisterRouter.scala:87:24] wire out_woready_1_210; // @[RegisterRouter.scala:87:24] wire out_woready_1_211; // @[RegisterRouter.scala:87:24] wire out_woready_1_212; // @[RegisterRouter.scala:87:24] wire out_woready_1_213; // @[RegisterRouter.scala:87:24] wire out_woready_1_214; // @[RegisterRouter.scala:87:24] wire out_woready_1_215; // @[RegisterRouter.scala:87:24] wire out_woready_1_216; // @[RegisterRouter.scala:87:24] wire out_woready_1_217; // @[RegisterRouter.scala:87:24] wire out_woready_1_218; // @[RegisterRouter.scala:87:24] wire out_woready_1_219; // @[RegisterRouter.scala:87:24] wire out_woready_1_220; // @[RegisterRouter.scala:87:24] wire out_woready_1_221; // @[RegisterRouter.scala:87:24] wire out_woready_1_222; // @[RegisterRouter.scala:87:24] wire out_woready_1_223; // @[RegisterRouter.scala:87:24] wire out_woready_1_224; // @[RegisterRouter.scala:87:24] wire out_woready_1_225; // @[RegisterRouter.scala:87:24] wire out_woready_1_226; // @[RegisterRouter.scala:87:24] wire out_woready_1_227; // @[RegisterRouter.scala:87:24] wire out_woready_1_228; // @[RegisterRouter.scala:87:24] wire out_woready_1_229; // @[RegisterRouter.scala:87:24] wire out_woready_1_230; // @[RegisterRouter.scala:87:24] wire out_woready_1_231; // @[RegisterRouter.scala:87:24] wire out_woready_1_232; // @[RegisterRouter.scala:87:24] wire out_woready_1_233; // @[RegisterRouter.scala:87:24] wire out_woready_1_234; // @[RegisterRouter.scala:87:24] wire out_woready_1_235; // @[RegisterRouter.scala:87:24] wire out_woready_1_236; // @[RegisterRouter.scala:87:24] wire out_woready_1_237; // @[RegisterRouter.scala:87:24] wire out_woready_1_238; // @[RegisterRouter.scala:87:24] wire out_woready_1_239; // @[RegisterRouter.scala:87:24] wire out_woready_1_240; // @[RegisterRouter.scala:87:24] wire out_woready_1_241; // @[RegisterRouter.scala:87:24] wire out_woready_1_242; // @[RegisterRouter.scala:87:24] wire out_woready_1_243; // @[RegisterRouter.scala:87:24] wire out_woready_1_244; // @[RegisterRouter.scala:87:24] wire out_woready_1_245; // @[RegisterRouter.scala:87:24] wire out_woready_1_246; // @[RegisterRouter.scala:87:24] wire out_woready_1_247; // @[RegisterRouter.scala:87:24] wire out_woready_1_248; // @[RegisterRouter.scala:87:24] wire out_woready_1_249; // @[RegisterRouter.scala:87:24] wire out_woready_1_250; // @[RegisterRouter.scala:87:24] wire out_woready_1_251; // @[RegisterRouter.scala:87:24] wire out_woready_1_252; // @[RegisterRouter.scala:87:24] wire out_woready_1_253; // @[RegisterRouter.scala:87:24] wire out_woready_1_254; // @[RegisterRouter.scala:87:24] wire out_woready_1_255; // @[RegisterRouter.scala:87:24] wire out_woready_1_256; // @[RegisterRouter.scala:87:24] wire out_woready_1_257; // @[RegisterRouter.scala:87:24] wire out_woready_1_258; // @[RegisterRouter.scala:87:24] wire out_woready_1_259; // @[RegisterRouter.scala:87:24] wire out_woready_1_260; // @[RegisterRouter.scala:87:24] wire out_woready_1_261; // @[RegisterRouter.scala:87:24] wire out_woready_1_262; // @[RegisterRouter.scala:87:24] wire out_woready_1_263; // @[RegisterRouter.scala:87:24] wire out_woready_1_264; // @[RegisterRouter.scala:87:24] wire out_woready_1_265; // @[RegisterRouter.scala:87:24] wire out_woready_1_266; // @[RegisterRouter.scala:87:24] wire out_woready_1_267; // @[RegisterRouter.scala:87:24] wire out_woready_1_268; // @[RegisterRouter.scala:87:24] wire out_woready_1_269; // @[RegisterRouter.scala:87:24] wire out_woready_1_270; // @[RegisterRouter.scala:87:24] wire out_woready_1_271; // @[RegisterRouter.scala:87:24] wire out_woready_1_272; // @[RegisterRouter.scala:87:24] wire out_woready_1_273; // @[RegisterRouter.scala:87:24] wire out_woready_1_274; // @[RegisterRouter.scala:87:24] wire out_woready_1_275; // @[RegisterRouter.scala:87:24] wire out_woready_1_276; // @[RegisterRouter.scala:87:24] wire out_woready_1_277; // @[RegisterRouter.scala:87:24] wire out_woready_1_278; // @[RegisterRouter.scala:87:24] wire out_woready_1_279; // @[RegisterRouter.scala:87:24] wire out_woready_1_280; // @[RegisterRouter.scala:87:24] wire out_woready_1_281; // @[RegisterRouter.scala:87:24] wire out_woready_1_282; // @[RegisterRouter.scala:87:24] wire out_woready_1_283; // @[RegisterRouter.scala:87:24] wire out_woready_1_284; // @[RegisterRouter.scala:87:24] wire out_woready_1_285; // @[RegisterRouter.scala:87:24] wire out_woready_1_286; // @[RegisterRouter.scala:87:24] wire out_woready_1_287; // @[RegisterRouter.scala:87:24] wire out_woready_1_288; // @[RegisterRouter.scala:87:24] wire out_woready_1_289; // @[RegisterRouter.scala:87:24] wire out_woready_1_290; // @[RegisterRouter.scala:87:24] wire out_woready_1_291; // @[RegisterRouter.scala:87:24] wire out_woready_1_292; // @[RegisterRouter.scala:87:24] wire out_woready_1_293; // @[RegisterRouter.scala:87:24] wire out_woready_1_294; // @[RegisterRouter.scala:87:24] wire out_woready_1_295; // @[RegisterRouter.scala:87:24] wire out_woready_1_296; // @[RegisterRouter.scala:87:24] wire out_woready_1_297; // @[RegisterRouter.scala:87:24] wire out_woready_1_298; // @[RegisterRouter.scala:87:24] wire out_woready_1_299; // @[RegisterRouter.scala:87:24] wire out_woready_1_300; // @[RegisterRouter.scala:87:24] wire out_woready_1_301; // @[RegisterRouter.scala:87:24] wire out_woready_1_302; // @[RegisterRouter.scala:87:24] wire out_woready_1_303; // @[RegisterRouter.scala:87:24] wire out_woready_1_304; // @[RegisterRouter.scala:87:24] wire out_woready_1_305; // @[RegisterRouter.scala:87:24] wire out_woready_1_306; // @[RegisterRouter.scala:87:24] wire out_woready_1_307; // @[RegisterRouter.scala:87:24] wire out_woready_1_308; // @[RegisterRouter.scala:87:24] wire out_woready_1_309; // @[RegisterRouter.scala:87:24] wire out_woready_1_310; // @[RegisterRouter.scala:87:24] wire out_woready_1_311; // @[RegisterRouter.scala:87:24] wire out_woready_1_312; // @[RegisterRouter.scala:87:24] wire out_woready_1_313; // @[RegisterRouter.scala:87:24] wire out_woready_1_314; // @[RegisterRouter.scala:87:24] wire out_woready_1_315; // @[RegisterRouter.scala:87:24] wire out_woready_1_316; // @[RegisterRouter.scala:87:24] wire out_woready_1_317; // @[RegisterRouter.scala:87:24] wire out_woready_1_318; // @[RegisterRouter.scala:87:24] wire out_woready_1_319; // @[RegisterRouter.scala:87:24] wire out_woready_1_320; // @[RegisterRouter.scala:87:24] wire out_woready_1_321; // @[RegisterRouter.scala:87:24] wire out_woready_1_322; // @[RegisterRouter.scala:87:24] wire out_woready_1_323; // @[RegisterRouter.scala:87:24] wire out_woready_1_324; // @[RegisterRouter.scala:87:24] wire out_woready_1_325; // @[RegisterRouter.scala:87:24] wire out_woready_1_326; // @[RegisterRouter.scala:87:24] wire out_woready_1_327; // @[RegisterRouter.scala:87:24] wire out_woready_1_328; // @[RegisterRouter.scala:87:24] wire out_woready_1_329; // @[RegisterRouter.scala:87:24] wire out_woready_1_330; // @[RegisterRouter.scala:87:24] wire out_woready_1_331; // @[RegisterRouter.scala:87:24] wire out_woready_1_332; // @[RegisterRouter.scala:87:24] wire out_woready_1_333; // @[RegisterRouter.scala:87:24] wire out_woready_1_334; // @[RegisterRouter.scala:87:24] wire out_woready_1_335; // @[RegisterRouter.scala:87:24] wire out_woready_1_336; // @[RegisterRouter.scala:87:24] wire out_woready_1_337; // @[RegisterRouter.scala:87:24] wire out_woready_1_338; // @[RegisterRouter.scala:87:24] wire out_woready_1_339; // @[RegisterRouter.scala:87:24] wire out_woready_1_340; // @[RegisterRouter.scala:87:24] wire out_woready_1_341; // @[RegisterRouter.scala:87:24] wire out_woready_1_342; // @[RegisterRouter.scala:87:24] wire out_woready_1_343; // @[RegisterRouter.scala:87:24] wire out_woready_1_344; // @[RegisterRouter.scala:87:24] wire out_woready_1_345; // @[RegisterRouter.scala:87:24] wire out_woready_1_346; // @[RegisterRouter.scala:87:24] wire out_woready_1_347; // @[RegisterRouter.scala:87:24] wire out_woready_1_348; // @[RegisterRouter.scala:87:24] wire out_woready_1_349; // @[RegisterRouter.scala:87:24] wire out_woready_1_350; // @[RegisterRouter.scala:87:24] wire out_woready_1_351; // @[RegisterRouter.scala:87:24] wire out_woready_1_352; // @[RegisterRouter.scala:87:24] wire out_woready_1_353; // @[RegisterRouter.scala:87:24] wire out_woready_1_354; // @[RegisterRouter.scala:87:24] wire out_woready_1_355; // @[RegisterRouter.scala:87:24] wire out_woready_1_356; // @[RegisterRouter.scala:87:24] wire out_woready_1_357; // @[RegisterRouter.scala:87:24] wire out_woready_1_358; // @[RegisterRouter.scala:87:24] wire out_woready_1_359; // @[RegisterRouter.scala:87:24] wire out_woready_1_360; // @[RegisterRouter.scala:87:24] wire out_woready_1_361; // @[RegisterRouter.scala:87:24] wire out_woready_1_362; // @[RegisterRouter.scala:87:24] wire out_woready_1_363; // @[RegisterRouter.scala:87:24] wire out_woready_1_364; // @[RegisterRouter.scala:87:24] wire out_woready_1_365; // @[RegisterRouter.scala:87:24] wire out_woready_1_366; // @[RegisterRouter.scala:87:24] wire out_woready_1_367; // @[RegisterRouter.scala:87:24] wire out_woready_1_368; // @[RegisterRouter.scala:87:24] wire out_woready_1_369; // @[RegisterRouter.scala:87:24] wire out_woready_1_370; // @[RegisterRouter.scala:87:24] wire out_woready_1_371; // @[RegisterRouter.scala:87:24] wire out_woready_1_372; // @[RegisterRouter.scala:87:24] wire out_woready_1_373; // @[RegisterRouter.scala:87:24] wire out_woready_1_374; // @[RegisterRouter.scala:87:24] wire out_woready_1_375; // @[RegisterRouter.scala:87:24] wire out_woready_1_376; // @[RegisterRouter.scala:87:24] wire out_woready_1_377; // @[RegisterRouter.scala:87:24] wire out_woready_1_378; // @[RegisterRouter.scala:87:24] wire out_woready_1_379; // @[RegisterRouter.scala:87:24] wire out_woready_1_380; // @[RegisterRouter.scala:87:24] wire out_woready_1_381; // @[RegisterRouter.scala:87:24] wire out_woready_1_382; // @[RegisterRouter.scala:87:24] wire out_woready_1_383; // @[RegisterRouter.scala:87:24] wire out_woready_1_384; // @[RegisterRouter.scala:87:24] wire out_woready_1_385; // @[RegisterRouter.scala:87:24] wire out_woready_1_386; // @[RegisterRouter.scala:87:24] wire out_woready_1_387; // @[RegisterRouter.scala:87:24] wire out_woready_1_388; // @[RegisterRouter.scala:87:24] wire out_woready_1_389; // @[RegisterRouter.scala:87:24] wire out_woready_1_390; // @[RegisterRouter.scala:87:24] wire out_woready_1_391; // @[RegisterRouter.scala:87:24] wire out_woready_1_392; // @[RegisterRouter.scala:87:24] wire out_woready_1_393; // @[RegisterRouter.scala:87:24] wire out_woready_1_394; // @[RegisterRouter.scala:87:24] wire out_woready_1_395; // @[RegisterRouter.scala:87:24] wire out_woready_1_396; // @[RegisterRouter.scala:87:24] wire out_woready_1_397; // @[RegisterRouter.scala:87:24] wire out_woready_1_398; // @[RegisterRouter.scala:87:24] wire out_woready_1_399; // @[RegisterRouter.scala:87:24] wire out_woready_1_400; // @[RegisterRouter.scala:87:24] wire out_woready_1_401; // @[RegisterRouter.scala:87:24] wire out_woready_1_402; // @[RegisterRouter.scala:87:24] wire out_woready_1_403; // @[RegisterRouter.scala:87:24] wire out_woready_1_404; // @[RegisterRouter.scala:87:24] wire out_woready_1_405; // @[RegisterRouter.scala:87:24] wire out_woready_1_406; // @[RegisterRouter.scala:87:24] wire out_woready_1_407; // @[RegisterRouter.scala:87:24] wire out_woready_1_408; // @[RegisterRouter.scala:87:24] wire out_woready_1_409; // @[RegisterRouter.scala:87:24] wire out_woready_1_410; // @[RegisterRouter.scala:87:24] wire out_woready_1_411; // @[RegisterRouter.scala:87:24] wire out_woready_1_412; // @[RegisterRouter.scala:87:24] wire out_woready_1_413; // @[RegisterRouter.scala:87:24] wire out_woready_1_414; // @[RegisterRouter.scala:87:24] wire out_woready_1_415; // @[RegisterRouter.scala:87:24] wire out_woready_1_416; // @[RegisterRouter.scala:87:24] wire out_woready_1_417; // @[RegisterRouter.scala:87:24] wire out_woready_1_418; // @[RegisterRouter.scala:87:24] wire out_woready_1_419; // @[RegisterRouter.scala:87:24] wire out_woready_1_420; // @[RegisterRouter.scala:87:24] wire out_woready_1_421; // @[RegisterRouter.scala:87:24] wire out_woready_1_422; // @[RegisterRouter.scala:87:24] wire out_woready_1_423; // @[RegisterRouter.scala:87:24] wire out_woready_1_424; // @[RegisterRouter.scala:87:24] wire out_woready_1_425; // @[RegisterRouter.scala:87:24] wire out_woready_1_426; // @[RegisterRouter.scala:87:24] wire out_woready_1_427; // @[RegisterRouter.scala:87:24] wire out_woready_1_428; // @[RegisterRouter.scala:87:24] wire out_woready_1_429; // @[RegisterRouter.scala:87:24] wire out_woready_1_430; // @[RegisterRouter.scala:87:24] wire out_woready_1_431; // @[RegisterRouter.scala:87:24] wire out_woready_1_432; // @[RegisterRouter.scala:87:24] wire out_woready_1_433; // @[RegisterRouter.scala:87:24] wire out_woready_1_434; // @[RegisterRouter.scala:87:24] wire out_woready_1_435; // @[RegisterRouter.scala:87:24] wire out_woready_1_436; // @[RegisterRouter.scala:87:24] wire out_woready_1_437; // @[RegisterRouter.scala:87:24] wire out_woready_1_438; // @[RegisterRouter.scala:87:24] wire out_woready_1_439; // @[RegisterRouter.scala:87:24] wire out_woready_1_440; // @[RegisterRouter.scala:87:24] wire out_woready_1_441; // @[RegisterRouter.scala:87:24] wire out_woready_1_442; // @[RegisterRouter.scala:87:24] wire out_woready_1_443; // @[RegisterRouter.scala:87:24] wire out_woready_1_444; // @[RegisterRouter.scala:87:24] wire out_woready_1_445; // @[RegisterRouter.scala:87:24] wire out_woready_1_446; // @[RegisterRouter.scala:87:24] wire out_woready_1_447; // @[RegisterRouter.scala:87:24] wire out_woready_1_448; // @[RegisterRouter.scala:87:24] wire out_woready_1_449; // @[RegisterRouter.scala:87:24] wire out_woready_1_450; // @[RegisterRouter.scala:87:24] wire out_woready_1_451; // @[RegisterRouter.scala:87:24] wire out_woready_1_452; // @[RegisterRouter.scala:87:24] wire out_woready_1_453; // @[RegisterRouter.scala:87:24] wire out_woready_1_454; // @[RegisterRouter.scala:87:24] wire out_woready_1_455; // @[RegisterRouter.scala:87:24] wire out_woready_1_456; // @[RegisterRouter.scala:87:24] wire out_woready_1_457; // @[RegisterRouter.scala:87:24] wire out_woready_1_458; // @[RegisterRouter.scala:87:24] wire out_woready_1_459; // @[RegisterRouter.scala:87:24] wire out_woready_1_460; // @[RegisterRouter.scala:87:24] wire out_woready_1_461; // @[RegisterRouter.scala:87:24] wire out_woready_1_462; // @[RegisterRouter.scala:87:24] wire out_woready_1_463; // @[RegisterRouter.scala:87:24] wire out_woready_1_464; // @[RegisterRouter.scala:87:24] wire out_woready_1_465; // @[RegisterRouter.scala:87:24] wire out_woready_1_466; // @[RegisterRouter.scala:87:24] wire out_woready_1_467; // @[RegisterRouter.scala:87:24] wire out_woready_1_468; // @[RegisterRouter.scala:87:24] wire out_woready_1_469; // @[RegisterRouter.scala:87:24] wire out_woready_1_470; // @[RegisterRouter.scala:87:24] wire out_woready_1_471; // @[RegisterRouter.scala:87:24] wire out_woready_1_472; // @[RegisterRouter.scala:87:24] wire out_woready_1_473; // @[RegisterRouter.scala:87:24] wire out_woready_1_474; // @[RegisterRouter.scala:87:24] wire out_woready_1_475; // @[RegisterRouter.scala:87:24] wire out_woready_1_476; // @[RegisterRouter.scala:87:24] wire out_woready_1_477; // @[RegisterRouter.scala:87:24] wire out_woready_1_478; // @[RegisterRouter.scala:87:24] wire out_woready_1_479; // @[RegisterRouter.scala:87:24] wire out_woready_1_480; // @[RegisterRouter.scala:87:24] wire out_woready_1_481; // @[RegisterRouter.scala:87:24] wire out_woready_1_482; // @[RegisterRouter.scala:87:24] wire out_woready_1_483; // @[RegisterRouter.scala:87:24] wire out_woready_1_484; // @[RegisterRouter.scala:87:24] wire out_woready_1_485; // @[RegisterRouter.scala:87:24] wire out_woready_1_486; // @[RegisterRouter.scala:87:24] wire out_woready_1_487; // @[RegisterRouter.scala:87:24] wire out_woready_1_488; // @[RegisterRouter.scala:87:24] wire out_woready_1_489; // @[RegisterRouter.scala:87:24] wire out_woready_1_490; // @[RegisterRouter.scala:87:24] wire out_woready_1_491; // @[RegisterRouter.scala:87:24] wire out_woready_1_492; // @[RegisterRouter.scala:87:24] wire out_woready_1_493; // @[RegisterRouter.scala:87:24] wire out_woready_1_494; // @[RegisterRouter.scala:87:24] wire out_woready_1_495; // @[RegisterRouter.scala:87:24] wire out_woready_1_496; // @[RegisterRouter.scala:87:24] wire out_woready_1_497; // @[RegisterRouter.scala:87:24] wire out_woready_1_498; // @[RegisterRouter.scala:87:24] wire out_woready_1_499; // @[RegisterRouter.scala:87:24] wire out_woready_1_500; // @[RegisterRouter.scala:87:24] wire out_woready_1_501; // @[RegisterRouter.scala:87:24] wire out_woready_1_502; // @[RegisterRouter.scala:87:24] wire out_woready_1_503; // @[RegisterRouter.scala:87:24] wire out_woready_1_504; // @[RegisterRouter.scala:87:24] wire out_woready_1_505; // @[RegisterRouter.scala:87:24] wire out_woready_1_506; // @[RegisterRouter.scala:87:24] wire out_woready_1_507; // @[RegisterRouter.scala:87:24] wire out_woready_1_508; // @[RegisterRouter.scala:87:24] wire out_woready_1_509; // @[RegisterRouter.scala:87:24] wire out_woready_1_510; // @[RegisterRouter.scala:87:24] wire out_woready_1_511; // @[RegisterRouter.scala:87:24] wire out_woready_1_512; // @[RegisterRouter.scala:87:24] wire out_woready_1_513; // @[RegisterRouter.scala:87:24] wire out_woready_1_514; // @[RegisterRouter.scala:87:24] wire out_woready_1_515; // @[RegisterRouter.scala:87:24] wire out_woready_1_516; // @[RegisterRouter.scala:87:24] wire out_woready_1_517; // @[RegisterRouter.scala:87:24] wire out_woready_1_518; // @[RegisterRouter.scala:87:24] wire out_woready_1_519; // @[RegisterRouter.scala:87:24] wire out_woready_1_520; // @[RegisterRouter.scala:87:24] wire out_woready_1_521; // @[RegisterRouter.scala:87:24] wire out_woready_1_522; // @[RegisterRouter.scala:87:24] wire out_woready_1_523; // @[RegisterRouter.scala:87:24] wire out_woready_1_524; // @[RegisterRouter.scala:87:24] wire out_woready_1_525; // @[RegisterRouter.scala:87:24] wire out_woready_1_526; // @[RegisterRouter.scala:87:24] wire out_woready_1_527; // @[RegisterRouter.scala:87:24] wire out_woready_1_528; // @[RegisterRouter.scala:87:24] wire out_woready_1_529; // @[RegisterRouter.scala:87:24] wire out_woready_1_530; // @[RegisterRouter.scala:87:24] wire out_woready_1_531; // @[RegisterRouter.scala:87:24] wire out_woready_1_532; // @[RegisterRouter.scala:87:24] wire out_woready_1_533; // @[RegisterRouter.scala:87:24] wire out_woready_1_534; // @[RegisterRouter.scala:87:24] wire out_woready_1_535; // @[RegisterRouter.scala:87:24] wire out_woready_1_536; // @[RegisterRouter.scala:87:24] wire out_woready_1_537; // @[RegisterRouter.scala:87:24] wire out_woready_1_538; // @[RegisterRouter.scala:87:24] wire out_woready_1_539; // @[RegisterRouter.scala:87:24] wire out_woready_1_540; // @[RegisterRouter.scala:87:24] wire out_woready_1_541; // @[RegisterRouter.scala:87:24] wire out_woready_1_542; // @[RegisterRouter.scala:87:24] wire out_woready_1_543; // @[RegisterRouter.scala:87:24] wire out_woready_1_544; // @[RegisterRouter.scala:87:24] wire out_woready_1_545; // @[RegisterRouter.scala:87:24] wire out_woready_1_546; // @[RegisterRouter.scala:87:24] wire out_woready_1_547; // @[RegisterRouter.scala:87:24] wire out_woready_1_548; // @[RegisterRouter.scala:87:24] wire out_woready_1_549; // @[RegisterRouter.scala:87:24] wire out_woready_1_550; // @[RegisterRouter.scala:87:24] wire out_woready_1_551; // @[RegisterRouter.scala:87:24] wire out_woready_1_552; // @[RegisterRouter.scala:87:24] wire out_woready_1_553; // @[RegisterRouter.scala:87:24] wire out_woready_1_554; // @[RegisterRouter.scala:87:24] wire out_woready_1_555; // @[RegisterRouter.scala:87:24] wire out_woready_1_556; // @[RegisterRouter.scala:87:24] wire out_woready_1_557; // @[RegisterRouter.scala:87:24] wire out_woready_1_558; // @[RegisterRouter.scala:87:24] wire out_woready_1_559; // @[RegisterRouter.scala:87:24] wire out_woready_1_560; // @[RegisterRouter.scala:87:24] wire out_woready_1_561; // @[RegisterRouter.scala:87:24] wire out_woready_1_562; // @[RegisterRouter.scala:87:24] wire out_woready_1_563; // @[RegisterRouter.scala:87:24] wire out_woready_1_564; // @[RegisterRouter.scala:87:24] wire out_woready_1_565; // @[RegisterRouter.scala:87:24] wire out_woready_1_566; // @[RegisterRouter.scala:87:24] wire out_woready_1_567; // @[RegisterRouter.scala:87:24] wire out_woready_1_568; // @[RegisterRouter.scala:87:24] wire out_woready_1_569; // @[RegisterRouter.scala:87:24] wire out_woready_1_570; // @[RegisterRouter.scala:87:24] wire out_woready_1_571; // @[RegisterRouter.scala:87:24] wire out_woready_1_572; // @[RegisterRouter.scala:87:24] wire out_woready_1_573; // @[RegisterRouter.scala:87:24] wire out_woready_1_574; // @[RegisterRouter.scala:87:24] wire out_woready_1_575; // @[RegisterRouter.scala:87:24] wire out_woready_1_576; // @[RegisterRouter.scala:87:24] wire out_woready_1_577; // @[RegisterRouter.scala:87:24] wire out_woready_1_578; // @[RegisterRouter.scala:87:24] wire out_woready_1_579; // @[RegisterRouter.scala:87:24] wire out_woready_1_580; // @[RegisterRouter.scala:87:24] wire out_woready_1_581; // @[RegisterRouter.scala:87:24] wire out_woready_1_582; // @[RegisterRouter.scala:87:24] wire out_woready_1_583; // @[RegisterRouter.scala:87:24] wire out_woready_1_584; // @[RegisterRouter.scala:87:24] wire out_woready_1_585; // @[RegisterRouter.scala:87:24] wire out_woready_1_586; // @[RegisterRouter.scala:87:24] wire out_woready_1_587; // @[RegisterRouter.scala:87:24] wire out_woready_1_588; // @[RegisterRouter.scala:87:24] wire out_woready_1_589; // @[RegisterRouter.scala:87:24] wire out_woready_1_590; // @[RegisterRouter.scala:87:24] wire out_woready_1_591; // @[RegisterRouter.scala:87:24] wire out_woready_1_592; // @[RegisterRouter.scala:87:24] wire out_woready_1_593; // @[RegisterRouter.scala:87:24] wire out_woready_1_594; // @[RegisterRouter.scala:87:24] wire out_woready_1_595; // @[RegisterRouter.scala:87:24] wire out_woready_1_596; // @[RegisterRouter.scala:87:24] wire out_woready_1_597; // @[RegisterRouter.scala:87:24] wire out_woready_1_598; // @[RegisterRouter.scala:87:24] wire out_woready_1_599; // @[RegisterRouter.scala:87:24] wire out_woready_1_600; // @[RegisterRouter.scala:87:24] wire out_woready_1_601; // @[RegisterRouter.scala:87:24] wire out_woready_1_602; // @[RegisterRouter.scala:87:24] wire out_woready_1_603; // @[RegisterRouter.scala:87:24] wire out_woready_1_604; // @[RegisterRouter.scala:87:24] wire out_woready_1_605; // @[RegisterRouter.scala:87:24] wire out_woready_1_606; // @[RegisterRouter.scala:87:24] wire out_woready_1_607; // @[RegisterRouter.scala:87:24] wire out_woready_1_608; // @[RegisterRouter.scala:87:24] wire out_woready_1_609; // @[RegisterRouter.scala:87:24] wire out_woready_1_610; // @[RegisterRouter.scala:87:24] wire out_woready_1_611; // @[RegisterRouter.scala:87:24] wire out_woready_1_612; // @[RegisterRouter.scala:87:24] wire out_woready_1_613; // @[RegisterRouter.scala:87:24] wire out_woready_1_614; // @[RegisterRouter.scala:87:24] wire out_woready_1_615; // @[RegisterRouter.scala:87:24] wire out_woready_1_616; // @[RegisterRouter.scala:87:24] wire out_woready_1_617; // @[RegisterRouter.scala:87:24] wire out_woready_1_618; // @[RegisterRouter.scala:87:24] wire out_woready_1_619; // @[RegisterRouter.scala:87:24] wire out_woready_1_620; // @[RegisterRouter.scala:87:24] wire out_woready_1_621; // @[RegisterRouter.scala:87:24] wire out_woready_1_622; // @[RegisterRouter.scala:87:24] wire out_woready_1_623; // @[RegisterRouter.scala:87:24] wire out_woready_1_624; // @[RegisterRouter.scala:87:24] wire out_woready_1_625; // @[RegisterRouter.scala:87:24] wire out_woready_1_626; // @[RegisterRouter.scala:87:24] wire out_woready_1_627; // @[RegisterRouter.scala:87:24] wire out_woready_1_628; // @[RegisterRouter.scala:87:24] wire out_woready_1_629; // @[RegisterRouter.scala:87:24] wire out_woready_1_630; // @[RegisterRouter.scala:87:24] wire out_woready_1_631; // @[RegisterRouter.scala:87:24] wire out_woready_1_632; // @[RegisterRouter.scala:87:24] wire out_woready_1_633; // @[RegisterRouter.scala:87:24] wire out_woready_1_634; // @[RegisterRouter.scala:87:24] wire out_woready_1_635; // @[RegisterRouter.scala:87:24] wire out_woready_1_636; // @[RegisterRouter.scala:87:24] wire out_woready_1_637; // @[RegisterRouter.scala:87:24] wire out_woready_1_638; // @[RegisterRouter.scala:87:24] wire out_woready_1_639; // @[RegisterRouter.scala:87:24] wire out_woready_1_640; // @[RegisterRouter.scala:87:24] wire out_woready_1_641; // @[RegisterRouter.scala:87:24] wire out_woready_1_642; // @[RegisterRouter.scala:87:24] wire out_woready_1_643; // @[RegisterRouter.scala:87:24] wire out_woready_1_644; // @[RegisterRouter.scala:87:24] wire out_woready_1_645; // @[RegisterRouter.scala:87:24] wire out_woready_1_646; // @[RegisterRouter.scala:87:24] wire out_woready_1_647; // @[RegisterRouter.scala:87:24] wire out_woready_1_648; // @[RegisterRouter.scala:87:24] wire out_woready_1_649; // @[RegisterRouter.scala:87:24] wire out_woready_1_650; // @[RegisterRouter.scala:87:24] wire out_woready_1_651; // @[RegisterRouter.scala:87:24] wire out_woready_1_652; // @[RegisterRouter.scala:87:24] wire out_woready_1_653; // @[RegisterRouter.scala:87:24] wire out_woready_1_654; // @[RegisterRouter.scala:87:24] wire out_woready_1_655; // @[RegisterRouter.scala:87:24] wire out_woready_1_656; // @[RegisterRouter.scala:87:24] wire out_woready_1_657; // @[RegisterRouter.scala:87:24] wire out_woready_1_658; // @[RegisterRouter.scala:87:24] wire out_woready_1_659; // @[RegisterRouter.scala:87:24] wire out_woready_1_660; // @[RegisterRouter.scala:87:24] wire out_woready_1_661; // @[RegisterRouter.scala:87:24] wire out_woready_1_662; // @[RegisterRouter.scala:87:24] wire out_woready_1_663; // @[RegisterRouter.scala:87:24] wire out_woready_1_664; // @[RegisterRouter.scala:87:24] wire out_woready_1_665; // @[RegisterRouter.scala:87:24] wire out_woready_1_666; // @[RegisterRouter.scala:87:24] wire out_woready_1_667; // @[RegisterRouter.scala:87:24] wire out_woready_1_668; // @[RegisterRouter.scala:87:24] wire out_woready_1_669; // @[RegisterRouter.scala:87:24] wire out_woready_1_670; // @[RegisterRouter.scala:87:24] wire out_woready_1_671; // @[RegisterRouter.scala:87:24] wire out_woready_1_672; // @[RegisterRouter.scala:87:24] wire out_woready_1_673; // @[RegisterRouter.scala:87:24] wire out_woready_1_674; // @[RegisterRouter.scala:87:24] wire out_woready_1_675; // @[RegisterRouter.scala:87:24] wire out_woready_1_676; // @[RegisterRouter.scala:87:24] wire out_woready_1_677; // @[RegisterRouter.scala:87:24] wire out_woready_1_678; // @[RegisterRouter.scala:87:24] wire out_woready_1_679; // @[RegisterRouter.scala:87:24] wire out_woready_1_680; // @[RegisterRouter.scala:87:24] wire out_woready_1_681; // @[RegisterRouter.scala:87:24] wire out_woready_1_682; // @[RegisterRouter.scala:87:24] wire out_woready_1_683; // @[RegisterRouter.scala:87:24] wire out_woready_1_684; // @[RegisterRouter.scala:87:24] wire out_woready_1_685; // @[RegisterRouter.scala:87:24] wire out_woready_1_686; // @[RegisterRouter.scala:87:24] wire out_woready_1_687; // @[RegisterRouter.scala:87:24] wire out_woready_1_688; // @[RegisterRouter.scala:87:24] wire out_woready_1_689; // @[RegisterRouter.scala:87:24] wire out_woready_1_690; // @[RegisterRouter.scala:87:24] wire out_woready_1_691; // @[RegisterRouter.scala:87:24] wire out_woready_1_692; // @[RegisterRouter.scala:87:24] wire out_woready_1_693; // @[RegisterRouter.scala:87:24] wire out_woready_1_694; // @[RegisterRouter.scala:87:24] wire out_woready_1_695; // @[RegisterRouter.scala:87:24] wire out_woready_1_696; // @[RegisterRouter.scala:87:24] wire out_woready_1_697; // @[RegisterRouter.scala:87:24] wire out_woready_1_698; // @[RegisterRouter.scala:87:24] wire out_woready_1_699; // @[RegisterRouter.scala:87:24] wire out_woready_1_700; // @[RegisterRouter.scala:87:24] wire out_woready_1_701; // @[RegisterRouter.scala:87:24] wire out_woready_1_702; // @[RegisterRouter.scala:87:24] wire out_woready_1_703; // @[RegisterRouter.scala:87:24] wire out_woready_1_704; // @[RegisterRouter.scala:87:24] wire out_woready_1_705; // @[RegisterRouter.scala:87:24] wire out_woready_1_706; // @[RegisterRouter.scala:87:24] wire out_woready_1_707; // @[RegisterRouter.scala:87:24] wire out_woready_1_708; // @[RegisterRouter.scala:87:24] wire out_woready_1_709; // @[RegisterRouter.scala:87:24] wire out_woready_1_710; // @[RegisterRouter.scala:87:24] wire out_woready_1_711; // @[RegisterRouter.scala:87:24] wire out_woready_1_712; // @[RegisterRouter.scala:87:24] wire out_woready_1_713; // @[RegisterRouter.scala:87:24] wire out_woready_1_714; // @[RegisterRouter.scala:87:24] wire out_woready_1_715; // @[RegisterRouter.scala:87:24] wire out_woready_1_716; // @[RegisterRouter.scala:87:24] wire out_woready_1_717; // @[RegisterRouter.scala:87:24] wire out_woready_1_718; // @[RegisterRouter.scala:87:24] wire out_woready_1_719; // @[RegisterRouter.scala:87:24] wire out_woready_1_720; // @[RegisterRouter.scala:87:24] wire out_woready_1_721; // @[RegisterRouter.scala:87:24] wire out_woready_1_722; // @[RegisterRouter.scala:87:24] wire out_woready_1_723; // @[RegisterRouter.scala:87:24] wire out_woready_1_724; // @[RegisterRouter.scala:87:24] wire out_woready_1_725; // @[RegisterRouter.scala:87:24] wire out_woready_1_726; // @[RegisterRouter.scala:87:24] wire out_woready_1_727; // @[RegisterRouter.scala:87:24] wire out_woready_1_728; // @[RegisterRouter.scala:87:24] wire out_woready_1_729; // @[RegisterRouter.scala:87:24] wire out_woready_1_730; // @[RegisterRouter.scala:87:24] wire out_woready_1_731; // @[RegisterRouter.scala:87:24] wire out_woready_1_732; // @[RegisterRouter.scala:87:24] wire out_woready_1_733; // @[RegisterRouter.scala:87:24] wire out_woready_1_734; // @[RegisterRouter.scala:87:24] wire out_woready_1_735; // @[RegisterRouter.scala:87:24] wire out_woready_1_736; // @[RegisterRouter.scala:87:24] wire out_woready_1_737; // @[RegisterRouter.scala:87:24] wire out_woready_1_738; // @[RegisterRouter.scala:87:24] wire out_woready_1_739; // @[RegisterRouter.scala:87:24] wire out_woready_1_740; // @[RegisterRouter.scala:87:24] wire out_woready_1_741; // @[RegisterRouter.scala:87:24] wire out_woready_1_742; // @[RegisterRouter.scala:87:24] wire out_woready_1_743; // @[RegisterRouter.scala:87:24] wire out_woready_1_744; // @[RegisterRouter.scala:87:24] wire out_woready_1_745; // @[RegisterRouter.scala:87:24] wire out_woready_1_746; // @[RegisterRouter.scala:87:24] wire out_woready_1_747; // @[RegisterRouter.scala:87:24] wire out_woready_1_748; // @[RegisterRouter.scala:87:24] wire out_woready_1_749; // @[RegisterRouter.scala:87:24] wire out_woready_1_750; // @[RegisterRouter.scala:87:24] wire out_woready_1_751; // @[RegisterRouter.scala:87:24] wire out_woready_1_752; // @[RegisterRouter.scala:87:24] wire out_woready_1_753; // @[RegisterRouter.scala:87:24] wire out_woready_1_754; // @[RegisterRouter.scala:87:24] wire out_woready_1_755; // @[RegisterRouter.scala:87:24] wire out_woready_1_756; // @[RegisterRouter.scala:87:24] wire out_woready_1_757; // @[RegisterRouter.scala:87:24] wire out_woready_1_758; // @[RegisterRouter.scala:87:24] wire out_woready_1_759; // @[RegisterRouter.scala:87:24] wire out_woready_1_760; // @[RegisterRouter.scala:87:24] wire out_woready_1_761; // @[RegisterRouter.scala:87:24] wire out_woready_1_762; // @[RegisterRouter.scala:87:24] wire out_woready_1_763; // @[RegisterRouter.scala:87:24] wire out_woready_1_764; // @[RegisterRouter.scala:87:24] wire out_woready_1_765; // @[RegisterRouter.scala:87:24] wire out_woready_1_766; // @[RegisterRouter.scala:87:24] wire out_woready_1_767; // @[RegisterRouter.scala:87:24] wire out_woready_1_768; // @[RegisterRouter.scala:87:24] wire out_woready_1_769; // @[RegisterRouter.scala:87:24] wire out_woready_1_770; // @[RegisterRouter.scala:87:24] wire out_woready_1_771; // @[RegisterRouter.scala:87:24] wire out_woready_1_772; // @[RegisterRouter.scala:87:24] wire out_woready_1_773; // @[RegisterRouter.scala:87:24] wire out_woready_1_774; // @[RegisterRouter.scala:87:24] wire out_woready_1_775; // @[RegisterRouter.scala:87:24] wire out_woready_1_776; // @[RegisterRouter.scala:87:24] wire out_woready_1_777; // @[RegisterRouter.scala:87:24] wire out_woready_1_778; // @[RegisterRouter.scala:87:24] wire out_woready_1_779; // @[RegisterRouter.scala:87:24] wire out_woready_1_780; // @[RegisterRouter.scala:87:24] wire out_woready_1_781; // @[RegisterRouter.scala:87:24] wire out_woready_1_782; // @[RegisterRouter.scala:87:24] wire out_woready_1_783; // @[RegisterRouter.scala:87:24] wire out_woready_1_784; // @[RegisterRouter.scala:87:24] wire out_woready_1_785; // @[RegisterRouter.scala:87:24] wire out_woready_1_786; // @[RegisterRouter.scala:87:24] wire out_woready_1_787; // @[RegisterRouter.scala:87:24] wire out_woready_1_788; // @[RegisterRouter.scala:87:24] wire out_woready_1_789; // @[RegisterRouter.scala:87:24] wire out_woready_1_790; // @[RegisterRouter.scala:87:24] wire out_woready_1_791; // @[RegisterRouter.scala:87:24] wire out_woready_1_792; // @[RegisterRouter.scala:87:24] wire out_woready_1_793; // @[RegisterRouter.scala:87:24] wire out_woready_1_794; // @[RegisterRouter.scala:87:24] wire out_woready_1_795; // @[RegisterRouter.scala:87:24] wire out_woready_1_796; // @[RegisterRouter.scala:87:24] wire out_woready_1_797; // @[RegisterRouter.scala:87:24] wire out_woready_1_798; // @[RegisterRouter.scala:87:24] wire out_woready_1_799; // @[RegisterRouter.scala:87:24] wire out_woready_1_800; // @[RegisterRouter.scala:87:24] wire out_woready_1_801; // @[RegisterRouter.scala:87:24] wire out_woready_1_802; // @[RegisterRouter.scala:87:24] wire out_woready_1_803; // @[RegisterRouter.scala:87:24] wire out_woready_1_804; // @[RegisterRouter.scala:87:24] wire out_woready_1_805; // @[RegisterRouter.scala:87:24] wire out_woready_1_806; // @[RegisterRouter.scala:87:24] wire out_woready_1_807; // @[RegisterRouter.scala:87:24] wire out_woready_1_808; // @[RegisterRouter.scala:87:24] wire out_woready_1_809; // @[RegisterRouter.scala:87:24] wire out_woready_1_810; // @[RegisterRouter.scala:87:24] wire out_woready_1_811; // @[RegisterRouter.scala:87:24] wire out_woready_1_812; // @[RegisterRouter.scala:87:24] wire out_woready_1_813; // @[RegisterRouter.scala:87:24] wire out_woready_1_814; // @[RegisterRouter.scala:87:24] wire out_woready_1_815; // @[RegisterRouter.scala:87:24] wire out_woready_1_816; // @[RegisterRouter.scala:87:24] wire out_woready_1_817; // @[RegisterRouter.scala:87:24] wire out_woready_1_818; // @[RegisterRouter.scala:87:24] wire out_woready_1_819; // @[RegisterRouter.scala:87:24] wire out_woready_1_820; // @[RegisterRouter.scala:87:24] wire out_woready_1_821; // @[RegisterRouter.scala:87:24] wire out_woready_1_822; // @[RegisterRouter.scala:87:24] wire out_woready_1_823; // @[RegisterRouter.scala:87:24] wire out_woready_1_824; // @[RegisterRouter.scala:87:24] wire out_woready_1_825; // @[RegisterRouter.scala:87:24] wire out_woready_1_826; // @[RegisterRouter.scala:87:24] wire out_woready_1_827; // @[RegisterRouter.scala:87:24] wire out_woready_1_828; // @[RegisterRouter.scala:87:24] wire out_woready_1_829; // @[RegisterRouter.scala:87:24] wire out_woready_1_830; // @[RegisterRouter.scala:87:24] wire out_woready_1_831; // @[RegisterRouter.scala:87:24] wire out_woready_1_832; // @[RegisterRouter.scala:87:24] wire out_woready_1_833; // @[RegisterRouter.scala:87:24] wire out_woready_1_834; // @[RegisterRouter.scala:87:24] wire out_woready_1_835; // @[RegisterRouter.scala:87:24] wire out_woready_1_836; // @[RegisterRouter.scala:87:24] wire out_woready_1_837; // @[RegisterRouter.scala:87:24] wire out_woready_1_838; // @[RegisterRouter.scala:87:24] wire out_woready_1_839; // @[RegisterRouter.scala:87:24] wire out_woready_1_840; // @[RegisterRouter.scala:87:24] wire out_woready_1_841; // @[RegisterRouter.scala:87:24] wire out_woready_1_842; // @[RegisterRouter.scala:87:24] wire out_woready_1_843; // @[RegisterRouter.scala:87:24] wire out_woready_1_844; // @[RegisterRouter.scala:87:24] wire out_woready_1_845; // @[RegisterRouter.scala:87:24] wire out_woready_1_846; // @[RegisterRouter.scala:87:24] wire out_woready_1_847; // @[RegisterRouter.scala:87:24] wire out_woready_1_848; // @[RegisterRouter.scala:87:24] wire out_woready_1_849; // @[RegisterRouter.scala:87:24] wire out_woready_1_850; // @[RegisterRouter.scala:87:24] wire out_woready_1_851; // @[RegisterRouter.scala:87:24] wire out_woready_1_852; // @[RegisterRouter.scala:87:24] wire out_woready_1_853; // @[RegisterRouter.scala:87:24] wire out_woready_1_854; // @[RegisterRouter.scala:87:24] wire out_woready_1_855; // @[RegisterRouter.scala:87:24] wire out_woready_1_856; // @[RegisterRouter.scala:87:24] wire out_woready_1_857; // @[RegisterRouter.scala:87:24] wire out_woready_1_858; // @[RegisterRouter.scala:87:24] wire out_woready_1_859; // @[RegisterRouter.scala:87:24] wire out_woready_1_860; // @[RegisterRouter.scala:87:24] wire out_woready_1_861; // @[RegisterRouter.scala:87:24] wire out_woready_1_862; // @[RegisterRouter.scala:87:24] wire out_woready_1_863; // @[RegisterRouter.scala:87:24] wire out_woready_1_864; // @[RegisterRouter.scala:87:24] wire out_woready_1_865; // @[RegisterRouter.scala:87:24] wire out_woready_1_866; // @[RegisterRouter.scala:87:24] wire out_woready_1_867; // @[RegisterRouter.scala:87:24] wire out_woready_1_868; // @[RegisterRouter.scala:87:24] wire out_woready_1_869; // @[RegisterRouter.scala:87:24] wire out_woready_1_870; // @[RegisterRouter.scala:87:24] wire out_woready_1_871; // @[RegisterRouter.scala:87:24] wire out_woready_1_872; // @[RegisterRouter.scala:87:24] wire out_woready_1_873; // @[RegisterRouter.scala:87:24] wire out_woready_1_874; // @[RegisterRouter.scala:87:24] wire out_woready_1_875; // @[RegisterRouter.scala:87:24] wire out_woready_1_876; // @[RegisterRouter.scala:87:24] wire out_woready_1_877; // @[RegisterRouter.scala:87:24] wire out_woready_1_878; // @[RegisterRouter.scala:87:24] wire out_woready_1_879; // @[RegisterRouter.scala:87:24] wire out_woready_1_880; // @[RegisterRouter.scala:87:24] wire out_woready_1_881; // @[RegisterRouter.scala:87:24] wire out_woready_1_882; // @[RegisterRouter.scala:87:24] wire out_woready_1_883; // @[RegisterRouter.scala:87:24] wire out_woready_1_884; // @[RegisterRouter.scala:87:24] wire out_woready_1_885; // @[RegisterRouter.scala:87:24] wire out_woready_1_886; // @[RegisterRouter.scala:87:24] wire out_woready_1_887; // @[RegisterRouter.scala:87:24] wire out_woready_1_888; // @[RegisterRouter.scala:87:24] wire out_woready_1_889; // @[RegisterRouter.scala:87:24] wire out_woready_1_890; // @[RegisterRouter.scala:87:24] wire out_woready_1_891; // @[RegisterRouter.scala:87:24] wire out_woready_1_892; // @[RegisterRouter.scala:87:24] wire out_woready_1_893; // @[RegisterRouter.scala:87:24] wire out_woready_1_894; // @[RegisterRouter.scala:87:24] wire out_woready_1_895; // @[RegisterRouter.scala:87:24] wire out_woready_1_896; // @[RegisterRouter.scala:87:24] wire out_woready_1_897; // @[RegisterRouter.scala:87:24] wire out_woready_1_898; // @[RegisterRouter.scala:87:24] wire out_woready_1_899; // @[RegisterRouter.scala:87:24] wire out_woready_1_900; // @[RegisterRouter.scala:87:24] wire out_woready_1_901; // @[RegisterRouter.scala:87:24] wire out_woready_1_902; // @[RegisterRouter.scala:87:24] wire out_woready_1_903; // @[RegisterRouter.scala:87:24] wire out_woready_1_904; // @[RegisterRouter.scala:87:24] wire out_woready_1_905; // @[RegisterRouter.scala:87:24] wire out_woready_1_906; // @[RegisterRouter.scala:87:24] wire out_woready_1_907; // @[RegisterRouter.scala:87:24] wire out_woready_1_908; // @[RegisterRouter.scala:87:24] wire out_woready_1_909; // @[RegisterRouter.scala:87:24] wire out_woready_1_910; // @[RegisterRouter.scala:87:24] wire out_woready_1_911; // @[RegisterRouter.scala:87:24] wire out_woready_1_912; // @[RegisterRouter.scala:87:24] wire out_woready_1_913; // @[RegisterRouter.scala:87:24] wire out_woready_1_914; // @[RegisterRouter.scala:87:24] wire out_woready_1_915; // @[RegisterRouter.scala:87:24] wire out_woready_1_916; // @[RegisterRouter.scala:87:24] wire out_woready_1_917; // @[RegisterRouter.scala:87:24] wire out_woready_1_918; // @[RegisterRouter.scala:87:24] wire out_woready_1_919; // @[RegisterRouter.scala:87:24] wire out_woready_1_920; // @[RegisterRouter.scala:87:24] wire out_woready_1_921; // @[RegisterRouter.scala:87:24] wire out_woready_1_922; // @[RegisterRouter.scala:87:24] wire out_woready_1_923; // @[RegisterRouter.scala:87:24] wire out_woready_1_924; // @[RegisterRouter.scala:87:24] wire out_woready_1_925; // @[RegisterRouter.scala:87:24] wire out_woready_1_926; // @[RegisterRouter.scala:87:24] wire out_woready_1_927; // @[RegisterRouter.scala:87:24] wire out_woready_1_928; // @[RegisterRouter.scala:87:24] wire out_woready_1_929; // @[RegisterRouter.scala:87:24] wire out_woready_1_930; // @[RegisterRouter.scala:87:24] wire out_woready_1_931; // @[RegisterRouter.scala:87:24] wire out_woready_1_932; // @[RegisterRouter.scala:87:24] wire out_woready_1_933; // @[RegisterRouter.scala:87:24] wire out_woready_1_934; // @[RegisterRouter.scala:87:24] wire out_woready_1_935; // @[RegisterRouter.scala:87:24] wire out_woready_1_936; // @[RegisterRouter.scala:87:24] wire out_woready_1_937; // @[RegisterRouter.scala:87:24] wire out_woready_1_938; // @[RegisterRouter.scala:87:24] wire out_woready_1_939; // @[RegisterRouter.scala:87:24] wire out_woready_1_940; // @[RegisterRouter.scala:87:24] wire out_woready_1_941; // @[RegisterRouter.scala:87:24] wire out_woready_1_942; // @[RegisterRouter.scala:87:24] wire out_woready_1_943; // @[RegisterRouter.scala:87:24] wire out_woready_1_944; // @[RegisterRouter.scala:87:24] wire out_woready_1_945; // @[RegisterRouter.scala:87:24] wire out_woready_1_946; // @[RegisterRouter.scala:87:24] wire out_woready_1_947; // @[RegisterRouter.scala:87:24] wire out_woready_1_948; // @[RegisterRouter.scala:87:24] wire out_woready_1_949; // @[RegisterRouter.scala:87:24] wire out_woready_1_950; // @[RegisterRouter.scala:87:24] wire out_woready_1_951; // @[RegisterRouter.scala:87:24] wire out_woready_1_952; // @[RegisterRouter.scala:87:24] wire out_woready_1_953; // @[RegisterRouter.scala:87:24] wire out_woready_1_954; // @[RegisterRouter.scala:87:24] wire out_woready_1_955; // @[RegisterRouter.scala:87:24] wire out_woready_1_956; // @[RegisterRouter.scala:87:24] wire out_woready_1_957; // @[RegisterRouter.scala:87:24] wire out_woready_1_958; // @[RegisterRouter.scala:87:24] wire out_woready_1_959; // @[RegisterRouter.scala:87:24] wire out_woready_1_960; // @[RegisterRouter.scala:87:24] wire out_woready_1_961; // @[RegisterRouter.scala:87:24] wire out_woready_1_962; // @[RegisterRouter.scala:87:24] wire out_woready_1_963; // @[RegisterRouter.scala:87:24] wire out_woready_1_964; // @[RegisterRouter.scala:87:24] wire out_woready_1_965; // @[RegisterRouter.scala:87:24] wire out_woready_1_966; // @[RegisterRouter.scala:87:24] wire out_woready_1_967; // @[RegisterRouter.scala:87:24] wire out_woready_1_968; // @[RegisterRouter.scala:87:24] wire out_woready_1_969; // @[RegisterRouter.scala:87:24] wire out_woready_1_970; // @[RegisterRouter.scala:87:24] wire out_woready_1_971; // @[RegisterRouter.scala:87:24] wire out_woready_1_972; // @[RegisterRouter.scala:87:24] wire out_woready_1_973; // @[RegisterRouter.scala:87:24] wire out_woready_1_974; // @[RegisterRouter.scala:87:24] wire out_woready_1_975; // @[RegisterRouter.scala:87:24] wire out_woready_1_976; // @[RegisterRouter.scala:87:24] wire out_woready_1_977; // @[RegisterRouter.scala:87:24] wire out_woready_1_978; // @[RegisterRouter.scala:87:24] wire out_woready_1_979; // @[RegisterRouter.scala:87:24] wire out_woready_1_980; // @[RegisterRouter.scala:87:24] wire out_woready_1_981; // @[RegisterRouter.scala:87:24] wire out_woready_1_982; // @[RegisterRouter.scala:87:24] wire out_woready_1_983; // @[RegisterRouter.scala:87:24] wire out_woready_1_984; // @[RegisterRouter.scala:87:24] wire out_woready_1_985; // @[RegisterRouter.scala:87:24] wire out_woready_1_986; // @[RegisterRouter.scala:87:24] wire out_woready_1_987; // @[RegisterRouter.scala:87:24] wire out_woready_1_988; // @[RegisterRouter.scala:87:24] wire out_woready_1_989; // @[RegisterRouter.scala:87:24] wire out_woready_1_990; // @[RegisterRouter.scala:87:24] wire out_woready_1_991; // @[RegisterRouter.scala:87:24] wire out_woready_1_992; // @[RegisterRouter.scala:87:24] wire out_woready_1_993; // @[RegisterRouter.scala:87:24] wire out_woready_1_994; // @[RegisterRouter.scala:87:24] wire out_woready_1_995; // @[RegisterRouter.scala:87:24] wire out_woready_1_996; // @[RegisterRouter.scala:87:24] wire out_woready_1_997; // @[RegisterRouter.scala:87:24] wire out_woready_1_998; // @[RegisterRouter.scala:87:24] wire out_woready_1_999; // @[RegisterRouter.scala:87:24] wire out_woready_1_1000; // @[RegisterRouter.scala:87:24] wire out_woready_1_1001; // @[RegisterRouter.scala:87:24] wire out_woready_1_1002; // @[RegisterRouter.scala:87:24] wire out_woready_1_1003; // @[RegisterRouter.scala:87:24] wire out_woready_1_1004; // @[RegisterRouter.scala:87:24] wire out_woready_1_1005; // @[RegisterRouter.scala:87:24] wire out_woready_1_1006; // @[RegisterRouter.scala:87:24] wire out_woready_1_1007; // @[RegisterRouter.scala:87:24] wire out_woready_1_1008; // @[RegisterRouter.scala:87:24] wire out_woready_1_1009; // @[RegisterRouter.scala:87:24] wire out_woready_1_1010; // @[RegisterRouter.scala:87:24] wire out_woready_1_1011; // @[RegisterRouter.scala:87:24] wire out_woready_1_1012; // @[RegisterRouter.scala:87:24] wire out_woready_1_1013; // @[RegisterRouter.scala:87:24] wire out_woready_1_1014; // @[RegisterRouter.scala:87:24] wire out_woready_1_1015; // @[RegisterRouter.scala:87:24] wire out_woready_1_1016; // @[RegisterRouter.scala:87:24] wire out_woready_1_1017; // @[RegisterRouter.scala:87:24] wire out_woready_1_1018; // @[RegisterRouter.scala:87:24] wire out_woready_1_1019; // @[RegisterRouter.scala:87:24] wire out_woready_1_1020; // @[RegisterRouter.scala:87:24] wire out_woready_1_1021; // @[RegisterRouter.scala:87:24] wire out_woready_1_1022; // @[RegisterRouter.scala:87:24] wire out_woready_1_1023; // @[RegisterRouter.scala:87:24] wire out_woready_1_1024; // @[RegisterRouter.scala:87:24] wire out_woready_1_1025; // @[RegisterRouter.scala:87:24] wire out_woready_1_1026; // @[RegisterRouter.scala:87:24] wire out_woready_1_1027; // @[RegisterRouter.scala:87:24] wire out_woready_1_1028; // @[RegisterRouter.scala:87:24] wire out_woready_1_1029; // @[RegisterRouter.scala:87:24] wire out_woready_1_1030; // @[RegisterRouter.scala:87:24] wire out_woready_1_1031; // @[RegisterRouter.scala:87:24] wire out_woready_1_1032; // @[RegisterRouter.scala:87:24] wire out_woready_1_1033; // @[RegisterRouter.scala:87:24] wire out_woready_1_1034; // @[RegisterRouter.scala:87:24] wire out_woready_1_1035; // @[RegisterRouter.scala:87:24] wire out_woready_1_1036; // @[RegisterRouter.scala:87:24] wire out_woready_1_1037; // @[RegisterRouter.scala:87:24] wire out_woready_1_1038; // @[RegisterRouter.scala:87:24] wire out_woready_1_1039; // @[RegisterRouter.scala:87:24] wire out_woready_1_1040; // @[RegisterRouter.scala:87:24] wire out_woready_1_1041; // @[RegisterRouter.scala:87:24] wire out_woready_1_1042; // @[RegisterRouter.scala:87:24] wire out_woready_1_1043; // @[RegisterRouter.scala:87:24] wire out_woready_1_1044; // @[RegisterRouter.scala:87:24] wire out_woready_1_1045; // @[RegisterRouter.scala:87:24] wire out_woready_1_1046; // @[RegisterRouter.scala:87:24] wire out_woready_1_1047; // @[RegisterRouter.scala:87:24] wire out_woready_1_1048; // @[RegisterRouter.scala:87:24] wire out_woready_1_1049; // @[RegisterRouter.scala:87:24] wire out_woready_1_1050; // @[RegisterRouter.scala:87:24] wire out_woready_1_1051; // @[RegisterRouter.scala:87:24] wire out_woready_1_1052; // @[RegisterRouter.scala:87:24] wire out_woready_1_1053; // @[RegisterRouter.scala:87:24] wire out_woready_1_1054; // @[RegisterRouter.scala:87:24] wire out_woready_1_1055; // @[RegisterRouter.scala:87:24] wire out_woready_1_1056; // @[RegisterRouter.scala:87:24] wire out_woready_1_1057; // @[RegisterRouter.scala:87:24] wire out_woready_1_1058; // @[RegisterRouter.scala:87:24] wire out_woready_1_1059; // @[RegisterRouter.scala:87:24] wire out_woready_1_1060; // @[RegisterRouter.scala:87:24] wire out_woready_1_1061; // @[RegisterRouter.scala:87:24] wire out_woready_1_1062; // @[RegisterRouter.scala:87:24] wire out_woready_1_1063; // @[RegisterRouter.scala:87:24] wire out_woready_1_1064; // @[RegisterRouter.scala:87:24] wire out_woready_1_1065; // @[RegisterRouter.scala:87:24] wire out_woready_1_1066; // @[RegisterRouter.scala:87:24] wire out_woready_1_1067; // @[RegisterRouter.scala:87:24] wire out_woready_1_1068; // @[RegisterRouter.scala:87:24] wire out_woready_1_1069; // @[RegisterRouter.scala:87:24] wire out_woready_1_1070; // @[RegisterRouter.scala:87:24] wire out_woready_1_1071; // @[RegisterRouter.scala:87:24] wire out_woready_1_1072; // @[RegisterRouter.scala:87:24] wire out_woready_1_1073; // @[RegisterRouter.scala:87:24] wire out_woready_1_1074; // @[RegisterRouter.scala:87:24] wire out_woready_1_1075; // @[RegisterRouter.scala:87:24] wire out_woready_1_1076; // @[RegisterRouter.scala:87:24] wire out_woready_1_1077; // @[RegisterRouter.scala:87:24] wire out_woready_1_1078; // @[RegisterRouter.scala:87:24] wire out_woready_1_1079; // @[RegisterRouter.scala:87:24] wire out_woready_1_1080; // @[RegisterRouter.scala:87:24] wire out_woready_1_1081; // @[RegisterRouter.scala:87:24] wire out_woready_1_1082; // @[RegisterRouter.scala:87:24] wire out_woready_1_1083; // @[RegisterRouter.scala:87:24] wire out_woready_1_1084; // @[RegisterRouter.scala:87:24] wire out_woready_1_1085; // @[RegisterRouter.scala:87:24] wire out_woready_1_1086; // @[RegisterRouter.scala:87:24] wire out_woready_1_1087; // @[RegisterRouter.scala:87:24] wire out_woready_1_1088; // @[RegisterRouter.scala:87:24] wire out_woready_1_1089; // @[RegisterRouter.scala:87:24] wire out_woready_1_1090; // @[RegisterRouter.scala:87:24] wire out_woready_1_1091; // @[RegisterRouter.scala:87:24] wire out_woready_1_1092; // @[RegisterRouter.scala:87:24] wire out_woready_1_1093; // @[RegisterRouter.scala:87:24] wire out_woready_1_1094; // @[RegisterRouter.scala:87:24] wire out_woready_1_1095; // @[RegisterRouter.scala:87:24] wire out_woready_1_1096; // @[RegisterRouter.scala:87:24] wire out_woready_1_1097; // @[RegisterRouter.scala:87:24] wire out_woready_1_1098; // @[RegisterRouter.scala:87:24] wire out_woready_1_1099; // @[RegisterRouter.scala:87:24] wire out_woready_1_1100; // @[RegisterRouter.scala:87:24] wire out_woready_1_1101; // @[RegisterRouter.scala:87:24] wire out_woready_1_1102; // @[RegisterRouter.scala:87:24] wire out_woready_1_1103; // @[RegisterRouter.scala:87:24] wire out_woready_1_1104; // @[RegisterRouter.scala:87:24] wire out_woready_1_1105; // @[RegisterRouter.scala:87:24] wire out_woready_1_1106; // @[RegisterRouter.scala:87:24] wire out_woready_1_1107; // @[RegisterRouter.scala:87:24] wire out_woready_1_1108; // @[RegisterRouter.scala:87:24] wire out_woready_1_1109; // @[RegisterRouter.scala:87:24] wire out_woready_1_1110; // @[RegisterRouter.scala:87:24] wire out_woready_1_1111; // @[RegisterRouter.scala:87:24] wire out_woready_1_1112; // @[RegisterRouter.scala:87:24] wire out_woready_1_1113; // @[RegisterRouter.scala:87:24] wire out_woready_1_1114; // @[RegisterRouter.scala:87:24] wire out_woready_1_1115; // @[RegisterRouter.scala:87:24] wire out_woready_1_1116; // @[RegisterRouter.scala:87:24] wire out_woready_1_1117; // @[RegisterRouter.scala:87:24] wire out_woready_1_1118; // @[RegisterRouter.scala:87:24] wire out_woready_1_1119; // @[RegisterRouter.scala:87:24] wire out_woready_1_1120; // @[RegisterRouter.scala:87:24] wire out_woready_1_1121; // @[RegisterRouter.scala:87:24] wire out_woready_1_1122; // @[RegisterRouter.scala:87:24] wire out_woready_1_1123; // @[RegisterRouter.scala:87:24] wire out_woready_1_1124; // @[RegisterRouter.scala:87:24] wire out_woready_1_1125; // @[RegisterRouter.scala:87:24] wire out_woready_1_1126; // @[RegisterRouter.scala:87:24] wire out_woready_1_1127; // @[RegisterRouter.scala:87:24] wire out_woready_1_1128; // @[RegisterRouter.scala:87:24] wire out_woready_1_1129; // @[RegisterRouter.scala:87:24] wire out_woready_1_1130; // @[RegisterRouter.scala:87:24] wire out_woready_1_1131; // @[RegisterRouter.scala:87:24] wire out_woready_1_1132; // @[RegisterRouter.scala:87:24] wire out_woready_1_1133; // @[RegisterRouter.scala:87:24] wire out_woready_1_1134; // @[RegisterRouter.scala:87:24] wire out_woready_1_1135; // @[RegisterRouter.scala:87:24] wire out_woready_1_1136; // @[RegisterRouter.scala:87:24] wire out_woready_1_1137; // @[RegisterRouter.scala:87:24] wire out_woready_1_1138; // @[RegisterRouter.scala:87:24] wire out_woready_1_1139; // @[RegisterRouter.scala:87:24] wire out_woready_1_1140; // @[RegisterRouter.scala:87:24] wire out_woready_1_1141; // @[RegisterRouter.scala:87:24] wire out_woready_1_1142; // @[RegisterRouter.scala:87:24] wire out_woready_1_1143; // @[RegisterRouter.scala:87:24] wire out_woready_1_1144; // @[RegisterRouter.scala:87:24] wire out_woready_1_1145; // @[RegisterRouter.scala:87:24] wire out_woready_1_1146; // @[RegisterRouter.scala:87:24] wire out_woready_1_1147; // @[RegisterRouter.scala:87:24] wire out_woready_1_1148; // @[RegisterRouter.scala:87:24] wire out_woready_1_1149; // @[RegisterRouter.scala:87:24] wire out_woready_1_1150; // @[RegisterRouter.scala:87:24] wire out_woready_1_1151; // @[RegisterRouter.scala:87:24] wire out_woready_1_1152; // @[RegisterRouter.scala:87:24] wire out_woready_1_1153; // @[RegisterRouter.scala:87:24] wire out_woready_1_1154; // @[RegisterRouter.scala:87:24] wire out_woready_1_1155; // @[RegisterRouter.scala:87:24] wire out_woready_1_1156; // @[RegisterRouter.scala:87:24] wire out_woready_1_1157; // @[RegisterRouter.scala:87:24] wire out_woready_1_1158; // @[RegisterRouter.scala:87:24] wire out_woready_1_1159; // @[RegisterRouter.scala:87:24] wire out_woready_1_1160; // @[RegisterRouter.scala:87:24] wire out_woready_1_1161; // @[RegisterRouter.scala:87:24] wire out_woready_1_1162; // @[RegisterRouter.scala:87:24] wire out_woready_1_1163; // @[RegisterRouter.scala:87:24] wire out_woready_1_1164; // @[RegisterRouter.scala:87:24] wire out_woready_1_1165; // @[RegisterRouter.scala:87:24] wire out_woready_1_1166; // @[RegisterRouter.scala:87:24] wire out_woready_1_1167; // @[RegisterRouter.scala:87:24] wire out_woready_1_1168; // @[RegisterRouter.scala:87:24] wire out_woready_1_1169; // @[RegisterRouter.scala:87:24] wire out_woready_1_1170; // @[RegisterRouter.scala:87:24] wire out_woready_1_1171; // @[RegisterRouter.scala:87:24] wire out_woready_1_1172; // @[RegisterRouter.scala:87:24] wire out_woready_1_1173; // @[RegisterRouter.scala:87:24] wire out_woready_1_1174; // @[RegisterRouter.scala:87:24] wire out_woready_1_1175; // @[RegisterRouter.scala:87:24] wire out_woready_1_1176; // @[RegisterRouter.scala:87:24] wire out_woready_1_1177; // @[RegisterRouter.scala:87:24] wire out_woready_1_1178; // @[RegisterRouter.scala:87:24] wire out_woready_1_1179; // @[RegisterRouter.scala:87:24] wire out_woready_1_1180; // @[RegisterRouter.scala:87:24] wire out_woready_1_1181; // @[RegisterRouter.scala:87:24] wire out_woready_1_1182; // @[RegisterRouter.scala:87:24] wire out_woready_1_1183; // @[RegisterRouter.scala:87:24] wire out_woready_1_1184; // @[RegisterRouter.scala:87:24] wire out_woready_1_1185; // @[RegisterRouter.scala:87:24] wire out_woready_1_1186; // @[RegisterRouter.scala:87:24] wire out_woready_1_1187; // @[RegisterRouter.scala:87:24] wire out_woready_1_1188; // @[RegisterRouter.scala:87:24] wire out_woready_1_1189; // @[RegisterRouter.scala:87:24] wire out_woready_1_1190; // @[RegisterRouter.scala:87:24] wire out_woready_1_1191; // @[RegisterRouter.scala:87:24] wire out_woready_1_1192; // @[RegisterRouter.scala:87:24] wire out_woready_1_1193; // @[RegisterRouter.scala:87:24] wire out_woready_1_1194; // @[RegisterRouter.scala:87:24] wire out_woready_1_1195; // @[RegisterRouter.scala:87:24] wire out_woready_1_1196; // @[RegisterRouter.scala:87:24] wire out_woready_1_1197; // @[RegisterRouter.scala:87:24] wire out_woready_1_1198; // @[RegisterRouter.scala:87:24] wire out_woready_1_1199; // @[RegisterRouter.scala:87:24] wire out_woready_1_1200; // @[RegisterRouter.scala:87:24] wire out_woready_1_1201; // @[RegisterRouter.scala:87:24] wire out_woready_1_1202; // @[RegisterRouter.scala:87:24] wire out_woready_1_1203; // @[RegisterRouter.scala:87:24] wire out_woready_1_1204; // @[RegisterRouter.scala:87:24] wire out_woready_1_1205; // @[RegisterRouter.scala:87:24] wire out_woready_1_1206; // @[RegisterRouter.scala:87:24] wire out_woready_1_1207; // @[RegisterRouter.scala:87:24] wire out_woready_1_1208; // @[RegisterRouter.scala:87:24] wire out_woready_1_1209; // @[RegisterRouter.scala:87:24] wire out_woready_1_1210; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_16 = {8{_out_frontMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_17 = {8{_out_frontMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_18 = {8{_out_frontMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_19 = {8{_out_frontMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_20 = {8{_out_frontMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_21 = {8{_out_frontMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_22 = {8{_out_frontMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_23 = {8{_out_frontMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_17, _out_frontMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_19, _out_frontMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo_1 = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_21, _out_frontMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_23, _out_frontMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi_1 = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask_1 = {out_frontMask_hi_1, out_frontMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_16 = {8{_out_backMask_T_8}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_17 = {8{_out_backMask_T_9}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_18 = {8{_out_backMask_T_10}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_19 = {8{_out_backMask_T_11}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_20 = {8{_out_backMask_T_12}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_21 = {8{_out_backMask_T_13}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_22 = {8{_out_backMask_T_14}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_23 = {8{_out_backMask_T_15}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_17, _out_backMask_T_16}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_19, _out_backMask_T_18}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo_1 = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_21, _out_backMask_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_23, _out_backMask_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi_1 = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask_1 = {out_backMask_hi_1, out_backMask_lo_1}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_146 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_154 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_162 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_170 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_178 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_186 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_194 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_202 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_210 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_218 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_226 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_234 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_242 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_250 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_258 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_266 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_274 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_282 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_290 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_298 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_306 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_314 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_322 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_330 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_338 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_346 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_354 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_362 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_370 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_378 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_386 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_394 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_402 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_410 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_418 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_426 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_434 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_442 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_450 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_458 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_466 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_474 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_482 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_490 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_500 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_508 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_516 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_524 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_532 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_540 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_548 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_556 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_564 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_572 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_580 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_589 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_597 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_605 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_613 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_621 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_629 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_633 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_641 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_649 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_657 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_665 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_673 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_683 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_691 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_699 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_707 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_715 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_723 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_731 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_739 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_747 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_755 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_763 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_771 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_779 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_787 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_795 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_803 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_811 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_819 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_827 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_835 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_845 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_853 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_861 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_869 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_877 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_885 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_893 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_901 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_909 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_917 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_925 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_933 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_941 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_949 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_957 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_965 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_973 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_981 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_989 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_997 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1005 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1013 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1021 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1029 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1037 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1045 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1053 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1061 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1069 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1077 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1085 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1093 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1101 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1109 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1117 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1125 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1133 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1141 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1149 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1157 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1165 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1173 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1181 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1189 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1197 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1205 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1213 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1221 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1229 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1237 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1245 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1253 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1261 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1269 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1277 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1285 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1293 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1301 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1309 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1317 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1325 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1333 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1341 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1349 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_146 = |_out_rimask_T_146; // @[RegisterRouter.scala:87:24] wire out_wimask_146 = &_out_wimask_T_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_146 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_154 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_162 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_170 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_178 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_186 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_194 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_202 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_210 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_218 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_226 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_234 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_242 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_250 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_258 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_266 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_274 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_282 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_290 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_298 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_306 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_314 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_322 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_330 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_338 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_346 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_354 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_362 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_370 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_378 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_386 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_394 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_402 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_410 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_418 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_426 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_434 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_442 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_450 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_458 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_466 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_474 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_482 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_490 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_500 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_508 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_516 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_524 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_532 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_540 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_548 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_556 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_564 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_572 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_580 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_589 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_597 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_605 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_613 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_621 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_629 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_633 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_641 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_649 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_657 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_665 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_673 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_683 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_691 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_699 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_707 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_715 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_723 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_731 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_739 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_747 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_755 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_763 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_771 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_779 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_787 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_795 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_803 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_811 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_819 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_827 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_835 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_845 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_853 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_861 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_869 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_877 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_885 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_893 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_901 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_909 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_917 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_925 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_933 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_941 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_949 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_957 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_965 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_973 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_981 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_989 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_997 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1005 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1013 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1021 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1029 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1037 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1045 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1053 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1061 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1069 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1077 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1085 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1093 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1101 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1109 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1117 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1125 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1133 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1141 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1149 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1157 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1165 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1173 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1181 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1189 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1197 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1205 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1213 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1221 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1229 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1237 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1245 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1253 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1261 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1269 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1277 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1285 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1293 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1301 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1309 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1317 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1325 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1333 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1341 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1349 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_146 = |_out_romask_T_146; // @[RegisterRouter.scala:87:24] wire out_womask_146 = &_out_womask_T_146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_146 = out_rivalid_1_0 & out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1911 = out_f_rivalid_146; // @[RegisterRouter.scala:87:24] wire out_f_roready_146 = out_roready_1_0 & out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1912 = out_f_roready_146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_146 = out_wivalid_1_0 & out_wimask_146; // @[RegisterRouter.scala:87:24] wire out_f_woready_146 = out_woready_1_0 & out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2126 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2198 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2286 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2358 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2430 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2502 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2574 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2646 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2718 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2790 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2862 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2934 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3022 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3094 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3166 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3238 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3310 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3382 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3454 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3526 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3598 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3670 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3758 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3830 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3902 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3974 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4046 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4118 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4190 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4262 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4334 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4406 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4478 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4550 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4622 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4694 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4766 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4838 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4910 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4982 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5054 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5144 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5216 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5288 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5360 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5432 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5504 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5576 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5648 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5720 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5792 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5864 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5945 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6357 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6429 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6501 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6573 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6661 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6733 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6823 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6895 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6967 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7039 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7111 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7183 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7255 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7327 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7399 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7471 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7543 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7615 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7687 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7759 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7831 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7903 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7991 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8063 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8135 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8207 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8297 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8369 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8441 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8513 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8585 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8961 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9033 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9105 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9177 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9249 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9321 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9393 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9465 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9625 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9697 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9769 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9841 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9913 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9985 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10057 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10129 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10201 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10273 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10345 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10417 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10505 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10577 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10649 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10721 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10793 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10865 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10953 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11025 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11097 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11169 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11241 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11313 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11385 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11457 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11529 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11601 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11673 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11745 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11817 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11889 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11977 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12049 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12121 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12193 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12265 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12337 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12409 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12481 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12553 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12641 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12713 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12785 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12857 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12929 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_1913 = ~out_rimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1914 = ~out_wimask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1915 = ~out_romask_146; // @[RegisterRouter.scala:87:24] wire _out_T_1916 = ~out_womask_146; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1918 = _out_T_1917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_112 = _out_T_1918; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_147 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_155 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_163 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_171 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_179 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_187 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_195 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_203 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_211 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_219 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_227 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_235 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_243 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_251 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_259 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_267 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_275 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_283 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_291 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_299 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_307 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_315 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_323 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_331 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_339 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_347 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_355 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_363 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_371 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_379 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_387 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_395 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_403 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_411 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_419 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_427 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_435 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_443 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_451 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_459 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_467 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_475 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_483 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_491 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_501 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_509 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_517 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_525 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_533 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_541 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_549 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_557 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_565 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_573 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_581 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_590 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_598 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_606 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_614 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_622 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_630 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_634 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_642 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_650 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_658 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_666 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_674 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_684 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_692 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_700 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_708 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_716 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_724 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_732 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_740 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_748 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_756 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_764 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_772 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_780 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_788 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_796 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_804 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_812 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_820 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_828 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_836 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_846 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_854 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_862 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_870 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_878 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_886 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_894 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_902 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_910 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_918 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_926 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_934 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_942 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_950 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_958 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_966 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_974 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_982 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_990 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_998 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1006 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1014 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1022 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1030 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1038 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1046 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1054 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1062 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1070 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1078 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1086 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1094 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1102 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1110 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1118 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1126 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1134 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1142 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1150 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1158 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1166 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1174 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1182 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1190 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1198 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1206 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1214 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1222 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1230 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1238 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1246 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1254 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1262 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1270 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1278 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1286 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1294 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1302 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1310 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1318 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1326 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1334 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1342 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1350 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_147 = |_out_rimask_T_147; // @[RegisterRouter.scala:87:24] wire out_wimask_147 = &_out_wimask_T_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_147 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_155 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_163 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_171 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_179 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_187 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_195 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_203 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_211 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_219 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_227 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_235 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_243 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_251 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_259 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_267 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_275 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_283 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_291 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_299 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_307 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_315 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_323 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_331 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_339 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_347 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_355 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_363 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_371 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_379 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_387 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_395 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_403 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_411 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_419 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_427 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_435 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_443 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_451 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_459 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_467 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_475 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_483 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_491 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_501 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_509 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_517 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_525 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_533 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_541 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_549 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_557 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_565 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_573 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_581 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_590 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_598 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_606 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_614 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_622 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_630 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_634 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_642 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_650 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_658 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_666 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_674 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_684 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_692 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_700 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_708 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_716 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_724 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_732 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_740 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_748 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_756 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_764 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_772 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_780 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_788 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_796 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_804 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_812 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_820 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_828 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_836 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_846 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_854 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_862 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_870 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_878 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_886 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_894 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_902 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_910 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_918 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_926 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_934 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_942 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_950 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_958 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_966 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_974 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_982 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_990 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_998 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1006 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1014 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1022 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1030 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1038 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1046 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1054 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1062 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1070 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1078 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1086 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1094 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1102 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1110 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1118 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1126 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1134 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1142 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1150 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1158 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1166 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1174 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1182 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1190 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1198 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1206 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1214 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1222 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1230 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1238 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1246 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1254 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1262 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1270 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1278 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1286 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1294 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1302 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1310 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1318 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1326 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1334 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1342 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1350 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_147 = |_out_romask_T_147; // @[RegisterRouter.scala:87:24] wire out_womask_147 = &_out_womask_T_147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_147 = out_rivalid_1_1 & out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1920 = out_f_rivalid_147; // @[RegisterRouter.scala:87:24] wire out_f_roready_147 = out_roready_1_1 & out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1921 = out_f_roready_147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_147 = out_wivalid_1_1 & out_wimask_147; // @[RegisterRouter.scala:87:24] wire out_f_woready_147 = out_woready_1_1 & out_womask_147; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2135 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2209 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2295 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2367 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2439 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2511 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2583 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2655 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2727 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2799 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2871 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2945 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3031 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3103 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3175 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3247 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3319 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3391 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3463 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3535 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3607 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3681 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3767 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3839 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3911 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3983 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4055 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4127 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4199 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4271 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4343 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4415 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4487 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4559 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4631 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4703 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4775 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4847 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4919 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4991 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5063 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5153 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5225 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5297 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5369 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5441 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5513 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5585 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5657 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5729 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5801 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5873 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5956 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6366 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6438 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6510 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6584 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6670 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6742 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6832 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6904 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6976 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7048 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7120 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7192 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7264 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7336 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7408 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7480 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7552 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7624 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7696 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7768 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7840 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7914 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8000 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8072 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8144 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8216 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8306 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8378 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8450 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8522 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8596 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8898 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8970 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9042 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9114 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9186 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9258 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9330 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9402 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9476 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9562 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9634 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9706 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9778 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9850 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9922 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9994 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10066 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10138 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10210 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10282 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10354 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10428 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10514 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10586 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10658 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10730 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10802 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10876 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10962 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11034 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11106 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11178 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11250 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11322 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11394 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11466 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11538 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11610 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11682 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11754 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11826 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11900 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11986 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12058 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12130 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12202 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12274 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12346 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12418 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12490 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12564 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12650 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12722 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12794 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12866 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12938 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_1922 = ~out_rimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1923 = ~out_wimask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1924 = ~out_romask_147; // @[RegisterRouter.scala:87:24] wire _out_T_1925 = ~out_womask_147; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_112 = {hi_82, flags_0_go, _out_prepend_T_112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1926 = out_prepend_112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1927 = _out_T_1926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_113 = _out_T_1927; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_148 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_156 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_164 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_172 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_180 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_188 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_196 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_204 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_212 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_220 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_228 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_236 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_244 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_252 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_260 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_268 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_276 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_284 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_292 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_300 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_308 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_316 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_324 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_332 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_340 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_348 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_356 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_364 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_372 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_380 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_388 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_396 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_404 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_412 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_420 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_428 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_436 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_444 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_452 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_460 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_468 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_476 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_484 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_492 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_502 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_510 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_518 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_526 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_534 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_542 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_550 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_558 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_566 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_574 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_582 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_591 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_599 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_607 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_615 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_623 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_631 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_635 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_643 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_651 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_659 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_667 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_675 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_685 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_693 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_701 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_709 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_717 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_725 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_733 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_741 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_749 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_757 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_765 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_773 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_781 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_789 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_797 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_805 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_813 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_821 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_829 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_837 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_847 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_855 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_863 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_871 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_879 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_887 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_895 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_903 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_911 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_919 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_927 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_935 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_943 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_951 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_959 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_967 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_975 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_983 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_991 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_999 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1007 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1015 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1023 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1031 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1039 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1047 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1055 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1063 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1071 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1079 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1087 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1095 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1103 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1111 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1119 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1127 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1135 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1143 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1151 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1159 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1167 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1175 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1183 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1191 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1199 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1207 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1215 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1223 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1231 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1239 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1247 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1255 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1263 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1271 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1279 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1287 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1295 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1303 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1311 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1319 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1327 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1335 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1343 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1351 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_148 = |_out_rimask_T_148; // @[RegisterRouter.scala:87:24] wire out_wimask_148 = &_out_wimask_T_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_148 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_156 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_164 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_172 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_180 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_188 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_196 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_204 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_212 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_220 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_228 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_236 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_244 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_252 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_260 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_268 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_276 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_284 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_292 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_300 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_308 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_316 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_324 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_332 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_340 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_348 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_356 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_364 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_372 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_380 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_388 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_396 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_404 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_412 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_420 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_428 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_436 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_444 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_452 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_460 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_468 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_476 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_484 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_492 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_502 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_510 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_518 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_526 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_534 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_542 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_550 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_558 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_566 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_574 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_582 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_591 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_599 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_607 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_615 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_623 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_631 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_635 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_643 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_651 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_659 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_667 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_675 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_685 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_693 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_701 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_709 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_717 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_725 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_733 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_741 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_749 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_757 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_765 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_773 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_781 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_789 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_797 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_805 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_813 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_821 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_829 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_837 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_847 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_855 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_863 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_871 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_879 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_887 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_895 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_903 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_911 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_919 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_927 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_935 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_943 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_951 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_959 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_967 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_975 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_983 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_991 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_999 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1007 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1015 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1023 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1031 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1039 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1047 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1055 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1063 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1071 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1079 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1087 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1095 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1103 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1111 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1119 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1127 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1135 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1143 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1151 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1159 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1167 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1175 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1183 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1191 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1199 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1207 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1215 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1223 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1231 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1239 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1247 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1255 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1263 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1271 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1279 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1287 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1295 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1303 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1311 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1319 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1327 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1335 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1343 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1351 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_148 = |_out_romask_T_148; // @[RegisterRouter.scala:87:24] wire out_womask_148 = &_out_womask_T_148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_148 = out_rivalid_1_2 & out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1929 = out_f_rivalid_148; // @[RegisterRouter.scala:87:24] wire out_f_roready_148 = out_roready_1_2 & out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1930 = out_f_roready_148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_148 = out_wivalid_1_2 & out_wimask_148; // @[RegisterRouter.scala:87:24] wire out_f_woready_148 = out_woready_1_2 & out_womask_148; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2144 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2220 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2304 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2376 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2448 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2520 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2592 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2664 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2736 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2808 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2880 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2956 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3040 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3112 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3184 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3256 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3328 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3400 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3472 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3544 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3616 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3692 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3776 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3848 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3920 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3992 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4064 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4136 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4208 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4280 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4352 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4424 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4496 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4568 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4640 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4712 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4784 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4856 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4928 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5000 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5072 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5162 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5234 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5306 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5378 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5450 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5522 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5594 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5666 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5738 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5810 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5882 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5967 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6375 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6447 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6519 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6679 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6751 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6841 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6913 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6985 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7057 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7129 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7201 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7273 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7345 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7417 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7489 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7561 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7633 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7705 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7777 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7849 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7925 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8009 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8081 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8153 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8225 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8315 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8387 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8459 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8531 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8607 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8907 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8979 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9051 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9123 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9195 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9267 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9339 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9411 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9487 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9571 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9643 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9715 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9787 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9859 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9931 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10003 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10075 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10147 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10219 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10291 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10363 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10439 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10523 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10595 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10667 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10739 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10811 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10887 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10971 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11043 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11115 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11187 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11259 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11331 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11403 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11475 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11547 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11619 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11691 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11763 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11835 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11911 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11995 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12067 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12139 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12211 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12283 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12355 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12427 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12499 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12575 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12659 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12731 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12803 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12875 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12947 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_1931 = ~out_rimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1932 = ~out_wimask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1933 = ~out_romask_148; // @[RegisterRouter.scala:87:24] wire _out_T_1934 = ~out_womask_148; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_113 = {hi_83, flags_0_go, _out_prepend_T_113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1935 = out_prepend_113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_1936 = _out_T_1935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_114 = _out_T_1936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_149 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_157 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_165 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_173 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_181 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_189 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_197 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_205 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_213 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_221 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_229 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_237 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_245 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_253 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_261 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_269 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_277 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_285 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_293 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_301 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_309 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_317 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_325 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_333 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_341 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_349 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_357 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_365 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_373 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_381 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_389 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_397 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_405 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_413 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_421 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_429 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_437 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_445 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_453 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_461 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_469 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_477 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_485 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_493 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_503 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_511 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_519 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_527 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_535 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_543 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_551 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_559 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_567 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_575 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_583 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_592 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_600 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_608 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_616 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_624 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_632 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_636 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_644 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_652 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_660 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_668 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_676 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_686 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_694 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_702 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_710 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_718 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_726 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_734 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_742 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_750 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_758 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_766 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_774 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_782 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_790 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_798 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_806 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_814 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_822 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_830 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_838 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_848 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_856 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_864 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_872 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_880 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_888 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_896 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_904 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_912 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_920 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_928 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_936 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_944 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_952 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_960 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_968 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_976 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_984 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_992 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1000 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1008 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1016 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1024 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1032 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1040 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1048 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1056 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1064 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1072 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1080 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1088 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1096 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1104 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1112 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1120 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1128 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1136 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1144 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1152 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1160 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1168 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1176 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1184 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1192 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1200 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1208 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1216 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1224 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1232 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1240 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1248 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1256 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1264 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1272 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1280 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1288 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1296 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1304 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1312 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1320 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1328 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1336 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1344 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1352 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_149 = |_out_rimask_T_149; // @[RegisterRouter.scala:87:24] wire out_wimask_149 = &_out_wimask_T_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_149 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_157 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_165 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_173 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_181 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_189 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_197 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_205 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_213 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_221 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_229 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_237 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_245 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_253 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_261 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_269 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_277 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_285 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_293 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_301 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_309 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_317 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_325 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_333 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_341 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_349 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_357 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_365 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_373 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_381 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_389 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_397 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_405 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_413 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_421 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_429 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_437 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_445 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_453 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_461 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_469 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_477 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_485 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_493 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_503 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_511 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_519 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_527 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_535 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_543 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_551 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_559 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_567 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_575 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_583 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_592 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_600 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_608 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_616 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_624 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_632 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_636 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_644 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_652 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_660 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_668 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_676 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_686 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_694 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_702 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_710 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_718 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_726 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_734 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_742 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_750 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_758 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_766 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_774 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_782 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_790 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_798 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_806 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_814 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_822 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_830 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_838 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_848 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_856 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_864 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_872 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_880 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_888 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_896 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_904 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_912 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_920 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_928 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_936 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_944 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_952 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_960 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_968 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_976 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_984 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_992 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1000 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1008 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1016 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1024 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1032 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1040 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1048 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1056 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1064 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1072 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1080 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1088 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1096 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1104 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1112 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1120 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1128 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1136 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1144 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1152 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1160 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1168 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1176 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1184 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1192 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1200 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1208 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1216 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1224 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1232 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1240 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1248 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1256 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1264 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1272 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1280 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1288 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1296 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1304 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1312 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1320 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1328 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1336 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1344 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1352 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_149 = |_out_romask_T_149; // @[RegisterRouter.scala:87:24] wire out_womask_149 = &_out_womask_T_149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_149 = out_rivalid_1_3 & out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1938 = out_f_rivalid_149; // @[RegisterRouter.scala:87:24] wire out_f_roready_149 = out_roready_1_3 & out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1939 = out_f_roready_149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_149 = out_wivalid_1_3 & out_wimask_149; // @[RegisterRouter.scala:87:24] wire out_f_woready_149 = out_woready_1_3 & out_womask_149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2153 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2231 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2313 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2385 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2457 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2529 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2601 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2673 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2745 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2817 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2889 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2967 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3049 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3121 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3193 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3265 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3337 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3409 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3481 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3553 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3625 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3703 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3785 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3857 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3929 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4001 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4073 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4145 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4217 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4289 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4361 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4433 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4505 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4577 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4649 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4721 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4793 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4865 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4937 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5009 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5081 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5171 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5243 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5315 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5387 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5459 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5531 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5603 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5675 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5747 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5819 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5891 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5978 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6384 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6456 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6528 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6606 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6688 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6760 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6850 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6994 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7066 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7138 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7210 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7282 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7354 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7426 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7570 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7642 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7714 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7786 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7858 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7936 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8018 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8090 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8162 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8234 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8324 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8396 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8468 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8540 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8618 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8916 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8988 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9060 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9132 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9204 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9276 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9348 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9420 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9498 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9580 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9652 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9724 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9796 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9868 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9940 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10012 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10084 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10156 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10228 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10300 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10372 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10450 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10532 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10604 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10676 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10748 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10820 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10898 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10980 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11052 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11124 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11196 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11268 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11340 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11412 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11484 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11556 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11628 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11700 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11772 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11844 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11922 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12004 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12076 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12148 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12220 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12292 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12364 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12436 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12508 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12586 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12668 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12740 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12812 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12884 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12956 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_1940 = ~out_rimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1941 = ~out_wimask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1942 = ~out_romask_149; // @[RegisterRouter.scala:87:24] wire _out_T_1943 = ~out_womask_149; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_114 = {hi_84, flags_0_go, _out_prepend_T_114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1944 = out_prepend_114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_1945 = _out_T_1944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_115 = _out_T_1945; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_150 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_158 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_166 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_174 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_182 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_190 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_198 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_206 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_214 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_222 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_230 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_238 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_246 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_254 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_262 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_270 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_278 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_286 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_294 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_302 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_310 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_318 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_326 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_334 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_342 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_350 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_358 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_366 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_374 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_382 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_390 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_398 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_406 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_414 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_422 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_430 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_438 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_446 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_454 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_462 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_470 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_478 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_486 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_494 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_504 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_512 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_520 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_528 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_536 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_544 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_552 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_560 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_568 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_576 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_584 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_593 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_601 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_609 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_617 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_625 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_637 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_645 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_653 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_661 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_669 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_677 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_687 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_695 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_703 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_711 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_719 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_727 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_735 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_743 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_751 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_759 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_767 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_775 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_783 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_791 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_799 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_807 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_815 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_823 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_831 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_839 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_849 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_857 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_865 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_873 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_881 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_889 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_897 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_905 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_913 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_921 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_929 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_937 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_945 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_953 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_961 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_969 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_977 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_985 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_993 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1001 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1009 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1017 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1025 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1033 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1041 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1049 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1057 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1065 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1073 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1081 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1089 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1097 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1105 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1113 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1121 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1129 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1137 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1145 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1153 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1161 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1169 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1177 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1185 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1193 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1201 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1209 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1217 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1225 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1233 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1241 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1249 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1257 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1265 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1273 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1281 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1289 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1297 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1305 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1313 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1321 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1329 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1337 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1345 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1353 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_150 = |_out_rimask_T_150; // @[RegisterRouter.scala:87:24] wire out_wimask_150 = &_out_wimask_T_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_150 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_158 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_166 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_174 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_182 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_190 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_198 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_206 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_214 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_222 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_230 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_238 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_246 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_254 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_262 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_270 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_278 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_286 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_294 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_302 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_310 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_318 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_326 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_334 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_342 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_350 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_358 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_366 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_374 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_382 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_390 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_398 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_406 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_414 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_422 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_430 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_438 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_446 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_454 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_462 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_470 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_478 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_486 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_494 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_504 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_512 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_520 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_528 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_536 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_544 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_552 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_560 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_568 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_576 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_584 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_593 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_601 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_609 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_617 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_625 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_637 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_645 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_653 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_661 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_669 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_677 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_687 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_695 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_703 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_711 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_719 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_727 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_735 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_743 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_751 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_759 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_767 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_775 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_783 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_791 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_799 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_807 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_815 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_823 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_831 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_839 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_849 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_857 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_865 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_873 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_881 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_889 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_897 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_905 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_913 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_921 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_929 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_937 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_945 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_953 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_961 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_969 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_977 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_985 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_993 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1001 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1009 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1017 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1025 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1033 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1041 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1049 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1057 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1065 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1073 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1081 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1089 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1097 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1105 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1113 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1121 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1129 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1137 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1145 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1153 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1161 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1169 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1177 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1185 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1193 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1201 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1209 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1217 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1225 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1233 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1241 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1249 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1257 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1265 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1273 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1281 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1289 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1297 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1305 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1313 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1321 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1329 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1337 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1345 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1353 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_150 = |_out_romask_T_150; // @[RegisterRouter.scala:87:24] wire out_womask_150 = &_out_womask_T_150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_150 = out_rivalid_1_4 & out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1947 = out_f_rivalid_150; // @[RegisterRouter.scala:87:24] wire out_f_roready_150 = out_roready_1_4 & out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1948 = out_f_roready_150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_150 = out_wivalid_1_4 & out_wimask_150; // @[RegisterRouter.scala:87:24] wire out_f_woready_150 = out_woready_1_4 & out_womask_150; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2162 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2242 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2322 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2394 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2466 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2538 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2610 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2682 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2754 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2826 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2898 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2978 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3058 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3130 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3202 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3274 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3346 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3418 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3490 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3562 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3634 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3714 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3794 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3866 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3938 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4010 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4082 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4154 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4226 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4298 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4370 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4442 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4514 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4586 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4658 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4730 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4802 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4874 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4946 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5018 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5090 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5180 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5252 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5324 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5396 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5468 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5540 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5612 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5684 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5756 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5828 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5900 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6393 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6465 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6537 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6617 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6697 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6769 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6859 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6931 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7003 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7075 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7147 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7219 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7291 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7363 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7435 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7507 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7579 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7651 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7723 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7795 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7867 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7947 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8027 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8099 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8171 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8243 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8333 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8405 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8477 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8549 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8629 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8925 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8997 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9069 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9141 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9213 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9285 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9357 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9429 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9509 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9589 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9661 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9733 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9805 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9877 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9949 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10021 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10093 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10165 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10237 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10309 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10381 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10461 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10541 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10613 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10685 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10757 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10829 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10909 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10989 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11061 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11133 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11205 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11277 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11349 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11421 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11493 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11565 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11637 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11709 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11781 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11853 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11933 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12013 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12085 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12157 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12229 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12301 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12373 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12445 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12517 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12597 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12677 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12749 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12821 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12893 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12965 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_1949 = ~out_rimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1950 = ~out_wimask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1951 = ~out_romask_150; // @[RegisterRouter.scala:87:24] wire _out_T_1952 = ~out_womask_150; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_115 = {hi_85, flags_0_go, _out_prepend_T_115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1953 = out_prepend_115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_1954 = _out_T_1953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_116 = _out_T_1954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_151 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_159 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_167 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_175 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_183 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_191 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_199 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_207 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_215 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_223 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_231 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_239 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_247 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_255 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_263 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_271 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_279 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_287 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_295 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_303 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_311 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_319 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_327 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_335 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_343 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_351 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_359 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_367 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_375 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_383 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_391 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_399 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_407 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_415 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_423 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_431 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_439 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_447 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_455 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_463 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_471 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_479 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_487 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_495 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_505 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_513 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_521 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_529 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_537 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_545 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_553 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_561 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_569 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_577 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_585 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_594 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_602 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_610 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_618 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_626 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_638 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_646 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_654 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_662 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_670 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_678 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_688 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_696 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_704 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_712 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_720 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_728 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_736 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_744 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_752 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_760 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_768 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_776 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_784 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_792 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_800 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_808 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_816 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_824 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_832 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_840 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_850 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_858 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_866 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_874 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_882 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_890 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_898 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_906 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_914 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_922 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_930 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_938 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_946 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_954 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_962 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_970 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_978 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_986 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_994 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1002 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1010 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1018 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1026 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1034 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1042 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1050 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1058 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1066 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1074 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1082 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1090 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1098 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1106 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1114 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1122 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1130 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1138 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1146 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1154 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1162 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1170 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1178 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1186 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1194 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1202 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1210 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1218 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1226 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1234 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1242 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1250 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1258 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1266 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1274 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1282 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1290 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1298 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1306 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1314 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1322 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1330 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1338 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1346 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1354 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_151 = |_out_rimask_T_151; // @[RegisterRouter.scala:87:24] wire out_wimask_151 = &_out_wimask_T_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_151 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_159 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_167 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_175 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_183 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_191 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_199 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_207 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_215 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_223 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_231 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_239 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_247 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_255 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_263 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_271 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_279 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_287 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_295 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_303 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_311 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_319 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_327 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_335 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_343 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_351 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_359 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_367 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_375 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_383 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_391 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_399 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_407 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_415 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_423 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_431 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_439 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_447 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_455 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_463 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_471 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_479 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_487 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_495 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_505 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_513 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_521 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_529 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_537 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_545 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_553 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_561 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_569 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_577 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_585 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_594 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_602 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_610 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_618 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_626 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_638 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_646 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_654 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_662 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_670 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_678 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_688 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_696 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_704 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_712 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_720 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_728 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_736 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_744 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_752 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_760 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_768 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_776 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_784 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_792 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_800 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_808 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_816 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_824 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_832 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_840 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_850 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_858 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_866 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_874 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_882 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_890 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_898 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_906 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_914 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_922 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_930 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_938 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_946 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_954 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_962 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_970 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_978 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_986 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_994 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1002 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1010 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1018 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1026 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1034 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1042 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1050 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1058 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1066 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1074 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1082 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1090 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1098 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1106 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1114 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1122 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1130 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1138 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1146 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1154 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1162 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1170 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1178 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1186 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1194 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1202 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1210 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1218 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1226 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1234 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1242 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1250 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1258 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1266 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1274 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1282 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1290 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1298 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1306 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1314 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1322 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1330 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1338 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1346 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1354 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_151 = |_out_romask_T_151; // @[RegisterRouter.scala:87:24] wire out_womask_151 = &_out_womask_T_151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_151 = out_rivalid_1_5 & out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1956 = out_f_rivalid_151; // @[RegisterRouter.scala:87:24] wire out_f_roready_151 = out_roready_1_5 & out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1957 = out_f_roready_151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_151 = out_wivalid_1_5 & out_wimask_151; // @[RegisterRouter.scala:87:24] wire out_f_woready_151 = out_woready_1_5 & out_womask_151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2171 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2253 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2331 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2403 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2475 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2547 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2619 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2691 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2763 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2835 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2907 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2989 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3067 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3139 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3211 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3283 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3355 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3427 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3499 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3571 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3643 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3725 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3803 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3875 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3947 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4019 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4091 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4163 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4235 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4307 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4379 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4451 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4523 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4595 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4667 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4739 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4811 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4883 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4955 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5027 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5099 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5189 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5261 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5333 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5405 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5477 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5549 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5621 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5693 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5765 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5837 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5909 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6000 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6402 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6474 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6546 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6628 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6706 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6778 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6868 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6940 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7012 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7084 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7156 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7228 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7300 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7372 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7444 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7516 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7588 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7660 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7732 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7804 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7876 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8036 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8108 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8180 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8252 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8342 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8414 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8486 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8558 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8640 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8934 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9006 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9078 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9150 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9222 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9294 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9366 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9438 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9520 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9598 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9670 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9742 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9814 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9886 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9958 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10030 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10102 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10174 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10246 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10318 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10390 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10472 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10550 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10622 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10694 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10766 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10838 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10920 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10998 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11070 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11142 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11214 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11286 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11358 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11430 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11502 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11574 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11646 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11718 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11790 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11862 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11944 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12022 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12094 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12166 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12238 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12310 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12382 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12454 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12526 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12608 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12686 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12758 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12830 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12902 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12974 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire _out_T_1958 = ~out_rimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1959 = ~out_wimask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1960 = ~out_romask_151; // @[RegisterRouter.scala:87:24] wire _out_T_1961 = ~out_womask_151; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_116 = {hi_86, flags_0_go, _out_prepend_T_116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1962 = out_prepend_116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_1963 = _out_T_1962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_117 = _out_T_1963; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_152 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_160 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_168 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_176 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_184 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_192 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_200 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_208 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_216 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_224 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_232 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_240 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_248 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_256 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_264 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_272 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_280 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_288 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_296 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_304 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_312 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_320 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_328 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_336 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_344 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_352 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_360 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_368 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_376 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_384 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_392 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_400 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_408 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_416 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_424 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_432 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_440 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_448 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_456 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_464 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_472 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_480 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_488 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_496 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_506 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_514 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_522 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_530 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_538 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_546 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_554 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_562 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_570 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_578 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_586 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_595 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_603 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_611 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_619 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_627 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_639 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_647 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_655 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_663 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_671 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_679 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_689 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_697 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_705 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_713 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_721 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_729 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_737 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_745 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_753 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_761 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_769 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_777 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_785 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_793 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_801 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_809 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_817 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_825 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_833 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_841 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_851 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_859 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_867 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_875 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_883 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_891 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_899 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_907 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_915 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_923 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_931 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_939 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_947 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_955 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_963 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_971 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_979 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_987 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_995 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1003 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1011 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1019 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1027 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1035 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1043 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1051 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1059 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1067 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1075 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1083 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1091 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1099 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1107 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1115 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1123 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1131 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1139 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1147 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1155 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1163 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1171 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1179 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1187 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1195 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1203 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1211 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1219 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1227 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1235 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1243 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1251 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1259 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1267 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1275 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1283 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1291 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1299 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1307 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1315 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1323 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1331 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1339 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1347 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1355 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_152 = |_out_rimask_T_152; // @[RegisterRouter.scala:87:24] wire out_wimask_152 = &_out_wimask_T_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_152 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_160 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_168 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_176 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_184 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_192 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_200 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_208 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_216 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_224 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_232 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_240 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_248 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_256 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_264 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_272 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_280 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_288 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_296 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_304 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_312 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_320 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_328 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_336 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_344 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_352 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_360 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_368 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_376 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_384 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_392 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_400 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_408 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_416 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_424 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_432 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_440 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_448 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_456 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_464 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_472 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_480 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_488 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_496 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_506 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_514 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_522 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_530 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_538 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_546 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_554 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_562 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_570 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_578 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_586 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_595 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_603 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_611 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_619 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_627 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_639 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_647 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_655 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_663 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_671 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_679 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_689 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_697 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_705 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_713 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_721 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_729 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_737 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_745 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_753 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_761 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_769 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_777 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_785 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_793 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_801 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_809 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_817 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_825 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_833 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_841 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_851 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_859 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_867 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_875 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_883 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_891 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_899 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_907 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_915 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_923 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_931 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_939 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_947 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_955 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_963 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_971 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_979 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_987 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_995 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1003 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1011 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1019 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1027 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1035 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1043 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1051 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1059 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1067 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1075 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1083 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1091 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1099 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1107 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1115 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1123 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1131 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1139 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1147 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1155 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1163 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1171 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1179 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1187 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1195 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1203 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1211 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1219 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1227 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1235 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1243 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1251 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1259 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1267 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1275 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1283 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1291 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1299 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1307 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1315 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1323 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1331 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1339 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1347 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1355 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_152 = |_out_romask_T_152; // @[RegisterRouter.scala:87:24] wire out_womask_152 = &_out_womask_T_152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_152 = out_rivalid_1_6 & out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1965 = out_f_rivalid_152; // @[RegisterRouter.scala:87:24] wire out_f_roready_152 = out_roready_1_6 & out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1966 = out_f_roready_152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_152 = out_wivalid_1_6 & out_wimask_152; // @[RegisterRouter.scala:87:24] wire out_f_woready_152 = out_woready_1_6 & out_womask_152; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2180 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2264 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2340 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2412 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2484 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2556 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2628 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2700 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2772 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2844 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2916 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3000 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3076 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3148 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3220 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3292 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3364 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3436 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3508 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3580 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3652 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3736 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3812 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3884 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3956 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4028 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4100 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4172 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4244 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4316 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4388 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4460 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4532 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4604 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4676 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4748 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4820 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4892 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4964 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5036 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5108 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5198 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5270 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5342 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5414 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5486 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5558 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5630 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5702 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5774 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5846 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5918 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6011 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6411 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6555 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6639 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6715 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6787 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6877 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6949 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7021 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7093 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7165 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7237 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7309 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7381 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7453 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7525 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7597 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7669 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7741 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7813 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7885 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7969 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8045 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8117 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8189 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8261 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8351 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8423 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8495 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8567 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8651 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8943 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9015 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9087 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9159 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9303 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9375 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9447 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9531 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9607 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9679 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9751 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9823 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9895 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9967 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10039 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10111 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10183 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10255 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10327 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10399 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10483 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10559 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10631 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10703 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10775 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10847 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10931 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11007 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11079 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11151 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11223 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11295 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11367 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11439 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11511 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11583 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11655 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11727 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11799 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11871 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11955 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12031 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12103 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12175 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12247 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12319 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12391 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12463 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12535 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12619 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12695 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12767 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12839 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12911 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12983 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire _out_T_1967 = ~out_rimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1968 = ~out_wimask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1969 = ~out_romask_152; // @[RegisterRouter.scala:87:24] wire _out_T_1970 = ~out_womask_152; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_117 = {hi_87, flags_0_go, _out_prepend_T_117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1971 = out_prepend_117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_1972 = _out_T_1971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_118 = _out_T_1972; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_153 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_161 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_169 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_177 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_185 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_193 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_201 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_209 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_217 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_225 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_233 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_241 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_249 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_257 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_265 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_273 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_281 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_289 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_297 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_305 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_313 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_321 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_329 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_337 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_345 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_353 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_361 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_369 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_377 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_385 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_393 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_401 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_409 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_417 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_425 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_433 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_441 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_449 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_457 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_465 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_473 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_481 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_489 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_497 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_507 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_515 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_523 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_531 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_539 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_547 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_555 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_563 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_571 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_579 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_587 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_596 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_604 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_612 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_620 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_628 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_640 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_648 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_656 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_664 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_672 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_680 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_690 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_698 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_706 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_714 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_722 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_730 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_738 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_746 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_754 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_762 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_770 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_778 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_786 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_794 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_802 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_810 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_818 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_826 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_834 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_842 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_852 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_860 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_868 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_876 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_884 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_892 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_900 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_908 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_916 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_924 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_932 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_940 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_948 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_956 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_964 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_972 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_980 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_988 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_996 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1004 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1012 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1020 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1028 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1036 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1044 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1052 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1060 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1068 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1076 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1084 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1092 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1100 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1108 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1116 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1124 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1132 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1140 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1148 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1156 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1164 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1172 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1180 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1188 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1196 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1204 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1212 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1220 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1228 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1236 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1244 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1252 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1260 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1268 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1276 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1284 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1292 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1300 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1308 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1316 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1324 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1332 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1340 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1348 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1356 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_153 = |_out_rimask_T_153; // @[RegisterRouter.scala:87:24] wire out_wimask_153 = &_out_wimask_T_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_153 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_161 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_169 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_177 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_185 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_193 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_201 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_209 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_217 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_225 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_233 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_241 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_249 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_257 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_265 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_273 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_281 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_289 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_297 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_305 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_313 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_321 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_329 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_337 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_345 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_353 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_361 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_369 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_377 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_385 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_393 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_401 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_409 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_417 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_425 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_433 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_441 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_449 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_457 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_465 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_473 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_481 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_489 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_497 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_507 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_515 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_523 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_531 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_539 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_547 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_555 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_563 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_571 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_579 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_587 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_596 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_604 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_612 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_620 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_628 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_640 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_648 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_656 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_664 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_672 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_680 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_690 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_698 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_706 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_714 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_722 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_730 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_738 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_746 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_754 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_762 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_770 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_778 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_786 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_794 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_802 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_810 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_818 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_826 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_834 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_842 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_852 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_860 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_868 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_876 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_884 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_892 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_900 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_908 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_916 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_924 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_932 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_940 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_948 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_956 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_964 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_972 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_980 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_988 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_996 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1004 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1012 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1020 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1028 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1036 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1044 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1052 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1060 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1068 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1076 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1084 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1092 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1100 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1108 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1116 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1124 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1132 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1140 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1148 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1156 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1164 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1172 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1180 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1188 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1196 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1204 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1212 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1220 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1228 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1236 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1244 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1252 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1260 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1268 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1276 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1284 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1292 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1300 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1308 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1316 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1324 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1332 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1340 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1348 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1356 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_153 = |_out_romask_T_153; // @[RegisterRouter.scala:87:24] wire out_womask_153 = &_out_womask_T_153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_153 = out_rivalid_1_7 & out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1974 = out_f_rivalid_153; // @[RegisterRouter.scala:87:24] wire out_f_roready_153 = out_roready_1_7 & out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1975 = out_f_roready_153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_153 = out_wivalid_1_7 & out_wimask_153; // @[RegisterRouter.scala:87:24] wire out_f_woready_153 = out_woready_1_7 & out_womask_153; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2189 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2275 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2349 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2421 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2493 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2565 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2637 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2709 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2781 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2853 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2925 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3011 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3085 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3157 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3229 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3301 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3373 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3445 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3517 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3589 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3661 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3747 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3821 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3893 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3965 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4037 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4109 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4181 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4253 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4325 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4397 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4469 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4541 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4613 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4685 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4757 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4829 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4901 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4973 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5045 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5117 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5207 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5279 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5351 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5423 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5495 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5567 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5639 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5711 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5783 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5855 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5927 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6022 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6420 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6492 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6564 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6650 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6724 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6796 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6886 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6958 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7030 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7102 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7174 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7246 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7318 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7390 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7462 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7534 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7606 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7678 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7750 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7822 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7894 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7980 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8054 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8126 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8198 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8270 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8360 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8432 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8504 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8576 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8662 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8952 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9024 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9096 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9168 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9240 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9312 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9384 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9456 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9542 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9616 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9688 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9760 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9832 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9904 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9976 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10048 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10120 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10192 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10264 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10336 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10408 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10494 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10568 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10640 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10712 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10784 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10856 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10942 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11016 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11088 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11160 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11232 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11304 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11376 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11448 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11520 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11592 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11664 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11736 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11808 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11880 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11966 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12040 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12112 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12184 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12256 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12328 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12400 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12472 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12544 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12630 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12704 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12776 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12848 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12920 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12992 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire _out_T_1976 = ~out_rimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1977 = ~out_wimask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1978 = ~out_romask_153; // @[RegisterRouter.scala:87:24] wire _out_T_1979 = ~out_womask_153; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_118 = {hi_88, flags_0_go, _out_prepend_T_118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1980 = out_prepend_118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_1981 = _out_T_1980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_138 = _out_T_1981; // @[MuxLiteral.scala:49:48] wire out_rimask_154 = |_out_rimask_T_154; // @[RegisterRouter.scala:87:24] wire out_wimask_154 = &_out_wimask_T_154; // @[RegisterRouter.scala:87:24] wire out_romask_154 = |_out_romask_T_154; // @[RegisterRouter.scala:87:24] wire out_womask_154 = &_out_womask_T_154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_154 = out_rivalid_1_8 & out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1983 = out_f_rivalid_154; // @[RegisterRouter.scala:87:24] wire out_f_roready_154 = out_roready_1_8 & out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1984 = out_f_roready_154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_154 = out_wivalid_1_8 & out_wimask_154; // @[RegisterRouter.scala:87:24] wire out_f_woready_154 = out_woready_1_8 & out_womask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1985 = ~out_rimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1986 = ~out_wimask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1987 = ~out_romask_154; // @[RegisterRouter.scala:87:24] wire _out_T_1988 = ~out_womask_154; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_1990 = _out_T_1989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_119 = _out_T_1990; // @[RegisterRouter.scala:87:24] wire out_rimask_155 = |_out_rimask_T_155; // @[RegisterRouter.scala:87:24] wire out_wimask_155 = &_out_wimask_T_155; // @[RegisterRouter.scala:87:24] wire out_romask_155 = |_out_romask_T_155; // @[RegisterRouter.scala:87:24] wire out_womask_155 = &_out_womask_T_155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_155 = out_rivalid_1_9 & out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1992 = out_f_rivalid_155; // @[RegisterRouter.scala:87:24] wire out_f_roready_155 = out_roready_1_9 & out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1993 = out_f_roready_155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_155 = out_wivalid_1_9 & out_wimask_155; // @[RegisterRouter.scala:87:24] wire out_f_woready_155 = out_woready_1_9 & out_womask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1994 = ~out_rimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1995 = ~out_wimask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1996 = ~out_romask_155; // @[RegisterRouter.scala:87:24] wire _out_T_1997 = ~out_womask_155; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_119 = {hi_970, flags_0_go, _out_prepend_T_119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1998 = out_prepend_119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_1999 = _out_T_1998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_120 = _out_T_1999; // @[RegisterRouter.scala:87:24] wire out_rimask_156 = |_out_rimask_T_156; // @[RegisterRouter.scala:87:24] wire out_wimask_156 = &_out_wimask_T_156; // @[RegisterRouter.scala:87:24] wire out_romask_156 = |_out_romask_T_156; // @[RegisterRouter.scala:87:24] wire out_womask_156 = &_out_womask_T_156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_156 = out_rivalid_1_10 & out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2001 = out_f_rivalid_156; // @[RegisterRouter.scala:87:24] wire out_f_roready_156 = out_roready_1_10 & out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2002 = out_f_roready_156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_156 = out_wivalid_1_10 & out_wimask_156; // @[RegisterRouter.scala:87:24] wire out_f_woready_156 = out_woready_1_10 & out_womask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2003 = ~out_rimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2004 = ~out_wimask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2005 = ~out_romask_156; // @[RegisterRouter.scala:87:24] wire _out_T_2006 = ~out_womask_156; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_120 = {hi_971, flags_0_go, _out_prepend_T_120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2007 = out_prepend_120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2008 = _out_T_2007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_121 = _out_T_2008; // @[RegisterRouter.scala:87:24] wire out_rimask_157 = |_out_rimask_T_157; // @[RegisterRouter.scala:87:24] wire out_wimask_157 = &_out_wimask_T_157; // @[RegisterRouter.scala:87:24] wire out_romask_157 = |_out_romask_T_157; // @[RegisterRouter.scala:87:24] wire out_womask_157 = &_out_womask_T_157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_157 = out_rivalid_1_11 & out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2010 = out_f_rivalid_157; // @[RegisterRouter.scala:87:24] wire out_f_roready_157 = out_roready_1_11 & out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2011 = out_f_roready_157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_157 = out_wivalid_1_11 & out_wimask_157; // @[RegisterRouter.scala:87:24] wire out_f_woready_157 = out_woready_1_11 & out_womask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2012 = ~out_rimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2013 = ~out_wimask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2014 = ~out_romask_157; // @[RegisterRouter.scala:87:24] wire _out_T_2015 = ~out_womask_157; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_121 = {hi_972, flags_0_go, _out_prepend_T_121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2016 = out_prepend_121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2017 = _out_T_2016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_122 = _out_T_2017; // @[RegisterRouter.scala:87:24] wire out_rimask_158 = |_out_rimask_T_158; // @[RegisterRouter.scala:87:24] wire out_wimask_158 = &_out_wimask_T_158; // @[RegisterRouter.scala:87:24] wire out_romask_158 = |_out_romask_T_158; // @[RegisterRouter.scala:87:24] wire out_womask_158 = &_out_womask_T_158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_158 = out_rivalid_1_12 & out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2019 = out_f_rivalid_158; // @[RegisterRouter.scala:87:24] wire out_f_roready_158 = out_roready_1_12 & out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2020 = out_f_roready_158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_158 = out_wivalid_1_12 & out_wimask_158; // @[RegisterRouter.scala:87:24] wire out_f_woready_158 = out_woready_1_12 & out_womask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2021 = ~out_rimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2022 = ~out_wimask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2023 = ~out_romask_158; // @[RegisterRouter.scala:87:24] wire _out_T_2024 = ~out_womask_158; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_122 = {hi_973, flags_0_go, _out_prepend_T_122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2025 = out_prepend_122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2026 = _out_T_2025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_123 = _out_T_2026; // @[RegisterRouter.scala:87:24] wire out_rimask_159 = |_out_rimask_T_159; // @[RegisterRouter.scala:87:24] wire out_wimask_159 = &_out_wimask_T_159; // @[RegisterRouter.scala:87:24] wire out_romask_159 = |_out_romask_T_159; // @[RegisterRouter.scala:87:24] wire out_womask_159 = &_out_womask_T_159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_159 = out_rivalid_1_13 & out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2028 = out_f_rivalid_159; // @[RegisterRouter.scala:87:24] wire out_f_roready_159 = out_roready_1_13 & out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2029 = out_f_roready_159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_159 = out_wivalid_1_13 & out_wimask_159; // @[RegisterRouter.scala:87:24] wire out_f_woready_159 = out_woready_1_13 & out_womask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2030 = ~out_rimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2031 = ~out_wimask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2032 = ~out_romask_159; // @[RegisterRouter.scala:87:24] wire _out_T_2033 = ~out_womask_159; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_123 = {hi_974, flags_0_go, _out_prepend_T_123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2034 = out_prepend_123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2035 = _out_T_2034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_124 = _out_T_2035; // @[RegisterRouter.scala:87:24] wire out_rimask_160 = |_out_rimask_T_160; // @[RegisterRouter.scala:87:24] wire out_wimask_160 = &_out_wimask_T_160; // @[RegisterRouter.scala:87:24] wire out_romask_160 = |_out_romask_T_160; // @[RegisterRouter.scala:87:24] wire out_womask_160 = &_out_womask_T_160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_160 = out_rivalid_1_14 & out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2037 = out_f_rivalid_160; // @[RegisterRouter.scala:87:24] wire out_f_roready_160 = out_roready_1_14 & out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2038 = out_f_roready_160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_160 = out_wivalid_1_14 & out_wimask_160; // @[RegisterRouter.scala:87:24] wire out_f_woready_160 = out_woready_1_14 & out_womask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2039 = ~out_rimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2040 = ~out_wimask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2041 = ~out_romask_160; // @[RegisterRouter.scala:87:24] wire _out_T_2042 = ~out_womask_160; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_124 = {hi_975, flags_0_go, _out_prepend_T_124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2043 = out_prepend_124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2044 = _out_T_2043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_125 = _out_T_2044; // @[RegisterRouter.scala:87:24] wire out_rimask_161 = |_out_rimask_T_161; // @[RegisterRouter.scala:87:24] wire out_wimask_161 = &_out_wimask_T_161; // @[RegisterRouter.scala:87:24] wire out_romask_161 = |_out_romask_T_161; // @[RegisterRouter.scala:87:24] wire out_womask_161 = &_out_womask_T_161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_161 = out_rivalid_1_15 & out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2046 = out_f_rivalid_161; // @[RegisterRouter.scala:87:24] wire out_f_roready_161 = out_roready_1_15 & out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2047 = out_f_roready_161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_161 = out_wivalid_1_15 & out_wimask_161; // @[RegisterRouter.scala:87:24] wire out_f_woready_161 = out_woready_1_15 & out_womask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2048 = ~out_rimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2049 = ~out_wimask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2050 = ~out_romask_161; // @[RegisterRouter.scala:87:24] wire _out_T_2051 = ~out_womask_161; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_125 = {hi_976, flags_0_go, _out_prepend_T_125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2052 = out_prepend_125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2053 = _out_T_2052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_249 = _out_T_2053; // @[MuxLiteral.scala:49:48] wire out_rimask_162 = |_out_rimask_T_162; // @[RegisterRouter.scala:87:24] wire out_wimask_162 = &_out_wimask_T_162; // @[RegisterRouter.scala:87:24] wire out_romask_162 = |_out_romask_T_162; // @[RegisterRouter.scala:87:24] wire out_womask_162 = &_out_womask_T_162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_162 = out_rivalid_1_16 & out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2055 = out_f_rivalid_162; // @[RegisterRouter.scala:87:24] wire out_f_roready_162 = out_roready_1_16 & out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2056 = out_f_roready_162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_162 = out_wivalid_1_16 & out_wimask_162; // @[RegisterRouter.scala:87:24] wire out_f_woready_162 = out_woready_1_16 & out_womask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2057 = ~out_rimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2058 = ~out_wimask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2059 = ~out_romask_162; // @[RegisterRouter.scala:87:24] wire _out_T_2060 = ~out_womask_162; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2062 = _out_T_2061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_126 = _out_T_2062; // @[RegisterRouter.scala:87:24] wire out_rimask_163 = |_out_rimask_T_163; // @[RegisterRouter.scala:87:24] wire out_wimask_163 = &_out_wimask_T_163; // @[RegisterRouter.scala:87:24] wire out_romask_163 = |_out_romask_T_163; // @[RegisterRouter.scala:87:24] wire out_womask_163 = &_out_womask_T_163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_163 = out_rivalid_1_17 & out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2064 = out_f_rivalid_163; // @[RegisterRouter.scala:87:24] wire out_f_roready_163 = out_roready_1_17 & out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2065 = out_f_roready_163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_163 = out_wivalid_1_17 & out_wimask_163; // @[RegisterRouter.scala:87:24] wire out_f_woready_163 = out_woready_1_17 & out_womask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2066 = ~out_rimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2067 = ~out_wimask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2068 = ~out_romask_163; // @[RegisterRouter.scala:87:24] wire _out_T_2069 = ~out_womask_163; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_126 = {hi_850, flags_0_go, _out_prepend_T_126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2070 = out_prepend_126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2071 = _out_T_2070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_127 = _out_T_2071; // @[RegisterRouter.scala:87:24] wire out_rimask_164 = |_out_rimask_T_164; // @[RegisterRouter.scala:87:24] wire out_wimask_164 = &_out_wimask_T_164; // @[RegisterRouter.scala:87:24] wire out_romask_164 = |_out_romask_T_164; // @[RegisterRouter.scala:87:24] wire out_womask_164 = &_out_womask_T_164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_164 = out_rivalid_1_18 & out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2073 = out_f_rivalid_164; // @[RegisterRouter.scala:87:24] wire out_f_roready_164 = out_roready_1_18 & out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2074 = out_f_roready_164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_164 = out_wivalid_1_18 & out_wimask_164; // @[RegisterRouter.scala:87:24] wire out_f_woready_164 = out_woready_1_18 & out_womask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2075 = ~out_rimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2076 = ~out_wimask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2077 = ~out_romask_164; // @[RegisterRouter.scala:87:24] wire _out_T_2078 = ~out_womask_164; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_127 = {hi_851, flags_0_go, _out_prepend_T_127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2079 = out_prepend_127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2080 = _out_T_2079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_128 = _out_T_2080; // @[RegisterRouter.scala:87:24] wire out_rimask_165 = |_out_rimask_T_165; // @[RegisterRouter.scala:87:24] wire out_wimask_165 = &_out_wimask_T_165; // @[RegisterRouter.scala:87:24] wire out_romask_165 = |_out_romask_T_165; // @[RegisterRouter.scala:87:24] wire out_womask_165 = &_out_womask_T_165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_165 = out_rivalid_1_19 & out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2082 = out_f_rivalid_165; // @[RegisterRouter.scala:87:24] wire out_f_roready_165 = out_roready_1_19 & out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2083 = out_f_roready_165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_165 = out_wivalid_1_19 & out_wimask_165; // @[RegisterRouter.scala:87:24] wire out_f_woready_165 = out_woready_1_19 & out_womask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2084 = ~out_rimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2085 = ~out_wimask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2086 = ~out_romask_165; // @[RegisterRouter.scala:87:24] wire _out_T_2087 = ~out_womask_165; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_128 = {hi_852, flags_0_go, _out_prepend_T_128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2088 = out_prepend_128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2089 = _out_T_2088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_129 = _out_T_2089; // @[RegisterRouter.scala:87:24] wire out_rimask_166 = |_out_rimask_T_166; // @[RegisterRouter.scala:87:24] wire out_wimask_166 = &_out_wimask_T_166; // @[RegisterRouter.scala:87:24] wire out_romask_166 = |_out_romask_T_166; // @[RegisterRouter.scala:87:24] wire out_womask_166 = &_out_womask_T_166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_166 = out_rivalid_1_20 & out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2091 = out_f_rivalid_166; // @[RegisterRouter.scala:87:24] wire out_f_roready_166 = out_roready_1_20 & out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2092 = out_f_roready_166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_166 = out_wivalid_1_20 & out_wimask_166; // @[RegisterRouter.scala:87:24] wire out_f_woready_166 = out_woready_1_20 & out_womask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2093 = ~out_rimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2094 = ~out_wimask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2095 = ~out_romask_166; // @[RegisterRouter.scala:87:24] wire _out_T_2096 = ~out_womask_166; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_129 = {hi_853, flags_0_go, _out_prepend_T_129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2097 = out_prepend_129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2098 = _out_T_2097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_130 = _out_T_2098; // @[RegisterRouter.scala:87:24] wire out_rimask_167 = |_out_rimask_T_167; // @[RegisterRouter.scala:87:24] wire out_wimask_167 = &_out_wimask_T_167; // @[RegisterRouter.scala:87:24] wire out_romask_167 = |_out_romask_T_167; // @[RegisterRouter.scala:87:24] wire out_womask_167 = &_out_womask_T_167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_167 = out_rivalid_1_21 & out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2100 = out_f_rivalid_167; // @[RegisterRouter.scala:87:24] wire out_f_roready_167 = out_roready_1_21 & out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2101 = out_f_roready_167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_167 = out_wivalid_1_21 & out_wimask_167; // @[RegisterRouter.scala:87:24] wire out_f_woready_167 = out_woready_1_21 & out_womask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2102 = ~out_rimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2103 = ~out_wimask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2104 = ~out_romask_167; // @[RegisterRouter.scala:87:24] wire _out_T_2105 = ~out_womask_167; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_130 = {hi_854, flags_0_go, _out_prepend_T_130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2106 = out_prepend_130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2107 = _out_T_2106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_131 = _out_T_2107; // @[RegisterRouter.scala:87:24] wire out_rimask_168 = |_out_rimask_T_168; // @[RegisterRouter.scala:87:24] wire out_wimask_168 = &_out_wimask_T_168; // @[RegisterRouter.scala:87:24] wire out_romask_168 = |_out_romask_T_168; // @[RegisterRouter.scala:87:24] wire out_womask_168 = &_out_womask_T_168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_168 = out_rivalid_1_22 & out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2109 = out_f_rivalid_168; // @[RegisterRouter.scala:87:24] wire out_f_roready_168 = out_roready_1_22 & out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2110 = out_f_roready_168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_168 = out_wivalid_1_22 & out_wimask_168; // @[RegisterRouter.scala:87:24] wire out_f_woready_168 = out_woready_1_22 & out_womask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2111 = ~out_rimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2112 = ~out_wimask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2113 = ~out_romask_168; // @[RegisterRouter.scala:87:24] wire _out_T_2114 = ~out_womask_168; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_131 = {hi_855, flags_0_go, _out_prepend_T_131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2115 = out_prepend_131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2116 = _out_T_2115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_132 = _out_T_2116; // @[RegisterRouter.scala:87:24] wire out_rimask_169 = |_out_rimask_T_169; // @[RegisterRouter.scala:87:24] wire out_wimask_169 = &_out_wimask_T_169; // @[RegisterRouter.scala:87:24] wire out_romask_169 = |_out_romask_T_169; // @[RegisterRouter.scala:87:24] wire out_womask_169 = &_out_womask_T_169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_169 = out_rivalid_1_23 & out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2118 = out_f_rivalid_169; // @[RegisterRouter.scala:87:24] wire out_f_roready_169 = out_roready_1_23 & out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2119 = out_f_roready_169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_169 = out_wivalid_1_23 & out_wimask_169; // @[RegisterRouter.scala:87:24] wire out_f_woready_169 = out_woready_1_23 & out_womask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2120 = ~out_rimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2121 = ~out_wimask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2122 = ~out_romask_169; // @[RegisterRouter.scala:87:24] wire _out_T_2123 = ~out_womask_169; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_132 = {hi_856, flags_0_go, _out_prepend_T_132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2124 = out_prepend_132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2125 = _out_T_2124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_234 = _out_T_2125; // @[MuxLiteral.scala:49:48] wire out_rimask_170 = |_out_rimask_T_170; // @[RegisterRouter.scala:87:24] wire out_wimask_170 = &_out_wimask_T_170; // @[RegisterRouter.scala:87:24] wire out_romask_170 = |_out_romask_T_170; // @[RegisterRouter.scala:87:24] wire out_womask_170 = &_out_womask_T_170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_170 = out_rivalid_1_24 & out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2127 = out_f_rivalid_170; // @[RegisterRouter.scala:87:24] wire out_f_roready_170 = out_roready_1_24 & out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2128 = out_f_roready_170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_170 = out_wivalid_1_24 & out_wimask_170; // @[RegisterRouter.scala:87:24] wire out_f_woready_170 = out_woready_1_24 & out_womask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2129 = ~out_rimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2130 = ~out_wimask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2131 = ~out_romask_170; // @[RegisterRouter.scala:87:24] wire _out_T_2132 = ~out_womask_170; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2134 = _out_T_2133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_133 = _out_T_2134; // @[RegisterRouter.scala:87:24] wire out_rimask_171 = |_out_rimask_T_171; // @[RegisterRouter.scala:87:24] wire out_wimask_171 = &_out_wimask_T_171; // @[RegisterRouter.scala:87:24] wire out_romask_171 = |_out_romask_T_171; // @[RegisterRouter.scala:87:24] wire out_womask_171 = &_out_womask_T_171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_171 = out_rivalid_1_25 & out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2136 = out_f_rivalid_171; // @[RegisterRouter.scala:87:24] wire out_f_roready_171 = out_roready_1_25 & out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2137 = out_f_roready_171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_171 = out_wivalid_1_25 & out_wimask_171; // @[RegisterRouter.scala:87:24] wire out_f_woready_171 = out_woready_1_25 & out_womask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2138 = ~out_rimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2139 = ~out_wimask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2140 = ~out_romask_171; // @[RegisterRouter.scala:87:24] wire _out_T_2141 = ~out_womask_171; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_133 = {hi_338, flags_0_go, _out_prepend_T_133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2142 = out_prepend_133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2143 = _out_T_2142; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_134 = _out_T_2143; // @[RegisterRouter.scala:87:24] wire out_rimask_172 = |_out_rimask_T_172; // @[RegisterRouter.scala:87:24] wire out_wimask_172 = &_out_wimask_T_172; // @[RegisterRouter.scala:87:24] wire out_romask_172 = |_out_romask_T_172; // @[RegisterRouter.scala:87:24] wire out_womask_172 = &_out_womask_T_172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_172 = out_rivalid_1_26 & out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2145 = out_f_rivalid_172; // @[RegisterRouter.scala:87:24] wire out_f_roready_172 = out_roready_1_26 & out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2146 = out_f_roready_172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_172 = out_wivalid_1_26 & out_wimask_172; // @[RegisterRouter.scala:87:24] wire out_f_woready_172 = out_woready_1_26 & out_womask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2147 = ~out_rimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2148 = ~out_wimask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2149 = ~out_romask_172; // @[RegisterRouter.scala:87:24] wire _out_T_2150 = ~out_womask_172; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_134 = {hi_339, flags_0_go, _out_prepend_T_134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2151 = out_prepend_134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2152 = _out_T_2151; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_135 = _out_T_2152; // @[RegisterRouter.scala:87:24] wire out_rimask_173 = |_out_rimask_T_173; // @[RegisterRouter.scala:87:24] wire out_wimask_173 = &_out_wimask_T_173; // @[RegisterRouter.scala:87:24] wire out_romask_173 = |_out_romask_T_173; // @[RegisterRouter.scala:87:24] wire out_womask_173 = &_out_womask_T_173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_173 = out_rivalid_1_27 & out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2154 = out_f_rivalid_173; // @[RegisterRouter.scala:87:24] wire out_f_roready_173 = out_roready_1_27 & out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2155 = out_f_roready_173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_173 = out_wivalid_1_27 & out_wimask_173; // @[RegisterRouter.scala:87:24] wire out_f_woready_173 = out_woready_1_27 & out_womask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2156 = ~out_rimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2157 = ~out_wimask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2158 = ~out_romask_173; // @[RegisterRouter.scala:87:24] wire _out_T_2159 = ~out_womask_173; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_135 = {hi_340, flags_0_go, _out_prepend_T_135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2160 = out_prepend_135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2161 = _out_T_2160; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_136 = _out_T_2161; // @[RegisterRouter.scala:87:24] wire out_rimask_174 = |_out_rimask_T_174; // @[RegisterRouter.scala:87:24] wire out_wimask_174 = &_out_wimask_T_174; // @[RegisterRouter.scala:87:24] wire out_romask_174 = |_out_romask_T_174; // @[RegisterRouter.scala:87:24] wire out_womask_174 = &_out_womask_T_174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_174 = out_rivalid_1_28 & out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2163 = out_f_rivalid_174; // @[RegisterRouter.scala:87:24] wire out_f_roready_174 = out_roready_1_28 & out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2164 = out_f_roready_174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_174 = out_wivalid_1_28 & out_wimask_174; // @[RegisterRouter.scala:87:24] wire out_f_woready_174 = out_woready_1_28 & out_womask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2165 = ~out_rimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2166 = ~out_wimask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2167 = ~out_romask_174; // @[RegisterRouter.scala:87:24] wire _out_T_2168 = ~out_womask_174; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_136 = {hi_341, flags_0_go, _out_prepend_T_136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2169 = out_prepend_136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2170 = _out_T_2169; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_137 = _out_T_2170; // @[RegisterRouter.scala:87:24] wire out_rimask_175 = |_out_rimask_T_175; // @[RegisterRouter.scala:87:24] wire out_wimask_175 = &_out_wimask_T_175; // @[RegisterRouter.scala:87:24] wire out_romask_175 = |_out_romask_T_175; // @[RegisterRouter.scala:87:24] wire out_womask_175 = &_out_womask_T_175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_175 = out_rivalid_1_29 & out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2172 = out_f_rivalid_175; // @[RegisterRouter.scala:87:24] wire out_f_roready_175 = out_roready_1_29 & out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2173 = out_f_roready_175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_175 = out_wivalid_1_29 & out_wimask_175; // @[RegisterRouter.scala:87:24] wire out_f_woready_175 = out_woready_1_29 & out_womask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2174 = ~out_rimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2175 = ~out_wimask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2176 = ~out_romask_175; // @[RegisterRouter.scala:87:24] wire _out_T_2177 = ~out_womask_175; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_137 = {hi_342, flags_0_go, _out_prepend_T_137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2178 = out_prepend_137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2179 = _out_T_2178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_138 = _out_T_2179; // @[RegisterRouter.scala:87:24] wire out_rimask_176 = |_out_rimask_T_176; // @[RegisterRouter.scala:87:24] wire out_wimask_176 = &_out_wimask_T_176; // @[RegisterRouter.scala:87:24] wire out_romask_176 = |_out_romask_T_176; // @[RegisterRouter.scala:87:24] wire out_womask_176 = &_out_womask_T_176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_176 = out_rivalid_1_30 & out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2181 = out_f_rivalid_176; // @[RegisterRouter.scala:87:24] wire out_f_roready_176 = out_roready_1_30 & out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2182 = out_f_roready_176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_176 = out_wivalid_1_30 & out_wimask_176; // @[RegisterRouter.scala:87:24] wire out_f_woready_176 = out_woready_1_30 & out_womask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2183 = ~out_rimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2184 = ~out_wimask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2185 = ~out_romask_176; // @[RegisterRouter.scala:87:24] wire _out_T_2186 = ~out_womask_176; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_138 = {hi_343, flags_0_go, _out_prepend_T_138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2187 = out_prepend_138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2188 = _out_T_2187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_139 = _out_T_2188; // @[RegisterRouter.scala:87:24] wire out_rimask_177 = |_out_rimask_T_177; // @[RegisterRouter.scala:87:24] wire out_wimask_177 = &_out_wimask_T_177; // @[RegisterRouter.scala:87:24] wire out_romask_177 = |_out_romask_T_177; // @[RegisterRouter.scala:87:24] wire out_womask_177 = &_out_womask_T_177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_177 = out_rivalid_1_31 & out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2190 = out_f_rivalid_177; // @[RegisterRouter.scala:87:24] wire out_f_roready_177 = out_roready_1_31 & out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2191 = out_f_roready_177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_177 = out_wivalid_1_31 & out_wimask_177; // @[RegisterRouter.scala:87:24] wire out_f_woready_177 = out_woready_1_31 & out_womask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2192 = ~out_rimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2193 = ~out_wimask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2194 = ~out_romask_177; // @[RegisterRouter.scala:87:24] wire _out_T_2195 = ~out_womask_177; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_139 = {hi_344, flags_0_go, _out_prepend_T_139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2196 = out_prepend_139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2197 = _out_T_2196; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_170 = _out_T_2197; // @[MuxLiteral.scala:49:48] wire out_rimask_178 = |_out_rimask_T_178; // @[RegisterRouter.scala:87:24] wire out_wimask_178 = &_out_wimask_T_178; // @[RegisterRouter.scala:87:24] wire out_romask_178 = |_out_romask_T_178; // @[RegisterRouter.scala:87:24] wire out_womask_178 = &_out_womask_T_178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_178 = out_rivalid_1_32 & out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2199 = out_f_rivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_roready_178 = out_roready_1_32 & out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2200 = out_f_roready_178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_178 = out_wivalid_1_32 & out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2201 = out_f_wivalid_178; // @[RegisterRouter.scala:87:24] wire out_f_woready_178 = out_woready_1_32 & out_womask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2202 = out_f_woready_178; // @[RegisterRouter.scala:87:24] wire _out_T_2203 = ~out_rimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2204 = ~out_wimask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2205 = ~out_romask_178; // @[RegisterRouter.scala:87:24] wire _out_T_2206 = ~out_womask_178; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2208 = _out_T_2207; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_140 = _out_T_2208; // @[RegisterRouter.scala:87:24] wire out_rimask_179 = |_out_rimask_T_179; // @[RegisterRouter.scala:87:24] wire out_wimask_179 = &_out_wimask_T_179; // @[RegisterRouter.scala:87:24] wire out_romask_179 = |_out_romask_T_179; // @[RegisterRouter.scala:87:24] wire out_womask_179 = &_out_womask_T_179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_179 = out_rivalid_1_33 & out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2210 = out_f_rivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_roready_179 = out_roready_1_33 & out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2211 = out_f_roready_179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_179 = out_wivalid_1_33 & out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2212 = out_f_wivalid_179; // @[RegisterRouter.scala:87:24] wire out_f_woready_179 = out_woready_1_33 & out_womask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2213 = out_f_woready_179; // @[RegisterRouter.scala:87:24] wire _out_T_2214 = ~out_rimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2215 = ~out_wimask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2216 = ~out_romask_179; // @[RegisterRouter.scala:87:24] wire _out_T_2217 = ~out_womask_179; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_140 = {abstractDataMem_25, _out_prepend_T_140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2218 = out_prepend_140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2219 = _out_T_2218; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_141 = _out_T_2219; // @[RegisterRouter.scala:87:24] wire out_rimask_180 = |_out_rimask_T_180; // @[RegisterRouter.scala:87:24] wire out_wimask_180 = &_out_wimask_T_180; // @[RegisterRouter.scala:87:24] wire out_romask_180 = |_out_romask_T_180; // @[RegisterRouter.scala:87:24] wire out_womask_180 = &_out_womask_T_180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_180 = out_rivalid_1_34 & out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2221 = out_f_rivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_roready_180 = out_roready_1_34 & out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2222 = out_f_roready_180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_180 = out_wivalid_1_34 & out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2223 = out_f_wivalid_180; // @[RegisterRouter.scala:87:24] wire out_f_woready_180 = out_woready_1_34 & out_womask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2224 = out_f_woready_180; // @[RegisterRouter.scala:87:24] wire _out_T_2225 = ~out_rimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2226 = ~out_wimask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2227 = ~out_romask_180; // @[RegisterRouter.scala:87:24] wire _out_T_2228 = ~out_womask_180; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_141 = {abstractDataMem_26, _out_prepend_T_141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2229 = out_prepend_141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2230 = _out_T_2229; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_142 = _out_T_2230; // @[RegisterRouter.scala:87:24] wire out_rimask_181 = |_out_rimask_T_181; // @[RegisterRouter.scala:87:24] wire out_wimask_181 = &_out_wimask_T_181; // @[RegisterRouter.scala:87:24] wire out_romask_181 = |_out_romask_T_181; // @[RegisterRouter.scala:87:24] wire out_womask_181 = &_out_womask_T_181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_181 = out_rivalid_1_35 & out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2232 = out_f_rivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_roready_181 = out_roready_1_35 & out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2233 = out_f_roready_181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_181 = out_wivalid_1_35 & out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2234 = out_f_wivalid_181; // @[RegisterRouter.scala:87:24] wire out_f_woready_181 = out_woready_1_35 & out_womask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2235 = out_f_woready_181; // @[RegisterRouter.scala:87:24] wire _out_T_2236 = ~out_rimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2237 = ~out_wimask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2238 = ~out_romask_181; // @[RegisterRouter.scala:87:24] wire _out_T_2239 = ~out_womask_181; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_142 = {abstractDataMem_27, _out_prepend_T_142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2240 = out_prepend_142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2241 = _out_T_2240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_143 = _out_T_2241; // @[RegisterRouter.scala:87:24] wire out_rimask_182 = |_out_rimask_T_182; // @[RegisterRouter.scala:87:24] wire out_wimask_182 = &_out_wimask_T_182; // @[RegisterRouter.scala:87:24] wire out_romask_182 = |_out_romask_T_182; // @[RegisterRouter.scala:87:24] wire out_womask_182 = &_out_womask_T_182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_182 = out_rivalid_1_36 & out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2243 = out_f_rivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_roready_182 = out_roready_1_36 & out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2244 = out_f_roready_182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_182 = out_wivalid_1_36 & out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2245 = out_f_wivalid_182; // @[RegisterRouter.scala:87:24] wire out_f_woready_182 = out_woready_1_36 & out_womask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2246 = out_f_woready_182; // @[RegisterRouter.scala:87:24] wire _out_T_2247 = ~out_rimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2248 = ~out_wimask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2249 = ~out_romask_182; // @[RegisterRouter.scala:87:24] wire _out_T_2250 = ~out_womask_182; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_143 = {abstractDataMem_28, _out_prepend_T_143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2251 = out_prepend_143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2252 = _out_T_2251; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_144 = _out_T_2252; // @[RegisterRouter.scala:87:24] wire out_rimask_183 = |_out_rimask_T_183; // @[RegisterRouter.scala:87:24] wire out_wimask_183 = &_out_wimask_T_183; // @[RegisterRouter.scala:87:24] wire out_romask_183 = |_out_romask_T_183; // @[RegisterRouter.scala:87:24] wire out_womask_183 = &_out_womask_T_183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_183 = out_rivalid_1_37 & out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2254 = out_f_rivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_roready_183 = out_roready_1_37 & out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2255 = out_f_roready_183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_183 = out_wivalid_1_37 & out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2256 = out_f_wivalid_183; // @[RegisterRouter.scala:87:24] wire out_f_woready_183 = out_woready_1_37 & out_womask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2257 = out_f_woready_183; // @[RegisterRouter.scala:87:24] wire _out_T_2258 = ~out_rimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2259 = ~out_wimask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2260 = ~out_romask_183; // @[RegisterRouter.scala:87:24] wire _out_T_2261 = ~out_womask_183; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_144 = {abstractDataMem_29, _out_prepend_T_144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2262 = out_prepend_144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2263 = _out_T_2262; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_145 = _out_T_2263; // @[RegisterRouter.scala:87:24] wire out_rimask_184 = |_out_rimask_T_184; // @[RegisterRouter.scala:87:24] wire out_wimask_184 = &_out_wimask_T_184; // @[RegisterRouter.scala:87:24] wire out_romask_184 = |_out_romask_T_184; // @[RegisterRouter.scala:87:24] wire out_womask_184 = &_out_womask_T_184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_184 = out_rivalid_1_38 & out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2265 = out_f_rivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_roready_184 = out_roready_1_38 & out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2266 = out_f_roready_184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_184 = out_wivalid_1_38 & out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2267 = out_f_wivalid_184; // @[RegisterRouter.scala:87:24] wire out_f_woready_184 = out_woready_1_38 & out_womask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2268 = out_f_woready_184; // @[RegisterRouter.scala:87:24] wire _out_T_2269 = ~out_rimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2270 = ~out_wimask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2271 = ~out_romask_184; // @[RegisterRouter.scala:87:24] wire _out_T_2272 = ~out_womask_184; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_145 = {abstractDataMem_30, _out_prepend_T_145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2273 = out_prepend_145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2274 = _out_T_2273; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_146 = _out_T_2274; // @[RegisterRouter.scala:87:24] wire out_rimask_185 = |_out_rimask_T_185; // @[RegisterRouter.scala:87:24] wire out_wimask_185 = &_out_wimask_T_185; // @[RegisterRouter.scala:87:24] wire out_romask_185 = |_out_romask_T_185; // @[RegisterRouter.scala:87:24] wire out_womask_185 = &_out_womask_T_185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_185 = out_rivalid_1_39 & out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2276 = out_f_rivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_roready_185 = out_roready_1_39 & out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2277 = out_f_roready_185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_185 = out_wivalid_1_39 & out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2278 = out_f_wivalid_185; // @[RegisterRouter.scala:87:24] wire out_f_woready_185 = out_woready_1_39 & out_womask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2279 = out_f_woready_185; // @[RegisterRouter.scala:87:24] wire _out_T_2280 = ~out_rimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2281 = ~out_wimask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2282 = ~out_romask_185; // @[RegisterRouter.scala:87:24] wire _out_T_2283 = ~out_womask_185; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_146 = {abstractDataMem_31, _out_prepend_T_146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2284 = out_prepend_146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2285 = _out_T_2284; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_115 = _out_T_2285; // @[MuxLiteral.scala:49:48] wire out_rimask_186 = |_out_rimask_T_186; // @[RegisterRouter.scala:87:24] wire out_wimask_186 = &_out_wimask_T_186; // @[RegisterRouter.scala:87:24] wire out_romask_186 = |_out_romask_T_186; // @[RegisterRouter.scala:87:24] wire out_womask_186 = &_out_womask_T_186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_186 = out_rivalid_1_40 & out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2287 = out_f_rivalid_186; // @[RegisterRouter.scala:87:24] wire out_f_roready_186 = out_roready_1_40 & out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2288 = out_f_roready_186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_186 = out_wivalid_1_40 & out_wimask_186; // @[RegisterRouter.scala:87:24] wire out_f_woready_186 = out_woready_1_40 & out_womask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2289 = ~out_rimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2290 = ~out_wimask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2291 = ~out_romask_186; // @[RegisterRouter.scala:87:24] wire _out_T_2292 = ~out_womask_186; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2294 = _out_T_2293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_147 = _out_T_2294; // @[RegisterRouter.scala:87:24] wire out_rimask_187 = |_out_rimask_T_187; // @[RegisterRouter.scala:87:24] wire out_wimask_187 = &_out_wimask_T_187; // @[RegisterRouter.scala:87:24] wire out_romask_187 = |_out_romask_T_187; // @[RegisterRouter.scala:87:24] wire out_womask_187 = &_out_womask_T_187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_187 = out_rivalid_1_41 & out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2296 = out_f_rivalid_187; // @[RegisterRouter.scala:87:24] wire out_f_roready_187 = out_roready_1_41 & out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2297 = out_f_roready_187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_187 = out_wivalid_1_41 & out_wimask_187; // @[RegisterRouter.scala:87:24] wire out_f_woready_187 = out_woready_1_41 & out_womask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2298 = ~out_rimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2299 = ~out_wimask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2300 = ~out_romask_187; // @[RegisterRouter.scala:87:24] wire _out_T_2301 = ~out_womask_187; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_147 = {hi_714, flags_0_go, _out_prepend_T_147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2302 = out_prepend_147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2303 = _out_T_2302; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_148 = _out_T_2303; // @[RegisterRouter.scala:87:24] wire out_rimask_188 = |_out_rimask_T_188; // @[RegisterRouter.scala:87:24] wire out_wimask_188 = &_out_wimask_T_188; // @[RegisterRouter.scala:87:24] wire out_romask_188 = |_out_romask_T_188; // @[RegisterRouter.scala:87:24] wire out_womask_188 = &_out_womask_T_188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_188 = out_rivalid_1_42 & out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2305 = out_f_rivalid_188; // @[RegisterRouter.scala:87:24] wire out_f_roready_188 = out_roready_1_42 & out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2306 = out_f_roready_188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_188 = out_wivalid_1_42 & out_wimask_188; // @[RegisterRouter.scala:87:24] wire out_f_woready_188 = out_woready_1_42 & out_womask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2307 = ~out_rimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2308 = ~out_wimask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2309 = ~out_romask_188; // @[RegisterRouter.scala:87:24] wire _out_T_2310 = ~out_womask_188; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_148 = {hi_715, flags_0_go, _out_prepend_T_148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2311 = out_prepend_148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2312 = _out_T_2311; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_149 = _out_T_2312; // @[RegisterRouter.scala:87:24] wire out_rimask_189 = |_out_rimask_T_189; // @[RegisterRouter.scala:87:24] wire out_wimask_189 = &_out_wimask_T_189; // @[RegisterRouter.scala:87:24] wire out_romask_189 = |_out_romask_T_189; // @[RegisterRouter.scala:87:24] wire out_womask_189 = &_out_womask_T_189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_189 = out_rivalid_1_43 & out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2314 = out_f_rivalid_189; // @[RegisterRouter.scala:87:24] wire out_f_roready_189 = out_roready_1_43 & out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2315 = out_f_roready_189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_189 = out_wivalid_1_43 & out_wimask_189; // @[RegisterRouter.scala:87:24] wire out_f_woready_189 = out_woready_1_43 & out_womask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2316 = ~out_rimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2317 = ~out_wimask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2318 = ~out_romask_189; // @[RegisterRouter.scala:87:24] wire _out_T_2319 = ~out_womask_189; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_149 = {hi_716, flags_0_go, _out_prepend_T_149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2320 = out_prepend_149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2321 = _out_T_2320; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_150 = _out_T_2321; // @[RegisterRouter.scala:87:24] wire out_rimask_190 = |_out_rimask_T_190; // @[RegisterRouter.scala:87:24] wire out_wimask_190 = &_out_wimask_T_190; // @[RegisterRouter.scala:87:24] wire out_romask_190 = |_out_romask_T_190; // @[RegisterRouter.scala:87:24] wire out_womask_190 = &_out_womask_T_190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_190 = out_rivalid_1_44 & out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2323 = out_f_rivalid_190; // @[RegisterRouter.scala:87:24] wire out_f_roready_190 = out_roready_1_44 & out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2324 = out_f_roready_190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_190 = out_wivalid_1_44 & out_wimask_190; // @[RegisterRouter.scala:87:24] wire out_f_woready_190 = out_woready_1_44 & out_womask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2325 = ~out_rimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2326 = ~out_wimask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2327 = ~out_romask_190; // @[RegisterRouter.scala:87:24] wire _out_T_2328 = ~out_womask_190; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_150 = {hi_717, flags_0_go, _out_prepend_T_150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2329 = out_prepend_150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2330 = _out_T_2329; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_151 = _out_T_2330; // @[RegisterRouter.scala:87:24] wire out_rimask_191 = |_out_rimask_T_191; // @[RegisterRouter.scala:87:24] wire out_wimask_191 = &_out_wimask_T_191; // @[RegisterRouter.scala:87:24] wire out_romask_191 = |_out_romask_T_191; // @[RegisterRouter.scala:87:24] wire out_womask_191 = &_out_womask_T_191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_191 = out_rivalid_1_45 & out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2332 = out_f_rivalid_191; // @[RegisterRouter.scala:87:24] wire out_f_roready_191 = out_roready_1_45 & out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2333 = out_f_roready_191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_191 = out_wivalid_1_45 & out_wimask_191; // @[RegisterRouter.scala:87:24] wire out_f_woready_191 = out_woready_1_45 & out_womask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2334 = ~out_rimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2335 = ~out_wimask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2336 = ~out_romask_191; // @[RegisterRouter.scala:87:24] wire _out_T_2337 = ~out_womask_191; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_151 = {hi_718, flags_0_go, _out_prepend_T_151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2338 = out_prepend_151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2339 = _out_T_2338; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_152 = _out_T_2339; // @[RegisterRouter.scala:87:24] wire out_rimask_192 = |_out_rimask_T_192; // @[RegisterRouter.scala:87:24] wire out_wimask_192 = &_out_wimask_T_192; // @[RegisterRouter.scala:87:24] wire out_romask_192 = |_out_romask_T_192; // @[RegisterRouter.scala:87:24] wire out_womask_192 = &_out_womask_T_192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_192 = out_rivalid_1_46 & out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2341 = out_f_rivalid_192; // @[RegisterRouter.scala:87:24] wire out_f_roready_192 = out_roready_1_46 & out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2342 = out_f_roready_192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_192 = out_wivalid_1_46 & out_wimask_192; // @[RegisterRouter.scala:87:24] wire out_f_woready_192 = out_woready_1_46 & out_womask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2343 = ~out_rimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2344 = ~out_wimask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2345 = ~out_romask_192; // @[RegisterRouter.scala:87:24] wire _out_T_2346 = ~out_womask_192; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_152 = {hi_719, flags_0_go, _out_prepend_T_152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2347 = out_prepend_152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2348 = _out_T_2347; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_153 = _out_T_2348; // @[RegisterRouter.scala:87:24] wire out_rimask_193 = |_out_rimask_T_193; // @[RegisterRouter.scala:87:24] wire out_wimask_193 = &_out_wimask_T_193; // @[RegisterRouter.scala:87:24] wire out_romask_193 = |_out_romask_T_193; // @[RegisterRouter.scala:87:24] wire out_womask_193 = &_out_womask_T_193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_193 = out_rivalid_1_47 & out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2350 = out_f_rivalid_193; // @[RegisterRouter.scala:87:24] wire out_f_roready_193 = out_roready_1_47 & out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2351 = out_f_roready_193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_193 = out_wivalid_1_47 & out_wimask_193; // @[RegisterRouter.scala:87:24] wire out_f_woready_193 = out_woready_1_47 & out_womask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2352 = ~out_rimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2353 = ~out_wimask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2354 = ~out_romask_193; // @[RegisterRouter.scala:87:24] wire _out_T_2355 = ~out_womask_193; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_153 = {hi_720, flags_0_go, _out_prepend_T_153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2356 = out_prepend_153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2357 = _out_T_2356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_217 = _out_T_2357; // @[MuxLiteral.scala:49:48] wire out_rimask_194 = |_out_rimask_T_194; // @[RegisterRouter.scala:87:24] wire out_wimask_194 = &_out_wimask_T_194; // @[RegisterRouter.scala:87:24] wire out_romask_194 = |_out_romask_T_194; // @[RegisterRouter.scala:87:24] wire out_womask_194 = &_out_womask_T_194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_194 = out_rivalid_1_48 & out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2359 = out_f_rivalid_194; // @[RegisterRouter.scala:87:24] wire out_f_roready_194 = out_roready_1_48 & out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2360 = out_f_roready_194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_194 = out_wivalid_1_48 & out_wimask_194; // @[RegisterRouter.scala:87:24] wire out_f_woready_194 = out_woready_1_48 & out_womask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2361 = ~out_rimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2362 = ~out_wimask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2363 = ~out_romask_194; // @[RegisterRouter.scala:87:24] wire _out_T_2364 = ~out_womask_194; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2366 = _out_T_2365; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_154 = _out_T_2366; // @[RegisterRouter.scala:87:24] wire out_rimask_195 = |_out_rimask_T_195; // @[RegisterRouter.scala:87:24] wire out_wimask_195 = &_out_wimask_T_195; // @[RegisterRouter.scala:87:24] wire out_romask_195 = |_out_romask_T_195; // @[RegisterRouter.scala:87:24] wire out_womask_195 = &_out_womask_T_195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_195 = out_rivalid_1_49 & out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2368 = out_f_rivalid_195; // @[RegisterRouter.scala:87:24] wire out_f_roready_195 = out_roready_1_49 & out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2369 = out_f_roready_195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_195 = out_wivalid_1_49 & out_wimask_195; // @[RegisterRouter.scala:87:24] wire out_f_woready_195 = out_woready_1_49 & out_womask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2370 = ~out_rimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2371 = ~out_wimask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2372 = ~out_romask_195; // @[RegisterRouter.scala:87:24] wire _out_T_2373 = ~out_womask_195; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_154 = {hi_954, flags_0_go, _out_prepend_T_154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2374 = out_prepend_154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2375 = _out_T_2374; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_155 = _out_T_2375; // @[RegisterRouter.scala:87:24] wire out_rimask_196 = |_out_rimask_T_196; // @[RegisterRouter.scala:87:24] wire out_wimask_196 = &_out_wimask_T_196; // @[RegisterRouter.scala:87:24] wire out_romask_196 = |_out_romask_T_196; // @[RegisterRouter.scala:87:24] wire out_womask_196 = &_out_womask_T_196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_196 = out_rivalid_1_50 & out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2377 = out_f_rivalid_196; // @[RegisterRouter.scala:87:24] wire out_f_roready_196 = out_roready_1_50 & out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2378 = out_f_roready_196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_196 = out_wivalid_1_50 & out_wimask_196; // @[RegisterRouter.scala:87:24] wire out_f_woready_196 = out_woready_1_50 & out_womask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2379 = ~out_rimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2380 = ~out_wimask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2381 = ~out_romask_196; // @[RegisterRouter.scala:87:24] wire _out_T_2382 = ~out_womask_196; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_155 = {hi_955, flags_0_go, _out_prepend_T_155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2383 = out_prepend_155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2384 = _out_T_2383; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_156 = _out_T_2384; // @[RegisterRouter.scala:87:24] wire out_rimask_197 = |_out_rimask_T_197; // @[RegisterRouter.scala:87:24] wire out_wimask_197 = &_out_wimask_T_197; // @[RegisterRouter.scala:87:24] wire out_romask_197 = |_out_romask_T_197; // @[RegisterRouter.scala:87:24] wire out_womask_197 = &_out_womask_T_197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_197 = out_rivalid_1_51 & out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2386 = out_f_rivalid_197; // @[RegisterRouter.scala:87:24] wire out_f_roready_197 = out_roready_1_51 & out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2387 = out_f_roready_197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_197 = out_wivalid_1_51 & out_wimask_197; // @[RegisterRouter.scala:87:24] wire out_f_woready_197 = out_woready_1_51 & out_womask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2388 = ~out_rimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2389 = ~out_wimask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2390 = ~out_romask_197; // @[RegisterRouter.scala:87:24] wire _out_T_2391 = ~out_womask_197; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_156 = {hi_956, flags_0_go, _out_prepend_T_156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2392 = out_prepend_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2393 = _out_T_2392; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_157 = _out_T_2393; // @[RegisterRouter.scala:87:24] wire out_rimask_198 = |_out_rimask_T_198; // @[RegisterRouter.scala:87:24] wire out_wimask_198 = &_out_wimask_T_198; // @[RegisterRouter.scala:87:24] wire out_romask_198 = |_out_romask_T_198; // @[RegisterRouter.scala:87:24] wire out_womask_198 = &_out_womask_T_198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_198 = out_rivalid_1_52 & out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2395 = out_f_rivalid_198; // @[RegisterRouter.scala:87:24] wire out_f_roready_198 = out_roready_1_52 & out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2396 = out_f_roready_198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_198 = out_wivalid_1_52 & out_wimask_198; // @[RegisterRouter.scala:87:24] wire out_f_woready_198 = out_woready_1_52 & out_womask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2397 = ~out_rimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2398 = ~out_wimask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2399 = ~out_romask_198; // @[RegisterRouter.scala:87:24] wire _out_T_2400 = ~out_womask_198; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_157 = {hi_957, flags_0_go, _out_prepend_T_157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2401 = out_prepend_157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2402 = _out_T_2401; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_158 = _out_T_2402; // @[RegisterRouter.scala:87:24] wire out_rimask_199 = |_out_rimask_T_199; // @[RegisterRouter.scala:87:24] wire out_wimask_199 = &_out_wimask_T_199; // @[RegisterRouter.scala:87:24] wire out_romask_199 = |_out_romask_T_199; // @[RegisterRouter.scala:87:24] wire out_womask_199 = &_out_womask_T_199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_199 = out_rivalid_1_53 & out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2404 = out_f_rivalid_199; // @[RegisterRouter.scala:87:24] wire out_f_roready_199 = out_roready_1_53 & out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2405 = out_f_roready_199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_199 = out_wivalid_1_53 & out_wimask_199; // @[RegisterRouter.scala:87:24] wire out_f_woready_199 = out_woready_1_53 & out_womask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2406 = ~out_rimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2407 = ~out_wimask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2408 = ~out_romask_199; // @[RegisterRouter.scala:87:24] wire _out_T_2409 = ~out_womask_199; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_158 = {hi_958, flags_0_go, _out_prepend_T_158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2410 = out_prepend_158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2411 = _out_T_2410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_159 = _out_T_2411; // @[RegisterRouter.scala:87:24] wire out_rimask_200 = |_out_rimask_T_200; // @[RegisterRouter.scala:87:24] wire out_wimask_200 = &_out_wimask_T_200; // @[RegisterRouter.scala:87:24] wire out_romask_200 = |_out_romask_T_200; // @[RegisterRouter.scala:87:24] wire out_womask_200 = &_out_womask_T_200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_200 = out_rivalid_1_54 & out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2413 = out_f_rivalid_200; // @[RegisterRouter.scala:87:24] wire out_f_roready_200 = out_roready_1_54 & out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2414 = out_f_roready_200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_200 = out_wivalid_1_54 & out_wimask_200; // @[RegisterRouter.scala:87:24] wire out_f_woready_200 = out_woready_1_54 & out_womask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2415 = ~out_rimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2416 = ~out_wimask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2417 = ~out_romask_200; // @[RegisterRouter.scala:87:24] wire _out_T_2418 = ~out_womask_200; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_159 = {hi_959, flags_0_go, _out_prepend_T_159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2419 = out_prepend_159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2420 = _out_T_2419; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_160 = _out_T_2420; // @[RegisterRouter.scala:87:24] wire out_rimask_201 = |_out_rimask_T_201; // @[RegisterRouter.scala:87:24] wire out_wimask_201 = &_out_wimask_T_201; // @[RegisterRouter.scala:87:24] wire out_romask_201 = |_out_romask_T_201; // @[RegisterRouter.scala:87:24] wire out_womask_201 = &_out_womask_T_201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_201 = out_rivalid_1_55 & out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2422 = out_f_rivalid_201; // @[RegisterRouter.scala:87:24] wire out_f_roready_201 = out_roready_1_55 & out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2423 = out_f_roready_201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_201 = out_wivalid_1_55 & out_wimask_201; // @[RegisterRouter.scala:87:24] wire out_f_woready_201 = out_woready_1_55 & out_womask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2424 = ~out_rimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2425 = ~out_wimask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2426 = ~out_romask_201; // @[RegisterRouter.scala:87:24] wire _out_T_2427 = ~out_womask_201; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_160 = {hi_960, flags_0_go, _out_prepend_T_160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2428 = out_prepend_160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2429 = _out_T_2428; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_247 = _out_T_2429; // @[MuxLiteral.scala:49:48] wire out_rimask_202 = |_out_rimask_T_202; // @[RegisterRouter.scala:87:24] wire out_wimask_202 = &_out_wimask_T_202; // @[RegisterRouter.scala:87:24] wire out_romask_202 = |_out_romask_T_202; // @[RegisterRouter.scala:87:24] wire out_womask_202 = &_out_womask_T_202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_202 = out_rivalid_1_56 & out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2431 = out_f_rivalid_202; // @[RegisterRouter.scala:87:24] wire out_f_roready_202 = out_roready_1_56 & out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2432 = out_f_roready_202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_202 = out_wivalid_1_56 & out_wimask_202; // @[RegisterRouter.scala:87:24] wire out_f_woready_202 = out_woready_1_56 & out_womask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2433 = ~out_rimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2434 = ~out_wimask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2435 = ~out_romask_202; // @[RegisterRouter.scala:87:24] wire _out_T_2436 = ~out_womask_202; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2438 = _out_T_2437; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_161 = _out_T_2438; // @[RegisterRouter.scala:87:24] wire out_rimask_203 = |_out_rimask_T_203; // @[RegisterRouter.scala:87:24] wire out_wimask_203 = &_out_wimask_T_203; // @[RegisterRouter.scala:87:24] wire out_romask_203 = |_out_romask_T_203; // @[RegisterRouter.scala:87:24] wire out_womask_203 = &_out_womask_T_203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_203 = out_rivalid_1_57 & out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2440 = out_f_rivalid_203; // @[RegisterRouter.scala:87:24] wire out_f_roready_203 = out_roready_1_57 & out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2441 = out_f_roready_203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_203 = out_wivalid_1_57 & out_wimask_203; // @[RegisterRouter.scala:87:24] wire out_f_woready_203 = out_woready_1_57 & out_womask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2442 = ~out_rimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2443 = ~out_wimask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2444 = ~out_romask_203; // @[RegisterRouter.scala:87:24] wire _out_T_2445 = ~out_womask_203; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_161 = {hi_594, flags_0_go, _out_prepend_T_161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2446 = out_prepend_161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2447 = _out_T_2446; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_162 = _out_T_2447; // @[RegisterRouter.scala:87:24] wire out_rimask_204 = |_out_rimask_T_204; // @[RegisterRouter.scala:87:24] wire out_wimask_204 = &_out_wimask_T_204; // @[RegisterRouter.scala:87:24] wire out_romask_204 = |_out_romask_T_204; // @[RegisterRouter.scala:87:24] wire out_womask_204 = &_out_womask_T_204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_204 = out_rivalid_1_58 & out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2449 = out_f_rivalid_204; // @[RegisterRouter.scala:87:24] wire out_f_roready_204 = out_roready_1_58 & out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2450 = out_f_roready_204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_204 = out_wivalid_1_58 & out_wimask_204; // @[RegisterRouter.scala:87:24] wire out_f_woready_204 = out_woready_1_58 & out_womask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2451 = ~out_rimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2452 = ~out_wimask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2453 = ~out_romask_204; // @[RegisterRouter.scala:87:24] wire _out_T_2454 = ~out_womask_204; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_162 = {hi_595, flags_0_go, _out_prepend_T_162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2455 = out_prepend_162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2456 = _out_T_2455; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_163 = _out_T_2456; // @[RegisterRouter.scala:87:24] wire out_rimask_205 = |_out_rimask_T_205; // @[RegisterRouter.scala:87:24] wire out_wimask_205 = &_out_wimask_T_205; // @[RegisterRouter.scala:87:24] wire out_romask_205 = |_out_romask_T_205; // @[RegisterRouter.scala:87:24] wire out_womask_205 = &_out_womask_T_205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_205 = out_rivalid_1_59 & out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2458 = out_f_rivalid_205; // @[RegisterRouter.scala:87:24] wire out_f_roready_205 = out_roready_1_59 & out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2459 = out_f_roready_205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_205 = out_wivalid_1_59 & out_wimask_205; // @[RegisterRouter.scala:87:24] wire out_f_woready_205 = out_woready_1_59 & out_womask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2460 = ~out_rimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2461 = ~out_wimask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2462 = ~out_romask_205; // @[RegisterRouter.scala:87:24] wire _out_T_2463 = ~out_womask_205; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_163 = {hi_596, flags_0_go, _out_prepend_T_163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2464 = out_prepend_163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2465 = _out_T_2464; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_164 = _out_T_2465; // @[RegisterRouter.scala:87:24] wire out_rimask_206 = |_out_rimask_T_206; // @[RegisterRouter.scala:87:24] wire out_wimask_206 = &_out_wimask_T_206; // @[RegisterRouter.scala:87:24] wire out_romask_206 = |_out_romask_T_206; // @[RegisterRouter.scala:87:24] wire out_womask_206 = &_out_womask_T_206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_206 = out_rivalid_1_60 & out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2467 = out_f_rivalid_206; // @[RegisterRouter.scala:87:24] wire out_f_roready_206 = out_roready_1_60 & out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2468 = out_f_roready_206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_206 = out_wivalid_1_60 & out_wimask_206; // @[RegisterRouter.scala:87:24] wire out_f_woready_206 = out_woready_1_60 & out_womask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2469 = ~out_rimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2470 = ~out_wimask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2471 = ~out_romask_206; // @[RegisterRouter.scala:87:24] wire _out_T_2472 = ~out_womask_206; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_164 = {hi_597, flags_0_go, _out_prepend_T_164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2473 = out_prepend_164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2474 = _out_T_2473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_165 = _out_T_2474; // @[RegisterRouter.scala:87:24] wire out_rimask_207 = |_out_rimask_T_207; // @[RegisterRouter.scala:87:24] wire out_wimask_207 = &_out_wimask_T_207; // @[RegisterRouter.scala:87:24] wire out_romask_207 = |_out_romask_T_207; // @[RegisterRouter.scala:87:24] wire out_womask_207 = &_out_womask_T_207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_207 = out_rivalid_1_61 & out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2476 = out_f_rivalid_207; // @[RegisterRouter.scala:87:24] wire out_f_roready_207 = out_roready_1_61 & out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2477 = out_f_roready_207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_207 = out_wivalid_1_61 & out_wimask_207; // @[RegisterRouter.scala:87:24] wire out_f_woready_207 = out_woready_1_61 & out_womask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2478 = ~out_rimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2479 = ~out_wimask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2480 = ~out_romask_207; // @[RegisterRouter.scala:87:24] wire _out_T_2481 = ~out_womask_207; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_165 = {hi_598, flags_0_go, _out_prepend_T_165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2482 = out_prepend_165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2483 = _out_T_2482; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_166 = _out_T_2483; // @[RegisterRouter.scala:87:24] wire out_rimask_208 = |_out_rimask_T_208; // @[RegisterRouter.scala:87:24] wire out_wimask_208 = &_out_wimask_T_208; // @[RegisterRouter.scala:87:24] wire out_romask_208 = |_out_romask_T_208; // @[RegisterRouter.scala:87:24] wire out_womask_208 = &_out_womask_T_208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_208 = out_rivalid_1_62 & out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2485 = out_f_rivalid_208; // @[RegisterRouter.scala:87:24] wire out_f_roready_208 = out_roready_1_62 & out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2486 = out_f_roready_208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_208 = out_wivalid_1_62 & out_wimask_208; // @[RegisterRouter.scala:87:24] wire out_f_woready_208 = out_woready_1_62 & out_womask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2487 = ~out_rimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2488 = ~out_wimask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2489 = ~out_romask_208; // @[RegisterRouter.scala:87:24] wire _out_T_2490 = ~out_womask_208; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_166 = {hi_599, flags_0_go, _out_prepend_T_166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2491 = out_prepend_166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2492 = _out_T_2491; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_167 = _out_T_2492; // @[RegisterRouter.scala:87:24] wire out_rimask_209 = |_out_rimask_T_209; // @[RegisterRouter.scala:87:24] wire out_wimask_209 = &_out_wimask_T_209; // @[RegisterRouter.scala:87:24] wire out_romask_209 = |_out_romask_T_209; // @[RegisterRouter.scala:87:24] wire out_womask_209 = &_out_womask_T_209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_209 = out_rivalid_1_63 & out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2494 = out_f_rivalid_209; // @[RegisterRouter.scala:87:24] wire out_f_roready_209 = out_roready_1_63 & out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2495 = out_f_roready_209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_209 = out_wivalid_1_63 & out_wimask_209; // @[RegisterRouter.scala:87:24] wire out_f_woready_209 = out_woready_1_63 & out_womask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2496 = ~out_rimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2497 = ~out_wimask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2498 = ~out_romask_209; // @[RegisterRouter.scala:87:24] wire _out_T_2499 = ~out_womask_209; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_167 = {hi_600, flags_0_go, _out_prepend_T_167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2500 = out_prepend_167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2501 = _out_T_2500; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_202 = _out_T_2501; // @[MuxLiteral.scala:49:48] wire out_rimask_210 = |_out_rimask_T_210; // @[RegisterRouter.scala:87:24] wire out_wimask_210 = &_out_wimask_T_210; // @[RegisterRouter.scala:87:24] wire out_romask_210 = |_out_romask_T_210; // @[RegisterRouter.scala:87:24] wire out_womask_210 = &_out_womask_T_210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_210 = out_rivalid_1_64 & out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2503 = out_f_rivalid_210; // @[RegisterRouter.scala:87:24] wire out_f_roready_210 = out_roready_1_64 & out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2504 = out_f_roready_210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_210 = out_wivalid_1_64 & out_wimask_210; // @[RegisterRouter.scala:87:24] wire out_f_woready_210 = out_woready_1_64 & out_womask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2505 = ~out_rimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2506 = ~out_wimask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2507 = ~out_romask_210; // @[RegisterRouter.scala:87:24] wire _out_T_2508 = ~out_womask_210; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2510 = _out_T_2509; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_168 = _out_T_2510; // @[RegisterRouter.scala:87:24] wire out_rimask_211 = |_out_rimask_T_211; // @[RegisterRouter.scala:87:24] wire out_wimask_211 = &_out_wimask_T_211; // @[RegisterRouter.scala:87:24] wire out_romask_211 = |_out_romask_T_211; // @[RegisterRouter.scala:87:24] wire out_womask_211 = &_out_womask_T_211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_211 = out_rivalid_1_65 & out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2512 = out_f_rivalid_211; // @[RegisterRouter.scala:87:24] wire out_f_roready_211 = out_roready_1_65 & out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2513 = out_f_roready_211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_211 = out_wivalid_1_65 & out_wimask_211; // @[RegisterRouter.scala:87:24] wire out_f_woready_211 = out_woready_1_65 & out_womask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2514 = ~out_rimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2515 = ~out_wimask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2516 = ~out_romask_211; // @[RegisterRouter.scala:87:24] wire _out_T_2517 = ~out_womask_211; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_168 = {hi_114, flags_0_go, _out_prepend_T_168}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2518 = out_prepend_168; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2519 = _out_T_2518; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_169 = _out_T_2519; // @[RegisterRouter.scala:87:24] wire out_rimask_212 = |_out_rimask_T_212; // @[RegisterRouter.scala:87:24] wire out_wimask_212 = &_out_wimask_T_212; // @[RegisterRouter.scala:87:24] wire out_romask_212 = |_out_romask_T_212; // @[RegisterRouter.scala:87:24] wire out_womask_212 = &_out_womask_T_212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_212 = out_rivalid_1_66 & out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2521 = out_f_rivalid_212; // @[RegisterRouter.scala:87:24] wire out_f_roready_212 = out_roready_1_66 & out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2522 = out_f_roready_212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_212 = out_wivalid_1_66 & out_wimask_212; // @[RegisterRouter.scala:87:24] wire out_f_woready_212 = out_woready_1_66 & out_womask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2523 = ~out_rimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2524 = ~out_wimask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2525 = ~out_romask_212; // @[RegisterRouter.scala:87:24] wire _out_T_2526 = ~out_womask_212; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_169 = {hi_115, flags_0_go, _out_prepend_T_169}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2527 = out_prepend_169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2528 = _out_T_2527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_170 = _out_T_2528; // @[RegisterRouter.scala:87:24] wire out_rimask_213 = |_out_rimask_T_213; // @[RegisterRouter.scala:87:24] wire out_wimask_213 = &_out_wimask_T_213; // @[RegisterRouter.scala:87:24] wire out_romask_213 = |_out_romask_T_213; // @[RegisterRouter.scala:87:24] wire out_womask_213 = &_out_womask_T_213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_213 = out_rivalid_1_67 & out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2530 = out_f_rivalid_213; // @[RegisterRouter.scala:87:24] wire out_f_roready_213 = out_roready_1_67 & out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2531 = out_f_roready_213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_213 = out_wivalid_1_67 & out_wimask_213; // @[RegisterRouter.scala:87:24] wire out_f_woready_213 = out_woready_1_67 & out_womask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2532 = ~out_rimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2533 = ~out_wimask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2534 = ~out_romask_213; // @[RegisterRouter.scala:87:24] wire _out_T_2535 = ~out_womask_213; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_170 = {hi_116, flags_0_go, _out_prepend_T_170}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2536 = out_prepend_170; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2537 = _out_T_2536; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_171 = _out_T_2537; // @[RegisterRouter.scala:87:24] wire out_rimask_214 = |_out_rimask_T_214; // @[RegisterRouter.scala:87:24] wire out_wimask_214 = &_out_wimask_T_214; // @[RegisterRouter.scala:87:24] wire out_romask_214 = |_out_romask_T_214; // @[RegisterRouter.scala:87:24] wire out_womask_214 = &_out_womask_T_214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_214 = out_rivalid_1_68 & out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2539 = out_f_rivalid_214; // @[RegisterRouter.scala:87:24] wire out_f_roready_214 = out_roready_1_68 & out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2540 = out_f_roready_214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_214 = out_wivalid_1_68 & out_wimask_214; // @[RegisterRouter.scala:87:24] wire out_f_woready_214 = out_woready_1_68 & out_womask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2541 = ~out_rimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2542 = ~out_wimask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2543 = ~out_romask_214; // @[RegisterRouter.scala:87:24] wire _out_T_2544 = ~out_womask_214; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_171 = {hi_117, flags_0_go, _out_prepend_T_171}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2545 = out_prepend_171; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2546 = _out_T_2545; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_172 = _out_T_2546; // @[RegisterRouter.scala:87:24] wire out_rimask_215 = |_out_rimask_T_215; // @[RegisterRouter.scala:87:24] wire out_wimask_215 = &_out_wimask_T_215; // @[RegisterRouter.scala:87:24] wire out_romask_215 = |_out_romask_T_215; // @[RegisterRouter.scala:87:24] wire out_womask_215 = &_out_womask_T_215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_215 = out_rivalid_1_69 & out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2548 = out_f_rivalid_215; // @[RegisterRouter.scala:87:24] wire out_f_roready_215 = out_roready_1_69 & out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2549 = out_f_roready_215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_215 = out_wivalid_1_69 & out_wimask_215; // @[RegisterRouter.scala:87:24] wire out_f_woready_215 = out_woready_1_69 & out_womask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2550 = ~out_rimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2551 = ~out_wimask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2552 = ~out_romask_215; // @[RegisterRouter.scala:87:24] wire _out_T_2553 = ~out_womask_215; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_172 = {hi_118, flags_0_go, _out_prepend_T_172}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2554 = out_prepend_172; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2555 = _out_T_2554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_173 = _out_T_2555; // @[RegisterRouter.scala:87:24] wire out_rimask_216 = |_out_rimask_T_216; // @[RegisterRouter.scala:87:24] wire out_wimask_216 = &_out_wimask_T_216; // @[RegisterRouter.scala:87:24] wire out_romask_216 = |_out_romask_T_216; // @[RegisterRouter.scala:87:24] wire out_womask_216 = &_out_womask_T_216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_216 = out_rivalid_1_70 & out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2557 = out_f_rivalid_216; // @[RegisterRouter.scala:87:24] wire out_f_roready_216 = out_roready_1_70 & out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2558 = out_f_roready_216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_216 = out_wivalid_1_70 & out_wimask_216; // @[RegisterRouter.scala:87:24] wire out_f_woready_216 = out_woready_1_70 & out_womask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2559 = ~out_rimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2560 = ~out_wimask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2561 = ~out_romask_216; // @[RegisterRouter.scala:87:24] wire _out_T_2562 = ~out_womask_216; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_173 = {hi_119, flags_0_go, _out_prepend_T_173}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2563 = out_prepend_173; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2564 = _out_T_2563; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_174 = _out_T_2564; // @[RegisterRouter.scala:87:24] wire out_rimask_217 = |_out_rimask_T_217; // @[RegisterRouter.scala:87:24] wire out_wimask_217 = &_out_wimask_T_217; // @[RegisterRouter.scala:87:24] wire out_romask_217 = |_out_romask_T_217; // @[RegisterRouter.scala:87:24] wire out_womask_217 = &_out_womask_T_217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_217 = out_rivalid_1_71 & out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2566 = out_f_rivalid_217; // @[RegisterRouter.scala:87:24] wire out_f_roready_217 = out_roready_1_71 & out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2567 = out_f_roready_217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_217 = out_wivalid_1_71 & out_wimask_217; // @[RegisterRouter.scala:87:24] wire out_f_woready_217 = out_woready_1_71 & out_womask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2568 = ~out_rimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2569 = ~out_wimask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2570 = ~out_romask_217; // @[RegisterRouter.scala:87:24] wire _out_T_2571 = ~out_womask_217; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_174 = {hi_120, flags_0_go, _out_prepend_T_174}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2572 = out_prepend_174; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2573 = _out_T_2572; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_142 = _out_T_2573; // @[MuxLiteral.scala:49:48] wire out_rimask_218 = |_out_rimask_T_218; // @[RegisterRouter.scala:87:24] wire out_wimask_218 = &_out_wimask_T_218; // @[RegisterRouter.scala:87:24] wire out_romask_218 = |_out_romask_T_218; // @[RegisterRouter.scala:87:24] wire out_womask_218 = &_out_womask_T_218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_218 = out_rivalid_1_72 & out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2575 = out_f_rivalid_218; // @[RegisterRouter.scala:87:24] wire out_f_roready_218 = out_roready_1_72 & out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2576 = out_f_roready_218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_218 = out_wivalid_1_72 & out_wimask_218; // @[RegisterRouter.scala:87:24] wire out_f_woready_218 = out_woready_1_72 & out_womask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2577 = ~out_rimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2578 = ~out_wimask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2579 = ~out_romask_218; // @[RegisterRouter.scala:87:24] wire _out_T_2580 = ~out_womask_218; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2582 = _out_T_2581; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_175 = _out_T_2582; // @[RegisterRouter.scala:87:24] wire out_rimask_219 = |_out_rimask_T_219; // @[RegisterRouter.scala:87:24] wire out_wimask_219 = &_out_wimask_T_219; // @[RegisterRouter.scala:87:24] wire out_romask_219 = |_out_romask_T_219; // @[RegisterRouter.scala:87:24] wire out_womask_219 = &_out_womask_T_219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_219 = out_rivalid_1_73 & out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2584 = out_f_rivalid_219; // @[RegisterRouter.scala:87:24] wire out_f_roready_219 = out_roready_1_73 & out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2585 = out_f_roready_219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_219 = out_wivalid_1_73 & out_wimask_219; // @[RegisterRouter.scala:87:24] wire out_f_woready_219 = out_woready_1_73 & out_womask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2586 = ~out_rimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2587 = ~out_wimask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2588 = ~out_romask_219; // @[RegisterRouter.scala:87:24] wire _out_T_2589 = ~out_womask_219; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_175 = {hi_202, flags_0_go, _out_prepend_T_175}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2590 = out_prepend_175; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2591 = _out_T_2590; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_176 = _out_T_2591; // @[RegisterRouter.scala:87:24] wire out_rimask_220 = |_out_rimask_T_220; // @[RegisterRouter.scala:87:24] wire out_wimask_220 = &_out_wimask_T_220; // @[RegisterRouter.scala:87:24] wire out_romask_220 = |_out_romask_T_220; // @[RegisterRouter.scala:87:24] wire out_womask_220 = &_out_womask_T_220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_220 = out_rivalid_1_74 & out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2593 = out_f_rivalid_220; // @[RegisterRouter.scala:87:24] wire out_f_roready_220 = out_roready_1_74 & out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2594 = out_f_roready_220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_220 = out_wivalid_1_74 & out_wimask_220; // @[RegisterRouter.scala:87:24] wire out_f_woready_220 = out_woready_1_74 & out_womask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2595 = ~out_rimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2596 = ~out_wimask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2597 = ~out_romask_220; // @[RegisterRouter.scala:87:24] wire _out_T_2598 = ~out_womask_220; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_176 = {hi_203, flags_0_go, _out_prepend_T_176}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2599 = out_prepend_176; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2600 = _out_T_2599; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_177 = _out_T_2600; // @[RegisterRouter.scala:87:24] wire out_rimask_221 = |_out_rimask_T_221; // @[RegisterRouter.scala:87:24] wire out_wimask_221 = &_out_wimask_T_221; // @[RegisterRouter.scala:87:24] wire out_romask_221 = |_out_romask_T_221; // @[RegisterRouter.scala:87:24] wire out_womask_221 = &_out_womask_T_221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_221 = out_rivalid_1_75 & out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2602 = out_f_rivalid_221; // @[RegisterRouter.scala:87:24] wire out_f_roready_221 = out_roready_1_75 & out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2603 = out_f_roready_221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_221 = out_wivalid_1_75 & out_wimask_221; // @[RegisterRouter.scala:87:24] wire out_f_woready_221 = out_woready_1_75 & out_womask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2604 = ~out_rimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2605 = ~out_wimask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2606 = ~out_romask_221; // @[RegisterRouter.scala:87:24] wire _out_T_2607 = ~out_womask_221; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_177 = {hi_204, flags_0_go, _out_prepend_T_177}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2608 = out_prepend_177; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2609 = _out_T_2608; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_178 = _out_T_2609; // @[RegisterRouter.scala:87:24] wire out_rimask_222 = |_out_rimask_T_222; // @[RegisterRouter.scala:87:24] wire out_wimask_222 = &_out_wimask_T_222; // @[RegisterRouter.scala:87:24] wire out_romask_222 = |_out_romask_T_222; // @[RegisterRouter.scala:87:24] wire out_womask_222 = &_out_womask_T_222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_222 = out_rivalid_1_76 & out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2611 = out_f_rivalid_222; // @[RegisterRouter.scala:87:24] wire out_f_roready_222 = out_roready_1_76 & out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2612 = out_f_roready_222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_222 = out_wivalid_1_76 & out_wimask_222; // @[RegisterRouter.scala:87:24] wire out_f_woready_222 = out_woready_1_76 & out_womask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2613 = ~out_rimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2614 = ~out_wimask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2615 = ~out_romask_222; // @[RegisterRouter.scala:87:24] wire _out_T_2616 = ~out_womask_222; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_178 = {hi_205, flags_0_go, _out_prepend_T_178}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2617 = out_prepend_178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2618 = _out_T_2617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_179 = _out_T_2618; // @[RegisterRouter.scala:87:24] wire out_rimask_223 = |_out_rimask_T_223; // @[RegisterRouter.scala:87:24] wire out_wimask_223 = &_out_wimask_T_223; // @[RegisterRouter.scala:87:24] wire out_romask_223 = |_out_romask_T_223; // @[RegisterRouter.scala:87:24] wire out_womask_223 = &_out_womask_T_223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_223 = out_rivalid_1_77 & out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2620 = out_f_rivalid_223; // @[RegisterRouter.scala:87:24] wire out_f_roready_223 = out_roready_1_77 & out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2621 = out_f_roready_223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_223 = out_wivalid_1_77 & out_wimask_223; // @[RegisterRouter.scala:87:24] wire out_f_woready_223 = out_woready_1_77 & out_womask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2622 = ~out_rimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2623 = ~out_wimask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2624 = ~out_romask_223; // @[RegisterRouter.scala:87:24] wire _out_T_2625 = ~out_womask_223; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_179 = {hi_206, flags_0_go, _out_prepend_T_179}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2626 = out_prepend_179; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2627 = _out_T_2626; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_180 = _out_T_2627; // @[RegisterRouter.scala:87:24] wire out_rimask_224 = |_out_rimask_T_224; // @[RegisterRouter.scala:87:24] wire out_wimask_224 = &_out_wimask_T_224; // @[RegisterRouter.scala:87:24] wire out_romask_224 = |_out_romask_T_224; // @[RegisterRouter.scala:87:24] wire out_womask_224 = &_out_womask_T_224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_224 = out_rivalid_1_78 & out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2629 = out_f_rivalid_224; // @[RegisterRouter.scala:87:24] wire out_f_roready_224 = out_roready_1_78 & out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2630 = out_f_roready_224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_224 = out_wivalid_1_78 & out_wimask_224; // @[RegisterRouter.scala:87:24] wire out_f_woready_224 = out_woready_1_78 & out_womask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2631 = ~out_rimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2632 = ~out_wimask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2633 = ~out_romask_224; // @[RegisterRouter.scala:87:24] wire _out_T_2634 = ~out_womask_224; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_180 = {hi_207, flags_0_go, _out_prepend_T_180}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2635 = out_prepend_180; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2636 = _out_T_2635; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_181 = _out_T_2636; // @[RegisterRouter.scala:87:24] wire out_rimask_225 = |_out_rimask_T_225; // @[RegisterRouter.scala:87:24] wire out_wimask_225 = &_out_wimask_T_225; // @[RegisterRouter.scala:87:24] wire out_romask_225 = |_out_romask_T_225; // @[RegisterRouter.scala:87:24] wire out_womask_225 = &_out_womask_T_225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_225 = out_rivalid_1_79 & out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2638 = out_f_rivalid_225; // @[RegisterRouter.scala:87:24] wire out_f_roready_225 = out_roready_1_79 & out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2639 = out_f_roready_225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_225 = out_wivalid_1_79 & out_wimask_225; // @[RegisterRouter.scala:87:24] wire out_f_woready_225 = out_woready_1_79 & out_womask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2640 = ~out_rimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2641 = ~out_wimask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2642 = ~out_romask_225; // @[RegisterRouter.scala:87:24] wire _out_T_2643 = ~out_womask_225; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_181 = {hi_208, flags_0_go, _out_prepend_T_181}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2644 = out_prepend_181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2645 = _out_T_2644; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_153 = _out_T_2645; // @[MuxLiteral.scala:49:48] wire out_rimask_226 = |_out_rimask_T_226; // @[RegisterRouter.scala:87:24] wire out_wimask_226 = &_out_wimask_T_226; // @[RegisterRouter.scala:87:24] wire out_romask_226 = |_out_romask_T_226; // @[RegisterRouter.scala:87:24] wire out_womask_226 = &_out_womask_T_226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_226 = out_rivalid_1_80 & out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2647 = out_f_rivalid_226; // @[RegisterRouter.scala:87:24] wire out_f_roready_226 = out_roready_1_80 & out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2648 = out_f_roready_226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_226 = out_wivalid_1_80 & out_wimask_226; // @[RegisterRouter.scala:87:24] wire out_f_woready_226 = out_woready_1_80 & out_womask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2649 = ~out_rimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2650 = ~out_wimask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2651 = ~out_romask_226; // @[RegisterRouter.scala:87:24] wire _out_T_2652 = ~out_womask_226; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2654 = _out_T_2653; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_182 = _out_T_2654; // @[RegisterRouter.scala:87:24] wire out_rimask_227 = |_out_rimask_T_227; // @[RegisterRouter.scala:87:24] wire out_wimask_227 = &_out_wimask_T_227; // @[RegisterRouter.scala:87:24] wire out_romask_227 = |_out_romask_T_227; // @[RegisterRouter.scala:87:24] wire out_womask_227 = &_out_womask_T_227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_227 = out_rivalid_1_81 & out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2656 = out_f_rivalid_227; // @[RegisterRouter.scala:87:24] wire out_f_roready_227 = out_roready_1_81 & out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2657 = out_f_roready_227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_227 = out_wivalid_1_81 & out_wimask_227; // @[RegisterRouter.scala:87:24] wire out_f_woready_227 = out_woready_1_81 & out_womask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2658 = ~out_rimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2659 = ~out_wimask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2660 = ~out_romask_227; // @[RegisterRouter.scala:87:24] wire _out_T_2661 = ~out_womask_227; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_182 = {hi_370, flags_0_go, _out_prepend_T_182}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2662 = out_prepend_182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2663 = _out_T_2662; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_183 = _out_T_2663; // @[RegisterRouter.scala:87:24] wire out_rimask_228 = |_out_rimask_T_228; // @[RegisterRouter.scala:87:24] wire out_wimask_228 = &_out_wimask_T_228; // @[RegisterRouter.scala:87:24] wire out_romask_228 = |_out_romask_T_228; // @[RegisterRouter.scala:87:24] wire out_womask_228 = &_out_womask_T_228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_228 = out_rivalid_1_82 & out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2665 = out_f_rivalid_228; // @[RegisterRouter.scala:87:24] wire out_f_roready_228 = out_roready_1_82 & out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2666 = out_f_roready_228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_228 = out_wivalid_1_82 & out_wimask_228; // @[RegisterRouter.scala:87:24] wire out_f_woready_228 = out_woready_1_82 & out_womask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2667 = ~out_rimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2668 = ~out_wimask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2669 = ~out_romask_228; // @[RegisterRouter.scala:87:24] wire _out_T_2670 = ~out_womask_228; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_183 = {hi_371, flags_0_go, _out_prepend_T_183}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2671 = out_prepend_183; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2672 = _out_T_2671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_184 = _out_T_2672; // @[RegisterRouter.scala:87:24] wire out_rimask_229 = |_out_rimask_T_229; // @[RegisterRouter.scala:87:24] wire out_wimask_229 = &_out_wimask_T_229; // @[RegisterRouter.scala:87:24] wire out_romask_229 = |_out_romask_T_229; // @[RegisterRouter.scala:87:24] wire out_womask_229 = &_out_womask_T_229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_229 = out_rivalid_1_83 & out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2674 = out_f_rivalid_229; // @[RegisterRouter.scala:87:24] wire out_f_roready_229 = out_roready_1_83 & out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2675 = out_f_roready_229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_229 = out_wivalid_1_83 & out_wimask_229; // @[RegisterRouter.scala:87:24] wire out_f_woready_229 = out_woready_1_83 & out_womask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2676 = ~out_rimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2677 = ~out_wimask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2678 = ~out_romask_229; // @[RegisterRouter.scala:87:24] wire _out_T_2679 = ~out_womask_229; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_184 = {hi_372, flags_0_go, _out_prepend_T_184}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2680 = out_prepend_184; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2681 = _out_T_2680; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_185 = _out_T_2681; // @[RegisterRouter.scala:87:24] wire out_rimask_230 = |_out_rimask_T_230; // @[RegisterRouter.scala:87:24] wire out_wimask_230 = &_out_wimask_T_230; // @[RegisterRouter.scala:87:24] wire out_romask_230 = |_out_romask_T_230; // @[RegisterRouter.scala:87:24] wire out_womask_230 = &_out_womask_T_230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_230 = out_rivalid_1_84 & out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2683 = out_f_rivalid_230; // @[RegisterRouter.scala:87:24] wire out_f_roready_230 = out_roready_1_84 & out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2684 = out_f_roready_230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_230 = out_wivalid_1_84 & out_wimask_230; // @[RegisterRouter.scala:87:24] wire out_f_woready_230 = out_woready_1_84 & out_womask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2685 = ~out_rimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2686 = ~out_wimask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2687 = ~out_romask_230; // @[RegisterRouter.scala:87:24] wire _out_T_2688 = ~out_womask_230; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_185 = {hi_373, flags_0_go, _out_prepend_T_185}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2689 = out_prepend_185; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2690 = _out_T_2689; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_186 = _out_T_2690; // @[RegisterRouter.scala:87:24] wire out_rimask_231 = |_out_rimask_T_231; // @[RegisterRouter.scala:87:24] wire out_wimask_231 = &_out_wimask_T_231; // @[RegisterRouter.scala:87:24] wire out_romask_231 = |_out_romask_T_231; // @[RegisterRouter.scala:87:24] wire out_womask_231 = &_out_womask_T_231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_231 = out_rivalid_1_85 & out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2692 = out_f_rivalid_231; // @[RegisterRouter.scala:87:24] wire out_f_roready_231 = out_roready_1_85 & out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2693 = out_f_roready_231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_231 = out_wivalid_1_85 & out_wimask_231; // @[RegisterRouter.scala:87:24] wire out_f_woready_231 = out_woready_1_85 & out_womask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2694 = ~out_rimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2695 = ~out_wimask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2696 = ~out_romask_231; // @[RegisterRouter.scala:87:24] wire _out_T_2697 = ~out_womask_231; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_186 = {hi_374, flags_0_go, _out_prepend_T_186}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2698 = out_prepend_186; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2699 = _out_T_2698; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_187 = _out_T_2699; // @[RegisterRouter.scala:87:24] wire out_rimask_232 = |_out_rimask_T_232; // @[RegisterRouter.scala:87:24] wire out_wimask_232 = &_out_wimask_T_232; // @[RegisterRouter.scala:87:24] wire out_romask_232 = |_out_romask_T_232; // @[RegisterRouter.scala:87:24] wire out_womask_232 = &_out_womask_T_232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_232 = out_rivalid_1_86 & out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2701 = out_f_rivalid_232; // @[RegisterRouter.scala:87:24] wire out_f_roready_232 = out_roready_1_86 & out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2702 = out_f_roready_232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_232 = out_wivalid_1_86 & out_wimask_232; // @[RegisterRouter.scala:87:24] wire out_f_woready_232 = out_woready_1_86 & out_womask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2703 = ~out_rimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2704 = ~out_wimask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2705 = ~out_romask_232; // @[RegisterRouter.scala:87:24] wire _out_T_2706 = ~out_womask_232; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_187 = {hi_375, flags_0_go, _out_prepend_T_187}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2707 = out_prepend_187; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2708 = _out_T_2707; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_188 = _out_T_2708; // @[RegisterRouter.scala:87:24] wire out_rimask_233 = |_out_rimask_T_233; // @[RegisterRouter.scala:87:24] wire out_wimask_233 = &_out_wimask_T_233; // @[RegisterRouter.scala:87:24] wire out_romask_233 = |_out_romask_T_233; // @[RegisterRouter.scala:87:24] wire out_womask_233 = &_out_womask_T_233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_233 = out_rivalid_1_87 & out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2710 = out_f_rivalid_233; // @[RegisterRouter.scala:87:24] wire out_f_roready_233 = out_roready_1_87 & out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2711 = out_f_roready_233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_233 = out_wivalid_1_87 & out_wimask_233; // @[RegisterRouter.scala:87:24] wire out_f_woready_233 = out_woready_1_87 & out_womask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2712 = ~out_rimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2713 = ~out_wimask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2714 = ~out_romask_233; // @[RegisterRouter.scala:87:24] wire _out_T_2715 = ~out_womask_233; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_188 = {hi_376, flags_0_go, _out_prepend_T_188}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2716 = out_prepend_188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2717 = _out_T_2716; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_174 = _out_T_2717; // @[MuxLiteral.scala:49:48] wire out_rimask_234 = |_out_rimask_T_234; // @[RegisterRouter.scala:87:24] wire out_wimask_234 = &_out_wimask_T_234; // @[RegisterRouter.scala:87:24] wire out_romask_234 = |_out_romask_T_234; // @[RegisterRouter.scala:87:24] wire out_womask_234 = &_out_womask_T_234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_234 = out_rivalid_1_88 & out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2719 = out_f_rivalid_234; // @[RegisterRouter.scala:87:24] wire out_f_roready_234 = out_roready_1_88 & out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2720 = out_f_roready_234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_234 = out_wivalid_1_88 & out_wimask_234; // @[RegisterRouter.scala:87:24] wire out_f_woready_234 = out_woready_1_88 & out_womask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2721 = ~out_rimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2722 = ~out_wimask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2723 = ~out_romask_234; // @[RegisterRouter.scala:87:24] wire _out_T_2724 = ~out_womask_234; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2726 = _out_T_2725; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_189 = _out_T_2726; // @[RegisterRouter.scala:87:24] wire out_rimask_235 = |_out_rimask_T_235; // @[RegisterRouter.scala:87:24] wire out_wimask_235 = &_out_wimask_T_235; // @[RegisterRouter.scala:87:24] wire out_romask_235 = |_out_romask_T_235; // @[RegisterRouter.scala:87:24] wire out_womask_235 = &_out_womask_T_235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_235 = out_rivalid_1_89 & out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2728 = out_f_rivalid_235; // @[RegisterRouter.scala:87:24] wire out_f_roready_235 = out_roready_1_89 & out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2729 = out_f_roready_235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_235 = out_wivalid_1_89 & out_wimask_235; // @[RegisterRouter.scala:87:24] wire out_f_woready_235 = out_woready_1_89 & out_womask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2730 = ~out_rimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2731 = ~out_wimask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2732 = ~out_romask_235; // @[RegisterRouter.scala:87:24] wire _out_T_2733 = ~out_womask_235; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_189 = {hi_458, flags_0_go, _out_prepend_T_189}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2734 = out_prepend_189; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2735 = _out_T_2734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_190 = _out_T_2735; // @[RegisterRouter.scala:87:24] wire out_rimask_236 = |_out_rimask_T_236; // @[RegisterRouter.scala:87:24] wire out_wimask_236 = &_out_wimask_T_236; // @[RegisterRouter.scala:87:24] wire out_romask_236 = |_out_romask_T_236; // @[RegisterRouter.scala:87:24] wire out_womask_236 = &_out_womask_T_236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_236 = out_rivalid_1_90 & out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2737 = out_f_rivalid_236; // @[RegisterRouter.scala:87:24] wire out_f_roready_236 = out_roready_1_90 & out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2738 = out_f_roready_236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_236 = out_wivalid_1_90 & out_wimask_236; // @[RegisterRouter.scala:87:24] wire out_f_woready_236 = out_woready_1_90 & out_womask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2739 = ~out_rimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2740 = ~out_wimask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2741 = ~out_romask_236; // @[RegisterRouter.scala:87:24] wire _out_T_2742 = ~out_womask_236; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_190 = {hi_459, flags_0_go, _out_prepend_T_190}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2743 = out_prepend_190; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2744 = _out_T_2743; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_191 = _out_T_2744; // @[RegisterRouter.scala:87:24] wire out_rimask_237 = |_out_rimask_T_237; // @[RegisterRouter.scala:87:24] wire out_wimask_237 = &_out_wimask_T_237; // @[RegisterRouter.scala:87:24] wire out_romask_237 = |_out_romask_T_237; // @[RegisterRouter.scala:87:24] wire out_womask_237 = &_out_womask_T_237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_237 = out_rivalid_1_91 & out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2746 = out_f_rivalid_237; // @[RegisterRouter.scala:87:24] wire out_f_roready_237 = out_roready_1_91 & out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2747 = out_f_roready_237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_237 = out_wivalid_1_91 & out_wimask_237; // @[RegisterRouter.scala:87:24] wire out_f_woready_237 = out_woready_1_91 & out_womask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2748 = ~out_rimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2749 = ~out_wimask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2750 = ~out_romask_237; // @[RegisterRouter.scala:87:24] wire _out_T_2751 = ~out_womask_237; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_191 = {hi_460, flags_0_go, _out_prepend_T_191}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2752 = out_prepend_191; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2753 = _out_T_2752; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_192 = _out_T_2753; // @[RegisterRouter.scala:87:24] wire out_rimask_238 = |_out_rimask_T_238; // @[RegisterRouter.scala:87:24] wire out_wimask_238 = &_out_wimask_T_238; // @[RegisterRouter.scala:87:24] wire out_romask_238 = |_out_romask_T_238; // @[RegisterRouter.scala:87:24] wire out_womask_238 = &_out_womask_T_238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_238 = out_rivalid_1_92 & out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2755 = out_f_rivalid_238; // @[RegisterRouter.scala:87:24] wire out_f_roready_238 = out_roready_1_92 & out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2756 = out_f_roready_238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_238 = out_wivalid_1_92 & out_wimask_238; // @[RegisterRouter.scala:87:24] wire out_f_woready_238 = out_woready_1_92 & out_womask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2757 = ~out_rimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2758 = ~out_wimask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2759 = ~out_romask_238; // @[RegisterRouter.scala:87:24] wire _out_T_2760 = ~out_womask_238; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_192 = {hi_461, flags_0_go, _out_prepend_T_192}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2761 = out_prepend_192; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2762 = _out_T_2761; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_193 = _out_T_2762; // @[RegisterRouter.scala:87:24] wire out_rimask_239 = |_out_rimask_T_239; // @[RegisterRouter.scala:87:24] wire out_wimask_239 = &_out_wimask_T_239; // @[RegisterRouter.scala:87:24] wire out_romask_239 = |_out_romask_T_239; // @[RegisterRouter.scala:87:24] wire out_womask_239 = &_out_womask_T_239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_239 = out_rivalid_1_93 & out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2764 = out_f_rivalid_239; // @[RegisterRouter.scala:87:24] wire out_f_roready_239 = out_roready_1_93 & out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2765 = out_f_roready_239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_239 = out_wivalid_1_93 & out_wimask_239; // @[RegisterRouter.scala:87:24] wire out_f_woready_239 = out_woready_1_93 & out_womask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2766 = ~out_rimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2767 = ~out_wimask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2768 = ~out_romask_239; // @[RegisterRouter.scala:87:24] wire _out_T_2769 = ~out_womask_239; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_193 = {hi_462, flags_0_go, _out_prepend_T_193}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2770 = out_prepend_193; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2771 = _out_T_2770; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_194 = _out_T_2771; // @[RegisterRouter.scala:87:24] wire out_rimask_240 = |_out_rimask_T_240; // @[RegisterRouter.scala:87:24] wire out_wimask_240 = &_out_wimask_T_240; // @[RegisterRouter.scala:87:24] wire out_romask_240 = |_out_romask_T_240; // @[RegisterRouter.scala:87:24] wire out_womask_240 = &_out_womask_T_240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_240 = out_rivalid_1_94 & out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2773 = out_f_rivalid_240; // @[RegisterRouter.scala:87:24] wire out_f_roready_240 = out_roready_1_94 & out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2774 = out_f_roready_240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_240 = out_wivalid_1_94 & out_wimask_240; // @[RegisterRouter.scala:87:24] wire out_f_woready_240 = out_woready_1_94 & out_womask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2775 = ~out_rimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2776 = ~out_wimask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2777 = ~out_romask_240; // @[RegisterRouter.scala:87:24] wire _out_T_2778 = ~out_womask_240; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_194 = {hi_463, flags_0_go, _out_prepend_T_194}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2779 = out_prepend_194; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2780 = _out_T_2779; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_195 = _out_T_2780; // @[RegisterRouter.scala:87:24] wire out_rimask_241 = |_out_rimask_T_241; // @[RegisterRouter.scala:87:24] wire out_wimask_241 = &_out_wimask_T_241; // @[RegisterRouter.scala:87:24] wire out_romask_241 = |_out_romask_T_241; // @[RegisterRouter.scala:87:24] wire out_womask_241 = &_out_womask_T_241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_241 = out_rivalid_1_95 & out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2782 = out_f_rivalid_241; // @[RegisterRouter.scala:87:24] wire out_f_roready_241 = out_roready_1_95 & out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2783 = out_f_roready_241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_241 = out_wivalid_1_95 & out_wimask_241; // @[RegisterRouter.scala:87:24] wire out_f_woready_241 = out_woready_1_95 & out_womask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2784 = ~out_rimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2785 = ~out_wimask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2786 = ~out_romask_241; // @[RegisterRouter.scala:87:24] wire _out_T_2787 = ~out_womask_241; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_195 = {hi_464, flags_0_go, _out_prepend_T_195}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2788 = out_prepend_195; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2789 = _out_T_2788; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_185 = _out_T_2789; // @[MuxLiteral.scala:49:48] wire out_rimask_242 = |_out_rimask_T_242; // @[RegisterRouter.scala:87:24] wire out_wimask_242 = &_out_wimask_T_242; // @[RegisterRouter.scala:87:24] wire out_romask_242 = |_out_romask_T_242; // @[RegisterRouter.scala:87:24] wire out_womask_242 = &_out_womask_T_242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_242 = out_rivalid_1_96 & out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2791 = out_f_rivalid_242; // @[RegisterRouter.scala:87:24] wire out_f_roready_242 = out_roready_1_96 & out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2792 = out_f_roready_242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_242 = out_wivalid_1_96 & out_wimask_242; // @[RegisterRouter.scala:87:24] wire out_f_woready_242 = out_woready_1_96 & out_womask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2793 = ~out_rimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2794 = ~out_wimask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2795 = ~out_romask_242; // @[RegisterRouter.scala:87:24] wire _out_T_2796 = ~out_womask_242; // @[RegisterRouter.scala:87:24] wire out_rimask_243 = |_out_rimask_T_243; // @[RegisterRouter.scala:87:24] wire out_wimask_243 = &_out_wimask_T_243; // @[RegisterRouter.scala:87:24] wire out_romask_243 = |_out_romask_T_243; // @[RegisterRouter.scala:87:24] wire out_womask_243 = &_out_womask_T_243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_243 = out_rivalid_1_97 & out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2800 = out_f_rivalid_243; // @[RegisterRouter.scala:87:24] wire out_f_roready_243 = out_roready_1_97 & out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2801 = out_f_roready_243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_243 = out_wivalid_1_97 & out_wimask_243; // @[RegisterRouter.scala:87:24] wire out_f_woready_243 = out_woready_1_97 & out_womask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2802 = ~out_rimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2803 = ~out_wimask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2804 = ~out_romask_243; // @[RegisterRouter.scala:87:24] wire _out_T_2805 = ~out_womask_243; // @[RegisterRouter.scala:87:24] wire out_rimask_244 = |_out_rimask_T_244; // @[RegisterRouter.scala:87:24] wire out_wimask_244 = &_out_wimask_T_244; // @[RegisterRouter.scala:87:24] wire out_romask_244 = |_out_romask_T_244; // @[RegisterRouter.scala:87:24] wire out_womask_244 = &_out_womask_T_244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_244 = out_rivalid_1_98 & out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2809 = out_f_rivalid_244; // @[RegisterRouter.scala:87:24] wire out_f_roready_244 = out_roready_1_98 & out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2810 = out_f_roready_244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_244 = out_wivalid_1_98 & out_wimask_244; // @[RegisterRouter.scala:87:24] wire out_f_woready_244 = out_woready_1_98 & out_womask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2811 = ~out_rimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2812 = ~out_wimask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2813 = ~out_romask_244; // @[RegisterRouter.scala:87:24] wire _out_T_2814 = ~out_womask_244; // @[RegisterRouter.scala:87:24] wire out_rimask_245 = |_out_rimask_T_245; // @[RegisterRouter.scala:87:24] wire out_wimask_245 = &_out_wimask_T_245; // @[RegisterRouter.scala:87:24] wire out_romask_245 = |_out_romask_T_245; // @[RegisterRouter.scala:87:24] wire out_womask_245 = &_out_womask_T_245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_245 = out_rivalid_1_99 & out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2818 = out_f_rivalid_245; // @[RegisterRouter.scala:87:24] wire out_f_roready_245 = out_roready_1_99 & out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2819 = out_f_roready_245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_245 = out_wivalid_1_99 & out_wimask_245; // @[RegisterRouter.scala:87:24] wire out_f_woready_245 = out_woready_1_99 & out_womask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2820 = ~out_rimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2821 = ~out_wimask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2822 = ~out_romask_245; // @[RegisterRouter.scala:87:24] wire _out_T_2823 = ~out_womask_245; // @[RegisterRouter.scala:87:24] wire out_rimask_246 = |_out_rimask_T_246; // @[RegisterRouter.scala:87:24] wire out_wimask_246 = &_out_wimask_T_246; // @[RegisterRouter.scala:87:24] wire out_romask_246 = |_out_romask_T_246; // @[RegisterRouter.scala:87:24] wire out_womask_246 = &_out_womask_T_246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_246 = out_rivalid_1_100 & out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2827 = out_f_rivalid_246; // @[RegisterRouter.scala:87:24] wire out_f_roready_246 = out_roready_1_100 & out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2828 = out_f_roready_246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_246 = out_wivalid_1_100 & out_wimask_246; // @[RegisterRouter.scala:87:24] wire out_f_woready_246 = out_woready_1_100 & out_womask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2829 = ~out_rimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2830 = ~out_wimask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2831 = ~out_romask_246; // @[RegisterRouter.scala:87:24] wire _out_T_2832 = ~out_womask_246; // @[RegisterRouter.scala:87:24] wire out_rimask_247 = |_out_rimask_T_247; // @[RegisterRouter.scala:87:24] wire out_wimask_247 = &_out_wimask_T_247; // @[RegisterRouter.scala:87:24] wire out_romask_247 = |_out_romask_T_247; // @[RegisterRouter.scala:87:24] wire out_womask_247 = &_out_womask_T_247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_247 = out_rivalid_1_101 & out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2836 = out_f_rivalid_247; // @[RegisterRouter.scala:87:24] wire out_f_roready_247 = out_roready_1_101 & out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2837 = out_f_roready_247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_247 = out_wivalid_1_101 & out_wimask_247; // @[RegisterRouter.scala:87:24] wire out_f_woready_247 = out_woready_1_101 & out_womask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2838 = ~out_rimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2839 = ~out_wimask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2840 = ~out_romask_247; // @[RegisterRouter.scala:87:24] wire _out_T_2841 = ~out_womask_247; // @[RegisterRouter.scala:87:24] wire out_rimask_248 = |_out_rimask_T_248; // @[RegisterRouter.scala:87:24] wire out_wimask_248 = &_out_wimask_T_248; // @[RegisterRouter.scala:87:24] wire out_romask_248 = |_out_romask_T_248; // @[RegisterRouter.scala:87:24] wire out_womask_248 = &_out_womask_T_248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_248 = out_rivalid_1_102 & out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2845 = out_f_rivalid_248; // @[RegisterRouter.scala:87:24] wire out_f_roready_248 = out_roready_1_102 & out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2846 = out_f_roready_248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_248 = out_wivalid_1_102 & out_wimask_248; // @[RegisterRouter.scala:87:24] wire out_f_woready_248 = out_woready_1_102 & out_womask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2847 = ~out_rimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2848 = ~out_wimask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2849 = ~out_romask_248; // @[RegisterRouter.scala:87:24] wire _out_T_2850 = ~out_womask_248; // @[RegisterRouter.scala:87:24] wire out_rimask_249 = |_out_rimask_T_249; // @[RegisterRouter.scala:87:24] wire out_wimask_249 = &_out_wimask_T_249; // @[RegisterRouter.scala:87:24] wire out_romask_249 = |_out_romask_T_249; // @[RegisterRouter.scala:87:24] wire out_womask_249 = &_out_womask_T_249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_249 = out_rivalid_1_103 & out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2854 = out_f_rivalid_249; // @[RegisterRouter.scala:87:24] wire out_f_roready_249 = out_roready_1_103 & out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2855 = out_f_roready_249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_249 = out_wivalid_1_103 & out_wimask_249; // @[RegisterRouter.scala:87:24] wire out_f_woready_249 = out_woready_1_103 & out_womask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2856 = ~out_rimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2857 = ~out_wimask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2858 = ~out_romask_249; // @[RegisterRouter.scala:87:24] wire _out_T_2859 = ~out_womask_249; // @[RegisterRouter.scala:87:24] wire out_rimask_250 = |_out_rimask_T_250; // @[RegisterRouter.scala:87:24] wire out_wimask_250 = &_out_wimask_T_250; // @[RegisterRouter.scala:87:24] wire out_romask_250 = |_out_romask_T_250; // @[RegisterRouter.scala:87:24] wire out_womask_250 = &_out_womask_T_250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_250 = out_rivalid_1_104 & out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2863 = out_f_rivalid_250; // @[RegisterRouter.scala:87:24] wire out_f_roready_250 = out_roready_1_104 & out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2864 = out_f_roready_250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_250 = out_wivalid_1_104 & out_wimask_250; // @[RegisterRouter.scala:87:24] wire out_f_woready_250 = out_woready_1_104 & out_womask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2865 = ~out_rimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2866 = ~out_wimask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2867 = ~out_romask_250; // @[RegisterRouter.scala:87:24] wire _out_T_2868 = ~out_womask_250; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2870 = _out_T_2869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_203 = _out_T_2870; // @[RegisterRouter.scala:87:24] wire out_rimask_251 = |_out_rimask_T_251; // @[RegisterRouter.scala:87:24] wire out_wimask_251 = &_out_wimask_T_251; // @[RegisterRouter.scala:87:24] wire out_romask_251 = |_out_romask_T_251; // @[RegisterRouter.scala:87:24] wire out_womask_251 = &_out_womask_T_251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_251 = out_rivalid_1_105 & out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2872 = out_f_rivalid_251; // @[RegisterRouter.scala:87:24] wire out_f_roready_251 = out_roready_1_105 & out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2873 = out_f_roready_251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_251 = out_wivalid_1_105 & out_wimask_251; // @[RegisterRouter.scala:87:24] wire out_f_woready_251 = out_woready_1_105 & out_womask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2874 = ~out_rimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2875 = ~out_wimask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2876 = ~out_romask_251; // @[RegisterRouter.scala:87:24] wire _out_T_2877 = ~out_womask_251; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_203 = {hi_450, flags_0_go, _out_prepend_T_203}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2878 = out_prepend_203; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2879 = _out_T_2878; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_204 = _out_T_2879; // @[RegisterRouter.scala:87:24] wire out_rimask_252 = |_out_rimask_T_252; // @[RegisterRouter.scala:87:24] wire out_wimask_252 = &_out_wimask_T_252; // @[RegisterRouter.scala:87:24] wire out_romask_252 = |_out_romask_T_252; // @[RegisterRouter.scala:87:24] wire out_womask_252 = &_out_womask_T_252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_252 = out_rivalid_1_106 & out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2881 = out_f_rivalid_252; // @[RegisterRouter.scala:87:24] wire out_f_roready_252 = out_roready_1_106 & out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2882 = out_f_roready_252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_252 = out_wivalid_1_106 & out_wimask_252; // @[RegisterRouter.scala:87:24] wire out_f_woready_252 = out_woready_1_106 & out_womask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2883 = ~out_rimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2884 = ~out_wimask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2885 = ~out_romask_252; // @[RegisterRouter.scala:87:24] wire _out_T_2886 = ~out_womask_252; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_204 = {hi_451, flags_0_go, _out_prepend_T_204}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2887 = out_prepend_204; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2888 = _out_T_2887; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_205 = _out_T_2888; // @[RegisterRouter.scala:87:24] wire out_rimask_253 = |_out_rimask_T_253; // @[RegisterRouter.scala:87:24] wire out_wimask_253 = &_out_wimask_T_253; // @[RegisterRouter.scala:87:24] wire out_romask_253 = |_out_romask_T_253; // @[RegisterRouter.scala:87:24] wire out_womask_253 = &_out_womask_T_253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_253 = out_rivalid_1_107 & out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2890 = out_f_rivalid_253; // @[RegisterRouter.scala:87:24] wire out_f_roready_253 = out_roready_1_107 & out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2891 = out_f_roready_253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_253 = out_wivalid_1_107 & out_wimask_253; // @[RegisterRouter.scala:87:24] wire out_f_woready_253 = out_woready_1_107 & out_womask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2892 = ~out_rimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2893 = ~out_wimask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2894 = ~out_romask_253; // @[RegisterRouter.scala:87:24] wire _out_T_2895 = ~out_womask_253; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_205 = {hi_452, flags_0_go, _out_prepend_T_205}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2896 = out_prepend_205; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2897 = _out_T_2896; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_206 = _out_T_2897; // @[RegisterRouter.scala:87:24] wire out_rimask_254 = |_out_rimask_T_254; // @[RegisterRouter.scala:87:24] wire out_wimask_254 = &_out_wimask_T_254; // @[RegisterRouter.scala:87:24] wire out_romask_254 = |_out_romask_T_254; // @[RegisterRouter.scala:87:24] wire out_womask_254 = &_out_womask_T_254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_254 = out_rivalid_1_108 & out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2899 = out_f_rivalid_254; // @[RegisterRouter.scala:87:24] wire out_f_roready_254 = out_roready_1_108 & out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2900 = out_f_roready_254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_254 = out_wivalid_1_108 & out_wimask_254; // @[RegisterRouter.scala:87:24] wire out_f_woready_254 = out_woready_1_108 & out_womask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2901 = ~out_rimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2902 = ~out_wimask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2903 = ~out_romask_254; // @[RegisterRouter.scala:87:24] wire _out_T_2904 = ~out_womask_254; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_206 = {hi_453, flags_0_go, _out_prepend_T_206}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2905 = out_prepend_206; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2906 = _out_T_2905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_207 = _out_T_2906; // @[RegisterRouter.scala:87:24] wire out_rimask_255 = |_out_rimask_T_255; // @[RegisterRouter.scala:87:24] wire out_wimask_255 = &_out_wimask_T_255; // @[RegisterRouter.scala:87:24] wire out_romask_255 = |_out_romask_T_255; // @[RegisterRouter.scala:87:24] wire out_womask_255 = &_out_womask_T_255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_255 = out_rivalid_1_109 & out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2908 = out_f_rivalid_255; // @[RegisterRouter.scala:87:24] wire out_f_roready_255 = out_roready_1_109 & out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2909 = out_f_roready_255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_255 = out_wivalid_1_109 & out_wimask_255; // @[RegisterRouter.scala:87:24] wire out_f_woready_255 = out_woready_1_109 & out_womask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2910 = ~out_rimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2911 = ~out_wimask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2912 = ~out_romask_255; // @[RegisterRouter.scala:87:24] wire _out_T_2913 = ~out_womask_255; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_207 = {hi_454, flags_0_go, _out_prepend_T_207}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2914 = out_prepend_207; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2915 = _out_T_2914; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_208 = _out_T_2915; // @[RegisterRouter.scala:87:24] wire out_rimask_256 = |_out_rimask_T_256; // @[RegisterRouter.scala:87:24] wire out_wimask_256 = &_out_wimask_T_256; // @[RegisterRouter.scala:87:24] wire out_romask_256 = |_out_romask_T_256; // @[RegisterRouter.scala:87:24] wire out_womask_256 = &_out_womask_T_256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_256 = out_rivalid_1_110 & out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2917 = out_f_rivalid_256; // @[RegisterRouter.scala:87:24] wire out_f_roready_256 = out_roready_1_110 & out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2918 = out_f_roready_256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_256 = out_wivalid_1_110 & out_wimask_256; // @[RegisterRouter.scala:87:24] wire out_f_woready_256 = out_woready_1_110 & out_womask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2919 = ~out_rimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2920 = ~out_wimask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2921 = ~out_romask_256; // @[RegisterRouter.scala:87:24] wire _out_T_2922 = ~out_womask_256; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_208 = {hi_455, flags_0_go, _out_prepend_T_208}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2923 = out_prepend_208; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_2924 = _out_T_2923; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_209 = _out_T_2924; // @[RegisterRouter.scala:87:24] wire out_rimask_257 = |_out_rimask_T_257; // @[RegisterRouter.scala:87:24] wire out_wimask_257 = &_out_wimask_T_257; // @[RegisterRouter.scala:87:24] wire out_romask_257 = |_out_romask_T_257; // @[RegisterRouter.scala:87:24] wire out_womask_257 = &_out_womask_T_257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_257 = out_rivalid_1_111 & out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2926 = out_f_rivalid_257; // @[RegisterRouter.scala:87:24] wire out_f_roready_257 = out_roready_1_111 & out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2927 = out_f_roready_257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_257 = out_wivalid_1_111 & out_wimask_257; // @[RegisterRouter.scala:87:24] wire out_f_woready_257 = out_woready_1_111 & out_womask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2928 = ~out_rimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2929 = ~out_wimask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2930 = ~out_romask_257; // @[RegisterRouter.scala:87:24] wire _out_T_2931 = ~out_womask_257; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_209 = {hi_456, flags_0_go, _out_prepend_T_209}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2932 = out_prepend_209; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_2933 = _out_T_2932; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_184 = _out_T_2933; // @[MuxLiteral.scala:49:48] wire out_rimask_258 = |_out_rimask_T_258; // @[RegisterRouter.scala:87:24] wire out_wimask_258 = &_out_wimask_T_258; // @[RegisterRouter.scala:87:24] wire out_romask_258 = |_out_romask_T_258; // @[RegisterRouter.scala:87:24] wire out_womask_258 = &_out_womask_T_258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_258 = out_rivalid_1_112 & out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2935 = out_f_rivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_roready_258 = out_roready_1_112 & out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2936 = out_f_roready_258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_258 = out_wivalid_1_112 & out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2937 = out_f_wivalid_258; // @[RegisterRouter.scala:87:24] wire out_f_woready_258 = out_woready_1_112 & out_womask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2938 = out_f_woready_258; // @[RegisterRouter.scala:87:24] wire _out_T_2939 = ~out_rimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2940 = ~out_wimask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2941 = ~out_romask_258; // @[RegisterRouter.scala:87:24] wire _out_T_2942 = ~out_womask_258; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_2944 = _out_T_2943; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_210 = _out_T_2944; // @[RegisterRouter.scala:87:24] wire out_rimask_259 = |_out_rimask_T_259; // @[RegisterRouter.scala:87:24] wire out_wimask_259 = &_out_wimask_T_259; // @[RegisterRouter.scala:87:24] wire out_romask_259 = |_out_romask_T_259; // @[RegisterRouter.scala:87:24] wire out_womask_259 = &_out_womask_T_259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_259 = out_rivalid_1_113 & out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2946 = out_f_rivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_roready_259 = out_roready_1_113 & out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2947 = out_f_roready_259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_259 = out_wivalid_1_113 & out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2948 = out_f_wivalid_259; // @[RegisterRouter.scala:87:24] wire out_f_woready_259 = out_woready_1_113 & out_womask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2949 = out_f_woready_259; // @[RegisterRouter.scala:87:24] wire _out_T_2950 = ~out_rimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2951 = ~out_wimask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2952 = ~out_romask_259; // @[RegisterRouter.scala:87:24] wire _out_T_2953 = ~out_womask_259; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_210 = {programBufferMem_49, _out_prepend_T_210}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2954 = out_prepend_210; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_2955 = _out_T_2954; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_211 = _out_T_2955; // @[RegisterRouter.scala:87:24] wire out_rimask_260 = |_out_rimask_T_260; // @[RegisterRouter.scala:87:24] wire out_wimask_260 = &_out_wimask_T_260; // @[RegisterRouter.scala:87:24] wire out_romask_260 = |_out_romask_T_260; // @[RegisterRouter.scala:87:24] wire out_womask_260 = &_out_womask_T_260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_260 = out_rivalid_1_114 & out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2957 = out_f_rivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_roready_260 = out_roready_1_114 & out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2958 = out_f_roready_260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_260 = out_wivalid_1_114 & out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2959 = out_f_wivalid_260; // @[RegisterRouter.scala:87:24] wire out_f_woready_260 = out_woready_1_114 & out_womask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2960 = out_f_woready_260; // @[RegisterRouter.scala:87:24] wire _out_T_2961 = ~out_rimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2962 = ~out_wimask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2963 = ~out_romask_260; // @[RegisterRouter.scala:87:24] wire _out_T_2964 = ~out_womask_260; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_211 = {programBufferMem_50, _out_prepend_T_211}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2965 = out_prepend_211; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_2966 = _out_T_2965; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_212 = _out_T_2966; // @[RegisterRouter.scala:87:24] wire out_rimask_261 = |_out_rimask_T_261; // @[RegisterRouter.scala:87:24] wire out_wimask_261 = &_out_wimask_T_261; // @[RegisterRouter.scala:87:24] wire out_romask_261 = |_out_romask_T_261; // @[RegisterRouter.scala:87:24] wire out_womask_261 = &_out_womask_T_261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_261 = out_rivalid_1_115 & out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2968 = out_f_rivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_roready_261 = out_roready_1_115 & out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2969 = out_f_roready_261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_261 = out_wivalid_1_115 & out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2970 = out_f_wivalid_261; // @[RegisterRouter.scala:87:24] wire out_f_woready_261 = out_woready_1_115 & out_womask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2971 = out_f_woready_261; // @[RegisterRouter.scala:87:24] wire _out_T_2972 = ~out_rimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2973 = ~out_wimask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2974 = ~out_romask_261; // @[RegisterRouter.scala:87:24] wire _out_T_2975 = ~out_womask_261; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_212 = {programBufferMem_51, _out_prepend_T_212}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2976 = out_prepend_212; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_2977 = _out_T_2976; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_213 = _out_T_2977; // @[RegisterRouter.scala:87:24] wire out_rimask_262 = |_out_rimask_T_262; // @[RegisterRouter.scala:87:24] wire out_wimask_262 = &_out_wimask_T_262; // @[RegisterRouter.scala:87:24] wire out_romask_262 = |_out_romask_T_262; // @[RegisterRouter.scala:87:24] wire out_womask_262 = &_out_womask_T_262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_262 = out_rivalid_1_116 & out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2979 = out_f_rivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_roready_262 = out_roready_1_116 & out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2980 = out_f_roready_262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_262 = out_wivalid_1_116 & out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2981 = out_f_wivalid_262; // @[RegisterRouter.scala:87:24] wire out_f_woready_262 = out_woready_1_116 & out_womask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2982 = out_f_woready_262; // @[RegisterRouter.scala:87:24] wire _out_T_2983 = ~out_rimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2984 = ~out_wimask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2985 = ~out_romask_262; // @[RegisterRouter.scala:87:24] wire _out_T_2986 = ~out_womask_262; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_213 = {programBufferMem_52, _out_prepend_T_213}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2987 = out_prepend_213; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_2988 = _out_T_2987; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_214 = _out_T_2988; // @[RegisterRouter.scala:87:24] wire out_rimask_263 = |_out_rimask_T_263; // @[RegisterRouter.scala:87:24] wire out_wimask_263 = &_out_wimask_T_263; // @[RegisterRouter.scala:87:24] wire out_romask_263 = |_out_romask_T_263; // @[RegisterRouter.scala:87:24] wire out_womask_263 = &_out_womask_T_263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_263 = out_rivalid_1_117 & out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2990 = out_f_rivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_roready_263 = out_roready_1_117 & out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2991 = out_f_roready_263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_263 = out_wivalid_1_117 & out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2992 = out_f_wivalid_263; // @[RegisterRouter.scala:87:24] wire out_f_woready_263 = out_woready_1_117 & out_womask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2993 = out_f_woready_263; // @[RegisterRouter.scala:87:24] wire _out_T_2994 = ~out_rimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2995 = ~out_wimask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2996 = ~out_romask_263; // @[RegisterRouter.scala:87:24] wire _out_T_2997 = ~out_womask_263; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_214 = {programBufferMem_53, _out_prepend_T_214}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2998 = out_prepend_214; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_2999 = _out_T_2998; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_215 = _out_T_2999; // @[RegisterRouter.scala:87:24] wire out_rimask_264 = |_out_rimask_T_264; // @[RegisterRouter.scala:87:24] wire out_wimask_264 = &_out_wimask_T_264; // @[RegisterRouter.scala:87:24] wire out_romask_264 = |_out_romask_T_264; // @[RegisterRouter.scala:87:24] wire out_womask_264 = &_out_womask_T_264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_264 = out_rivalid_1_118 & out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3001 = out_f_rivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_roready_264 = out_roready_1_118 & out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3002 = out_f_roready_264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_264 = out_wivalid_1_118 & out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3003 = out_f_wivalid_264; // @[RegisterRouter.scala:87:24] wire out_f_woready_264 = out_woready_1_118 & out_womask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3004 = out_f_woready_264; // @[RegisterRouter.scala:87:24] wire _out_T_3005 = ~out_rimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3006 = ~out_wimask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3007 = ~out_romask_264; // @[RegisterRouter.scala:87:24] wire _out_T_3008 = ~out_womask_264; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_215 = {programBufferMem_54, _out_prepend_T_215}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3009 = out_prepend_215; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3010 = _out_T_3009; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_216 = _out_T_3010; // @[RegisterRouter.scala:87:24] wire out_rimask_265 = |_out_rimask_T_265; // @[RegisterRouter.scala:87:24] wire out_wimask_265 = &_out_wimask_T_265; // @[RegisterRouter.scala:87:24] wire out_romask_265 = |_out_romask_T_265; // @[RegisterRouter.scala:87:24] wire out_womask_265 = &_out_womask_T_265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_265 = out_rivalid_1_119 & out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3012 = out_f_rivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_roready_265 = out_roready_1_119 & out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3013 = out_f_roready_265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_265 = out_wivalid_1_119 & out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3014 = out_f_wivalid_265; // @[RegisterRouter.scala:87:24] wire out_f_woready_265 = out_woready_1_119 & out_womask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3015 = out_f_woready_265; // @[RegisterRouter.scala:87:24] wire _out_T_3016 = ~out_rimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3017 = ~out_wimask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3018 = ~out_romask_265; // @[RegisterRouter.scala:87:24] wire _out_T_3019 = ~out_womask_265; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_216 = {programBufferMem_55, _out_prepend_T_216}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3020 = out_prepend_216; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3021 = _out_T_3020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_110 = _out_T_3021; // @[MuxLiteral.scala:49:48] wire out_rimask_266 = |_out_rimask_T_266; // @[RegisterRouter.scala:87:24] wire out_wimask_266 = &_out_wimask_T_266; // @[RegisterRouter.scala:87:24] wire out_romask_266 = |_out_romask_T_266; // @[RegisterRouter.scala:87:24] wire out_womask_266 = &_out_womask_T_266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_266 = out_rivalid_1_120 & out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3023 = out_f_rivalid_266; // @[RegisterRouter.scala:87:24] wire out_f_roready_266 = out_roready_1_120 & out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3024 = out_f_roready_266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_266 = out_wivalid_1_120 & out_wimask_266; // @[RegisterRouter.scala:87:24] wire out_f_woready_266 = out_woready_1_120 & out_womask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3025 = ~out_rimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3026 = ~out_wimask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3027 = ~out_romask_266; // @[RegisterRouter.scala:87:24] wire _out_T_3028 = ~out_womask_266; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3030 = _out_T_3029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_217 = _out_T_3030; // @[RegisterRouter.scala:87:24] wire out_rimask_267 = |_out_rimask_T_267; // @[RegisterRouter.scala:87:24] wire out_wimask_267 = &_out_wimask_T_267; // @[RegisterRouter.scala:87:24] wire out_romask_267 = |_out_romask_T_267; // @[RegisterRouter.scala:87:24] wire out_womask_267 = &_out_womask_T_267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_267 = out_rivalid_1_121 & out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3032 = out_f_rivalid_267; // @[RegisterRouter.scala:87:24] wire out_f_roready_267 = out_roready_1_121 & out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3033 = out_f_roready_267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_267 = out_wivalid_1_121 & out_wimask_267; // @[RegisterRouter.scala:87:24] wire out_f_woready_267 = out_woready_1_121 & out_womask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3034 = ~out_rimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3035 = ~out_wimask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3036 = ~out_romask_267; // @[RegisterRouter.scala:87:24] wire _out_T_3037 = ~out_womask_267; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_217 = {hi_546, flags_0_go, _out_prepend_T_217}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3038 = out_prepend_217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3039 = _out_T_3038; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_218 = _out_T_3039; // @[RegisterRouter.scala:87:24] wire out_rimask_268 = |_out_rimask_T_268; // @[RegisterRouter.scala:87:24] wire out_wimask_268 = &_out_wimask_T_268; // @[RegisterRouter.scala:87:24] wire out_romask_268 = |_out_romask_T_268; // @[RegisterRouter.scala:87:24] wire out_womask_268 = &_out_womask_T_268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_268 = out_rivalid_1_122 & out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3041 = out_f_rivalid_268; // @[RegisterRouter.scala:87:24] wire out_f_roready_268 = out_roready_1_122 & out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3042 = out_f_roready_268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_268 = out_wivalid_1_122 & out_wimask_268; // @[RegisterRouter.scala:87:24] wire out_f_woready_268 = out_woready_1_122 & out_womask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3043 = ~out_rimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3044 = ~out_wimask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3045 = ~out_romask_268; // @[RegisterRouter.scala:87:24] wire _out_T_3046 = ~out_womask_268; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_218 = {hi_547, flags_0_go, _out_prepend_T_218}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3047 = out_prepend_218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3048 = _out_T_3047; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_219 = _out_T_3048; // @[RegisterRouter.scala:87:24] wire out_rimask_269 = |_out_rimask_T_269; // @[RegisterRouter.scala:87:24] wire out_wimask_269 = &_out_wimask_T_269; // @[RegisterRouter.scala:87:24] wire out_romask_269 = |_out_romask_T_269; // @[RegisterRouter.scala:87:24] wire out_womask_269 = &_out_womask_T_269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_269 = out_rivalid_1_123 & out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3050 = out_f_rivalid_269; // @[RegisterRouter.scala:87:24] wire out_f_roready_269 = out_roready_1_123 & out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3051 = out_f_roready_269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_269 = out_wivalid_1_123 & out_wimask_269; // @[RegisterRouter.scala:87:24] wire out_f_woready_269 = out_woready_1_123 & out_womask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3052 = ~out_rimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3053 = ~out_wimask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3054 = ~out_romask_269; // @[RegisterRouter.scala:87:24] wire _out_T_3055 = ~out_womask_269; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_219 = {hi_548, flags_0_go, _out_prepend_T_219}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3056 = out_prepend_219; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3057 = _out_T_3056; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_220 = _out_T_3057; // @[RegisterRouter.scala:87:24] wire out_rimask_270 = |_out_rimask_T_270; // @[RegisterRouter.scala:87:24] wire out_wimask_270 = &_out_wimask_T_270; // @[RegisterRouter.scala:87:24] wire out_romask_270 = |_out_romask_T_270; // @[RegisterRouter.scala:87:24] wire out_womask_270 = &_out_womask_T_270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_270 = out_rivalid_1_124 & out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3059 = out_f_rivalid_270; // @[RegisterRouter.scala:87:24] wire out_f_roready_270 = out_roready_1_124 & out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3060 = out_f_roready_270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_270 = out_wivalid_1_124 & out_wimask_270; // @[RegisterRouter.scala:87:24] wire out_f_woready_270 = out_woready_1_124 & out_womask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3061 = ~out_rimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3062 = ~out_wimask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3063 = ~out_romask_270; // @[RegisterRouter.scala:87:24] wire _out_T_3064 = ~out_womask_270; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_220 = {hi_549, flags_0_go, _out_prepend_T_220}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3065 = out_prepend_220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3066 = _out_T_3065; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_221 = _out_T_3066; // @[RegisterRouter.scala:87:24] wire out_rimask_271 = |_out_rimask_T_271; // @[RegisterRouter.scala:87:24] wire out_wimask_271 = &_out_wimask_T_271; // @[RegisterRouter.scala:87:24] wire out_romask_271 = |_out_romask_T_271; // @[RegisterRouter.scala:87:24] wire out_womask_271 = &_out_womask_T_271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_271 = out_rivalid_1_125 & out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3068 = out_f_rivalid_271; // @[RegisterRouter.scala:87:24] wire out_f_roready_271 = out_roready_1_125 & out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3069 = out_f_roready_271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_271 = out_wivalid_1_125 & out_wimask_271; // @[RegisterRouter.scala:87:24] wire out_f_woready_271 = out_woready_1_125 & out_womask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3070 = ~out_rimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3071 = ~out_wimask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3072 = ~out_romask_271; // @[RegisterRouter.scala:87:24] wire _out_T_3073 = ~out_womask_271; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_221 = {hi_550, flags_0_go, _out_prepend_T_221}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3074 = out_prepend_221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3075 = _out_T_3074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_222 = _out_T_3075; // @[RegisterRouter.scala:87:24] wire out_rimask_272 = |_out_rimask_T_272; // @[RegisterRouter.scala:87:24] wire out_wimask_272 = &_out_wimask_T_272; // @[RegisterRouter.scala:87:24] wire out_romask_272 = |_out_romask_T_272; // @[RegisterRouter.scala:87:24] wire out_womask_272 = &_out_womask_T_272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_272 = out_rivalid_1_126 & out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3077 = out_f_rivalid_272; // @[RegisterRouter.scala:87:24] wire out_f_roready_272 = out_roready_1_126 & out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3078 = out_f_roready_272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_272 = out_wivalid_1_126 & out_wimask_272; // @[RegisterRouter.scala:87:24] wire out_f_woready_272 = out_woready_1_126 & out_womask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3079 = ~out_rimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3080 = ~out_wimask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3081 = ~out_romask_272; // @[RegisterRouter.scala:87:24] wire _out_T_3082 = ~out_womask_272; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_222 = {hi_551, flags_0_go, _out_prepend_T_222}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3083 = out_prepend_222; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3084 = _out_T_3083; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_223 = _out_T_3084; // @[RegisterRouter.scala:87:24] wire out_rimask_273 = |_out_rimask_T_273; // @[RegisterRouter.scala:87:24] wire out_wimask_273 = &_out_wimask_T_273; // @[RegisterRouter.scala:87:24] wire out_romask_273 = |_out_romask_T_273; // @[RegisterRouter.scala:87:24] wire out_womask_273 = &_out_womask_T_273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_273 = out_rivalid_1_127 & out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3086 = out_f_rivalid_273; // @[RegisterRouter.scala:87:24] wire out_f_roready_273 = out_roready_1_127 & out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3087 = out_f_roready_273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_273 = out_wivalid_1_127 & out_wimask_273; // @[RegisterRouter.scala:87:24] wire out_f_woready_273 = out_woready_1_127 & out_womask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3088 = ~out_rimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3089 = ~out_wimask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3090 = ~out_romask_273; // @[RegisterRouter.scala:87:24] wire _out_T_3091 = ~out_womask_273; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_223 = {hi_552, flags_0_go, _out_prepend_T_223}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3092 = out_prepend_223; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3093 = _out_T_3092; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_196 = _out_T_3093; // @[MuxLiteral.scala:49:48] wire out_rimask_274 = |_out_rimask_T_274; // @[RegisterRouter.scala:87:24] wire out_wimask_274 = &_out_wimask_T_274; // @[RegisterRouter.scala:87:24] wire out_romask_274 = |_out_romask_T_274; // @[RegisterRouter.scala:87:24] wire out_womask_274 = &_out_womask_T_274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_274 = out_rivalid_1_128 & out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3095 = out_f_rivalid_274; // @[RegisterRouter.scala:87:24] wire out_f_roready_274 = out_roready_1_128 & out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3096 = out_f_roready_274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_274 = out_wivalid_1_128 & out_wimask_274; // @[RegisterRouter.scala:87:24] wire out_f_woready_274 = out_woready_1_128 & out_womask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3097 = ~out_rimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3098 = ~out_wimask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3099 = ~out_romask_274; // @[RegisterRouter.scala:87:24] wire _out_T_3100 = ~out_womask_274; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3102 = _out_T_3101; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_224 = _out_T_3102; // @[RegisterRouter.scala:87:24] wire out_rimask_275 = |_out_rimask_T_275; // @[RegisterRouter.scala:87:24] wire out_wimask_275 = &_out_wimask_T_275; // @[RegisterRouter.scala:87:24] wire out_romask_275 = |_out_romask_T_275; // @[RegisterRouter.scala:87:24] wire out_womask_275 = &_out_womask_T_275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_275 = out_rivalid_1_129 & out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3104 = out_f_rivalid_275; // @[RegisterRouter.scala:87:24] wire out_f_roready_275 = out_roready_1_129 & out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3105 = out_f_roready_275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_275 = out_wivalid_1_129 & out_wimask_275; // @[RegisterRouter.scala:87:24] wire out_f_woready_275 = out_woready_1_129 & out_womask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3106 = ~out_rimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3107 = ~out_wimask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3108 = ~out_romask_275; // @[RegisterRouter.scala:87:24] wire _out_T_3109 = ~out_womask_275; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_224 = {hi_234, flags_0_go, _out_prepend_T_224}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3110 = out_prepend_224; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3111 = _out_T_3110; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_225 = _out_T_3111; // @[RegisterRouter.scala:87:24] wire out_rimask_276 = |_out_rimask_T_276; // @[RegisterRouter.scala:87:24] wire out_wimask_276 = &_out_wimask_T_276; // @[RegisterRouter.scala:87:24] wire out_romask_276 = |_out_romask_T_276; // @[RegisterRouter.scala:87:24] wire out_womask_276 = &_out_womask_T_276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_276 = out_rivalid_1_130 & out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3113 = out_f_rivalid_276; // @[RegisterRouter.scala:87:24] wire out_f_roready_276 = out_roready_1_130 & out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3114 = out_f_roready_276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_276 = out_wivalid_1_130 & out_wimask_276; // @[RegisterRouter.scala:87:24] wire out_f_woready_276 = out_woready_1_130 & out_womask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3115 = ~out_rimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3116 = ~out_wimask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3117 = ~out_romask_276; // @[RegisterRouter.scala:87:24] wire _out_T_3118 = ~out_womask_276; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_225 = {hi_235, flags_0_go, _out_prepend_T_225}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3119 = out_prepend_225; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3120 = _out_T_3119; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_226 = _out_T_3120; // @[RegisterRouter.scala:87:24] wire out_rimask_277 = |_out_rimask_T_277; // @[RegisterRouter.scala:87:24] wire out_wimask_277 = &_out_wimask_T_277; // @[RegisterRouter.scala:87:24] wire out_romask_277 = |_out_romask_T_277; // @[RegisterRouter.scala:87:24] wire out_womask_277 = &_out_womask_T_277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_277 = out_rivalid_1_131 & out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3122 = out_f_rivalid_277; // @[RegisterRouter.scala:87:24] wire out_f_roready_277 = out_roready_1_131 & out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3123 = out_f_roready_277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_277 = out_wivalid_1_131 & out_wimask_277; // @[RegisterRouter.scala:87:24] wire out_f_woready_277 = out_woready_1_131 & out_womask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3124 = ~out_rimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3125 = ~out_wimask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3126 = ~out_romask_277; // @[RegisterRouter.scala:87:24] wire _out_T_3127 = ~out_womask_277; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_226 = {hi_236, flags_0_go, _out_prepend_T_226}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3128 = out_prepend_226; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3129 = _out_T_3128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_227 = _out_T_3129; // @[RegisterRouter.scala:87:24] wire out_rimask_278 = |_out_rimask_T_278; // @[RegisterRouter.scala:87:24] wire out_wimask_278 = &_out_wimask_T_278; // @[RegisterRouter.scala:87:24] wire out_romask_278 = |_out_romask_T_278; // @[RegisterRouter.scala:87:24] wire out_womask_278 = &_out_womask_T_278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_278 = out_rivalid_1_132 & out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3131 = out_f_rivalid_278; // @[RegisterRouter.scala:87:24] wire out_f_roready_278 = out_roready_1_132 & out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3132 = out_f_roready_278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_278 = out_wivalid_1_132 & out_wimask_278; // @[RegisterRouter.scala:87:24] wire out_f_woready_278 = out_woready_1_132 & out_womask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3133 = ~out_rimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3134 = ~out_wimask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3135 = ~out_romask_278; // @[RegisterRouter.scala:87:24] wire _out_T_3136 = ~out_womask_278; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_227 = {hi_237, flags_0_go, _out_prepend_T_227}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3137 = out_prepend_227; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3138 = _out_T_3137; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_228 = _out_T_3138; // @[RegisterRouter.scala:87:24] wire out_rimask_279 = |_out_rimask_T_279; // @[RegisterRouter.scala:87:24] wire out_wimask_279 = &_out_wimask_T_279; // @[RegisterRouter.scala:87:24] wire out_romask_279 = |_out_romask_T_279; // @[RegisterRouter.scala:87:24] wire out_womask_279 = &_out_womask_T_279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_279 = out_rivalid_1_133 & out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3140 = out_f_rivalid_279; // @[RegisterRouter.scala:87:24] wire out_f_roready_279 = out_roready_1_133 & out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3141 = out_f_roready_279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_279 = out_wivalid_1_133 & out_wimask_279; // @[RegisterRouter.scala:87:24] wire out_f_woready_279 = out_woready_1_133 & out_womask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3142 = ~out_rimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3143 = ~out_wimask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3144 = ~out_romask_279; // @[RegisterRouter.scala:87:24] wire _out_T_3145 = ~out_womask_279; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_228 = {hi_238, flags_0_go, _out_prepend_T_228}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3146 = out_prepend_228; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3147 = _out_T_3146; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_229 = _out_T_3147; // @[RegisterRouter.scala:87:24] wire out_rimask_280 = |_out_rimask_T_280; // @[RegisterRouter.scala:87:24] wire out_wimask_280 = &_out_wimask_T_280; // @[RegisterRouter.scala:87:24] wire out_romask_280 = |_out_romask_T_280; // @[RegisterRouter.scala:87:24] wire out_womask_280 = &_out_womask_T_280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_280 = out_rivalid_1_134 & out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3149 = out_f_rivalid_280; // @[RegisterRouter.scala:87:24] wire out_f_roready_280 = out_roready_1_134 & out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3150 = out_f_roready_280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_280 = out_wivalid_1_134 & out_wimask_280; // @[RegisterRouter.scala:87:24] wire out_f_woready_280 = out_woready_1_134 & out_womask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3151 = ~out_rimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3152 = ~out_wimask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3153 = ~out_romask_280; // @[RegisterRouter.scala:87:24] wire _out_T_3154 = ~out_womask_280; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_229 = {hi_239, flags_0_go, _out_prepend_T_229}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3155 = out_prepend_229; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3156 = _out_T_3155; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_230 = _out_T_3156; // @[RegisterRouter.scala:87:24] wire out_rimask_281 = |_out_rimask_T_281; // @[RegisterRouter.scala:87:24] wire out_wimask_281 = &_out_wimask_T_281; // @[RegisterRouter.scala:87:24] wire out_romask_281 = |_out_romask_T_281; // @[RegisterRouter.scala:87:24] wire out_womask_281 = &_out_womask_T_281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_281 = out_rivalid_1_135 & out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3158 = out_f_rivalid_281; // @[RegisterRouter.scala:87:24] wire out_f_roready_281 = out_roready_1_135 & out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3159 = out_f_roready_281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_281 = out_wivalid_1_135 & out_wimask_281; // @[RegisterRouter.scala:87:24] wire out_f_woready_281 = out_woready_1_135 & out_womask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3160 = ~out_rimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3161 = ~out_wimask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3162 = ~out_romask_281; // @[RegisterRouter.scala:87:24] wire _out_T_3163 = ~out_womask_281; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_230 = {hi_240, flags_0_go, _out_prepend_T_230}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3164 = out_prepend_230; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3165 = _out_T_3164; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_157 = _out_T_3165; // @[MuxLiteral.scala:49:48] wire out_rimask_282 = |_out_rimask_T_282; // @[RegisterRouter.scala:87:24] wire out_wimask_282 = &_out_wimask_T_282; // @[RegisterRouter.scala:87:24] wire out_romask_282 = |_out_romask_T_282; // @[RegisterRouter.scala:87:24] wire out_womask_282 = &_out_womask_T_282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_282 = out_rivalid_1_136 & out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3167 = out_f_rivalid_282; // @[RegisterRouter.scala:87:24] wire out_f_roready_282 = out_roready_1_136 & out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3168 = out_f_roready_282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_282 = out_wivalid_1_136 & out_wimask_282; // @[RegisterRouter.scala:87:24] wire out_f_woready_282 = out_woready_1_136 & out_womask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3169 = ~out_rimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3170 = ~out_wimask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3171 = ~out_romask_282; // @[RegisterRouter.scala:87:24] wire _out_T_3172 = ~out_womask_282; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3174 = _out_T_3173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_231 = _out_T_3174; // @[RegisterRouter.scala:87:24] wire out_rimask_283 = |_out_rimask_T_283; // @[RegisterRouter.scala:87:24] wire out_wimask_283 = &_out_wimask_T_283; // @[RegisterRouter.scala:87:24] wire out_romask_283 = |_out_romask_T_283; // @[RegisterRouter.scala:87:24] wire out_womask_283 = &_out_womask_T_283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_283 = out_rivalid_1_137 & out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3176 = out_f_rivalid_283; // @[RegisterRouter.scala:87:24] wire out_f_roready_283 = out_roready_1_137 & out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3177 = out_f_roready_283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_283 = out_wivalid_1_137 & out_wimask_283; // @[RegisterRouter.scala:87:24] wire out_f_woready_283 = out_woready_1_137 & out_womask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3178 = ~out_rimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3179 = ~out_wimask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3180 = ~out_romask_283; // @[RegisterRouter.scala:87:24] wire _out_T_3181 = ~out_womask_283; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_231 = {hi_490, flags_0_go, _out_prepend_T_231}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3182 = out_prepend_231; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3183 = _out_T_3182; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_232 = _out_T_3183; // @[RegisterRouter.scala:87:24] wire out_rimask_284 = |_out_rimask_T_284; // @[RegisterRouter.scala:87:24] wire out_wimask_284 = &_out_wimask_T_284; // @[RegisterRouter.scala:87:24] wire out_romask_284 = |_out_romask_T_284; // @[RegisterRouter.scala:87:24] wire out_womask_284 = &_out_womask_T_284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_284 = out_rivalid_1_138 & out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3185 = out_f_rivalid_284; // @[RegisterRouter.scala:87:24] wire out_f_roready_284 = out_roready_1_138 & out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3186 = out_f_roready_284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_284 = out_wivalid_1_138 & out_wimask_284; // @[RegisterRouter.scala:87:24] wire out_f_woready_284 = out_woready_1_138 & out_womask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3187 = ~out_rimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3188 = ~out_wimask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3189 = ~out_romask_284; // @[RegisterRouter.scala:87:24] wire _out_T_3190 = ~out_womask_284; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_232 = {hi_491, flags_0_go, _out_prepend_T_232}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3191 = out_prepend_232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3192 = _out_T_3191; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_233 = _out_T_3192; // @[RegisterRouter.scala:87:24] wire out_rimask_285 = |_out_rimask_T_285; // @[RegisterRouter.scala:87:24] wire out_wimask_285 = &_out_wimask_T_285; // @[RegisterRouter.scala:87:24] wire out_romask_285 = |_out_romask_T_285; // @[RegisterRouter.scala:87:24] wire out_womask_285 = &_out_womask_T_285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_285 = out_rivalid_1_139 & out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3194 = out_f_rivalid_285; // @[RegisterRouter.scala:87:24] wire out_f_roready_285 = out_roready_1_139 & out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3195 = out_f_roready_285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_285 = out_wivalid_1_139 & out_wimask_285; // @[RegisterRouter.scala:87:24] wire out_f_woready_285 = out_woready_1_139 & out_womask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3196 = ~out_rimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3197 = ~out_wimask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3198 = ~out_romask_285; // @[RegisterRouter.scala:87:24] wire _out_T_3199 = ~out_womask_285; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_233 = {hi_492, flags_0_go, _out_prepend_T_233}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3200 = out_prepend_233; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3201 = _out_T_3200; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_234 = _out_T_3201; // @[RegisterRouter.scala:87:24] wire out_rimask_286 = |_out_rimask_T_286; // @[RegisterRouter.scala:87:24] wire out_wimask_286 = &_out_wimask_T_286; // @[RegisterRouter.scala:87:24] wire out_romask_286 = |_out_romask_T_286; // @[RegisterRouter.scala:87:24] wire out_womask_286 = &_out_womask_T_286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_286 = out_rivalid_1_140 & out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3203 = out_f_rivalid_286; // @[RegisterRouter.scala:87:24] wire out_f_roready_286 = out_roready_1_140 & out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3204 = out_f_roready_286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_286 = out_wivalid_1_140 & out_wimask_286; // @[RegisterRouter.scala:87:24] wire out_f_woready_286 = out_woready_1_140 & out_womask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3205 = ~out_rimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3206 = ~out_wimask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3207 = ~out_romask_286; // @[RegisterRouter.scala:87:24] wire _out_T_3208 = ~out_womask_286; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_234 = {hi_493, flags_0_go, _out_prepend_T_234}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3209 = out_prepend_234; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3210 = _out_T_3209; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_235 = _out_T_3210; // @[RegisterRouter.scala:87:24] wire out_rimask_287 = |_out_rimask_T_287; // @[RegisterRouter.scala:87:24] wire out_wimask_287 = &_out_wimask_T_287; // @[RegisterRouter.scala:87:24] wire out_romask_287 = |_out_romask_T_287; // @[RegisterRouter.scala:87:24] wire out_womask_287 = &_out_womask_T_287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_287 = out_rivalid_1_141 & out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3212 = out_f_rivalid_287; // @[RegisterRouter.scala:87:24] wire out_f_roready_287 = out_roready_1_141 & out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3213 = out_f_roready_287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_287 = out_wivalid_1_141 & out_wimask_287; // @[RegisterRouter.scala:87:24] wire out_f_woready_287 = out_woready_1_141 & out_womask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3214 = ~out_rimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3215 = ~out_wimask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3216 = ~out_romask_287; // @[RegisterRouter.scala:87:24] wire _out_T_3217 = ~out_womask_287; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_235 = {hi_494, flags_0_go, _out_prepend_T_235}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3218 = out_prepend_235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3219 = _out_T_3218; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_236 = _out_T_3219; // @[RegisterRouter.scala:87:24] wire out_rimask_288 = |_out_rimask_T_288; // @[RegisterRouter.scala:87:24] wire out_wimask_288 = &_out_wimask_T_288; // @[RegisterRouter.scala:87:24] wire out_romask_288 = |_out_romask_T_288; // @[RegisterRouter.scala:87:24] wire out_womask_288 = &_out_womask_T_288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_288 = out_rivalid_1_142 & out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3221 = out_f_rivalid_288; // @[RegisterRouter.scala:87:24] wire out_f_roready_288 = out_roready_1_142 & out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3222 = out_f_roready_288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_288 = out_wivalid_1_142 & out_wimask_288; // @[RegisterRouter.scala:87:24] wire out_f_woready_288 = out_woready_1_142 & out_womask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3223 = ~out_rimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3224 = ~out_wimask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3225 = ~out_romask_288; // @[RegisterRouter.scala:87:24] wire _out_T_3226 = ~out_womask_288; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_236 = {hi_495, flags_0_go, _out_prepend_T_236}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3227 = out_prepend_236; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3228 = _out_T_3227; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_237 = _out_T_3228; // @[RegisterRouter.scala:87:24] wire out_rimask_289 = |_out_rimask_T_289; // @[RegisterRouter.scala:87:24] wire out_wimask_289 = &_out_wimask_T_289; // @[RegisterRouter.scala:87:24] wire out_romask_289 = |_out_romask_T_289; // @[RegisterRouter.scala:87:24] wire out_womask_289 = &_out_womask_T_289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_289 = out_rivalid_1_143 & out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3230 = out_f_rivalid_289; // @[RegisterRouter.scala:87:24] wire out_f_roready_289 = out_roready_1_143 & out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3231 = out_f_roready_289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_289 = out_wivalid_1_143 & out_wimask_289; // @[RegisterRouter.scala:87:24] wire out_f_woready_289 = out_woready_1_143 & out_womask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3232 = ~out_rimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3233 = ~out_wimask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3234 = ~out_romask_289; // @[RegisterRouter.scala:87:24] wire _out_T_3235 = ~out_womask_289; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_237 = {hi_496, flags_0_go, _out_prepend_T_237}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3236 = out_prepend_237; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3237 = _out_T_3236; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_189 = _out_T_3237; // @[MuxLiteral.scala:49:48] wire out_rimask_290 = |_out_rimask_T_290; // @[RegisterRouter.scala:87:24] wire out_wimask_290 = &_out_wimask_T_290; // @[RegisterRouter.scala:87:24] wire out_romask_290 = |_out_romask_T_290; // @[RegisterRouter.scala:87:24] wire out_womask_290 = &_out_womask_T_290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_290 = out_rivalid_1_144 & out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3239 = out_f_rivalid_290; // @[RegisterRouter.scala:87:24] wire out_f_roready_290 = out_roready_1_144 & out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3240 = out_f_roready_290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_290 = out_wivalid_1_144 & out_wimask_290; // @[RegisterRouter.scala:87:24] wire out_f_woready_290 = out_woready_1_144 & out_womask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3241 = ~out_rimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3242 = ~out_wimask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3243 = ~out_romask_290; // @[RegisterRouter.scala:87:24] wire _out_T_3244 = ~out_womask_290; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3246 = _out_T_3245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_238 = _out_T_3246; // @[RegisterRouter.scala:87:24] wire out_rimask_291 = |_out_rimask_T_291; // @[RegisterRouter.scala:87:24] wire out_wimask_291 = &_out_wimask_T_291; // @[RegisterRouter.scala:87:24] wire out_romask_291 = |_out_romask_T_291; // @[RegisterRouter.scala:87:24] wire out_womask_291 = &_out_womask_T_291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_291 = out_rivalid_1_145 & out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3248 = out_f_rivalid_291; // @[RegisterRouter.scala:87:24] wire out_f_roready_291 = out_roready_1_145 & out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3249 = out_f_roready_291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_291 = out_wivalid_1_145 & out_wimask_291; // @[RegisterRouter.scala:87:24] wire out_f_woready_291 = out_woready_1_145 & out_womask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3250 = ~out_rimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3251 = ~out_wimask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3252 = ~out_romask_291; // @[RegisterRouter.scala:87:24] wire _out_T_3253 = ~out_womask_291; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_238 = {hi_194, flags_0_go, _out_prepend_T_238}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3254 = out_prepend_238; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3255 = _out_T_3254; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_239 = _out_T_3255; // @[RegisterRouter.scala:87:24] wire out_rimask_292 = |_out_rimask_T_292; // @[RegisterRouter.scala:87:24] wire out_wimask_292 = &_out_wimask_T_292; // @[RegisterRouter.scala:87:24] wire out_romask_292 = |_out_romask_T_292; // @[RegisterRouter.scala:87:24] wire out_womask_292 = &_out_womask_T_292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_292 = out_rivalid_1_146 & out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3257 = out_f_rivalid_292; // @[RegisterRouter.scala:87:24] wire out_f_roready_292 = out_roready_1_146 & out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3258 = out_f_roready_292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_292 = out_wivalid_1_146 & out_wimask_292; // @[RegisterRouter.scala:87:24] wire out_f_woready_292 = out_woready_1_146 & out_womask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3259 = ~out_rimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3260 = ~out_wimask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3261 = ~out_romask_292; // @[RegisterRouter.scala:87:24] wire _out_T_3262 = ~out_womask_292; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_239 = {hi_195, flags_0_go, _out_prepend_T_239}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3263 = out_prepend_239; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3264 = _out_T_3263; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_240 = _out_T_3264; // @[RegisterRouter.scala:87:24] wire out_rimask_293 = |_out_rimask_T_293; // @[RegisterRouter.scala:87:24] wire out_wimask_293 = &_out_wimask_T_293; // @[RegisterRouter.scala:87:24] wire out_romask_293 = |_out_romask_T_293; // @[RegisterRouter.scala:87:24] wire out_womask_293 = &_out_womask_T_293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_293 = out_rivalid_1_147 & out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3266 = out_f_rivalid_293; // @[RegisterRouter.scala:87:24] wire out_f_roready_293 = out_roready_1_147 & out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3267 = out_f_roready_293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_293 = out_wivalid_1_147 & out_wimask_293; // @[RegisterRouter.scala:87:24] wire out_f_woready_293 = out_woready_1_147 & out_womask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3268 = ~out_rimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3269 = ~out_wimask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3270 = ~out_romask_293; // @[RegisterRouter.scala:87:24] wire _out_T_3271 = ~out_womask_293; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_240 = {hi_196, flags_0_go, _out_prepend_T_240}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3272 = out_prepend_240; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3273 = _out_T_3272; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_241 = _out_T_3273; // @[RegisterRouter.scala:87:24] wire out_rimask_294 = |_out_rimask_T_294; // @[RegisterRouter.scala:87:24] wire out_wimask_294 = &_out_wimask_T_294; // @[RegisterRouter.scala:87:24] wire out_romask_294 = |_out_romask_T_294; // @[RegisterRouter.scala:87:24] wire out_womask_294 = &_out_womask_T_294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_294 = out_rivalid_1_148 & out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3275 = out_f_rivalid_294; // @[RegisterRouter.scala:87:24] wire out_f_roready_294 = out_roready_1_148 & out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3276 = out_f_roready_294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_294 = out_wivalid_1_148 & out_wimask_294; // @[RegisterRouter.scala:87:24] wire out_f_woready_294 = out_woready_1_148 & out_womask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3277 = ~out_rimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3278 = ~out_wimask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3279 = ~out_romask_294; // @[RegisterRouter.scala:87:24] wire _out_T_3280 = ~out_womask_294; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_241 = {hi_197, flags_0_go, _out_prepend_T_241}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3281 = out_prepend_241; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3282 = _out_T_3281; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_242 = _out_T_3282; // @[RegisterRouter.scala:87:24] wire out_rimask_295 = |_out_rimask_T_295; // @[RegisterRouter.scala:87:24] wire out_wimask_295 = &_out_wimask_T_295; // @[RegisterRouter.scala:87:24] wire out_romask_295 = |_out_romask_T_295; // @[RegisterRouter.scala:87:24] wire out_womask_295 = &_out_womask_T_295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_295 = out_rivalid_1_149 & out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3284 = out_f_rivalid_295; // @[RegisterRouter.scala:87:24] wire out_f_roready_295 = out_roready_1_149 & out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3285 = out_f_roready_295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_295 = out_wivalid_1_149 & out_wimask_295; // @[RegisterRouter.scala:87:24] wire out_f_woready_295 = out_woready_1_149 & out_womask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3286 = ~out_rimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3287 = ~out_wimask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3288 = ~out_romask_295; // @[RegisterRouter.scala:87:24] wire _out_T_3289 = ~out_womask_295; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_242 = {hi_198, flags_0_go, _out_prepend_T_242}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3290 = out_prepend_242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3291 = _out_T_3290; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_243 = _out_T_3291; // @[RegisterRouter.scala:87:24] wire out_rimask_296 = |_out_rimask_T_296; // @[RegisterRouter.scala:87:24] wire out_wimask_296 = &_out_wimask_T_296; // @[RegisterRouter.scala:87:24] wire out_romask_296 = |_out_romask_T_296; // @[RegisterRouter.scala:87:24] wire out_womask_296 = &_out_womask_T_296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_296 = out_rivalid_1_150 & out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3293 = out_f_rivalid_296; // @[RegisterRouter.scala:87:24] wire out_f_roready_296 = out_roready_1_150 & out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3294 = out_f_roready_296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_296 = out_wivalid_1_150 & out_wimask_296; // @[RegisterRouter.scala:87:24] wire out_f_woready_296 = out_woready_1_150 & out_womask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3295 = ~out_rimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3296 = ~out_wimask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3297 = ~out_romask_296; // @[RegisterRouter.scala:87:24] wire _out_T_3298 = ~out_womask_296; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_243 = {hi_199, flags_0_go, _out_prepend_T_243}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3299 = out_prepend_243; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3300 = _out_T_3299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_244 = _out_T_3300; // @[RegisterRouter.scala:87:24] wire out_rimask_297 = |_out_rimask_T_297; // @[RegisterRouter.scala:87:24] wire out_wimask_297 = &_out_wimask_T_297; // @[RegisterRouter.scala:87:24] wire out_romask_297 = |_out_romask_T_297; // @[RegisterRouter.scala:87:24] wire out_womask_297 = &_out_womask_T_297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_297 = out_rivalid_1_151 & out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3302 = out_f_rivalid_297; // @[RegisterRouter.scala:87:24] wire out_f_roready_297 = out_roready_1_151 & out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3303 = out_f_roready_297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_297 = out_wivalid_1_151 & out_wimask_297; // @[RegisterRouter.scala:87:24] wire out_f_woready_297 = out_woready_1_151 & out_womask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3304 = ~out_rimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3305 = ~out_wimask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3306 = ~out_romask_297; // @[RegisterRouter.scala:87:24] wire _out_T_3307 = ~out_womask_297; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_244 = {hi_200, flags_0_go, _out_prepend_T_244}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3308 = out_prepend_244; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3309 = _out_T_3308; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_152 = _out_T_3309; // @[MuxLiteral.scala:49:48] wire out_rimask_298 = |_out_rimask_T_298; // @[RegisterRouter.scala:87:24] wire out_wimask_298 = &_out_wimask_T_298; // @[RegisterRouter.scala:87:24] wire out_romask_298 = |_out_romask_T_298; // @[RegisterRouter.scala:87:24] wire out_womask_298 = &_out_womask_T_298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_298 = out_rivalid_1_152 & out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3311 = out_f_rivalid_298; // @[RegisterRouter.scala:87:24] wire out_f_roready_298 = out_roready_1_152 & out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3312 = out_f_roready_298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_298 = out_wivalid_1_152 & out_wimask_298; // @[RegisterRouter.scala:87:24] wire out_f_woready_298 = out_woready_1_152 & out_womask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3313 = ~out_rimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3314 = ~out_wimask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3315 = ~out_romask_298; // @[RegisterRouter.scala:87:24] wire _out_T_3316 = ~out_womask_298; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3318 = _out_T_3317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_245 = _out_T_3318; // @[RegisterRouter.scala:87:24] wire out_rimask_299 = |_out_rimask_T_299; // @[RegisterRouter.scala:87:24] wire out_wimask_299 = &_out_wimask_T_299; // @[RegisterRouter.scala:87:24] wire out_romask_299 = |_out_romask_T_299; // @[RegisterRouter.scala:87:24] wire out_womask_299 = &_out_womask_T_299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_299 = out_rivalid_1_153 & out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3320 = out_f_rivalid_299; // @[RegisterRouter.scala:87:24] wire out_f_roready_299 = out_roready_1_153 & out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3321 = out_f_roready_299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_299 = out_wivalid_1_153 & out_wimask_299; // @[RegisterRouter.scala:87:24] wire out_f_woready_299 = out_woready_1_153 & out_womask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3322 = ~out_rimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3323 = ~out_wimask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3324 = ~out_romask_299; // @[RegisterRouter.scala:87:24] wire _out_T_3325 = ~out_womask_299; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_245 = {hi_802, flags_0_go, _out_prepend_T_245}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3326 = out_prepend_245; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3327 = _out_T_3326; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_246 = _out_T_3327; // @[RegisterRouter.scala:87:24] wire out_rimask_300 = |_out_rimask_T_300; // @[RegisterRouter.scala:87:24] wire out_wimask_300 = &_out_wimask_T_300; // @[RegisterRouter.scala:87:24] wire out_romask_300 = |_out_romask_T_300; // @[RegisterRouter.scala:87:24] wire out_womask_300 = &_out_womask_T_300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_300 = out_rivalid_1_154 & out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3329 = out_f_rivalid_300; // @[RegisterRouter.scala:87:24] wire out_f_roready_300 = out_roready_1_154 & out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3330 = out_f_roready_300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_300 = out_wivalid_1_154 & out_wimask_300; // @[RegisterRouter.scala:87:24] wire out_f_woready_300 = out_woready_1_154 & out_womask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3331 = ~out_rimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3332 = ~out_wimask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3333 = ~out_romask_300; // @[RegisterRouter.scala:87:24] wire _out_T_3334 = ~out_womask_300; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_246 = {hi_803, flags_0_go, _out_prepend_T_246}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3335 = out_prepend_246; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3336 = _out_T_3335; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_247 = _out_T_3336; // @[RegisterRouter.scala:87:24] wire out_rimask_301 = |_out_rimask_T_301; // @[RegisterRouter.scala:87:24] wire out_wimask_301 = &_out_wimask_T_301; // @[RegisterRouter.scala:87:24] wire out_romask_301 = |_out_romask_T_301; // @[RegisterRouter.scala:87:24] wire out_womask_301 = &_out_womask_T_301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_301 = out_rivalid_1_155 & out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3338 = out_f_rivalid_301; // @[RegisterRouter.scala:87:24] wire out_f_roready_301 = out_roready_1_155 & out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3339 = out_f_roready_301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_301 = out_wivalid_1_155 & out_wimask_301; // @[RegisterRouter.scala:87:24] wire out_f_woready_301 = out_woready_1_155 & out_womask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3340 = ~out_rimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3341 = ~out_wimask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3342 = ~out_romask_301; // @[RegisterRouter.scala:87:24] wire _out_T_3343 = ~out_womask_301; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_247 = {hi_804, flags_0_go, _out_prepend_T_247}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3344 = out_prepend_247; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3345 = _out_T_3344; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_248 = _out_T_3345; // @[RegisterRouter.scala:87:24] wire out_rimask_302 = |_out_rimask_T_302; // @[RegisterRouter.scala:87:24] wire out_wimask_302 = &_out_wimask_T_302; // @[RegisterRouter.scala:87:24] wire out_romask_302 = |_out_romask_T_302; // @[RegisterRouter.scala:87:24] wire out_womask_302 = &_out_womask_T_302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_302 = out_rivalid_1_156 & out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3347 = out_f_rivalid_302; // @[RegisterRouter.scala:87:24] wire out_f_roready_302 = out_roready_1_156 & out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3348 = out_f_roready_302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_302 = out_wivalid_1_156 & out_wimask_302; // @[RegisterRouter.scala:87:24] wire out_f_woready_302 = out_woready_1_156 & out_womask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3349 = ~out_rimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3350 = ~out_wimask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3351 = ~out_romask_302; // @[RegisterRouter.scala:87:24] wire _out_T_3352 = ~out_womask_302; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_248 = {hi_805, flags_0_go, _out_prepend_T_248}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3353 = out_prepend_248; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3354 = _out_T_3353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_249 = _out_T_3354; // @[RegisterRouter.scala:87:24] wire out_rimask_303 = |_out_rimask_T_303; // @[RegisterRouter.scala:87:24] wire out_wimask_303 = &_out_wimask_T_303; // @[RegisterRouter.scala:87:24] wire out_romask_303 = |_out_romask_T_303; // @[RegisterRouter.scala:87:24] wire out_womask_303 = &_out_womask_T_303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_303 = out_rivalid_1_157 & out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3356 = out_f_rivalid_303; // @[RegisterRouter.scala:87:24] wire out_f_roready_303 = out_roready_1_157 & out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3357 = out_f_roready_303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_303 = out_wivalid_1_157 & out_wimask_303; // @[RegisterRouter.scala:87:24] wire out_f_woready_303 = out_woready_1_157 & out_womask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3358 = ~out_rimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3359 = ~out_wimask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3360 = ~out_romask_303; // @[RegisterRouter.scala:87:24] wire _out_T_3361 = ~out_womask_303; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_249 = {hi_806, flags_0_go, _out_prepend_T_249}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3362 = out_prepend_249; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3363 = _out_T_3362; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_250 = _out_T_3363; // @[RegisterRouter.scala:87:24] wire out_rimask_304 = |_out_rimask_T_304; // @[RegisterRouter.scala:87:24] wire out_wimask_304 = &_out_wimask_T_304; // @[RegisterRouter.scala:87:24] wire out_romask_304 = |_out_romask_T_304; // @[RegisterRouter.scala:87:24] wire out_womask_304 = &_out_womask_T_304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_304 = out_rivalid_1_158 & out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3365 = out_f_rivalid_304; // @[RegisterRouter.scala:87:24] wire out_f_roready_304 = out_roready_1_158 & out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3366 = out_f_roready_304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_304 = out_wivalid_1_158 & out_wimask_304; // @[RegisterRouter.scala:87:24] wire out_f_woready_304 = out_woready_1_158 & out_womask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3367 = ~out_rimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3368 = ~out_wimask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3369 = ~out_romask_304; // @[RegisterRouter.scala:87:24] wire _out_T_3370 = ~out_womask_304; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_250 = {hi_807, flags_0_go, _out_prepend_T_250}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3371 = out_prepend_250; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3372 = _out_T_3371; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_251 = _out_T_3372; // @[RegisterRouter.scala:87:24] wire out_rimask_305 = |_out_rimask_T_305; // @[RegisterRouter.scala:87:24] wire out_wimask_305 = &_out_wimask_T_305; // @[RegisterRouter.scala:87:24] wire out_romask_305 = |_out_romask_T_305; // @[RegisterRouter.scala:87:24] wire out_womask_305 = &_out_womask_T_305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_305 = out_rivalid_1_159 & out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3374 = out_f_rivalid_305; // @[RegisterRouter.scala:87:24] wire out_f_roready_305 = out_roready_1_159 & out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3375 = out_f_roready_305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_305 = out_wivalid_1_159 & out_wimask_305; // @[RegisterRouter.scala:87:24] wire out_f_woready_305 = out_woready_1_159 & out_womask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3376 = ~out_rimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3377 = ~out_wimask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3378 = ~out_romask_305; // @[RegisterRouter.scala:87:24] wire _out_T_3379 = ~out_womask_305; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_251 = {hi_808, flags_0_go, _out_prepend_T_251}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3380 = out_prepend_251; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3381 = _out_T_3380; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_228 = _out_T_3381; // @[MuxLiteral.scala:49:48] wire out_rimask_306 = |_out_rimask_T_306; // @[RegisterRouter.scala:87:24] wire out_wimask_306 = &_out_wimask_T_306; // @[RegisterRouter.scala:87:24] wire out_romask_306 = |_out_romask_T_306; // @[RegisterRouter.scala:87:24] wire out_womask_306 = &_out_womask_T_306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_306 = out_rivalid_1_160 & out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3383 = out_f_rivalid_306; // @[RegisterRouter.scala:87:24] wire out_f_roready_306 = out_roready_1_160 & out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3384 = out_f_roready_306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_306 = out_wivalid_1_160 & out_wimask_306; // @[RegisterRouter.scala:87:24] wire out_f_woready_306 = out_woready_1_160 & out_womask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3385 = ~out_rimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3386 = ~out_wimask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3387 = ~out_romask_306; // @[RegisterRouter.scala:87:24] wire _out_T_3388 = ~out_womask_306; // @[RegisterRouter.scala:87:24] wire out_rimask_307 = |_out_rimask_T_307; // @[RegisterRouter.scala:87:24] wire out_wimask_307 = &_out_wimask_T_307; // @[RegisterRouter.scala:87:24] wire out_romask_307 = |_out_romask_T_307; // @[RegisterRouter.scala:87:24] wire out_womask_307 = &_out_womask_T_307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_307 = out_rivalid_1_161 & out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3392 = out_f_rivalid_307; // @[RegisterRouter.scala:87:24] wire out_f_roready_307 = out_roready_1_161 & out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3393 = out_f_roready_307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_307 = out_wivalid_1_161 & out_wimask_307; // @[RegisterRouter.scala:87:24] wire out_f_woready_307 = out_woready_1_161 & out_womask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3394 = ~out_rimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3395 = ~out_wimask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3396 = ~out_romask_307; // @[RegisterRouter.scala:87:24] wire _out_T_3397 = ~out_womask_307; // @[RegisterRouter.scala:87:24] wire out_rimask_308 = |_out_rimask_T_308; // @[RegisterRouter.scala:87:24] wire out_wimask_308 = &_out_wimask_T_308; // @[RegisterRouter.scala:87:24] wire out_romask_308 = |_out_romask_T_308; // @[RegisterRouter.scala:87:24] wire out_womask_308 = &_out_womask_T_308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_308 = out_rivalid_1_162 & out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3401 = out_f_rivalid_308; // @[RegisterRouter.scala:87:24] wire out_f_roready_308 = out_roready_1_162 & out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3402 = out_f_roready_308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_308 = out_wivalid_1_162 & out_wimask_308; // @[RegisterRouter.scala:87:24] wire out_f_woready_308 = out_woready_1_162 & out_womask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3403 = ~out_rimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3404 = ~out_wimask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3405 = ~out_romask_308; // @[RegisterRouter.scala:87:24] wire _out_T_3406 = ~out_womask_308; // @[RegisterRouter.scala:87:24] wire out_rimask_309 = |_out_rimask_T_309; // @[RegisterRouter.scala:87:24] wire out_wimask_309 = &_out_wimask_T_309; // @[RegisterRouter.scala:87:24] wire out_romask_309 = |_out_romask_T_309; // @[RegisterRouter.scala:87:24] wire out_womask_309 = &_out_womask_T_309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_309 = out_rivalid_1_163 & out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3410 = out_f_rivalid_309; // @[RegisterRouter.scala:87:24] wire out_f_roready_309 = out_roready_1_163 & out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3411 = out_f_roready_309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_309 = out_wivalid_1_163 & out_wimask_309; // @[RegisterRouter.scala:87:24] wire out_f_woready_309 = out_woready_1_163 & out_womask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3412 = ~out_rimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3413 = ~out_wimask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3414 = ~out_romask_309; // @[RegisterRouter.scala:87:24] wire _out_T_3415 = ~out_womask_309; // @[RegisterRouter.scala:87:24] wire out_rimask_310 = |_out_rimask_T_310; // @[RegisterRouter.scala:87:24] wire out_wimask_310 = &_out_wimask_T_310; // @[RegisterRouter.scala:87:24] wire out_romask_310 = |_out_romask_T_310; // @[RegisterRouter.scala:87:24] wire out_womask_310 = &_out_womask_T_310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_310 = out_rivalid_1_164 & out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3419 = out_f_rivalid_310; // @[RegisterRouter.scala:87:24] wire out_f_roready_310 = out_roready_1_164 & out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3420 = out_f_roready_310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_310 = out_wivalid_1_164 & out_wimask_310; // @[RegisterRouter.scala:87:24] wire out_f_woready_310 = out_woready_1_164 & out_womask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3421 = ~out_rimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3422 = ~out_wimask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3423 = ~out_romask_310; // @[RegisterRouter.scala:87:24] wire _out_T_3424 = ~out_womask_310; // @[RegisterRouter.scala:87:24] wire out_rimask_311 = |_out_rimask_T_311; // @[RegisterRouter.scala:87:24] wire out_wimask_311 = &_out_wimask_T_311; // @[RegisterRouter.scala:87:24] wire out_romask_311 = |_out_romask_T_311; // @[RegisterRouter.scala:87:24] wire out_womask_311 = &_out_womask_T_311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_311 = out_rivalid_1_165 & out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3428 = out_f_rivalid_311; // @[RegisterRouter.scala:87:24] wire out_f_roready_311 = out_roready_1_165 & out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3429 = out_f_roready_311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_311 = out_wivalid_1_165 & out_wimask_311; // @[RegisterRouter.scala:87:24] wire out_f_woready_311 = out_woready_1_165 & out_womask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3430 = ~out_rimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3431 = ~out_wimask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3432 = ~out_romask_311; // @[RegisterRouter.scala:87:24] wire _out_T_3433 = ~out_womask_311; // @[RegisterRouter.scala:87:24] wire out_rimask_312 = |_out_rimask_T_312; // @[RegisterRouter.scala:87:24] wire out_wimask_312 = &_out_wimask_T_312; // @[RegisterRouter.scala:87:24] wire out_romask_312 = |_out_romask_T_312; // @[RegisterRouter.scala:87:24] wire out_womask_312 = &_out_womask_T_312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_312 = out_rivalid_1_166 & out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3437 = out_f_rivalid_312; // @[RegisterRouter.scala:87:24] wire out_f_roready_312 = out_roready_1_166 & out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3438 = out_f_roready_312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_312 = out_wivalid_1_166 & out_wimask_312; // @[RegisterRouter.scala:87:24] wire out_f_woready_312 = out_woready_1_166 & out_womask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3439 = ~out_rimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3440 = ~out_wimask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3441 = ~out_romask_312; // @[RegisterRouter.scala:87:24] wire _out_T_3442 = ~out_womask_312; // @[RegisterRouter.scala:87:24] wire out_rimask_313 = |_out_rimask_T_313; // @[RegisterRouter.scala:87:24] wire out_wimask_313 = &_out_wimask_T_313; // @[RegisterRouter.scala:87:24] wire out_romask_313 = |_out_romask_T_313; // @[RegisterRouter.scala:87:24] wire out_womask_313 = &_out_womask_T_313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_313 = out_rivalid_1_167 & out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3446 = out_f_rivalid_313; // @[RegisterRouter.scala:87:24] wire out_f_roready_313 = out_roready_1_167 & out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3447 = out_f_roready_313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_313 = out_wivalid_1_167 & out_wimask_313; // @[RegisterRouter.scala:87:24] wire out_f_woready_313 = out_woready_1_167 & out_womask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3448 = ~out_rimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3449 = ~out_wimask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3450 = ~out_romask_313; // @[RegisterRouter.scala:87:24] wire _out_T_3451 = ~out_womask_313; // @[RegisterRouter.scala:87:24] wire out_rimask_314 = |_out_rimask_T_314; // @[RegisterRouter.scala:87:24] wire out_wimask_314 = &_out_wimask_T_314; // @[RegisterRouter.scala:87:24] wire out_romask_314 = |_out_romask_T_314; // @[RegisterRouter.scala:87:24] wire out_womask_314 = &_out_womask_T_314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_314 = out_rivalid_1_168 & out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3455 = out_f_rivalid_314; // @[RegisterRouter.scala:87:24] wire out_f_roready_314 = out_roready_1_168 & out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3456 = out_f_roready_314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_314 = out_wivalid_1_168 & out_wimask_314; // @[RegisterRouter.scala:87:24] wire out_f_woready_314 = out_woready_1_168 & out_womask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3457 = ~out_rimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3458 = ~out_wimask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3459 = ~out_romask_314; // @[RegisterRouter.scala:87:24] wire _out_T_3460 = ~out_womask_314; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3462 = _out_T_3461; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_259 = _out_T_3462; // @[RegisterRouter.scala:87:24] wire out_rimask_315 = |_out_rimask_T_315; // @[RegisterRouter.scala:87:24] wire out_wimask_315 = &_out_wimask_T_315; // @[RegisterRouter.scala:87:24] wire out_romask_315 = |_out_romask_T_315; // @[RegisterRouter.scala:87:24] wire out_womask_315 = &_out_womask_T_315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_315 = out_rivalid_1_169 & out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3464 = out_f_rivalid_315; // @[RegisterRouter.scala:87:24] wire out_f_roready_315 = out_roready_1_169 & out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3465 = out_f_roready_315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_315 = out_wivalid_1_169 & out_wimask_315; // @[RegisterRouter.scala:87:24] wire out_f_woready_315 = out_woready_1_169 & out_womask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3466 = ~out_rimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3467 = ~out_wimask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3468 = ~out_romask_315; // @[RegisterRouter.scala:87:24] wire _out_T_3469 = ~out_womask_315; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_259 = {hi_706, flags_0_go, _out_prepend_T_259}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3470 = out_prepend_259; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3471 = _out_T_3470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_260 = _out_T_3471; // @[RegisterRouter.scala:87:24] wire out_rimask_316 = |_out_rimask_T_316; // @[RegisterRouter.scala:87:24] wire out_wimask_316 = &_out_wimask_T_316; // @[RegisterRouter.scala:87:24] wire out_romask_316 = |_out_romask_T_316; // @[RegisterRouter.scala:87:24] wire out_womask_316 = &_out_womask_T_316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_316 = out_rivalid_1_170 & out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3473 = out_f_rivalid_316; // @[RegisterRouter.scala:87:24] wire out_f_roready_316 = out_roready_1_170 & out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3474 = out_f_roready_316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_316 = out_wivalid_1_170 & out_wimask_316; // @[RegisterRouter.scala:87:24] wire out_f_woready_316 = out_woready_1_170 & out_womask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3475 = ~out_rimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3476 = ~out_wimask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3477 = ~out_romask_316; // @[RegisterRouter.scala:87:24] wire _out_T_3478 = ~out_womask_316; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_260 = {hi_707, flags_0_go, _out_prepend_T_260}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3479 = out_prepend_260; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3480 = _out_T_3479; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_261 = _out_T_3480; // @[RegisterRouter.scala:87:24] wire out_rimask_317 = |_out_rimask_T_317; // @[RegisterRouter.scala:87:24] wire out_wimask_317 = &_out_wimask_T_317; // @[RegisterRouter.scala:87:24] wire out_romask_317 = |_out_romask_T_317; // @[RegisterRouter.scala:87:24] wire out_womask_317 = &_out_womask_T_317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_317 = out_rivalid_1_171 & out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3482 = out_f_rivalid_317; // @[RegisterRouter.scala:87:24] wire out_f_roready_317 = out_roready_1_171 & out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3483 = out_f_roready_317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_317 = out_wivalid_1_171 & out_wimask_317; // @[RegisterRouter.scala:87:24] wire out_f_woready_317 = out_woready_1_171 & out_womask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3484 = ~out_rimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3485 = ~out_wimask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3486 = ~out_romask_317; // @[RegisterRouter.scala:87:24] wire _out_T_3487 = ~out_womask_317; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_261 = {hi_708, flags_0_go, _out_prepend_T_261}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3488 = out_prepend_261; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3489 = _out_T_3488; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_262 = _out_T_3489; // @[RegisterRouter.scala:87:24] wire out_rimask_318 = |_out_rimask_T_318; // @[RegisterRouter.scala:87:24] wire out_wimask_318 = &_out_wimask_T_318; // @[RegisterRouter.scala:87:24] wire out_romask_318 = |_out_romask_T_318; // @[RegisterRouter.scala:87:24] wire out_womask_318 = &_out_womask_T_318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_318 = out_rivalid_1_172 & out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3491 = out_f_rivalid_318; // @[RegisterRouter.scala:87:24] wire out_f_roready_318 = out_roready_1_172 & out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3492 = out_f_roready_318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_318 = out_wivalid_1_172 & out_wimask_318; // @[RegisterRouter.scala:87:24] wire out_f_woready_318 = out_woready_1_172 & out_womask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3493 = ~out_rimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3494 = ~out_wimask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3495 = ~out_romask_318; // @[RegisterRouter.scala:87:24] wire _out_T_3496 = ~out_womask_318; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_262 = {hi_709, flags_0_go, _out_prepend_T_262}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3497 = out_prepend_262; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3498 = _out_T_3497; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_263 = _out_T_3498; // @[RegisterRouter.scala:87:24] wire out_rimask_319 = |_out_rimask_T_319; // @[RegisterRouter.scala:87:24] wire out_wimask_319 = &_out_wimask_T_319; // @[RegisterRouter.scala:87:24] wire out_romask_319 = |_out_romask_T_319; // @[RegisterRouter.scala:87:24] wire out_womask_319 = &_out_womask_T_319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_319 = out_rivalid_1_173 & out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3500 = out_f_rivalid_319; // @[RegisterRouter.scala:87:24] wire out_f_roready_319 = out_roready_1_173 & out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3501 = out_f_roready_319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_319 = out_wivalid_1_173 & out_wimask_319; // @[RegisterRouter.scala:87:24] wire out_f_woready_319 = out_woready_1_173 & out_womask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3502 = ~out_rimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3503 = ~out_wimask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3504 = ~out_romask_319; // @[RegisterRouter.scala:87:24] wire _out_T_3505 = ~out_womask_319; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_263 = {hi_710, flags_0_go, _out_prepend_T_263}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3506 = out_prepend_263; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3507 = _out_T_3506; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_264 = _out_T_3507; // @[RegisterRouter.scala:87:24] wire out_rimask_320 = |_out_rimask_T_320; // @[RegisterRouter.scala:87:24] wire out_wimask_320 = &_out_wimask_T_320; // @[RegisterRouter.scala:87:24] wire out_romask_320 = |_out_romask_T_320; // @[RegisterRouter.scala:87:24] wire out_womask_320 = &_out_womask_T_320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_320 = out_rivalid_1_174 & out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3509 = out_f_rivalid_320; // @[RegisterRouter.scala:87:24] wire out_f_roready_320 = out_roready_1_174 & out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3510 = out_f_roready_320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_320 = out_wivalid_1_174 & out_wimask_320; // @[RegisterRouter.scala:87:24] wire out_f_woready_320 = out_woready_1_174 & out_womask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3511 = ~out_rimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3512 = ~out_wimask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3513 = ~out_romask_320; // @[RegisterRouter.scala:87:24] wire _out_T_3514 = ~out_womask_320; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_264 = {hi_711, flags_0_go, _out_prepend_T_264}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3515 = out_prepend_264; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3516 = _out_T_3515; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_265 = _out_T_3516; // @[RegisterRouter.scala:87:24] wire out_rimask_321 = |_out_rimask_T_321; // @[RegisterRouter.scala:87:24] wire out_wimask_321 = &_out_wimask_T_321; // @[RegisterRouter.scala:87:24] wire out_romask_321 = |_out_romask_T_321; // @[RegisterRouter.scala:87:24] wire out_womask_321 = &_out_womask_T_321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_321 = out_rivalid_1_175 & out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3518 = out_f_rivalid_321; // @[RegisterRouter.scala:87:24] wire out_f_roready_321 = out_roready_1_175 & out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3519 = out_f_roready_321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_321 = out_wivalid_1_175 & out_wimask_321; // @[RegisterRouter.scala:87:24] wire out_f_woready_321 = out_woready_1_175 & out_womask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3520 = ~out_rimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3521 = ~out_wimask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3522 = ~out_romask_321; // @[RegisterRouter.scala:87:24] wire _out_T_3523 = ~out_womask_321; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_265 = {hi_712, flags_0_go, _out_prepend_T_265}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3524 = out_prepend_265; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3525 = _out_T_3524; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_216 = _out_T_3525; // @[MuxLiteral.scala:49:48] wire out_rimask_322 = |_out_rimask_T_322; // @[RegisterRouter.scala:87:24] wire out_wimask_322 = &_out_wimask_T_322; // @[RegisterRouter.scala:87:24] wire out_romask_322 = |_out_romask_T_322; // @[RegisterRouter.scala:87:24] wire out_womask_322 = &_out_womask_T_322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_322 = out_rivalid_1_176 & out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3527 = out_f_rivalid_322; // @[RegisterRouter.scala:87:24] wire out_f_roready_322 = out_roready_1_176 & out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3528 = out_f_roready_322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_322 = out_wivalid_1_176 & out_wimask_322; // @[RegisterRouter.scala:87:24] wire out_f_woready_322 = out_woready_1_176 & out_womask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3529 = ~out_rimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3530 = ~out_wimask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3531 = ~out_romask_322; // @[RegisterRouter.scala:87:24] wire _out_T_3532 = ~out_womask_322; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3534 = _out_T_3533; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_266 = _out_T_3534; // @[RegisterRouter.scala:87:24] wire out_rimask_323 = |_out_rimask_T_323; // @[RegisterRouter.scala:87:24] wire out_wimask_323 = &_out_wimask_T_323; // @[RegisterRouter.scala:87:24] wire out_romask_323 = |_out_romask_T_323; // @[RegisterRouter.scala:87:24] wire out_womask_323 = &_out_womask_T_323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_323 = out_rivalid_1_177 & out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3536 = out_f_rivalid_323; // @[RegisterRouter.scala:87:24] wire out_f_roready_323 = out_roready_1_177 & out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3537 = out_f_roready_323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_323 = out_wivalid_1_177 & out_wimask_323; // @[RegisterRouter.scala:87:24] wire out_f_woready_323 = out_woready_1_177 & out_womask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3538 = ~out_rimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3539 = ~out_wimask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3540 = ~out_romask_323; // @[RegisterRouter.scala:87:24] wire _out_T_3541 = ~out_womask_323; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_266 = {hi_290, flags_0_go, _out_prepend_T_266}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3542 = out_prepend_266; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3543 = _out_T_3542; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_267 = _out_T_3543; // @[RegisterRouter.scala:87:24] wire out_rimask_324 = |_out_rimask_T_324; // @[RegisterRouter.scala:87:24] wire out_wimask_324 = &_out_wimask_T_324; // @[RegisterRouter.scala:87:24] wire out_romask_324 = |_out_romask_T_324; // @[RegisterRouter.scala:87:24] wire out_womask_324 = &_out_womask_T_324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_324 = out_rivalid_1_178 & out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3545 = out_f_rivalid_324; // @[RegisterRouter.scala:87:24] wire out_f_roready_324 = out_roready_1_178 & out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3546 = out_f_roready_324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_324 = out_wivalid_1_178 & out_wimask_324; // @[RegisterRouter.scala:87:24] wire out_f_woready_324 = out_woready_1_178 & out_womask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3547 = ~out_rimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3548 = ~out_wimask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3549 = ~out_romask_324; // @[RegisterRouter.scala:87:24] wire _out_T_3550 = ~out_womask_324; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_267 = {hi_291, flags_0_go, _out_prepend_T_267}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3551 = out_prepend_267; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3552 = _out_T_3551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_268 = _out_T_3552; // @[RegisterRouter.scala:87:24] wire out_rimask_325 = |_out_rimask_T_325; // @[RegisterRouter.scala:87:24] wire out_wimask_325 = &_out_wimask_T_325; // @[RegisterRouter.scala:87:24] wire out_romask_325 = |_out_romask_T_325; // @[RegisterRouter.scala:87:24] wire out_womask_325 = &_out_womask_T_325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_325 = out_rivalid_1_179 & out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3554 = out_f_rivalid_325; // @[RegisterRouter.scala:87:24] wire out_f_roready_325 = out_roready_1_179 & out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3555 = out_f_roready_325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_325 = out_wivalid_1_179 & out_wimask_325; // @[RegisterRouter.scala:87:24] wire out_f_woready_325 = out_woready_1_179 & out_womask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3556 = ~out_rimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3557 = ~out_wimask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3558 = ~out_romask_325; // @[RegisterRouter.scala:87:24] wire _out_T_3559 = ~out_womask_325; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_268 = {hi_292, flags_0_go, _out_prepend_T_268}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3560 = out_prepend_268; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3561 = _out_T_3560; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_269 = _out_T_3561; // @[RegisterRouter.scala:87:24] wire out_rimask_326 = |_out_rimask_T_326; // @[RegisterRouter.scala:87:24] wire out_wimask_326 = &_out_wimask_T_326; // @[RegisterRouter.scala:87:24] wire out_romask_326 = |_out_romask_T_326; // @[RegisterRouter.scala:87:24] wire out_womask_326 = &_out_womask_T_326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_326 = out_rivalid_1_180 & out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3563 = out_f_rivalid_326; // @[RegisterRouter.scala:87:24] wire out_f_roready_326 = out_roready_1_180 & out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3564 = out_f_roready_326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_326 = out_wivalid_1_180 & out_wimask_326; // @[RegisterRouter.scala:87:24] wire out_f_woready_326 = out_woready_1_180 & out_womask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3565 = ~out_rimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3566 = ~out_wimask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3567 = ~out_romask_326; // @[RegisterRouter.scala:87:24] wire _out_T_3568 = ~out_womask_326; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_269 = {hi_293, flags_0_go, _out_prepend_T_269}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3569 = out_prepend_269; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3570 = _out_T_3569; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_270 = _out_T_3570; // @[RegisterRouter.scala:87:24] wire out_rimask_327 = |_out_rimask_T_327; // @[RegisterRouter.scala:87:24] wire out_wimask_327 = &_out_wimask_T_327; // @[RegisterRouter.scala:87:24] wire out_romask_327 = |_out_romask_T_327; // @[RegisterRouter.scala:87:24] wire out_womask_327 = &_out_womask_T_327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_327 = out_rivalid_1_181 & out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3572 = out_f_rivalid_327; // @[RegisterRouter.scala:87:24] wire out_f_roready_327 = out_roready_1_181 & out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3573 = out_f_roready_327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_327 = out_wivalid_1_181 & out_wimask_327; // @[RegisterRouter.scala:87:24] wire out_f_woready_327 = out_woready_1_181 & out_womask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3574 = ~out_rimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3575 = ~out_wimask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3576 = ~out_romask_327; // @[RegisterRouter.scala:87:24] wire _out_T_3577 = ~out_womask_327; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_270 = {hi_294, flags_0_go, _out_prepend_T_270}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3578 = out_prepend_270; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3579 = _out_T_3578; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_271 = _out_T_3579; // @[RegisterRouter.scala:87:24] wire out_rimask_328 = |_out_rimask_T_328; // @[RegisterRouter.scala:87:24] wire out_wimask_328 = &_out_wimask_T_328; // @[RegisterRouter.scala:87:24] wire out_romask_328 = |_out_romask_T_328; // @[RegisterRouter.scala:87:24] wire out_womask_328 = &_out_womask_T_328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_328 = out_rivalid_1_182 & out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3581 = out_f_rivalid_328; // @[RegisterRouter.scala:87:24] wire out_f_roready_328 = out_roready_1_182 & out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3582 = out_f_roready_328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_328 = out_wivalid_1_182 & out_wimask_328; // @[RegisterRouter.scala:87:24] wire out_f_woready_328 = out_woready_1_182 & out_womask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3583 = ~out_rimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3584 = ~out_wimask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3585 = ~out_romask_328; // @[RegisterRouter.scala:87:24] wire _out_T_3586 = ~out_womask_328; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_271 = {hi_295, flags_0_go, _out_prepend_T_271}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3587 = out_prepend_271; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3588 = _out_T_3587; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_272 = _out_T_3588; // @[RegisterRouter.scala:87:24] wire out_rimask_329 = |_out_rimask_T_329; // @[RegisterRouter.scala:87:24] wire out_wimask_329 = &_out_wimask_T_329; // @[RegisterRouter.scala:87:24] wire out_romask_329 = |_out_romask_T_329; // @[RegisterRouter.scala:87:24] wire out_womask_329 = &_out_womask_T_329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_329 = out_rivalid_1_183 & out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3590 = out_f_rivalid_329; // @[RegisterRouter.scala:87:24] wire out_f_roready_329 = out_roready_1_183 & out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3591 = out_f_roready_329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_329 = out_wivalid_1_183 & out_wimask_329; // @[RegisterRouter.scala:87:24] wire out_f_woready_329 = out_woready_1_183 & out_womask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3592 = ~out_rimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3593 = ~out_wimask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3594 = ~out_romask_329; // @[RegisterRouter.scala:87:24] wire _out_T_3595 = ~out_womask_329; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_272 = {hi_296, flags_0_go, _out_prepend_T_272}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3596 = out_prepend_272; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3597 = _out_T_3596; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_164 = _out_T_3597; // @[MuxLiteral.scala:49:48] wire out_rimask_330 = |_out_rimask_T_330; // @[RegisterRouter.scala:87:24] wire out_wimask_330 = &_out_wimask_T_330; // @[RegisterRouter.scala:87:24] wire out_romask_330 = |_out_romask_T_330; // @[RegisterRouter.scala:87:24] wire out_womask_330 = &_out_womask_T_330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_330 = out_rivalid_1_184 & out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3599 = out_f_rivalid_330; // @[RegisterRouter.scala:87:24] wire out_f_roready_330 = out_roready_1_184 & out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3600 = out_f_roready_330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_330 = out_wivalid_1_184 & out_wimask_330; // @[RegisterRouter.scala:87:24] wire out_f_woready_330 = out_woready_1_184 & out_womask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3601 = ~out_rimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3602 = ~out_wimask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3603 = ~out_romask_330; // @[RegisterRouter.scala:87:24] wire _out_T_3604 = ~out_womask_330; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3606 = _out_T_3605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_273 = _out_T_3606; // @[RegisterRouter.scala:87:24] wire out_rimask_331 = |_out_rimask_T_331; // @[RegisterRouter.scala:87:24] wire out_wimask_331 = &_out_wimask_T_331; // @[RegisterRouter.scala:87:24] wire out_romask_331 = |_out_romask_T_331; // @[RegisterRouter.scala:87:24] wire out_womask_331 = &_out_womask_T_331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_331 = out_rivalid_1_185 & out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3608 = out_f_rivalid_331; // @[RegisterRouter.scala:87:24] wire out_f_roready_331 = out_roready_1_185 & out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3609 = out_f_roready_331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_331 = out_wivalid_1_185 & out_wimask_331; // @[RegisterRouter.scala:87:24] wire out_f_woready_331 = out_woready_1_185 & out_womask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3610 = ~out_rimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3611 = ~out_wimask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3612 = ~out_romask_331; // @[RegisterRouter.scala:87:24] wire _out_T_3613 = ~out_womask_331; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_273 = {hi_410, flags_0_go, _out_prepend_T_273}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3614 = out_prepend_273; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3615 = _out_T_3614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_274 = _out_T_3615; // @[RegisterRouter.scala:87:24] wire out_rimask_332 = |_out_rimask_T_332; // @[RegisterRouter.scala:87:24] wire out_wimask_332 = &_out_wimask_T_332; // @[RegisterRouter.scala:87:24] wire out_romask_332 = |_out_romask_T_332; // @[RegisterRouter.scala:87:24] wire out_womask_332 = &_out_womask_T_332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_332 = out_rivalid_1_186 & out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3617 = out_f_rivalid_332; // @[RegisterRouter.scala:87:24] wire out_f_roready_332 = out_roready_1_186 & out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3618 = out_f_roready_332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_332 = out_wivalid_1_186 & out_wimask_332; // @[RegisterRouter.scala:87:24] wire out_f_woready_332 = out_woready_1_186 & out_womask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3619 = ~out_rimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3620 = ~out_wimask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3621 = ~out_romask_332; // @[RegisterRouter.scala:87:24] wire _out_T_3622 = ~out_womask_332; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_274 = {hi_411, flags_0_go, _out_prepend_T_274}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3623 = out_prepend_274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3624 = _out_T_3623; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_275 = _out_T_3624; // @[RegisterRouter.scala:87:24] wire out_rimask_333 = |_out_rimask_T_333; // @[RegisterRouter.scala:87:24] wire out_wimask_333 = &_out_wimask_T_333; // @[RegisterRouter.scala:87:24] wire out_romask_333 = |_out_romask_T_333; // @[RegisterRouter.scala:87:24] wire out_womask_333 = &_out_womask_T_333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_333 = out_rivalid_1_187 & out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3626 = out_f_rivalid_333; // @[RegisterRouter.scala:87:24] wire out_f_roready_333 = out_roready_1_187 & out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3627 = out_f_roready_333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_333 = out_wivalid_1_187 & out_wimask_333; // @[RegisterRouter.scala:87:24] wire out_f_woready_333 = out_woready_1_187 & out_womask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3628 = ~out_rimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3629 = ~out_wimask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3630 = ~out_romask_333; // @[RegisterRouter.scala:87:24] wire _out_T_3631 = ~out_womask_333; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_275 = {hi_412, flags_0_go, _out_prepend_T_275}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3632 = out_prepend_275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3633 = _out_T_3632; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_276 = _out_T_3633; // @[RegisterRouter.scala:87:24] wire out_rimask_334 = |_out_rimask_T_334; // @[RegisterRouter.scala:87:24] wire out_wimask_334 = &_out_wimask_T_334; // @[RegisterRouter.scala:87:24] wire out_romask_334 = |_out_romask_T_334; // @[RegisterRouter.scala:87:24] wire out_womask_334 = &_out_womask_T_334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_334 = out_rivalid_1_188 & out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3635 = out_f_rivalid_334; // @[RegisterRouter.scala:87:24] wire out_f_roready_334 = out_roready_1_188 & out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3636 = out_f_roready_334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_334 = out_wivalid_1_188 & out_wimask_334; // @[RegisterRouter.scala:87:24] wire out_f_woready_334 = out_woready_1_188 & out_womask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3637 = ~out_rimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3638 = ~out_wimask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3639 = ~out_romask_334; // @[RegisterRouter.scala:87:24] wire _out_T_3640 = ~out_womask_334; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_276 = {hi_413, flags_0_go, _out_prepend_T_276}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3641 = out_prepend_276; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3642 = _out_T_3641; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_277 = _out_T_3642; // @[RegisterRouter.scala:87:24] wire out_rimask_335 = |_out_rimask_T_335; // @[RegisterRouter.scala:87:24] wire out_wimask_335 = &_out_wimask_T_335; // @[RegisterRouter.scala:87:24] wire out_romask_335 = |_out_romask_T_335; // @[RegisterRouter.scala:87:24] wire out_womask_335 = &_out_womask_T_335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_335 = out_rivalid_1_189 & out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3644 = out_f_rivalid_335; // @[RegisterRouter.scala:87:24] wire out_f_roready_335 = out_roready_1_189 & out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3645 = out_f_roready_335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_335 = out_wivalid_1_189 & out_wimask_335; // @[RegisterRouter.scala:87:24] wire out_f_woready_335 = out_woready_1_189 & out_womask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3646 = ~out_rimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3647 = ~out_wimask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3648 = ~out_romask_335; // @[RegisterRouter.scala:87:24] wire _out_T_3649 = ~out_womask_335; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_277 = {hi_414, flags_0_go, _out_prepend_T_277}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3650 = out_prepend_277; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3651 = _out_T_3650; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_278 = _out_T_3651; // @[RegisterRouter.scala:87:24] wire out_rimask_336 = |_out_rimask_T_336; // @[RegisterRouter.scala:87:24] wire out_wimask_336 = &_out_wimask_T_336; // @[RegisterRouter.scala:87:24] wire out_romask_336 = |_out_romask_T_336; // @[RegisterRouter.scala:87:24] wire out_womask_336 = &_out_womask_T_336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_336 = out_rivalid_1_190 & out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3653 = out_f_rivalid_336; // @[RegisterRouter.scala:87:24] wire out_f_roready_336 = out_roready_1_190 & out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3654 = out_f_roready_336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_336 = out_wivalid_1_190 & out_wimask_336; // @[RegisterRouter.scala:87:24] wire out_f_woready_336 = out_woready_1_190 & out_womask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3655 = ~out_rimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3656 = ~out_wimask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3657 = ~out_romask_336; // @[RegisterRouter.scala:87:24] wire _out_T_3658 = ~out_womask_336; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_278 = {hi_415, flags_0_go, _out_prepend_T_278}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3659 = out_prepend_278; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3660 = _out_T_3659; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_279 = _out_T_3660; // @[RegisterRouter.scala:87:24] wire out_rimask_337 = |_out_rimask_T_337; // @[RegisterRouter.scala:87:24] wire out_wimask_337 = &_out_wimask_T_337; // @[RegisterRouter.scala:87:24] wire out_romask_337 = |_out_romask_T_337; // @[RegisterRouter.scala:87:24] wire out_womask_337 = &_out_womask_T_337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_337 = out_rivalid_1_191 & out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3662 = out_f_rivalid_337; // @[RegisterRouter.scala:87:24] wire out_f_roready_337 = out_roready_1_191 & out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3663 = out_f_roready_337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_337 = out_wivalid_1_191 & out_wimask_337; // @[RegisterRouter.scala:87:24] wire out_f_woready_337 = out_woready_1_191 & out_womask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3664 = ~out_rimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3665 = ~out_wimask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3666 = ~out_romask_337; // @[RegisterRouter.scala:87:24] wire _out_T_3667 = ~out_womask_337; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_279 = {hi_416, flags_0_go, _out_prepend_T_279}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3668 = out_prepend_279; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3669 = _out_T_3668; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_179 = _out_T_3669; // @[MuxLiteral.scala:49:48] wire out_rimask_338 = |_out_rimask_T_338; // @[RegisterRouter.scala:87:24] wire out_wimask_338 = &_out_wimask_T_338; // @[RegisterRouter.scala:87:24] wire out_romask_338 = |_out_romask_T_338; // @[RegisterRouter.scala:87:24] wire out_womask_338 = &_out_womask_T_338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_338 = out_rivalid_1_192 & out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3671 = out_f_rivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_roready_338 = out_roready_1_192 & out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3672 = out_f_roready_338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_338 = out_wivalid_1_192 & out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3673 = out_f_wivalid_338; // @[RegisterRouter.scala:87:24] wire out_f_woready_338 = out_woready_1_192 & out_womask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3674 = out_f_woready_338; // @[RegisterRouter.scala:87:24] wire _out_T_3675 = ~out_rimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3676 = ~out_wimask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3677 = ~out_romask_338; // @[RegisterRouter.scala:87:24] wire _out_T_3678 = ~out_womask_338; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3680 = _out_T_3679; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_280 = _out_T_3680; // @[RegisterRouter.scala:87:24] wire out_rimask_339 = |_out_rimask_T_339; // @[RegisterRouter.scala:87:24] wire out_wimask_339 = &_out_wimask_T_339; // @[RegisterRouter.scala:87:24] wire out_romask_339 = |_out_romask_T_339; // @[RegisterRouter.scala:87:24] wire out_womask_339 = &_out_womask_T_339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_339 = out_rivalid_1_193 & out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3682 = out_f_rivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_roready_339 = out_roready_1_193 & out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3683 = out_f_roready_339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_339 = out_wivalid_1_193 & out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3684 = out_f_wivalid_339; // @[RegisterRouter.scala:87:24] wire out_f_woready_339 = out_woready_1_193 & out_womask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3685 = out_f_woready_339; // @[RegisterRouter.scala:87:24] wire _out_T_3686 = ~out_rimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3687 = ~out_wimask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3688 = ~out_romask_339; // @[RegisterRouter.scala:87:24] wire _out_T_3689 = ~out_womask_339; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_280 = {programBufferMem_17, _out_prepend_T_280}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3690 = out_prepend_280; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3691 = _out_T_3690; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_281 = _out_T_3691; // @[RegisterRouter.scala:87:24] wire out_rimask_340 = |_out_rimask_T_340; // @[RegisterRouter.scala:87:24] wire out_wimask_340 = &_out_wimask_T_340; // @[RegisterRouter.scala:87:24] wire out_romask_340 = |_out_romask_T_340; // @[RegisterRouter.scala:87:24] wire out_womask_340 = &_out_womask_T_340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_340 = out_rivalid_1_194 & out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3693 = out_f_rivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_roready_340 = out_roready_1_194 & out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3694 = out_f_roready_340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_340 = out_wivalid_1_194 & out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3695 = out_f_wivalid_340; // @[RegisterRouter.scala:87:24] wire out_f_woready_340 = out_woready_1_194 & out_womask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3696 = out_f_woready_340; // @[RegisterRouter.scala:87:24] wire _out_T_3697 = ~out_rimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3698 = ~out_wimask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3699 = ~out_romask_340; // @[RegisterRouter.scala:87:24] wire _out_T_3700 = ~out_womask_340; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_281 = {programBufferMem_18, _out_prepend_T_281}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3701 = out_prepend_281; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3702 = _out_T_3701; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_282 = _out_T_3702; // @[RegisterRouter.scala:87:24] wire out_rimask_341 = |_out_rimask_T_341; // @[RegisterRouter.scala:87:24] wire out_wimask_341 = &_out_wimask_T_341; // @[RegisterRouter.scala:87:24] wire out_romask_341 = |_out_romask_T_341; // @[RegisterRouter.scala:87:24] wire out_womask_341 = &_out_womask_T_341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_341 = out_rivalid_1_195 & out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3704 = out_f_rivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_roready_341 = out_roready_1_195 & out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3705 = out_f_roready_341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_341 = out_wivalid_1_195 & out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3706 = out_f_wivalid_341; // @[RegisterRouter.scala:87:24] wire out_f_woready_341 = out_woready_1_195 & out_womask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3707 = out_f_woready_341; // @[RegisterRouter.scala:87:24] wire _out_T_3708 = ~out_rimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3709 = ~out_wimask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3710 = ~out_romask_341; // @[RegisterRouter.scala:87:24] wire _out_T_3711 = ~out_womask_341; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_282 = {programBufferMem_19, _out_prepend_T_282}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3712 = out_prepend_282; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3713 = _out_T_3712; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_283 = _out_T_3713; // @[RegisterRouter.scala:87:24] wire out_rimask_342 = |_out_rimask_T_342; // @[RegisterRouter.scala:87:24] wire out_wimask_342 = &_out_wimask_T_342; // @[RegisterRouter.scala:87:24] wire out_romask_342 = |_out_romask_T_342; // @[RegisterRouter.scala:87:24] wire out_womask_342 = &_out_womask_T_342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_342 = out_rivalid_1_196 & out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3715 = out_f_rivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_roready_342 = out_roready_1_196 & out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3716 = out_f_roready_342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_342 = out_wivalid_1_196 & out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3717 = out_f_wivalid_342; // @[RegisterRouter.scala:87:24] wire out_f_woready_342 = out_woready_1_196 & out_womask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3718 = out_f_woready_342; // @[RegisterRouter.scala:87:24] wire _out_T_3719 = ~out_rimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3720 = ~out_wimask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3721 = ~out_romask_342; // @[RegisterRouter.scala:87:24] wire _out_T_3722 = ~out_womask_342; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_283 = {programBufferMem_20, _out_prepend_T_283}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3723 = out_prepend_283; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3724 = _out_T_3723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_284 = _out_T_3724; // @[RegisterRouter.scala:87:24] wire out_rimask_343 = |_out_rimask_T_343; // @[RegisterRouter.scala:87:24] wire out_wimask_343 = &_out_wimask_T_343; // @[RegisterRouter.scala:87:24] wire out_romask_343 = |_out_romask_T_343; // @[RegisterRouter.scala:87:24] wire out_womask_343 = &_out_womask_T_343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_343 = out_rivalid_1_197 & out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3726 = out_f_rivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_roready_343 = out_roready_1_197 & out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3727 = out_f_roready_343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_343 = out_wivalid_1_197 & out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3728 = out_f_wivalid_343; // @[RegisterRouter.scala:87:24] wire out_f_woready_343 = out_woready_1_197 & out_womask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3729 = out_f_woready_343; // @[RegisterRouter.scala:87:24] wire _out_T_3730 = ~out_rimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3731 = ~out_wimask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3732 = ~out_romask_343; // @[RegisterRouter.scala:87:24] wire _out_T_3733 = ~out_womask_343; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_284 = {programBufferMem_21, _out_prepend_T_284}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3734 = out_prepend_284; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3735 = _out_T_3734; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_285 = _out_T_3735; // @[RegisterRouter.scala:87:24] wire out_rimask_344 = |_out_rimask_T_344; // @[RegisterRouter.scala:87:24] wire out_wimask_344 = &_out_wimask_T_344; // @[RegisterRouter.scala:87:24] wire out_romask_344 = |_out_romask_T_344; // @[RegisterRouter.scala:87:24] wire out_womask_344 = &_out_womask_T_344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_344 = out_rivalid_1_198 & out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3737 = out_f_rivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_roready_344 = out_roready_1_198 & out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3738 = out_f_roready_344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_344 = out_wivalid_1_198 & out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3739 = out_f_wivalid_344; // @[RegisterRouter.scala:87:24] wire out_f_woready_344 = out_woready_1_198 & out_womask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3740 = out_f_woready_344; // @[RegisterRouter.scala:87:24] wire _out_T_3741 = ~out_rimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3742 = ~out_wimask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3743 = ~out_romask_344; // @[RegisterRouter.scala:87:24] wire _out_T_3744 = ~out_womask_344; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_285 = {programBufferMem_22, _out_prepend_T_285}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3745 = out_prepend_285; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3746 = _out_T_3745; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_286 = _out_T_3746; // @[RegisterRouter.scala:87:24] wire out_rimask_345 = |_out_rimask_T_345; // @[RegisterRouter.scala:87:24] wire out_wimask_345 = &_out_wimask_T_345; // @[RegisterRouter.scala:87:24] wire out_romask_345 = |_out_romask_T_345; // @[RegisterRouter.scala:87:24] wire out_womask_345 = &_out_womask_T_345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_345 = out_rivalid_1_199 & out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3748 = out_f_rivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_roready_345 = out_roready_1_199 & out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3749 = out_f_roready_345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_345 = out_wivalid_1_199 & out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3750 = out_f_wivalid_345; // @[RegisterRouter.scala:87:24] wire out_f_woready_345 = out_woready_1_199 & out_womask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3751 = out_f_woready_345; // @[RegisterRouter.scala:87:24] wire _out_T_3752 = ~out_rimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3753 = ~out_wimask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3754 = ~out_romask_345; // @[RegisterRouter.scala:87:24] wire _out_T_3755 = ~out_womask_345; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_286 = {programBufferMem_23, _out_prepend_T_286}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3756 = out_prepend_286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3757 = _out_T_3756; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_106 = _out_T_3757; // @[MuxLiteral.scala:49:48] wire out_rimask_346 = |_out_rimask_T_346; // @[RegisterRouter.scala:87:24] wire out_wimask_346 = &_out_wimask_T_346; // @[RegisterRouter.scala:87:24] wire out_romask_346 = |_out_romask_T_346; // @[RegisterRouter.scala:87:24] wire out_womask_346 = &_out_womask_T_346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_346 = out_rivalid_1_200 & out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3759 = out_f_rivalid_346; // @[RegisterRouter.scala:87:24] wire out_f_roready_346 = out_roready_1_200 & out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3760 = out_f_roready_346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_346 = out_wivalid_1_200 & out_wimask_346; // @[RegisterRouter.scala:87:24] wire out_f_woready_346 = out_woready_1_200 & out_womask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3761 = ~out_rimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3762 = ~out_wimask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3763 = ~out_romask_346; // @[RegisterRouter.scala:87:24] wire _out_T_3764 = ~out_womask_346; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3766 = _out_T_3765; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_287 = _out_T_3766; // @[RegisterRouter.scala:87:24] wire out_rimask_347 = |_out_rimask_T_347; // @[RegisterRouter.scala:87:24] wire out_wimask_347 = &_out_wimask_T_347; // @[RegisterRouter.scala:87:24] wire out_romask_347 = |_out_romask_T_347; // @[RegisterRouter.scala:87:24] wire out_womask_347 = &_out_womask_T_347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_347 = out_rivalid_1_201 & out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3768 = out_f_rivalid_347; // @[RegisterRouter.scala:87:24] wire out_f_roready_347 = out_roready_1_201 & out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3769 = out_f_roready_347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_347 = out_wivalid_1_201 & out_wimask_347; // @[RegisterRouter.scala:87:24] wire out_f_woready_347 = out_woready_1_201 & out_womask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3770 = ~out_rimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3771 = ~out_wimask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3772 = ~out_romask_347; // @[RegisterRouter.scala:87:24] wire _out_T_3773 = ~out_womask_347; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_287 = {hi_882, flags_0_go, _out_prepend_T_287}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3774 = out_prepend_287; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3775 = _out_T_3774; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_288 = _out_T_3775; // @[RegisterRouter.scala:87:24] wire out_rimask_348 = |_out_rimask_T_348; // @[RegisterRouter.scala:87:24] wire out_wimask_348 = &_out_wimask_T_348; // @[RegisterRouter.scala:87:24] wire out_romask_348 = |_out_romask_T_348; // @[RegisterRouter.scala:87:24] wire out_womask_348 = &_out_womask_T_348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_348 = out_rivalid_1_202 & out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3777 = out_f_rivalid_348; // @[RegisterRouter.scala:87:24] wire out_f_roready_348 = out_roready_1_202 & out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3778 = out_f_roready_348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_348 = out_wivalid_1_202 & out_wimask_348; // @[RegisterRouter.scala:87:24] wire out_f_woready_348 = out_woready_1_202 & out_womask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3779 = ~out_rimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3780 = ~out_wimask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3781 = ~out_romask_348; // @[RegisterRouter.scala:87:24] wire _out_T_3782 = ~out_womask_348; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_288 = {hi_883, flags_0_go, _out_prepend_T_288}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3783 = out_prepend_288; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3784 = _out_T_3783; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_289 = _out_T_3784; // @[RegisterRouter.scala:87:24] wire out_rimask_349 = |_out_rimask_T_349; // @[RegisterRouter.scala:87:24] wire out_wimask_349 = &_out_wimask_T_349; // @[RegisterRouter.scala:87:24] wire out_romask_349 = |_out_romask_T_349; // @[RegisterRouter.scala:87:24] wire out_womask_349 = &_out_womask_T_349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_349 = out_rivalid_1_203 & out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3786 = out_f_rivalid_349; // @[RegisterRouter.scala:87:24] wire out_f_roready_349 = out_roready_1_203 & out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3787 = out_f_roready_349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_349 = out_wivalid_1_203 & out_wimask_349; // @[RegisterRouter.scala:87:24] wire out_f_woready_349 = out_woready_1_203 & out_womask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3788 = ~out_rimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3789 = ~out_wimask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3790 = ~out_romask_349; // @[RegisterRouter.scala:87:24] wire _out_T_3791 = ~out_womask_349; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_289 = {hi_884, flags_0_go, _out_prepend_T_289}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3792 = out_prepend_289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3793 = _out_T_3792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_290 = _out_T_3793; // @[RegisterRouter.scala:87:24] wire out_rimask_350 = |_out_rimask_T_350; // @[RegisterRouter.scala:87:24] wire out_wimask_350 = &_out_wimask_T_350; // @[RegisterRouter.scala:87:24] wire out_romask_350 = |_out_romask_T_350; // @[RegisterRouter.scala:87:24] wire out_womask_350 = &_out_womask_T_350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_350 = out_rivalid_1_204 & out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3795 = out_f_rivalid_350; // @[RegisterRouter.scala:87:24] wire out_f_roready_350 = out_roready_1_204 & out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3796 = out_f_roready_350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_350 = out_wivalid_1_204 & out_wimask_350; // @[RegisterRouter.scala:87:24] wire out_f_woready_350 = out_woready_1_204 & out_womask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3797 = ~out_rimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3798 = ~out_wimask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3799 = ~out_romask_350; // @[RegisterRouter.scala:87:24] wire _out_T_3800 = ~out_womask_350; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_290 = {hi_885, flags_0_go, _out_prepend_T_290}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3801 = out_prepend_290; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3802 = _out_T_3801; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_291 = _out_T_3802; // @[RegisterRouter.scala:87:24] wire out_rimask_351 = |_out_rimask_T_351; // @[RegisterRouter.scala:87:24] wire out_wimask_351 = &_out_wimask_T_351; // @[RegisterRouter.scala:87:24] wire out_romask_351 = |_out_romask_T_351; // @[RegisterRouter.scala:87:24] wire out_womask_351 = &_out_womask_T_351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_351 = out_rivalid_1_205 & out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3804 = out_f_rivalid_351; // @[RegisterRouter.scala:87:24] wire out_f_roready_351 = out_roready_1_205 & out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3805 = out_f_roready_351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_351 = out_wivalid_1_205 & out_wimask_351; // @[RegisterRouter.scala:87:24] wire out_f_woready_351 = out_woready_1_205 & out_womask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3806 = ~out_rimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3807 = ~out_wimask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3808 = ~out_romask_351; // @[RegisterRouter.scala:87:24] wire _out_T_3809 = ~out_womask_351; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_291 = {hi_886, flags_0_go, _out_prepend_T_291}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3810 = out_prepend_291; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3811 = _out_T_3810; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_292 = _out_T_3811; // @[RegisterRouter.scala:87:24] wire out_rimask_352 = |_out_rimask_T_352; // @[RegisterRouter.scala:87:24] wire out_wimask_352 = &_out_wimask_T_352; // @[RegisterRouter.scala:87:24] wire out_romask_352 = |_out_romask_T_352; // @[RegisterRouter.scala:87:24] wire out_womask_352 = &_out_womask_T_352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_352 = out_rivalid_1_206 & out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3813 = out_f_rivalid_352; // @[RegisterRouter.scala:87:24] wire out_f_roready_352 = out_roready_1_206 & out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3814 = out_f_roready_352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_352 = out_wivalid_1_206 & out_wimask_352; // @[RegisterRouter.scala:87:24] wire out_f_woready_352 = out_woready_1_206 & out_womask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3815 = ~out_rimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3816 = ~out_wimask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3817 = ~out_romask_352; // @[RegisterRouter.scala:87:24] wire _out_T_3818 = ~out_womask_352; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_292 = {hi_887, flags_0_go, _out_prepend_T_292}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3819 = out_prepend_292; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3820 = _out_T_3819; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_293 = _out_T_3820; // @[RegisterRouter.scala:87:24] wire out_rimask_353 = |_out_rimask_T_353; // @[RegisterRouter.scala:87:24] wire out_wimask_353 = &_out_wimask_T_353; // @[RegisterRouter.scala:87:24] wire out_romask_353 = |_out_romask_T_353; // @[RegisterRouter.scala:87:24] wire out_womask_353 = &_out_womask_T_353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_353 = out_rivalid_1_207 & out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3822 = out_f_rivalid_353; // @[RegisterRouter.scala:87:24] wire out_f_roready_353 = out_roready_1_207 & out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3823 = out_f_roready_353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_353 = out_wivalid_1_207 & out_wimask_353; // @[RegisterRouter.scala:87:24] wire out_f_woready_353 = out_woready_1_207 & out_womask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3824 = ~out_rimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3825 = ~out_wimask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3826 = ~out_romask_353; // @[RegisterRouter.scala:87:24] wire _out_T_3827 = ~out_womask_353; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_293 = {hi_888, flags_0_go, _out_prepend_T_293}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3828 = out_prepend_293; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3829 = _out_T_3828; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_238 = _out_T_3829; // @[MuxLiteral.scala:49:48] wire out_rimask_354 = |_out_rimask_T_354; // @[RegisterRouter.scala:87:24] wire out_wimask_354 = &_out_wimask_T_354; // @[RegisterRouter.scala:87:24] wire out_romask_354 = |_out_romask_T_354; // @[RegisterRouter.scala:87:24] wire out_womask_354 = &_out_womask_T_354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_354 = out_rivalid_1_208 & out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3831 = out_f_rivalid_354; // @[RegisterRouter.scala:87:24] wire out_f_roready_354 = out_roready_1_208 & out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3832 = out_f_roready_354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_354 = out_wivalid_1_208 & out_wimask_354; // @[RegisterRouter.scala:87:24] wire out_f_woready_354 = out_woready_1_208 & out_womask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3833 = ~out_rimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3834 = ~out_wimask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3835 = ~out_romask_354; // @[RegisterRouter.scala:87:24] wire _out_T_3836 = ~out_womask_354; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3838 = _out_T_3837; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_294 = _out_T_3838; // @[RegisterRouter.scala:87:24] wire out_rimask_355 = |_out_rimask_T_355; // @[RegisterRouter.scala:87:24] wire out_wimask_355 = &_out_wimask_T_355; // @[RegisterRouter.scala:87:24] wire out_romask_355 = |_out_romask_T_355; // @[RegisterRouter.scala:87:24] wire out_womask_355 = &_out_womask_T_355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_355 = out_rivalid_1_209 & out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3840 = out_f_rivalid_355; // @[RegisterRouter.scala:87:24] wire out_f_roready_355 = out_roready_1_209 & out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3841 = out_f_roready_355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_355 = out_wivalid_1_209 & out_wimask_355; // @[RegisterRouter.scala:87:24] wire out_f_woready_355 = out_woready_1_209 & out_womask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3842 = ~out_rimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3843 = ~out_wimask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3844 = ~out_romask_355; // @[RegisterRouter.scala:87:24] wire _out_T_3845 = ~out_womask_355; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_294 = {hi_666, flags_0_go, _out_prepend_T_294}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3846 = out_prepend_294; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3847 = _out_T_3846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_295 = _out_T_3847; // @[RegisterRouter.scala:87:24] wire out_rimask_356 = |_out_rimask_T_356; // @[RegisterRouter.scala:87:24] wire out_wimask_356 = &_out_wimask_T_356; // @[RegisterRouter.scala:87:24] wire out_romask_356 = |_out_romask_T_356; // @[RegisterRouter.scala:87:24] wire out_womask_356 = &_out_womask_T_356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_356 = out_rivalid_1_210 & out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3849 = out_f_rivalid_356; // @[RegisterRouter.scala:87:24] wire out_f_roready_356 = out_roready_1_210 & out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3850 = out_f_roready_356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_356 = out_wivalid_1_210 & out_wimask_356; // @[RegisterRouter.scala:87:24] wire out_f_woready_356 = out_woready_1_210 & out_womask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3851 = ~out_rimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3852 = ~out_wimask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3853 = ~out_romask_356; // @[RegisterRouter.scala:87:24] wire _out_T_3854 = ~out_womask_356; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_295 = {hi_667, flags_0_go, _out_prepend_T_295}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3855 = out_prepend_295; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3856 = _out_T_3855; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_296 = _out_T_3856; // @[RegisterRouter.scala:87:24] wire out_rimask_357 = |_out_rimask_T_357; // @[RegisterRouter.scala:87:24] wire out_wimask_357 = &_out_wimask_T_357; // @[RegisterRouter.scala:87:24] wire out_romask_357 = |_out_romask_T_357; // @[RegisterRouter.scala:87:24] wire out_womask_357 = &_out_womask_T_357; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_357 = out_rivalid_1_211 & out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3858 = out_f_rivalid_357; // @[RegisterRouter.scala:87:24] wire out_f_roready_357 = out_roready_1_211 & out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3859 = out_f_roready_357; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_357 = out_wivalid_1_211 & out_wimask_357; // @[RegisterRouter.scala:87:24] wire out_f_woready_357 = out_woready_1_211 & out_womask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3860 = ~out_rimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3861 = ~out_wimask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3862 = ~out_romask_357; // @[RegisterRouter.scala:87:24] wire _out_T_3863 = ~out_womask_357; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_296 = {hi_668, flags_0_go, _out_prepend_T_296}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3864 = out_prepend_296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3865 = _out_T_3864; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_297 = _out_T_3865; // @[RegisterRouter.scala:87:24] wire out_rimask_358 = |_out_rimask_T_358; // @[RegisterRouter.scala:87:24] wire out_wimask_358 = &_out_wimask_T_358; // @[RegisterRouter.scala:87:24] wire out_romask_358 = |_out_romask_T_358; // @[RegisterRouter.scala:87:24] wire out_womask_358 = &_out_womask_T_358; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_358 = out_rivalid_1_212 & out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3867 = out_f_rivalid_358; // @[RegisterRouter.scala:87:24] wire out_f_roready_358 = out_roready_1_212 & out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3868 = out_f_roready_358; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_358 = out_wivalid_1_212 & out_wimask_358; // @[RegisterRouter.scala:87:24] wire out_f_woready_358 = out_woready_1_212 & out_womask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3869 = ~out_rimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3870 = ~out_wimask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3871 = ~out_romask_358; // @[RegisterRouter.scala:87:24] wire _out_T_3872 = ~out_womask_358; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_297 = {hi_669, flags_0_go, _out_prepend_T_297}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3873 = out_prepend_297; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3874 = _out_T_3873; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_298 = _out_T_3874; // @[RegisterRouter.scala:87:24] wire out_rimask_359 = |_out_rimask_T_359; // @[RegisterRouter.scala:87:24] wire out_wimask_359 = &_out_wimask_T_359; // @[RegisterRouter.scala:87:24] wire out_romask_359 = |_out_romask_T_359; // @[RegisterRouter.scala:87:24] wire out_womask_359 = &_out_womask_T_359; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_359 = out_rivalid_1_213 & out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3876 = out_f_rivalid_359; // @[RegisterRouter.scala:87:24] wire out_f_roready_359 = out_roready_1_213 & out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3877 = out_f_roready_359; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_359 = out_wivalid_1_213 & out_wimask_359; // @[RegisterRouter.scala:87:24] wire out_f_woready_359 = out_woready_1_213 & out_womask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3878 = ~out_rimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3879 = ~out_wimask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3880 = ~out_romask_359; // @[RegisterRouter.scala:87:24] wire _out_T_3881 = ~out_womask_359; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_298 = {hi_670, flags_0_go, _out_prepend_T_298}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3882 = out_prepend_298; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3883 = _out_T_3882; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_299 = _out_T_3883; // @[RegisterRouter.scala:87:24] wire out_rimask_360 = |_out_rimask_T_360; // @[RegisterRouter.scala:87:24] wire out_wimask_360 = &_out_wimask_T_360; // @[RegisterRouter.scala:87:24] wire out_romask_360 = |_out_romask_T_360; // @[RegisterRouter.scala:87:24] wire out_womask_360 = &_out_womask_T_360; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_360 = out_rivalid_1_214 & out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3885 = out_f_rivalid_360; // @[RegisterRouter.scala:87:24] wire out_f_roready_360 = out_roready_1_214 & out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3886 = out_f_roready_360; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_360 = out_wivalid_1_214 & out_wimask_360; // @[RegisterRouter.scala:87:24] wire out_f_woready_360 = out_woready_1_214 & out_womask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3887 = ~out_rimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3888 = ~out_wimask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3889 = ~out_romask_360; // @[RegisterRouter.scala:87:24] wire _out_T_3890 = ~out_womask_360; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_299 = {hi_671, flags_0_go, _out_prepend_T_299}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3891 = out_prepend_299; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3892 = _out_T_3891; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_300 = _out_T_3892; // @[RegisterRouter.scala:87:24] wire out_rimask_361 = |_out_rimask_T_361; // @[RegisterRouter.scala:87:24] wire out_wimask_361 = &_out_wimask_T_361; // @[RegisterRouter.scala:87:24] wire out_romask_361 = |_out_romask_T_361; // @[RegisterRouter.scala:87:24] wire out_womask_361 = &_out_womask_T_361; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_361 = out_rivalid_1_215 & out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3894 = out_f_rivalid_361; // @[RegisterRouter.scala:87:24] wire out_f_roready_361 = out_roready_1_215 & out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3895 = out_f_roready_361; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_361 = out_wivalid_1_215 & out_wimask_361; // @[RegisterRouter.scala:87:24] wire out_f_woready_361 = out_woready_1_215 & out_womask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3896 = ~out_rimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3897 = ~out_wimask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3898 = ~out_romask_361; // @[RegisterRouter.scala:87:24] wire _out_T_3899 = ~out_womask_361; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_300 = {hi_672, flags_0_go, _out_prepend_T_300}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3900 = out_prepend_300; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3901 = _out_T_3900; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_211 = _out_T_3901; // @[MuxLiteral.scala:49:48] wire out_rimask_362 = |_out_rimask_T_362; // @[RegisterRouter.scala:87:24] wire out_wimask_362 = &_out_wimask_T_362; // @[RegisterRouter.scala:87:24] wire out_romask_362 = |_out_romask_T_362; // @[RegisterRouter.scala:87:24] wire out_womask_362 = &_out_womask_T_362; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_362 = out_rivalid_1_216 & out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3903 = out_f_rivalid_362; // @[RegisterRouter.scala:87:24] wire out_f_roready_362 = out_roready_1_216 & out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3904 = out_f_roready_362; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_362 = out_wivalid_1_216 & out_wimask_362; // @[RegisterRouter.scala:87:24] wire out_f_woready_362 = out_woready_1_216 & out_womask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3905 = ~out_rimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3906 = ~out_wimask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3907 = ~out_romask_362; // @[RegisterRouter.scala:87:24] wire _out_T_3908 = ~out_womask_362; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3910 = _out_T_3909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_301 = _out_T_3910; // @[RegisterRouter.scala:87:24] wire out_rimask_363 = |_out_rimask_T_363; // @[RegisterRouter.scala:87:24] wire out_wimask_363 = &_out_wimask_T_363; // @[RegisterRouter.scala:87:24] wire out_romask_363 = |_out_romask_T_363; // @[RegisterRouter.scala:87:24] wire out_womask_363 = &_out_womask_T_363; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_363 = out_rivalid_1_217 & out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3912 = out_f_rivalid_363; // @[RegisterRouter.scala:87:24] wire out_f_roready_363 = out_roready_1_217 & out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3913 = out_f_roready_363; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_363 = out_wivalid_1_217 & out_wimask_363; // @[RegisterRouter.scala:87:24] wire out_f_woready_363 = out_woready_1_217 & out_womask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3914 = ~out_rimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3915 = ~out_wimask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3916 = ~out_romask_363; // @[RegisterRouter.scala:87:24] wire _out_T_3917 = ~out_womask_363; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_301 = {hi_1002, flags_0_go, _out_prepend_T_301}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3918 = out_prepend_301; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3919 = _out_T_3918; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_302 = _out_T_3919; // @[RegisterRouter.scala:87:24] wire out_rimask_364 = |_out_rimask_T_364; // @[RegisterRouter.scala:87:24] wire out_wimask_364 = &_out_wimask_T_364; // @[RegisterRouter.scala:87:24] wire out_romask_364 = |_out_romask_T_364; // @[RegisterRouter.scala:87:24] wire out_womask_364 = &_out_womask_T_364; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_364 = out_rivalid_1_218 & out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3921 = out_f_rivalid_364; // @[RegisterRouter.scala:87:24] wire out_f_roready_364 = out_roready_1_218 & out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3922 = out_f_roready_364; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_364 = out_wivalid_1_218 & out_wimask_364; // @[RegisterRouter.scala:87:24] wire out_f_woready_364 = out_woready_1_218 & out_womask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3923 = ~out_rimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3924 = ~out_wimask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3925 = ~out_romask_364; // @[RegisterRouter.scala:87:24] wire _out_T_3926 = ~out_womask_364; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_302 = {hi_1003, flags_0_go, _out_prepend_T_302}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3927 = out_prepend_302; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3928 = _out_T_3927; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_303 = _out_T_3928; // @[RegisterRouter.scala:87:24] wire out_rimask_365 = |_out_rimask_T_365; // @[RegisterRouter.scala:87:24] wire out_wimask_365 = &_out_wimask_T_365; // @[RegisterRouter.scala:87:24] wire out_romask_365 = |_out_romask_T_365; // @[RegisterRouter.scala:87:24] wire out_womask_365 = &_out_womask_T_365; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_365 = out_rivalid_1_219 & out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3930 = out_f_rivalid_365; // @[RegisterRouter.scala:87:24] wire out_f_roready_365 = out_roready_1_219 & out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3931 = out_f_roready_365; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_365 = out_wivalid_1_219 & out_wimask_365; // @[RegisterRouter.scala:87:24] wire out_f_woready_365 = out_woready_1_219 & out_womask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3932 = ~out_rimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3933 = ~out_wimask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3934 = ~out_romask_365; // @[RegisterRouter.scala:87:24] wire _out_T_3935 = ~out_womask_365; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_303 = {hi_1004, flags_0_go, _out_prepend_T_303}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3936 = out_prepend_303; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_3937 = _out_T_3936; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_304 = _out_T_3937; // @[RegisterRouter.scala:87:24] wire out_rimask_366 = |_out_rimask_T_366; // @[RegisterRouter.scala:87:24] wire out_wimask_366 = &_out_wimask_T_366; // @[RegisterRouter.scala:87:24] wire out_romask_366 = |_out_romask_T_366; // @[RegisterRouter.scala:87:24] wire out_womask_366 = &_out_womask_T_366; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_366 = out_rivalid_1_220 & out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3939 = out_f_rivalid_366; // @[RegisterRouter.scala:87:24] wire out_f_roready_366 = out_roready_1_220 & out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3940 = out_f_roready_366; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_366 = out_wivalid_1_220 & out_wimask_366; // @[RegisterRouter.scala:87:24] wire out_f_woready_366 = out_woready_1_220 & out_womask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3941 = ~out_rimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3942 = ~out_wimask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3943 = ~out_romask_366; // @[RegisterRouter.scala:87:24] wire _out_T_3944 = ~out_womask_366; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_304 = {hi_1005, flags_0_go, _out_prepend_T_304}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3945 = out_prepend_304; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_3946 = _out_T_3945; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_305 = _out_T_3946; // @[RegisterRouter.scala:87:24] wire out_rimask_367 = |_out_rimask_T_367; // @[RegisterRouter.scala:87:24] wire out_wimask_367 = &_out_wimask_T_367; // @[RegisterRouter.scala:87:24] wire out_romask_367 = |_out_romask_T_367; // @[RegisterRouter.scala:87:24] wire out_womask_367 = &_out_womask_T_367; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_367 = out_rivalid_1_221 & out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3948 = out_f_rivalid_367; // @[RegisterRouter.scala:87:24] wire out_f_roready_367 = out_roready_1_221 & out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3949 = out_f_roready_367; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_367 = out_wivalid_1_221 & out_wimask_367; // @[RegisterRouter.scala:87:24] wire out_f_woready_367 = out_woready_1_221 & out_womask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3950 = ~out_rimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3951 = ~out_wimask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3952 = ~out_romask_367; // @[RegisterRouter.scala:87:24] wire _out_T_3953 = ~out_womask_367; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_305 = {hi_1006, flags_0_go, _out_prepend_T_305}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3954 = out_prepend_305; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_3955 = _out_T_3954; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_306 = _out_T_3955; // @[RegisterRouter.scala:87:24] wire out_rimask_368 = |_out_rimask_T_368; // @[RegisterRouter.scala:87:24] wire out_wimask_368 = &_out_wimask_T_368; // @[RegisterRouter.scala:87:24] wire out_romask_368 = |_out_romask_T_368; // @[RegisterRouter.scala:87:24] wire out_womask_368 = &_out_womask_T_368; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_368 = out_rivalid_1_222 & out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3957 = out_f_rivalid_368; // @[RegisterRouter.scala:87:24] wire out_f_roready_368 = out_roready_1_222 & out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3958 = out_f_roready_368; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_368 = out_wivalid_1_222 & out_wimask_368; // @[RegisterRouter.scala:87:24] wire out_f_woready_368 = out_woready_1_222 & out_womask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3959 = ~out_rimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3960 = ~out_wimask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3961 = ~out_romask_368; // @[RegisterRouter.scala:87:24] wire _out_T_3962 = ~out_womask_368; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_306 = {hi_1007, flags_0_go, _out_prepend_T_306}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3963 = out_prepend_306; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_3964 = _out_T_3963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_307 = _out_T_3964; // @[RegisterRouter.scala:87:24] wire out_rimask_369 = |_out_rimask_T_369; // @[RegisterRouter.scala:87:24] wire out_wimask_369 = &_out_wimask_T_369; // @[RegisterRouter.scala:87:24] wire out_romask_369 = |_out_romask_T_369; // @[RegisterRouter.scala:87:24] wire out_womask_369 = &_out_womask_T_369; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_369 = out_rivalid_1_223 & out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3966 = out_f_rivalid_369; // @[RegisterRouter.scala:87:24] wire out_f_roready_369 = out_roready_1_223 & out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3967 = out_f_roready_369; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_369 = out_wivalid_1_223 & out_wimask_369; // @[RegisterRouter.scala:87:24] wire out_f_woready_369 = out_woready_1_223 & out_womask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3968 = ~out_rimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3969 = ~out_wimask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3970 = ~out_romask_369; // @[RegisterRouter.scala:87:24] wire _out_T_3971 = ~out_womask_369; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_307 = {hi_1008, flags_0_go, _out_prepend_T_307}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3972 = out_prepend_307; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_3973 = _out_T_3972; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_253 = _out_T_3973; // @[MuxLiteral.scala:49:48] wire out_rimask_370 = |_out_rimask_T_370; // @[RegisterRouter.scala:87:24] wire out_wimask_370 = &_out_wimask_T_370; // @[RegisterRouter.scala:87:24] wire out_romask_370 = |_out_romask_T_370; // @[RegisterRouter.scala:87:24] wire out_womask_370 = &_out_womask_T_370; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_370 = out_rivalid_1_224 & out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3975 = out_f_rivalid_370; // @[RegisterRouter.scala:87:24] wire out_f_roready_370 = out_roready_1_224 & out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3976 = out_f_roready_370; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_370 = out_wivalid_1_224 & out_wimask_370; // @[RegisterRouter.scala:87:24] wire out_f_woready_370 = out_woready_1_224 & out_womask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3977 = ~out_rimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3978 = ~out_wimask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3979 = ~out_romask_370; // @[RegisterRouter.scala:87:24] wire _out_T_3980 = ~out_womask_370; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_3982 = _out_T_3981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_308 = _out_T_3982; // @[RegisterRouter.scala:87:24] wire out_rimask_371 = |_out_rimask_T_371; // @[RegisterRouter.scala:87:24] wire out_wimask_371 = &_out_wimask_T_371; // @[RegisterRouter.scala:87:24] wire out_romask_371 = |_out_romask_T_371; // @[RegisterRouter.scala:87:24] wire out_womask_371 = &_out_womask_T_371; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_371 = out_rivalid_1_225 & out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3984 = out_f_rivalid_371; // @[RegisterRouter.scala:87:24] wire out_f_roready_371 = out_roready_1_225 & out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3985 = out_f_roready_371; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_371 = out_wivalid_1_225 & out_wimask_371; // @[RegisterRouter.scala:87:24] wire out_f_woready_371 = out_woready_1_225 & out_womask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3986 = ~out_rimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3987 = ~out_wimask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3988 = ~out_romask_371; // @[RegisterRouter.scala:87:24] wire _out_T_3989 = ~out_womask_371; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_308 = {hi_154, flags_0_go, _out_prepend_T_308}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3990 = out_prepend_308; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_3991 = _out_T_3990; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_309 = _out_T_3991; // @[RegisterRouter.scala:87:24] wire out_rimask_372 = |_out_rimask_T_372; // @[RegisterRouter.scala:87:24] wire out_wimask_372 = &_out_wimask_T_372; // @[RegisterRouter.scala:87:24] wire out_romask_372 = |_out_romask_T_372; // @[RegisterRouter.scala:87:24] wire out_womask_372 = &_out_womask_T_372; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_372 = out_rivalid_1_226 & out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3993 = out_f_rivalid_372; // @[RegisterRouter.scala:87:24] wire out_f_roready_372 = out_roready_1_226 & out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3994 = out_f_roready_372; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_372 = out_wivalid_1_226 & out_wimask_372; // @[RegisterRouter.scala:87:24] wire out_f_woready_372 = out_woready_1_226 & out_womask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3995 = ~out_rimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3996 = ~out_wimask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3997 = ~out_romask_372; // @[RegisterRouter.scala:87:24] wire _out_T_3998 = ~out_womask_372; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_309 = {hi_155, flags_0_go, _out_prepend_T_309}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_3999 = out_prepend_309; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4000 = _out_T_3999; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_310 = _out_T_4000; // @[RegisterRouter.scala:87:24] wire out_rimask_373 = |_out_rimask_T_373; // @[RegisterRouter.scala:87:24] wire out_wimask_373 = &_out_wimask_T_373; // @[RegisterRouter.scala:87:24] wire out_romask_373 = |_out_romask_T_373; // @[RegisterRouter.scala:87:24] wire out_womask_373 = &_out_womask_T_373; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_373 = out_rivalid_1_227 & out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4002 = out_f_rivalid_373; // @[RegisterRouter.scala:87:24] wire out_f_roready_373 = out_roready_1_227 & out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4003 = out_f_roready_373; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_373 = out_wivalid_1_227 & out_wimask_373; // @[RegisterRouter.scala:87:24] wire out_f_woready_373 = out_woready_1_227 & out_womask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4004 = ~out_rimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4005 = ~out_wimask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4006 = ~out_romask_373; // @[RegisterRouter.scala:87:24] wire _out_T_4007 = ~out_womask_373; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_310 = {hi_156, flags_0_go, _out_prepend_T_310}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4008 = out_prepend_310; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4009 = _out_T_4008; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_311 = _out_T_4009; // @[RegisterRouter.scala:87:24] wire out_rimask_374 = |_out_rimask_T_374; // @[RegisterRouter.scala:87:24] wire out_wimask_374 = &_out_wimask_T_374; // @[RegisterRouter.scala:87:24] wire out_romask_374 = |_out_romask_T_374; // @[RegisterRouter.scala:87:24] wire out_womask_374 = &_out_womask_T_374; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_374 = out_rivalid_1_228 & out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4011 = out_f_rivalid_374; // @[RegisterRouter.scala:87:24] wire out_f_roready_374 = out_roready_1_228 & out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4012 = out_f_roready_374; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_374 = out_wivalid_1_228 & out_wimask_374; // @[RegisterRouter.scala:87:24] wire out_f_woready_374 = out_woready_1_228 & out_womask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4013 = ~out_rimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4014 = ~out_wimask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4015 = ~out_romask_374; // @[RegisterRouter.scala:87:24] wire _out_T_4016 = ~out_womask_374; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_311 = {hi_157, flags_0_go, _out_prepend_T_311}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4017 = out_prepend_311; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4018 = _out_T_4017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_312 = _out_T_4018; // @[RegisterRouter.scala:87:24] wire out_rimask_375 = |_out_rimask_T_375; // @[RegisterRouter.scala:87:24] wire out_wimask_375 = &_out_wimask_T_375; // @[RegisterRouter.scala:87:24] wire out_romask_375 = |_out_romask_T_375; // @[RegisterRouter.scala:87:24] wire out_womask_375 = &_out_womask_T_375; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_375 = out_rivalid_1_229 & out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4020 = out_f_rivalid_375; // @[RegisterRouter.scala:87:24] wire out_f_roready_375 = out_roready_1_229 & out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4021 = out_f_roready_375; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_375 = out_wivalid_1_229 & out_wimask_375; // @[RegisterRouter.scala:87:24] wire out_f_woready_375 = out_woready_1_229 & out_womask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4022 = ~out_rimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4023 = ~out_wimask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4024 = ~out_romask_375; // @[RegisterRouter.scala:87:24] wire _out_T_4025 = ~out_womask_375; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_312 = {hi_158, flags_0_go, _out_prepend_T_312}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4026 = out_prepend_312; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4027 = _out_T_4026; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_313 = _out_T_4027; // @[RegisterRouter.scala:87:24] wire out_rimask_376 = |_out_rimask_T_376; // @[RegisterRouter.scala:87:24] wire out_wimask_376 = &_out_wimask_T_376; // @[RegisterRouter.scala:87:24] wire out_romask_376 = |_out_romask_T_376; // @[RegisterRouter.scala:87:24] wire out_womask_376 = &_out_womask_T_376; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_376 = out_rivalid_1_230 & out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4029 = out_f_rivalid_376; // @[RegisterRouter.scala:87:24] wire out_f_roready_376 = out_roready_1_230 & out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4030 = out_f_roready_376; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_376 = out_wivalid_1_230 & out_wimask_376; // @[RegisterRouter.scala:87:24] wire out_f_woready_376 = out_woready_1_230 & out_womask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4031 = ~out_rimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4032 = ~out_wimask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4033 = ~out_romask_376; // @[RegisterRouter.scala:87:24] wire _out_T_4034 = ~out_womask_376; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_313 = {hi_159, flags_0_go, _out_prepend_T_313}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4035 = out_prepend_313; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4036 = _out_T_4035; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_314 = _out_T_4036; // @[RegisterRouter.scala:87:24] wire out_rimask_377 = |_out_rimask_T_377; // @[RegisterRouter.scala:87:24] wire out_wimask_377 = &_out_wimask_T_377; // @[RegisterRouter.scala:87:24] wire out_romask_377 = |_out_romask_T_377; // @[RegisterRouter.scala:87:24] wire out_womask_377 = &_out_womask_T_377; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_377 = out_rivalid_1_231 & out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4038 = out_f_rivalid_377; // @[RegisterRouter.scala:87:24] wire out_f_roready_377 = out_roready_1_231 & out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4039 = out_f_roready_377; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_377 = out_wivalid_1_231 & out_wimask_377; // @[RegisterRouter.scala:87:24] wire out_f_woready_377 = out_woready_1_231 & out_womask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4040 = ~out_rimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4041 = ~out_wimask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4042 = ~out_romask_377; // @[RegisterRouter.scala:87:24] wire _out_T_4043 = ~out_womask_377; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_314 = {hi_160, flags_0_go, _out_prepend_T_314}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4044 = out_prepend_314; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4045 = _out_T_4044; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_147 = _out_T_4045; // @[MuxLiteral.scala:49:48] wire out_rimask_378 = |_out_rimask_T_378; // @[RegisterRouter.scala:87:24] wire out_wimask_378 = &_out_wimask_T_378; // @[RegisterRouter.scala:87:24] wire out_romask_378 = |_out_romask_T_378; // @[RegisterRouter.scala:87:24] wire out_womask_378 = &_out_womask_T_378; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_378 = out_rivalid_1_232 & out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4047 = out_f_rivalid_378; // @[RegisterRouter.scala:87:24] wire out_f_roready_378 = out_roready_1_232 & out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4048 = out_f_roready_378; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_378 = out_wivalid_1_232 & out_wimask_378; // @[RegisterRouter.scala:87:24] wire out_f_woready_378 = out_woready_1_232 & out_womask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4049 = ~out_rimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4050 = ~out_wimask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4051 = ~out_romask_378; // @[RegisterRouter.scala:87:24] wire _out_T_4052 = ~out_womask_378; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4054 = _out_T_4053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_315 = _out_T_4054; // @[RegisterRouter.scala:87:24] wire out_rimask_379 = |_out_rimask_T_379; // @[RegisterRouter.scala:87:24] wire out_wimask_379 = &_out_wimask_T_379; // @[RegisterRouter.scala:87:24] wire out_romask_379 = |_out_romask_T_379; // @[RegisterRouter.scala:87:24] wire out_womask_379 = &_out_womask_T_379; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_379 = out_rivalid_1_233 & out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4056 = out_f_rivalid_379; // @[RegisterRouter.scala:87:24] wire out_f_roready_379 = out_roready_1_233 & out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4057 = out_f_roready_379; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_379 = out_wivalid_1_233 & out_wimask_379; // @[RegisterRouter.scala:87:24] wire out_f_woready_379 = out_woready_1_233 & out_womask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4058 = ~out_rimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4059 = ~out_wimask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4060 = ~out_romask_379; // @[RegisterRouter.scala:87:24] wire _out_T_4061 = ~out_womask_379; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_315 = {hi_746, flags_0_go, _out_prepend_T_315}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4062 = out_prepend_315; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4063 = _out_T_4062; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_316 = _out_T_4063; // @[RegisterRouter.scala:87:24] wire out_rimask_380 = |_out_rimask_T_380; // @[RegisterRouter.scala:87:24] wire out_wimask_380 = &_out_wimask_T_380; // @[RegisterRouter.scala:87:24] wire out_romask_380 = |_out_romask_T_380; // @[RegisterRouter.scala:87:24] wire out_womask_380 = &_out_womask_T_380; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_380 = out_rivalid_1_234 & out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4065 = out_f_rivalid_380; // @[RegisterRouter.scala:87:24] wire out_f_roready_380 = out_roready_1_234 & out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4066 = out_f_roready_380; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_380 = out_wivalid_1_234 & out_wimask_380; // @[RegisterRouter.scala:87:24] wire out_f_woready_380 = out_woready_1_234 & out_womask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4067 = ~out_rimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4068 = ~out_wimask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4069 = ~out_romask_380; // @[RegisterRouter.scala:87:24] wire _out_T_4070 = ~out_womask_380; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_316 = {hi_747, flags_0_go, _out_prepend_T_316}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4071 = out_prepend_316; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4072 = _out_T_4071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_317 = _out_T_4072; // @[RegisterRouter.scala:87:24] wire out_rimask_381 = |_out_rimask_T_381; // @[RegisterRouter.scala:87:24] wire out_wimask_381 = &_out_wimask_T_381; // @[RegisterRouter.scala:87:24] wire out_romask_381 = |_out_romask_T_381; // @[RegisterRouter.scala:87:24] wire out_womask_381 = &_out_womask_T_381; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_381 = out_rivalid_1_235 & out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4074 = out_f_rivalid_381; // @[RegisterRouter.scala:87:24] wire out_f_roready_381 = out_roready_1_235 & out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4075 = out_f_roready_381; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_381 = out_wivalid_1_235 & out_wimask_381; // @[RegisterRouter.scala:87:24] wire out_f_woready_381 = out_woready_1_235 & out_womask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4076 = ~out_rimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4077 = ~out_wimask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4078 = ~out_romask_381; // @[RegisterRouter.scala:87:24] wire _out_T_4079 = ~out_womask_381; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_317 = {hi_748, flags_0_go, _out_prepend_T_317}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4080 = out_prepend_317; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4081 = _out_T_4080; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_318 = _out_T_4081; // @[RegisterRouter.scala:87:24] wire out_rimask_382 = |_out_rimask_T_382; // @[RegisterRouter.scala:87:24] wire out_wimask_382 = &_out_wimask_T_382; // @[RegisterRouter.scala:87:24] wire out_romask_382 = |_out_romask_T_382; // @[RegisterRouter.scala:87:24] wire out_womask_382 = &_out_womask_T_382; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_382 = out_rivalid_1_236 & out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4083 = out_f_rivalid_382; // @[RegisterRouter.scala:87:24] wire out_f_roready_382 = out_roready_1_236 & out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4084 = out_f_roready_382; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_382 = out_wivalid_1_236 & out_wimask_382; // @[RegisterRouter.scala:87:24] wire out_f_woready_382 = out_woready_1_236 & out_womask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4085 = ~out_rimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4086 = ~out_wimask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4087 = ~out_romask_382; // @[RegisterRouter.scala:87:24] wire _out_T_4088 = ~out_womask_382; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_318 = {hi_749, flags_0_go, _out_prepend_T_318}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4089 = out_prepend_318; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4090 = _out_T_4089; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_319 = _out_T_4090; // @[RegisterRouter.scala:87:24] wire out_rimask_383 = |_out_rimask_T_383; // @[RegisterRouter.scala:87:24] wire out_wimask_383 = &_out_wimask_T_383; // @[RegisterRouter.scala:87:24] wire out_romask_383 = |_out_romask_T_383; // @[RegisterRouter.scala:87:24] wire out_womask_383 = &_out_womask_T_383; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_383 = out_rivalid_1_237 & out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4092 = out_f_rivalid_383; // @[RegisterRouter.scala:87:24] wire out_f_roready_383 = out_roready_1_237 & out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4093 = out_f_roready_383; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_383 = out_wivalid_1_237 & out_wimask_383; // @[RegisterRouter.scala:87:24] wire out_f_woready_383 = out_woready_1_237 & out_womask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4094 = ~out_rimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4095 = ~out_wimask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4096 = ~out_romask_383; // @[RegisterRouter.scala:87:24] wire _out_T_4097 = ~out_womask_383; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_319 = {hi_750, flags_0_go, _out_prepend_T_319}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4098 = out_prepend_319; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4099 = _out_T_4098; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_320 = _out_T_4099; // @[RegisterRouter.scala:87:24] wire out_rimask_384 = |_out_rimask_T_384; // @[RegisterRouter.scala:87:24] wire out_wimask_384 = &_out_wimask_T_384; // @[RegisterRouter.scala:87:24] wire out_romask_384 = |_out_romask_T_384; // @[RegisterRouter.scala:87:24] wire out_womask_384 = &_out_womask_T_384; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_384 = out_rivalid_1_238 & out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4101 = out_f_rivalid_384; // @[RegisterRouter.scala:87:24] wire out_f_roready_384 = out_roready_1_238 & out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4102 = out_f_roready_384; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_384 = out_wivalid_1_238 & out_wimask_384; // @[RegisterRouter.scala:87:24] wire out_f_woready_384 = out_woready_1_238 & out_womask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4103 = ~out_rimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4104 = ~out_wimask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4105 = ~out_romask_384; // @[RegisterRouter.scala:87:24] wire _out_T_4106 = ~out_womask_384; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_320 = {hi_751, flags_0_go, _out_prepend_T_320}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4107 = out_prepend_320; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4108 = _out_T_4107; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_321 = _out_T_4108; // @[RegisterRouter.scala:87:24] wire out_rimask_385 = |_out_rimask_T_385; // @[RegisterRouter.scala:87:24] wire out_wimask_385 = &_out_wimask_T_385; // @[RegisterRouter.scala:87:24] wire out_romask_385 = |_out_romask_T_385; // @[RegisterRouter.scala:87:24] wire out_womask_385 = &_out_womask_T_385; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_385 = out_rivalid_1_239 & out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4110 = out_f_rivalid_385; // @[RegisterRouter.scala:87:24] wire out_f_roready_385 = out_roready_1_239 & out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4111 = out_f_roready_385; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_385 = out_wivalid_1_239 & out_wimask_385; // @[RegisterRouter.scala:87:24] wire out_f_woready_385 = out_woready_1_239 & out_womask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4112 = ~out_rimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4113 = ~out_wimask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4114 = ~out_romask_385; // @[RegisterRouter.scala:87:24] wire _out_T_4115 = ~out_womask_385; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_321 = {hi_752, flags_0_go, _out_prepend_T_321}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4116 = out_prepend_321; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4117 = _out_T_4116; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_221 = _out_T_4117; // @[MuxLiteral.scala:49:48] wire out_rimask_386 = |_out_rimask_T_386; // @[RegisterRouter.scala:87:24] wire out_wimask_386 = &_out_wimask_T_386; // @[RegisterRouter.scala:87:24] wire out_romask_386 = |_out_romask_T_386; // @[RegisterRouter.scala:87:24] wire out_womask_386 = &_out_womask_T_386; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_386 = out_rivalid_1_240 & out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4119 = out_f_rivalid_386; // @[RegisterRouter.scala:87:24] wire out_f_roready_386 = out_roready_1_240 & out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4120 = out_f_roready_386; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_386 = out_wivalid_1_240 & out_wimask_386; // @[RegisterRouter.scala:87:24] wire out_f_woready_386 = out_woready_1_240 & out_womask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4121 = ~out_rimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4122 = ~out_wimask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4123 = ~out_romask_386; // @[RegisterRouter.scala:87:24] wire _out_T_4124 = ~out_womask_386; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4126 = _out_T_4125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_322 = _out_T_4126; // @[RegisterRouter.scala:87:24] wire out_rimask_387 = |_out_rimask_T_387; // @[RegisterRouter.scala:87:24] wire out_wimask_387 = &_out_wimask_T_387; // @[RegisterRouter.scala:87:24] wire out_romask_387 = |_out_romask_T_387; // @[RegisterRouter.scala:87:24] wire out_womask_387 = &_out_womask_T_387; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_387 = out_rivalid_1_241 & out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4128 = out_f_rivalid_387; // @[RegisterRouter.scala:87:24] wire out_f_roready_387 = out_roready_1_241 & out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4129 = out_f_roready_387; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_387 = out_wivalid_1_241 & out_wimask_387; // @[RegisterRouter.scala:87:24] wire out_f_woready_387 = out_woready_1_241 & out_womask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4130 = ~out_rimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4131 = ~out_wimask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4132 = ~out_romask_387; // @[RegisterRouter.scala:87:24] wire _out_T_4133 = ~out_womask_387; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_322 = {hi_34, flags_0_go, _out_prepend_T_322}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4134 = out_prepend_322; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4135 = _out_T_4134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_323 = _out_T_4135; // @[RegisterRouter.scala:87:24] wire out_rimask_388 = |_out_rimask_T_388; // @[RegisterRouter.scala:87:24] wire out_wimask_388 = &_out_wimask_T_388; // @[RegisterRouter.scala:87:24] wire out_romask_388 = |_out_romask_T_388; // @[RegisterRouter.scala:87:24] wire out_womask_388 = &_out_womask_T_388; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_388 = out_rivalid_1_242 & out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4137 = out_f_rivalid_388; // @[RegisterRouter.scala:87:24] wire out_f_roready_388 = out_roready_1_242 & out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4138 = out_f_roready_388; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_388 = out_wivalid_1_242 & out_wimask_388; // @[RegisterRouter.scala:87:24] wire out_f_woready_388 = out_woready_1_242 & out_womask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4139 = ~out_rimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4140 = ~out_wimask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4141 = ~out_romask_388; // @[RegisterRouter.scala:87:24] wire _out_T_4142 = ~out_womask_388; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_323 = {hi_35, flags_0_go, _out_prepend_T_323}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4143 = out_prepend_323; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4144 = _out_T_4143; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_324 = _out_T_4144; // @[RegisterRouter.scala:87:24] wire out_rimask_389 = |_out_rimask_T_389; // @[RegisterRouter.scala:87:24] wire out_wimask_389 = &_out_wimask_T_389; // @[RegisterRouter.scala:87:24] wire out_romask_389 = |_out_romask_T_389; // @[RegisterRouter.scala:87:24] wire out_womask_389 = &_out_womask_T_389; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_389 = out_rivalid_1_243 & out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4146 = out_f_rivalid_389; // @[RegisterRouter.scala:87:24] wire out_f_roready_389 = out_roready_1_243 & out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4147 = out_f_roready_389; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_389 = out_wivalid_1_243 & out_wimask_389; // @[RegisterRouter.scala:87:24] wire out_f_woready_389 = out_woready_1_243 & out_womask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4148 = ~out_rimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4149 = ~out_wimask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4150 = ~out_romask_389; // @[RegisterRouter.scala:87:24] wire _out_T_4151 = ~out_womask_389; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_324 = {hi_36, flags_0_go, _out_prepend_T_324}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4152 = out_prepend_324; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4153 = _out_T_4152; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_325 = _out_T_4153; // @[RegisterRouter.scala:87:24] wire out_rimask_390 = |_out_rimask_T_390; // @[RegisterRouter.scala:87:24] wire out_wimask_390 = &_out_wimask_T_390; // @[RegisterRouter.scala:87:24] wire out_romask_390 = |_out_romask_T_390; // @[RegisterRouter.scala:87:24] wire out_womask_390 = &_out_womask_T_390; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_390 = out_rivalid_1_244 & out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4155 = out_f_rivalid_390; // @[RegisterRouter.scala:87:24] wire out_f_roready_390 = out_roready_1_244 & out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4156 = out_f_roready_390; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_390 = out_wivalid_1_244 & out_wimask_390; // @[RegisterRouter.scala:87:24] wire out_f_woready_390 = out_woready_1_244 & out_womask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4157 = ~out_rimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4158 = ~out_wimask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4159 = ~out_romask_390; // @[RegisterRouter.scala:87:24] wire _out_T_4160 = ~out_womask_390; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_325 = {hi_37, flags_0_go, _out_prepend_T_325}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4161 = out_prepend_325; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4162 = _out_T_4161; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_326 = _out_T_4162; // @[RegisterRouter.scala:87:24] wire out_rimask_391 = |_out_rimask_T_391; // @[RegisterRouter.scala:87:24] wire out_wimask_391 = &_out_wimask_T_391; // @[RegisterRouter.scala:87:24] wire out_romask_391 = |_out_romask_T_391; // @[RegisterRouter.scala:87:24] wire out_womask_391 = &_out_womask_T_391; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_391 = out_rivalid_1_245 & out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4164 = out_f_rivalid_391; // @[RegisterRouter.scala:87:24] wire out_f_roready_391 = out_roready_1_245 & out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4165 = out_f_roready_391; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_391 = out_wivalid_1_245 & out_wimask_391; // @[RegisterRouter.scala:87:24] wire out_f_woready_391 = out_woready_1_245 & out_womask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4166 = ~out_rimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4167 = ~out_wimask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4168 = ~out_romask_391; // @[RegisterRouter.scala:87:24] wire _out_T_4169 = ~out_womask_391; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_326 = {hi_38, flags_0_go, _out_prepend_T_326}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4170 = out_prepend_326; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4171 = _out_T_4170; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_327 = _out_T_4171; // @[RegisterRouter.scala:87:24] wire out_rimask_392 = |_out_rimask_T_392; // @[RegisterRouter.scala:87:24] wire out_wimask_392 = &_out_wimask_T_392; // @[RegisterRouter.scala:87:24] wire out_romask_392 = |_out_romask_T_392; // @[RegisterRouter.scala:87:24] wire out_womask_392 = &_out_womask_T_392; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_392 = out_rivalid_1_246 & out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4173 = out_f_rivalid_392; // @[RegisterRouter.scala:87:24] wire out_f_roready_392 = out_roready_1_246 & out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4174 = out_f_roready_392; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_392 = out_wivalid_1_246 & out_wimask_392; // @[RegisterRouter.scala:87:24] wire out_f_woready_392 = out_woready_1_246 & out_womask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4175 = ~out_rimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4176 = ~out_wimask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4177 = ~out_romask_392; // @[RegisterRouter.scala:87:24] wire _out_T_4178 = ~out_womask_392; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_327 = {hi_39, flags_0_go, _out_prepend_T_327}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4179 = out_prepend_327; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4180 = _out_T_4179; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_328 = _out_T_4180; // @[RegisterRouter.scala:87:24] wire out_rimask_393 = |_out_rimask_T_393; // @[RegisterRouter.scala:87:24] wire out_wimask_393 = &_out_wimask_T_393; // @[RegisterRouter.scala:87:24] wire out_romask_393 = |_out_romask_T_393; // @[RegisterRouter.scala:87:24] wire out_womask_393 = &_out_womask_T_393; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_393 = out_rivalid_1_247 & out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4182 = out_f_rivalid_393; // @[RegisterRouter.scala:87:24] wire out_f_roready_393 = out_roready_1_247 & out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4183 = out_f_roready_393; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_393 = out_wivalid_1_247 & out_wimask_393; // @[RegisterRouter.scala:87:24] wire out_f_woready_393 = out_woready_1_247 & out_womask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4184 = ~out_rimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4185 = ~out_wimask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4186 = ~out_romask_393; // @[RegisterRouter.scala:87:24] wire _out_T_4187 = ~out_womask_393; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_328 = {hi_40, flags_0_go, _out_prepend_T_328}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4188 = out_prepend_328; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4189 = _out_T_4188; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_132 = _out_T_4189; // @[MuxLiteral.scala:49:48] wire out_rimask_394 = |_out_rimask_T_394; // @[RegisterRouter.scala:87:24] wire out_wimask_394 = &_out_wimask_T_394; // @[RegisterRouter.scala:87:24] wire out_romask_394 = |_out_romask_T_394; // @[RegisterRouter.scala:87:24] wire out_womask_394 = &_out_womask_T_394; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_394 = out_rivalid_1_248 & out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4191 = out_f_rivalid_394; // @[RegisterRouter.scala:87:24] wire out_f_roready_394 = out_roready_1_248 & out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4192 = out_f_roready_394; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_394 = out_wivalid_1_248 & out_wimask_394; // @[RegisterRouter.scala:87:24] wire out_f_woready_394 = out_woready_1_248 & out_womask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4193 = ~out_rimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4194 = ~out_wimask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4195 = ~out_romask_394; // @[RegisterRouter.scala:87:24] wire _out_T_4196 = ~out_womask_394; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4198 = _out_T_4197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_329 = _out_T_4198; // @[RegisterRouter.scala:87:24] wire out_rimask_395 = |_out_rimask_T_395; // @[RegisterRouter.scala:87:24] wire out_wimask_395 = &_out_wimask_T_395; // @[RegisterRouter.scala:87:24] wire out_romask_395 = |_out_romask_T_395; // @[RegisterRouter.scala:87:24] wire out_womask_395 = &_out_womask_T_395; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_395 = out_rivalid_1_249 & out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4200 = out_f_rivalid_395; // @[RegisterRouter.scala:87:24] wire out_f_roready_395 = out_roready_1_249 & out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4201 = out_f_roready_395; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_395 = out_wivalid_1_249 & out_wimask_395; // @[RegisterRouter.scala:87:24] wire out_f_woready_395 = out_woready_1_249 & out_womask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4202 = ~out_rimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4203 = ~out_wimask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4204 = ~out_romask_395; // @[RegisterRouter.scala:87:24] wire _out_T_4205 = ~out_womask_395; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_329 = {hi_42, flags_0_go, _out_prepend_T_329}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4206 = out_prepend_329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4207 = _out_T_4206; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_330 = _out_T_4207; // @[RegisterRouter.scala:87:24] wire out_rimask_396 = |_out_rimask_T_396; // @[RegisterRouter.scala:87:24] wire out_wimask_396 = &_out_wimask_T_396; // @[RegisterRouter.scala:87:24] wire out_romask_396 = |_out_romask_T_396; // @[RegisterRouter.scala:87:24] wire out_womask_396 = &_out_womask_T_396; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_396 = out_rivalid_1_250 & out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4209 = out_f_rivalid_396; // @[RegisterRouter.scala:87:24] wire out_f_roready_396 = out_roready_1_250 & out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4210 = out_f_roready_396; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_396 = out_wivalid_1_250 & out_wimask_396; // @[RegisterRouter.scala:87:24] wire out_f_woready_396 = out_woready_1_250 & out_womask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4211 = ~out_rimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4212 = ~out_wimask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4213 = ~out_romask_396; // @[RegisterRouter.scala:87:24] wire _out_T_4214 = ~out_womask_396; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_330 = {hi_43, flags_0_go, _out_prepend_T_330}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4215 = out_prepend_330; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4216 = _out_T_4215; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_331 = _out_T_4216; // @[RegisterRouter.scala:87:24] wire out_rimask_397 = |_out_rimask_T_397; // @[RegisterRouter.scala:87:24] wire out_wimask_397 = &_out_wimask_T_397; // @[RegisterRouter.scala:87:24] wire out_romask_397 = |_out_romask_T_397; // @[RegisterRouter.scala:87:24] wire out_womask_397 = &_out_womask_T_397; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_397 = out_rivalid_1_251 & out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4218 = out_f_rivalid_397; // @[RegisterRouter.scala:87:24] wire out_f_roready_397 = out_roready_1_251 & out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4219 = out_f_roready_397; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_397 = out_wivalid_1_251 & out_wimask_397; // @[RegisterRouter.scala:87:24] wire out_f_woready_397 = out_woready_1_251 & out_womask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4220 = ~out_rimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4221 = ~out_wimask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4222 = ~out_romask_397; // @[RegisterRouter.scala:87:24] wire _out_T_4223 = ~out_womask_397; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_331 = {hi_44, flags_0_go, _out_prepend_T_331}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4224 = out_prepend_331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4225 = _out_T_4224; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_332 = _out_T_4225; // @[RegisterRouter.scala:87:24] wire out_rimask_398 = |_out_rimask_T_398; // @[RegisterRouter.scala:87:24] wire out_wimask_398 = &_out_wimask_T_398; // @[RegisterRouter.scala:87:24] wire out_romask_398 = |_out_romask_T_398; // @[RegisterRouter.scala:87:24] wire out_womask_398 = &_out_womask_T_398; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_398 = out_rivalid_1_252 & out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4227 = out_f_rivalid_398; // @[RegisterRouter.scala:87:24] wire out_f_roready_398 = out_roready_1_252 & out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4228 = out_f_roready_398; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_398 = out_wivalid_1_252 & out_wimask_398; // @[RegisterRouter.scala:87:24] wire out_f_woready_398 = out_woready_1_252 & out_womask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4229 = ~out_rimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4230 = ~out_wimask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4231 = ~out_romask_398; // @[RegisterRouter.scala:87:24] wire _out_T_4232 = ~out_womask_398; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_332 = {hi_45, flags_0_go, _out_prepend_T_332}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4233 = out_prepend_332; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4234 = _out_T_4233; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_333 = _out_T_4234; // @[RegisterRouter.scala:87:24] wire out_rimask_399 = |_out_rimask_T_399; // @[RegisterRouter.scala:87:24] wire out_wimask_399 = &_out_wimask_T_399; // @[RegisterRouter.scala:87:24] wire out_romask_399 = |_out_romask_T_399; // @[RegisterRouter.scala:87:24] wire out_womask_399 = &_out_womask_T_399; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_399 = out_rivalid_1_253 & out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4236 = out_f_rivalid_399; // @[RegisterRouter.scala:87:24] wire out_f_roready_399 = out_roready_1_253 & out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4237 = out_f_roready_399; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_399 = out_wivalid_1_253 & out_wimask_399; // @[RegisterRouter.scala:87:24] wire out_f_woready_399 = out_woready_1_253 & out_womask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4238 = ~out_rimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4239 = ~out_wimask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4240 = ~out_romask_399; // @[RegisterRouter.scala:87:24] wire _out_T_4241 = ~out_womask_399; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_333 = {hi_46, flags_0_go, _out_prepend_T_333}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4242 = out_prepend_333; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4243 = _out_T_4242; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_334 = _out_T_4243; // @[RegisterRouter.scala:87:24] wire out_rimask_400 = |_out_rimask_T_400; // @[RegisterRouter.scala:87:24] wire out_wimask_400 = &_out_wimask_T_400; // @[RegisterRouter.scala:87:24] wire out_romask_400 = |_out_romask_T_400; // @[RegisterRouter.scala:87:24] wire out_womask_400 = &_out_womask_T_400; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_400 = out_rivalid_1_254 & out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4245 = out_f_rivalid_400; // @[RegisterRouter.scala:87:24] wire out_f_roready_400 = out_roready_1_254 & out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4246 = out_f_roready_400; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_400 = out_wivalid_1_254 & out_wimask_400; // @[RegisterRouter.scala:87:24] wire out_f_woready_400 = out_woready_1_254 & out_womask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4247 = ~out_rimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4248 = ~out_wimask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4249 = ~out_romask_400; // @[RegisterRouter.scala:87:24] wire _out_T_4250 = ~out_womask_400; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_334 = {hi_47, flags_0_go, _out_prepend_T_334}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4251 = out_prepend_334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4252 = _out_T_4251; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_335 = _out_T_4252; // @[RegisterRouter.scala:87:24] wire out_rimask_401 = |_out_rimask_T_401; // @[RegisterRouter.scala:87:24] wire out_wimask_401 = &_out_wimask_T_401; // @[RegisterRouter.scala:87:24] wire out_romask_401 = |_out_romask_T_401; // @[RegisterRouter.scala:87:24] wire out_womask_401 = &_out_womask_T_401; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_401 = out_rivalid_1_255 & out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4254 = out_f_rivalid_401; // @[RegisterRouter.scala:87:24] wire out_f_roready_401 = out_roready_1_255 & out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4255 = out_f_roready_401; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_401 = out_wivalid_1_255 & out_wimask_401; // @[RegisterRouter.scala:87:24] wire out_f_woready_401 = out_woready_1_255 & out_womask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4256 = ~out_rimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4257 = ~out_wimask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4258 = ~out_romask_401; // @[RegisterRouter.scala:87:24] wire _out_T_4259 = ~out_womask_401; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_335 = {hi_48, flags_0_go, _out_prepend_T_335}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4260 = out_prepend_335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4261 = _out_T_4260; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_133 = _out_T_4261; // @[MuxLiteral.scala:49:48] wire out_rimask_402 = |_out_rimask_T_402; // @[RegisterRouter.scala:87:24] wire out_wimask_402 = &_out_wimask_T_402; // @[RegisterRouter.scala:87:24] wire out_romask_402 = |_out_romask_T_402; // @[RegisterRouter.scala:87:24] wire out_womask_402 = &_out_womask_T_402; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_402 = out_rivalid_1_256 & out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4263 = out_f_rivalid_402; // @[RegisterRouter.scala:87:24] wire out_f_roready_402 = out_roready_1_256 & out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4264 = out_f_roready_402; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_402 = out_wivalid_1_256 & out_wimask_402; // @[RegisterRouter.scala:87:24] wire out_f_woready_402 = out_woready_1_256 & out_womask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4265 = ~out_rimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4266 = ~out_wimask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4267 = ~out_romask_402; // @[RegisterRouter.scala:87:24] wire _out_T_4268 = ~out_womask_402; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4270 = _out_T_4269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_336 = _out_T_4270; // @[RegisterRouter.scala:87:24] wire out_rimask_403 = |_out_rimask_T_403; // @[RegisterRouter.scala:87:24] wire out_wimask_403 = &_out_wimask_T_403; // @[RegisterRouter.scala:87:24] wire out_romask_403 = |_out_romask_T_403; // @[RegisterRouter.scala:87:24] wire out_womask_403 = &_out_womask_T_403; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_403 = out_rivalid_1_257 & out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4272 = out_f_rivalid_403; // @[RegisterRouter.scala:87:24] wire out_f_roready_403 = out_roready_1_257 & out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4273 = out_f_roready_403; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_403 = out_wivalid_1_257 & out_wimask_403; // @[RegisterRouter.scala:87:24] wire out_f_woready_403 = out_woready_1_257 & out_womask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4274 = ~out_rimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4275 = ~out_wimask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4276 = ~out_romask_403; // @[RegisterRouter.scala:87:24] wire _out_T_4277 = ~out_womask_403; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_336 = {hi_922, flags_0_go, _out_prepend_T_336}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4278 = out_prepend_336; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4279 = _out_T_4278; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_337 = _out_T_4279; // @[RegisterRouter.scala:87:24] wire out_rimask_404 = |_out_rimask_T_404; // @[RegisterRouter.scala:87:24] wire out_wimask_404 = &_out_wimask_T_404; // @[RegisterRouter.scala:87:24] wire out_romask_404 = |_out_romask_T_404; // @[RegisterRouter.scala:87:24] wire out_womask_404 = &_out_womask_T_404; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_404 = out_rivalid_1_258 & out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4281 = out_f_rivalid_404; // @[RegisterRouter.scala:87:24] wire out_f_roready_404 = out_roready_1_258 & out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4282 = out_f_roready_404; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_404 = out_wivalid_1_258 & out_wimask_404; // @[RegisterRouter.scala:87:24] wire out_f_woready_404 = out_woready_1_258 & out_womask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4283 = ~out_rimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4284 = ~out_wimask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4285 = ~out_romask_404; // @[RegisterRouter.scala:87:24] wire _out_T_4286 = ~out_womask_404; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_337 = {hi_923, flags_0_go, _out_prepend_T_337}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4287 = out_prepend_337; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4288 = _out_T_4287; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_338 = _out_T_4288; // @[RegisterRouter.scala:87:24] wire out_rimask_405 = |_out_rimask_T_405; // @[RegisterRouter.scala:87:24] wire out_wimask_405 = &_out_wimask_T_405; // @[RegisterRouter.scala:87:24] wire out_romask_405 = |_out_romask_T_405; // @[RegisterRouter.scala:87:24] wire out_womask_405 = &_out_womask_T_405; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_405 = out_rivalid_1_259 & out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4290 = out_f_rivalid_405; // @[RegisterRouter.scala:87:24] wire out_f_roready_405 = out_roready_1_259 & out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4291 = out_f_roready_405; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_405 = out_wivalid_1_259 & out_wimask_405; // @[RegisterRouter.scala:87:24] wire out_f_woready_405 = out_woready_1_259 & out_womask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4292 = ~out_rimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4293 = ~out_wimask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4294 = ~out_romask_405; // @[RegisterRouter.scala:87:24] wire _out_T_4295 = ~out_womask_405; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_338 = {hi_924, flags_0_go, _out_prepend_T_338}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4296 = out_prepend_338; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4297 = _out_T_4296; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_339 = _out_T_4297; // @[RegisterRouter.scala:87:24] wire out_rimask_406 = |_out_rimask_T_406; // @[RegisterRouter.scala:87:24] wire out_wimask_406 = &_out_wimask_T_406; // @[RegisterRouter.scala:87:24] wire out_romask_406 = |_out_romask_T_406; // @[RegisterRouter.scala:87:24] wire out_womask_406 = &_out_womask_T_406; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_406 = out_rivalid_1_260 & out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4299 = out_f_rivalid_406; // @[RegisterRouter.scala:87:24] wire out_f_roready_406 = out_roready_1_260 & out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4300 = out_f_roready_406; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_406 = out_wivalid_1_260 & out_wimask_406; // @[RegisterRouter.scala:87:24] wire out_f_woready_406 = out_woready_1_260 & out_womask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4301 = ~out_rimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4302 = ~out_wimask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4303 = ~out_romask_406; // @[RegisterRouter.scala:87:24] wire _out_T_4304 = ~out_womask_406; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_339 = {hi_925, flags_0_go, _out_prepend_T_339}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4305 = out_prepend_339; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4306 = _out_T_4305; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_340 = _out_T_4306; // @[RegisterRouter.scala:87:24] wire out_rimask_407 = |_out_rimask_T_407; // @[RegisterRouter.scala:87:24] wire out_wimask_407 = &_out_wimask_T_407; // @[RegisterRouter.scala:87:24] wire out_romask_407 = |_out_romask_T_407; // @[RegisterRouter.scala:87:24] wire out_womask_407 = &_out_womask_T_407; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_407 = out_rivalid_1_261 & out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4308 = out_f_rivalid_407; // @[RegisterRouter.scala:87:24] wire out_f_roready_407 = out_roready_1_261 & out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4309 = out_f_roready_407; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_407 = out_wivalid_1_261 & out_wimask_407; // @[RegisterRouter.scala:87:24] wire out_f_woready_407 = out_woready_1_261 & out_womask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4310 = ~out_rimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4311 = ~out_wimask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4312 = ~out_romask_407; // @[RegisterRouter.scala:87:24] wire _out_T_4313 = ~out_womask_407; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_340 = {hi_926, flags_0_go, _out_prepend_T_340}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4314 = out_prepend_340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4315 = _out_T_4314; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_341 = _out_T_4315; // @[RegisterRouter.scala:87:24] wire out_rimask_408 = |_out_rimask_T_408; // @[RegisterRouter.scala:87:24] wire out_wimask_408 = &_out_wimask_T_408; // @[RegisterRouter.scala:87:24] wire out_romask_408 = |_out_romask_T_408; // @[RegisterRouter.scala:87:24] wire out_womask_408 = &_out_womask_T_408; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_408 = out_rivalid_1_262 & out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4317 = out_f_rivalid_408; // @[RegisterRouter.scala:87:24] wire out_f_roready_408 = out_roready_1_262 & out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4318 = out_f_roready_408; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_408 = out_wivalid_1_262 & out_wimask_408; // @[RegisterRouter.scala:87:24] wire out_f_woready_408 = out_woready_1_262 & out_womask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4319 = ~out_rimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4320 = ~out_wimask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4321 = ~out_romask_408; // @[RegisterRouter.scala:87:24] wire _out_T_4322 = ~out_womask_408; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_341 = {hi_927, flags_0_go, _out_prepend_T_341}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4323 = out_prepend_341; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4324 = _out_T_4323; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_342 = _out_T_4324; // @[RegisterRouter.scala:87:24] wire out_rimask_409 = |_out_rimask_T_409; // @[RegisterRouter.scala:87:24] wire out_wimask_409 = &_out_wimask_T_409; // @[RegisterRouter.scala:87:24] wire out_romask_409 = |_out_romask_T_409; // @[RegisterRouter.scala:87:24] wire out_womask_409 = &_out_womask_T_409; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_409 = out_rivalid_1_263 & out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4326 = out_f_rivalid_409; // @[RegisterRouter.scala:87:24] wire out_f_roready_409 = out_roready_1_263 & out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4327 = out_f_roready_409; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_409 = out_wivalid_1_263 & out_wimask_409; // @[RegisterRouter.scala:87:24] wire out_f_woready_409 = out_woready_1_263 & out_womask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4328 = ~out_rimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4329 = ~out_wimask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4330 = ~out_romask_409; // @[RegisterRouter.scala:87:24] wire _out_T_4331 = ~out_womask_409; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_342 = {hi_928, flags_0_go, _out_prepend_T_342}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4332 = out_prepend_342; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4333 = _out_T_4332; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_243 = _out_T_4333; // @[MuxLiteral.scala:49:48] wire out_rimask_410 = |_out_rimask_T_410; // @[RegisterRouter.scala:87:24] wire out_wimask_410 = &_out_wimask_T_410; // @[RegisterRouter.scala:87:24] wire out_romask_410 = |_out_romask_T_410; // @[RegisterRouter.scala:87:24] wire out_womask_410 = &_out_womask_T_410; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_410 = out_rivalid_1_264 & out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4335 = out_f_rivalid_410; // @[RegisterRouter.scala:87:24] wire out_f_roready_410 = out_roready_1_264 & out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4336 = out_f_roready_410; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_410 = out_wivalid_1_264 & out_wimask_410; // @[RegisterRouter.scala:87:24] wire out_f_woready_410 = out_woready_1_264 & out_womask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4337 = ~out_rimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4338 = ~out_wimask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4339 = ~out_romask_410; // @[RegisterRouter.scala:87:24] wire _out_T_4340 = ~out_womask_410; // @[RegisterRouter.scala:87:24] wire out_rimask_411 = |_out_rimask_T_411; // @[RegisterRouter.scala:87:24] wire out_wimask_411 = &_out_wimask_T_411; // @[RegisterRouter.scala:87:24] wire out_romask_411 = |_out_romask_T_411; // @[RegisterRouter.scala:87:24] wire out_womask_411 = &_out_womask_T_411; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_411 = out_rivalid_1_265 & out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4344 = out_f_rivalid_411; // @[RegisterRouter.scala:87:24] wire out_f_roready_411 = out_roready_1_265 & out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4345 = out_f_roready_411; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_411 = out_wivalid_1_265 & out_wimask_411; // @[RegisterRouter.scala:87:24] wire out_f_woready_411 = out_woready_1_265 & out_womask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4346 = ~out_rimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4347 = ~out_wimask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4348 = ~out_romask_411; // @[RegisterRouter.scala:87:24] wire _out_T_4349 = ~out_womask_411; // @[RegisterRouter.scala:87:24] wire out_rimask_412 = |_out_rimask_T_412; // @[RegisterRouter.scala:87:24] wire out_wimask_412 = &_out_wimask_T_412; // @[RegisterRouter.scala:87:24] wire out_romask_412 = |_out_romask_T_412; // @[RegisterRouter.scala:87:24] wire out_womask_412 = &_out_womask_T_412; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_412 = out_rivalid_1_266 & out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4353 = out_f_rivalid_412; // @[RegisterRouter.scala:87:24] wire out_f_roready_412 = out_roready_1_266 & out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4354 = out_f_roready_412; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_412 = out_wivalid_1_266 & out_wimask_412; // @[RegisterRouter.scala:87:24] wire out_f_woready_412 = out_woready_1_266 & out_womask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4355 = ~out_rimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4356 = ~out_wimask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4357 = ~out_romask_412; // @[RegisterRouter.scala:87:24] wire _out_T_4358 = ~out_womask_412; // @[RegisterRouter.scala:87:24] wire out_rimask_413 = |_out_rimask_T_413; // @[RegisterRouter.scala:87:24] wire out_wimask_413 = &_out_wimask_T_413; // @[RegisterRouter.scala:87:24] wire out_romask_413 = |_out_romask_T_413; // @[RegisterRouter.scala:87:24] wire out_womask_413 = &_out_womask_T_413; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_413 = out_rivalid_1_267 & out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4362 = out_f_rivalid_413; // @[RegisterRouter.scala:87:24] wire out_f_roready_413 = out_roready_1_267 & out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4363 = out_f_roready_413; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_413 = out_wivalid_1_267 & out_wimask_413; // @[RegisterRouter.scala:87:24] wire out_f_woready_413 = out_woready_1_267 & out_womask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4364 = ~out_rimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4365 = ~out_wimask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4366 = ~out_romask_413; // @[RegisterRouter.scala:87:24] wire _out_T_4367 = ~out_womask_413; // @[RegisterRouter.scala:87:24] wire out_rimask_414 = |_out_rimask_T_414; // @[RegisterRouter.scala:87:24] wire out_wimask_414 = &_out_wimask_T_414; // @[RegisterRouter.scala:87:24] wire out_romask_414 = |_out_romask_T_414; // @[RegisterRouter.scala:87:24] wire out_womask_414 = &_out_womask_T_414; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_414 = out_rivalid_1_268 & out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4371 = out_f_rivalid_414; // @[RegisterRouter.scala:87:24] wire out_f_roready_414 = out_roready_1_268 & out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4372 = out_f_roready_414; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_414 = out_wivalid_1_268 & out_wimask_414; // @[RegisterRouter.scala:87:24] wire out_f_woready_414 = out_woready_1_268 & out_womask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4373 = ~out_rimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4374 = ~out_wimask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4375 = ~out_romask_414; // @[RegisterRouter.scala:87:24] wire _out_T_4376 = ~out_womask_414; // @[RegisterRouter.scala:87:24] wire out_rimask_415 = |_out_rimask_T_415; // @[RegisterRouter.scala:87:24] wire out_wimask_415 = &_out_wimask_T_415; // @[RegisterRouter.scala:87:24] wire out_romask_415 = |_out_romask_T_415; // @[RegisterRouter.scala:87:24] wire out_womask_415 = &_out_womask_T_415; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_415 = out_rivalid_1_269 & out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4380 = out_f_rivalid_415; // @[RegisterRouter.scala:87:24] wire out_f_roready_415 = out_roready_1_269 & out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4381 = out_f_roready_415; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_415 = out_wivalid_1_269 & out_wimask_415; // @[RegisterRouter.scala:87:24] wire out_f_woready_415 = out_woready_1_269 & out_womask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4382 = ~out_rimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4383 = ~out_wimask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4384 = ~out_romask_415; // @[RegisterRouter.scala:87:24] wire _out_T_4385 = ~out_womask_415; // @[RegisterRouter.scala:87:24] wire out_rimask_416 = |_out_rimask_T_416; // @[RegisterRouter.scala:87:24] wire out_wimask_416 = &_out_wimask_T_416; // @[RegisterRouter.scala:87:24] wire out_romask_416 = |_out_romask_T_416; // @[RegisterRouter.scala:87:24] wire out_womask_416 = &_out_womask_T_416; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_416 = out_rivalid_1_270 & out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4389 = out_f_rivalid_416; // @[RegisterRouter.scala:87:24] wire out_f_roready_416 = out_roready_1_270 & out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4390 = out_f_roready_416; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_416 = out_wivalid_1_270 & out_wimask_416; // @[RegisterRouter.scala:87:24] wire out_f_woready_416 = out_woready_1_270 & out_womask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4391 = ~out_rimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4392 = ~out_wimask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4393 = ~out_romask_416; // @[RegisterRouter.scala:87:24] wire _out_T_4394 = ~out_womask_416; // @[RegisterRouter.scala:87:24] wire out_rimask_417 = |_out_rimask_T_417; // @[RegisterRouter.scala:87:24] wire out_wimask_417 = &_out_wimask_T_417; // @[RegisterRouter.scala:87:24] wire out_romask_417 = |_out_romask_T_417; // @[RegisterRouter.scala:87:24] wire out_womask_417 = &_out_womask_T_417; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_417 = out_rivalid_1_271 & out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4398 = out_f_rivalid_417; // @[RegisterRouter.scala:87:24] wire out_f_roready_417 = out_roready_1_271 & out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4399 = out_f_roready_417; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_417 = out_wivalid_1_271 & out_wimask_417; // @[RegisterRouter.scala:87:24] wire out_f_woready_417 = out_woready_1_271 & out_womask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4400 = ~out_rimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4401 = ~out_wimask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4402 = ~out_romask_417; // @[RegisterRouter.scala:87:24] wire _out_T_4403 = ~out_womask_417; // @[RegisterRouter.scala:87:24] wire out_rimask_418 = |_out_rimask_T_418; // @[RegisterRouter.scala:87:24] wire out_wimask_418 = &_out_wimask_T_418; // @[RegisterRouter.scala:87:24] wire out_romask_418 = |_out_romask_T_418; // @[RegisterRouter.scala:87:24] wire out_womask_418 = &_out_womask_T_418; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_418 = out_rivalid_1_272 & out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4407 = out_f_rivalid_418; // @[RegisterRouter.scala:87:24] wire out_f_roready_418 = out_roready_1_272 & out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4408 = out_f_roready_418; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_418 = out_wivalid_1_272 & out_wimask_418; // @[RegisterRouter.scala:87:24] wire out_f_woready_418 = out_woready_1_272 & out_womask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4409 = ~out_rimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4410 = ~out_wimask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4411 = ~out_romask_418; // @[RegisterRouter.scala:87:24] wire _out_T_4412 = ~out_womask_418; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4414 = _out_T_4413; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_350 = _out_T_4414; // @[RegisterRouter.scala:87:24] wire out_rimask_419 = |_out_rimask_T_419; // @[RegisterRouter.scala:87:24] wire out_wimask_419 = &_out_wimask_T_419; // @[RegisterRouter.scala:87:24] wire out_romask_419 = |_out_romask_T_419; // @[RegisterRouter.scala:87:24] wire out_womask_419 = &_out_womask_T_419; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_419 = out_rivalid_1_273 & out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4416 = out_f_rivalid_419; // @[RegisterRouter.scala:87:24] wire out_f_roready_419 = out_roready_1_273 & out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4417 = out_f_roready_419; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_419 = out_wivalid_1_273 & out_wimask_419; // @[RegisterRouter.scala:87:24] wire out_f_woready_419 = out_woready_1_273 & out_womask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4418 = ~out_rimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4419 = ~out_wimask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4420 = ~out_romask_419; // @[RegisterRouter.scala:87:24] wire _out_T_4421 = ~out_womask_419; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_350 = {hi_626, flags_0_go, _out_prepend_T_350}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4422 = out_prepend_350; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4423 = _out_T_4422; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_351 = _out_T_4423; // @[RegisterRouter.scala:87:24] wire out_rimask_420 = |_out_rimask_T_420; // @[RegisterRouter.scala:87:24] wire out_wimask_420 = &_out_wimask_T_420; // @[RegisterRouter.scala:87:24] wire out_romask_420 = |_out_romask_T_420; // @[RegisterRouter.scala:87:24] wire out_womask_420 = &_out_womask_T_420; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_420 = out_rivalid_1_274 & out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4425 = out_f_rivalid_420; // @[RegisterRouter.scala:87:24] wire out_f_roready_420 = out_roready_1_274 & out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4426 = out_f_roready_420; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_420 = out_wivalid_1_274 & out_wimask_420; // @[RegisterRouter.scala:87:24] wire out_f_woready_420 = out_woready_1_274 & out_womask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4427 = ~out_rimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4428 = ~out_wimask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4429 = ~out_romask_420; // @[RegisterRouter.scala:87:24] wire _out_T_4430 = ~out_womask_420; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_351 = {hi_627, flags_0_go, _out_prepend_T_351}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4431 = out_prepend_351; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4432 = _out_T_4431; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_352 = _out_T_4432; // @[RegisterRouter.scala:87:24] wire out_rimask_421 = |_out_rimask_T_421; // @[RegisterRouter.scala:87:24] wire out_wimask_421 = &_out_wimask_T_421; // @[RegisterRouter.scala:87:24] wire out_romask_421 = |_out_romask_T_421; // @[RegisterRouter.scala:87:24] wire out_womask_421 = &_out_womask_T_421; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_421 = out_rivalid_1_275 & out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4434 = out_f_rivalid_421; // @[RegisterRouter.scala:87:24] wire out_f_roready_421 = out_roready_1_275 & out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4435 = out_f_roready_421; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_421 = out_wivalid_1_275 & out_wimask_421; // @[RegisterRouter.scala:87:24] wire out_f_woready_421 = out_woready_1_275 & out_womask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4436 = ~out_rimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4437 = ~out_wimask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4438 = ~out_romask_421; // @[RegisterRouter.scala:87:24] wire _out_T_4439 = ~out_womask_421; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_352 = {hi_628, flags_0_go, _out_prepend_T_352}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4440 = out_prepend_352; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4441 = _out_T_4440; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_353 = _out_T_4441; // @[RegisterRouter.scala:87:24] wire out_rimask_422 = |_out_rimask_T_422; // @[RegisterRouter.scala:87:24] wire out_wimask_422 = &_out_wimask_T_422; // @[RegisterRouter.scala:87:24] wire out_romask_422 = |_out_romask_T_422; // @[RegisterRouter.scala:87:24] wire out_womask_422 = &_out_womask_T_422; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_422 = out_rivalid_1_276 & out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4443 = out_f_rivalid_422; // @[RegisterRouter.scala:87:24] wire out_f_roready_422 = out_roready_1_276 & out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4444 = out_f_roready_422; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_422 = out_wivalid_1_276 & out_wimask_422; // @[RegisterRouter.scala:87:24] wire out_f_woready_422 = out_woready_1_276 & out_womask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4445 = ~out_rimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4446 = ~out_wimask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4447 = ~out_romask_422; // @[RegisterRouter.scala:87:24] wire _out_T_4448 = ~out_womask_422; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_353 = {hi_629, flags_0_go, _out_prepend_T_353}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4449 = out_prepend_353; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4450 = _out_T_4449; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_354 = _out_T_4450; // @[RegisterRouter.scala:87:24] wire out_rimask_423 = |_out_rimask_T_423; // @[RegisterRouter.scala:87:24] wire out_wimask_423 = &_out_wimask_T_423; // @[RegisterRouter.scala:87:24] wire out_romask_423 = |_out_romask_T_423; // @[RegisterRouter.scala:87:24] wire out_womask_423 = &_out_womask_T_423; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_423 = out_rivalid_1_277 & out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4452 = out_f_rivalid_423; // @[RegisterRouter.scala:87:24] wire out_f_roready_423 = out_roready_1_277 & out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4453 = out_f_roready_423; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_423 = out_wivalid_1_277 & out_wimask_423; // @[RegisterRouter.scala:87:24] wire out_f_woready_423 = out_woready_1_277 & out_womask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4454 = ~out_rimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4455 = ~out_wimask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4456 = ~out_romask_423; // @[RegisterRouter.scala:87:24] wire _out_T_4457 = ~out_womask_423; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_354 = {hi_630, flags_0_go, _out_prepend_T_354}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4458 = out_prepend_354; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4459 = _out_T_4458; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_355 = _out_T_4459; // @[RegisterRouter.scala:87:24] wire out_rimask_424 = |_out_rimask_T_424; // @[RegisterRouter.scala:87:24] wire out_wimask_424 = &_out_wimask_T_424; // @[RegisterRouter.scala:87:24] wire out_romask_424 = |_out_romask_T_424; // @[RegisterRouter.scala:87:24] wire out_womask_424 = &_out_womask_T_424; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_424 = out_rivalid_1_278 & out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4461 = out_f_rivalid_424; // @[RegisterRouter.scala:87:24] wire out_f_roready_424 = out_roready_1_278 & out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4462 = out_f_roready_424; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_424 = out_wivalid_1_278 & out_wimask_424; // @[RegisterRouter.scala:87:24] wire out_f_woready_424 = out_woready_1_278 & out_womask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4463 = ~out_rimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4464 = ~out_wimask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4465 = ~out_romask_424; // @[RegisterRouter.scala:87:24] wire _out_T_4466 = ~out_womask_424; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_355 = {hi_631, flags_0_go, _out_prepend_T_355}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4467 = out_prepend_355; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4468 = _out_T_4467; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_356 = _out_T_4468; // @[RegisterRouter.scala:87:24] wire out_rimask_425 = |_out_rimask_T_425; // @[RegisterRouter.scala:87:24] wire out_wimask_425 = &_out_wimask_T_425; // @[RegisterRouter.scala:87:24] wire out_romask_425 = |_out_romask_T_425; // @[RegisterRouter.scala:87:24] wire out_womask_425 = &_out_womask_T_425; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_425 = out_rivalid_1_279 & out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4470 = out_f_rivalid_425; // @[RegisterRouter.scala:87:24] wire out_f_roready_425 = out_roready_1_279 & out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4471 = out_f_roready_425; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_425 = out_wivalid_1_279 & out_wimask_425; // @[RegisterRouter.scala:87:24] wire out_f_woready_425 = out_woready_1_279 & out_womask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4472 = ~out_rimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4473 = ~out_wimask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4474 = ~out_romask_425; // @[RegisterRouter.scala:87:24] wire _out_T_4475 = ~out_womask_425; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_356 = {hi_632, flags_0_go, _out_prepend_T_356}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4476 = out_prepend_356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4477 = _out_T_4476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_206 = _out_T_4477; // @[MuxLiteral.scala:49:48] wire out_rimask_426 = |_out_rimask_T_426; // @[RegisterRouter.scala:87:24] wire out_wimask_426 = &_out_wimask_T_426; // @[RegisterRouter.scala:87:24] wire out_romask_426 = |_out_romask_T_426; // @[RegisterRouter.scala:87:24] wire out_womask_426 = &_out_womask_T_426; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_426 = out_rivalid_1_280 & out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4479 = out_f_rivalid_426; // @[RegisterRouter.scala:87:24] wire out_f_roready_426 = out_roready_1_280 & out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4480 = out_f_roready_426; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_426 = out_wivalid_1_280 & out_wimask_426; // @[RegisterRouter.scala:87:24] wire out_f_woready_426 = out_woready_1_280 & out_womask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4481 = ~out_rimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4482 = ~out_wimask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4483 = ~out_romask_426; // @[RegisterRouter.scala:87:24] wire _out_T_4484 = ~out_womask_426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4486 = _out_T_4485; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_357 = _out_T_4486; // @[RegisterRouter.scala:87:24] wire out_rimask_427 = |_out_rimask_T_427; // @[RegisterRouter.scala:87:24] wire out_wimask_427 = &_out_wimask_T_427; // @[RegisterRouter.scala:87:24] wire out_romask_427 = |_out_romask_T_427; // @[RegisterRouter.scala:87:24] wire out_womask_427 = &_out_womask_T_427; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_427 = out_rivalid_1_281 & out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4488 = out_f_rivalid_427; // @[RegisterRouter.scala:87:24] wire out_f_roready_427 = out_roready_1_281 & out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4489 = out_f_roready_427; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_427 = out_wivalid_1_281 & out_wimask_427; // @[RegisterRouter.scala:87:24] wire out_f_woready_427 = out_woready_1_281 & out_womask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4490 = ~out_rimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4491 = ~out_wimask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4492 = ~out_romask_427; // @[RegisterRouter.scala:87:24] wire _out_T_4493 = ~out_womask_427; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_357 = {hi_842, flags_0_go, _out_prepend_T_357}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4494 = out_prepend_357; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4495 = _out_T_4494; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_358 = _out_T_4495; // @[RegisterRouter.scala:87:24] wire out_rimask_428 = |_out_rimask_T_428; // @[RegisterRouter.scala:87:24] wire out_wimask_428 = &_out_wimask_T_428; // @[RegisterRouter.scala:87:24] wire out_romask_428 = |_out_romask_T_428; // @[RegisterRouter.scala:87:24] wire out_womask_428 = &_out_womask_T_428; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_428 = out_rivalid_1_282 & out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4497 = out_f_rivalid_428; // @[RegisterRouter.scala:87:24] wire out_f_roready_428 = out_roready_1_282 & out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4498 = out_f_roready_428; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_428 = out_wivalid_1_282 & out_wimask_428; // @[RegisterRouter.scala:87:24] wire out_f_woready_428 = out_woready_1_282 & out_womask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4499 = ~out_rimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4500 = ~out_wimask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4501 = ~out_romask_428; // @[RegisterRouter.scala:87:24] wire _out_T_4502 = ~out_womask_428; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_358 = {hi_843, flags_0_go, _out_prepend_T_358}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4503 = out_prepend_358; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4504 = _out_T_4503; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_359 = _out_T_4504; // @[RegisterRouter.scala:87:24] wire out_rimask_429 = |_out_rimask_T_429; // @[RegisterRouter.scala:87:24] wire out_wimask_429 = &_out_wimask_T_429; // @[RegisterRouter.scala:87:24] wire out_romask_429 = |_out_romask_T_429; // @[RegisterRouter.scala:87:24] wire out_womask_429 = &_out_womask_T_429; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_429 = out_rivalid_1_283 & out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4506 = out_f_rivalid_429; // @[RegisterRouter.scala:87:24] wire out_f_roready_429 = out_roready_1_283 & out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4507 = out_f_roready_429; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_429 = out_wivalid_1_283 & out_wimask_429; // @[RegisterRouter.scala:87:24] wire out_f_woready_429 = out_woready_1_283 & out_womask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4508 = ~out_rimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4509 = ~out_wimask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4510 = ~out_romask_429; // @[RegisterRouter.scala:87:24] wire _out_T_4511 = ~out_womask_429; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_359 = {hi_844, flags_0_go, _out_prepend_T_359}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4512 = out_prepend_359; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4513 = _out_T_4512; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_360 = _out_T_4513; // @[RegisterRouter.scala:87:24] wire out_rimask_430 = |_out_rimask_T_430; // @[RegisterRouter.scala:87:24] wire out_wimask_430 = &_out_wimask_T_430; // @[RegisterRouter.scala:87:24] wire out_romask_430 = |_out_romask_T_430; // @[RegisterRouter.scala:87:24] wire out_womask_430 = &_out_womask_T_430; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_430 = out_rivalid_1_284 & out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4515 = out_f_rivalid_430; // @[RegisterRouter.scala:87:24] wire out_f_roready_430 = out_roready_1_284 & out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4516 = out_f_roready_430; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_430 = out_wivalid_1_284 & out_wimask_430; // @[RegisterRouter.scala:87:24] wire out_f_woready_430 = out_woready_1_284 & out_womask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4517 = ~out_rimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4518 = ~out_wimask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4519 = ~out_romask_430; // @[RegisterRouter.scala:87:24] wire _out_T_4520 = ~out_womask_430; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_360 = {hi_845, flags_0_go, _out_prepend_T_360}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4521 = out_prepend_360; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4522 = _out_T_4521; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_361 = _out_T_4522; // @[RegisterRouter.scala:87:24] wire out_rimask_431 = |_out_rimask_T_431; // @[RegisterRouter.scala:87:24] wire out_wimask_431 = &_out_wimask_T_431; // @[RegisterRouter.scala:87:24] wire out_romask_431 = |_out_romask_T_431; // @[RegisterRouter.scala:87:24] wire out_womask_431 = &_out_womask_T_431; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_431 = out_rivalid_1_285 & out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4524 = out_f_rivalid_431; // @[RegisterRouter.scala:87:24] wire out_f_roready_431 = out_roready_1_285 & out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4525 = out_f_roready_431; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_431 = out_wivalid_1_285 & out_wimask_431; // @[RegisterRouter.scala:87:24] wire out_f_woready_431 = out_woready_1_285 & out_womask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4526 = ~out_rimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4527 = ~out_wimask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4528 = ~out_romask_431; // @[RegisterRouter.scala:87:24] wire _out_T_4529 = ~out_womask_431; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_361 = {hi_846, flags_0_go, _out_prepend_T_361}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4530 = out_prepend_361; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4531 = _out_T_4530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_362 = _out_T_4531; // @[RegisterRouter.scala:87:24] wire out_rimask_432 = |_out_rimask_T_432; // @[RegisterRouter.scala:87:24] wire out_wimask_432 = &_out_wimask_T_432; // @[RegisterRouter.scala:87:24] wire out_romask_432 = |_out_romask_T_432; // @[RegisterRouter.scala:87:24] wire out_womask_432 = &_out_womask_T_432; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_432 = out_rivalid_1_286 & out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4533 = out_f_rivalid_432; // @[RegisterRouter.scala:87:24] wire out_f_roready_432 = out_roready_1_286 & out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4534 = out_f_roready_432; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_432 = out_wivalid_1_286 & out_wimask_432; // @[RegisterRouter.scala:87:24] wire out_f_woready_432 = out_woready_1_286 & out_womask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4535 = ~out_rimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4536 = ~out_wimask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4537 = ~out_romask_432; // @[RegisterRouter.scala:87:24] wire _out_T_4538 = ~out_womask_432; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_362 = {hi_847, flags_0_go, _out_prepend_T_362}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4539 = out_prepend_362; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4540 = _out_T_4539; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_363 = _out_T_4540; // @[RegisterRouter.scala:87:24] wire out_rimask_433 = |_out_rimask_T_433; // @[RegisterRouter.scala:87:24] wire out_wimask_433 = &_out_wimask_T_433; // @[RegisterRouter.scala:87:24] wire out_romask_433 = |_out_romask_T_433; // @[RegisterRouter.scala:87:24] wire out_womask_433 = &_out_womask_T_433; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_433 = out_rivalid_1_287 & out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4542 = out_f_rivalid_433; // @[RegisterRouter.scala:87:24] wire out_f_roready_433 = out_roready_1_287 & out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4543 = out_f_roready_433; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_433 = out_wivalid_1_287 & out_wimask_433; // @[RegisterRouter.scala:87:24] wire out_f_woready_433 = out_woready_1_287 & out_womask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4544 = ~out_rimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4545 = ~out_wimask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4546 = ~out_romask_433; // @[RegisterRouter.scala:87:24] wire _out_T_4547 = ~out_womask_433; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_363 = {hi_848, flags_0_go, _out_prepend_T_363}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4548 = out_prepend_363; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4549 = _out_T_4548; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_233 = _out_T_4549; // @[MuxLiteral.scala:49:48] wire out_rimask_434 = |_out_rimask_T_434; // @[RegisterRouter.scala:87:24] wire out_wimask_434 = &_out_wimask_T_434; // @[RegisterRouter.scala:87:24] wire out_romask_434 = |_out_romask_T_434; // @[RegisterRouter.scala:87:24] wire out_womask_434 = &_out_womask_T_434; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_434 = out_rivalid_1_288 & out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4551 = out_f_rivalid_434; // @[RegisterRouter.scala:87:24] wire out_f_roready_434 = out_roready_1_288 & out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4552 = out_f_roready_434; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_434 = out_wivalid_1_288 & out_wimask_434; // @[RegisterRouter.scala:87:24] wire out_f_woready_434 = out_woready_1_288 & out_womask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4553 = ~out_rimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4554 = ~out_wimask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4555 = ~out_romask_434; // @[RegisterRouter.scala:87:24] wire _out_T_4556 = ~out_womask_434; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4558 = _out_T_4557; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_364 = _out_T_4558; // @[RegisterRouter.scala:87:24] wire out_rimask_435 = |_out_rimask_T_435; // @[RegisterRouter.scala:87:24] wire out_wimask_435 = &_out_wimask_T_435; // @[RegisterRouter.scala:87:24] wire out_romask_435 = |_out_romask_T_435; // @[RegisterRouter.scala:87:24] wire out_womask_435 = &_out_womask_T_435; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_435 = out_rivalid_1_289 & out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4560 = out_f_rivalid_435; // @[RegisterRouter.scala:87:24] wire out_f_roready_435 = out_roready_1_289 & out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4561 = out_f_roready_435; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_435 = out_wivalid_1_289 & out_wimask_435; // @[RegisterRouter.scala:87:24] wire out_f_woready_435 = out_woready_1_289 & out_womask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4562 = ~out_rimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4563 = ~out_wimask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4564 = ~out_romask_435; // @[RegisterRouter.scala:87:24] wire _out_T_4565 = ~out_womask_435; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_364 = {hi_962, flags_0_go, _out_prepend_T_364}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4566 = out_prepend_364; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4567 = _out_T_4566; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_365 = _out_T_4567; // @[RegisterRouter.scala:87:24] wire out_rimask_436 = |_out_rimask_T_436; // @[RegisterRouter.scala:87:24] wire out_wimask_436 = &_out_wimask_T_436; // @[RegisterRouter.scala:87:24] wire out_romask_436 = |_out_romask_T_436; // @[RegisterRouter.scala:87:24] wire out_womask_436 = &_out_womask_T_436; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_436 = out_rivalid_1_290 & out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4569 = out_f_rivalid_436; // @[RegisterRouter.scala:87:24] wire out_f_roready_436 = out_roready_1_290 & out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4570 = out_f_roready_436; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_436 = out_wivalid_1_290 & out_wimask_436; // @[RegisterRouter.scala:87:24] wire out_f_woready_436 = out_woready_1_290 & out_womask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4571 = ~out_rimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4572 = ~out_wimask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4573 = ~out_romask_436; // @[RegisterRouter.scala:87:24] wire _out_T_4574 = ~out_womask_436; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_365 = {hi_963, flags_0_go, _out_prepend_T_365}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4575 = out_prepend_365; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4576 = _out_T_4575; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_366 = _out_T_4576; // @[RegisterRouter.scala:87:24] wire out_rimask_437 = |_out_rimask_T_437; // @[RegisterRouter.scala:87:24] wire out_wimask_437 = &_out_wimask_T_437; // @[RegisterRouter.scala:87:24] wire out_romask_437 = |_out_romask_T_437; // @[RegisterRouter.scala:87:24] wire out_womask_437 = &_out_womask_T_437; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_437 = out_rivalid_1_291 & out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4578 = out_f_rivalid_437; // @[RegisterRouter.scala:87:24] wire out_f_roready_437 = out_roready_1_291 & out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4579 = out_f_roready_437; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_437 = out_wivalid_1_291 & out_wimask_437; // @[RegisterRouter.scala:87:24] wire out_f_woready_437 = out_woready_1_291 & out_womask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4580 = ~out_rimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4581 = ~out_wimask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4582 = ~out_romask_437; // @[RegisterRouter.scala:87:24] wire _out_T_4583 = ~out_womask_437; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_366 = {hi_964, flags_0_go, _out_prepend_T_366}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4584 = out_prepend_366; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4585 = _out_T_4584; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_367 = _out_T_4585; // @[RegisterRouter.scala:87:24] wire out_rimask_438 = |_out_rimask_T_438; // @[RegisterRouter.scala:87:24] wire out_wimask_438 = &_out_wimask_T_438; // @[RegisterRouter.scala:87:24] wire out_romask_438 = |_out_romask_T_438; // @[RegisterRouter.scala:87:24] wire out_womask_438 = &_out_womask_T_438; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_438 = out_rivalid_1_292 & out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4587 = out_f_rivalid_438; // @[RegisterRouter.scala:87:24] wire out_f_roready_438 = out_roready_1_292 & out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4588 = out_f_roready_438; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_438 = out_wivalid_1_292 & out_wimask_438; // @[RegisterRouter.scala:87:24] wire out_f_woready_438 = out_woready_1_292 & out_womask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4589 = ~out_rimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4590 = ~out_wimask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4591 = ~out_romask_438; // @[RegisterRouter.scala:87:24] wire _out_T_4592 = ~out_womask_438; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_367 = {hi_965, flags_0_go, _out_prepend_T_367}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4593 = out_prepend_367; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4594 = _out_T_4593; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_368 = _out_T_4594; // @[RegisterRouter.scala:87:24] wire out_rimask_439 = |_out_rimask_T_439; // @[RegisterRouter.scala:87:24] wire out_wimask_439 = &_out_wimask_T_439; // @[RegisterRouter.scala:87:24] wire out_romask_439 = |_out_romask_T_439; // @[RegisterRouter.scala:87:24] wire out_womask_439 = &_out_womask_T_439; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_439 = out_rivalid_1_293 & out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4596 = out_f_rivalid_439; // @[RegisterRouter.scala:87:24] wire out_f_roready_439 = out_roready_1_293 & out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4597 = out_f_roready_439; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_439 = out_wivalid_1_293 & out_wimask_439; // @[RegisterRouter.scala:87:24] wire out_f_woready_439 = out_woready_1_293 & out_womask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4598 = ~out_rimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4599 = ~out_wimask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4600 = ~out_romask_439; // @[RegisterRouter.scala:87:24] wire _out_T_4601 = ~out_womask_439; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_368 = {hi_966, flags_0_go, _out_prepend_T_368}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4602 = out_prepend_368; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4603 = _out_T_4602; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_369 = _out_T_4603; // @[RegisterRouter.scala:87:24] wire out_rimask_440 = |_out_rimask_T_440; // @[RegisterRouter.scala:87:24] wire out_wimask_440 = &_out_wimask_T_440; // @[RegisterRouter.scala:87:24] wire out_romask_440 = |_out_romask_T_440; // @[RegisterRouter.scala:87:24] wire out_womask_440 = &_out_womask_T_440; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_440 = out_rivalid_1_294 & out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4605 = out_f_rivalid_440; // @[RegisterRouter.scala:87:24] wire out_f_roready_440 = out_roready_1_294 & out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4606 = out_f_roready_440; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_440 = out_wivalid_1_294 & out_wimask_440; // @[RegisterRouter.scala:87:24] wire out_f_woready_440 = out_woready_1_294 & out_womask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4607 = ~out_rimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4608 = ~out_wimask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4609 = ~out_romask_440; // @[RegisterRouter.scala:87:24] wire _out_T_4610 = ~out_womask_440; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_369 = {hi_967, flags_0_go, _out_prepend_T_369}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4611 = out_prepend_369; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4612 = _out_T_4611; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_370 = _out_T_4612; // @[RegisterRouter.scala:87:24] wire out_rimask_441 = |_out_rimask_T_441; // @[RegisterRouter.scala:87:24] wire out_wimask_441 = &_out_wimask_T_441; // @[RegisterRouter.scala:87:24] wire out_romask_441 = |_out_romask_T_441; // @[RegisterRouter.scala:87:24] wire out_womask_441 = &_out_womask_T_441; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_441 = out_rivalid_1_295 & out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4614 = out_f_rivalid_441; // @[RegisterRouter.scala:87:24] wire out_f_roready_441 = out_roready_1_295 & out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4615 = out_f_roready_441; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_441 = out_wivalid_1_295 & out_wimask_441; // @[RegisterRouter.scala:87:24] wire out_f_woready_441 = out_woready_1_295 & out_womask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4616 = ~out_rimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4617 = ~out_wimask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4618 = ~out_romask_441; // @[RegisterRouter.scala:87:24] wire _out_T_4619 = ~out_womask_441; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_370 = {hi_968, flags_0_go, _out_prepend_T_370}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4620 = out_prepend_370; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4621 = _out_T_4620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_248 = _out_T_4621; // @[MuxLiteral.scala:49:48] wire out_rimask_442 = |_out_rimask_T_442; // @[RegisterRouter.scala:87:24] wire out_wimask_442 = &_out_wimask_T_442; // @[RegisterRouter.scala:87:24] wire out_romask_442 = |_out_romask_T_442; // @[RegisterRouter.scala:87:24] wire out_womask_442 = &_out_womask_T_442; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_442 = out_rivalid_1_296 & out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4623 = out_f_rivalid_442; // @[RegisterRouter.scala:87:24] wire out_f_roready_442 = out_roready_1_296 & out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4624 = out_f_roready_442; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_442 = out_wivalid_1_296 & out_wimask_442; // @[RegisterRouter.scala:87:24] wire out_f_woready_442 = out_woready_1_296 & out_womask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4625 = ~out_rimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4626 = ~out_wimask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4627 = ~out_romask_442; // @[RegisterRouter.scala:87:24] wire _out_T_4628 = ~out_womask_442; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4630 = _out_T_4629; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_371 = _out_T_4630; // @[RegisterRouter.scala:87:24] wire out_rimask_443 = |_out_rimask_T_443; // @[RegisterRouter.scala:87:24] wire out_wimask_443 = &_out_wimask_T_443; // @[RegisterRouter.scala:87:24] wire out_romask_443 = |_out_romask_T_443; // @[RegisterRouter.scala:87:24] wire out_womask_443 = &_out_womask_T_443; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_443 = out_rivalid_1_297 & out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4632 = out_f_rivalid_443; // @[RegisterRouter.scala:87:24] wire out_f_roready_443 = out_roready_1_297 & out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4633 = out_f_roready_443; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_443 = out_wivalid_1_297 & out_wimask_443; // @[RegisterRouter.scala:87:24] wire out_f_woready_443 = out_woready_1_297 & out_womask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4634 = ~out_rimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4635 = ~out_wimask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4636 = ~out_romask_443; // @[RegisterRouter.scala:87:24] wire _out_T_4637 = ~out_womask_443; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_371 = {hi_586, flags_0_go, _out_prepend_T_371}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4638 = out_prepend_371; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4639 = _out_T_4638; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_372 = _out_T_4639; // @[RegisterRouter.scala:87:24] wire out_rimask_444 = |_out_rimask_T_444; // @[RegisterRouter.scala:87:24] wire out_wimask_444 = &_out_wimask_T_444; // @[RegisterRouter.scala:87:24] wire out_romask_444 = |_out_romask_T_444; // @[RegisterRouter.scala:87:24] wire out_womask_444 = &_out_womask_T_444; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_444 = out_rivalid_1_298 & out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4641 = out_f_rivalid_444; // @[RegisterRouter.scala:87:24] wire out_f_roready_444 = out_roready_1_298 & out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4642 = out_f_roready_444; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_444 = out_wivalid_1_298 & out_wimask_444; // @[RegisterRouter.scala:87:24] wire out_f_woready_444 = out_woready_1_298 & out_womask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4643 = ~out_rimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4644 = ~out_wimask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4645 = ~out_romask_444; // @[RegisterRouter.scala:87:24] wire _out_T_4646 = ~out_womask_444; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_372 = {hi_587, flags_0_go, _out_prepend_T_372}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4647 = out_prepend_372; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4648 = _out_T_4647; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_373 = _out_T_4648; // @[RegisterRouter.scala:87:24] wire out_rimask_445 = |_out_rimask_T_445; // @[RegisterRouter.scala:87:24] wire out_wimask_445 = &_out_wimask_T_445; // @[RegisterRouter.scala:87:24] wire out_romask_445 = |_out_romask_T_445; // @[RegisterRouter.scala:87:24] wire out_womask_445 = &_out_womask_T_445; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_445 = out_rivalid_1_299 & out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4650 = out_f_rivalid_445; // @[RegisterRouter.scala:87:24] wire out_f_roready_445 = out_roready_1_299 & out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4651 = out_f_roready_445; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_445 = out_wivalid_1_299 & out_wimask_445; // @[RegisterRouter.scala:87:24] wire out_f_woready_445 = out_woready_1_299 & out_womask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4652 = ~out_rimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4653 = ~out_wimask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4654 = ~out_romask_445; // @[RegisterRouter.scala:87:24] wire _out_T_4655 = ~out_womask_445; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_373 = {hi_588, flags_0_go, _out_prepend_T_373}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4656 = out_prepend_373; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4657 = _out_T_4656; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_374 = _out_T_4657; // @[RegisterRouter.scala:87:24] wire out_rimask_446 = |_out_rimask_T_446; // @[RegisterRouter.scala:87:24] wire out_wimask_446 = &_out_wimask_T_446; // @[RegisterRouter.scala:87:24] wire out_romask_446 = |_out_romask_T_446; // @[RegisterRouter.scala:87:24] wire out_womask_446 = &_out_womask_T_446; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_446 = out_rivalid_1_300 & out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4659 = out_f_rivalid_446; // @[RegisterRouter.scala:87:24] wire out_f_roready_446 = out_roready_1_300 & out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4660 = out_f_roready_446; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_446 = out_wivalid_1_300 & out_wimask_446; // @[RegisterRouter.scala:87:24] wire out_f_woready_446 = out_woready_1_300 & out_womask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4661 = ~out_rimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4662 = ~out_wimask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4663 = ~out_romask_446; // @[RegisterRouter.scala:87:24] wire _out_T_4664 = ~out_womask_446; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_374 = {hi_589, flags_0_go, _out_prepend_T_374}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4665 = out_prepend_374; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4666 = _out_T_4665; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_375 = _out_T_4666; // @[RegisterRouter.scala:87:24] wire out_rimask_447 = |_out_rimask_T_447; // @[RegisterRouter.scala:87:24] wire out_wimask_447 = &_out_wimask_T_447; // @[RegisterRouter.scala:87:24] wire out_romask_447 = |_out_romask_T_447; // @[RegisterRouter.scala:87:24] wire out_womask_447 = &_out_womask_T_447; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_447 = out_rivalid_1_301 & out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4668 = out_f_rivalid_447; // @[RegisterRouter.scala:87:24] wire out_f_roready_447 = out_roready_1_301 & out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4669 = out_f_roready_447; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_447 = out_wivalid_1_301 & out_wimask_447; // @[RegisterRouter.scala:87:24] wire out_f_woready_447 = out_woready_1_301 & out_womask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4670 = ~out_rimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4671 = ~out_wimask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4672 = ~out_romask_447; // @[RegisterRouter.scala:87:24] wire _out_T_4673 = ~out_womask_447; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_375 = {hi_590, flags_0_go, _out_prepend_T_375}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4674 = out_prepend_375; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4675 = _out_T_4674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_376 = _out_T_4675; // @[RegisterRouter.scala:87:24] wire out_rimask_448 = |_out_rimask_T_448; // @[RegisterRouter.scala:87:24] wire out_wimask_448 = &_out_wimask_T_448; // @[RegisterRouter.scala:87:24] wire out_romask_448 = |_out_romask_T_448; // @[RegisterRouter.scala:87:24] wire out_womask_448 = &_out_womask_T_448; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_448 = out_rivalid_1_302 & out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4677 = out_f_rivalid_448; // @[RegisterRouter.scala:87:24] wire out_f_roready_448 = out_roready_1_302 & out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4678 = out_f_roready_448; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_448 = out_wivalid_1_302 & out_wimask_448; // @[RegisterRouter.scala:87:24] wire out_f_woready_448 = out_woready_1_302 & out_womask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4679 = ~out_rimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4680 = ~out_wimask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4681 = ~out_romask_448; // @[RegisterRouter.scala:87:24] wire _out_T_4682 = ~out_womask_448; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_376 = {hi_591, flags_0_go, _out_prepend_T_376}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4683 = out_prepend_376; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4684 = _out_T_4683; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_377 = _out_T_4684; // @[RegisterRouter.scala:87:24] wire out_rimask_449 = |_out_rimask_T_449; // @[RegisterRouter.scala:87:24] wire out_wimask_449 = &_out_wimask_T_449; // @[RegisterRouter.scala:87:24] wire out_romask_449 = |_out_romask_T_449; // @[RegisterRouter.scala:87:24] wire out_womask_449 = &_out_womask_T_449; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_449 = out_rivalid_1_303 & out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4686 = out_f_rivalid_449; // @[RegisterRouter.scala:87:24] wire out_f_roready_449 = out_roready_1_303 & out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4687 = out_f_roready_449; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_449 = out_wivalid_1_303 & out_wimask_449; // @[RegisterRouter.scala:87:24] wire out_f_woready_449 = out_woready_1_303 & out_womask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4688 = ~out_rimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4689 = ~out_wimask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4690 = ~out_romask_449; // @[RegisterRouter.scala:87:24] wire _out_T_4691 = ~out_womask_449; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_377 = {hi_592, flags_0_go, _out_prepend_T_377}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4692 = out_prepend_377; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4693 = _out_T_4692; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_201 = _out_T_4693; // @[MuxLiteral.scala:49:48] wire out_rimask_450 = |_out_rimask_T_450; // @[RegisterRouter.scala:87:24] wire out_wimask_450 = &_out_wimask_T_450; // @[RegisterRouter.scala:87:24] wire out_romask_450 = |_out_romask_T_450; // @[RegisterRouter.scala:87:24] wire out_womask_450 = &_out_womask_T_450; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_450 = out_rivalid_1_304 & out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4695 = out_f_rivalid_450; // @[RegisterRouter.scala:87:24] wire out_f_roready_450 = out_roready_1_304 & out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4696 = out_f_roready_450; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_450 = out_wivalid_1_304 & out_wimask_450; // @[RegisterRouter.scala:87:24] wire out_f_woready_450 = out_woready_1_304 & out_womask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4697 = ~out_rimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4698 = ~out_wimask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4699 = ~out_romask_450; // @[RegisterRouter.scala:87:24] wire _out_T_4700 = ~out_womask_450; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4702 = _out_T_4701; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_378 = _out_T_4702; // @[RegisterRouter.scala:87:24] wire out_rimask_451 = |_out_rimask_T_451; // @[RegisterRouter.scala:87:24] wire out_wimask_451 = &_out_wimask_T_451; // @[RegisterRouter.scala:87:24] wire out_romask_451 = |_out_romask_T_451; // @[RegisterRouter.scala:87:24] wire out_womask_451 = &_out_womask_T_451; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_451 = out_rivalid_1_305 & out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4704 = out_f_rivalid_451; // @[RegisterRouter.scala:87:24] wire out_f_roready_451 = out_roready_1_305 & out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4705 = out_f_roready_451; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_451 = out_wivalid_1_305 & out_wimask_451; // @[RegisterRouter.scala:87:24] wire out_f_woready_451 = out_woready_1_305 & out_womask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4706 = ~out_rimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4707 = ~out_wimask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4708 = ~out_romask_451; // @[RegisterRouter.scala:87:24] wire _out_T_4709 = ~out_womask_451; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_378 = {hi_738, flags_0_go, _out_prepend_T_378}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4710 = out_prepend_378; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4711 = _out_T_4710; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_379 = _out_T_4711; // @[RegisterRouter.scala:87:24] wire out_rimask_452 = |_out_rimask_T_452; // @[RegisterRouter.scala:87:24] wire out_wimask_452 = &_out_wimask_T_452; // @[RegisterRouter.scala:87:24] wire out_romask_452 = |_out_romask_T_452; // @[RegisterRouter.scala:87:24] wire out_womask_452 = &_out_womask_T_452; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_452 = out_rivalid_1_306 & out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4713 = out_f_rivalid_452; // @[RegisterRouter.scala:87:24] wire out_f_roready_452 = out_roready_1_306 & out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4714 = out_f_roready_452; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_452 = out_wivalid_1_306 & out_wimask_452; // @[RegisterRouter.scala:87:24] wire out_f_woready_452 = out_woready_1_306 & out_womask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4715 = ~out_rimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4716 = ~out_wimask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4717 = ~out_romask_452; // @[RegisterRouter.scala:87:24] wire _out_T_4718 = ~out_womask_452; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_379 = {hi_739, flags_0_go, _out_prepend_T_379}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4719 = out_prepend_379; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4720 = _out_T_4719; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_380 = _out_T_4720; // @[RegisterRouter.scala:87:24] wire out_rimask_453 = |_out_rimask_T_453; // @[RegisterRouter.scala:87:24] wire out_wimask_453 = &_out_wimask_T_453; // @[RegisterRouter.scala:87:24] wire out_romask_453 = |_out_romask_T_453; // @[RegisterRouter.scala:87:24] wire out_womask_453 = &_out_womask_T_453; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_453 = out_rivalid_1_307 & out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4722 = out_f_rivalid_453; // @[RegisterRouter.scala:87:24] wire out_f_roready_453 = out_roready_1_307 & out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4723 = out_f_roready_453; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_453 = out_wivalid_1_307 & out_wimask_453; // @[RegisterRouter.scala:87:24] wire out_f_woready_453 = out_woready_1_307 & out_womask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4724 = ~out_rimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4725 = ~out_wimask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4726 = ~out_romask_453; // @[RegisterRouter.scala:87:24] wire _out_T_4727 = ~out_womask_453; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_380 = {hi_740, flags_0_go, _out_prepend_T_380}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4728 = out_prepend_380; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4729 = _out_T_4728; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_381 = _out_T_4729; // @[RegisterRouter.scala:87:24] wire out_rimask_454 = |_out_rimask_T_454; // @[RegisterRouter.scala:87:24] wire out_wimask_454 = &_out_wimask_T_454; // @[RegisterRouter.scala:87:24] wire out_romask_454 = |_out_romask_T_454; // @[RegisterRouter.scala:87:24] wire out_womask_454 = &_out_womask_T_454; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_454 = out_rivalid_1_308 & out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4731 = out_f_rivalid_454; // @[RegisterRouter.scala:87:24] wire out_f_roready_454 = out_roready_1_308 & out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4732 = out_f_roready_454; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_454 = out_wivalid_1_308 & out_wimask_454; // @[RegisterRouter.scala:87:24] wire out_f_woready_454 = out_woready_1_308 & out_womask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4733 = ~out_rimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4734 = ~out_wimask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4735 = ~out_romask_454; // @[RegisterRouter.scala:87:24] wire _out_T_4736 = ~out_womask_454; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_381 = {hi_741, flags_0_go, _out_prepend_T_381}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4737 = out_prepend_381; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4738 = _out_T_4737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_382 = _out_T_4738; // @[RegisterRouter.scala:87:24] wire out_rimask_455 = |_out_rimask_T_455; // @[RegisterRouter.scala:87:24] wire out_wimask_455 = &_out_wimask_T_455; // @[RegisterRouter.scala:87:24] wire out_romask_455 = |_out_romask_T_455; // @[RegisterRouter.scala:87:24] wire out_womask_455 = &_out_womask_T_455; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_455 = out_rivalid_1_309 & out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4740 = out_f_rivalid_455; // @[RegisterRouter.scala:87:24] wire out_f_roready_455 = out_roready_1_309 & out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4741 = out_f_roready_455; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_455 = out_wivalid_1_309 & out_wimask_455; // @[RegisterRouter.scala:87:24] wire out_f_woready_455 = out_woready_1_309 & out_womask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4742 = ~out_rimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4743 = ~out_wimask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4744 = ~out_romask_455; // @[RegisterRouter.scala:87:24] wire _out_T_4745 = ~out_womask_455; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_382 = {hi_742, flags_0_go, _out_prepend_T_382}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4746 = out_prepend_382; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4747 = _out_T_4746; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_383 = _out_T_4747; // @[RegisterRouter.scala:87:24] wire out_rimask_456 = |_out_rimask_T_456; // @[RegisterRouter.scala:87:24] wire out_wimask_456 = &_out_wimask_T_456; // @[RegisterRouter.scala:87:24] wire out_romask_456 = |_out_romask_T_456; // @[RegisterRouter.scala:87:24] wire out_womask_456 = &_out_womask_T_456; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_456 = out_rivalid_1_310 & out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4749 = out_f_rivalid_456; // @[RegisterRouter.scala:87:24] wire out_f_roready_456 = out_roready_1_310 & out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4750 = out_f_roready_456; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_456 = out_wivalid_1_310 & out_wimask_456; // @[RegisterRouter.scala:87:24] wire out_f_woready_456 = out_woready_1_310 & out_womask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4751 = ~out_rimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4752 = ~out_wimask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4753 = ~out_romask_456; // @[RegisterRouter.scala:87:24] wire _out_T_4754 = ~out_womask_456; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_383 = {hi_743, flags_0_go, _out_prepend_T_383}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4755 = out_prepend_383; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4756 = _out_T_4755; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_384 = _out_T_4756; // @[RegisterRouter.scala:87:24] wire out_rimask_457 = |_out_rimask_T_457; // @[RegisterRouter.scala:87:24] wire out_wimask_457 = &_out_wimask_T_457; // @[RegisterRouter.scala:87:24] wire out_romask_457 = |_out_romask_T_457; // @[RegisterRouter.scala:87:24] wire out_womask_457 = &_out_womask_T_457; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_457 = out_rivalid_1_311 & out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4758 = out_f_rivalid_457; // @[RegisterRouter.scala:87:24] wire out_f_roready_457 = out_roready_1_311 & out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4759 = out_f_roready_457; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_457 = out_wivalid_1_311 & out_wimask_457; // @[RegisterRouter.scala:87:24] wire out_f_woready_457 = out_woready_1_311 & out_womask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4760 = ~out_rimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4761 = ~out_wimask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4762 = ~out_romask_457; // @[RegisterRouter.scala:87:24] wire _out_T_4763 = ~out_womask_457; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_384 = {hi_744, flags_0_go, _out_prepend_T_384}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4764 = out_prepend_384; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4765 = _out_T_4764; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_220 = _out_T_4765; // @[MuxLiteral.scala:49:48] wire out_rimask_458 = |_out_rimask_T_458; // @[RegisterRouter.scala:87:24] wire out_wimask_458 = &_out_wimask_T_458; // @[RegisterRouter.scala:87:24] wire out_romask_458 = |_out_romask_T_458; // @[RegisterRouter.scala:87:24] wire out_womask_458 = &_out_womask_T_458; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_458 = out_rivalid_1_312 & out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4767 = out_f_rivalid_458; // @[RegisterRouter.scala:87:24] wire out_f_roready_458 = out_roready_1_312 & out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4768 = out_f_roready_458; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_458 = out_wivalid_1_312 & out_wimask_458; // @[RegisterRouter.scala:87:24] wire out_f_woready_458 = out_woready_1_312 & out_womask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4769 = ~out_rimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4770 = ~out_wimask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4771 = ~out_romask_458; // @[RegisterRouter.scala:87:24] wire _out_T_4772 = ~out_womask_458; // @[RegisterRouter.scala:87:24] wire out_rimask_459 = |_out_rimask_T_459; // @[RegisterRouter.scala:87:24] wire out_wimask_459 = &_out_wimask_T_459; // @[RegisterRouter.scala:87:24] wire out_romask_459 = |_out_romask_T_459; // @[RegisterRouter.scala:87:24] wire out_womask_459 = &_out_womask_T_459; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_459 = out_rivalid_1_313 & out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4776 = out_f_rivalid_459; // @[RegisterRouter.scala:87:24] wire out_f_roready_459 = out_roready_1_313 & out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4777 = out_f_roready_459; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_459 = out_wivalid_1_313 & out_wimask_459; // @[RegisterRouter.scala:87:24] wire out_f_woready_459 = out_woready_1_313 & out_womask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4778 = ~out_rimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4779 = ~out_wimask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4780 = ~out_romask_459; // @[RegisterRouter.scala:87:24] wire _out_T_4781 = ~out_womask_459; // @[RegisterRouter.scala:87:24] wire out_rimask_460 = |_out_rimask_T_460; // @[RegisterRouter.scala:87:24] wire out_wimask_460 = &_out_wimask_T_460; // @[RegisterRouter.scala:87:24] wire out_romask_460 = |_out_romask_T_460; // @[RegisterRouter.scala:87:24] wire out_womask_460 = &_out_womask_T_460; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_460 = out_rivalid_1_314 & out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4785 = out_f_rivalid_460; // @[RegisterRouter.scala:87:24] wire out_f_roready_460 = out_roready_1_314 & out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4786 = out_f_roready_460; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_460 = out_wivalid_1_314 & out_wimask_460; // @[RegisterRouter.scala:87:24] wire out_f_woready_460 = out_woready_1_314 & out_womask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4787 = ~out_rimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4788 = ~out_wimask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4789 = ~out_romask_460; // @[RegisterRouter.scala:87:24] wire _out_T_4790 = ~out_womask_460; // @[RegisterRouter.scala:87:24] wire out_rimask_461 = |_out_rimask_T_461; // @[RegisterRouter.scala:87:24] wire out_wimask_461 = &_out_wimask_T_461; // @[RegisterRouter.scala:87:24] wire out_romask_461 = |_out_romask_T_461; // @[RegisterRouter.scala:87:24] wire out_womask_461 = &_out_womask_T_461; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_461 = out_rivalid_1_315 & out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4794 = out_f_rivalid_461; // @[RegisterRouter.scala:87:24] wire out_f_roready_461 = out_roready_1_315 & out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4795 = out_f_roready_461; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_461 = out_wivalid_1_315 & out_wimask_461; // @[RegisterRouter.scala:87:24] wire out_f_woready_461 = out_woready_1_315 & out_womask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4796 = ~out_rimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4797 = ~out_wimask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4798 = ~out_romask_461; // @[RegisterRouter.scala:87:24] wire _out_T_4799 = ~out_womask_461; // @[RegisterRouter.scala:87:24] wire out_rimask_462 = |_out_rimask_T_462; // @[RegisterRouter.scala:87:24] wire out_wimask_462 = &_out_wimask_T_462; // @[RegisterRouter.scala:87:24] wire out_romask_462 = |_out_romask_T_462; // @[RegisterRouter.scala:87:24] wire out_womask_462 = &_out_womask_T_462; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_462 = out_rivalid_1_316 & out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4803 = out_f_rivalid_462; // @[RegisterRouter.scala:87:24] wire out_f_roready_462 = out_roready_1_316 & out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4804 = out_f_roready_462; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_462 = out_wivalid_1_316 & out_wimask_462; // @[RegisterRouter.scala:87:24] wire out_f_woready_462 = out_woready_1_316 & out_womask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4805 = ~out_rimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4806 = ~out_wimask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4807 = ~out_romask_462; // @[RegisterRouter.scala:87:24] wire _out_T_4808 = ~out_womask_462; // @[RegisterRouter.scala:87:24] wire out_rimask_463 = |_out_rimask_T_463; // @[RegisterRouter.scala:87:24] wire out_wimask_463 = &_out_wimask_T_463; // @[RegisterRouter.scala:87:24] wire out_romask_463 = |_out_romask_T_463; // @[RegisterRouter.scala:87:24] wire out_womask_463 = &_out_womask_T_463; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_463 = out_rivalid_1_317 & out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4812 = out_f_rivalid_463; // @[RegisterRouter.scala:87:24] wire out_f_roready_463 = out_roready_1_317 & out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4813 = out_f_roready_463; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_463 = out_wivalid_1_317 & out_wimask_463; // @[RegisterRouter.scala:87:24] wire out_f_woready_463 = out_woready_1_317 & out_womask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4814 = ~out_rimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4815 = ~out_wimask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4816 = ~out_romask_463; // @[RegisterRouter.scala:87:24] wire _out_T_4817 = ~out_womask_463; // @[RegisterRouter.scala:87:24] wire out_rimask_464 = |_out_rimask_T_464; // @[RegisterRouter.scala:87:24] wire out_wimask_464 = &_out_wimask_T_464; // @[RegisterRouter.scala:87:24] wire out_romask_464 = |_out_romask_T_464; // @[RegisterRouter.scala:87:24] wire out_womask_464 = &_out_womask_T_464; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_464 = out_rivalid_1_318 & out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4821 = out_f_rivalid_464; // @[RegisterRouter.scala:87:24] wire out_f_roready_464 = out_roready_1_318 & out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4822 = out_f_roready_464; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_464 = out_wivalid_1_318 & out_wimask_464; // @[RegisterRouter.scala:87:24] wire out_f_woready_464 = out_woready_1_318 & out_womask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4823 = ~out_rimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4824 = ~out_wimask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4825 = ~out_romask_464; // @[RegisterRouter.scala:87:24] wire _out_T_4826 = ~out_womask_464; // @[RegisterRouter.scala:87:24] wire out_rimask_465 = |_out_rimask_T_465; // @[RegisterRouter.scala:87:24] wire out_wimask_465 = &_out_wimask_T_465; // @[RegisterRouter.scala:87:24] wire out_romask_465 = |_out_romask_T_465; // @[RegisterRouter.scala:87:24] wire out_womask_465 = &_out_womask_T_465; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_465 = out_rivalid_1_319 & out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4830 = out_f_rivalid_465; // @[RegisterRouter.scala:87:24] wire out_f_roready_465 = out_roready_1_319 & out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4831 = out_f_roready_465; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_465 = out_wivalid_1_319 & out_wimask_465; // @[RegisterRouter.scala:87:24] wire out_f_woready_465 = out_woready_1_319 & out_womask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4832 = ~out_rimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4833 = ~out_wimask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4834 = ~out_romask_465; // @[RegisterRouter.scala:87:24] wire _out_T_4835 = ~out_womask_465; // @[RegisterRouter.scala:87:24] wire out_rimask_466 = |_out_rimask_T_466; // @[RegisterRouter.scala:87:24] wire out_wimask_466 = &_out_wimask_T_466; // @[RegisterRouter.scala:87:24] wire out_romask_466 = |_out_romask_T_466; // @[RegisterRouter.scala:87:24] wire out_womask_466 = &_out_womask_T_466; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_466 = out_rivalid_1_320 & out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4839 = out_f_rivalid_466; // @[RegisterRouter.scala:87:24] wire out_f_roready_466 = out_roready_1_320 & out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4840 = out_f_roready_466; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_466 = out_wivalid_1_320 & out_wimask_466; // @[RegisterRouter.scala:87:24] wire out_f_woready_466 = out_woready_1_320 & out_womask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4841 = ~out_rimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4842 = ~out_wimask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4843 = ~out_romask_466; // @[RegisterRouter.scala:87:24] wire _out_T_4844 = ~out_womask_466; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4846 = _out_T_4845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_392 = _out_T_4846; // @[RegisterRouter.scala:87:24] wire out_rimask_467 = |_out_rimask_T_467; // @[RegisterRouter.scala:87:24] wire out_wimask_467 = &_out_wimask_T_467; // @[RegisterRouter.scala:87:24] wire out_romask_467 = |_out_romask_T_467; // @[RegisterRouter.scala:87:24] wire out_womask_467 = &_out_womask_T_467; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_467 = out_rivalid_1_321 & out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4848 = out_f_rivalid_467; // @[RegisterRouter.scala:87:24] wire out_f_roready_467 = out_roready_1_321 & out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4849 = out_f_roready_467; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_467 = out_wivalid_1_321 & out_wimask_467; // @[RegisterRouter.scala:87:24] wire out_f_woready_467 = out_woready_1_321 & out_womask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4850 = ~out_rimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4851 = ~out_wimask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4852 = ~out_romask_467; // @[RegisterRouter.scala:87:24] wire _out_T_4853 = ~out_womask_467; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_392 = {hi_258, flags_0_go, _out_prepend_T_392}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4854 = out_prepend_392; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4855 = _out_T_4854; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_393 = _out_T_4855; // @[RegisterRouter.scala:87:24] wire out_rimask_468 = |_out_rimask_T_468; // @[RegisterRouter.scala:87:24] wire out_wimask_468 = &_out_wimask_T_468; // @[RegisterRouter.scala:87:24] wire out_romask_468 = |_out_romask_T_468; // @[RegisterRouter.scala:87:24] wire out_womask_468 = &_out_womask_T_468; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_468 = out_rivalid_1_322 & out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4857 = out_f_rivalid_468; // @[RegisterRouter.scala:87:24] wire out_f_roready_468 = out_roready_1_322 & out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4858 = out_f_roready_468; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_468 = out_wivalid_1_322 & out_wimask_468; // @[RegisterRouter.scala:87:24] wire out_f_woready_468 = out_woready_1_322 & out_womask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4859 = ~out_rimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4860 = ~out_wimask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4861 = ~out_romask_468; // @[RegisterRouter.scala:87:24] wire _out_T_4862 = ~out_womask_468; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_393 = {hi_259, flags_0_go, _out_prepend_T_393}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4863 = out_prepend_393; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4864 = _out_T_4863; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_394 = _out_T_4864; // @[RegisterRouter.scala:87:24] wire out_rimask_469 = |_out_rimask_T_469; // @[RegisterRouter.scala:87:24] wire out_wimask_469 = &_out_wimask_T_469; // @[RegisterRouter.scala:87:24] wire out_romask_469 = |_out_romask_T_469; // @[RegisterRouter.scala:87:24] wire out_womask_469 = &_out_womask_T_469; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_469 = out_rivalid_1_323 & out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4866 = out_f_rivalid_469; // @[RegisterRouter.scala:87:24] wire out_f_roready_469 = out_roready_1_323 & out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4867 = out_f_roready_469; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_469 = out_wivalid_1_323 & out_wimask_469; // @[RegisterRouter.scala:87:24] wire out_f_woready_469 = out_woready_1_323 & out_womask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4868 = ~out_rimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4869 = ~out_wimask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4870 = ~out_romask_469; // @[RegisterRouter.scala:87:24] wire _out_T_4871 = ~out_womask_469; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_394 = {hi_260, flags_0_go, _out_prepend_T_394}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4872 = out_prepend_394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4873 = _out_T_4872; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_395 = _out_T_4873; // @[RegisterRouter.scala:87:24] wire out_rimask_470 = |_out_rimask_T_470; // @[RegisterRouter.scala:87:24] wire out_wimask_470 = &_out_wimask_T_470; // @[RegisterRouter.scala:87:24] wire out_romask_470 = |_out_romask_T_470; // @[RegisterRouter.scala:87:24] wire out_womask_470 = &_out_womask_T_470; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_470 = out_rivalid_1_324 & out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4875 = out_f_rivalid_470; // @[RegisterRouter.scala:87:24] wire out_f_roready_470 = out_roready_1_324 & out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4876 = out_f_roready_470; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_470 = out_wivalid_1_324 & out_wimask_470; // @[RegisterRouter.scala:87:24] wire out_f_woready_470 = out_woready_1_324 & out_womask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4877 = ~out_rimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4878 = ~out_wimask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4879 = ~out_romask_470; // @[RegisterRouter.scala:87:24] wire _out_T_4880 = ~out_womask_470; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_395 = {hi_261, flags_0_go, _out_prepend_T_395}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4881 = out_prepend_395; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4882 = _out_T_4881; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_396 = _out_T_4882; // @[RegisterRouter.scala:87:24] wire out_rimask_471 = |_out_rimask_T_471; // @[RegisterRouter.scala:87:24] wire out_wimask_471 = &_out_wimask_T_471; // @[RegisterRouter.scala:87:24] wire out_romask_471 = |_out_romask_T_471; // @[RegisterRouter.scala:87:24] wire out_womask_471 = &_out_womask_T_471; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_471 = out_rivalid_1_325 & out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4884 = out_f_rivalid_471; // @[RegisterRouter.scala:87:24] wire out_f_roready_471 = out_roready_1_325 & out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4885 = out_f_roready_471; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_471 = out_wivalid_1_325 & out_wimask_471; // @[RegisterRouter.scala:87:24] wire out_f_woready_471 = out_woready_1_325 & out_womask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4886 = ~out_rimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4887 = ~out_wimask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4888 = ~out_romask_471; // @[RegisterRouter.scala:87:24] wire _out_T_4889 = ~out_womask_471; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_396 = {hi_262, flags_0_go, _out_prepend_T_396}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4890 = out_prepend_396; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4891 = _out_T_4890; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_397 = _out_T_4891; // @[RegisterRouter.scala:87:24] wire out_rimask_472 = |_out_rimask_T_472; // @[RegisterRouter.scala:87:24] wire out_wimask_472 = &_out_wimask_T_472; // @[RegisterRouter.scala:87:24] wire out_romask_472 = |_out_romask_T_472; // @[RegisterRouter.scala:87:24] wire out_womask_472 = &_out_womask_T_472; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_472 = out_rivalid_1_326 & out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4893 = out_f_rivalid_472; // @[RegisterRouter.scala:87:24] wire out_f_roready_472 = out_roready_1_326 & out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4894 = out_f_roready_472; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_472 = out_wivalid_1_326 & out_wimask_472; // @[RegisterRouter.scala:87:24] wire out_f_woready_472 = out_woready_1_326 & out_womask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4895 = ~out_rimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4896 = ~out_wimask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4897 = ~out_romask_472; // @[RegisterRouter.scala:87:24] wire _out_T_4898 = ~out_womask_472; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_397 = {hi_263, flags_0_go, _out_prepend_T_397}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4899 = out_prepend_397; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4900 = _out_T_4899; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_398 = _out_T_4900; // @[RegisterRouter.scala:87:24] wire out_rimask_473 = |_out_rimask_T_473; // @[RegisterRouter.scala:87:24] wire out_wimask_473 = &_out_wimask_T_473; // @[RegisterRouter.scala:87:24] wire out_romask_473 = |_out_romask_T_473; // @[RegisterRouter.scala:87:24] wire out_womask_473 = &_out_womask_T_473; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_473 = out_rivalid_1_327 & out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4902 = out_f_rivalid_473; // @[RegisterRouter.scala:87:24] wire out_f_roready_473 = out_roready_1_327 & out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4903 = out_f_roready_473; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_473 = out_wivalid_1_327 & out_wimask_473; // @[RegisterRouter.scala:87:24] wire out_f_woready_473 = out_woready_1_327 & out_womask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4904 = ~out_rimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4905 = ~out_wimask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4906 = ~out_romask_473; // @[RegisterRouter.scala:87:24] wire _out_T_4907 = ~out_womask_473; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_398 = {hi_264, flags_0_go, _out_prepend_T_398}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4908 = out_prepend_398; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4909 = _out_T_4908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_160 = _out_T_4909; // @[MuxLiteral.scala:49:48] wire out_rimask_474 = |_out_rimask_T_474; // @[RegisterRouter.scala:87:24] wire out_wimask_474 = &_out_wimask_T_474; // @[RegisterRouter.scala:87:24] wire out_romask_474 = |_out_romask_T_474; // @[RegisterRouter.scala:87:24] wire out_womask_474 = &_out_womask_T_474; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_474 = out_rivalid_1_328 & out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4911 = out_f_rivalid_474; // @[RegisterRouter.scala:87:24] wire out_f_roready_474 = out_roready_1_328 & out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4912 = out_f_roready_474; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_474 = out_wivalid_1_328 & out_wimask_474; // @[RegisterRouter.scala:87:24] wire out_f_woready_474 = out_woready_1_328 & out_womask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4913 = ~out_rimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4914 = ~out_wimask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4915 = ~out_romask_474; // @[RegisterRouter.scala:87:24] wire _out_T_4916 = ~out_womask_474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4918 = _out_T_4917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_399 = _out_T_4918; // @[RegisterRouter.scala:87:24] wire out_rimask_475 = |_out_rimask_T_475; // @[RegisterRouter.scala:87:24] wire out_wimask_475 = &_out_wimask_T_475; // @[RegisterRouter.scala:87:24] wire out_romask_475 = |_out_romask_T_475; // @[RegisterRouter.scala:87:24] wire out_womask_475 = &_out_womask_T_475; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_475 = out_rivalid_1_329 & out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4920 = out_f_rivalid_475; // @[RegisterRouter.scala:87:24] wire out_f_roready_475 = out_roready_1_329 & out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4921 = out_f_roready_475; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_475 = out_wivalid_1_329 & out_wimask_475; // @[RegisterRouter.scala:87:24] wire out_f_woready_475 = out_woready_1_329 & out_womask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4922 = ~out_rimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4923 = ~out_wimask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4924 = ~out_romask_475; // @[RegisterRouter.scala:87:24] wire _out_T_4925 = ~out_womask_475; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_399 = {hi_514, flags_0_go, _out_prepend_T_399}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4926 = out_prepend_399; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4927 = _out_T_4926; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_400 = _out_T_4927; // @[RegisterRouter.scala:87:24] wire out_rimask_476 = |_out_rimask_T_476; // @[RegisterRouter.scala:87:24] wire out_wimask_476 = &_out_wimask_T_476; // @[RegisterRouter.scala:87:24] wire out_romask_476 = |_out_romask_T_476; // @[RegisterRouter.scala:87:24] wire out_womask_476 = &_out_womask_T_476; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_476 = out_rivalid_1_330 & out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4929 = out_f_rivalid_476; // @[RegisterRouter.scala:87:24] wire out_f_roready_476 = out_roready_1_330 & out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4930 = out_f_roready_476; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_476 = out_wivalid_1_330 & out_wimask_476; // @[RegisterRouter.scala:87:24] wire out_f_woready_476 = out_woready_1_330 & out_womask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4931 = ~out_rimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4932 = ~out_wimask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4933 = ~out_romask_476; // @[RegisterRouter.scala:87:24] wire _out_T_4934 = ~out_womask_476; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_400 = {hi_515, flags_0_go, _out_prepend_T_400}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4935 = out_prepend_400; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_4936 = _out_T_4935; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_401 = _out_T_4936; // @[RegisterRouter.scala:87:24] wire out_rimask_477 = |_out_rimask_T_477; // @[RegisterRouter.scala:87:24] wire out_wimask_477 = &_out_wimask_T_477; // @[RegisterRouter.scala:87:24] wire out_romask_477 = |_out_romask_T_477; // @[RegisterRouter.scala:87:24] wire out_womask_477 = &_out_womask_T_477; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_477 = out_rivalid_1_331 & out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4938 = out_f_rivalid_477; // @[RegisterRouter.scala:87:24] wire out_f_roready_477 = out_roready_1_331 & out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4939 = out_f_roready_477; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_477 = out_wivalid_1_331 & out_wimask_477; // @[RegisterRouter.scala:87:24] wire out_f_woready_477 = out_woready_1_331 & out_womask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4940 = ~out_rimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4941 = ~out_wimask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4942 = ~out_romask_477; // @[RegisterRouter.scala:87:24] wire _out_T_4943 = ~out_womask_477; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_401 = {hi_516, flags_0_go, _out_prepend_T_401}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4944 = out_prepend_401; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_4945 = _out_T_4944; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_402 = _out_T_4945; // @[RegisterRouter.scala:87:24] wire out_rimask_478 = |_out_rimask_T_478; // @[RegisterRouter.scala:87:24] wire out_wimask_478 = &_out_wimask_T_478; // @[RegisterRouter.scala:87:24] wire out_romask_478 = |_out_romask_T_478; // @[RegisterRouter.scala:87:24] wire out_womask_478 = &_out_womask_T_478; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_478 = out_rivalid_1_332 & out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4947 = out_f_rivalid_478; // @[RegisterRouter.scala:87:24] wire out_f_roready_478 = out_roready_1_332 & out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4948 = out_f_roready_478; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_478 = out_wivalid_1_332 & out_wimask_478; // @[RegisterRouter.scala:87:24] wire out_f_woready_478 = out_woready_1_332 & out_womask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4949 = ~out_rimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4950 = ~out_wimask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4951 = ~out_romask_478; // @[RegisterRouter.scala:87:24] wire _out_T_4952 = ~out_womask_478; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_402 = {hi_517, flags_0_go, _out_prepend_T_402}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4953 = out_prepend_402; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_4954 = _out_T_4953; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_403 = _out_T_4954; // @[RegisterRouter.scala:87:24] wire out_rimask_479 = |_out_rimask_T_479; // @[RegisterRouter.scala:87:24] wire out_wimask_479 = &_out_wimask_T_479; // @[RegisterRouter.scala:87:24] wire out_romask_479 = |_out_romask_T_479; // @[RegisterRouter.scala:87:24] wire out_womask_479 = &_out_womask_T_479; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_479 = out_rivalid_1_333 & out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4956 = out_f_rivalid_479; // @[RegisterRouter.scala:87:24] wire out_f_roready_479 = out_roready_1_333 & out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4957 = out_f_roready_479; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_479 = out_wivalid_1_333 & out_wimask_479; // @[RegisterRouter.scala:87:24] wire out_f_woready_479 = out_woready_1_333 & out_womask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4958 = ~out_rimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4959 = ~out_wimask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4960 = ~out_romask_479; // @[RegisterRouter.scala:87:24] wire _out_T_4961 = ~out_womask_479; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_403 = {hi_518, flags_0_go, _out_prepend_T_403}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4962 = out_prepend_403; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_4963 = _out_T_4962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_404 = _out_T_4963; // @[RegisterRouter.scala:87:24] wire out_rimask_480 = |_out_rimask_T_480; // @[RegisterRouter.scala:87:24] wire out_wimask_480 = &_out_wimask_T_480; // @[RegisterRouter.scala:87:24] wire out_romask_480 = |_out_romask_T_480; // @[RegisterRouter.scala:87:24] wire out_womask_480 = &_out_womask_T_480; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_480 = out_rivalid_1_334 & out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4965 = out_f_rivalid_480; // @[RegisterRouter.scala:87:24] wire out_f_roready_480 = out_roready_1_334 & out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4966 = out_f_roready_480; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_480 = out_wivalid_1_334 & out_wimask_480; // @[RegisterRouter.scala:87:24] wire out_f_woready_480 = out_woready_1_334 & out_womask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4967 = ~out_rimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4968 = ~out_wimask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4969 = ~out_romask_480; // @[RegisterRouter.scala:87:24] wire _out_T_4970 = ~out_womask_480; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_404 = {hi_519, flags_0_go, _out_prepend_T_404}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4971 = out_prepend_404; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_4972 = _out_T_4971; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_405 = _out_T_4972; // @[RegisterRouter.scala:87:24] wire out_rimask_481 = |_out_rimask_T_481; // @[RegisterRouter.scala:87:24] wire out_wimask_481 = &_out_wimask_T_481; // @[RegisterRouter.scala:87:24] wire out_romask_481 = |_out_romask_T_481; // @[RegisterRouter.scala:87:24] wire out_womask_481 = &_out_womask_T_481; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_481 = out_rivalid_1_335 & out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4974 = out_f_rivalid_481; // @[RegisterRouter.scala:87:24] wire out_f_roready_481 = out_roready_1_335 & out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4975 = out_f_roready_481; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_481 = out_wivalid_1_335 & out_wimask_481; // @[RegisterRouter.scala:87:24] wire out_f_woready_481 = out_woready_1_335 & out_womask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4976 = ~out_rimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4977 = ~out_wimask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4978 = ~out_romask_481; // @[RegisterRouter.scala:87:24] wire _out_T_4979 = ~out_womask_481; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_405 = {hi_520, flags_0_go, _out_prepend_T_405}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4980 = out_prepend_405; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_4981 = _out_T_4980; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_192 = _out_T_4981; // @[MuxLiteral.scala:49:48] wire out_rimask_482 = |_out_rimask_T_482; // @[RegisterRouter.scala:87:24] wire out_wimask_482 = &_out_wimask_T_482; // @[RegisterRouter.scala:87:24] wire out_romask_482 = |_out_romask_T_482; // @[RegisterRouter.scala:87:24] wire out_womask_482 = &_out_womask_T_482; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_482 = out_rivalid_1_336 & out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4983 = out_f_rivalid_482; // @[RegisterRouter.scala:87:24] wire out_f_roready_482 = out_roready_1_336 & out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4984 = out_f_roready_482; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_482 = out_wivalid_1_336 & out_wimask_482; // @[RegisterRouter.scala:87:24] wire out_f_woready_482 = out_woready_1_336 & out_womask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4985 = ~out_rimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4986 = ~out_wimask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4987 = ~out_romask_482; // @[RegisterRouter.scala:87:24] wire _out_T_4988 = ~out_womask_482; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_4990 = _out_T_4989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_406 = _out_T_4990; // @[RegisterRouter.scala:87:24] wire out_rimask_483 = |_out_rimask_T_483; // @[RegisterRouter.scala:87:24] wire out_wimask_483 = &_out_wimask_T_483; // @[RegisterRouter.scala:87:24] wire out_romask_483 = |_out_romask_T_483; // @[RegisterRouter.scala:87:24] wire out_womask_483 = &_out_womask_T_483; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_483 = out_rivalid_1_337 & out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4992 = out_f_rivalid_483; // @[RegisterRouter.scala:87:24] wire out_f_roready_483 = out_roready_1_337 & out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4993 = out_f_roready_483; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_483 = out_wivalid_1_337 & out_wimask_483; // @[RegisterRouter.scala:87:24] wire out_f_woready_483 = out_woready_1_337 & out_womask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4994 = ~out_rimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4995 = ~out_wimask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4996 = ~out_romask_483; // @[RegisterRouter.scala:87:24] wire _out_T_4997 = ~out_womask_483; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_406 = {hi_74, flags_0_go, _out_prepend_T_406}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4998 = out_prepend_406; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_4999 = _out_T_4998; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_407 = _out_T_4999; // @[RegisterRouter.scala:87:24] wire out_rimask_484 = |_out_rimask_T_484; // @[RegisterRouter.scala:87:24] wire out_wimask_484 = &_out_wimask_T_484; // @[RegisterRouter.scala:87:24] wire out_romask_484 = |_out_romask_T_484; // @[RegisterRouter.scala:87:24] wire out_womask_484 = &_out_womask_T_484; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_484 = out_rivalid_1_338 & out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5001 = out_f_rivalid_484; // @[RegisterRouter.scala:87:24] wire out_f_roready_484 = out_roready_1_338 & out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5002 = out_f_roready_484; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_484 = out_wivalid_1_338 & out_wimask_484; // @[RegisterRouter.scala:87:24] wire out_f_woready_484 = out_woready_1_338 & out_womask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5003 = ~out_rimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5004 = ~out_wimask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5005 = ~out_romask_484; // @[RegisterRouter.scala:87:24] wire _out_T_5006 = ~out_womask_484; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_407 = {hi_75, flags_0_go, _out_prepend_T_407}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5007 = out_prepend_407; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5008 = _out_T_5007; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_408 = _out_T_5008; // @[RegisterRouter.scala:87:24] wire out_rimask_485 = |_out_rimask_T_485; // @[RegisterRouter.scala:87:24] wire out_wimask_485 = &_out_wimask_T_485; // @[RegisterRouter.scala:87:24] wire out_romask_485 = |_out_romask_T_485; // @[RegisterRouter.scala:87:24] wire out_womask_485 = &_out_womask_T_485; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_485 = out_rivalid_1_339 & out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5010 = out_f_rivalid_485; // @[RegisterRouter.scala:87:24] wire out_f_roready_485 = out_roready_1_339 & out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5011 = out_f_roready_485; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_485 = out_wivalid_1_339 & out_wimask_485; // @[RegisterRouter.scala:87:24] wire out_f_woready_485 = out_woready_1_339 & out_womask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5012 = ~out_rimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5013 = ~out_wimask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5014 = ~out_romask_485; // @[RegisterRouter.scala:87:24] wire _out_T_5015 = ~out_womask_485; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_408 = {hi_76, flags_0_go, _out_prepend_T_408}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5016 = out_prepend_408; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5017 = _out_T_5016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_409 = _out_T_5017; // @[RegisterRouter.scala:87:24] wire out_rimask_486 = |_out_rimask_T_486; // @[RegisterRouter.scala:87:24] wire out_wimask_486 = &_out_wimask_T_486; // @[RegisterRouter.scala:87:24] wire out_romask_486 = |_out_romask_T_486; // @[RegisterRouter.scala:87:24] wire out_womask_486 = &_out_womask_T_486; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_486 = out_rivalid_1_340 & out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5019 = out_f_rivalid_486; // @[RegisterRouter.scala:87:24] wire out_f_roready_486 = out_roready_1_340 & out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5020 = out_f_roready_486; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_486 = out_wivalid_1_340 & out_wimask_486; // @[RegisterRouter.scala:87:24] wire out_f_woready_486 = out_woready_1_340 & out_womask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5021 = ~out_rimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5022 = ~out_wimask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5023 = ~out_romask_486; // @[RegisterRouter.scala:87:24] wire _out_T_5024 = ~out_womask_486; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_409 = {hi_77, flags_0_go, _out_prepend_T_409}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5025 = out_prepend_409; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5026 = _out_T_5025; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_410 = _out_T_5026; // @[RegisterRouter.scala:87:24] wire out_rimask_487 = |_out_rimask_T_487; // @[RegisterRouter.scala:87:24] wire out_wimask_487 = &_out_wimask_T_487; // @[RegisterRouter.scala:87:24] wire out_romask_487 = |_out_romask_T_487; // @[RegisterRouter.scala:87:24] wire out_womask_487 = &_out_womask_T_487; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_487 = out_rivalid_1_341 & out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5028 = out_f_rivalid_487; // @[RegisterRouter.scala:87:24] wire out_f_roready_487 = out_roready_1_341 & out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5029 = out_f_roready_487; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_487 = out_wivalid_1_341 & out_wimask_487; // @[RegisterRouter.scala:87:24] wire out_f_woready_487 = out_woready_1_341 & out_womask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5030 = ~out_rimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5031 = ~out_wimask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5032 = ~out_romask_487; // @[RegisterRouter.scala:87:24] wire _out_T_5033 = ~out_womask_487; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_410 = {hi_78, flags_0_go, _out_prepend_T_410}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5034 = out_prepend_410; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5035 = _out_T_5034; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_411 = _out_T_5035; // @[RegisterRouter.scala:87:24] wire out_rimask_488 = |_out_rimask_T_488; // @[RegisterRouter.scala:87:24] wire out_wimask_488 = &_out_wimask_T_488; // @[RegisterRouter.scala:87:24] wire out_romask_488 = |_out_romask_T_488; // @[RegisterRouter.scala:87:24] wire out_womask_488 = &_out_womask_T_488; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_488 = out_rivalid_1_342 & out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5037 = out_f_rivalid_488; // @[RegisterRouter.scala:87:24] wire out_f_roready_488 = out_roready_1_342 & out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5038 = out_f_roready_488; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_488 = out_wivalid_1_342 & out_wimask_488; // @[RegisterRouter.scala:87:24] wire out_f_woready_488 = out_woready_1_342 & out_womask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5039 = ~out_rimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5040 = ~out_wimask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5041 = ~out_romask_488; // @[RegisterRouter.scala:87:24] wire _out_T_5042 = ~out_womask_488; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_411 = {hi_79, flags_0_go, _out_prepend_T_411}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5043 = out_prepend_411; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5044 = _out_T_5043; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_412 = _out_T_5044; // @[RegisterRouter.scala:87:24] wire out_rimask_489 = |_out_rimask_T_489; // @[RegisterRouter.scala:87:24] wire out_wimask_489 = &_out_wimask_T_489; // @[RegisterRouter.scala:87:24] wire out_romask_489 = |_out_romask_T_489; // @[RegisterRouter.scala:87:24] wire out_womask_489 = &_out_womask_T_489; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_489 = out_rivalid_1_343 & out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5046 = out_f_rivalid_489; // @[RegisterRouter.scala:87:24] wire out_f_roready_489 = out_roready_1_343 & out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5047 = out_f_roready_489; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_489 = out_wivalid_1_343 & out_wimask_489; // @[RegisterRouter.scala:87:24] wire out_f_woready_489 = out_woready_1_343 & out_womask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5048 = ~out_rimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5049 = ~out_wimask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5050 = ~out_romask_489; // @[RegisterRouter.scala:87:24] wire _out_T_5051 = ~out_womask_489; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_412 = {hi_80, flags_0_go, _out_prepend_T_412}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5052 = out_prepend_412; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5053 = _out_T_5052; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_137 = _out_T_5053; // @[MuxLiteral.scala:49:48] wire out_rimask_490 = |_out_rimask_T_490; // @[RegisterRouter.scala:87:24] wire out_wimask_490 = &_out_wimask_T_490; // @[RegisterRouter.scala:87:24] wire out_romask_490 = |_out_romask_T_490; // @[RegisterRouter.scala:87:24] wire out_womask_490 = &_out_womask_T_490; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_490 = out_rivalid_1_344 & out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5055 = out_f_rivalid_490; // @[RegisterRouter.scala:87:24] wire out_f_roready_490 = out_roready_1_344 & out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5056 = out_f_roready_490; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_490 = out_wivalid_1_344 & out_wimask_490; // @[RegisterRouter.scala:87:24] wire out_f_woready_490 = out_woready_1_344 & out_womask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5057 = ~out_rimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5058 = ~out_wimask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5059 = ~out_romask_490; // @[RegisterRouter.scala:87:24] wire _out_T_5060 = ~out_womask_490; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5062 = _out_T_5061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_413 = _out_T_5062; // @[RegisterRouter.scala:87:24] wire out_rimask_491 = |_out_rimask_T_491; // @[RegisterRouter.scala:87:24] wire out_wimask_491 = &_out_wimask_T_491; // @[RegisterRouter.scala:87:24] wire out_romask_491 = |_out_romask_T_491; // @[RegisterRouter.scala:87:24] wire out_womask_491 = &_out_womask_T_491; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_491 = out_rivalid_1_345 & out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5064 = out_f_rivalid_491; // @[RegisterRouter.scala:87:24] wire out_f_roready_491 = out_roready_1_345 & out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5065 = out_f_roready_491; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_491 = out_wivalid_1_345 & out_wimask_491; // @[RegisterRouter.scala:87:24] wire out_f_woready_491 = out_woready_1_345 & out_womask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5066 = ~out_rimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5067 = ~out_wimask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5068 = ~out_romask_491; // @[RegisterRouter.scala:87:24] wire _out_T_5069 = ~out_womask_491; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_413 = {hi_298, flags_0_go, _out_prepend_T_413}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5070 = out_prepend_413; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5071 = _out_T_5070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_414 = _out_T_5071; // @[RegisterRouter.scala:87:24] wire out_rimask_492 = |_out_rimask_T_492; // @[RegisterRouter.scala:87:24] wire out_wimask_492 = &_out_wimask_T_492; // @[RegisterRouter.scala:87:24] wire out_romask_492 = |_out_romask_T_492; // @[RegisterRouter.scala:87:24] wire out_womask_492 = &_out_womask_T_492; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_492 = out_rivalid_1_346 & out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5073 = out_f_rivalid_492; // @[RegisterRouter.scala:87:24] wire out_f_roready_492 = out_roready_1_346 & out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5074 = out_f_roready_492; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_492 = out_wivalid_1_346 & out_wimask_492; // @[RegisterRouter.scala:87:24] wire out_f_woready_492 = out_woready_1_346 & out_womask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5075 = ~out_rimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5076 = ~out_wimask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5077 = ~out_romask_492; // @[RegisterRouter.scala:87:24] wire _out_T_5078 = ~out_womask_492; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_414 = {hi_299, flags_0_go, _out_prepend_T_414}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5079 = out_prepend_414; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5080 = _out_T_5079; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_415 = _out_T_5080; // @[RegisterRouter.scala:87:24] wire out_rimask_493 = |_out_rimask_T_493; // @[RegisterRouter.scala:87:24] wire out_wimask_493 = &_out_wimask_T_493; // @[RegisterRouter.scala:87:24] wire out_romask_493 = |_out_romask_T_493; // @[RegisterRouter.scala:87:24] wire out_womask_493 = &_out_womask_T_493; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_493 = out_rivalid_1_347 & out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5082 = out_f_rivalid_493; // @[RegisterRouter.scala:87:24] wire out_f_roready_493 = out_roready_1_347 & out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5083 = out_f_roready_493; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_493 = out_wivalid_1_347 & out_wimask_493; // @[RegisterRouter.scala:87:24] wire out_f_woready_493 = out_woready_1_347 & out_womask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5084 = ~out_rimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5085 = ~out_wimask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5086 = ~out_romask_493; // @[RegisterRouter.scala:87:24] wire _out_T_5087 = ~out_womask_493; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_415 = {hi_300, flags_0_go, _out_prepend_T_415}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5088 = out_prepend_415; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5089 = _out_T_5088; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_416 = _out_T_5089; // @[RegisterRouter.scala:87:24] wire out_rimask_494 = |_out_rimask_T_494; // @[RegisterRouter.scala:87:24] wire out_wimask_494 = &_out_wimask_T_494; // @[RegisterRouter.scala:87:24] wire out_romask_494 = |_out_romask_T_494; // @[RegisterRouter.scala:87:24] wire out_womask_494 = &_out_womask_T_494; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_494 = out_rivalid_1_348 & out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5091 = out_f_rivalid_494; // @[RegisterRouter.scala:87:24] wire out_f_roready_494 = out_roready_1_348 & out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5092 = out_f_roready_494; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_494 = out_wivalid_1_348 & out_wimask_494; // @[RegisterRouter.scala:87:24] wire out_f_woready_494 = out_woready_1_348 & out_womask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5093 = ~out_rimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5094 = ~out_wimask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5095 = ~out_romask_494; // @[RegisterRouter.scala:87:24] wire _out_T_5096 = ~out_womask_494; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_416 = {hi_301, flags_0_go, _out_prepend_T_416}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5097 = out_prepend_416; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5098 = _out_T_5097; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_417 = _out_T_5098; // @[RegisterRouter.scala:87:24] wire out_rimask_495 = |_out_rimask_T_495; // @[RegisterRouter.scala:87:24] wire out_wimask_495 = &_out_wimask_T_495; // @[RegisterRouter.scala:87:24] wire out_romask_495 = |_out_romask_T_495; // @[RegisterRouter.scala:87:24] wire out_womask_495 = &_out_womask_T_495; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_495 = out_rivalid_1_349 & out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5100 = out_f_rivalid_495; // @[RegisterRouter.scala:87:24] wire out_f_roready_495 = out_roready_1_349 & out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5101 = out_f_roready_495; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_495 = out_wivalid_1_349 & out_wimask_495; // @[RegisterRouter.scala:87:24] wire out_f_woready_495 = out_woready_1_349 & out_womask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5102 = ~out_rimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5103 = ~out_wimask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5104 = ~out_romask_495; // @[RegisterRouter.scala:87:24] wire _out_T_5105 = ~out_womask_495; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_417 = {hi_302, flags_0_go, _out_prepend_T_417}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5106 = out_prepend_417; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5107 = _out_T_5106; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_418 = _out_T_5107; // @[RegisterRouter.scala:87:24] wire out_rimask_496 = |_out_rimask_T_496; // @[RegisterRouter.scala:87:24] wire out_wimask_496 = &_out_wimask_T_496; // @[RegisterRouter.scala:87:24] wire out_romask_496 = |_out_romask_T_496; // @[RegisterRouter.scala:87:24] wire out_womask_496 = &_out_womask_T_496; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_496 = out_rivalid_1_350 & out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5109 = out_f_rivalid_496; // @[RegisterRouter.scala:87:24] wire out_f_roready_496 = out_roready_1_350 & out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5110 = out_f_roready_496; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_496 = out_wivalid_1_350 & out_wimask_496; // @[RegisterRouter.scala:87:24] wire out_f_woready_496 = out_woready_1_350 & out_womask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5111 = ~out_rimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5112 = ~out_wimask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5113 = ~out_romask_496; // @[RegisterRouter.scala:87:24] wire _out_T_5114 = ~out_womask_496; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_418 = {hi_303, flags_0_go, _out_prepend_T_418}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5115 = out_prepend_418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5116 = _out_T_5115; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_419 = _out_T_5116; // @[RegisterRouter.scala:87:24] wire out_rimask_497 = |_out_rimask_T_497; // @[RegisterRouter.scala:87:24] wire out_wimask_497 = &_out_wimask_T_497; // @[RegisterRouter.scala:87:24] wire out_romask_497 = |_out_romask_T_497; // @[RegisterRouter.scala:87:24] wire out_womask_497 = &_out_womask_T_497; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_497 = out_rivalid_1_351 & out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5118 = out_f_rivalid_497; // @[RegisterRouter.scala:87:24] wire out_f_roready_497 = out_roready_1_351 & out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5119 = out_f_roready_497; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_497 = out_wivalid_1_351 & out_wimask_497; // @[RegisterRouter.scala:87:24] wire out_f_woready_497 = out_woready_1_351 & out_womask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5120 = ~out_rimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5121 = ~out_wimask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5122 = ~out_romask_497; // @[RegisterRouter.scala:87:24] wire _out_T_5123 = ~out_womask_497; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_419 = {hi_304, flags_0_go, _out_prepend_T_419}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5124 = out_prepend_419; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5125 = _out_T_5124; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_165 = _out_T_5125; // @[MuxLiteral.scala:49:48] wire [9:0] _out_rimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_498 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_681 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_498 = |_out_rimask_T_498; // @[RegisterRouter.scala:87:24] wire out_wimask_498 = &_out_wimask_T_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_498 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_681 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24] wire out_romask_498 = |_out_romask_T_498; // @[RegisterRouter.scala:87:24] wire out_womask_498 = &_out_womask_T_498; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_498 = out_rivalid_1_352 & out_rimask_498; // @[RegisterRouter.scala:87:24] wire out_f_roready_498 = out_roready_1_352 & out_romask_498; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_498 = out_wivalid_1_352 & out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5127 = out_f_wivalid_498; // @[RegisterRouter.scala:87:24] assign out_f_woready_498 = out_woready_1_352 & out_womask_498; // @[RegisterRouter.scala:87:24] assign hartResumingWrEn = out_f_woready_498; // @[RegisterRouter.scala:87:24] wire _out_T_5128 = out_f_woready_498; // @[RegisterRouter.scala:87:24] assign _out_T_5126 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign _out_T_6805 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24] assign hartResumingId = _out_T_5126; // @[RegisterRouter.scala:87:24] wire _out_T_5129 = ~out_rimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5130 = ~out_wimask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5131 = ~out_romask_498; // @[RegisterRouter.scala:87:24] wire _out_T_5132 = ~out_womask_498; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_499 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_rimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_wimask_T_682 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_499 = |_out_rimask_T_499; // @[RegisterRouter.scala:87:24] wire out_wimask_499 = &_out_wimask_T_499; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_499 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_romask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire [9:0] _out_womask_T_682 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24] wire out_romask_499 = |_out_romask_T_499; // @[RegisterRouter.scala:87:24] wire out_womask_499 = &_out_womask_T_499; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_499 = out_rivalid_1_353 & out_rimask_499; // @[RegisterRouter.scala:87:24] wire out_f_roready_499 = out_roready_1_353 & out_romask_499; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_499 = out_wivalid_1_353 & out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5136 = out_f_wivalid_499; // @[RegisterRouter.scala:87:24] assign out_f_woready_499 = out_woready_1_353 & out_womask_499; // @[RegisterRouter.scala:87:24] assign hartExceptionWrEn = out_f_woready_499; // @[RegisterRouter.scala:87:24] wire _out_T_5137 = out_f_woready_499; // @[RegisterRouter.scala:87:24] assign _out_T_5135 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign _out_T_6814 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24] assign hartExceptionId = _out_T_5135; // @[RegisterRouter.scala:87:24] wire _out_T_5138 = ~out_rimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5139 = ~out_wimask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5140 = ~out_romask_499; // @[RegisterRouter.scala:87:24] wire _out_T_5141 = ~out_womask_499; // @[RegisterRouter.scala:87:24] wire out_rimask_500 = |_out_rimask_T_500; // @[RegisterRouter.scala:87:24] wire out_wimask_500 = &_out_wimask_T_500; // @[RegisterRouter.scala:87:24] wire out_romask_500 = |_out_romask_T_500; // @[RegisterRouter.scala:87:24] wire out_womask_500 = &_out_womask_T_500; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_500 = out_rivalid_1_354 & out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5145 = out_f_rivalid_500; // @[RegisterRouter.scala:87:24] wire out_f_roready_500 = out_roready_1_354 & out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5146 = out_f_roready_500; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_500 = out_wivalid_1_354 & out_wimask_500; // @[RegisterRouter.scala:87:24] wire out_f_woready_500 = out_woready_1_354 & out_womask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5147 = ~out_rimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5148 = ~out_wimask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5149 = ~out_romask_500; // @[RegisterRouter.scala:87:24] wire _out_T_5150 = ~out_womask_500; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5152 = _out_T_5151; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_421 = _out_T_5152; // @[RegisterRouter.scala:87:24] wire out_rimask_501 = |_out_rimask_T_501; // @[RegisterRouter.scala:87:24] wire out_wimask_501 = &_out_wimask_T_501; // @[RegisterRouter.scala:87:24] wire out_romask_501 = |_out_romask_T_501; // @[RegisterRouter.scala:87:24] wire out_womask_501 = &_out_womask_T_501; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_501 = out_rivalid_1_355 & out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5154 = out_f_rivalid_501; // @[RegisterRouter.scala:87:24] wire out_f_roready_501 = out_roready_1_355 & out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5155 = out_f_roready_501; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_501 = out_wivalid_1_355 & out_wimask_501; // @[RegisterRouter.scala:87:24] wire out_f_woready_501 = out_woready_1_355 & out_womask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5156 = ~out_rimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5157 = ~out_wimask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5158 = ~out_romask_501; // @[RegisterRouter.scala:87:24] wire _out_T_5159 = ~out_womask_501; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_421 = {hi_810, flags_0_go, _out_prepend_T_421}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5160 = out_prepend_421; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5161 = _out_T_5160; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_422 = _out_T_5161; // @[RegisterRouter.scala:87:24] wire out_rimask_502 = |_out_rimask_T_502; // @[RegisterRouter.scala:87:24] wire out_wimask_502 = &_out_wimask_T_502; // @[RegisterRouter.scala:87:24] wire out_romask_502 = |_out_romask_T_502; // @[RegisterRouter.scala:87:24] wire out_womask_502 = &_out_womask_T_502; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_502 = out_rivalid_1_356 & out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5163 = out_f_rivalid_502; // @[RegisterRouter.scala:87:24] wire out_f_roready_502 = out_roready_1_356 & out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5164 = out_f_roready_502; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_502 = out_wivalid_1_356 & out_wimask_502; // @[RegisterRouter.scala:87:24] wire out_f_woready_502 = out_woready_1_356 & out_womask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5165 = ~out_rimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5166 = ~out_wimask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5167 = ~out_romask_502; // @[RegisterRouter.scala:87:24] wire _out_T_5168 = ~out_womask_502; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_422 = {hi_811, flags_0_go, _out_prepend_T_422}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5169 = out_prepend_422; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5170 = _out_T_5169; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_423 = _out_T_5170; // @[RegisterRouter.scala:87:24] wire out_rimask_503 = |_out_rimask_T_503; // @[RegisterRouter.scala:87:24] wire out_wimask_503 = &_out_wimask_T_503; // @[RegisterRouter.scala:87:24] wire out_romask_503 = |_out_romask_T_503; // @[RegisterRouter.scala:87:24] wire out_womask_503 = &_out_womask_T_503; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_503 = out_rivalid_1_357 & out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5172 = out_f_rivalid_503; // @[RegisterRouter.scala:87:24] wire out_f_roready_503 = out_roready_1_357 & out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5173 = out_f_roready_503; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_503 = out_wivalid_1_357 & out_wimask_503; // @[RegisterRouter.scala:87:24] wire out_f_woready_503 = out_woready_1_357 & out_womask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5174 = ~out_rimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5175 = ~out_wimask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5176 = ~out_romask_503; // @[RegisterRouter.scala:87:24] wire _out_T_5177 = ~out_womask_503; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_423 = {hi_812, flags_0_go, _out_prepend_T_423}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5178 = out_prepend_423; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5179 = _out_T_5178; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_424 = _out_T_5179; // @[RegisterRouter.scala:87:24] wire out_rimask_504 = |_out_rimask_T_504; // @[RegisterRouter.scala:87:24] wire out_wimask_504 = &_out_wimask_T_504; // @[RegisterRouter.scala:87:24] wire out_romask_504 = |_out_romask_T_504; // @[RegisterRouter.scala:87:24] wire out_womask_504 = &_out_womask_T_504; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_504 = out_rivalid_1_358 & out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5181 = out_f_rivalid_504; // @[RegisterRouter.scala:87:24] wire out_f_roready_504 = out_roready_1_358 & out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5182 = out_f_roready_504; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_504 = out_wivalid_1_358 & out_wimask_504; // @[RegisterRouter.scala:87:24] wire out_f_woready_504 = out_woready_1_358 & out_womask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5183 = ~out_rimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5184 = ~out_wimask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5185 = ~out_romask_504; // @[RegisterRouter.scala:87:24] wire _out_T_5186 = ~out_womask_504; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_424 = {hi_813, flags_0_go, _out_prepend_T_424}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5187 = out_prepend_424; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5188 = _out_T_5187; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_425 = _out_T_5188; // @[RegisterRouter.scala:87:24] wire out_rimask_505 = |_out_rimask_T_505; // @[RegisterRouter.scala:87:24] wire out_wimask_505 = &_out_wimask_T_505; // @[RegisterRouter.scala:87:24] wire out_romask_505 = |_out_romask_T_505; // @[RegisterRouter.scala:87:24] wire out_womask_505 = &_out_womask_T_505; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_505 = out_rivalid_1_359 & out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5190 = out_f_rivalid_505; // @[RegisterRouter.scala:87:24] wire out_f_roready_505 = out_roready_1_359 & out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5191 = out_f_roready_505; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_505 = out_wivalid_1_359 & out_wimask_505; // @[RegisterRouter.scala:87:24] wire out_f_woready_505 = out_woready_1_359 & out_womask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5192 = ~out_rimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5193 = ~out_wimask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5194 = ~out_romask_505; // @[RegisterRouter.scala:87:24] wire _out_T_5195 = ~out_womask_505; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_425 = {hi_814, flags_0_go, _out_prepend_T_425}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5196 = out_prepend_425; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5197 = _out_T_5196; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_426 = _out_T_5197; // @[RegisterRouter.scala:87:24] wire out_rimask_506 = |_out_rimask_T_506; // @[RegisterRouter.scala:87:24] wire out_wimask_506 = &_out_wimask_T_506; // @[RegisterRouter.scala:87:24] wire out_romask_506 = |_out_romask_T_506; // @[RegisterRouter.scala:87:24] wire out_womask_506 = &_out_womask_T_506; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_506 = out_rivalid_1_360 & out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5199 = out_f_rivalid_506; // @[RegisterRouter.scala:87:24] wire out_f_roready_506 = out_roready_1_360 & out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5200 = out_f_roready_506; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_506 = out_wivalid_1_360 & out_wimask_506; // @[RegisterRouter.scala:87:24] wire out_f_woready_506 = out_woready_1_360 & out_womask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5201 = ~out_rimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5202 = ~out_wimask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5203 = ~out_romask_506; // @[RegisterRouter.scala:87:24] wire _out_T_5204 = ~out_womask_506; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_426 = {hi_815, flags_0_go, _out_prepend_T_426}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5205 = out_prepend_426; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5206 = _out_T_5205; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_427 = _out_T_5206; // @[RegisterRouter.scala:87:24] wire out_rimask_507 = |_out_rimask_T_507; // @[RegisterRouter.scala:87:24] wire out_wimask_507 = &_out_wimask_T_507; // @[RegisterRouter.scala:87:24] wire out_romask_507 = |_out_romask_T_507; // @[RegisterRouter.scala:87:24] wire out_womask_507 = &_out_womask_T_507; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_507 = out_rivalid_1_361 & out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5208 = out_f_rivalid_507; // @[RegisterRouter.scala:87:24] wire out_f_roready_507 = out_roready_1_361 & out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5209 = out_f_roready_507; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_507 = out_wivalid_1_361 & out_wimask_507; // @[RegisterRouter.scala:87:24] wire out_f_woready_507 = out_woready_1_361 & out_womask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5210 = ~out_rimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5211 = ~out_wimask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5212 = ~out_romask_507; // @[RegisterRouter.scala:87:24] wire _out_T_5213 = ~out_womask_507; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_427 = {hi_816, flags_0_go, _out_prepend_T_427}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5214 = out_prepend_427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5215 = _out_T_5214; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_229 = _out_T_5215; // @[MuxLiteral.scala:49:48] wire out_rimask_508 = |_out_rimask_T_508; // @[RegisterRouter.scala:87:24] wire out_wimask_508 = &_out_wimask_T_508; // @[RegisterRouter.scala:87:24] wire out_romask_508 = |_out_romask_T_508; // @[RegisterRouter.scala:87:24] wire out_womask_508 = &_out_womask_T_508; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_508 = out_rivalid_1_362 & out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5217 = out_f_rivalid_508; // @[RegisterRouter.scala:87:24] wire out_f_roready_508 = out_roready_1_362 & out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5218 = out_f_roready_508; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_508 = out_wivalid_1_362 & out_wimask_508; // @[RegisterRouter.scala:87:24] wire out_f_woready_508 = out_woready_1_362 & out_womask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5219 = ~out_rimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5220 = ~out_wimask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5221 = ~out_romask_508; // @[RegisterRouter.scala:87:24] wire _out_T_5222 = ~out_womask_508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5224 = _out_T_5223; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_428 = _out_T_5224; // @[RegisterRouter.scala:87:24] wire out_rimask_509 = |_out_rimask_T_509; // @[RegisterRouter.scala:87:24] wire out_wimask_509 = &_out_wimask_T_509; // @[RegisterRouter.scala:87:24] wire out_romask_509 = |_out_romask_T_509; // @[RegisterRouter.scala:87:24] wire out_womask_509 = &_out_womask_T_509; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_509 = out_rivalid_1_363 & out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5226 = out_f_rivalid_509; // @[RegisterRouter.scala:87:24] wire out_f_roready_509 = out_roready_1_363 & out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5227 = out_f_roready_509; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_509 = out_wivalid_1_363 & out_wimask_509; // @[RegisterRouter.scala:87:24] wire out_f_woready_509 = out_woready_1_363 & out_womask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5228 = ~out_rimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5229 = ~out_wimask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5230 = ~out_romask_509; // @[RegisterRouter.scala:87:24] wire _out_T_5231 = ~out_womask_509; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_428 = {hi_994, flags_0_go, _out_prepend_T_428}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5232 = out_prepend_428; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5233 = _out_T_5232; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_429 = _out_T_5233; // @[RegisterRouter.scala:87:24] wire out_rimask_510 = |_out_rimask_T_510; // @[RegisterRouter.scala:87:24] wire out_wimask_510 = &_out_wimask_T_510; // @[RegisterRouter.scala:87:24] wire out_romask_510 = |_out_romask_T_510; // @[RegisterRouter.scala:87:24] wire out_womask_510 = &_out_womask_T_510; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_510 = out_rivalid_1_364 & out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5235 = out_f_rivalid_510; // @[RegisterRouter.scala:87:24] wire out_f_roready_510 = out_roready_1_364 & out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5236 = out_f_roready_510; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_510 = out_wivalid_1_364 & out_wimask_510; // @[RegisterRouter.scala:87:24] wire out_f_woready_510 = out_woready_1_364 & out_womask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5237 = ~out_rimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5238 = ~out_wimask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5239 = ~out_romask_510; // @[RegisterRouter.scala:87:24] wire _out_T_5240 = ~out_womask_510; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_429 = {hi_995, flags_0_go, _out_prepend_T_429}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5241 = out_prepend_429; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5242 = _out_T_5241; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_430 = _out_T_5242; // @[RegisterRouter.scala:87:24] wire out_rimask_511 = |_out_rimask_T_511; // @[RegisterRouter.scala:87:24] wire out_wimask_511 = &_out_wimask_T_511; // @[RegisterRouter.scala:87:24] wire out_romask_511 = |_out_romask_T_511; // @[RegisterRouter.scala:87:24] wire out_womask_511 = &_out_womask_T_511; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_511 = out_rivalid_1_365 & out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5244 = out_f_rivalid_511; // @[RegisterRouter.scala:87:24] wire out_f_roready_511 = out_roready_1_365 & out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5245 = out_f_roready_511; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_511 = out_wivalid_1_365 & out_wimask_511; // @[RegisterRouter.scala:87:24] wire out_f_woready_511 = out_woready_1_365 & out_womask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5246 = ~out_rimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5247 = ~out_wimask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5248 = ~out_romask_511; // @[RegisterRouter.scala:87:24] wire _out_T_5249 = ~out_womask_511; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_430 = {hi_996, flags_0_go, _out_prepend_T_430}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5250 = out_prepend_430; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5251 = _out_T_5250; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_431 = _out_T_5251; // @[RegisterRouter.scala:87:24] wire out_rimask_512 = |_out_rimask_T_512; // @[RegisterRouter.scala:87:24] wire out_wimask_512 = &_out_wimask_T_512; // @[RegisterRouter.scala:87:24] wire out_romask_512 = |_out_romask_T_512; // @[RegisterRouter.scala:87:24] wire out_womask_512 = &_out_womask_T_512; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_512 = out_rivalid_1_366 & out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5253 = out_f_rivalid_512; // @[RegisterRouter.scala:87:24] wire out_f_roready_512 = out_roready_1_366 & out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5254 = out_f_roready_512; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_512 = out_wivalid_1_366 & out_wimask_512; // @[RegisterRouter.scala:87:24] wire out_f_woready_512 = out_woready_1_366 & out_womask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5255 = ~out_rimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5256 = ~out_wimask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5257 = ~out_romask_512; // @[RegisterRouter.scala:87:24] wire _out_T_5258 = ~out_womask_512; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_431 = {hi_997, flags_0_go, _out_prepend_T_431}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5259 = out_prepend_431; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5260 = _out_T_5259; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_432 = _out_T_5260; // @[RegisterRouter.scala:87:24] wire out_rimask_513 = |_out_rimask_T_513; // @[RegisterRouter.scala:87:24] wire out_wimask_513 = &_out_wimask_T_513; // @[RegisterRouter.scala:87:24] wire out_romask_513 = |_out_romask_T_513; // @[RegisterRouter.scala:87:24] wire out_womask_513 = &_out_womask_T_513; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_513 = out_rivalid_1_367 & out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5262 = out_f_rivalid_513; // @[RegisterRouter.scala:87:24] wire out_f_roready_513 = out_roready_1_367 & out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5263 = out_f_roready_513; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_513 = out_wivalid_1_367 & out_wimask_513; // @[RegisterRouter.scala:87:24] wire out_f_woready_513 = out_woready_1_367 & out_womask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5264 = ~out_rimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5265 = ~out_wimask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5266 = ~out_romask_513; // @[RegisterRouter.scala:87:24] wire _out_T_5267 = ~out_womask_513; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_432 = {hi_998, flags_0_go, _out_prepend_T_432}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5268 = out_prepend_432; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5269 = _out_T_5268; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_433 = _out_T_5269; // @[RegisterRouter.scala:87:24] wire out_rimask_514 = |_out_rimask_T_514; // @[RegisterRouter.scala:87:24] wire out_wimask_514 = &_out_wimask_T_514; // @[RegisterRouter.scala:87:24] wire out_romask_514 = |_out_romask_T_514; // @[RegisterRouter.scala:87:24] wire out_womask_514 = &_out_womask_T_514; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_514 = out_rivalid_1_368 & out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5271 = out_f_rivalid_514; // @[RegisterRouter.scala:87:24] wire out_f_roready_514 = out_roready_1_368 & out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5272 = out_f_roready_514; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_514 = out_wivalid_1_368 & out_wimask_514; // @[RegisterRouter.scala:87:24] wire out_f_woready_514 = out_woready_1_368 & out_womask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5273 = ~out_rimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5274 = ~out_wimask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5275 = ~out_romask_514; // @[RegisterRouter.scala:87:24] wire _out_T_5276 = ~out_womask_514; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_433 = {hi_999, flags_0_go, _out_prepend_T_433}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5277 = out_prepend_433; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5278 = _out_T_5277; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_434 = _out_T_5278; // @[RegisterRouter.scala:87:24] wire out_rimask_515 = |_out_rimask_T_515; // @[RegisterRouter.scala:87:24] wire out_wimask_515 = &_out_wimask_T_515; // @[RegisterRouter.scala:87:24] wire out_romask_515 = |_out_romask_T_515; // @[RegisterRouter.scala:87:24] wire out_womask_515 = &_out_womask_T_515; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_515 = out_rivalid_1_369 & out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5280 = out_f_rivalid_515; // @[RegisterRouter.scala:87:24] wire out_f_roready_515 = out_roready_1_369 & out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5281 = out_f_roready_515; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_515 = out_wivalid_1_369 & out_wimask_515; // @[RegisterRouter.scala:87:24] wire out_f_woready_515 = out_woready_1_369 & out_womask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5282 = ~out_rimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5283 = ~out_wimask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5284 = ~out_romask_515; // @[RegisterRouter.scala:87:24] wire _out_T_5285 = ~out_womask_515; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_434 = {hi_1000, flags_0_go, _out_prepend_T_434}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5286 = out_prepend_434; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5287 = _out_T_5286; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_252 = _out_T_5287; // @[MuxLiteral.scala:49:48] wire out_rimask_516 = |_out_rimask_T_516; // @[RegisterRouter.scala:87:24] wire out_wimask_516 = &_out_wimask_T_516; // @[RegisterRouter.scala:87:24] wire out_romask_516 = |_out_romask_T_516; // @[RegisterRouter.scala:87:24] wire out_womask_516 = &_out_womask_T_516; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_516 = out_rivalid_1_370 & out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5289 = out_f_rivalid_516; // @[RegisterRouter.scala:87:24] wire out_f_roready_516 = out_roready_1_370 & out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5290 = out_f_roready_516; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_516 = out_wivalid_1_370 & out_wimask_516; // @[RegisterRouter.scala:87:24] wire out_f_woready_516 = out_woready_1_370 & out_womask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5291 = ~out_rimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5292 = ~out_wimask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5293 = ~out_romask_516; // @[RegisterRouter.scala:87:24] wire _out_T_5294 = ~out_womask_516; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5296 = _out_T_5295; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_435 = _out_T_5296; // @[RegisterRouter.scala:87:24] wire out_rimask_517 = |_out_rimask_T_517; // @[RegisterRouter.scala:87:24] wire out_wimask_517 = &_out_wimask_T_517; // @[RegisterRouter.scala:87:24] wire out_romask_517 = |_out_romask_T_517; // @[RegisterRouter.scala:87:24] wire out_womask_517 = &_out_womask_T_517; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_517 = out_rivalid_1_371 & out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5298 = out_f_rivalid_517; // @[RegisterRouter.scala:87:24] wire out_f_roready_517 = out_roready_1_371 & out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5299 = out_f_roready_517; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_517 = out_wivalid_1_371 & out_wimask_517; // @[RegisterRouter.scala:87:24] wire out_f_woready_517 = out_woready_1_371 & out_womask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5300 = ~out_rimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5301 = ~out_wimask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5302 = ~out_romask_517; // @[RegisterRouter.scala:87:24] wire _out_T_5303 = ~out_womask_517; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_435 = {hi_554, flags_0_go, _out_prepend_T_435}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5304 = out_prepend_435; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5305 = _out_T_5304; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_436 = _out_T_5305; // @[RegisterRouter.scala:87:24] wire out_rimask_518 = |_out_rimask_T_518; // @[RegisterRouter.scala:87:24] wire out_wimask_518 = &_out_wimask_T_518; // @[RegisterRouter.scala:87:24] wire out_romask_518 = |_out_romask_T_518; // @[RegisterRouter.scala:87:24] wire out_womask_518 = &_out_womask_T_518; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_518 = out_rivalid_1_372 & out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5307 = out_f_rivalid_518; // @[RegisterRouter.scala:87:24] wire out_f_roready_518 = out_roready_1_372 & out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5308 = out_f_roready_518; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_518 = out_wivalid_1_372 & out_wimask_518; // @[RegisterRouter.scala:87:24] wire out_f_woready_518 = out_woready_1_372 & out_womask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5309 = ~out_rimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5310 = ~out_wimask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5311 = ~out_romask_518; // @[RegisterRouter.scala:87:24] wire _out_T_5312 = ~out_womask_518; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_436 = {hi_555, flags_0_go, _out_prepend_T_436}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5313 = out_prepend_436; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5314 = _out_T_5313; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_437 = _out_T_5314; // @[RegisterRouter.scala:87:24] wire out_rimask_519 = |_out_rimask_T_519; // @[RegisterRouter.scala:87:24] wire out_wimask_519 = &_out_wimask_T_519; // @[RegisterRouter.scala:87:24] wire out_romask_519 = |_out_romask_T_519; // @[RegisterRouter.scala:87:24] wire out_womask_519 = &_out_womask_T_519; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_519 = out_rivalid_1_373 & out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5316 = out_f_rivalid_519; // @[RegisterRouter.scala:87:24] wire out_f_roready_519 = out_roready_1_373 & out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5317 = out_f_roready_519; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_519 = out_wivalid_1_373 & out_wimask_519; // @[RegisterRouter.scala:87:24] wire out_f_woready_519 = out_woready_1_373 & out_womask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5318 = ~out_rimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5319 = ~out_wimask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5320 = ~out_romask_519; // @[RegisterRouter.scala:87:24] wire _out_T_5321 = ~out_womask_519; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_437 = {hi_556, flags_0_go, _out_prepend_T_437}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5322 = out_prepend_437; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5323 = _out_T_5322; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_438 = _out_T_5323; // @[RegisterRouter.scala:87:24] wire out_rimask_520 = |_out_rimask_T_520; // @[RegisterRouter.scala:87:24] wire out_wimask_520 = &_out_wimask_T_520; // @[RegisterRouter.scala:87:24] wire out_romask_520 = |_out_romask_T_520; // @[RegisterRouter.scala:87:24] wire out_womask_520 = &_out_womask_T_520; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_520 = out_rivalid_1_374 & out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5325 = out_f_rivalid_520; // @[RegisterRouter.scala:87:24] wire out_f_roready_520 = out_roready_1_374 & out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5326 = out_f_roready_520; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_520 = out_wivalid_1_374 & out_wimask_520; // @[RegisterRouter.scala:87:24] wire out_f_woready_520 = out_woready_1_374 & out_womask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5327 = ~out_rimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5328 = ~out_wimask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5329 = ~out_romask_520; // @[RegisterRouter.scala:87:24] wire _out_T_5330 = ~out_womask_520; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_438 = {hi_557, flags_0_go, _out_prepend_T_438}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5331 = out_prepend_438; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5332 = _out_T_5331; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_439 = _out_T_5332; // @[RegisterRouter.scala:87:24] wire out_rimask_521 = |_out_rimask_T_521; // @[RegisterRouter.scala:87:24] wire out_wimask_521 = &_out_wimask_T_521; // @[RegisterRouter.scala:87:24] wire out_romask_521 = |_out_romask_T_521; // @[RegisterRouter.scala:87:24] wire out_womask_521 = &_out_womask_T_521; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_521 = out_rivalid_1_375 & out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5334 = out_f_rivalid_521; // @[RegisterRouter.scala:87:24] wire out_f_roready_521 = out_roready_1_375 & out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5335 = out_f_roready_521; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_521 = out_wivalid_1_375 & out_wimask_521; // @[RegisterRouter.scala:87:24] wire out_f_woready_521 = out_woready_1_375 & out_womask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5336 = ~out_rimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5337 = ~out_wimask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5338 = ~out_romask_521; // @[RegisterRouter.scala:87:24] wire _out_T_5339 = ~out_womask_521; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_439 = {hi_558, flags_0_go, _out_prepend_T_439}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5340 = out_prepend_439; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5341 = _out_T_5340; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_440 = _out_T_5341; // @[RegisterRouter.scala:87:24] wire out_rimask_522 = |_out_rimask_T_522; // @[RegisterRouter.scala:87:24] wire out_wimask_522 = &_out_wimask_T_522; // @[RegisterRouter.scala:87:24] wire out_romask_522 = |_out_romask_T_522; // @[RegisterRouter.scala:87:24] wire out_womask_522 = &_out_womask_T_522; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_522 = out_rivalid_1_376 & out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5343 = out_f_rivalid_522; // @[RegisterRouter.scala:87:24] wire out_f_roready_522 = out_roready_1_376 & out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5344 = out_f_roready_522; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_522 = out_wivalid_1_376 & out_wimask_522; // @[RegisterRouter.scala:87:24] wire out_f_woready_522 = out_woready_1_376 & out_womask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5345 = ~out_rimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5346 = ~out_wimask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5347 = ~out_romask_522; // @[RegisterRouter.scala:87:24] wire _out_T_5348 = ~out_womask_522; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_440 = {hi_559, flags_0_go, _out_prepend_T_440}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5349 = out_prepend_440; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5350 = _out_T_5349; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_441 = _out_T_5350; // @[RegisterRouter.scala:87:24] wire out_rimask_523 = |_out_rimask_T_523; // @[RegisterRouter.scala:87:24] wire out_wimask_523 = &_out_wimask_T_523; // @[RegisterRouter.scala:87:24] wire out_romask_523 = |_out_romask_T_523; // @[RegisterRouter.scala:87:24] wire out_womask_523 = &_out_womask_T_523; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_523 = out_rivalid_1_377 & out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5352 = out_f_rivalid_523; // @[RegisterRouter.scala:87:24] wire out_f_roready_523 = out_roready_1_377 & out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5353 = out_f_roready_523; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_523 = out_wivalid_1_377 & out_wimask_523; // @[RegisterRouter.scala:87:24] wire out_f_woready_523 = out_woready_1_377 & out_womask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5354 = ~out_rimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5355 = ~out_wimask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5356 = ~out_romask_523; // @[RegisterRouter.scala:87:24] wire _out_T_5357 = ~out_womask_523; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_441 = {hi_560, flags_0_go, _out_prepend_T_441}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5358 = out_prepend_441; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5359 = _out_T_5358; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_197 = _out_T_5359; // @[MuxLiteral.scala:49:48] wire out_rimask_524 = |_out_rimask_T_524; // @[RegisterRouter.scala:87:24] wire out_wimask_524 = &_out_wimask_T_524; // @[RegisterRouter.scala:87:24] wire out_romask_524 = |_out_romask_T_524; // @[RegisterRouter.scala:87:24] wire out_womask_524 = &_out_womask_T_524; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_524 = out_rivalid_1_378 & out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5361 = out_f_rivalid_524; // @[RegisterRouter.scala:87:24] wire out_f_roready_524 = out_roready_1_378 & out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5362 = out_f_roready_524; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_524 = out_wivalid_1_378 & out_wimask_524; // @[RegisterRouter.scala:87:24] wire out_f_woready_524 = out_woready_1_378 & out_womask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5363 = ~out_rimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5364 = ~out_wimask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5365 = ~out_romask_524; // @[RegisterRouter.scala:87:24] wire _out_T_5366 = ~out_womask_524; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5368 = _out_T_5367; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_442 = _out_T_5368; // @[RegisterRouter.scala:87:24] wire out_rimask_525 = |_out_rimask_T_525; // @[RegisterRouter.scala:87:24] wire out_wimask_525 = &_out_wimask_T_525; // @[RegisterRouter.scala:87:24] wire out_romask_525 = |_out_romask_T_525; // @[RegisterRouter.scala:87:24] wire out_womask_525 = &_out_womask_T_525; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_525 = out_rivalid_1_379 & out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5370 = out_f_rivalid_525; // @[RegisterRouter.scala:87:24] wire out_f_roready_525 = out_roready_1_379 & out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5371 = out_f_roready_525; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_525 = out_wivalid_1_379 & out_wimask_525; // @[RegisterRouter.scala:87:24] wire out_f_woready_525 = out_woready_1_379 & out_womask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5372 = ~out_rimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5373 = ~out_wimask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5374 = ~out_romask_525; // @[RegisterRouter.scala:87:24] wire _out_T_5375 = ~out_womask_525; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_442 = {hi_770, flags_0_go, _out_prepend_T_442}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5376 = out_prepend_442; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5377 = _out_T_5376; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_443 = _out_T_5377; // @[RegisterRouter.scala:87:24] wire out_rimask_526 = |_out_rimask_T_526; // @[RegisterRouter.scala:87:24] wire out_wimask_526 = &_out_wimask_T_526; // @[RegisterRouter.scala:87:24] wire out_romask_526 = |_out_romask_T_526; // @[RegisterRouter.scala:87:24] wire out_womask_526 = &_out_womask_T_526; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_526 = out_rivalid_1_380 & out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5379 = out_f_rivalid_526; // @[RegisterRouter.scala:87:24] wire out_f_roready_526 = out_roready_1_380 & out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5380 = out_f_roready_526; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_526 = out_wivalid_1_380 & out_wimask_526; // @[RegisterRouter.scala:87:24] wire out_f_woready_526 = out_woready_1_380 & out_womask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5381 = ~out_rimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5382 = ~out_wimask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5383 = ~out_romask_526; // @[RegisterRouter.scala:87:24] wire _out_T_5384 = ~out_womask_526; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_443 = {hi_771, flags_0_go, _out_prepend_T_443}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5385 = out_prepend_443; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5386 = _out_T_5385; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_444 = _out_T_5386; // @[RegisterRouter.scala:87:24] wire out_rimask_527 = |_out_rimask_T_527; // @[RegisterRouter.scala:87:24] wire out_wimask_527 = &_out_wimask_T_527; // @[RegisterRouter.scala:87:24] wire out_romask_527 = |_out_romask_T_527; // @[RegisterRouter.scala:87:24] wire out_womask_527 = &_out_womask_T_527; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_527 = out_rivalid_1_381 & out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5388 = out_f_rivalid_527; // @[RegisterRouter.scala:87:24] wire out_f_roready_527 = out_roready_1_381 & out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5389 = out_f_roready_527; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_527 = out_wivalid_1_381 & out_wimask_527; // @[RegisterRouter.scala:87:24] wire out_f_woready_527 = out_woready_1_381 & out_womask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5390 = ~out_rimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5391 = ~out_wimask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5392 = ~out_romask_527; // @[RegisterRouter.scala:87:24] wire _out_T_5393 = ~out_womask_527; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_444 = {hi_772, flags_0_go, _out_prepend_T_444}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5394 = out_prepend_444; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5395 = _out_T_5394; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_445 = _out_T_5395; // @[RegisterRouter.scala:87:24] wire out_rimask_528 = |_out_rimask_T_528; // @[RegisterRouter.scala:87:24] wire out_wimask_528 = &_out_wimask_T_528; // @[RegisterRouter.scala:87:24] wire out_romask_528 = |_out_romask_T_528; // @[RegisterRouter.scala:87:24] wire out_womask_528 = &_out_womask_T_528; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_528 = out_rivalid_1_382 & out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5397 = out_f_rivalid_528; // @[RegisterRouter.scala:87:24] wire out_f_roready_528 = out_roready_1_382 & out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5398 = out_f_roready_528; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_528 = out_wivalid_1_382 & out_wimask_528; // @[RegisterRouter.scala:87:24] wire out_f_woready_528 = out_woready_1_382 & out_womask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5399 = ~out_rimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5400 = ~out_wimask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5401 = ~out_romask_528; // @[RegisterRouter.scala:87:24] wire _out_T_5402 = ~out_womask_528; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_445 = {hi_773, flags_0_go, _out_prepend_T_445}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5403 = out_prepend_445; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5404 = _out_T_5403; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_446 = _out_T_5404; // @[RegisterRouter.scala:87:24] wire out_rimask_529 = |_out_rimask_T_529; // @[RegisterRouter.scala:87:24] wire out_wimask_529 = &_out_wimask_T_529; // @[RegisterRouter.scala:87:24] wire out_romask_529 = |_out_romask_T_529; // @[RegisterRouter.scala:87:24] wire out_womask_529 = &_out_womask_T_529; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_529 = out_rivalid_1_383 & out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5406 = out_f_rivalid_529; // @[RegisterRouter.scala:87:24] wire out_f_roready_529 = out_roready_1_383 & out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5407 = out_f_roready_529; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_529 = out_wivalid_1_383 & out_wimask_529; // @[RegisterRouter.scala:87:24] wire out_f_woready_529 = out_woready_1_383 & out_womask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5408 = ~out_rimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5409 = ~out_wimask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5410 = ~out_romask_529; // @[RegisterRouter.scala:87:24] wire _out_T_5411 = ~out_womask_529; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_446 = {hi_774, flags_0_go, _out_prepend_T_446}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5412 = out_prepend_446; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5413 = _out_T_5412; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_447 = _out_T_5413; // @[RegisterRouter.scala:87:24] wire out_rimask_530 = |_out_rimask_T_530; // @[RegisterRouter.scala:87:24] wire out_wimask_530 = &_out_wimask_T_530; // @[RegisterRouter.scala:87:24] wire out_romask_530 = |_out_romask_T_530; // @[RegisterRouter.scala:87:24] wire out_womask_530 = &_out_womask_T_530; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_530 = out_rivalid_1_384 & out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5415 = out_f_rivalid_530; // @[RegisterRouter.scala:87:24] wire out_f_roready_530 = out_roready_1_384 & out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5416 = out_f_roready_530; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_530 = out_wivalid_1_384 & out_wimask_530; // @[RegisterRouter.scala:87:24] wire out_f_woready_530 = out_woready_1_384 & out_womask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5417 = ~out_rimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5418 = ~out_wimask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5419 = ~out_romask_530; // @[RegisterRouter.scala:87:24] wire _out_T_5420 = ~out_womask_530; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_447 = {hi_775, flags_0_go, _out_prepend_T_447}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5421 = out_prepend_447; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5422 = _out_T_5421; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_448 = _out_T_5422; // @[RegisterRouter.scala:87:24] wire out_rimask_531 = |_out_rimask_T_531; // @[RegisterRouter.scala:87:24] wire out_wimask_531 = &_out_wimask_T_531; // @[RegisterRouter.scala:87:24] wire out_romask_531 = |_out_romask_T_531; // @[RegisterRouter.scala:87:24] wire out_womask_531 = &_out_womask_T_531; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_531 = out_rivalid_1_385 & out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5424 = out_f_rivalid_531; // @[RegisterRouter.scala:87:24] wire out_f_roready_531 = out_roready_1_385 & out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5425 = out_f_roready_531; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_531 = out_wivalid_1_385 & out_wimask_531; // @[RegisterRouter.scala:87:24] wire out_f_woready_531 = out_woready_1_385 & out_womask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5426 = ~out_rimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5427 = ~out_wimask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5428 = ~out_romask_531; // @[RegisterRouter.scala:87:24] wire _out_T_5429 = ~out_womask_531; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_448 = {hi_776, flags_0_go, _out_prepend_T_448}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5430 = out_prepend_448; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5431 = _out_T_5430; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_224 = _out_T_5431; // @[MuxLiteral.scala:49:48] wire out_rimask_532 = |_out_rimask_T_532; // @[RegisterRouter.scala:87:24] wire out_wimask_532 = &_out_wimask_T_532; // @[RegisterRouter.scala:87:24] wire out_romask_532 = |_out_romask_T_532; // @[RegisterRouter.scala:87:24] wire out_womask_532 = &_out_womask_T_532; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_532 = out_rivalid_1_386 & out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5433 = out_f_rivalid_532; // @[RegisterRouter.scala:87:24] wire out_f_roready_532 = out_roready_1_386 & out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5434 = out_f_roready_532; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_532 = out_wivalid_1_386 & out_wimask_532; // @[RegisterRouter.scala:87:24] wire out_f_woready_532 = out_woready_1_386 & out_womask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5435 = ~out_rimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5436 = ~out_wimask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5437 = ~out_romask_532; // @[RegisterRouter.scala:87:24] wire _out_T_5438 = ~out_womask_532; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5440 = _out_T_5439; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_449 = _out_T_5440; // @[RegisterRouter.scala:87:24] wire out_rimask_533 = |_out_rimask_T_533; // @[RegisterRouter.scala:87:24] wire out_wimask_533 = &_out_wimask_T_533; // @[RegisterRouter.scala:87:24] wire out_romask_533 = |_out_romask_T_533; // @[RegisterRouter.scala:87:24] wire out_womask_533 = &_out_womask_T_533; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_533 = out_rivalid_1_387 & out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5442 = out_f_rivalid_533; // @[RegisterRouter.scala:87:24] wire out_f_roready_533 = out_roready_1_387 & out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5443 = out_f_roready_533; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_533 = out_wivalid_1_387 & out_wimask_533; // @[RegisterRouter.scala:87:24] wire out_f_woready_533 = out_woready_1_387 & out_womask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5444 = ~out_rimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5445 = ~out_wimask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5446 = ~out_romask_533; // @[RegisterRouter.scala:87:24] wire _out_T_5447 = ~out_womask_533; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_449 = {hi_226, flags_0_go, _out_prepend_T_449}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5448 = out_prepend_449; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5449 = _out_T_5448; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_450 = _out_T_5449; // @[RegisterRouter.scala:87:24] wire out_rimask_534 = |_out_rimask_T_534; // @[RegisterRouter.scala:87:24] wire out_wimask_534 = &_out_wimask_T_534; // @[RegisterRouter.scala:87:24] wire out_romask_534 = |_out_romask_T_534; // @[RegisterRouter.scala:87:24] wire out_womask_534 = &_out_womask_T_534; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_534 = out_rivalid_1_388 & out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5451 = out_f_rivalid_534; // @[RegisterRouter.scala:87:24] wire out_f_roready_534 = out_roready_1_388 & out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5452 = out_f_roready_534; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_534 = out_wivalid_1_388 & out_wimask_534; // @[RegisterRouter.scala:87:24] wire out_f_woready_534 = out_woready_1_388 & out_womask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5453 = ~out_rimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5454 = ~out_wimask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5455 = ~out_romask_534; // @[RegisterRouter.scala:87:24] wire _out_T_5456 = ~out_womask_534; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_450 = {hi_227, flags_0_go, _out_prepend_T_450}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5457 = out_prepend_450; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5458 = _out_T_5457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_451 = _out_T_5458; // @[RegisterRouter.scala:87:24] wire out_rimask_535 = |_out_rimask_T_535; // @[RegisterRouter.scala:87:24] wire out_wimask_535 = &_out_wimask_T_535; // @[RegisterRouter.scala:87:24] wire out_romask_535 = |_out_romask_T_535; // @[RegisterRouter.scala:87:24] wire out_womask_535 = &_out_womask_T_535; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_535 = out_rivalid_1_389 & out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5460 = out_f_rivalid_535; // @[RegisterRouter.scala:87:24] wire out_f_roready_535 = out_roready_1_389 & out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5461 = out_f_roready_535; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_535 = out_wivalid_1_389 & out_wimask_535; // @[RegisterRouter.scala:87:24] wire out_f_woready_535 = out_woready_1_389 & out_womask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5462 = ~out_rimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5463 = ~out_wimask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5464 = ~out_romask_535; // @[RegisterRouter.scala:87:24] wire _out_T_5465 = ~out_womask_535; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_451 = {hi_228, flags_0_go, _out_prepend_T_451}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5466 = out_prepend_451; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5467 = _out_T_5466; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_452 = _out_T_5467; // @[RegisterRouter.scala:87:24] wire out_rimask_536 = |_out_rimask_T_536; // @[RegisterRouter.scala:87:24] wire out_wimask_536 = &_out_wimask_T_536; // @[RegisterRouter.scala:87:24] wire out_romask_536 = |_out_romask_T_536; // @[RegisterRouter.scala:87:24] wire out_womask_536 = &_out_womask_T_536; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_536 = out_rivalid_1_390 & out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5469 = out_f_rivalid_536; // @[RegisterRouter.scala:87:24] wire out_f_roready_536 = out_roready_1_390 & out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5470 = out_f_roready_536; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_536 = out_wivalid_1_390 & out_wimask_536; // @[RegisterRouter.scala:87:24] wire out_f_woready_536 = out_woready_1_390 & out_womask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5471 = ~out_rimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5472 = ~out_wimask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5473 = ~out_romask_536; // @[RegisterRouter.scala:87:24] wire _out_T_5474 = ~out_womask_536; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_452 = {hi_229, flags_0_go, _out_prepend_T_452}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5475 = out_prepend_452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5476 = _out_T_5475; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_453 = _out_T_5476; // @[RegisterRouter.scala:87:24] wire out_rimask_537 = |_out_rimask_T_537; // @[RegisterRouter.scala:87:24] wire out_wimask_537 = &_out_wimask_T_537; // @[RegisterRouter.scala:87:24] wire out_romask_537 = |_out_romask_T_537; // @[RegisterRouter.scala:87:24] wire out_womask_537 = &_out_womask_T_537; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_537 = out_rivalid_1_391 & out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5478 = out_f_rivalid_537; // @[RegisterRouter.scala:87:24] wire out_f_roready_537 = out_roready_1_391 & out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5479 = out_f_roready_537; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_537 = out_wivalid_1_391 & out_wimask_537; // @[RegisterRouter.scala:87:24] wire out_f_woready_537 = out_woready_1_391 & out_womask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5480 = ~out_rimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5481 = ~out_wimask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5482 = ~out_romask_537; // @[RegisterRouter.scala:87:24] wire _out_T_5483 = ~out_womask_537; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_453 = {hi_230, flags_0_go, _out_prepend_T_453}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5484 = out_prepend_453; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5485 = _out_T_5484; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_454 = _out_T_5485; // @[RegisterRouter.scala:87:24] wire out_rimask_538 = |_out_rimask_T_538; // @[RegisterRouter.scala:87:24] wire out_wimask_538 = &_out_wimask_T_538; // @[RegisterRouter.scala:87:24] wire out_romask_538 = |_out_romask_T_538; // @[RegisterRouter.scala:87:24] wire out_womask_538 = &_out_womask_T_538; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_538 = out_rivalid_1_392 & out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5487 = out_f_rivalid_538; // @[RegisterRouter.scala:87:24] wire out_f_roready_538 = out_roready_1_392 & out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5488 = out_f_roready_538; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_538 = out_wivalid_1_392 & out_wimask_538; // @[RegisterRouter.scala:87:24] wire out_f_woready_538 = out_woready_1_392 & out_womask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5489 = ~out_rimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5490 = ~out_wimask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5491 = ~out_romask_538; // @[RegisterRouter.scala:87:24] wire _out_T_5492 = ~out_womask_538; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_454 = {hi_231, flags_0_go, _out_prepend_T_454}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5493 = out_prepend_454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5494 = _out_T_5493; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_455 = _out_T_5494; // @[RegisterRouter.scala:87:24] wire out_rimask_539 = |_out_rimask_T_539; // @[RegisterRouter.scala:87:24] wire out_wimask_539 = &_out_wimask_T_539; // @[RegisterRouter.scala:87:24] wire out_romask_539 = |_out_romask_T_539; // @[RegisterRouter.scala:87:24] wire out_womask_539 = &_out_womask_T_539; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_539 = out_rivalid_1_393 & out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5496 = out_f_rivalid_539; // @[RegisterRouter.scala:87:24] wire out_f_roready_539 = out_roready_1_393 & out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5497 = out_f_roready_539; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_539 = out_wivalid_1_393 & out_wimask_539; // @[RegisterRouter.scala:87:24] wire out_f_woready_539 = out_woready_1_393 & out_womask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5498 = ~out_rimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5499 = ~out_wimask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5500 = ~out_romask_539; // @[RegisterRouter.scala:87:24] wire _out_T_5501 = ~out_womask_539; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_455 = {hi_232, flags_0_go, _out_prepend_T_455}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5502 = out_prepend_455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5503 = _out_T_5502; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_156 = _out_T_5503; // @[MuxLiteral.scala:49:48] wire out_rimask_540 = |_out_rimask_T_540; // @[RegisterRouter.scala:87:24] wire out_wimask_540 = &_out_wimask_T_540; // @[RegisterRouter.scala:87:24] wire out_romask_540 = |_out_romask_T_540; // @[RegisterRouter.scala:87:24] wire out_womask_540 = &_out_womask_T_540; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_540 = out_rivalid_1_394 & out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5505 = out_f_rivalid_540; // @[RegisterRouter.scala:87:24] wire out_f_roready_540 = out_roready_1_394 & out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5506 = out_f_roready_540; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_540 = out_wivalid_1_394 & out_wimask_540; // @[RegisterRouter.scala:87:24] wire out_f_woready_540 = out_woready_1_394 & out_womask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5507 = ~out_rimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5508 = ~out_wimask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5509 = ~out_romask_540; // @[RegisterRouter.scala:87:24] wire _out_T_5510 = ~out_womask_540; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5512 = _out_T_5511; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_456 = _out_T_5512; // @[RegisterRouter.scala:87:24] wire out_rimask_541 = |_out_rimask_T_541; // @[RegisterRouter.scala:87:24] wire out_wimask_541 = &_out_wimask_T_541; // @[RegisterRouter.scala:87:24] wire out_romask_541 = |_out_romask_T_541; // @[RegisterRouter.scala:87:24] wire out_womask_541 = &_out_womask_T_541; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_541 = out_rivalid_1_395 & out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5514 = out_f_rivalid_541; // @[RegisterRouter.scala:87:24] wire out_f_roready_541 = out_roready_1_395 & out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5515 = out_f_roready_541; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_541 = out_wivalid_1_395 & out_wimask_541; // @[RegisterRouter.scala:87:24] wire out_f_woready_541 = out_woready_1_395 & out_womask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5516 = ~out_rimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5517 = ~out_wimask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5518 = ~out_romask_541; // @[RegisterRouter.scala:87:24] wire _out_T_5519 = ~out_womask_541; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_456 = {hi_482, flags_0_go, _out_prepend_T_456}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5520 = out_prepend_456; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5521 = _out_T_5520; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_457 = _out_T_5521; // @[RegisterRouter.scala:87:24] wire out_rimask_542 = |_out_rimask_T_542; // @[RegisterRouter.scala:87:24] wire out_wimask_542 = &_out_wimask_T_542; // @[RegisterRouter.scala:87:24] wire out_romask_542 = |_out_romask_T_542; // @[RegisterRouter.scala:87:24] wire out_womask_542 = &_out_womask_T_542; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_542 = out_rivalid_1_396 & out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5523 = out_f_rivalid_542; // @[RegisterRouter.scala:87:24] wire out_f_roready_542 = out_roready_1_396 & out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5524 = out_f_roready_542; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_542 = out_wivalid_1_396 & out_wimask_542; // @[RegisterRouter.scala:87:24] wire out_f_woready_542 = out_woready_1_396 & out_womask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5525 = ~out_rimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5526 = ~out_wimask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5527 = ~out_romask_542; // @[RegisterRouter.scala:87:24] wire _out_T_5528 = ~out_womask_542; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_457 = {hi_483, flags_0_go, _out_prepend_T_457}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5529 = out_prepend_457; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5530 = _out_T_5529; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_458 = _out_T_5530; // @[RegisterRouter.scala:87:24] wire out_rimask_543 = |_out_rimask_T_543; // @[RegisterRouter.scala:87:24] wire out_wimask_543 = &_out_wimask_T_543; // @[RegisterRouter.scala:87:24] wire out_romask_543 = |_out_romask_T_543; // @[RegisterRouter.scala:87:24] wire out_womask_543 = &_out_womask_T_543; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_543 = out_rivalid_1_397 & out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5532 = out_f_rivalid_543; // @[RegisterRouter.scala:87:24] wire out_f_roready_543 = out_roready_1_397 & out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5533 = out_f_roready_543; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_543 = out_wivalid_1_397 & out_wimask_543; // @[RegisterRouter.scala:87:24] wire out_f_woready_543 = out_woready_1_397 & out_womask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5534 = ~out_rimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5535 = ~out_wimask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5536 = ~out_romask_543; // @[RegisterRouter.scala:87:24] wire _out_T_5537 = ~out_womask_543; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_458 = {hi_484, flags_0_go, _out_prepend_T_458}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5538 = out_prepend_458; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5539 = _out_T_5538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_459 = _out_T_5539; // @[RegisterRouter.scala:87:24] wire out_rimask_544 = |_out_rimask_T_544; // @[RegisterRouter.scala:87:24] wire out_wimask_544 = &_out_wimask_T_544; // @[RegisterRouter.scala:87:24] wire out_romask_544 = |_out_romask_T_544; // @[RegisterRouter.scala:87:24] wire out_womask_544 = &_out_womask_T_544; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_544 = out_rivalid_1_398 & out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5541 = out_f_rivalid_544; // @[RegisterRouter.scala:87:24] wire out_f_roready_544 = out_roready_1_398 & out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5542 = out_f_roready_544; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_544 = out_wivalid_1_398 & out_wimask_544; // @[RegisterRouter.scala:87:24] wire out_f_woready_544 = out_woready_1_398 & out_womask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5543 = ~out_rimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5544 = ~out_wimask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5545 = ~out_romask_544; // @[RegisterRouter.scala:87:24] wire _out_T_5546 = ~out_womask_544; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_459 = {hi_485, flags_0_go, _out_prepend_T_459}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5547 = out_prepend_459; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5548 = _out_T_5547; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_460 = _out_T_5548; // @[RegisterRouter.scala:87:24] wire out_rimask_545 = |_out_rimask_T_545; // @[RegisterRouter.scala:87:24] wire out_wimask_545 = &_out_wimask_T_545; // @[RegisterRouter.scala:87:24] wire out_romask_545 = |_out_romask_T_545; // @[RegisterRouter.scala:87:24] wire out_womask_545 = &_out_womask_T_545; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_545 = out_rivalid_1_399 & out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5550 = out_f_rivalid_545; // @[RegisterRouter.scala:87:24] wire out_f_roready_545 = out_roready_1_399 & out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5551 = out_f_roready_545; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_545 = out_wivalid_1_399 & out_wimask_545; // @[RegisterRouter.scala:87:24] wire out_f_woready_545 = out_woready_1_399 & out_womask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5552 = ~out_rimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5553 = ~out_wimask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5554 = ~out_romask_545; // @[RegisterRouter.scala:87:24] wire _out_T_5555 = ~out_womask_545; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_460 = {hi_486, flags_0_go, _out_prepend_T_460}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5556 = out_prepend_460; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5557 = _out_T_5556; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_461 = _out_T_5557; // @[RegisterRouter.scala:87:24] wire out_rimask_546 = |_out_rimask_T_546; // @[RegisterRouter.scala:87:24] wire out_wimask_546 = &_out_wimask_T_546; // @[RegisterRouter.scala:87:24] wire out_romask_546 = |_out_romask_T_546; // @[RegisterRouter.scala:87:24] wire out_womask_546 = &_out_womask_T_546; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_546 = out_rivalid_1_400 & out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5559 = out_f_rivalid_546; // @[RegisterRouter.scala:87:24] wire out_f_roready_546 = out_roready_1_400 & out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5560 = out_f_roready_546; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_546 = out_wivalid_1_400 & out_wimask_546; // @[RegisterRouter.scala:87:24] wire out_f_woready_546 = out_woready_1_400 & out_womask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5561 = ~out_rimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5562 = ~out_wimask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5563 = ~out_romask_546; // @[RegisterRouter.scala:87:24] wire _out_T_5564 = ~out_womask_546; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_461 = {hi_487, flags_0_go, _out_prepend_T_461}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5565 = out_prepend_461; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5566 = _out_T_5565; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_462 = _out_T_5566; // @[RegisterRouter.scala:87:24] wire out_rimask_547 = |_out_rimask_T_547; // @[RegisterRouter.scala:87:24] wire out_wimask_547 = &_out_wimask_T_547; // @[RegisterRouter.scala:87:24] wire out_romask_547 = |_out_romask_T_547; // @[RegisterRouter.scala:87:24] wire out_womask_547 = &_out_womask_T_547; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_547 = out_rivalid_1_401 & out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5568 = out_f_rivalid_547; // @[RegisterRouter.scala:87:24] wire out_f_roready_547 = out_roready_1_401 & out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5569 = out_f_roready_547; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_547 = out_wivalid_1_401 & out_wimask_547; // @[RegisterRouter.scala:87:24] wire out_f_woready_547 = out_woready_1_401 & out_womask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5570 = ~out_rimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5571 = ~out_wimask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5572 = ~out_romask_547; // @[RegisterRouter.scala:87:24] wire _out_T_5573 = ~out_womask_547; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_462 = {hi_488, flags_0_go, _out_prepend_T_462}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5574 = out_prepend_462; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5575 = _out_T_5574; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_188 = _out_T_5575; // @[MuxLiteral.scala:49:48] wire out_rimask_548 = |_out_rimask_T_548; // @[RegisterRouter.scala:87:24] wire out_wimask_548 = &_out_wimask_T_548; // @[RegisterRouter.scala:87:24] wire out_romask_548 = |_out_romask_T_548; // @[RegisterRouter.scala:87:24] wire out_womask_548 = &_out_womask_T_548; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_548 = out_rivalid_1_402 & out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5577 = out_f_rivalid_548; // @[RegisterRouter.scala:87:24] wire out_f_roready_548 = out_roready_1_402 & out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5578 = out_f_roready_548; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_548 = out_wivalid_1_402 & out_wimask_548; // @[RegisterRouter.scala:87:24] wire out_f_woready_548 = out_woready_1_402 & out_womask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5579 = ~out_rimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5580 = ~out_wimask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5581 = ~out_romask_548; // @[RegisterRouter.scala:87:24] wire _out_T_5582 = ~out_womask_548; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5584 = _out_T_5583; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_463 = _out_T_5584; // @[RegisterRouter.scala:87:24] wire out_rimask_549 = |_out_rimask_T_549; // @[RegisterRouter.scala:87:24] wire out_wimask_549 = &_out_wimask_T_549; // @[RegisterRouter.scala:87:24] wire out_romask_549 = |_out_romask_T_549; // @[RegisterRouter.scala:87:24] wire out_womask_549 = &_out_womask_T_549; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_549 = out_rivalid_1_403 & out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5586 = out_f_rivalid_549; // @[RegisterRouter.scala:87:24] wire out_f_roready_549 = out_roready_1_403 & out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5587 = out_f_roready_549; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_549 = out_wivalid_1_403 & out_wimask_549; // @[RegisterRouter.scala:87:24] wire out_f_woready_549 = out_woready_1_403 & out_womask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5588 = ~out_rimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5589 = ~out_wimask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5590 = ~out_romask_549; // @[RegisterRouter.scala:87:24] wire _out_T_5591 = ~out_womask_549; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_463 = {hi_330, flags_0_go, _out_prepend_T_463}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5592 = out_prepend_463; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5593 = _out_T_5592; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_464 = _out_T_5593; // @[RegisterRouter.scala:87:24] wire out_rimask_550 = |_out_rimask_T_550; // @[RegisterRouter.scala:87:24] wire out_wimask_550 = &_out_wimask_T_550; // @[RegisterRouter.scala:87:24] wire out_romask_550 = |_out_romask_T_550; // @[RegisterRouter.scala:87:24] wire out_womask_550 = &_out_womask_T_550; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_550 = out_rivalid_1_404 & out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5595 = out_f_rivalid_550; // @[RegisterRouter.scala:87:24] wire out_f_roready_550 = out_roready_1_404 & out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5596 = out_f_roready_550; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_550 = out_wivalid_1_404 & out_wimask_550; // @[RegisterRouter.scala:87:24] wire out_f_woready_550 = out_woready_1_404 & out_womask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5597 = ~out_rimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5598 = ~out_wimask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5599 = ~out_romask_550; // @[RegisterRouter.scala:87:24] wire _out_T_5600 = ~out_womask_550; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_464 = {hi_331, flags_0_go, _out_prepend_T_464}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5601 = out_prepend_464; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5602 = _out_T_5601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_465 = _out_T_5602; // @[RegisterRouter.scala:87:24] wire out_rimask_551 = |_out_rimask_T_551; // @[RegisterRouter.scala:87:24] wire out_wimask_551 = &_out_wimask_T_551; // @[RegisterRouter.scala:87:24] wire out_romask_551 = |_out_romask_T_551; // @[RegisterRouter.scala:87:24] wire out_womask_551 = &_out_womask_T_551; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_551 = out_rivalid_1_405 & out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5604 = out_f_rivalid_551; // @[RegisterRouter.scala:87:24] wire out_f_roready_551 = out_roready_1_405 & out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5605 = out_f_roready_551; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_551 = out_wivalid_1_405 & out_wimask_551; // @[RegisterRouter.scala:87:24] wire out_f_woready_551 = out_woready_1_405 & out_womask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5606 = ~out_rimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5607 = ~out_wimask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5608 = ~out_romask_551; // @[RegisterRouter.scala:87:24] wire _out_T_5609 = ~out_womask_551; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_465 = {hi_332, flags_0_go, _out_prepend_T_465}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5610 = out_prepend_465; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5611 = _out_T_5610; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_466 = _out_T_5611; // @[RegisterRouter.scala:87:24] wire out_rimask_552 = |_out_rimask_T_552; // @[RegisterRouter.scala:87:24] wire out_wimask_552 = &_out_wimask_T_552; // @[RegisterRouter.scala:87:24] wire out_romask_552 = |_out_romask_T_552; // @[RegisterRouter.scala:87:24] wire out_womask_552 = &_out_womask_T_552; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_552 = out_rivalid_1_406 & out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5613 = out_f_rivalid_552; // @[RegisterRouter.scala:87:24] wire out_f_roready_552 = out_roready_1_406 & out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5614 = out_f_roready_552; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_552 = out_wivalid_1_406 & out_wimask_552; // @[RegisterRouter.scala:87:24] wire out_f_woready_552 = out_woready_1_406 & out_womask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5615 = ~out_rimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5616 = ~out_wimask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5617 = ~out_romask_552; // @[RegisterRouter.scala:87:24] wire _out_T_5618 = ~out_womask_552; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_466 = {hi_333, flags_0_go, _out_prepend_T_466}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5619 = out_prepend_466; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5620 = _out_T_5619; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_467 = _out_T_5620; // @[RegisterRouter.scala:87:24] wire out_rimask_553 = |_out_rimask_T_553; // @[RegisterRouter.scala:87:24] wire out_wimask_553 = &_out_wimask_T_553; // @[RegisterRouter.scala:87:24] wire out_romask_553 = |_out_romask_T_553; // @[RegisterRouter.scala:87:24] wire out_womask_553 = &_out_womask_T_553; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_553 = out_rivalid_1_407 & out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5622 = out_f_rivalid_553; // @[RegisterRouter.scala:87:24] wire out_f_roready_553 = out_roready_1_407 & out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5623 = out_f_roready_553; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_553 = out_wivalid_1_407 & out_wimask_553; // @[RegisterRouter.scala:87:24] wire out_f_woready_553 = out_woready_1_407 & out_womask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5624 = ~out_rimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5625 = ~out_wimask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5626 = ~out_romask_553; // @[RegisterRouter.scala:87:24] wire _out_T_5627 = ~out_womask_553; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_467 = {hi_334, flags_0_go, _out_prepend_T_467}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5628 = out_prepend_467; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5629 = _out_T_5628; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_468 = _out_T_5629; // @[RegisterRouter.scala:87:24] wire out_rimask_554 = |_out_rimask_T_554; // @[RegisterRouter.scala:87:24] wire out_wimask_554 = &_out_wimask_T_554; // @[RegisterRouter.scala:87:24] wire out_romask_554 = |_out_romask_T_554; // @[RegisterRouter.scala:87:24] wire out_womask_554 = &_out_womask_T_554; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_554 = out_rivalid_1_408 & out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5631 = out_f_rivalid_554; // @[RegisterRouter.scala:87:24] wire out_f_roready_554 = out_roready_1_408 & out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5632 = out_f_roready_554; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_554 = out_wivalid_1_408 & out_wimask_554; // @[RegisterRouter.scala:87:24] wire out_f_woready_554 = out_woready_1_408 & out_womask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5633 = ~out_rimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5634 = ~out_wimask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5635 = ~out_romask_554; // @[RegisterRouter.scala:87:24] wire _out_T_5636 = ~out_womask_554; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_468 = {hi_335, flags_0_go, _out_prepend_T_468}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5637 = out_prepend_468; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5638 = _out_T_5637; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_469 = _out_T_5638; // @[RegisterRouter.scala:87:24] wire out_rimask_555 = |_out_rimask_T_555; // @[RegisterRouter.scala:87:24] wire out_wimask_555 = &_out_wimask_T_555; // @[RegisterRouter.scala:87:24] wire out_romask_555 = |_out_romask_T_555; // @[RegisterRouter.scala:87:24] wire out_womask_555 = &_out_womask_T_555; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_555 = out_rivalid_1_409 & out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5640 = out_f_rivalid_555; // @[RegisterRouter.scala:87:24] wire out_f_roready_555 = out_roready_1_409 & out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5641 = out_f_roready_555; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_555 = out_wivalid_1_409 & out_wimask_555; // @[RegisterRouter.scala:87:24] wire out_f_woready_555 = out_woready_1_409 & out_womask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5642 = ~out_rimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5643 = ~out_wimask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5644 = ~out_romask_555; // @[RegisterRouter.scala:87:24] wire _out_T_5645 = ~out_womask_555; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_469 = {hi_336, flags_0_go, _out_prepend_T_469}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5646 = out_prepend_469; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5647 = _out_T_5646; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_169 = _out_T_5647; // @[MuxLiteral.scala:49:48] wire out_rimask_556 = |_out_rimask_T_556; // @[RegisterRouter.scala:87:24] wire out_wimask_556 = &_out_wimask_T_556; // @[RegisterRouter.scala:87:24] wire out_romask_556 = |_out_romask_T_556; // @[RegisterRouter.scala:87:24] wire out_womask_556 = &_out_womask_T_556; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_556 = out_rivalid_1_410 & out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5649 = out_f_rivalid_556; // @[RegisterRouter.scala:87:24] wire out_f_roready_556 = out_roready_1_410 & out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5650 = out_f_roready_556; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_556 = out_wivalid_1_410 & out_wimask_556; // @[RegisterRouter.scala:87:24] wire out_f_woready_556 = out_woready_1_410 & out_womask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5651 = ~out_rimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5652 = ~out_wimask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5653 = ~out_romask_556; // @[RegisterRouter.scala:87:24] wire _out_T_5654 = ~out_womask_556; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5656 = _out_T_5655; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_470 = _out_T_5656; // @[RegisterRouter.scala:87:24] wire out_rimask_557 = |_out_rimask_T_557; // @[RegisterRouter.scala:87:24] wire out_wimask_557 = &_out_wimask_T_557; // @[RegisterRouter.scala:87:24] wire out_romask_557 = |_out_romask_T_557; // @[RegisterRouter.scala:87:24] wire out_womask_557 = &_out_womask_T_557; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_557 = out_rivalid_1_411 & out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5658 = out_f_rivalid_557; // @[RegisterRouter.scala:87:24] wire out_f_roready_557 = out_roready_1_411 & out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5659 = out_f_roready_557; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_557 = out_wivalid_1_411 & out_wimask_557; // @[RegisterRouter.scala:87:24] wire out_f_woready_557 = out_woready_1_411 & out_womask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5660 = ~out_rimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5661 = ~out_wimask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5662 = ~out_romask_557; // @[RegisterRouter.scala:87:24] wire _out_T_5663 = ~out_womask_557; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_470 = {hi_106, flags_0_go, _out_prepend_T_470}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5664 = out_prepend_470; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5665 = _out_T_5664; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_471 = _out_T_5665; // @[RegisterRouter.scala:87:24] wire out_rimask_558 = |_out_rimask_T_558; // @[RegisterRouter.scala:87:24] wire out_wimask_558 = &_out_wimask_T_558; // @[RegisterRouter.scala:87:24] wire out_romask_558 = |_out_romask_T_558; // @[RegisterRouter.scala:87:24] wire out_womask_558 = &_out_womask_T_558; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_558 = out_rivalid_1_412 & out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5667 = out_f_rivalid_558; // @[RegisterRouter.scala:87:24] wire out_f_roready_558 = out_roready_1_412 & out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5668 = out_f_roready_558; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_558 = out_wivalid_1_412 & out_wimask_558; // @[RegisterRouter.scala:87:24] wire out_f_woready_558 = out_woready_1_412 & out_womask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5669 = ~out_rimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5670 = ~out_wimask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5671 = ~out_romask_558; // @[RegisterRouter.scala:87:24] wire _out_T_5672 = ~out_womask_558; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_471 = {hi_107, flags_0_go, _out_prepend_T_471}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5673 = out_prepend_471; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5674 = _out_T_5673; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_472 = _out_T_5674; // @[RegisterRouter.scala:87:24] wire out_rimask_559 = |_out_rimask_T_559; // @[RegisterRouter.scala:87:24] wire out_wimask_559 = &_out_wimask_T_559; // @[RegisterRouter.scala:87:24] wire out_romask_559 = |_out_romask_T_559; // @[RegisterRouter.scala:87:24] wire out_womask_559 = &_out_womask_T_559; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_559 = out_rivalid_1_413 & out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5676 = out_f_rivalid_559; // @[RegisterRouter.scala:87:24] wire out_f_roready_559 = out_roready_1_413 & out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5677 = out_f_roready_559; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_559 = out_wivalid_1_413 & out_wimask_559; // @[RegisterRouter.scala:87:24] wire out_f_woready_559 = out_woready_1_413 & out_womask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5678 = ~out_rimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5679 = ~out_wimask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5680 = ~out_romask_559; // @[RegisterRouter.scala:87:24] wire _out_T_5681 = ~out_womask_559; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_472 = {hi_108, flags_0_go, _out_prepend_T_472}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5682 = out_prepend_472; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5683 = _out_T_5682; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_473 = _out_T_5683; // @[RegisterRouter.scala:87:24] wire out_rimask_560 = |_out_rimask_T_560; // @[RegisterRouter.scala:87:24] wire out_wimask_560 = &_out_wimask_T_560; // @[RegisterRouter.scala:87:24] wire out_romask_560 = |_out_romask_T_560; // @[RegisterRouter.scala:87:24] wire out_womask_560 = &_out_womask_T_560; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_560 = out_rivalid_1_414 & out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5685 = out_f_rivalid_560; // @[RegisterRouter.scala:87:24] wire out_f_roready_560 = out_roready_1_414 & out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5686 = out_f_roready_560; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_560 = out_wivalid_1_414 & out_wimask_560; // @[RegisterRouter.scala:87:24] wire out_f_woready_560 = out_woready_1_414 & out_womask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5687 = ~out_rimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5688 = ~out_wimask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5689 = ~out_romask_560; // @[RegisterRouter.scala:87:24] wire _out_T_5690 = ~out_womask_560; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_473 = {hi_109, flags_0_go, _out_prepend_T_473}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5691 = out_prepend_473; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5692 = _out_T_5691; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_474 = _out_T_5692; // @[RegisterRouter.scala:87:24] wire out_rimask_561 = |_out_rimask_T_561; // @[RegisterRouter.scala:87:24] wire out_wimask_561 = &_out_wimask_T_561; // @[RegisterRouter.scala:87:24] wire out_romask_561 = |_out_romask_T_561; // @[RegisterRouter.scala:87:24] wire out_womask_561 = &_out_womask_T_561; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_561 = out_rivalid_1_415 & out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5694 = out_f_rivalid_561; // @[RegisterRouter.scala:87:24] wire out_f_roready_561 = out_roready_1_415 & out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5695 = out_f_roready_561; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_561 = out_wivalid_1_415 & out_wimask_561; // @[RegisterRouter.scala:87:24] wire out_f_woready_561 = out_woready_1_415 & out_womask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5696 = ~out_rimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5697 = ~out_wimask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5698 = ~out_romask_561; // @[RegisterRouter.scala:87:24] wire _out_T_5699 = ~out_womask_561; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_474 = {hi_110, flags_0_go, _out_prepend_T_474}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5700 = out_prepend_474; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5701 = _out_T_5700; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_475 = _out_T_5701; // @[RegisterRouter.scala:87:24] wire out_rimask_562 = |_out_rimask_T_562; // @[RegisterRouter.scala:87:24] wire out_wimask_562 = &_out_wimask_T_562; // @[RegisterRouter.scala:87:24] wire out_romask_562 = |_out_romask_T_562; // @[RegisterRouter.scala:87:24] wire out_womask_562 = &_out_womask_T_562; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_562 = out_rivalid_1_416 & out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5703 = out_f_rivalid_562; // @[RegisterRouter.scala:87:24] wire out_f_roready_562 = out_roready_1_416 & out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5704 = out_f_roready_562; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_562 = out_wivalid_1_416 & out_wimask_562; // @[RegisterRouter.scala:87:24] wire out_f_woready_562 = out_woready_1_416 & out_womask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5705 = ~out_rimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5706 = ~out_wimask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5707 = ~out_romask_562; // @[RegisterRouter.scala:87:24] wire _out_T_5708 = ~out_womask_562; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_475 = {hi_111, flags_0_go, _out_prepend_T_475}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5709 = out_prepend_475; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5710 = _out_T_5709; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_476 = _out_T_5710; // @[RegisterRouter.scala:87:24] wire out_rimask_563 = |_out_rimask_T_563; // @[RegisterRouter.scala:87:24] wire out_wimask_563 = &_out_wimask_T_563; // @[RegisterRouter.scala:87:24] wire out_romask_563 = |_out_romask_T_563; // @[RegisterRouter.scala:87:24] wire out_womask_563 = &_out_womask_T_563; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_563 = out_rivalid_1_417 & out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5712 = out_f_rivalid_563; // @[RegisterRouter.scala:87:24] wire out_f_roready_563 = out_roready_1_417 & out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5713 = out_f_roready_563; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_563 = out_wivalid_1_417 & out_wimask_563; // @[RegisterRouter.scala:87:24] wire out_f_woready_563 = out_woready_1_417 & out_womask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5714 = ~out_rimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5715 = ~out_wimask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5716 = ~out_romask_563; // @[RegisterRouter.scala:87:24] wire _out_T_5717 = ~out_womask_563; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_476 = {hi_112, flags_0_go, _out_prepend_T_476}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5718 = out_prepend_476; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5719 = _out_T_5718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_141 = _out_T_5719; // @[MuxLiteral.scala:49:48] wire out_rimask_564 = |_out_rimask_T_564; // @[RegisterRouter.scala:87:24] wire out_wimask_564 = &_out_wimask_T_564; // @[RegisterRouter.scala:87:24] wire out_romask_564 = |_out_romask_T_564; // @[RegisterRouter.scala:87:24] wire out_womask_564 = &_out_womask_T_564; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_564 = out_rivalid_1_418 & out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5721 = out_f_rivalid_564; // @[RegisterRouter.scala:87:24] wire out_f_roready_564 = out_roready_1_418 & out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5722 = out_f_roready_564; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_564 = out_wivalid_1_418 & out_wimask_564; // @[RegisterRouter.scala:87:24] wire out_f_woready_564 = out_woready_1_418 & out_womask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5723 = ~out_rimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5724 = ~out_wimask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5725 = ~out_romask_564; // @[RegisterRouter.scala:87:24] wire _out_T_5726 = ~out_womask_564; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5728 = _out_T_5727; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_477 = _out_T_5728; // @[RegisterRouter.scala:87:24] wire out_rimask_565 = |_out_rimask_T_565; // @[RegisterRouter.scala:87:24] wire out_wimask_565 = &_out_wimask_T_565; // @[RegisterRouter.scala:87:24] wire out_romask_565 = |_out_romask_T_565; // @[RegisterRouter.scala:87:24] wire out_womask_565 = &_out_womask_T_565; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_565 = out_rivalid_1_419 & out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5730 = out_f_rivalid_565; // @[RegisterRouter.scala:87:24] wire out_f_roready_565 = out_roready_1_419 & out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5731 = out_f_roready_565; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_565 = out_wivalid_1_419 & out_wimask_565; // @[RegisterRouter.scala:87:24] wire out_f_woready_565 = out_woready_1_419 & out_womask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5732 = ~out_rimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5733 = ~out_wimask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5734 = ~out_romask_565; // @[RegisterRouter.scala:87:24] wire _out_T_5735 = ~out_womask_565; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_477 = {hi_778, flags_0_go, _out_prepend_T_477}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5736 = out_prepend_477; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5737 = _out_T_5736; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_478 = _out_T_5737; // @[RegisterRouter.scala:87:24] wire out_rimask_566 = |_out_rimask_T_566; // @[RegisterRouter.scala:87:24] wire out_wimask_566 = &_out_wimask_T_566; // @[RegisterRouter.scala:87:24] wire out_romask_566 = |_out_romask_T_566; // @[RegisterRouter.scala:87:24] wire out_womask_566 = &_out_womask_T_566; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_566 = out_rivalid_1_420 & out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5739 = out_f_rivalid_566; // @[RegisterRouter.scala:87:24] wire out_f_roready_566 = out_roready_1_420 & out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5740 = out_f_roready_566; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_566 = out_wivalid_1_420 & out_wimask_566; // @[RegisterRouter.scala:87:24] wire out_f_woready_566 = out_woready_1_420 & out_womask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5741 = ~out_rimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5742 = ~out_wimask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5743 = ~out_romask_566; // @[RegisterRouter.scala:87:24] wire _out_T_5744 = ~out_womask_566; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_478 = {hi_779, flags_0_go, _out_prepend_T_478}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5745 = out_prepend_478; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5746 = _out_T_5745; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_479 = _out_T_5746; // @[RegisterRouter.scala:87:24] wire out_rimask_567 = |_out_rimask_T_567; // @[RegisterRouter.scala:87:24] wire out_wimask_567 = &_out_wimask_T_567; // @[RegisterRouter.scala:87:24] wire out_romask_567 = |_out_romask_T_567; // @[RegisterRouter.scala:87:24] wire out_womask_567 = &_out_womask_T_567; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_567 = out_rivalid_1_421 & out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5748 = out_f_rivalid_567; // @[RegisterRouter.scala:87:24] wire out_f_roready_567 = out_roready_1_421 & out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5749 = out_f_roready_567; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_567 = out_wivalid_1_421 & out_wimask_567; // @[RegisterRouter.scala:87:24] wire out_f_woready_567 = out_woready_1_421 & out_womask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5750 = ~out_rimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5751 = ~out_wimask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5752 = ~out_romask_567; // @[RegisterRouter.scala:87:24] wire _out_T_5753 = ~out_womask_567; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_479 = {hi_780, flags_0_go, _out_prepend_T_479}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5754 = out_prepend_479; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5755 = _out_T_5754; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_480 = _out_T_5755; // @[RegisterRouter.scala:87:24] wire out_rimask_568 = |_out_rimask_T_568; // @[RegisterRouter.scala:87:24] wire out_wimask_568 = &_out_wimask_T_568; // @[RegisterRouter.scala:87:24] wire out_romask_568 = |_out_romask_T_568; // @[RegisterRouter.scala:87:24] wire out_womask_568 = &_out_womask_T_568; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_568 = out_rivalid_1_422 & out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5757 = out_f_rivalid_568; // @[RegisterRouter.scala:87:24] wire out_f_roready_568 = out_roready_1_422 & out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5758 = out_f_roready_568; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_568 = out_wivalid_1_422 & out_wimask_568; // @[RegisterRouter.scala:87:24] wire out_f_woready_568 = out_woready_1_422 & out_womask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5759 = ~out_rimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5760 = ~out_wimask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5761 = ~out_romask_568; // @[RegisterRouter.scala:87:24] wire _out_T_5762 = ~out_womask_568; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_480 = {hi_781, flags_0_go, _out_prepend_T_480}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5763 = out_prepend_480; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5764 = _out_T_5763; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_481 = _out_T_5764; // @[RegisterRouter.scala:87:24] wire out_rimask_569 = |_out_rimask_T_569; // @[RegisterRouter.scala:87:24] wire out_wimask_569 = &_out_wimask_T_569; // @[RegisterRouter.scala:87:24] wire out_romask_569 = |_out_romask_T_569; // @[RegisterRouter.scala:87:24] wire out_womask_569 = &_out_womask_T_569; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_569 = out_rivalid_1_423 & out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5766 = out_f_rivalid_569; // @[RegisterRouter.scala:87:24] wire out_f_roready_569 = out_roready_1_423 & out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5767 = out_f_roready_569; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_569 = out_wivalid_1_423 & out_wimask_569; // @[RegisterRouter.scala:87:24] wire out_f_woready_569 = out_woready_1_423 & out_womask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5768 = ~out_rimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5769 = ~out_wimask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5770 = ~out_romask_569; // @[RegisterRouter.scala:87:24] wire _out_T_5771 = ~out_womask_569; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_481 = {hi_782, flags_0_go, _out_prepend_T_481}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5772 = out_prepend_481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5773 = _out_T_5772; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_482 = _out_T_5773; // @[RegisterRouter.scala:87:24] wire out_rimask_570 = |_out_rimask_T_570; // @[RegisterRouter.scala:87:24] wire out_wimask_570 = &_out_wimask_T_570; // @[RegisterRouter.scala:87:24] wire out_romask_570 = |_out_romask_T_570; // @[RegisterRouter.scala:87:24] wire out_womask_570 = &_out_womask_T_570; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_570 = out_rivalid_1_424 & out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5775 = out_f_rivalid_570; // @[RegisterRouter.scala:87:24] wire out_f_roready_570 = out_roready_1_424 & out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5776 = out_f_roready_570; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_570 = out_wivalid_1_424 & out_wimask_570; // @[RegisterRouter.scala:87:24] wire out_f_woready_570 = out_woready_1_424 & out_womask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5777 = ~out_rimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5778 = ~out_wimask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5779 = ~out_romask_570; // @[RegisterRouter.scala:87:24] wire _out_T_5780 = ~out_womask_570; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_482 = {hi_783, flags_0_go, _out_prepend_T_482}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5781 = out_prepend_482; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5782 = _out_T_5781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_483 = _out_T_5782; // @[RegisterRouter.scala:87:24] wire out_rimask_571 = |_out_rimask_T_571; // @[RegisterRouter.scala:87:24] wire out_wimask_571 = &_out_wimask_T_571; // @[RegisterRouter.scala:87:24] wire out_romask_571 = |_out_romask_T_571; // @[RegisterRouter.scala:87:24] wire out_womask_571 = &_out_womask_T_571; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_571 = out_rivalid_1_425 & out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5784 = out_f_rivalid_571; // @[RegisterRouter.scala:87:24] wire out_f_roready_571 = out_roready_1_425 & out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5785 = out_f_roready_571; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_571 = out_wivalid_1_425 & out_wimask_571; // @[RegisterRouter.scala:87:24] wire out_f_woready_571 = out_woready_1_425 & out_womask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5786 = ~out_rimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5787 = ~out_wimask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5788 = ~out_romask_571; // @[RegisterRouter.scala:87:24] wire _out_T_5789 = ~out_womask_571; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_483 = {hi_784, flags_0_go, _out_prepend_T_483}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5790 = out_prepend_483; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5791 = _out_T_5790; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_225 = _out_T_5791; // @[MuxLiteral.scala:49:48] wire out_rimask_572 = |_out_rimask_T_572; // @[RegisterRouter.scala:87:24] wire out_wimask_572 = &_out_wimask_T_572; // @[RegisterRouter.scala:87:24] wire out_romask_572 = |_out_romask_T_572; // @[RegisterRouter.scala:87:24] wire out_womask_572 = &_out_womask_T_572; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_572 = out_rivalid_1_426 & out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5793 = out_f_rivalid_572; // @[RegisterRouter.scala:87:24] wire out_f_roready_572 = out_roready_1_426 & out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5794 = out_f_roready_572; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_572 = out_wivalid_1_426 & out_wimask_572; // @[RegisterRouter.scala:87:24] wire out_f_woready_572 = out_woready_1_426 & out_womask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5795 = ~out_rimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5796 = ~out_wimask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5797 = ~out_romask_572; // @[RegisterRouter.scala:87:24] wire _out_T_5798 = ~out_womask_572; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5800 = _out_T_5799; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_484 = _out_T_5800; // @[RegisterRouter.scala:87:24] wire out_rimask_573 = |_out_rimask_T_573; // @[RegisterRouter.scala:87:24] wire out_wimask_573 = &_out_wimask_T_573; // @[RegisterRouter.scala:87:24] wire out_romask_573 = |_out_romask_T_573; // @[RegisterRouter.scala:87:24] wire out_womask_573 = &_out_womask_T_573; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_573 = out_rivalid_1_427 & out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5802 = out_f_rivalid_573; // @[RegisterRouter.scala:87:24] wire out_f_roready_573 = out_roready_1_427 & out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5803 = out_f_roready_573; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_573 = out_wivalid_1_427 & out_wimask_573; // @[RegisterRouter.scala:87:24] wire out_f_woready_573 = out_woready_1_427 & out_womask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5804 = ~out_rimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5805 = ~out_wimask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5806 = ~out_romask_573; // @[RegisterRouter.scala:87:24] wire _out_T_5807 = ~out_womask_573; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_484 = {hi_522, flags_0_go, _out_prepend_T_484}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5808 = out_prepend_484; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5809 = _out_T_5808; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_485 = _out_T_5809; // @[RegisterRouter.scala:87:24] wire out_rimask_574 = |_out_rimask_T_574; // @[RegisterRouter.scala:87:24] wire out_wimask_574 = &_out_wimask_T_574; // @[RegisterRouter.scala:87:24] wire out_romask_574 = |_out_romask_T_574; // @[RegisterRouter.scala:87:24] wire out_womask_574 = &_out_womask_T_574; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_574 = out_rivalid_1_428 & out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5811 = out_f_rivalid_574; // @[RegisterRouter.scala:87:24] wire out_f_roready_574 = out_roready_1_428 & out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5812 = out_f_roready_574; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_574 = out_wivalid_1_428 & out_wimask_574; // @[RegisterRouter.scala:87:24] wire out_f_woready_574 = out_woready_1_428 & out_womask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5813 = ~out_rimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5814 = ~out_wimask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5815 = ~out_romask_574; // @[RegisterRouter.scala:87:24] wire _out_T_5816 = ~out_womask_574; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_485 = {hi_523, flags_0_go, _out_prepend_T_485}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5817 = out_prepend_485; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5818 = _out_T_5817; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_486 = _out_T_5818; // @[RegisterRouter.scala:87:24] wire out_rimask_575 = |_out_rimask_T_575; // @[RegisterRouter.scala:87:24] wire out_wimask_575 = &_out_wimask_T_575; // @[RegisterRouter.scala:87:24] wire out_romask_575 = |_out_romask_T_575; // @[RegisterRouter.scala:87:24] wire out_womask_575 = &_out_womask_T_575; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_575 = out_rivalid_1_429 & out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5820 = out_f_rivalid_575; // @[RegisterRouter.scala:87:24] wire out_f_roready_575 = out_roready_1_429 & out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5821 = out_f_roready_575; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_575 = out_wivalid_1_429 & out_wimask_575; // @[RegisterRouter.scala:87:24] wire out_f_woready_575 = out_woready_1_429 & out_womask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5822 = ~out_rimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5823 = ~out_wimask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5824 = ~out_romask_575; // @[RegisterRouter.scala:87:24] wire _out_T_5825 = ~out_womask_575; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_486 = {hi_524, flags_0_go, _out_prepend_T_486}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5826 = out_prepend_486; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5827 = _out_T_5826; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_487 = _out_T_5827; // @[RegisterRouter.scala:87:24] wire out_rimask_576 = |_out_rimask_T_576; // @[RegisterRouter.scala:87:24] wire out_wimask_576 = &_out_wimask_T_576; // @[RegisterRouter.scala:87:24] wire out_romask_576 = |_out_romask_T_576; // @[RegisterRouter.scala:87:24] wire out_womask_576 = &_out_womask_T_576; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_576 = out_rivalid_1_430 & out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5829 = out_f_rivalid_576; // @[RegisterRouter.scala:87:24] wire out_f_roready_576 = out_roready_1_430 & out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5830 = out_f_roready_576; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_576 = out_wivalid_1_430 & out_wimask_576; // @[RegisterRouter.scala:87:24] wire out_f_woready_576 = out_woready_1_430 & out_womask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5831 = ~out_rimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5832 = ~out_wimask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5833 = ~out_romask_576; // @[RegisterRouter.scala:87:24] wire _out_T_5834 = ~out_womask_576; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_487 = {hi_525, flags_0_go, _out_prepend_T_487}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5835 = out_prepend_487; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5836 = _out_T_5835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_488 = _out_T_5836; // @[RegisterRouter.scala:87:24] wire out_rimask_577 = |_out_rimask_T_577; // @[RegisterRouter.scala:87:24] wire out_wimask_577 = &_out_wimask_T_577; // @[RegisterRouter.scala:87:24] wire out_romask_577 = |_out_romask_T_577; // @[RegisterRouter.scala:87:24] wire out_womask_577 = &_out_womask_T_577; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_577 = out_rivalid_1_431 & out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5838 = out_f_rivalid_577; // @[RegisterRouter.scala:87:24] wire out_f_roready_577 = out_roready_1_431 & out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5839 = out_f_roready_577; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_577 = out_wivalid_1_431 & out_wimask_577; // @[RegisterRouter.scala:87:24] wire out_f_woready_577 = out_woready_1_431 & out_womask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5840 = ~out_rimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5841 = ~out_wimask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5842 = ~out_romask_577; // @[RegisterRouter.scala:87:24] wire _out_T_5843 = ~out_womask_577; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_488 = {hi_526, flags_0_go, _out_prepend_T_488}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5844 = out_prepend_488; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5845 = _out_T_5844; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_489 = _out_T_5845; // @[RegisterRouter.scala:87:24] wire out_rimask_578 = |_out_rimask_T_578; // @[RegisterRouter.scala:87:24] wire out_wimask_578 = &_out_wimask_T_578; // @[RegisterRouter.scala:87:24] wire out_romask_578 = |_out_romask_T_578; // @[RegisterRouter.scala:87:24] wire out_womask_578 = &_out_womask_T_578; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_578 = out_rivalid_1_432 & out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5847 = out_f_rivalid_578; // @[RegisterRouter.scala:87:24] wire out_f_roready_578 = out_roready_1_432 & out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5848 = out_f_roready_578; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_578 = out_wivalid_1_432 & out_wimask_578; // @[RegisterRouter.scala:87:24] wire out_f_woready_578 = out_woready_1_432 & out_womask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5849 = ~out_rimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5850 = ~out_wimask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5851 = ~out_romask_578; // @[RegisterRouter.scala:87:24] wire _out_T_5852 = ~out_womask_578; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_489 = {hi_527, flags_0_go, _out_prepend_T_489}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5853 = out_prepend_489; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5854 = _out_T_5853; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_490 = _out_T_5854; // @[RegisterRouter.scala:87:24] wire out_rimask_579 = |_out_rimask_T_579; // @[RegisterRouter.scala:87:24] wire out_wimask_579 = &_out_wimask_T_579; // @[RegisterRouter.scala:87:24] wire out_romask_579 = |_out_romask_T_579; // @[RegisterRouter.scala:87:24] wire out_womask_579 = &_out_womask_T_579; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_579 = out_rivalid_1_433 & out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5856 = out_f_rivalid_579; // @[RegisterRouter.scala:87:24] wire out_f_roready_579 = out_roready_1_433 & out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5857 = out_f_roready_579; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_579 = out_wivalid_1_433 & out_wimask_579; // @[RegisterRouter.scala:87:24] wire out_f_woready_579 = out_woready_1_433 & out_womask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5858 = ~out_rimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5859 = ~out_wimask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5860 = ~out_romask_579; // @[RegisterRouter.scala:87:24] wire _out_T_5861 = ~out_womask_579; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_490 = {hi_528, flags_0_go, _out_prepend_T_490}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5862 = out_prepend_490; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5863 = _out_T_5862; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_193 = _out_T_5863; // @[MuxLiteral.scala:49:48] wire out_rimask_580 = |_out_rimask_T_580; // @[RegisterRouter.scala:87:24] wire out_wimask_580 = &_out_wimask_T_580; // @[RegisterRouter.scala:87:24] wire out_romask_580 = |_out_romask_T_580; // @[RegisterRouter.scala:87:24] wire out_womask_580 = &_out_womask_T_580; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_580 = out_rivalid_1_434 & out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5865 = out_f_rivalid_580; // @[RegisterRouter.scala:87:24] wire out_f_roready_580 = out_roready_1_434 & out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5866 = out_f_roready_580; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_580 = out_wivalid_1_434 & out_wimask_580; // @[RegisterRouter.scala:87:24] wire out_f_woready_580 = out_woready_1_434 & out_womask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5867 = ~out_rimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5868 = ~out_wimask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5869 = ~out_romask_580; // @[RegisterRouter.scala:87:24] wire _out_T_5870 = ~out_womask_580; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5872 = _out_T_5871; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_491 = _out_T_5872; // @[RegisterRouter.scala:87:24] wire out_rimask_581 = |_out_rimask_T_581; // @[RegisterRouter.scala:87:24] wire out_wimask_581 = &_out_wimask_T_581; // @[RegisterRouter.scala:87:24] wire out_romask_581 = |_out_romask_T_581; // @[RegisterRouter.scala:87:24] wire out_womask_581 = &_out_womask_T_581; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_581 = out_rivalid_1_435 & out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5874 = out_f_rivalid_581; // @[RegisterRouter.scala:87:24] wire out_f_roready_581 = out_roready_1_435 & out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5875 = out_f_roready_581; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_581 = out_wivalid_1_435 & out_wimask_581; // @[RegisterRouter.scala:87:24] wire out_f_woready_581 = out_woready_1_435 & out_womask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5876 = ~out_rimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5877 = ~out_wimask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5878 = ~out_romask_581; // @[RegisterRouter.scala:87:24] wire _out_T_5879 = ~out_womask_581; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_491 = {hi_674, flags_0_go, _out_prepend_T_491}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5880 = out_prepend_491; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5881 = _out_T_5880; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_492 = _out_T_5881; // @[RegisterRouter.scala:87:24] wire out_rimask_582 = |_out_rimask_T_582; // @[RegisterRouter.scala:87:24] wire out_wimask_582 = &_out_wimask_T_582; // @[RegisterRouter.scala:87:24] wire out_romask_582 = |_out_romask_T_582; // @[RegisterRouter.scala:87:24] wire out_womask_582 = &_out_womask_T_582; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_582 = out_rivalid_1_436 & out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5883 = out_f_rivalid_582; // @[RegisterRouter.scala:87:24] wire out_f_roready_582 = out_roready_1_436 & out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5884 = out_f_roready_582; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_582 = out_wivalid_1_436 & out_wimask_582; // @[RegisterRouter.scala:87:24] wire out_f_woready_582 = out_woready_1_436 & out_womask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5885 = ~out_rimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5886 = ~out_wimask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5887 = ~out_romask_582; // @[RegisterRouter.scala:87:24] wire _out_T_5888 = ~out_womask_582; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_492 = {hi_675, flags_0_go, _out_prepend_T_492}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5889 = out_prepend_492; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5890 = _out_T_5889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_493 = _out_T_5890; // @[RegisterRouter.scala:87:24] wire out_rimask_583 = |_out_rimask_T_583; // @[RegisterRouter.scala:87:24] wire out_wimask_583 = &_out_wimask_T_583; // @[RegisterRouter.scala:87:24] wire out_romask_583 = |_out_romask_T_583; // @[RegisterRouter.scala:87:24] wire out_womask_583 = &_out_womask_T_583; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_583 = out_rivalid_1_437 & out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5892 = out_f_rivalid_583; // @[RegisterRouter.scala:87:24] wire out_f_roready_583 = out_roready_1_437 & out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5893 = out_f_roready_583; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_583 = out_wivalid_1_437 & out_wimask_583; // @[RegisterRouter.scala:87:24] wire out_f_woready_583 = out_woready_1_437 & out_womask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5894 = ~out_rimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5895 = ~out_wimask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5896 = ~out_romask_583; // @[RegisterRouter.scala:87:24] wire _out_T_5897 = ~out_womask_583; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_493 = {hi_676, flags_0_go, _out_prepend_T_493}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5898 = out_prepend_493; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5899 = _out_T_5898; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_494 = _out_T_5899; // @[RegisterRouter.scala:87:24] wire out_rimask_584 = |_out_rimask_T_584; // @[RegisterRouter.scala:87:24] wire out_wimask_584 = &_out_wimask_T_584; // @[RegisterRouter.scala:87:24] wire out_romask_584 = |_out_romask_T_584; // @[RegisterRouter.scala:87:24] wire out_womask_584 = &_out_womask_T_584; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_584 = out_rivalid_1_438 & out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5901 = out_f_rivalid_584; // @[RegisterRouter.scala:87:24] wire out_f_roready_584 = out_roready_1_438 & out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5902 = out_f_roready_584; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_584 = out_wivalid_1_438 & out_wimask_584; // @[RegisterRouter.scala:87:24] wire out_f_woready_584 = out_woready_1_438 & out_womask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5903 = ~out_rimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5904 = ~out_wimask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5905 = ~out_romask_584; // @[RegisterRouter.scala:87:24] wire _out_T_5906 = ~out_womask_584; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_494 = {hi_677, flags_0_go, _out_prepend_T_494}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5907 = out_prepend_494; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5908 = _out_T_5907; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_495 = _out_T_5908; // @[RegisterRouter.scala:87:24] wire out_rimask_585 = |_out_rimask_T_585; // @[RegisterRouter.scala:87:24] wire out_wimask_585 = &_out_wimask_T_585; // @[RegisterRouter.scala:87:24] wire out_romask_585 = |_out_romask_T_585; // @[RegisterRouter.scala:87:24] wire out_womask_585 = &_out_womask_T_585; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_585 = out_rivalid_1_439 & out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5910 = out_f_rivalid_585; // @[RegisterRouter.scala:87:24] wire out_f_roready_585 = out_roready_1_439 & out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5911 = out_f_roready_585; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_585 = out_wivalid_1_439 & out_wimask_585; // @[RegisterRouter.scala:87:24] wire out_f_woready_585 = out_woready_1_439 & out_womask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5912 = ~out_rimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5913 = ~out_wimask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5914 = ~out_romask_585; // @[RegisterRouter.scala:87:24] wire _out_T_5915 = ~out_womask_585; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_495 = {hi_678, flags_0_go, _out_prepend_T_495}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5916 = out_prepend_495; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_5917 = _out_T_5916; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_496 = _out_T_5917; // @[RegisterRouter.scala:87:24] wire out_rimask_586 = |_out_rimask_T_586; // @[RegisterRouter.scala:87:24] wire out_wimask_586 = &_out_wimask_T_586; // @[RegisterRouter.scala:87:24] wire out_romask_586 = |_out_romask_T_586; // @[RegisterRouter.scala:87:24] wire out_womask_586 = &_out_womask_T_586; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_586 = out_rivalid_1_440 & out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5919 = out_f_rivalid_586; // @[RegisterRouter.scala:87:24] wire out_f_roready_586 = out_roready_1_440 & out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5920 = out_f_roready_586; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_586 = out_wivalid_1_440 & out_wimask_586; // @[RegisterRouter.scala:87:24] wire out_f_woready_586 = out_woready_1_440 & out_womask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5921 = ~out_rimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5922 = ~out_wimask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5923 = ~out_romask_586; // @[RegisterRouter.scala:87:24] wire _out_T_5924 = ~out_womask_586; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_496 = {hi_679, flags_0_go, _out_prepend_T_496}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5925 = out_prepend_496; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_5926 = _out_T_5925; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_497 = _out_T_5926; // @[RegisterRouter.scala:87:24] wire out_rimask_587 = |_out_rimask_T_587; // @[RegisterRouter.scala:87:24] wire out_wimask_587 = &_out_wimask_T_587; // @[RegisterRouter.scala:87:24] wire out_romask_587 = |_out_romask_T_587; // @[RegisterRouter.scala:87:24] wire out_womask_587 = &_out_womask_T_587; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_587 = out_rivalid_1_441 & out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5928 = out_f_rivalid_587; // @[RegisterRouter.scala:87:24] wire out_f_roready_587 = out_roready_1_441 & out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5929 = out_f_roready_587; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_587 = out_wivalid_1_441 & out_wimask_587; // @[RegisterRouter.scala:87:24] wire out_f_woready_587 = out_woready_1_441 & out_womask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5930 = ~out_rimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5931 = ~out_wimask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5932 = ~out_romask_587; // @[RegisterRouter.scala:87:24] wire _out_T_5933 = ~out_womask_587; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_497 = {hi_680, flags_0_go, _out_prepend_T_497}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5934 = out_prepend_497; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_5935 = _out_T_5934; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_212 = _out_T_5935; // @[MuxLiteral.scala:49:48] wire [31:0] _out_rimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_588 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_843 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_588 = |_out_rimask_T_588; // @[RegisterRouter.scala:87:24] wire out_wimask_588 = &_out_wimask_T_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_588 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_843 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_588 = |_out_romask_T_588; // @[RegisterRouter.scala:87:24] wire out_womask_588 = &_out_womask_T_588; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_588 = out_rivalid_1_442 & out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5937 = out_f_rivalid_588; // @[RegisterRouter.scala:87:24] wire out_f_roready_588 = out_roready_1_442 & out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5938 = out_f_roready_588; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_588 = out_wivalid_1_442 & out_wimask_588; // @[RegisterRouter.scala:87:24] wire out_f_woready_588 = out_woready_1_442 & out_womask_588; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5936 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8279 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24] wire _out_T_5939 = ~out_rimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5940 = ~out_wimask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5941 = ~out_romask_588; // @[RegisterRouter.scala:87:24] wire _out_T_5942 = ~out_womask_588; // @[RegisterRouter.scala:87:24] wire out_rimask_589 = |_out_rimask_T_589; // @[RegisterRouter.scala:87:24] wire out_wimask_589 = &_out_wimask_T_589; // @[RegisterRouter.scala:87:24] wire out_romask_589 = |_out_romask_T_589; // @[RegisterRouter.scala:87:24] wire out_womask_589 = &_out_womask_T_589; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_589 = out_rivalid_1_443 & out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5946 = out_f_rivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_roready_589 = out_roready_1_443 & out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5947 = out_f_roready_589; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_589 = out_wivalid_1_443 & out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5948 = out_f_wivalid_589; // @[RegisterRouter.scala:87:24] wire out_f_woready_589 = out_woready_1_443 & out_womask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5949 = out_f_woready_589; // @[RegisterRouter.scala:87:24] wire _out_T_5950 = ~out_rimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5951 = ~out_wimask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5952 = ~out_romask_589; // @[RegisterRouter.scala:87:24] wire _out_T_5953 = ~out_womask_589; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_5955 = _out_T_5954; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_498 = _out_T_5955; // @[RegisterRouter.scala:87:24] wire out_rimask_590 = |_out_rimask_T_590; // @[RegisterRouter.scala:87:24] wire out_wimask_590 = &_out_wimask_T_590; // @[RegisterRouter.scala:87:24] wire out_romask_590 = |_out_romask_T_590; // @[RegisterRouter.scala:87:24] wire out_womask_590 = &_out_womask_T_590; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_590 = out_rivalid_1_444 & out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5957 = out_f_rivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_roready_590 = out_roready_1_444 & out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5958 = out_f_roready_590; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_590 = out_wivalid_1_444 & out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5959 = out_f_wivalid_590; // @[RegisterRouter.scala:87:24] wire out_f_woready_590 = out_woready_1_444 & out_womask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5960 = out_f_woready_590; // @[RegisterRouter.scala:87:24] wire _out_T_5961 = ~out_rimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5962 = ~out_wimask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5963 = ~out_romask_590; // @[RegisterRouter.scala:87:24] wire _out_T_5964 = ~out_womask_590; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_498 = {programBufferMem_41, _out_prepend_T_498}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5965 = out_prepend_498; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_5966 = _out_T_5965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_499 = _out_T_5966; // @[RegisterRouter.scala:87:24] wire out_rimask_591 = |_out_rimask_T_591; // @[RegisterRouter.scala:87:24] wire out_wimask_591 = &_out_wimask_T_591; // @[RegisterRouter.scala:87:24] wire out_romask_591 = |_out_romask_T_591; // @[RegisterRouter.scala:87:24] wire out_womask_591 = &_out_womask_T_591; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_591 = out_rivalid_1_445 & out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5968 = out_f_rivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_roready_591 = out_roready_1_445 & out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5969 = out_f_roready_591; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_591 = out_wivalid_1_445 & out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5970 = out_f_wivalid_591; // @[RegisterRouter.scala:87:24] wire out_f_woready_591 = out_woready_1_445 & out_womask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5971 = out_f_woready_591; // @[RegisterRouter.scala:87:24] wire _out_T_5972 = ~out_rimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5973 = ~out_wimask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5974 = ~out_romask_591; // @[RegisterRouter.scala:87:24] wire _out_T_5975 = ~out_womask_591; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_499 = {programBufferMem_42, _out_prepend_T_499}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5976 = out_prepend_499; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_5977 = _out_T_5976; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_500 = _out_T_5977; // @[RegisterRouter.scala:87:24] wire out_rimask_592 = |_out_rimask_T_592; // @[RegisterRouter.scala:87:24] wire out_wimask_592 = &_out_wimask_T_592; // @[RegisterRouter.scala:87:24] wire out_romask_592 = |_out_romask_T_592; // @[RegisterRouter.scala:87:24] wire out_womask_592 = &_out_womask_T_592; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_592 = out_rivalid_1_446 & out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5979 = out_f_rivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_roready_592 = out_roready_1_446 & out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5980 = out_f_roready_592; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_592 = out_wivalid_1_446 & out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5981 = out_f_wivalid_592; // @[RegisterRouter.scala:87:24] wire out_f_woready_592 = out_woready_1_446 & out_womask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5982 = out_f_woready_592; // @[RegisterRouter.scala:87:24] wire _out_T_5983 = ~out_rimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5984 = ~out_wimask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5985 = ~out_romask_592; // @[RegisterRouter.scala:87:24] wire _out_T_5986 = ~out_womask_592; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_500 = {programBufferMem_43, _out_prepend_T_500}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5987 = out_prepend_500; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_5988 = _out_T_5987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_501 = _out_T_5988; // @[RegisterRouter.scala:87:24] wire out_rimask_593 = |_out_rimask_T_593; // @[RegisterRouter.scala:87:24] wire out_wimask_593 = &_out_wimask_T_593; // @[RegisterRouter.scala:87:24] wire out_romask_593 = |_out_romask_T_593; // @[RegisterRouter.scala:87:24] wire out_womask_593 = &_out_womask_T_593; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_593 = out_rivalid_1_447 & out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5990 = out_f_rivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_roready_593 = out_roready_1_447 & out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5991 = out_f_roready_593; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_593 = out_wivalid_1_447 & out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5992 = out_f_wivalid_593; // @[RegisterRouter.scala:87:24] wire out_f_woready_593 = out_woready_1_447 & out_womask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5993 = out_f_woready_593; // @[RegisterRouter.scala:87:24] wire _out_T_5994 = ~out_rimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5995 = ~out_wimask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5996 = ~out_romask_593; // @[RegisterRouter.scala:87:24] wire _out_T_5997 = ~out_womask_593; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_501 = {programBufferMem_44, _out_prepend_T_501}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5998 = out_prepend_501; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_5999 = _out_T_5998; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_502 = _out_T_5999; // @[RegisterRouter.scala:87:24] wire out_rimask_594 = |_out_rimask_T_594; // @[RegisterRouter.scala:87:24] wire out_wimask_594 = &_out_wimask_T_594; // @[RegisterRouter.scala:87:24] wire out_romask_594 = |_out_romask_T_594; // @[RegisterRouter.scala:87:24] wire out_womask_594 = &_out_womask_T_594; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_594 = out_rivalid_1_448 & out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6001 = out_f_rivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_roready_594 = out_roready_1_448 & out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6002 = out_f_roready_594; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_594 = out_wivalid_1_448 & out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6003 = out_f_wivalid_594; // @[RegisterRouter.scala:87:24] wire out_f_woready_594 = out_woready_1_448 & out_womask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6004 = out_f_woready_594; // @[RegisterRouter.scala:87:24] wire _out_T_6005 = ~out_rimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6006 = ~out_wimask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6007 = ~out_romask_594; // @[RegisterRouter.scala:87:24] wire _out_T_6008 = ~out_womask_594; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_502 = {programBufferMem_45, _out_prepend_T_502}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6009 = out_prepend_502; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6010 = _out_T_6009; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_503 = _out_T_6010; // @[RegisterRouter.scala:87:24] wire out_rimask_595 = |_out_rimask_T_595; // @[RegisterRouter.scala:87:24] wire out_wimask_595 = &_out_wimask_T_595; // @[RegisterRouter.scala:87:24] wire out_romask_595 = |_out_romask_T_595; // @[RegisterRouter.scala:87:24] wire out_womask_595 = &_out_womask_T_595; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_595 = out_rivalid_1_449 & out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6012 = out_f_rivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_roready_595 = out_roready_1_449 & out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6013 = out_f_roready_595; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_595 = out_wivalid_1_449 & out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6014 = out_f_wivalid_595; // @[RegisterRouter.scala:87:24] wire out_f_woready_595 = out_woready_1_449 & out_womask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6015 = out_f_woready_595; // @[RegisterRouter.scala:87:24] wire _out_T_6016 = ~out_rimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6017 = ~out_wimask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6018 = ~out_romask_595; // @[RegisterRouter.scala:87:24] wire _out_T_6019 = ~out_womask_595; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_503 = {programBufferMem_46, _out_prepend_T_503}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6020 = out_prepend_503; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6021 = _out_T_6020; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_504 = _out_T_6021; // @[RegisterRouter.scala:87:24] wire out_rimask_596 = |_out_rimask_T_596; // @[RegisterRouter.scala:87:24] wire out_wimask_596 = &_out_wimask_T_596; // @[RegisterRouter.scala:87:24] wire out_romask_596 = |_out_romask_T_596; // @[RegisterRouter.scala:87:24] wire out_womask_596 = &_out_womask_T_596; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_596 = out_rivalid_1_450 & out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6023 = out_f_rivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_roready_596 = out_roready_1_450 & out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6024 = out_f_roready_596; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_596 = out_wivalid_1_450 & out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6025 = out_f_wivalid_596; // @[RegisterRouter.scala:87:24] wire out_f_woready_596 = out_woready_1_450 & out_womask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6026 = out_f_woready_596; // @[RegisterRouter.scala:87:24] wire _out_T_6027 = ~out_rimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6028 = ~out_wimask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6029 = ~out_romask_596; // @[RegisterRouter.scala:87:24] wire _out_T_6030 = ~out_womask_596; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_504 = {programBufferMem_47, _out_prepend_T_504}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6031 = out_prepend_504; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6032 = _out_T_6031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_109 = _out_T_6032; // @[MuxLiteral.scala:49:48] wire out_rimask_597 = |_out_rimask_T_597; // @[RegisterRouter.scala:87:24] wire out_wimask_597 = &_out_wimask_T_597; // @[RegisterRouter.scala:87:24] wire out_romask_597 = |_out_romask_T_597; // @[RegisterRouter.scala:87:24] wire out_womask_597 = &_out_womask_T_597; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_597 = out_rivalid_1_451 & out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6034 = out_f_rivalid_597; // @[RegisterRouter.scala:87:24] wire out_f_roready_597 = out_roready_1_451 & out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6035 = out_f_roready_597; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_597 = out_wivalid_1_451 & out_wimask_597; // @[RegisterRouter.scala:87:24] wire out_f_woready_597 = out_woready_1_451 & out_womask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6036 = ~out_rimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6037 = ~out_wimask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6038 = ~out_romask_597; // @[RegisterRouter.scala:87:24] wire _out_T_6039 = ~out_womask_597; // @[RegisterRouter.scala:87:24] wire out_rimask_598 = |_out_rimask_T_598; // @[RegisterRouter.scala:87:24] wire out_wimask_598 = &_out_wimask_T_598; // @[RegisterRouter.scala:87:24] wire out_romask_598 = |_out_romask_T_598; // @[RegisterRouter.scala:87:24] wire out_womask_598 = &_out_womask_T_598; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_598 = out_rivalid_1_452 & out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6043 = out_f_rivalid_598; // @[RegisterRouter.scala:87:24] wire out_f_roready_598 = out_roready_1_452 & out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6044 = out_f_roready_598; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_598 = out_wivalid_1_452 & out_wimask_598; // @[RegisterRouter.scala:87:24] wire out_f_woready_598 = out_woready_1_452 & out_womask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6045 = ~out_rimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6046 = ~out_wimask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6047 = ~out_romask_598; // @[RegisterRouter.scala:87:24] wire _out_T_6048 = ~out_womask_598; // @[RegisterRouter.scala:87:24] wire out_rimask_599 = |_out_rimask_T_599; // @[RegisterRouter.scala:87:24] wire out_wimask_599 = &_out_wimask_T_599; // @[RegisterRouter.scala:87:24] wire out_romask_599 = |_out_romask_T_599; // @[RegisterRouter.scala:87:24] wire out_womask_599 = &_out_womask_T_599; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_599 = out_rivalid_1_453 & out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6052 = out_f_rivalid_599; // @[RegisterRouter.scala:87:24] wire out_f_roready_599 = out_roready_1_453 & out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6053 = out_f_roready_599; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_599 = out_wivalid_1_453 & out_wimask_599; // @[RegisterRouter.scala:87:24] wire out_f_woready_599 = out_woready_1_453 & out_womask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6054 = ~out_rimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6055 = ~out_wimask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6056 = ~out_romask_599; // @[RegisterRouter.scala:87:24] wire _out_T_6057 = ~out_womask_599; // @[RegisterRouter.scala:87:24] wire out_rimask_600 = |_out_rimask_T_600; // @[RegisterRouter.scala:87:24] wire out_wimask_600 = &_out_wimask_T_600; // @[RegisterRouter.scala:87:24] wire out_romask_600 = |_out_romask_T_600; // @[RegisterRouter.scala:87:24] wire out_womask_600 = &_out_womask_T_600; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_600 = out_rivalid_1_454 & out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6061 = out_f_rivalid_600; // @[RegisterRouter.scala:87:24] wire out_f_roready_600 = out_roready_1_454 & out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6062 = out_f_roready_600; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_600 = out_wivalid_1_454 & out_wimask_600; // @[RegisterRouter.scala:87:24] wire out_f_woready_600 = out_woready_1_454 & out_womask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6063 = ~out_rimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6064 = ~out_wimask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6065 = ~out_romask_600; // @[RegisterRouter.scala:87:24] wire _out_T_6066 = ~out_womask_600; // @[RegisterRouter.scala:87:24] wire out_rimask_601 = |_out_rimask_T_601; // @[RegisterRouter.scala:87:24] wire out_wimask_601 = &_out_wimask_T_601; // @[RegisterRouter.scala:87:24] wire out_romask_601 = |_out_romask_T_601; // @[RegisterRouter.scala:87:24] wire out_womask_601 = &_out_womask_T_601; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_601 = out_rivalid_1_455 & out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6070 = out_f_rivalid_601; // @[RegisterRouter.scala:87:24] wire out_f_roready_601 = out_roready_1_455 & out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6071 = out_f_roready_601; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_601 = out_wivalid_1_455 & out_wimask_601; // @[RegisterRouter.scala:87:24] wire out_f_woready_601 = out_woready_1_455 & out_womask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6072 = ~out_rimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6073 = ~out_wimask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6074 = ~out_romask_601; // @[RegisterRouter.scala:87:24] wire _out_T_6075 = ~out_womask_601; // @[RegisterRouter.scala:87:24] wire out_rimask_602 = |_out_rimask_T_602; // @[RegisterRouter.scala:87:24] wire out_wimask_602 = &_out_wimask_T_602; // @[RegisterRouter.scala:87:24] wire out_romask_602 = |_out_romask_T_602; // @[RegisterRouter.scala:87:24] wire out_womask_602 = &_out_womask_T_602; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_602 = out_rivalid_1_456 & out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6079 = out_f_rivalid_602; // @[RegisterRouter.scala:87:24] wire out_f_roready_602 = out_roready_1_456 & out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6080 = out_f_roready_602; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_602 = out_wivalid_1_456 & out_wimask_602; // @[RegisterRouter.scala:87:24] wire out_f_woready_602 = out_woready_1_456 & out_womask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6081 = ~out_rimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6082 = ~out_wimask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6083 = ~out_romask_602; // @[RegisterRouter.scala:87:24] wire _out_T_6084 = ~out_womask_602; // @[RegisterRouter.scala:87:24] wire out_rimask_603 = |_out_rimask_T_603; // @[RegisterRouter.scala:87:24] wire out_wimask_603 = &_out_wimask_T_603; // @[RegisterRouter.scala:87:24] wire out_romask_603 = |_out_romask_T_603; // @[RegisterRouter.scala:87:24] wire out_womask_603 = &_out_womask_T_603; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_603 = out_rivalid_1_457 & out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6088 = out_f_rivalid_603; // @[RegisterRouter.scala:87:24] wire out_f_roready_603 = out_roready_1_457 & out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6089 = out_f_roready_603; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_603 = out_wivalid_1_457 & out_wimask_603; // @[RegisterRouter.scala:87:24] wire out_f_woready_603 = out_woready_1_457 & out_womask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6090 = ~out_rimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6091 = ~out_wimask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6092 = ~out_romask_603; // @[RegisterRouter.scala:87:24] wire _out_T_6093 = ~out_womask_603; // @[RegisterRouter.scala:87:24] wire out_rimask_604 = |_out_rimask_T_604; // @[RegisterRouter.scala:87:24] wire out_wimask_604 = &_out_wimask_T_604; // @[RegisterRouter.scala:87:24] wire out_romask_604 = |_out_romask_T_604; // @[RegisterRouter.scala:87:24] wire out_womask_604 = &_out_womask_T_604; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_604 = out_rivalid_1_458 & out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6097 = out_f_rivalid_604; // @[RegisterRouter.scala:87:24] wire out_f_roready_604 = out_roready_1_458 & out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6098 = out_f_roready_604; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_604 = out_wivalid_1_458 & out_wimask_604; // @[RegisterRouter.scala:87:24] wire out_f_woready_604 = out_woready_1_458 & out_womask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6099 = ~out_rimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6100 = ~out_wimask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6101 = ~out_romask_604; // @[RegisterRouter.scala:87:24] wire _out_T_6102 = ~out_womask_604; // @[RegisterRouter.scala:87:24] wire out_rimask_605 = |_out_rimask_T_605; // @[RegisterRouter.scala:87:24] wire out_wimask_605 = &_out_wimask_T_605; // @[RegisterRouter.scala:87:24] wire out_romask_605 = |_out_romask_T_605; // @[RegisterRouter.scala:87:24] wire out_womask_605 = &_out_womask_T_605; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_605 = out_rivalid_1_459 & out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6106 = out_f_rivalid_605; // @[RegisterRouter.scala:87:24] wire out_f_roready_605 = out_roready_1_459 & out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6107 = out_f_roready_605; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_605 = out_wivalid_1_459 & out_wimask_605; // @[RegisterRouter.scala:87:24] wire out_f_woready_605 = out_woready_1_459 & out_womask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6108 = ~out_rimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6109 = ~out_wimask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6110 = ~out_romask_605; // @[RegisterRouter.scala:87:24] wire _out_T_6111 = ~out_womask_605; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6113 = _out_T_6112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_512 = _out_T_6113; // @[RegisterRouter.scala:87:24] wire out_rimask_606 = |_out_rimask_T_606; // @[RegisterRouter.scala:87:24] wire out_wimask_606 = &_out_wimask_T_606; // @[RegisterRouter.scala:87:24] wire out_romask_606 = |_out_romask_T_606; // @[RegisterRouter.scala:87:24] wire out_womask_606 = &_out_womask_T_606; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_606 = out_rivalid_1_460 & out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6115 = out_f_rivalid_606; // @[RegisterRouter.scala:87:24] wire out_f_roready_606 = out_roready_1_460 & out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6116 = out_f_roready_606; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_606 = out_wivalid_1_460 & out_wimask_606; // @[RegisterRouter.scala:87:24] wire out_f_woready_606 = out_woready_1_460 & out_womask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6117 = ~out_rimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6118 = ~out_wimask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6119 = ~out_romask_606; // @[RegisterRouter.scala:87:24] wire _out_T_6120 = ~out_womask_606; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_512 = {hi_362, flags_0_go, _out_prepend_T_512}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6121 = out_prepend_512; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6122 = _out_T_6121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_513 = _out_T_6122; // @[RegisterRouter.scala:87:24] wire out_rimask_607 = |_out_rimask_T_607; // @[RegisterRouter.scala:87:24] wire out_wimask_607 = &_out_wimask_T_607; // @[RegisterRouter.scala:87:24] wire out_romask_607 = |_out_romask_T_607; // @[RegisterRouter.scala:87:24] wire out_womask_607 = &_out_womask_T_607; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_607 = out_rivalid_1_461 & out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6124 = out_f_rivalid_607; // @[RegisterRouter.scala:87:24] wire out_f_roready_607 = out_roready_1_461 & out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6125 = out_f_roready_607; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_607 = out_wivalid_1_461 & out_wimask_607; // @[RegisterRouter.scala:87:24] wire out_f_woready_607 = out_woready_1_461 & out_womask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6126 = ~out_rimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6127 = ~out_wimask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6128 = ~out_romask_607; // @[RegisterRouter.scala:87:24] wire _out_T_6129 = ~out_womask_607; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_513 = {hi_363, flags_0_go, _out_prepend_T_513}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6130 = out_prepend_513; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6131 = _out_T_6130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_514 = _out_T_6131; // @[RegisterRouter.scala:87:24] wire out_rimask_608 = |_out_rimask_T_608; // @[RegisterRouter.scala:87:24] wire out_wimask_608 = &_out_wimask_T_608; // @[RegisterRouter.scala:87:24] wire out_romask_608 = |_out_romask_T_608; // @[RegisterRouter.scala:87:24] wire out_womask_608 = &_out_womask_T_608; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_608 = out_rivalid_1_462 & out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6133 = out_f_rivalid_608; // @[RegisterRouter.scala:87:24] wire out_f_roready_608 = out_roready_1_462 & out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6134 = out_f_roready_608; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_608 = out_wivalid_1_462 & out_wimask_608; // @[RegisterRouter.scala:87:24] wire out_f_woready_608 = out_woready_1_462 & out_womask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6135 = ~out_rimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6136 = ~out_wimask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6137 = ~out_romask_608; // @[RegisterRouter.scala:87:24] wire _out_T_6138 = ~out_womask_608; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_514 = {hi_364, flags_0_go, _out_prepend_T_514}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6139 = out_prepend_514; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6140 = _out_T_6139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_515 = _out_T_6140; // @[RegisterRouter.scala:87:24] wire out_rimask_609 = |_out_rimask_T_609; // @[RegisterRouter.scala:87:24] wire out_wimask_609 = &_out_wimask_T_609; // @[RegisterRouter.scala:87:24] wire out_romask_609 = |_out_romask_T_609; // @[RegisterRouter.scala:87:24] wire out_womask_609 = &_out_womask_T_609; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_609 = out_rivalid_1_463 & out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6142 = out_f_rivalid_609; // @[RegisterRouter.scala:87:24] wire out_f_roready_609 = out_roready_1_463 & out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6143 = out_f_roready_609; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_609 = out_wivalid_1_463 & out_wimask_609; // @[RegisterRouter.scala:87:24] wire out_f_woready_609 = out_woready_1_463 & out_womask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6144 = ~out_rimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6145 = ~out_wimask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6146 = ~out_romask_609; // @[RegisterRouter.scala:87:24] wire _out_T_6147 = ~out_womask_609; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_515 = {hi_365, flags_0_go, _out_prepend_T_515}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6148 = out_prepend_515; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6149 = _out_T_6148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_516 = _out_T_6149; // @[RegisterRouter.scala:87:24] wire out_rimask_610 = |_out_rimask_T_610; // @[RegisterRouter.scala:87:24] wire out_wimask_610 = &_out_wimask_T_610; // @[RegisterRouter.scala:87:24] wire out_romask_610 = |_out_romask_T_610; // @[RegisterRouter.scala:87:24] wire out_womask_610 = &_out_womask_T_610; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_610 = out_rivalid_1_464 & out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6151 = out_f_rivalid_610; // @[RegisterRouter.scala:87:24] wire out_f_roready_610 = out_roready_1_464 & out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6152 = out_f_roready_610; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_610 = out_wivalid_1_464 & out_wimask_610; // @[RegisterRouter.scala:87:24] wire out_f_woready_610 = out_woready_1_464 & out_womask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6153 = ~out_rimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6154 = ~out_wimask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6155 = ~out_romask_610; // @[RegisterRouter.scala:87:24] wire _out_T_6156 = ~out_womask_610; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_516 = {hi_366, flags_0_go, _out_prepend_T_516}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6157 = out_prepend_516; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6158 = _out_T_6157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_517 = _out_T_6158; // @[RegisterRouter.scala:87:24] wire out_rimask_611 = |_out_rimask_T_611; // @[RegisterRouter.scala:87:24] wire out_wimask_611 = &_out_wimask_T_611; // @[RegisterRouter.scala:87:24] wire out_romask_611 = |_out_romask_T_611; // @[RegisterRouter.scala:87:24] wire out_womask_611 = &_out_womask_T_611; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_611 = out_rivalid_1_465 & out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6160 = out_f_rivalid_611; // @[RegisterRouter.scala:87:24] wire out_f_roready_611 = out_roready_1_465 & out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6161 = out_f_roready_611; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_611 = out_wivalid_1_465 & out_wimask_611; // @[RegisterRouter.scala:87:24] wire out_f_woready_611 = out_woready_1_465 & out_womask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6162 = ~out_rimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6163 = ~out_wimask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6164 = ~out_romask_611; // @[RegisterRouter.scala:87:24] wire _out_T_6165 = ~out_womask_611; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_517 = {hi_367, flags_0_go, _out_prepend_T_517}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6166 = out_prepend_517; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6167 = _out_T_6166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_518 = _out_T_6167; // @[RegisterRouter.scala:87:24] wire out_rimask_612 = |_out_rimask_T_612; // @[RegisterRouter.scala:87:24] wire out_wimask_612 = &_out_wimask_T_612; // @[RegisterRouter.scala:87:24] wire out_romask_612 = |_out_romask_T_612; // @[RegisterRouter.scala:87:24] wire out_womask_612 = &_out_womask_T_612; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_612 = out_rivalid_1_466 & out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6169 = out_f_rivalid_612; // @[RegisterRouter.scala:87:24] wire out_f_roready_612 = out_roready_1_466 & out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6170 = out_f_roready_612; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_612 = out_wivalid_1_466 & out_wimask_612; // @[RegisterRouter.scala:87:24] wire out_f_woready_612 = out_woready_1_466 & out_womask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6171 = ~out_rimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6172 = ~out_wimask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6173 = ~out_romask_612; // @[RegisterRouter.scala:87:24] wire _out_T_6174 = ~out_womask_612; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_518 = {hi_368, flags_0_go, _out_prepend_T_518}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6175 = out_prepend_518; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6176 = _out_T_6175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_173 = _out_T_6176; // @[MuxLiteral.scala:49:48] wire out_rimask_613 = |_out_rimask_T_613; // @[RegisterRouter.scala:87:24] wire out_wimask_613 = &_out_wimask_T_613; // @[RegisterRouter.scala:87:24] wire out_romask_613 = |_out_romask_T_613; // @[RegisterRouter.scala:87:24] wire out_womask_613 = &_out_womask_T_613; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_613 = out_rivalid_1_467 & out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6178 = out_f_rivalid_613; // @[RegisterRouter.scala:87:24] wire out_f_roready_613 = out_roready_1_467 & out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6179 = out_f_roready_613; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_613 = out_wivalid_1_467 & out_wimask_613; // @[RegisterRouter.scala:87:24] wire out_f_woready_613 = out_woready_1_467 & out_womask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6180 = ~out_rimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6181 = ~out_wimask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6182 = ~out_romask_613; // @[RegisterRouter.scala:87:24] wire _out_T_6183 = ~out_womask_613; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6185 = _out_T_6184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_519 = _out_T_6185; // @[RegisterRouter.scala:87:24] wire out_rimask_614 = |_out_rimask_T_614; // @[RegisterRouter.scala:87:24] wire out_wimask_614 = &_out_wimask_T_614; // @[RegisterRouter.scala:87:24] wire out_romask_614 = |_out_romask_T_614; // @[RegisterRouter.scala:87:24] wire out_womask_614 = &_out_womask_T_614; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_614 = out_rivalid_1_468 & out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6187 = out_f_rivalid_614; // @[RegisterRouter.scala:87:24] wire out_f_roready_614 = out_roready_1_468 & out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6188 = out_f_roready_614; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_614 = out_wivalid_1_468 & out_wimask_614; // @[RegisterRouter.scala:87:24] wire out_f_woready_614 = out_woready_1_468 & out_womask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6189 = ~out_rimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6190 = ~out_wimask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6191 = ~out_romask_614; // @[RegisterRouter.scala:87:24] wire _out_T_6192 = ~out_womask_614; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_519 = {hi_10, flags_0_go, _out_prepend_T_519}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6193 = out_prepend_519; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6194 = _out_T_6193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_520 = _out_T_6194; // @[RegisterRouter.scala:87:24] wire out_rimask_615 = |_out_rimask_T_615; // @[RegisterRouter.scala:87:24] wire out_wimask_615 = &_out_wimask_T_615; // @[RegisterRouter.scala:87:24] wire out_romask_615 = |_out_romask_T_615; // @[RegisterRouter.scala:87:24] wire out_womask_615 = &_out_womask_T_615; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_615 = out_rivalid_1_469 & out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6196 = out_f_rivalid_615; // @[RegisterRouter.scala:87:24] wire out_f_roready_615 = out_roready_1_469 & out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6197 = out_f_roready_615; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_615 = out_wivalid_1_469 & out_wimask_615; // @[RegisterRouter.scala:87:24] wire out_f_woready_615 = out_woready_1_469 & out_womask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6198 = ~out_rimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6199 = ~out_wimask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6200 = ~out_romask_615; // @[RegisterRouter.scala:87:24] wire _out_T_6201 = ~out_womask_615; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_520 = {hi_11, flags_0_go, _out_prepend_T_520}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6202 = out_prepend_520; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6203 = _out_T_6202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_521 = _out_T_6203; // @[RegisterRouter.scala:87:24] wire out_rimask_616 = |_out_rimask_T_616; // @[RegisterRouter.scala:87:24] wire out_wimask_616 = &_out_wimask_T_616; // @[RegisterRouter.scala:87:24] wire out_romask_616 = |_out_romask_T_616; // @[RegisterRouter.scala:87:24] wire out_womask_616 = &_out_womask_T_616; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_616 = out_rivalid_1_470 & out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6205 = out_f_rivalid_616; // @[RegisterRouter.scala:87:24] wire out_f_roready_616 = out_roready_1_470 & out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6206 = out_f_roready_616; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_616 = out_wivalid_1_470 & out_wimask_616; // @[RegisterRouter.scala:87:24] wire out_f_woready_616 = out_woready_1_470 & out_womask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6207 = ~out_rimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6208 = ~out_wimask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6209 = ~out_romask_616; // @[RegisterRouter.scala:87:24] wire _out_T_6210 = ~out_womask_616; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_521 = {hi_12, flags_0_go, _out_prepend_T_521}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6211 = out_prepend_521; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6212 = _out_T_6211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_522 = _out_T_6212; // @[RegisterRouter.scala:87:24] wire out_rimask_617 = |_out_rimask_T_617; // @[RegisterRouter.scala:87:24] wire out_wimask_617 = &_out_wimask_T_617; // @[RegisterRouter.scala:87:24] wire out_romask_617 = |_out_romask_T_617; // @[RegisterRouter.scala:87:24] wire out_womask_617 = &_out_womask_T_617; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_617 = out_rivalid_1_471 & out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6214 = out_f_rivalid_617; // @[RegisterRouter.scala:87:24] wire out_f_roready_617 = out_roready_1_471 & out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6215 = out_f_roready_617; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_617 = out_wivalid_1_471 & out_wimask_617; // @[RegisterRouter.scala:87:24] wire out_f_woready_617 = out_woready_1_471 & out_womask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6216 = ~out_rimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6217 = ~out_wimask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6218 = ~out_romask_617; // @[RegisterRouter.scala:87:24] wire _out_T_6219 = ~out_womask_617; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_522 = {hi_13, flags_0_go, _out_prepend_T_522}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6220 = out_prepend_522; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6221 = _out_T_6220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_523 = _out_T_6221; // @[RegisterRouter.scala:87:24] wire out_rimask_618 = |_out_rimask_T_618; // @[RegisterRouter.scala:87:24] wire out_wimask_618 = &_out_wimask_T_618; // @[RegisterRouter.scala:87:24] wire out_romask_618 = |_out_romask_T_618; // @[RegisterRouter.scala:87:24] wire out_womask_618 = &_out_womask_T_618; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_618 = out_rivalid_1_472 & out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6223 = out_f_rivalid_618; // @[RegisterRouter.scala:87:24] wire out_f_roready_618 = out_roready_1_472 & out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6224 = out_f_roready_618; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_618 = out_wivalid_1_472 & out_wimask_618; // @[RegisterRouter.scala:87:24] wire out_f_woready_618 = out_woready_1_472 & out_womask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6225 = ~out_rimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6226 = ~out_wimask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6227 = ~out_romask_618; // @[RegisterRouter.scala:87:24] wire _out_T_6228 = ~out_womask_618; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_523 = {hi_14, flags_0_go, _out_prepend_T_523}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6229 = out_prepend_523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6230 = _out_T_6229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_524 = _out_T_6230; // @[RegisterRouter.scala:87:24] wire out_rimask_619 = |_out_rimask_T_619; // @[RegisterRouter.scala:87:24] wire out_wimask_619 = &_out_wimask_T_619; // @[RegisterRouter.scala:87:24] wire out_romask_619 = |_out_romask_T_619; // @[RegisterRouter.scala:87:24] wire out_womask_619 = &_out_womask_T_619; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_619 = out_rivalid_1_473 & out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6232 = out_f_rivalid_619; // @[RegisterRouter.scala:87:24] wire out_f_roready_619 = out_roready_1_473 & out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6233 = out_f_roready_619; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_619 = out_wivalid_1_473 & out_wimask_619; // @[RegisterRouter.scala:87:24] wire out_f_woready_619 = out_woready_1_473 & out_womask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6234 = ~out_rimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6235 = ~out_wimask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6236 = ~out_romask_619; // @[RegisterRouter.scala:87:24] wire _out_T_6237 = ~out_womask_619; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_524 = {hi_15, flags_0_go, _out_prepend_T_524}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6238 = out_prepend_524; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6239 = _out_T_6238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_525 = _out_T_6239; // @[RegisterRouter.scala:87:24] wire out_rimask_620 = |_out_rimask_T_620; // @[RegisterRouter.scala:87:24] wire out_wimask_620 = &_out_wimask_T_620; // @[RegisterRouter.scala:87:24] wire out_romask_620 = |_out_romask_T_620; // @[RegisterRouter.scala:87:24] wire out_womask_620 = &_out_womask_T_620; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_620 = out_rivalid_1_474 & out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6241 = out_f_rivalid_620; // @[RegisterRouter.scala:87:24] wire out_f_roready_620 = out_roready_1_474 & out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6242 = out_f_roready_620; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_620 = out_wivalid_1_474 & out_wimask_620; // @[RegisterRouter.scala:87:24] wire out_f_woready_620 = out_woready_1_474 & out_womask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6243 = ~out_rimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6244 = ~out_wimask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6245 = ~out_romask_620; // @[RegisterRouter.scala:87:24] wire _out_T_6246 = ~out_womask_620; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_525 = {hi_16, flags_0_go, _out_prepend_T_525}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6247 = out_prepend_525; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6248 = _out_T_6247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_129 = _out_T_6248; // @[MuxLiteral.scala:49:48] wire out_rimask_621 = |_out_rimask_T_621; // @[RegisterRouter.scala:87:24] wire out_wimask_621 = &_out_wimask_T_621; // @[RegisterRouter.scala:87:24] wire out_romask_621 = |_out_romask_T_621; // @[RegisterRouter.scala:87:24] wire out_womask_621 = &_out_womask_T_621; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_621 = out_rivalid_1_475 & out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6250 = out_f_rivalid_621; // @[RegisterRouter.scala:87:24] wire out_f_roready_621 = out_roready_1_475 & out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6251 = out_f_roready_621; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_621 = out_wivalid_1_475 & out_wimask_621; // @[RegisterRouter.scala:87:24] wire out_f_woready_621 = out_woready_1_475 & out_womask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6252 = ~out_rimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6253 = ~out_wimask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6254 = ~out_romask_621; // @[RegisterRouter.scala:87:24] wire _out_T_6255 = ~out_womask_621; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6257 = _out_T_6256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_526 = _out_T_6257; // @[RegisterRouter.scala:87:24] wire out_rimask_622 = |_out_rimask_T_622; // @[RegisterRouter.scala:87:24] wire out_wimask_622 = &_out_wimask_T_622; // @[RegisterRouter.scala:87:24] wire out_romask_622 = |_out_romask_T_622; // @[RegisterRouter.scala:87:24] wire out_womask_622 = &_out_womask_T_622; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_622 = out_rivalid_1_476 & out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6259 = out_f_rivalid_622; // @[RegisterRouter.scala:87:24] wire out_f_roready_622 = out_roready_1_476 & out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6260 = out_f_roready_622; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_622 = out_wivalid_1_476 & out_wimask_622; // @[RegisterRouter.scala:87:24] wire out_f_woready_622 = out_woready_1_476 & out_womask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6261 = ~out_rimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6262 = ~out_wimask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6263 = ~out_romask_622; // @[RegisterRouter.scala:87:24] wire _out_T_6264 = ~out_womask_622; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_526 = {hi_50, flags_0_go, _out_prepend_T_526}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6265 = out_prepend_526; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6266 = _out_T_6265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_527 = _out_T_6266; // @[RegisterRouter.scala:87:24] wire out_rimask_623 = |_out_rimask_T_623; // @[RegisterRouter.scala:87:24] wire out_wimask_623 = &_out_wimask_T_623; // @[RegisterRouter.scala:87:24] wire out_romask_623 = |_out_romask_T_623; // @[RegisterRouter.scala:87:24] wire out_womask_623 = &_out_womask_T_623; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_623 = out_rivalid_1_477 & out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6268 = out_f_rivalid_623; // @[RegisterRouter.scala:87:24] wire out_f_roready_623 = out_roready_1_477 & out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6269 = out_f_roready_623; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_623 = out_wivalid_1_477 & out_wimask_623; // @[RegisterRouter.scala:87:24] wire out_f_woready_623 = out_woready_1_477 & out_womask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6270 = ~out_rimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6271 = ~out_wimask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6272 = ~out_romask_623; // @[RegisterRouter.scala:87:24] wire _out_T_6273 = ~out_womask_623; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_527 = {hi_51, flags_0_go, _out_prepend_T_527}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6274 = out_prepend_527; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6275 = _out_T_6274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_528 = _out_T_6275; // @[RegisterRouter.scala:87:24] wire out_rimask_624 = |_out_rimask_T_624; // @[RegisterRouter.scala:87:24] wire out_wimask_624 = &_out_wimask_T_624; // @[RegisterRouter.scala:87:24] wire out_romask_624 = |_out_romask_T_624; // @[RegisterRouter.scala:87:24] wire out_womask_624 = &_out_womask_T_624; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_624 = out_rivalid_1_478 & out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6277 = out_f_rivalid_624; // @[RegisterRouter.scala:87:24] wire out_f_roready_624 = out_roready_1_478 & out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6278 = out_f_roready_624; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_624 = out_wivalid_1_478 & out_wimask_624; // @[RegisterRouter.scala:87:24] wire out_f_woready_624 = out_woready_1_478 & out_womask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6279 = ~out_rimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6280 = ~out_wimask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6281 = ~out_romask_624; // @[RegisterRouter.scala:87:24] wire _out_T_6282 = ~out_womask_624; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_528 = {hi_52, flags_0_go, _out_prepend_T_528}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6283 = out_prepend_528; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6284 = _out_T_6283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_529 = _out_T_6284; // @[RegisterRouter.scala:87:24] wire out_rimask_625 = |_out_rimask_T_625; // @[RegisterRouter.scala:87:24] wire out_wimask_625 = &_out_wimask_T_625; // @[RegisterRouter.scala:87:24] wire out_romask_625 = |_out_romask_T_625; // @[RegisterRouter.scala:87:24] wire out_womask_625 = &_out_womask_T_625; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_625 = out_rivalid_1_479 & out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6286 = out_f_rivalid_625; // @[RegisterRouter.scala:87:24] wire out_f_roready_625 = out_roready_1_479 & out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6287 = out_f_roready_625; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_625 = out_wivalid_1_479 & out_wimask_625; // @[RegisterRouter.scala:87:24] wire out_f_woready_625 = out_woready_1_479 & out_womask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6288 = ~out_rimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6289 = ~out_wimask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6290 = ~out_romask_625; // @[RegisterRouter.scala:87:24] wire _out_T_6291 = ~out_womask_625; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_529 = {hi_53, flags_0_go, _out_prepend_T_529}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6292 = out_prepend_529; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6293 = _out_T_6292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_530 = _out_T_6293; // @[RegisterRouter.scala:87:24] wire out_rimask_626 = |_out_rimask_T_626; // @[RegisterRouter.scala:87:24] wire out_wimask_626 = &_out_wimask_T_626; // @[RegisterRouter.scala:87:24] wire out_romask_626 = |_out_romask_T_626; // @[RegisterRouter.scala:87:24] wire out_womask_626 = &_out_womask_T_626; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_626 = out_rivalid_1_480 & out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6295 = out_f_rivalid_626; // @[RegisterRouter.scala:87:24] wire out_f_roready_626 = out_roready_1_480 & out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6296 = out_f_roready_626; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_626 = out_wivalid_1_480 & out_wimask_626; // @[RegisterRouter.scala:87:24] wire out_f_woready_626 = out_woready_1_480 & out_womask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6297 = ~out_rimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6298 = ~out_wimask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6299 = ~out_romask_626; // @[RegisterRouter.scala:87:24] wire _out_T_6300 = ~out_womask_626; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_530 = {hi_54, flags_0_go, _out_prepend_T_530}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6301 = out_prepend_530; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6302 = _out_T_6301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_531 = _out_T_6302; // @[RegisterRouter.scala:87:24] wire out_rimask_627 = |_out_rimask_T_627; // @[RegisterRouter.scala:87:24] wire out_wimask_627 = &_out_wimask_T_627; // @[RegisterRouter.scala:87:24] wire out_romask_627 = |_out_romask_T_627; // @[RegisterRouter.scala:87:24] wire out_womask_627 = &_out_womask_T_627; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_627 = out_rivalid_1_481 & out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6304 = out_f_rivalid_627; // @[RegisterRouter.scala:87:24] wire out_f_roready_627 = out_roready_1_481 & out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6305 = out_f_roready_627; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_627 = out_wivalid_1_481 & out_wimask_627; // @[RegisterRouter.scala:87:24] wire out_f_woready_627 = out_woready_1_481 & out_womask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6306 = ~out_rimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6307 = ~out_wimask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6308 = ~out_romask_627; // @[RegisterRouter.scala:87:24] wire _out_T_6309 = ~out_womask_627; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_531 = {hi_55, flags_0_go, _out_prepend_T_531}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6310 = out_prepend_531; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6311 = _out_T_6310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_532 = _out_T_6311; // @[RegisterRouter.scala:87:24] wire out_rimask_628 = |_out_rimask_T_628; // @[RegisterRouter.scala:87:24] wire out_wimask_628 = &_out_wimask_T_628; // @[RegisterRouter.scala:87:24] wire out_romask_628 = |_out_romask_T_628; // @[RegisterRouter.scala:87:24] wire out_womask_628 = &_out_womask_T_628; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_628 = out_rivalid_1_482 & out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6313 = out_f_rivalid_628; // @[RegisterRouter.scala:87:24] wire out_f_roready_628 = out_roready_1_482 & out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6314 = out_f_roready_628; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_628 = out_wivalid_1_482 & out_wimask_628; // @[RegisterRouter.scala:87:24] wire out_f_woready_628 = out_woready_1_482 & out_womask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6315 = ~out_rimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6316 = ~out_wimask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6317 = ~out_romask_628; // @[RegisterRouter.scala:87:24] wire _out_T_6318 = ~out_womask_628; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_532 = {hi_56, flags_0_go, _out_prepend_T_532}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6319 = out_prepend_532; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6320 = _out_T_6319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_134 = _out_T_6320; // @[MuxLiteral.scala:49:48] wire out_rimask_629 = |_out_rimask_T_629; // @[RegisterRouter.scala:87:24] wire out_wimask_629 = &_out_wimask_T_629; // @[RegisterRouter.scala:87:24] wire out_romask_629 = |_out_romask_T_629; // @[RegisterRouter.scala:87:24] wire out_womask_629 = &_out_womask_T_629; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_629 = out_rivalid_1_483 & out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6322 = out_f_rivalid_629; // @[RegisterRouter.scala:87:24] wire out_f_roready_629 = out_roready_1_483 & out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6323 = out_f_roready_629; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_629 = out_wivalid_1_483 & out_wimask_629; // @[RegisterRouter.scala:87:24] wire out_f_woready_629 = out_woready_1_483 & out_womask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6324 = ~out_rimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6325 = ~out_wimask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6326 = ~out_romask_629; // @[RegisterRouter.scala:87:24] wire _out_T_6327 = ~out_womask_629; // @[RegisterRouter.scala:87:24] wire out_rimask_630 = |_out_rimask_T_630; // @[RegisterRouter.scala:87:24] wire out_wimask_630 = &_out_wimask_T_630; // @[RegisterRouter.scala:87:24] wire out_romask_630 = |_out_romask_T_630; // @[RegisterRouter.scala:87:24] wire out_womask_630 = &_out_womask_T_630; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_630 = out_rivalid_1_484 & out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6331 = out_f_rivalid_630; // @[RegisterRouter.scala:87:24] wire out_f_roready_630 = out_roready_1_484 & out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6332 = out_f_roready_630; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_630 = out_wivalid_1_484 & out_wimask_630; // @[RegisterRouter.scala:87:24] wire out_f_woready_630 = out_woready_1_484 & out_womask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6333 = ~out_rimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6334 = ~out_wimask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6335 = ~out_romask_630; // @[RegisterRouter.scala:87:24] wire _out_T_6336 = ~out_womask_630; // @[RegisterRouter.scala:87:24] wire out_rimask_631 = |_out_rimask_T_631; // @[RegisterRouter.scala:87:24] wire out_wimask_631 = &_out_wimask_T_631; // @[RegisterRouter.scala:87:24] wire out_romask_631 = |_out_romask_T_631; // @[RegisterRouter.scala:87:24] wire out_womask_631 = &_out_womask_T_631; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_631 = out_rivalid_1_485 & out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6340 = out_f_rivalid_631; // @[RegisterRouter.scala:87:24] wire out_f_roready_631 = out_roready_1_485 & out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6341 = out_f_roready_631; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_631 = out_wivalid_1_485 & out_wimask_631; // @[RegisterRouter.scala:87:24] wire out_f_woready_631 = out_woready_1_485 & out_womask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6342 = ~out_rimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6343 = ~out_wimask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6344 = ~out_romask_631; // @[RegisterRouter.scala:87:24] wire _out_T_6345 = ~out_womask_631; // @[RegisterRouter.scala:87:24] wire out_rimask_632 = |_out_rimask_T_632; // @[RegisterRouter.scala:87:24] wire out_wimask_632 = &_out_wimask_T_632; // @[RegisterRouter.scala:87:24] wire out_romask_632 = |_out_romask_T_632; // @[RegisterRouter.scala:87:24] wire out_womask_632 = &_out_womask_T_632; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_632 = out_rivalid_1_486 & out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6349 = out_f_rivalid_632; // @[RegisterRouter.scala:87:24] wire out_f_roready_632 = out_roready_1_486 & out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6350 = out_f_roready_632; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_632 = out_wivalid_1_486 & out_wimask_632; // @[RegisterRouter.scala:87:24] wire out_f_woready_632 = out_woready_1_486 & out_womask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6351 = ~out_rimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6352 = ~out_wimask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6353 = ~out_romask_632; // @[RegisterRouter.scala:87:24] wire _out_T_6354 = ~out_womask_632; // @[RegisterRouter.scala:87:24] wire out_rimask_633 = |_out_rimask_T_633; // @[RegisterRouter.scala:87:24] wire out_wimask_633 = &_out_wimask_T_633; // @[RegisterRouter.scala:87:24] wire out_romask_633 = |_out_romask_T_633; // @[RegisterRouter.scala:87:24] wire out_womask_633 = &_out_womask_T_633; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_633 = out_rivalid_1_487 & out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6358 = out_f_rivalid_633; // @[RegisterRouter.scala:87:24] wire out_f_roready_633 = out_roready_1_487 & out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6359 = out_f_roready_633; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_633 = out_wivalid_1_487 & out_wimask_633; // @[RegisterRouter.scala:87:24] wire out_f_woready_633 = out_woready_1_487 & out_womask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6360 = ~out_rimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6361 = ~out_wimask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6362 = ~out_romask_633; // @[RegisterRouter.scala:87:24] wire _out_T_6363 = ~out_womask_633; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6365 = _out_T_6364; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_536 = _out_T_6365; // @[RegisterRouter.scala:87:24] wire out_rimask_634 = |_out_rimask_T_634; // @[RegisterRouter.scala:87:24] wire out_wimask_634 = &_out_wimask_T_634; // @[RegisterRouter.scala:87:24] wire out_romask_634 = |_out_romask_T_634; // @[RegisterRouter.scala:87:24] wire out_womask_634 = &_out_womask_T_634; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_634 = out_rivalid_1_488 & out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6367 = out_f_rivalid_634; // @[RegisterRouter.scala:87:24] wire out_f_roready_634 = out_roready_1_488 & out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6368 = out_f_roready_634; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_634 = out_wivalid_1_488 & out_wimask_634; // @[RegisterRouter.scala:87:24] wire out_f_woready_634 = out_woready_1_488 & out_womask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6369 = ~out_rimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6370 = ~out_wimask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6371 = ~out_romask_634; // @[RegisterRouter.scala:87:24] wire _out_T_6372 = ~out_womask_634; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_536 = {hi_618, flags_0_go, _out_prepend_T_536}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6373 = out_prepend_536; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6374 = _out_T_6373; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_537 = _out_T_6374; // @[RegisterRouter.scala:87:24] wire out_rimask_635 = |_out_rimask_T_635; // @[RegisterRouter.scala:87:24] wire out_wimask_635 = &_out_wimask_T_635; // @[RegisterRouter.scala:87:24] wire out_romask_635 = |_out_romask_T_635; // @[RegisterRouter.scala:87:24] wire out_womask_635 = &_out_womask_T_635; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_635 = out_rivalid_1_489 & out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6376 = out_f_rivalid_635; // @[RegisterRouter.scala:87:24] wire out_f_roready_635 = out_roready_1_489 & out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6377 = out_f_roready_635; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_635 = out_wivalid_1_489 & out_wimask_635; // @[RegisterRouter.scala:87:24] wire out_f_woready_635 = out_woready_1_489 & out_womask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6378 = ~out_rimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6379 = ~out_wimask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6380 = ~out_romask_635; // @[RegisterRouter.scala:87:24] wire _out_T_6381 = ~out_womask_635; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_537 = {hi_619, flags_0_go, _out_prepend_T_537}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6382 = out_prepend_537; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6383 = _out_T_6382; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_538 = _out_T_6383; // @[RegisterRouter.scala:87:24] wire out_rimask_636 = |_out_rimask_T_636; // @[RegisterRouter.scala:87:24] wire out_wimask_636 = &_out_wimask_T_636; // @[RegisterRouter.scala:87:24] wire out_romask_636 = |_out_romask_T_636; // @[RegisterRouter.scala:87:24] wire out_womask_636 = &_out_womask_T_636; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_636 = out_rivalid_1_490 & out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6385 = out_f_rivalid_636; // @[RegisterRouter.scala:87:24] wire out_f_roready_636 = out_roready_1_490 & out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6386 = out_f_roready_636; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_636 = out_wivalid_1_490 & out_wimask_636; // @[RegisterRouter.scala:87:24] wire out_f_woready_636 = out_woready_1_490 & out_womask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6387 = ~out_rimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6388 = ~out_wimask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6389 = ~out_romask_636; // @[RegisterRouter.scala:87:24] wire _out_T_6390 = ~out_womask_636; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_538 = {hi_620, flags_0_go, _out_prepend_T_538}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6391 = out_prepend_538; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6392 = _out_T_6391; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_539 = _out_T_6392; // @[RegisterRouter.scala:87:24] wire out_rimask_637 = |_out_rimask_T_637; // @[RegisterRouter.scala:87:24] wire out_wimask_637 = &_out_wimask_T_637; // @[RegisterRouter.scala:87:24] wire out_romask_637 = |_out_romask_T_637; // @[RegisterRouter.scala:87:24] wire out_womask_637 = &_out_womask_T_637; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_637 = out_rivalid_1_491 & out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6394 = out_f_rivalid_637; // @[RegisterRouter.scala:87:24] wire out_f_roready_637 = out_roready_1_491 & out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6395 = out_f_roready_637; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_637 = out_wivalid_1_491 & out_wimask_637; // @[RegisterRouter.scala:87:24] wire out_f_woready_637 = out_woready_1_491 & out_womask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6396 = ~out_rimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6397 = ~out_wimask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6398 = ~out_romask_637; // @[RegisterRouter.scala:87:24] wire _out_T_6399 = ~out_womask_637; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_539 = {hi_621, flags_0_go, _out_prepend_T_539}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6400 = out_prepend_539; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6401 = _out_T_6400; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_540 = _out_T_6401; // @[RegisterRouter.scala:87:24] wire out_rimask_638 = |_out_rimask_T_638; // @[RegisterRouter.scala:87:24] wire out_wimask_638 = &_out_wimask_T_638; // @[RegisterRouter.scala:87:24] wire out_romask_638 = |_out_romask_T_638; // @[RegisterRouter.scala:87:24] wire out_womask_638 = &_out_womask_T_638; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_638 = out_rivalid_1_492 & out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6403 = out_f_rivalid_638; // @[RegisterRouter.scala:87:24] wire out_f_roready_638 = out_roready_1_492 & out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6404 = out_f_roready_638; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_638 = out_wivalid_1_492 & out_wimask_638; // @[RegisterRouter.scala:87:24] wire out_f_woready_638 = out_woready_1_492 & out_womask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6405 = ~out_rimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6406 = ~out_wimask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6407 = ~out_romask_638; // @[RegisterRouter.scala:87:24] wire _out_T_6408 = ~out_womask_638; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_540 = {hi_622, flags_0_go, _out_prepend_T_540}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6409 = out_prepend_540; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6410 = _out_T_6409; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_541 = _out_T_6410; // @[RegisterRouter.scala:87:24] wire out_rimask_639 = |_out_rimask_T_639; // @[RegisterRouter.scala:87:24] wire out_wimask_639 = &_out_wimask_T_639; // @[RegisterRouter.scala:87:24] wire out_romask_639 = |_out_romask_T_639; // @[RegisterRouter.scala:87:24] wire out_womask_639 = &_out_womask_T_639; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_639 = out_rivalid_1_493 & out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6412 = out_f_rivalid_639; // @[RegisterRouter.scala:87:24] wire out_f_roready_639 = out_roready_1_493 & out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6413 = out_f_roready_639; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_639 = out_wivalid_1_493 & out_wimask_639; // @[RegisterRouter.scala:87:24] wire out_f_woready_639 = out_woready_1_493 & out_womask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6414 = ~out_rimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6415 = ~out_wimask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6416 = ~out_romask_639; // @[RegisterRouter.scala:87:24] wire _out_T_6417 = ~out_womask_639; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_541 = {hi_623, flags_0_go, _out_prepend_T_541}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6418 = out_prepend_541; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6419 = _out_T_6418; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_542 = _out_T_6419; // @[RegisterRouter.scala:87:24] wire out_rimask_640 = |_out_rimask_T_640; // @[RegisterRouter.scala:87:24] wire out_wimask_640 = &_out_wimask_T_640; // @[RegisterRouter.scala:87:24] wire out_romask_640 = |_out_romask_T_640; // @[RegisterRouter.scala:87:24] wire out_womask_640 = &_out_womask_T_640; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_640 = out_rivalid_1_494 & out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6421 = out_f_rivalid_640; // @[RegisterRouter.scala:87:24] wire out_f_roready_640 = out_roready_1_494 & out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6422 = out_f_roready_640; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_640 = out_wivalid_1_494 & out_wimask_640; // @[RegisterRouter.scala:87:24] wire out_f_woready_640 = out_woready_1_494 & out_womask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6423 = ~out_rimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6424 = ~out_wimask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6425 = ~out_romask_640; // @[RegisterRouter.scala:87:24] wire _out_T_6426 = ~out_womask_640; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_542 = {hi_624, flags_0_go, _out_prepend_T_542}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6427 = out_prepend_542; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6428 = _out_T_6427; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_205 = _out_T_6428; // @[MuxLiteral.scala:49:48] wire out_rimask_641 = |_out_rimask_T_641; // @[RegisterRouter.scala:87:24] wire out_wimask_641 = &_out_wimask_T_641; // @[RegisterRouter.scala:87:24] wire out_romask_641 = |_out_romask_T_641; // @[RegisterRouter.scala:87:24] wire out_womask_641 = &_out_womask_T_641; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_641 = out_rivalid_1_495 & out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6430 = out_f_rivalid_641; // @[RegisterRouter.scala:87:24] wire out_f_roready_641 = out_roready_1_495 & out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6431 = out_f_roready_641; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_641 = out_wivalid_1_495 & out_wimask_641; // @[RegisterRouter.scala:87:24] wire out_f_woready_641 = out_woready_1_495 & out_womask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6432 = ~out_rimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6433 = ~out_wimask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6434 = ~out_romask_641; // @[RegisterRouter.scala:87:24] wire _out_T_6435 = ~out_womask_641; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6437 = _out_T_6436; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_543 = _out_T_6437; // @[RegisterRouter.scala:87:24] wire out_rimask_642 = |_out_rimask_T_642; // @[RegisterRouter.scala:87:24] wire out_wimask_642 = &_out_wimask_T_642; // @[RegisterRouter.scala:87:24] wire out_romask_642 = |_out_romask_T_642; // @[RegisterRouter.scala:87:24] wire out_womask_642 = &_out_womask_T_642; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_642 = out_rivalid_1_496 & out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6439 = out_f_rivalid_642; // @[RegisterRouter.scala:87:24] wire out_f_roready_642 = out_roready_1_496 & out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6440 = out_f_roready_642; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_642 = out_wivalid_1_496 & out_wimask_642; // @[RegisterRouter.scala:87:24] wire out_f_woready_642 = out_woready_1_496 & out_womask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6441 = ~out_rimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6442 = ~out_wimask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6443 = ~out_romask_642; // @[RegisterRouter.scala:87:24] wire _out_T_6444 = ~out_womask_642; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_543 = {hi_2, flags_0_go, _out_prepend_T_543}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6445 = out_prepend_543; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6446 = _out_T_6445; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_544 = _out_T_6446; // @[RegisterRouter.scala:87:24] wire out_rimask_643 = |_out_rimask_T_643; // @[RegisterRouter.scala:87:24] wire out_wimask_643 = &_out_wimask_T_643; // @[RegisterRouter.scala:87:24] wire out_romask_643 = |_out_romask_T_643; // @[RegisterRouter.scala:87:24] wire out_womask_643 = &_out_womask_T_643; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_643 = out_rivalid_1_497 & out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6448 = out_f_rivalid_643; // @[RegisterRouter.scala:87:24] wire out_f_roready_643 = out_roready_1_497 & out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6449 = out_f_roready_643; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_643 = out_wivalid_1_497 & out_wimask_643; // @[RegisterRouter.scala:87:24] wire out_f_woready_643 = out_woready_1_497 & out_womask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6450 = ~out_rimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6451 = ~out_wimask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6452 = ~out_romask_643; // @[RegisterRouter.scala:87:24] wire _out_T_6453 = ~out_womask_643; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_544 = {hi_3, flags_0_go, _out_prepend_T_544}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6454 = out_prepend_544; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6455 = _out_T_6454; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_545 = _out_T_6455; // @[RegisterRouter.scala:87:24] wire out_rimask_644 = |_out_rimask_T_644; // @[RegisterRouter.scala:87:24] wire out_wimask_644 = &_out_wimask_T_644; // @[RegisterRouter.scala:87:24] wire out_romask_644 = |_out_romask_T_644; // @[RegisterRouter.scala:87:24] wire out_womask_644 = &_out_womask_T_644; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_644 = out_rivalid_1_498 & out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6457 = out_f_rivalid_644; // @[RegisterRouter.scala:87:24] wire out_f_roready_644 = out_roready_1_498 & out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6458 = out_f_roready_644; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_644 = out_wivalid_1_498 & out_wimask_644; // @[RegisterRouter.scala:87:24] wire out_f_woready_644 = out_woready_1_498 & out_womask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6459 = ~out_rimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6460 = ~out_wimask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6461 = ~out_romask_644; // @[RegisterRouter.scala:87:24] wire _out_T_6462 = ~out_womask_644; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_545 = {hi_4, flags_0_go, _out_prepend_T_545}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6463 = out_prepend_545; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6464 = _out_T_6463; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_546 = _out_T_6464; // @[RegisterRouter.scala:87:24] wire out_rimask_645 = |_out_rimask_T_645; // @[RegisterRouter.scala:87:24] wire out_wimask_645 = &_out_wimask_T_645; // @[RegisterRouter.scala:87:24] wire out_romask_645 = |_out_romask_T_645; // @[RegisterRouter.scala:87:24] wire out_womask_645 = &_out_womask_T_645; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_645 = out_rivalid_1_499 & out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6466 = out_f_rivalid_645; // @[RegisterRouter.scala:87:24] wire out_f_roready_645 = out_roready_1_499 & out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6467 = out_f_roready_645; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_645 = out_wivalid_1_499 & out_wimask_645; // @[RegisterRouter.scala:87:24] wire out_f_woready_645 = out_woready_1_499 & out_womask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6468 = ~out_rimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6469 = ~out_wimask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6470 = ~out_romask_645; // @[RegisterRouter.scala:87:24] wire _out_T_6471 = ~out_womask_645; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_546 = {hi_5, flags_0_go, _out_prepend_T_546}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6472 = out_prepend_546; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6473 = _out_T_6472; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_547 = _out_T_6473; // @[RegisterRouter.scala:87:24] wire out_rimask_646 = |_out_rimask_T_646; // @[RegisterRouter.scala:87:24] wire out_wimask_646 = &_out_wimask_T_646; // @[RegisterRouter.scala:87:24] wire out_romask_646 = |_out_romask_T_646; // @[RegisterRouter.scala:87:24] wire out_womask_646 = &_out_womask_T_646; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_646 = out_rivalid_1_500 & out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6475 = out_f_rivalid_646; // @[RegisterRouter.scala:87:24] wire out_f_roready_646 = out_roready_1_500 & out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6476 = out_f_roready_646; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_646 = out_wivalid_1_500 & out_wimask_646; // @[RegisterRouter.scala:87:24] wire out_f_woready_646 = out_woready_1_500 & out_womask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6477 = ~out_rimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6478 = ~out_wimask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6479 = ~out_romask_646; // @[RegisterRouter.scala:87:24] wire _out_T_6480 = ~out_womask_646; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_547 = {hi_6, flags_0_go, _out_prepend_T_547}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6481 = out_prepend_547; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6482 = _out_T_6481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_548 = _out_T_6482; // @[RegisterRouter.scala:87:24] wire out_rimask_647 = |_out_rimask_T_647; // @[RegisterRouter.scala:87:24] wire out_wimask_647 = &_out_wimask_T_647; // @[RegisterRouter.scala:87:24] wire out_romask_647 = |_out_romask_T_647; // @[RegisterRouter.scala:87:24] wire out_womask_647 = &_out_womask_T_647; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_647 = out_rivalid_1_501 & out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6484 = out_f_rivalid_647; // @[RegisterRouter.scala:87:24] wire out_f_roready_647 = out_roready_1_501 & out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6485 = out_f_roready_647; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_647 = out_wivalid_1_501 & out_wimask_647; // @[RegisterRouter.scala:87:24] wire out_f_woready_647 = out_woready_1_501 & out_womask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6486 = ~out_rimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6487 = ~out_wimask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6488 = ~out_romask_647; // @[RegisterRouter.scala:87:24] wire _out_T_6489 = ~out_womask_647; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_548 = {hi_7, flags_0_go, _out_prepend_T_548}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6490 = out_prepend_548; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6491 = _out_T_6490; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_549 = _out_T_6491; // @[RegisterRouter.scala:87:24] wire out_rimask_648 = |_out_rimask_T_648; // @[RegisterRouter.scala:87:24] wire out_wimask_648 = &_out_wimask_T_648; // @[RegisterRouter.scala:87:24] wire out_romask_648 = |_out_romask_T_648; // @[RegisterRouter.scala:87:24] wire out_womask_648 = &_out_womask_T_648; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_648 = out_rivalid_1_502 & out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6493 = out_f_rivalid_648; // @[RegisterRouter.scala:87:24] wire out_f_roready_648 = out_roready_1_502 & out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6494 = out_f_roready_648; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_648 = out_wivalid_1_502 & out_wimask_648; // @[RegisterRouter.scala:87:24] wire out_f_woready_648 = out_woready_1_502 & out_womask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6495 = ~out_rimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6496 = ~out_wimask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6497 = ~out_romask_648; // @[RegisterRouter.scala:87:24] wire _out_T_6498 = ~out_womask_648; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_549 = {hi_8, flags_0_go, _out_prepend_T_549}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6499 = out_prepend_549; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6500 = _out_T_6499; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_128 = _out_T_6500; // @[MuxLiteral.scala:49:48] wire out_rimask_649 = |_out_rimask_T_649; // @[RegisterRouter.scala:87:24] wire out_wimask_649 = &_out_wimask_T_649; // @[RegisterRouter.scala:87:24] wire out_romask_649 = |_out_romask_T_649; // @[RegisterRouter.scala:87:24] wire out_womask_649 = &_out_womask_T_649; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_649 = out_rivalid_1_503 & out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6502 = out_f_rivalid_649; // @[RegisterRouter.scala:87:24] wire out_f_roready_649 = out_roready_1_503 & out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6503 = out_f_roready_649; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_649 = out_wivalid_1_503 & out_wimask_649; // @[RegisterRouter.scala:87:24] wire out_f_woready_649 = out_woready_1_503 & out_womask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6504 = ~out_rimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6505 = ~out_wimask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6506 = ~out_romask_649; // @[RegisterRouter.scala:87:24] wire _out_T_6507 = ~out_womask_649; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6509 = _out_T_6508; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_550 = _out_T_6509; // @[RegisterRouter.scala:87:24] wire out_rimask_650 = |_out_rimask_T_650; // @[RegisterRouter.scala:87:24] wire out_wimask_650 = &_out_wimask_T_650; // @[RegisterRouter.scala:87:24] wire out_romask_650 = |_out_romask_T_650; // @[RegisterRouter.scala:87:24] wire out_womask_650 = &_out_womask_T_650; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_650 = out_rivalid_1_504 & out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6511 = out_f_rivalid_650; // @[RegisterRouter.scala:87:24] wire out_f_roready_650 = out_roready_1_504 & out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6512 = out_f_roready_650; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_650 = out_wivalid_1_504 & out_wimask_650; // @[RegisterRouter.scala:87:24] wire out_f_woready_650 = out_woready_1_504 & out_womask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6513 = ~out_rimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6514 = ~out_wimask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6515 = ~out_romask_650; // @[RegisterRouter.scala:87:24] wire _out_T_6516 = ~out_womask_650; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_550 = {hi_874, flags_0_go, _out_prepend_T_550}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6517 = out_prepend_550; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6518 = _out_T_6517; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_551 = _out_T_6518; // @[RegisterRouter.scala:87:24] wire out_rimask_651 = |_out_rimask_T_651; // @[RegisterRouter.scala:87:24] wire out_wimask_651 = &_out_wimask_T_651; // @[RegisterRouter.scala:87:24] wire out_romask_651 = |_out_romask_T_651; // @[RegisterRouter.scala:87:24] wire out_womask_651 = &_out_womask_T_651; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_651 = out_rivalid_1_505 & out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6520 = out_f_rivalid_651; // @[RegisterRouter.scala:87:24] wire out_f_roready_651 = out_roready_1_505 & out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6521 = out_f_roready_651; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_651 = out_wivalid_1_505 & out_wimask_651; // @[RegisterRouter.scala:87:24] wire out_f_woready_651 = out_woready_1_505 & out_womask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6522 = ~out_rimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6523 = ~out_wimask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6524 = ~out_romask_651; // @[RegisterRouter.scala:87:24] wire _out_T_6525 = ~out_womask_651; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_551 = {hi_875, flags_0_go, _out_prepend_T_551}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6526 = out_prepend_551; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6527 = _out_T_6526; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_552 = _out_T_6527; // @[RegisterRouter.scala:87:24] wire out_rimask_652 = |_out_rimask_T_652; // @[RegisterRouter.scala:87:24] wire out_wimask_652 = &_out_wimask_T_652; // @[RegisterRouter.scala:87:24] wire out_romask_652 = |_out_romask_T_652; // @[RegisterRouter.scala:87:24] wire out_womask_652 = &_out_womask_T_652; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_652 = out_rivalid_1_506 & out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6529 = out_f_rivalid_652; // @[RegisterRouter.scala:87:24] wire out_f_roready_652 = out_roready_1_506 & out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6530 = out_f_roready_652; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_652 = out_wivalid_1_506 & out_wimask_652; // @[RegisterRouter.scala:87:24] wire out_f_woready_652 = out_woready_1_506 & out_womask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6531 = ~out_rimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6532 = ~out_wimask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6533 = ~out_romask_652; // @[RegisterRouter.scala:87:24] wire _out_T_6534 = ~out_womask_652; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_552 = {hi_876, flags_0_go, _out_prepend_T_552}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6535 = out_prepend_552; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6536 = _out_T_6535; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_553 = _out_T_6536; // @[RegisterRouter.scala:87:24] wire out_rimask_653 = |_out_rimask_T_653; // @[RegisterRouter.scala:87:24] wire out_wimask_653 = &_out_wimask_T_653; // @[RegisterRouter.scala:87:24] wire out_romask_653 = |_out_romask_T_653; // @[RegisterRouter.scala:87:24] wire out_womask_653 = &_out_womask_T_653; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_653 = out_rivalid_1_507 & out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6538 = out_f_rivalid_653; // @[RegisterRouter.scala:87:24] wire out_f_roready_653 = out_roready_1_507 & out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6539 = out_f_roready_653; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_653 = out_wivalid_1_507 & out_wimask_653; // @[RegisterRouter.scala:87:24] wire out_f_woready_653 = out_woready_1_507 & out_womask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6540 = ~out_rimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6541 = ~out_wimask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6542 = ~out_romask_653; // @[RegisterRouter.scala:87:24] wire _out_T_6543 = ~out_womask_653; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_553 = {hi_877, flags_0_go, _out_prepend_T_553}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6544 = out_prepend_553; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6545 = _out_T_6544; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_554 = _out_T_6545; // @[RegisterRouter.scala:87:24] wire out_rimask_654 = |_out_rimask_T_654; // @[RegisterRouter.scala:87:24] wire out_wimask_654 = &_out_wimask_T_654; // @[RegisterRouter.scala:87:24] wire out_romask_654 = |_out_romask_T_654; // @[RegisterRouter.scala:87:24] wire out_womask_654 = &_out_womask_T_654; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_654 = out_rivalid_1_508 & out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6547 = out_f_rivalid_654; // @[RegisterRouter.scala:87:24] wire out_f_roready_654 = out_roready_1_508 & out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6548 = out_f_roready_654; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_654 = out_wivalid_1_508 & out_wimask_654; // @[RegisterRouter.scala:87:24] wire out_f_woready_654 = out_woready_1_508 & out_womask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6549 = ~out_rimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6550 = ~out_wimask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6551 = ~out_romask_654; // @[RegisterRouter.scala:87:24] wire _out_T_6552 = ~out_womask_654; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_554 = {hi_878, flags_0_go, _out_prepend_T_554}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6553 = out_prepend_554; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6554 = _out_T_6553; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_555 = _out_T_6554; // @[RegisterRouter.scala:87:24] wire out_rimask_655 = |_out_rimask_T_655; // @[RegisterRouter.scala:87:24] wire out_wimask_655 = &_out_wimask_T_655; // @[RegisterRouter.scala:87:24] wire out_romask_655 = |_out_romask_T_655; // @[RegisterRouter.scala:87:24] wire out_womask_655 = &_out_womask_T_655; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_655 = out_rivalid_1_509 & out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6556 = out_f_rivalid_655; // @[RegisterRouter.scala:87:24] wire out_f_roready_655 = out_roready_1_509 & out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6557 = out_f_roready_655; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_655 = out_wivalid_1_509 & out_wimask_655; // @[RegisterRouter.scala:87:24] wire out_f_woready_655 = out_woready_1_509 & out_womask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6558 = ~out_rimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6559 = ~out_wimask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6560 = ~out_romask_655; // @[RegisterRouter.scala:87:24] wire _out_T_6561 = ~out_womask_655; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_555 = {hi_879, flags_0_go, _out_prepend_T_555}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6562 = out_prepend_555; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6563 = _out_T_6562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_556 = _out_T_6563; // @[RegisterRouter.scala:87:24] wire out_rimask_656 = |_out_rimask_T_656; // @[RegisterRouter.scala:87:24] wire out_wimask_656 = &_out_wimask_T_656; // @[RegisterRouter.scala:87:24] wire out_romask_656 = |_out_romask_T_656; // @[RegisterRouter.scala:87:24] wire out_womask_656 = &_out_womask_T_656; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_656 = out_rivalid_1_510 & out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6565 = out_f_rivalid_656; // @[RegisterRouter.scala:87:24] wire out_f_roready_656 = out_roready_1_510 & out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6566 = out_f_roready_656; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_656 = out_wivalid_1_510 & out_wimask_656; // @[RegisterRouter.scala:87:24] wire out_f_woready_656 = out_woready_1_510 & out_womask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6567 = ~out_rimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6568 = ~out_wimask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6569 = ~out_romask_656; // @[RegisterRouter.scala:87:24] wire _out_T_6570 = ~out_womask_656; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_556 = {hi_880, flags_0_go, _out_prepend_T_556}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6571 = out_prepend_556; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6572 = _out_T_6571; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_237 = _out_T_6572; // @[MuxLiteral.scala:49:48] wire out_rimask_657 = |_out_rimask_T_657; // @[RegisterRouter.scala:87:24] wire out_wimask_657 = &_out_wimask_T_657; // @[RegisterRouter.scala:87:24] wire out_romask_657 = |_out_romask_T_657; // @[RegisterRouter.scala:87:24] wire out_womask_657 = &_out_womask_T_657; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_657 = out_rivalid_1_511 & out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6574 = out_f_rivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_roready_657 = out_roready_1_511 & out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6575 = out_f_roready_657; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_657 = out_wivalid_1_511 & out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6576 = out_f_wivalid_657; // @[RegisterRouter.scala:87:24] wire out_f_woready_657 = out_woready_1_511 & out_womask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6577 = out_f_woready_657; // @[RegisterRouter.scala:87:24] wire _out_T_6578 = ~out_rimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6579 = ~out_wimask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6580 = ~out_romask_657; // @[RegisterRouter.scala:87:24] wire _out_T_6581 = ~out_womask_657; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6583 = _out_T_6582; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_557 = _out_T_6583; // @[RegisterRouter.scala:87:24] wire out_rimask_658 = |_out_rimask_T_658; // @[RegisterRouter.scala:87:24] wire out_wimask_658 = &_out_wimask_T_658; // @[RegisterRouter.scala:87:24] wire out_romask_658 = |_out_romask_T_658; // @[RegisterRouter.scala:87:24] wire out_womask_658 = &_out_womask_T_658; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_658 = out_rivalid_1_512 & out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6585 = out_f_rivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_roready_658 = out_roready_1_512 & out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6586 = out_f_roready_658; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_658 = out_wivalid_1_512 & out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6587 = out_f_wivalid_658; // @[RegisterRouter.scala:87:24] wire out_f_woready_658 = out_woready_1_512 & out_womask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6588 = out_f_woready_658; // @[RegisterRouter.scala:87:24] wire _out_T_6589 = ~out_rimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6590 = ~out_wimask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6591 = ~out_romask_658; // @[RegisterRouter.scala:87:24] wire _out_T_6592 = ~out_womask_658; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_557 = {programBufferMem_9, _out_prepend_T_557}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6593 = out_prepend_557; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6594 = _out_T_6593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_558 = _out_T_6594; // @[RegisterRouter.scala:87:24] wire out_rimask_659 = |_out_rimask_T_659; // @[RegisterRouter.scala:87:24] wire out_wimask_659 = &_out_wimask_T_659; // @[RegisterRouter.scala:87:24] wire out_romask_659 = |_out_romask_T_659; // @[RegisterRouter.scala:87:24] wire out_womask_659 = &_out_womask_T_659; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_659 = out_rivalid_1_513 & out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6596 = out_f_rivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_roready_659 = out_roready_1_513 & out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6597 = out_f_roready_659; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_659 = out_wivalid_1_513 & out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6598 = out_f_wivalid_659; // @[RegisterRouter.scala:87:24] wire out_f_woready_659 = out_woready_1_513 & out_womask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6599 = out_f_woready_659; // @[RegisterRouter.scala:87:24] wire _out_T_6600 = ~out_rimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6601 = ~out_wimask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6602 = ~out_romask_659; // @[RegisterRouter.scala:87:24] wire _out_T_6603 = ~out_womask_659; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_558 = {programBufferMem_10, _out_prepend_T_558}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6604 = out_prepend_558; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6605 = _out_T_6604; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_559 = _out_T_6605; // @[RegisterRouter.scala:87:24] wire out_rimask_660 = |_out_rimask_T_660; // @[RegisterRouter.scala:87:24] wire out_wimask_660 = &_out_wimask_T_660; // @[RegisterRouter.scala:87:24] wire out_romask_660 = |_out_romask_T_660; // @[RegisterRouter.scala:87:24] wire out_womask_660 = &_out_womask_T_660; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_660 = out_rivalid_1_514 & out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6607 = out_f_rivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_roready_660 = out_roready_1_514 & out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6608 = out_f_roready_660; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_660 = out_wivalid_1_514 & out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6609 = out_f_wivalid_660; // @[RegisterRouter.scala:87:24] wire out_f_woready_660 = out_woready_1_514 & out_womask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6610 = out_f_woready_660; // @[RegisterRouter.scala:87:24] wire _out_T_6611 = ~out_rimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6612 = ~out_wimask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6613 = ~out_romask_660; // @[RegisterRouter.scala:87:24] wire _out_T_6614 = ~out_womask_660; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_559 = {programBufferMem_11, _out_prepend_T_559}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6615 = out_prepend_559; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6616 = _out_T_6615; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_560 = _out_T_6616; // @[RegisterRouter.scala:87:24] wire out_rimask_661 = |_out_rimask_T_661; // @[RegisterRouter.scala:87:24] wire out_wimask_661 = &_out_wimask_T_661; // @[RegisterRouter.scala:87:24] wire out_romask_661 = |_out_romask_T_661; // @[RegisterRouter.scala:87:24] wire out_womask_661 = &_out_womask_T_661; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_661 = out_rivalid_1_515 & out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6618 = out_f_rivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_roready_661 = out_roready_1_515 & out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6619 = out_f_roready_661; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_661 = out_wivalid_1_515 & out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6620 = out_f_wivalid_661; // @[RegisterRouter.scala:87:24] wire out_f_woready_661 = out_woready_1_515 & out_womask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6621 = out_f_woready_661; // @[RegisterRouter.scala:87:24] wire _out_T_6622 = ~out_rimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6623 = ~out_wimask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6624 = ~out_romask_661; // @[RegisterRouter.scala:87:24] wire _out_T_6625 = ~out_womask_661; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_560 = {programBufferMem_12, _out_prepend_T_560}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6626 = out_prepend_560; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6627 = _out_T_6626; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_561 = _out_T_6627; // @[RegisterRouter.scala:87:24] wire out_rimask_662 = |_out_rimask_T_662; // @[RegisterRouter.scala:87:24] wire out_wimask_662 = &_out_wimask_T_662; // @[RegisterRouter.scala:87:24] wire out_romask_662 = |_out_romask_T_662; // @[RegisterRouter.scala:87:24] wire out_womask_662 = &_out_womask_T_662; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_662 = out_rivalid_1_516 & out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6629 = out_f_rivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_roready_662 = out_roready_1_516 & out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6630 = out_f_roready_662; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_662 = out_wivalid_1_516 & out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6631 = out_f_wivalid_662; // @[RegisterRouter.scala:87:24] wire out_f_woready_662 = out_woready_1_516 & out_womask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6632 = out_f_woready_662; // @[RegisterRouter.scala:87:24] wire _out_T_6633 = ~out_rimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6634 = ~out_wimask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6635 = ~out_romask_662; // @[RegisterRouter.scala:87:24] wire _out_T_6636 = ~out_womask_662; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_561 = {programBufferMem_13, _out_prepend_T_561}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6637 = out_prepend_561; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6638 = _out_T_6637; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_562 = _out_T_6638; // @[RegisterRouter.scala:87:24] wire out_rimask_663 = |_out_rimask_T_663; // @[RegisterRouter.scala:87:24] wire out_wimask_663 = &_out_wimask_T_663; // @[RegisterRouter.scala:87:24] wire out_romask_663 = |_out_romask_T_663; // @[RegisterRouter.scala:87:24] wire out_womask_663 = &_out_womask_T_663; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_663 = out_rivalid_1_517 & out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6640 = out_f_rivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_roready_663 = out_roready_1_517 & out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6641 = out_f_roready_663; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_663 = out_wivalid_1_517 & out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6642 = out_f_wivalid_663; // @[RegisterRouter.scala:87:24] wire out_f_woready_663 = out_woready_1_517 & out_womask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6643 = out_f_woready_663; // @[RegisterRouter.scala:87:24] wire _out_T_6644 = ~out_rimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6645 = ~out_wimask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6646 = ~out_romask_663; // @[RegisterRouter.scala:87:24] wire _out_T_6647 = ~out_womask_663; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_562 = {programBufferMem_14, _out_prepend_T_562}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6648 = out_prepend_562; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6649 = _out_T_6648; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_563 = _out_T_6649; // @[RegisterRouter.scala:87:24] wire out_rimask_664 = |_out_rimask_T_664; // @[RegisterRouter.scala:87:24] wire out_wimask_664 = &_out_wimask_T_664; // @[RegisterRouter.scala:87:24] wire out_romask_664 = |_out_romask_T_664; // @[RegisterRouter.scala:87:24] wire out_womask_664 = &_out_womask_T_664; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_664 = out_rivalid_1_518 & out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6651 = out_f_rivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_roready_664 = out_roready_1_518 & out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6652 = out_f_roready_664; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_664 = out_wivalid_1_518 & out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6653 = out_f_wivalid_664; // @[RegisterRouter.scala:87:24] wire out_f_woready_664 = out_woready_1_518 & out_womask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6654 = out_f_woready_664; // @[RegisterRouter.scala:87:24] wire _out_T_6655 = ~out_rimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6656 = ~out_wimask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6657 = ~out_romask_664; // @[RegisterRouter.scala:87:24] wire _out_T_6658 = ~out_womask_664; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_563 = {programBufferMem_15, _out_prepend_T_563}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6659 = out_prepend_563; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6660 = _out_T_6659; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_105 = _out_T_6660; // @[MuxLiteral.scala:49:48] wire out_rimask_665 = |_out_rimask_T_665; // @[RegisterRouter.scala:87:24] wire out_wimask_665 = &_out_wimask_T_665; // @[RegisterRouter.scala:87:24] wire out_romask_665 = |_out_romask_T_665; // @[RegisterRouter.scala:87:24] wire out_womask_665 = &_out_womask_T_665; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_665 = out_rivalid_1_519 & out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6662 = out_f_rivalid_665; // @[RegisterRouter.scala:87:24] wire out_f_roready_665 = out_roready_1_519 & out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6663 = out_f_roready_665; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_665 = out_wivalid_1_519 & out_wimask_665; // @[RegisterRouter.scala:87:24] wire out_f_woready_665 = out_woready_1_519 & out_womask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6664 = ~out_rimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6665 = ~out_wimask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6666 = ~out_romask_665; // @[RegisterRouter.scala:87:24] wire _out_T_6667 = ~out_womask_665; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6669 = _out_T_6668; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_564 = _out_T_6669; // @[RegisterRouter.scala:87:24] wire out_rimask_666 = |_out_rimask_T_666; // @[RegisterRouter.scala:87:24] wire out_wimask_666 = &_out_wimask_T_666; // @[RegisterRouter.scala:87:24] wire out_romask_666 = |_out_romask_T_666; // @[RegisterRouter.scala:87:24] wire out_womask_666 = &_out_womask_T_666; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_666 = out_rivalid_1_520 & out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6671 = out_f_rivalid_666; // @[RegisterRouter.scala:87:24] wire out_f_roready_666 = out_roready_1_520 & out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6672 = out_f_roready_666; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_666 = out_wivalid_1_520 & out_wimask_666; // @[RegisterRouter.scala:87:24] wire out_f_woready_666 = out_woready_1_520 & out_womask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6673 = ~out_rimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6674 = ~out_wimask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6675 = ~out_romask_666; // @[RegisterRouter.scala:87:24] wire _out_T_6676 = ~out_womask_666; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_564 = {hi_930, flags_0_go, _out_prepend_T_564}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6677 = out_prepend_564; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6678 = _out_T_6677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_565 = _out_T_6678; // @[RegisterRouter.scala:87:24] wire out_rimask_667 = |_out_rimask_T_667; // @[RegisterRouter.scala:87:24] wire out_wimask_667 = &_out_wimask_T_667; // @[RegisterRouter.scala:87:24] wire out_romask_667 = |_out_romask_T_667; // @[RegisterRouter.scala:87:24] wire out_womask_667 = &_out_womask_T_667; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_667 = out_rivalid_1_521 & out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6680 = out_f_rivalid_667; // @[RegisterRouter.scala:87:24] wire out_f_roready_667 = out_roready_1_521 & out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6681 = out_f_roready_667; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_667 = out_wivalid_1_521 & out_wimask_667; // @[RegisterRouter.scala:87:24] wire out_f_woready_667 = out_woready_1_521 & out_womask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6682 = ~out_rimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6683 = ~out_wimask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6684 = ~out_romask_667; // @[RegisterRouter.scala:87:24] wire _out_T_6685 = ~out_womask_667; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_565 = {hi_931, flags_0_go, _out_prepend_T_565}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6686 = out_prepend_565; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6687 = _out_T_6686; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_566 = _out_T_6687; // @[RegisterRouter.scala:87:24] wire out_rimask_668 = |_out_rimask_T_668; // @[RegisterRouter.scala:87:24] wire out_wimask_668 = &_out_wimask_T_668; // @[RegisterRouter.scala:87:24] wire out_romask_668 = |_out_romask_T_668; // @[RegisterRouter.scala:87:24] wire out_womask_668 = &_out_womask_T_668; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_668 = out_rivalid_1_522 & out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6689 = out_f_rivalid_668; // @[RegisterRouter.scala:87:24] wire out_f_roready_668 = out_roready_1_522 & out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6690 = out_f_roready_668; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_668 = out_wivalid_1_522 & out_wimask_668; // @[RegisterRouter.scala:87:24] wire out_f_woready_668 = out_woready_1_522 & out_womask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6691 = ~out_rimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6692 = ~out_wimask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6693 = ~out_romask_668; // @[RegisterRouter.scala:87:24] wire _out_T_6694 = ~out_womask_668; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_566 = {hi_932, flags_0_go, _out_prepend_T_566}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6695 = out_prepend_566; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6696 = _out_T_6695; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_567 = _out_T_6696; // @[RegisterRouter.scala:87:24] wire out_rimask_669 = |_out_rimask_T_669; // @[RegisterRouter.scala:87:24] wire out_wimask_669 = &_out_wimask_T_669; // @[RegisterRouter.scala:87:24] wire out_romask_669 = |_out_romask_T_669; // @[RegisterRouter.scala:87:24] wire out_womask_669 = &_out_womask_T_669; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_669 = out_rivalid_1_523 & out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6698 = out_f_rivalid_669; // @[RegisterRouter.scala:87:24] wire out_f_roready_669 = out_roready_1_523 & out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6699 = out_f_roready_669; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_669 = out_wivalid_1_523 & out_wimask_669; // @[RegisterRouter.scala:87:24] wire out_f_woready_669 = out_woready_1_523 & out_womask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6700 = ~out_rimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6701 = ~out_wimask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6702 = ~out_romask_669; // @[RegisterRouter.scala:87:24] wire _out_T_6703 = ~out_womask_669; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_567 = {hi_933, flags_0_go, _out_prepend_T_567}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6704 = out_prepend_567; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6705 = _out_T_6704; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_568 = _out_T_6705; // @[RegisterRouter.scala:87:24] wire out_rimask_670 = |_out_rimask_T_670; // @[RegisterRouter.scala:87:24] wire out_wimask_670 = &_out_wimask_T_670; // @[RegisterRouter.scala:87:24] wire out_romask_670 = |_out_romask_T_670; // @[RegisterRouter.scala:87:24] wire out_womask_670 = &_out_womask_T_670; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_670 = out_rivalid_1_524 & out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6707 = out_f_rivalid_670; // @[RegisterRouter.scala:87:24] wire out_f_roready_670 = out_roready_1_524 & out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6708 = out_f_roready_670; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_670 = out_wivalid_1_524 & out_wimask_670; // @[RegisterRouter.scala:87:24] wire out_f_woready_670 = out_woready_1_524 & out_womask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6709 = ~out_rimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6710 = ~out_wimask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6711 = ~out_romask_670; // @[RegisterRouter.scala:87:24] wire _out_T_6712 = ~out_womask_670; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_568 = {hi_934, flags_0_go, _out_prepend_T_568}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6713 = out_prepend_568; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6714 = _out_T_6713; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_569 = _out_T_6714; // @[RegisterRouter.scala:87:24] wire out_rimask_671 = |_out_rimask_T_671; // @[RegisterRouter.scala:87:24] wire out_wimask_671 = &_out_wimask_T_671; // @[RegisterRouter.scala:87:24] wire out_romask_671 = |_out_romask_T_671; // @[RegisterRouter.scala:87:24] wire out_womask_671 = &_out_womask_T_671; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_671 = out_rivalid_1_525 & out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6716 = out_f_rivalid_671; // @[RegisterRouter.scala:87:24] wire out_f_roready_671 = out_roready_1_525 & out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6717 = out_f_roready_671; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_671 = out_wivalid_1_525 & out_wimask_671; // @[RegisterRouter.scala:87:24] wire out_f_woready_671 = out_woready_1_525 & out_womask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6718 = ~out_rimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6719 = ~out_wimask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6720 = ~out_romask_671; // @[RegisterRouter.scala:87:24] wire _out_T_6721 = ~out_womask_671; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_569 = {hi_935, flags_0_go, _out_prepend_T_569}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6722 = out_prepend_569; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6723 = _out_T_6722; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_570 = _out_T_6723; // @[RegisterRouter.scala:87:24] wire out_rimask_672 = |_out_rimask_T_672; // @[RegisterRouter.scala:87:24] wire out_wimask_672 = &_out_wimask_T_672; // @[RegisterRouter.scala:87:24] wire out_romask_672 = |_out_romask_T_672; // @[RegisterRouter.scala:87:24] wire out_womask_672 = &_out_womask_T_672; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_672 = out_rivalid_1_526 & out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6725 = out_f_rivalid_672; // @[RegisterRouter.scala:87:24] wire out_f_roready_672 = out_roready_1_526 & out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6726 = out_f_roready_672; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_672 = out_wivalid_1_526 & out_wimask_672; // @[RegisterRouter.scala:87:24] wire out_f_woready_672 = out_woready_1_526 & out_womask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6727 = ~out_rimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6728 = ~out_wimask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6729 = ~out_romask_672; // @[RegisterRouter.scala:87:24] wire _out_T_6730 = ~out_womask_672; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_570 = {hi_936, flags_0_go, _out_prepend_T_570}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6731 = out_prepend_570; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6732 = _out_T_6731; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_244 = _out_T_6732; // @[MuxLiteral.scala:49:48] wire out_rimask_673 = |_out_rimask_T_673; // @[RegisterRouter.scala:87:24] wire out_wimask_673 = &_out_wimask_T_673; // @[RegisterRouter.scala:87:24] wire out_romask_673 = |_out_romask_T_673; // @[RegisterRouter.scala:87:24] wire out_womask_673 = &_out_womask_T_673; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_673 = out_rivalid_1_527 & out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6734 = out_f_rivalid_673; // @[RegisterRouter.scala:87:24] wire out_f_roready_673 = out_roready_1_527 & out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6735 = out_f_roready_673; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_673 = out_wivalid_1_527 & out_wimask_673; // @[RegisterRouter.scala:87:24] wire out_f_woready_673 = out_woready_1_527 & out_womask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6736 = ~out_rimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6737 = ~out_wimask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6738 = ~out_romask_673; // @[RegisterRouter.scala:87:24] wire _out_T_6739 = ~out_womask_673; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6741 = _out_T_6740; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_571 = _out_T_6741; // @[RegisterRouter.scala:87:24] wire out_rimask_674 = |_out_rimask_T_674; // @[RegisterRouter.scala:87:24] wire out_wimask_674 = &_out_wimask_T_674; // @[RegisterRouter.scala:87:24] wire out_romask_674 = |_out_romask_T_674; // @[RegisterRouter.scala:87:24] wire out_womask_674 = &_out_womask_T_674; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_674 = out_rivalid_1_528 & out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6743 = out_f_rivalid_674; // @[RegisterRouter.scala:87:24] wire out_f_roready_674 = out_roready_1_528 & out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6744 = out_f_roready_674; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_674 = out_wivalid_1_528 & out_wimask_674; // @[RegisterRouter.scala:87:24] wire out_f_woready_674 = out_woready_1_528 & out_womask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6745 = ~out_rimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6746 = ~out_wimask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6747 = ~out_romask_674; // @[RegisterRouter.scala:87:24] wire _out_T_6748 = ~out_womask_674; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_571 = {hi_306, flags_0_go, _out_prepend_T_571}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6749 = out_prepend_571; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6750 = _out_T_6749; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_572 = _out_T_6750; // @[RegisterRouter.scala:87:24] wire out_rimask_675 = |_out_rimask_T_675; // @[RegisterRouter.scala:87:24] wire out_wimask_675 = &_out_wimask_T_675; // @[RegisterRouter.scala:87:24] wire out_romask_675 = |_out_romask_T_675; // @[RegisterRouter.scala:87:24] wire out_womask_675 = &_out_womask_T_675; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_675 = out_rivalid_1_529 & out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6752 = out_f_rivalid_675; // @[RegisterRouter.scala:87:24] wire out_f_roready_675 = out_roready_1_529 & out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6753 = out_f_roready_675; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_675 = out_wivalid_1_529 & out_wimask_675; // @[RegisterRouter.scala:87:24] wire out_f_woready_675 = out_woready_1_529 & out_womask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6754 = ~out_rimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6755 = ~out_wimask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6756 = ~out_romask_675; // @[RegisterRouter.scala:87:24] wire _out_T_6757 = ~out_womask_675; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_572 = {hi_307, flags_0_go, _out_prepend_T_572}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6758 = out_prepend_572; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6759 = _out_T_6758; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_573 = _out_T_6759; // @[RegisterRouter.scala:87:24] wire out_rimask_676 = |_out_rimask_T_676; // @[RegisterRouter.scala:87:24] wire out_wimask_676 = &_out_wimask_T_676; // @[RegisterRouter.scala:87:24] wire out_romask_676 = |_out_romask_T_676; // @[RegisterRouter.scala:87:24] wire out_womask_676 = &_out_womask_T_676; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_676 = out_rivalid_1_530 & out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6761 = out_f_rivalid_676; // @[RegisterRouter.scala:87:24] wire out_f_roready_676 = out_roready_1_530 & out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6762 = out_f_roready_676; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_676 = out_wivalid_1_530 & out_wimask_676; // @[RegisterRouter.scala:87:24] wire out_f_woready_676 = out_woready_1_530 & out_womask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6763 = ~out_rimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6764 = ~out_wimask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6765 = ~out_romask_676; // @[RegisterRouter.scala:87:24] wire _out_T_6766 = ~out_womask_676; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_573 = {hi_308, flags_0_go, _out_prepend_T_573}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6767 = out_prepend_573; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6768 = _out_T_6767; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_574 = _out_T_6768; // @[RegisterRouter.scala:87:24] wire out_rimask_677 = |_out_rimask_T_677; // @[RegisterRouter.scala:87:24] wire out_wimask_677 = &_out_wimask_T_677; // @[RegisterRouter.scala:87:24] wire out_romask_677 = |_out_romask_T_677; // @[RegisterRouter.scala:87:24] wire out_womask_677 = &_out_womask_T_677; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_677 = out_rivalid_1_531 & out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6770 = out_f_rivalid_677; // @[RegisterRouter.scala:87:24] wire out_f_roready_677 = out_roready_1_531 & out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6771 = out_f_roready_677; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_677 = out_wivalid_1_531 & out_wimask_677; // @[RegisterRouter.scala:87:24] wire out_f_woready_677 = out_woready_1_531 & out_womask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6772 = ~out_rimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6773 = ~out_wimask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6774 = ~out_romask_677; // @[RegisterRouter.scala:87:24] wire _out_T_6775 = ~out_womask_677; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_574 = {hi_309, flags_0_go, _out_prepend_T_574}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6776 = out_prepend_574; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6777 = _out_T_6776; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_575 = _out_T_6777; // @[RegisterRouter.scala:87:24] wire out_rimask_678 = |_out_rimask_T_678; // @[RegisterRouter.scala:87:24] wire out_wimask_678 = &_out_wimask_T_678; // @[RegisterRouter.scala:87:24] wire out_romask_678 = |_out_romask_T_678; // @[RegisterRouter.scala:87:24] wire out_womask_678 = &_out_womask_T_678; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_678 = out_rivalid_1_532 & out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6779 = out_f_rivalid_678; // @[RegisterRouter.scala:87:24] wire out_f_roready_678 = out_roready_1_532 & out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6780 = out_f_roready_678; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_678 = out_wivalid_1_532 & out_wimask_678; // @[RegisterRouter.scala:87:24] wire out_f_woready_678 = out_woready_1_532 & out_womask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6781 = ~out_rimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6782 = ~out_wimask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6783 = ~out_romask_678; // @[RegisterRouter.scala:87:24] wire _out_T_6784 = ~out_womask_678; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_575 = {hi_310, flags_0_go, _out_prepend_T_575}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6785 = out_prepend_575; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6786 = _out_T_6785; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_576 = _out_T_6786; // @[RegisterRouter.scala:87:24] wire out_rimask_679 = |_out_rimask_T_679; // @[RegisterRouter.scala:87:24] wire out_wimask_679 = &_out_wimask_T_679; // @[RegisterRouter.scala:87:24] wire out_romask_679 = |_out_romask_T_679; // @[RegisterRouter.scala:87:24] wire out_womask_679 = &_out_womask_T_679; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_679 = out_rivalid_1_533 & out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6788 = out_f_rivalid_679; // @[RegisterRouter.scala:87:24] wire out_f_roready_679 = out_roready_1_533 & out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6789 = out_f_roready_679; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_679 = out_wivalid_1_533 & out_wimask_679; // @[RegisterRouter.scala:87:24] wire out_f_woready_679 = out_woready_1_533 & out_womask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6790 = ~out_rimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6791 = ~out_wimask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6792 = ~out_romask_679; // @[RegisterRouter.scala:87:24] wire _out_T_6793 = ~out_womask_679; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_576 = {hi_311, flags_0_go, _out_prepend_T_576}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6794 = out_prepend_576; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6795 = _out_T_6794; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_577 = _out_T_6795; // @[RegisterRouter.scala:87:24] wire out_rimask_680 = |_out_rimask_T_680; // @[RegisterRouter.scala:87:24] wire out_wimask_680 = &_out_wimask_T_680; // @[RegisterRouter.scala:87:24] wire out_romask_680 = |_out_romask_T_680; // @[RegisterRouter.scala:87:24] wire out_womask_680 = &_out_womask_T_680; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_680 = out_rivalid_1_534 & out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6797 = out_f_rivalid_680; // @[RegisterRouter.scala:87:24] wire out_f_roready_680 = out_roready_1_534 & out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6798 = out_f_roready_680; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_680 = out_wivalid_1_534 & out_wimask_680; // @[RegisterRouter.scala:87:24] wire out_f_woready_680 = out_woready_1_534 & out_womask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6799 = ~out_rimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6800 = ~out_wimask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6801 = ~out_romask_680; // @[RegisterRouter.scala:87:24] wire _out_T_6802 = ~out_womask_680; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_577 = {hi_312, flags_0_go, _out_prepend_T_577}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6803 = out_prepend_577; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6804 = _out_T_6803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_166 = _out_T_6804; // @[MuxLiteral.scala:49:48] wire out_rimask_681 = |_out_rimask_T_681; // @[RegisterRouter.scala:87:24] wire out_wimask_681 = &_out_wimask_T_681; // @[RegisterRouter.scala:87:24] wire out_romask_681 = |_out_romask_T_681; // @[RegisterRouter.scala:87:24] wire out_womask_681 = &_out_womask_T_681; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_681 = out_rivalid_1_535 & out_rimask_681; // @[RegisterRouter.scala:87:24] wire out_f_roready_681 = out_roready_1_535 & out_romask_681; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_681 = out_wivalid_1_535 & out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6806 = out_f_wivalid_681; // @[RegisterRouter.scala:87:24] assign out_f_woready_681 = out_woready_1_535 & out_womask_681; // @[RegisterRouter.scala:87:24] assign hartHaltedWrEn = out_f_woready_681; // @[RegisterRouter.scala:87:24] wire _out_T_6807 = out_f_woready_681; // @[RegisterRouter.scala:87:24] assign hartHaltedId = _out_T_6805; // @[RegisterRouter.scala:87:24] wire _out_T_6808 = ~out_rimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6809 = ~out_wimask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6810 = ~out_romask_681; // @[RegisterRouter.scala:87:24] wire _out_T_6811 = ~out_womask_681; // @[RegisterRouter.scala:87:24] wire out_rimask_682 = |_out_rimask_T_682; // @[RegisterRouter.scala:87:24] wire out_wimask_682 = &_out_wimask_T_682; // @[RegisterRouter.scala:87:24] wire out_romask_682 = |_out_romask_T_682; // @[RegisterRouter.scala:87:24] wire out_womask_682 = &_out_womask_T_682; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_682 = out_rivalid_1_536 & out_rimask_682; // @[RegisterRouter.scala:87:24] wire out_f_roready_682 = out_roready_1_536 & out_romask_682; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_682 = out_wivalid_1_536 & out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6815 = out_f_wivalid_682; // @[RegisterRouter.scala:87:24] assign out_f_woready_682 = out_woready_1_536 & out_womask_682; // @[RegisterRouter.scala:87:24] assign hartGoingWrEn = out_f_woready_682; // @[RegisterRouter.scala:87:24] wire _out_T_6816 = out_f_woready_682; // @[RegisterRouter.scala:87:24] assign hartGoingId = _out_T_6814; // @[RegisterRouter.scala:87:24] wire _out_T_6817 = ~out_rimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6818 = ~out_wimask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6819 = ~out_romask_682; // @[RegisterRouter.scala:87:24] wire _out_T_6820 = ~out_womask_682; // @[RegisterRouter.scala:87:24] wire out_rimask_683 = |_out_rimask_T_683; // @[RegisterRouter.scala:87:24] wire out_wimask_683 = &_out_wimask_T_683; // @[RegisterRouter.scala:87:24] wire out_romask_683 = |_out_romask_T_683; // @[RegisterRouter.scala:87:24] wire out_womask_683 = &_out_womask_T_683; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_683 = out_rivalid_1_537 & out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6824 = out_f_rivalid_683; // @[RegisterRouter.scala:87:24] wire out_f_roready_683 = out_roready_1_537 & out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6825 = out_f_roready_683; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_683 = out_wivalid_1_537 & out_wimask_683; // @[RegisterRouter.scala:87:24] wire out_f_woready_683 = out_woready_1_537 & out_womask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6826 = ~out_rimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6827 = ~out_wimask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6828 = ~out_romask_683; // @[RegisterRouter.scala:87:24] wire _out_T_6829 = ~out_womask_683; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6831 = _out_T_6830; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_579 = _out_T_6831; // @[RegisterRouter.scala:87:24] wire out_rimask_684 = |_out_rimask_T_684; // @[RegisterRouter.scala:87:24] wire out_wimask_684 = &_out_wimask_T_684; // @[RegisterRouter.scala:87:24] wire out_romask_684 = |_out_romask_T_684; // @[RegisterRouter.scala:87:24] wire out_womask_684 = &_out_womask_T_684; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_684 = out_rivalid_1_538 & out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6833 = out_f_rivalid_684; // @[RegisterRouter.scala:87:24] wire out_f_roready_684 = out_roready_1_538 & out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6834 = out_f_roready_684; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_684 = out_wivalid_1_538 & out_wimask_684; // @[RegisterRouter.scala:87:24] wire out_f_woready_684 = out_woready_1_538 & out_womask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6835 = ~out_rimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6836 = ~out_wimask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6837 = ~out_romask_684; // @[RegisterRouter.scala:87:24] wire _out_T_6838 = ~out_womask_684; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_579 = {hi_162, flags_0_go, _out_prepend_T_579}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6839 = out_prepend_579; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6840 = _out_T_6839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_580 = _out_T_6840; // @[RegisterRouter.scala:87:24] wire out_rimask_685 = |_out_rimask_T_685; // @[RegisterRouter.scala:87:24] wire out_wimask_685 = &_out_wimask_T_685; // @[RegisterRouter.scala:87:24] wire out_romask_685 = |_out_romask_T_685; // @[RegisterRouter.scala:87:24] wire out_womask_685 = &_out_womask_T_685; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_685 = out_rivalid_1_539 & out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6842 = out_f_rivalid_685; // @[RegisterRouter.scala:87:24] wire out_f_roready_685 = out_roready_1_539 & out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6843 = out_f_roready_685; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_685 = out_wivalid_1_539 & out_wimask_685; // @[RegisterRouter.scala:87:24] wire out_f_woready_685 = out_woready_1_539 & out_womask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6844 = ~out_rimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6845 = ~out_wimask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6846 = ~out_romask_685; // @[RegisterRouter.scala:87:24] wire _out_T_6847 = ~out_womask_685; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_580 = {hi_163, flags_0_go, _out_prepend_T_580}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6848 = out_prepend_580; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6849 = _out_T_6848; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_581 = _out_T_6849; // @[RegisterRouter.scala:87:24] wire out_rimask_686 = |_out_rimask_T_686; // @[RegisterRouter.scala:87:24] wire out_wimask_686 = &_out_wimask_T_686; // @[RegisterRouter.scala:87:24] wire out_romask_686 = |_out_romask_T_686; // @[RegisterRouter.scala:87:24] wire out_womask_686 = &_out_womask_T_686; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_686 = out_rivalid_1_540 & out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6851 = out_f_rivalid_686; // @[RegisterRouter.scala:87:24] wire out_f_roready_686 = out_roready_1_540 & out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6852 = out_f_roready_686; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_686 = out_wivalid_1_540 & out_wimask_686; // @[RegisterRouter.scala:87:24] wire out_f_woready_686 = out_woready_1_540 & out_womask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6853 = ~out_rimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6854 = ~out_wimask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6855 = ~out_romask_686; // @[RegisterRouter.scala:87:24] wire _out_T_6856 = ~out_womask_686; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_581 = {hi_164, flags_0_go, _out_prepend_T_581}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6857 = out_prepend_581; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_6858 = _out_T_6857; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_582 = _out_T_6858; // @[RegisterRouter.scala:87:24] wire out_rimask_687 = |_out_rimask_T_687; // @[RegisterRouter.scala:87:24] wire out_wimask_687 = &_out_wimask_T_687; // @[RegisterRouter.scala:87:24] wire out_romask_687 = |_out_romask_T_687; // @[RegisterRouter.scala:87:24] wire out_womask_687 = &_out_womask_T_687; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_687 = out_rivalid_1_541 & out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6860 = out_f_rivalid_687; // @[RegisterRouter.scala:87:24] wire out_f_roready_687 = out_roready_1_541 & out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6861 = out_f_roready_687; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_687 = out_wivalid_1_541 & out_wimask_687; // @[RegisterRouter.scala:87:24] wire out_f_woready_687 = out_woready_1_541 & out_womask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6862 = ~out_rimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6863 = ~out_wimask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6864 = ~out_romask_687; // @[RegisterRouter.scala:87:24] wire _out_T_6865 = ~out_womask_687; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_582 = {hi_165, flags_0_go, _out_prepend_T_582}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6866 = out_prepend_582; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_6867 = _out_T_6866; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_583 = _out_T_6867; // @[RegisterRouter.scala:87:24] wire out_rimask_688 = |_out_rimask_T_688; // @[RegisterRouter.scala:87:24] wire out_wimask_688 = &_out_wimask_T_688; // @[RegisterRouter.scala:87:24] wire out_romask_688 = |_out_romask_T_688; // @[RegisterRouter.scala:87:24] wire out_womask_688 = &_out_womask_T_688; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_688 = out_rivalid_1_542 & out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6869 = out_f_rivalid_688; // @[RegisterRouter.scala:87:24] wire out_f_roready_688 = out_roready_1_542 & out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6870 = out_f_roready_688; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_688 = out_wivalid_1_542 & out_wimask_688; // @[RegisterRouter.scala:87:24] wire out_f_woready_688 = out_woready_1_542 & out_womask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6871 = ~out_rimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6872 = ~out_wimask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6873 = ~out_romask_688; // @[RegisterRouter.scala:87:24] wire _out_T_6874 = ~out_womask_688; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_583 = {hi_166, flags_0_go, _out_prepend_T_583}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6875 = out_prepend_583; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_6876 = _out_T_6875; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_584 = _out_T_6876; // @[RegisterRouter.scala:87:24] wire out_rimask_689 = |_out_rimask_T_689; // @[RegisterRouter.scala:87:24] wire out_wimask_689 = &_out_wimask_T_689; // @[RegisterRouter.scala:87:24] wire out_romask_689 = |_out_romask_T_689; // @[RegisterRouter.scala:87:24] wire out_womask_689 = &_out_womask_T_689; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_689 = out_rivalid_1_543 & out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6878 = out_f_rivalid_689; // @[RegisterRouter.scala:87:24] wire out_f_roready_689 = out_roready_1_543 & out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6879 = out_f_roready_689; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_689 = out_wivalid_1_543 & out_wimask_689; // @[RegisterRouter.scala:87:24] wire out_f_woready_689 = out_woready_1_543 & out_womask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6880 = ~out_rimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6881 = ~out_wimask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6882 = ~out_romask_689; // @[RegisterRouter.scala:87:24] wire _out_T_6883 = ~out_womask_689; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_584 = {hi_167, flags_0_go, _out_prepend_T_584}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6884 = out_prepend_584; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_6885 = _out_T_6884; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_585 = _out_T_6885; // @[RegisterRouter.scala:87:24] wire out_rimask_690 = |_out_rimask_T_690; // @[RegisterRouter.scala:87:24] wire out_wimask_690 = &_out_wimask_T_690; // @[RegisterRouter.scala:87:24] wire out_romask_690 = |_out_romask_T_690; // @[RegisterRouter.scala:87:24] wire out_womask_690 = &_out_womask_T_690; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_690 = out_rivalid_1_544 & out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6887 = out_f_rivalid_690; // @[RegisterRouter.scala:87:24] wire out_f_roready_690 = out_roready_1_544 & out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6888 = out_f_roready_690; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_690 = out_wivalid_1_544 & out_wimask_690; // @[RegisterRouter.scala:87:24] wire out_f_woready_690 = out_woready_1_544 & out_womask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6889 = ~out_rimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6890 = ~out_wimask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6891 = ~out_romask_690; // @[RegisterRouter.scala:87:24] wire _out_T_6892 = ~out_womask_690; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_585 = {hi_168, flags_0_go, _out_prepend_T_585}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6893 = out_prepend_585; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_6894 = _out_T_6893; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_148 = _out_T_6894; // @[MuxLiteral.scala:49:48] wire out_rimask_691 = |_out_rimask_T_691; // @[RegisterRouter.scala:87:24] wire out_wimask_691 = &_out_wimask_T_691; // @[RegisterRouter.scala:87:24] wire out_romask_691 = |_out_romask_T_691; // @[RegisterRouter.scala:87:24] wire out_womask_691 = &_out_womask_T_691; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_691 = out_rivalid_1_545 & out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6896 = out_f_rivalid_691; // @[RegisterRouter.scala:87:24] wire out_f_roready_691 = out_roready_1_545 & out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6897 = out_f_roready_691; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_691 = out_wivalid_1_545 & out_wimask_691; // @[RegisterRouter.scala:87:24] wire out_f_woready_691 = out_woready_1_545 & out_womask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6898 = ~out_rimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6899 = ~out_wimask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6900 = ~out_romask_691; // @[RegisterRouter.scala:87:24] wire _out_T_6901 = ~out_womask_691; // @[RegisterRouter.scala:87:24] wire out_rimask_692 = |_out_rimask_T_692; // @[RegisterRouter.scala:87:24] wire out_wimask_692 = &_out_wimask_T_692; // @[RegisterRouter.scala:87:24] wire out_romask_692 = |_out_romask_T_692; // @[RegisterRouter.scala:87:24] wire out_womask_692 = &_out_womask_T_692; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_692 = out_rivalid_1_546 & out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6905 = out_f_rivalid_692; // @[RegisterRouter.scala:87:24] wire out_f_roready_692 = out_roready_1_546 & out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6906 = out_f_roready_692; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_692 = out_wivalid_1_546 & out_wimask_692; // @[RegisterRouter.scala:87:24] wire out_f_woready_692 = out_woready_1_546 & out_womask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6907 = ~out_rimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6908 = ~out_wimask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6909 = ~out_romask_692; // @[RegisterRouter.scala:87:24] wire _out_T_6910 = ~out_womask_692; // @[RegisterRouter.scala:87:24] wire out_rimask_693 = |_out_rimask_T_693; // @[RegisterRouter.scala:87:24] wire out_wimask_693 = &_out_wimask_T_693; // @[RegisterRouter.scala:87:24] wire out_romask_693 = |_out_romask_T_693; // @[RegisterRouter.scala:87:24] wire out_womask_693 = &_out_womask_T_693; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_693 = out_rivalid_1_547 & out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6914 = out_f_rivalid_693; // @[RegisterRouter.scala:87:24] wire out_f_roready_693 = out_roready_1_547 & out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6915 = out_f_roready_693; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_693 = out_wivalid_1_547 & out_wimask_693; // @[RegisterRouter.scala:87:24] wire out_f_woready_693 = out_woready_1_547 & out_womask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6916 = ~out_rimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6917 = ~out_wimask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6918 = ~out_romask_693; // @[RegisterRouter.scala:87:24] wire _out_T_6919 = ~out_womask_693; // @[RegisterRouter.scala:87:24] wire out_rimask_694 = |_out_rimask_T_694; // @[RegisterRouter.scala:87:24] wire out_wimask_694 = &_out_wimask_T_694; // @[RegisterRouter.scala:87:24] wire out_romask_694 = |_out_romask_T_694; // @[RegisterRouter.scala:87:24] wire out_womask_694 = &_out_womask_T_694; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_694 = out_rivalid_1_548 & out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6923 = out_f_rivalid_694; // @[RegisterRouter.scala:87:24] wire out_f_roready_694 = out_roready_1_548 & out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6924 = out_f_roready_694; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_694 = out_wivalid_1_548 & out_wimask_694; // @[RegisterRouter.scala:87:24] wire out_f_woready_694 = out_woready_1_548 & out_womask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6925 = ~out_rimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6926 = ~out_wimask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6927 = ~out_romask_694; // @[RegisterRouter.scala:87:24] wire _out_T_6928 = ~out_womask_694; // @[RegisterRouter.scala:87:24] wire out_rimask_695 = |_out_rimask_T_695; // @[RegisterRouter.scala:87:24] wire out_wimask_695 = &_out_wimask_T_695; // @[RegisterRouter.scala:87:24] wire out_romask_695 = |_out_romask_T_695; // @[RegisterRouter.scala:87:24] wire out_womask_695 = &_out_womask_T_695; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_695 = out_rivalid_1_549 & out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6932 = out_f_rivalid_695; // @[RegisterRouter.scala:87:24] wire out_f_roready_695 = out_roready_1_549 & out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6933 = out_f_roready_695; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_695 = out_wivalid_1_549 & out_wimask_695; // @[RegisterRouter.scala:87:24] wire out_f_woready_695 = out_woready_1_549 & out_womask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6934 = ~out_rimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6935 = ~out_wimask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6936 = ~out_romask_695; // @[RegisterRouter.scala:87:24] wire _out_T_6937 = ~out_womask_695; // @[RegisterRouter.scala:87:24] wire out_rimask_696 = |_out_rimask_T_696; // @[RegisterRouter.scala:87:24] wire out_wimask_696 = &_out_wimask_T_696; // @[RegisterRouter.scala:87:24] wire out_romask_696 = |_out_romask_T_696; // @[RegisterRouter.scala:87:24] wire out_womask_696 = &_out_womask_T_696; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_696 = out_rivalid_1_550 & out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6941 = out_f_rivalid_696; // @[RegisterRouter.scala:87:24] wire out_f_roready_696 = out_roready_1_550 & out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6942 = out_f_roready_696; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_696 = out_wivalid_1_550 & out_wimask_696; // @[RegisterRouter.scala:87:24] wire out_f_woready_696 = out_woready_1_550 & out_womask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6943 = ~out_rimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6944 = ~out_wimask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6945 = ~out_romask_696; // @[RegisterRouter.scala:87:24] wire _out_T_6946 = ~out_womask_696; // @[RegisterRouter.scala:87:24] wire out_rimask_697 = |_out_rimask_T_697; // @[RegisterRouter.scala:87:24] wire out_wimask_697 = &_out_wimask_T_697; // @[RegisterRouter.scala:87:24] wire out_romask_697 = |_out_romask_T_697; // @[RegisterRouter.scala:87:24] wire out_womask_697 = &_out_womask_T_697; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_697 = out_rivalid_1_551 & out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6950 = out_f_rivalid_697; // @[RegisterRouter.scala:87:24] wire out_f_roready_697 = out_roready_1_551 & out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6951 = out_f_roready_697; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_697 = out_wivalid_1_551 & out_wimask_697; // @[RegisterRouter.scala:87:24] wire out_f_woready_697 = out_woready_1_551 & out_womask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6952 = ~out_rimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6953 = ~out_wimask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6954 = ~out_romask_697; // @[RegisterRouter.scala:87:24] wire _out_T_6955 = ~out_womask_697; // @[RegisterRouter.scala:87:24] wire out_rimask_698 = |_out_rimask_T_698; // @[RegisterRouter.scala:87:24] wire out_wimask_698 = &_out_wimask_T_698; // @[RegisterRouter.scala:87:24] wire out_romask_698 = |_out_romask_T_698; // @[RegisterRouter.scala:87:24] wire out_womask_698 = &_out_womask_T_698; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_698 = out_rivalid_1_552 & out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6959 = out_f_rivalid_698; // @[RegisterRouter.scala:87:24] wire out_f_roready_698 = out_roready_1_552 & out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6960 = out_f_roready_698; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_698 = out_wivalid_1_552 & out_wimask_698; // @[RegisterRouter.scala:87:24] wire out_f_woready_698 = out_woready_1_552 & out_womask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6961 = ~out_rimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6962 = ~out_wimask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6963 = ~out_romask_698; // @[RegisterRouter.scala:87:24] wire _out_T_6964 = ~out_womask_698; // @[RegisterRouter.scala:87:24] wire out_rimask_699 = |_out_rimask_T_699; // @[RegisterRouter.scala:87:24] wire out_wimask_699 = &_out_wimask_T_699; // @[RegisterRouter.scala:87:24] wire out_romask_699 = |_out_romask_T_699; // @[RegisterRouter.scala:87:24] wire out_womask_699 = &_out_womask_T_699; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_699 = out_rivalid_1_553 & out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6968 = out_f_rivalid_699; // @[RegisterRouter.scala:87:24] wire out_f_roready_699 = out_roready_1_553 & out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6969 = out_f_roready_699; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_699 = out_wivalid_1_553 & out_wimask_699; // @[RegisterRouter.scala:87:24] wire out_f_woready_699 = out_woready_1_553 & out_womask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6970 = ~out_rimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6971 = ~out_wimask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6972 = ~out_romask_699; // @[RegisterRouter.scala:87:24] wire _out_T_6973 = ~out_womask_699; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6975 = _out_T_6974; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_593 = _out_T_6975; // @[RegisterRouter.scala:87:24] wire out_rimask_700 = |_out_rimask_T_700; // @[RegisterRouter.scala:87:24] wire out_wimask_700 = &_out_wimask_T_700; // @[RegisterRouter.scala:87:24] wire out_romask_700 = |_out_romask_T_700; // @[RegisterRouter.scala:87:24] wire out_womask_700 = &_out_womask_T_700; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_700 = out_rivalid_1_554 & out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6977 = out_f_rivalid_700; // @[RegisterRouter.scala:87:24] wire out_f_roready_700 = out_roready_1_554 & out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6978 = out_f_roready_700; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_700 = out_wivalid_1_554 & out_wimask_700; // @[RegisterRouter.scala:87:24] wire out_f_woready_700 = out_woready_1_554 & out_womask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6979 = ~out_rimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6980 = ~out_wimask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6981 = ~out_romask_700; // @[RegisterRouter.scala:87:24] wire _out_T_6982 = ~out_womask_700; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_593 = {hi_266, flags_0_go, _out_prepend_T_593}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6983 = out_prepend_593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_6984 = _out_T_6983; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_594 = _out_T_6984; // @[RegisterRouter.scala:87:24] wire out_rimask_701 = |_out_rimask_T_701; // @[RegisterRouter.scala:87:24] wire out_wimask_701 = &_out_wimask_T_701; // @[RegisterRouter.scala:87:24] wire out_romask_701 = |_out_romask_T_701; // @[RegisterRouter.scala:87:24] wire out_womask_701 = &_out_womask_T_701; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_701 = out_rivalid_1_555 & out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6986 = out_f_rivalid_701; // @[RegisterRouter.scala:87:24] wire out_f_roready_701 = out_roready_1_555 & out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6987 = out_f_roready_701; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_701 = out_wivalid_1_555 & out_wimask_701; // @[RegisterRouter.scala:87:24] wire out_f_woready_701 = out_woready_1_555 & out_womask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6988 = ~out_rimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6989 = ~out_wimask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6990 = ~out_romask_701; // @[RegisterRouter.scala:87:24] wire _out_T_6991 = ~out_womask_701; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_594 = {hi_267, flags_0_go, _out_prepend_T_594}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6992 = out_prepend_594; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_6993 = _out_T_6992; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_595 = _out_T_6993; // @[RegisterRouter.scala:87:24] wire out_rimask_702 = |_out_rimask_T_702; // @[RegisterRouter.scala:87:24] wire out_wimask_702 = &_out_wimask_T_702; // @[RegisterRouter.scala:87:24] wire out_romask_702 = |_out_romask_T_702; // @[RegisterRouter.scala:87:24] wire out_womask_702 = &_out_womask_T_702; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_702 = out_rivalid_1_556 & out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6995 = out_f_rivalid_702; // @[RegisterRouter.scala:87:24] wire out_f_roready_702 = out_roready_1_556 & out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6996 = out_f_roready_702; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_702 = out_wivalid_1_556 & out_wimask_702; // @[RegisterRouter.scala:87:24] wire out_f_woready_702 = out_woready_1_556 & out_womask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6997 = ~out_rimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6998 = ~out_wimask_702; // @[RegisterRouter.scala:87:24] wire _out_T_6999 = ~out_romask_702; // @[RegisterRouter.scala:87:24] wire _out_T_7000 = ~out_womask_702; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_595 = {hi_268, flags_0_go, _out_prepend_T_595}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7001 = out_prepend_595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7002 = _out_T_7001; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_596 = _out_T_7002; // @[RegisterRouter.scala:87:24] wire out_rimask_703 = |_out_rimask_T_703; // @[RegisterRouter.scala:87:24] wire out_wimask_703 = &_out_wimask_T_703; // @[RegisterRouter.scala:87:24] wire out_romask_703 = |_out_romask_T_703; // @[RegisterRouter.scala:87:24] wire out_womask_703 = &_out_womask_T_703; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_703 = out_rivalid_1_557 & out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7004 = out_f_rivalid_703; // @[RegisterRouter.scala:87:24] wire out_f_roready_703 = out_roready_1_557 & out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7005 = out_f_roready_703; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_703 = out_wivalid_1_557 & out_wimask_703; // @[RegisterRouter.scala:87:24] wire out_f_woready_703 = out_woready_1_557 & out_womask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7006 = ~out_rimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7007 = ~out_wimask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7008 = ~out_romask_703; // @[RegisterRouter.scala:87:24] wire _out_T_7009 = ~out_womask_703; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_596 = {hi_269, flags_0_go, _out_prepend_T_596}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7010 = out_prepend_596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7011 = _out_T_7010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_597 = _out_T_7011; // @[RegisterRouter.scala:87:24] wire out_rimask_704 = |_out_rimask_T_704; // @[RegisterRouter.scala:87:24] wire out_wimask_704 = &_out_wimask_T_704; // @[RegisterRouter.scala:87:24] wire out_romask_704 = |_out_romask_T_704; // @[RegisterRouter.scala:87:24] wire out_womask_704 = &_out_womask_T_704; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_704 = out_rivalid_1_558 & out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7013 = out_f_rivalid_704; // @[RegisterRouter.scala:87:24] wire out_f_roready_704 = out_roready_1_558 & out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7014 = out_f_roready_704; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_704 = out_wivalid_1_558 & out_wimask_704; // @[RegisterRouter.scala:87:24] wire out_f_woready_704 = out_woready_1_558 & out_womask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7015 = ~out_rimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7016 = ~out_wimask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7017 = ~out_romask_704; // @[RegisterRouter.scala:87:24] wire _out_T_7018 = ~out_womask_704; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_597 = {hi_270, flags_0_go, _out_prepend_T_597}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7019 = out_prepend_597; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7020 = _out_T_7019; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_598 = _out_T_7020; // @[RegisterRouter.scala:87:24] wire out_rimask_705 = |_out_rimask_T_705; // @[RegisterRouter.scala:87:24] wire out_wimask_705 = &_out_wimask_T_705; // @[RegisterRouter.scala:87:24] wire out_romask_705 = |_out_romask_T_705; // @[RegisterRouter.scala:87:24] wire out_womask_705 = &_out_womask_T_705; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_705 = out_rivalid_1_559 & out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7022 = out_f_rivalid_705; // @[RegisterRouter.scala:87:24] wire out_f_roready_705 = out_roready_1_559 & out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7023 = out_f_roready_705; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_705 = out_wivalid_1_559 & out_wimask_705; // @[RegisterRouter.scala:87:24] wire out_f_woready_705 = out_woready_1_559 & out_womask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7024 = ~out_rimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7025 = ~out_wimask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7026 = ~out_romask_705; // @[RegisterRouter.scala:87:24] wire _out_T_7027 = ~out_womask_705; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_598 = {hi_271, flags_0_go, _out_prepend_T_598}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7028 = out_prepend_598; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7029 = _out_T_7028; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_599 = _out_T_7029; // @[RegisterRouter.scala:87:24] wire out_rimask_706 = |_out_rimask_T_706; // @[RegisterRouter.scala:87:24] wire out_wimask_706 = &_out_wimask_T_706; // @[RegisterRouter.scala:87:24] wire out_romask_706 = |_out_romask_T_706; // @[RegisterRouter.scala:87:24] wire out_womask_706 = &_out_womask_T_706; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_706 = out_rivalid_1_560 & out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7031 = out_f_rivalid_706; // @[RegisterRouter.scala:87:24] wire out_f_roready_706 = out_roready_1_560 & out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7032 = out_f_roready_706; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_706 = out_wivalid_1_560 & out_wimask_706; // @[RegisterRouter.scala:87:24] wire out_f_woready_706 = out_woready_1_560 & out_womask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7033 = ~out_rimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7034 = ~out_wimask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7035 = ~out_romask_706; // @[RegisterRouter.scala:87:24] wire _out_T_7036 = ~out_womask_706; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_599 = {hi_272, flags_0_go, _out_prepend_T_599}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7037 = out_prepend_599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7038 = _out_T_7037; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_161 = _out_T_7038; // @[MuxLiteral.scala:49:48] wire out_rimask_707 = |_out_rimask_T_707; // @[RegisterRouter.scala:87:24] wire out_wimask_707 = &_out_wimask_T_707; // @[RegisterRouter.scala:87:24] wire out_romask_707 = |_out_romask_T_707; // @[RegisterRouter.scala:87:24] wire out_womask_707 = &_out_womask_T_707; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_707 = out_rivalid_1_561 & out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7040 = out_f_rivalid_707; // @[RegisterRouter.scala:87:24] wire out_f_roready_707 = out_roready_1_561 & out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7041 = out_f_roready_707; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_707 = out_wivalid_1_561 & out_wimask_707; // @[RegisterRouter.scala:87:24] wire out_f_woready_707 = out_woready_1_561 & out_womask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7042 = ~out_rimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7043 = ~out_wimask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7044 = ~out_romask_707; // @[RegisterRouter.scala:87:24] wire _out_T_7045 = ~out_womask_707; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7047 = _out_T_7046; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_600 = _out_T_7047; // @[RegisterRouter.scala:87:24] wire out_rimask_708 = |_out_rimask_T_708; // @[RegisterRouter.scala:87:24] wire out_wimask_708 = &_out_wimask_T_708; // @[RegisterRouter.scala:87:24] wire out_romask_708 = |_out_romask_T_708; // @[RegisterRouter.scala:87:24] wire out_womask_708 = &_out_womask_T_708; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_708 = out_rivalid_1_562 & out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7049 = out_f_rivalid_708; // @[RegisterRouter.scala:87:24] wire out_f_roready_708 = out_roready_1_562 & out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7050 = out_f_roready_708; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_708 = out_wivalid_1_562 & out_wimask_708; // @[RegisterRouter.scala:87:24] wire out_f_woready_708 = out_woready_1_562 & out_womask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7051 = ~out_rimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7052 = ~out_wimask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7053 = ~out_romask_708; // @[RegisterRouter.scala:87:24] wire _out_T_7054 = ~out_womask_708; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_600 = {hi_418, flags_0_go, _out_prepend_T_600}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7055 = out_prepend_600; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7056 = _out_T_7055; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_601 = _out_T_7056; // @[RegisterRouter.scala:87:24] wire out_rimask_709 = |_out_rimask_T_709; // @[RegisterRouter.scala:87:24] wire out_wimask_709 = &_out_wimask_T_709; // @[RegisterRouter.scala:87:24] wire out_romask_709 = |_out_romask_T_709; // @[RegisterRouter.scala:87:24] wire out_womask_709 = &_out_womask_T_709; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_709 = out_rivalid_1_563 & out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7058 = out_f_rivalid_709; // @[RegisterRouter.scala:87:24] wire out_f_roready_709 = out_roready_1_563 & out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7059 = out_f_roready_709; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_709 = out_wivalid_1_563 & out_wimask_709; // @[RegisterRouter.scala:87:24] wire out_f_woready_709 = out_woready_1_563 & out_womask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7060 = ~out_rimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7061 = ~out_wimask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7062 = ~out_romask_709; // @[RegisterRouter.scala:87:24] wire _out_T_7063 = ~out_womask_709; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_601 = {hi_419, flags_0_go, _out_prepend_T_601}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7064 = out_prepend_601; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7065 = _out_T_7064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_602 = _out_T_7065; // @[RegisterRouter.scala:87:24] wire out_rimask_710 = |_out_rimask_T_710; // @[RegisterRouter.scala:87:24] wire out_wimask_710 = &_out_wimask_T_710; // @[RegisterRouter.scala:87:24] wire out_romask_710 = |_out_romask_T_710; // @[RegisterRouter.scala:87:24] wire out_womask_710 = &_out_womask_T_710; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_710 = out_rivalid_1_564 & out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7067 = out_f_rivalid_710; // @[RegisterRouter.scala:87:24] wire out_f_roready_710 = out_roready_1_564 & out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7068 = out_f_roready_710; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_710 = out_wivalid_1_564 & out_wimask_710; // @[RegisterRouter.scala:87:24] wire out_f_woready_710 = out_woready_1_564 & out_womask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7069 = ~out_rimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7070 = ~out_wimask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7071 = ~out_romask_710; // @[RegisterRouter.scala:87:24] wire _out_T_7072 = ~out_womask_710; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_602 = {hi_420, flags_0_go, _out_prepend_T_602}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7073 = out_prepend_602; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7074 = _out_T_7073; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_603 = _out_T_7074; // @[RegisterRouter.scala:87:24] wire out_rimask_711 = |_out_rimask_T_711; // @[RegisterRouter.scala:87:24] wire out_wimask_711 = &_out_wimask_T_711; // @[RegisterRouter.scala:87:24] wire out_romask_711 = |_out_romask_T_711; // @[RegisterRouter.scala:87:24] wire out_womask_711 = &_out_womask_T_711; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_711 = out_rivalid_1_565 & out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7076 = out_f_rivalid_711; // @[RegisterRouter.scala:87:24] wire out_f_roready_711 = out_roready_1_565 & out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7077 = out_f_roready_711; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_711 = out_wivalid_1_565 & out_wimask_711; // @[RegisterRouter.scala:87:24] wire out_f_woready_711 = out_woready_1_565 & out_womask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7078 = ~out_rimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7079 = ~out_wimask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7080 = ~out_romask_711; // @[RegisterRouter.scala:87:24] wire _out_T_7081 = ~out_womask_711; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_603 = {hi_421, flags_0_go, _out_prepend_T_603}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7082 = out_prepend_603; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7083 = _out_T_7082; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_604 = _out_T_7083; // @[RegisterRouter.scala:87:24] wire out_rimask_712 = |_out_rimask_T_712; // @[RegisterRouter.scala:87:24] wire out_wimask_712 = &_out_wimask_T_712; // @[RegisterRouter.scala:87:24] wire out_romask_712 = |_out_romask_T_712; // @[RegisterRouter.scala:87:24] wire out_womask_712 = &_out_womask_T_712; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_712 = out_rivalid_1_566 & out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7085 = out_f_rivalid_712; // @[RegisterRouter.scala:87:24] wire out_f_roready_712 = out_roready_1_566 & out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7086 = out_f_roready_712; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_712 = out_wivalid_1_566 & out_wimask_712; // @[RegisterRouter.scala:87:24] wire out_f_woready_712 = out_woready_1_566 & out_womask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7087 = ~out_rimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7088 = ~out_wimask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7089 = ~out_romask_712; // @[RegisterRouter.scala:87:24] wire _out_T_7090 = ~out_womask_712; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_604 = {hi_422, flags_0_go, _out_prepend_T_604}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7091 = out_prepend_604; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7092 = _out_T_7091; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_605 = _out_T_7092; // @[RegisterRouter.scala:87:24] wire out_rimask_713 = |_out_rimask_T_713; // @[RegisterRouter.scala:87:24] wire out_wimask_713 = &_out_wimask_T_713; // @[RegisterRouter.scala:87:24] wire out_romask_713 = |_out_romask_T_713; // @[RegisterRouter.scala:87:24] wire out_womask_713 = &_out_womask_T_713; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_713 = out_rivalid_1_567 & out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7094 = out_f_rivalid_713; // @[RegisterRouter.scala:87:24] wire out_f_roready_713 = out_roready_1_567 & out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7095 = out_f_roready_713; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_713 = out_wivalid_1_567 & out_wimask_713; // @[RegisterRouter.scala:87:24] wire out_f_woready_713 = out_woready_1_567 & out_womask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7096 = ~out_rimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7097 = ~out_wimask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7098 = ~out_romask_713; // @[RegisterRouter.scala:87:24] wire _out_T_7099 = ~out_womask_713; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_605 = {hi_423, flags_0_go, _out_prepend_T_605}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7100 = out_prepend_605; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7101 = _out_T_7100; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_606 = _out_T_7101; // @[RegisterRouter.scala:87:24] wire out_rimask_714 = |_out_rimask_T_714; // @[RegisterRouter.scala:87:24] wire out_wimask_714 = &_out_wimask_T_714; // @[RegisterRouter.scala:87:24] wire out_romask_714 = |_out_romask_T_714; // @[RegisterRouter.scala:87:24] wire out_womask_714 = &_out_womask_T_714; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_714 = out_rivalid_1_568 & out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7103 = out_f_rivalid_714; // @[RegisterRouter.scala:87:24] wire out_f_roready_714 = out_roready_1_568 & out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7104 = out_f_roready_714; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_714 = out_wivalid_1_568 & out_wimask_714; // @[RegisterRouter.scala:87:24] wire out_f_woready_714 = out_woready_1_568 & out_womask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7105 = ~out_rimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7106 = ~out_wimask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7107 = ~out_romask_714; // @[RegisterRouter.scala:87:24] wire _out_T_7108 = ~out_womask_714; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_606 = {hi_424, flags_0_go, _out_prepend_T_606}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7109 = out_prepend_606; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7110 = _out_T_7109; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_180 = _out_T_7110; // @[MuxLiteral.scala:49:48] wire out_rimask_715 = |_out_rimask_T_715; // @[RegisterRouter.scala:87:24] wire out_wimask_715 = &_out_wimask_T_715; // @[RegisterRouter.scala:87:24] wire out_romask_715 = |_out_romask_T_715; // @[RegisterRouter.scala:87:24] wire out_womask_715 = &_out_womask_T_715; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_715 = out_rivalid_1_569 & out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7112 = out_f_rivalid_715; // @[RegisterRouter.scala:87:24] wire out_f_roready_715 = out_roready_1_569 & out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7113 = out_f_roready_715; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_715 = out_wivalid_1_569 & out_wimask_715; // @[RegisterRouter.scala:87:24] wire out_f_woready_715 = out_woready_1_569 & out_womask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7114 = ~out_rimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7115 = ~out_wimask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7116 = ~out_romask_715; // @[RegisterRouter.scala:87:24] wire _out_T_7117 = ~out_womask_715; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7119 = _out_T_7118; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_607 = _out_T_7119; // @[RegisterRouter.scala:87:24] wire out_rimask_716 = |_out_rimask_T_716; // @[RegisterRouter.scala:87:24] wire out_wimask_716 = &_out_wimask_T_716; // @[RegisterRouter.scala:87:24] wire out_romask_716 = |_out_romask_T_716; // @[RegisterRouter.scala:87:24] wire out_womask_716 = &_out_womask_T_716; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_716 = out_rivalid_1_570 & out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7121 = out_f_rivalid_716; // @[RegisterRouter.scala:87:24] wire out_f_roready_716 = out_roready_1_570 & out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7122 = out_f_roready_716; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_716 = out_wivalid_1_570 & out_wimask_716; // @[RegisterRouter.scala:87:24] wire out_f_woready_716 = out_woready_1_570 & out_womask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7123 = ~out_rimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7124 = ~out_wimask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7125 = ~out_romask_716; // @[RegisterRouter.scala:87:24] wire _out_T_7126 = ~out_womask_716; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_607 = {hi_170, flags_0_go, _out_prepend_T_607}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7127 = out_prepend_607; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7128 = _out_T_7127; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_608 = _out_T_7128; // @[RegisterRouter.scala:87:24] wire out_rimask_717 = |_out_rimask_T_717; // @[RegisterRouter.scala:87:24] wire out_wimask_717 = &_out_wimask_T_717; // @[RegisterRouter.scala:87:24] wire out_romask_717 = |_out_romask_T_717; // @[RegisterRouter.scala:87:24] wire out_womask_717 = &_out_womask_T_717; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_717 = out_rivalid_1_571 & out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7130 = out_f_rivalid_717; // @[RegisterRouter.scala:87:24] wire out_f_roready_717 = out_roready_1_571 & out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7131 = out_f_roready_717; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_717 = out_wivalid_1_571 & out_wimask_717; // @[RegisterRouter.scala:87:24] wire out_f_woready_717 = out_woready_1_571 & out_womask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7132 = ~out_rimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7133 = ~out_wimask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7134 = ~out_romask_717; // @[RegisterRouter.scala:87:24] wire _out_T_7135 = ~out_womask_717; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_608 = {hi_171, flags_0_go, _out_prepend_T_608}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7136 = out_prepend_608; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7137 = _out_T_7136; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_609 = _out_T_7137; // @[RegisterRouter.scala:87:24] wire out_rimask_718 = |_out_rimask_T_718; // @[RegisterRouter.scala:87:24] wire out_wimask_718 = &_out_wimask_T_718; // @[RegisterRouter.scala:87:24] wire out_romask_718 = |_out_romask_T_718; // @[RegisterRouter.scala:87:24] wire out_womask_718 = &_out_womask_T_718; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_718 = out_rivalid_1_572 & out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7139 = out_f_rivalid_718; // @[RegisterRouter.scala:87:24] wire out_f_roready_718 = out_roready_1_572 & out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7140 = out_f_roready_718; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_718 = out_wivalid_1_572 & out_wimask_718; // @[RegisterRouter.scala:87:24] wire out_f_woready_718 = out_woready_1_572 & out_womask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7141 = ~out_rimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7142 = ~out_wimask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7143 = ~out_romask_718; // @[RegisterRouter.scala:87:24] wire _out_T_7144 = ~out_womask_718; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_609 = {hi_172, flags_0_go, _out_prepend_T_609}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7145 = out_prepend_609; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7146 = _out_T_7145; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_610 = _out_T_7146; // @[RegisterRouter.scala:87:24] wire out_rimask_719 = |_out_rimask_T_719; // @[RegisterRouter.scala:87:24] wire out_wimask_719 = &_out_wimask_T_719; // @[RegisterRouter.scala:87:24] wire out_romask_719 = |_out_romask_T_719; // @[RegisterRouter.scala:87:24] wire out_womask_719 = &_out_womask_T_719; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_719 = out_rivalid_1_573 & out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7148 = out_f_rivalid_719; // @[RegisterRouter.scala:87:24] wire out_f_roready_719 = out_roready_1_573 & out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7149 = out_f_roready_719; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_719 = out_wivalid_1_573 & out_wimask_719; // @[RegisterRouter.scala:87:24] wire out_f_woready_719 = out_woready_1_573 & out_womask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7150 = ~out_rimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7151 = ~out_wimask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7152 = ~out_romask_719; // @[RegisterRouter.scala:87:24] wire _out_T_7153 = ~out_womask_719; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_610 = {hi_173, flags_0_go, _out_prepend_T_610}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7154 = out_prepend_610; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7155 = _out_T_7154; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_611 = _out_T_7155; // @[RegisterRouter.scala:87:24] wire out_rimask_720 = |_out_rimask_T_720; // @[RegisterRouter.scala:87:24] wire out_wimask_720 = &_out_wimask_T_720; // @[RegisterRouter.scala:87:24] wire out_romask_720 = |_out_romask_T_720; // @[RegisterRouter.scala:87:24] wire out_womask_720 = &_out_womask_T_720; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_720 = out_rivalid_1_574 & out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7157 = out_f_rivalid_720; // @[RegisterRouter.scala:87:24] wire out_f_roready_720 = out_roready_1_574 & out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7158 = out_f_roready_720; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_720 = out_wivalid_1_574 & out_wimask_720; // @[RegisterRouter.scala:87:24] wire out_f_woready_720 = out_woready_1_574 & out_womask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7159 = ~out_rimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7160 = ~out_wimask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7161 = ~out_romask_720; // @[RegisterRouter.scala:87:24] wire _out_T_7162 = ~out_womask_720; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_611 = {hi_174, flags_0_go, _out_prepend_T_611}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7163 = out_prepend_611; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7164 = _out_T_7163; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_612 = _out_T_7164; // @[RegisterRouter.scala:87:24] wire out_rimask_721 = |_out_rimask_T_721; // @[RegisterRouter.scala:87:24] wire out_wimask_721 = &_out_wimask_T_721; // @[RegisterRouter.scala:87:24] wire out_romask_721 = |_out_romask_T_721; // @[RegisterRouter.scala:87:24] wire out_womask_721 = &_out_womask_T_721; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_721 = out_rivalid_1_575 & out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7166 = out_f_rivalid_721; // @[RegisterRouter.scala:87:24] wire out_f_roready_721 = out_roready_1_575 & out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7167 = out_f_roready_721; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_721 = out_wivalid_1_575 & out_wimask_721; // @[RegisterRouter.scala:87:24] wire out_f_woready_721 = out_woready_1_575 & out_womask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7168 = ~out_rimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7169 = ~out_wimask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7170 = ~out_romask_721; // @[RegisterRouter.scala:87:24] wire _out_T_7171 = ~out_womask_721; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_612 = {hi_175, flags_0_go, _out_prepend_T_612}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7172 = out_prepend_612; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7173 = _out_T_7172; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_613 = _out_T_7173; // @[RegisterRouter.scala:87:24] wire out_rimask_722 = |_out_rimask_T_722; // @[RegisterRouter.scala:87:24] wire out_wimask_722 = &_out_wimask_T_722; // @[RegisterRouter.scala:87:24] wire out_romask_722 = |_out_romask_T_722; // @[RegisterRouter.scala:87:24] wire out_womask_722 = &_out_womask_T_722; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_722 = out_rivalid_1_576 & out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7175 = out_f_rivalid_722; // @[RegisterRouter.scala:87:24] wire out_f_roready_722 = out_roready_1_576 & out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7176 = out_f_roready_722; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_722 = out_wivalid_1_576 & out_wimask_722; // @[RegisterRouter.scala:87:24] wire out_f_woready_722 = out_woready_1_576 & out_womask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7177 = ~out_rimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7178 = ~out_wimask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7179 = ~out_romask_722; // @[RegisterRouter.scala:87:24] wire _out_T_7180 = ~out_womask_722; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_613 = {hi_176, flags_0_go, _out_prepend_T_613}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7181 = out_prepend_613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7182 = _out_T_7181; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_149 = _out_T_7182; // @[MuxLiteral.scala:49:48] wire out_rimask_723 = |_out_rimask_T_723; // @[RegisterRouter.scala:87:24] wire out_wimask_723 = &_out_wimask_T_723; // @[RegisterRouter.scala:87:24] wire out_romask_723 = |_out_romask_T_723; // @[RegisterRouter.scala:87:24] wire out_womask_723 = &_out_womask_T_723; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_723 = out_rivalid_1_577 & out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7184 = out_f_rivalid_723; // @[RegisterRouter.scala:87:24] wire out_f_roready_723 = out_roready_1_577 & out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7185 = out_f_roready_723; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_723 = out_wivalid_1_577 & out_wimask_723; // @[RegisterRouter.scala:87:24] wire out_f_woready_723 = out_woready_1_577 & out_womask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7186 = ~out_rimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7187 = ~out_wimask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7188 = ~out_romask_723; // @[RegisterRouter.scala:87:24] wire _out_T_7189 = ~out_womask_723; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7191 = _out_T_7190; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_614 = _out_T_7191; // @[RegisterRouter.scala:87:24] wire out_rimask_724 = |_out_rimask_T_724; // @[RegisterRouter.scala:87:24] wire out_wimask_724 = &_out_wimask_T_724; // @[RegisterRouter.scala:87:24] wire out_romask_724 = |_out_romask_T_724; // @[RegisterRouter.scala:87:24] wire out_womask_724 = &_out_womask_T_724; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_724 = out_rivalid_1_578 & out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7193 = out_f_rivalid_724; // @[RegisterRouter.scala:87:24] wire out_f_roready_724 = out_roready_1_578 & out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7194 = out_f_roready_724; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_724 = out_wivalid_1_578 & out_wimask_724; // @[RegisterRouter.scala:87:24] wire out_f_woready_724 = out_woready_1_578 & out_womask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7195 = ~out_rimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7196 = ~out_wimask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7197 = ~out_romask_724; // @[RegisterRouter.scala:87:24] wire _out_T_7198 = ~out_womask_724; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_614 = {hi_386, flags_0_go, _out_prepend_T_614}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7199 = out_prepend_614; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7200 = _out_T_7199; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_615 = _out_T_7200; // @[RegisterRouter.scala:87:24] wire out_rimask_725 = |_out_rimask_T_725; // @[RegisterRouter.scala:87:24] wire out_wimask_725 = &_out_wimask_T_725; // @[RegisterRouter.scala:87:24] wire out_romask_725 = |_out_romask_T_725; // @[RegisterRouter.scala:87:24] wire out_womask_725 = &_out_womask_T_725; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_725 = out_rivalid_1_579 & out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7202 = out_f_rivalid_725; // @[RegisterRouter.scala:87:24] wire out_f_roready_725 = out_roready_1_579 & out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7203 = out_f_roready_725; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_725 = out_wivalid_1_579 & out_wimask_725; // @[RegisterRouter.scala:87:24] wire out_f_woready_725 = out_woready_1_579 & out_womask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7204 = ~out_rimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7205 = ~out_wimask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7206 = ~out_romask_725; // @[RegisterRouter.scala:87:24] wire _out_T_7207 = ~out_womask_725; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_615 = {hi_387, flags_0_go, _out_prepend_T_615}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7208 = out_prepend_615; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7209 = _out_T_7208; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_616 = _out_T_7209; // @[RegisterRouter.scala:87:24] wire out_rimask_726 = |_out_rimask_T_726; // @[RegisterRouter.scala:87:24] wire out_wimask_726 = &_out_wimask_T_726; // @[RegisterRouter.scala:87:24] wire out_romask_726 = |_out_romask_T_726; // @[RegisterRouter.scala:87:24] wire out_womask_726 = &_out_womask_T_726; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_726 = out_rivalid_1_580 & out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7211 = out_f_rivalid_726; // @[RegisterRouter.scala:87:24] wire out_f_roready_726 = out_roready_1_580 & out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7212 = out_f_roready_726; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_726 = out_wivalid_1_580 & out_wimask_726; // @[RegisterRouter.scala:87:24] wire out_f_woready_726 = out_woready_1_580 & out_womask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7213 = ~out_rimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7214 = ~out_wimask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7215 = ~out_romask_726; // @[RegisterRouter.scala:87:24] wire _out_T_7216 = ~out_womask_726; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_616 = {hi_388, flags_0_go, _out_prepend_T_616}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7217 = out_prepend_616; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7218 = _out_T_7217; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_617 = _out_T_7218; // @[RegisterRouter.scala:87:24] wire out_rimask_727 = |_out_rimask_T_727; // @[RegisterRouter.scala:87:24] wire out_wimask_727 = &_out_wimask_T_727; // @[RegisterRouter.scala:87:24] wire out_romask_727 = |_out_romask_T_727; // @[RegisterRouter.scala:87:24] wire out_womask_727 = &_out_womask_T_727; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_727 = out_rivalid_1_581 & out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7220 = out_f_rivalid_727; // @[RegisterRouter.scala:87:24] wire out_f_roready_727 = out_roready_1_581 & out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7221 = out_f_roready_727; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_727 = out_wivalid_1_581 & out_wimask_727; // @[RegisterRouter.scala:87:24] wire out_f_woready_727 = out_woready_1_581 & out_womask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7222 = ~out_rimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7223 = ~out_wimask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7224 = ~out_romask_727; // @[RegisterRouter.scala:87:24] wire _out_T_7225 = ~out_womask_727; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_617 = {hi_389, flags_0_go, _out_prepend_T_617}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7226 = out_prepend_617; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7227 = _out_T_7226; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_618 = _out_T_7227; // @[RegisterRouter.scala:87:24] wire out_rimask_728 = |_out_rimask_T_728; // @[RegisterRouter.scala:87:24] wire out_wimask_728 = &_out_wimask_T_728; // @[RegisterRouter.scala:87:24] wire out_romask_728 = |_out_romask_T_728; // @[RegisterRouter.scala:87:24] wire out_womask_728 = &_out_womask_T_728; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_728 = out_rivalid_1_582 & out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7229 = out_f_rivalid_728; // @[RegisterRouter.scala:87:24] wire out_f_roready_728 = out_roready_1_582 & out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7230 = out_f_roready_728; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_728 = out_wivalid_1_582 & out_wimask_728; // @[RegisterRouter.scala:87:24] wire out_f_woready_728 = out_woready_1_582 & out_womask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7231 = ~out_rimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7232 = ~out_wimask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7233 = ~out_romask_728; // @[RegisterRouter.scala:87:24] wire _out_T_7234 = ~out_womask_728; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_618 = {hi_390, flags_0_go, _out_prepend_T_618}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7235 = out_prepend_618; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7236 = _out_T_7235; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_619 = _out_T_7236; // @[RegisterRouter.scala:87:24] wire out_rimask_729 = |_out_rimask_T_729; // @[RegisterRouter.scala:87:24] wire out_wimask_729 = &_out_wimask_T_729; // @[RegisterRouter.scala:87:24] wire out_romask_729 = |_out_romask_T_729; // @[RegisterRouter.scala:87:24] wire out_womask_729 = &_out_womask_T_729; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_729 = out_rivalid_1_583 & out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7238 = out_f_rivalid_729; // @[RegisterRouter.scala:87:24] wire out_f_roready_729 = out_roready_1_583 & out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7239 = out_f_roready_729; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_729 = out_wivalid_1_583 & out_wimask_729; // @[RegisterRouter.scala:87:24] wire out_f_woready_729 = out_woready_1_583 & out_womask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7240 = ~out_rimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7241 = ~out_wimask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7242 = ~out_romask_729; // @[RegisterRouter.scala:87:24] wire _out_T_7243 = ~out_womask_729; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_619 = {hi_391, flags_0_go, _out_prepend_T_619}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7244 = out_prepend_619; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7245 = _out_T_7244; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_620 = _out_T_7245; // @[RegisterRouter.scala:87:24] wire out_rimask_730 = |_out_rimask_T_730; // @[RegisterRouter.scala:87:24] wire out_wimask_730 = &_out_wimask_T_730; // @[RegisterRouter.scala:87:24] wire out_romask_730 = |_out_romask_T_730; // @[RegisterRouter.scala:87:24] wire out_womask_730 = &_out_womask_T_730; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_730 = out_rivalid_1_584 & out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7247 = out_f_rivalid_730; // @[RegisterRouter.scala:87:24] wire out_f_roready_730 = out_roready_1_584 & out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7248 = out_f_roready_730; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_730 = out_wivalid_1_584 & out_wimask_730; // @[RegisterRouter.scala:87:24] wire out_f_woready_730 = out_woready_1_584 & out_womask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7249 = ~out_rimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7250 = ~out_wimask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7251 = ~out_romask_730; // @[RegisterRouter.scala:87:24] wire _out_T_7252 = ~out_womask_730; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_620 = {hi_392, flags_0_go, _out_prepend_T_620}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7253 = out_prepend_620; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7254 = _out_T_7253; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_176 = _out_T_7254; // @[MuxLiteral.scala:49:48] wire out_rimask_731 = |_out_rimask_T_731; // @[RegisterRouter.scala:87:24] wire out_wimask_731 = &_out_wimask_T_731; // @[RegisterRouter.scala:87:24] wire out_romask_731 = |_out_romask_T_731; // @[RegisterRouter.scala:87:24] wire out_womask_731 = &_out_womask_T_731; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_731 = out_rivalid_1_585 & out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7256 = out_f_rivalid_731; // @[RegisterRouter.scala:87:24] wire out_f_roready_731 = out_roready_1_585 & out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7257 = out_f_roready_731; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_731 = out_wivalid_1_585 & out_wimask_731; // @[RegisterRouter.scala:87:24] wire out_f_woready_731 = out_woready_1_585 & out_womask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7258 = ~out_rimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7259 = ~out_wimask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7260 = ~out_romask_731; // @[RegisterRouter.scala:87:24] wire _out_T_7261 = ~out_womask_731; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7263 = _out_T_7262; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_621 = _out_T_7263; // @[RegisterRouter.scala:87:24] wire out_rimask_732 = |_out_rimask_T_732; // @[RegisterRouter.scala:87:24] wire out_wimask_732 = &_out_wimask_T_732; // @[RegisterRouter.scala:87:24] wire out_romask_732 = |_out_romask_T_732; // @[RegisterRouter.scala:87:24] wire out_womask_732 = &_out_womask_T_732; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_732 = out_rivalid_1_586 & out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7265 = out_f_rivalid_732; // @[RegisterRouter.scala:87:24] wire out_f_roready_732 = out_roready_1_586 & out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7266 = out_f_roready_732; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_732 = out_wivalid_1_586 & out_wimask_732; // @[RegisterRouter.scala:87:24] wire out_f_woready_732 = out_woready_1_586 & out_womask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7267 = ~out_rimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7268 = ~out_wimask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7269 = ~out_romask_732; // @[RegisterRouter.scala:87:24] wire _out_T_7270 = ~out_womask_732; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_621 = {hi_506, flags_0_go, _out_prepend_T_621}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7271 = out_prepend_621; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7272 = _out_T_7271; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_622 = _out_T_7272; // @[RegisterRouter.scala:87:24] wire out_rimask_733 = |_out_rimask_T_733; // @[RegisterRouter.scala:87:24] wire out_wimask_733 = &_out_wimask_T_733; // @[RegisterRouter.scala:87:24] wire out_romask_733 = |_out_romask_T_733; // @[RegisterRouter.scala:87:24] wire out_womask_733 = &_out_womask_T_733; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_733 = out_rivalid_1_587 & out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7274 = out_f_rivalid_733; // @[RegisterRouter.scala:87:24] wire out_f_roready_733 = out_roready_1_587 & out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7275 = out_f_roready_733; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_733 = out_wivalid_1_587 & out_wimask_733; // @[RegisterRouter.scala:87:24] wire out_f_woready_733 = out_woready_1_587 & out_womask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7276 = ~out_rimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7277 = ~out_wimask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7278 = ~out_romask_733; // @[RegisterRouter.scala:87:24] wire _out_T_7279 = ~out_womask_733; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_622 = {hi_507, flags_0_go, _out_prepend_T_622}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7280 = out_prepend_622; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7281 = _out_T_7280; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_623 = _out_T_7281; // @[RegisterRouter.scala:87:24] wire out_rimask_734 = |_out_rimask_T_734; // @[RegisterRouter.scala:87:24] wire out_wimask_734 = &_out_wimask_T_734; // @[RegisterRouter.scala:87:24] wire out_romask_734 = |_out_romask_T_734; // @[RegisterRouter.scala:87:24] wire out_womask_734 = &_out_womask_T_734; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_734 = out_rivalid_1_588 & out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7283 = out_f_rivalid_734; // @[RegisterRouter.scala:87:24] wire out_f_roready_734 = out_roready_1_588 & out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7284 = out_f_roready_734; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_734 = out_wivalid_1_588 & out_wimask_734; // @[RegisterRouter.scala:87:24] wire out_f_woready_734 = out_woready_1_588 & out_womask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7285 = ~out_rimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7286 = ~out_wimask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7287 = ~out_romask_734; // @[RegisterRouter.scala:87:24] wire _out_T_7288 = ~out_womask_734; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_623 = {hi_508, flags_0_go, _out_prepend_T_623}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7289 = out_prepend_623; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7290 = _out_T_7289; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_624 = _out_T_7290; // @[RegisterRouter.scala:87:24] wire out_rimask_735 = |_out_rimask_T_735; // @[RegisterRouter.scala:87:24] wire out_wimask_735 = &_out_wimask_T_735; // @[RegisterRouter.scala:87:24] wire out_romask_735 = |_out_romask_T_735; // @[RegisterRouter.scala:87:24] wire out_womask_735 = &_out_womask_T_735; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_735 = out_rivalid_1_589 & out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7292 = out_f_rivalid_735; // @[RegisterRouter.scala:87:24] wire out_f_roready_735 = out_roready_1_589 & out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7293 = out_f_roready_735; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_735 = out_wivalid_1_589 & out_wimask_735; // @[RegisterRouter.scala:87:24] wire out_f_woready_735 = out_woready_1_589 & out_womask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7294 = ~out_rimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7295 = ~out_wimask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7296 = ~out_romask_735; // @[RegisterRouter.scala:87:24] wire _out_T_7297 = ~out_womask_735; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_624 = {hi_509, flags_0_go, _out_prepend_T_624}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7298 = out_prepend_624; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7299 = _out_T_7298; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_625 = _out_T_7299; // @[RegisterRouter.scala:87:24] wire out_rimask_736 = |_out_rimask_T_736; // @[RegisterRouter.scala:87:24] wire out_wimask_736 = &_out_wimask_T_736; // @[RegisterRouter.scala:87:24] wire out_romask_736 = |_out_romask_T_736; // @[RegisterRouter.scala:87:24] wire out_womask_736 = &_out_womask_T_736; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_736 = out_rivalid_1_590 & out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7301 = out_f_rivalid_736; // @[RegisterRouter.scala:87:24] wire out_f_roready_736 = out_roready_1_590 & out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7302 = out_f_roready_736; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_736 = out_wivalid_1_590 & out_wimask_736; // @[RegisterRouter.scala:87:24] wire out_f_woready_736 = out_woready_1_590 & out_womask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7303 = ~out_rimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7304 = ~out_wimask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7305 = ~out_romask_736; // @[RegisterRouter.scala:87:24] wire _out_T_7306 = ~out_womask_736; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_625 = {hi_510, flags_0_go, _out_prepend_T_625}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7307 = out_prepend_625; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7308 = _out_T_7307; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_626 = _out_T_7308; // @[RegisterRouter.scala:87:24] wire out_rimask_737 = |_out_rimask_T_737; // @[RegisterRouter.scala:87:24] wire out_wimask_737 = &_out_wimask_T_737; // @[RegisterRouter.scala:87:24] wire out_romask_737 = |_out_romask_T_737; // @[RegisterRouter.scala:87:24] wire out_womask_737 = &_out_womask_T_737; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_737 = out_rivalid_1_591 & out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7310 = out_f_rivalid_737; // @[RegisterRouter.scala:87:24] wire out_f_roready_737 = out_roready_1_591 & out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7311 = out_f_roready_737; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_737 = out_wivalid_1_591 & out_wimask_737; // @[RegisterRouter.scala:87:24] wire out_f_woready_737 = out_woready_1_591 & out_womask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7312 = ~out_rimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7313 = ~out_wimask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7314 = ~out_romask_737; // @[RegisterRouter.scala:87:24] wire _out_T_7315 = ~out_womask_737; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_626 = {hi_511, flags_0_go, _out_prepend_T_626}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7316 = out_prepend_626; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7317 = _out_T_7316; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_627 = _out_T_7317; // @[RegisterRouter.scala:87:24] wire out_rimask_738 = |_out_rimask_T_738; // @[RegisterRouter.scala:87:24] wire out_wimask_738 = &_out_wimask_T_738; // @[RegisterRouter.scala:87:24] wire out_romask_738 = |_out_romask_T_738; // @[RegisterRouter.scala:87:24] wire out_womask_738 = &_out_womask_T_738; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_738 = out_rivalid_1_592 & out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7319 = out_f_rivalid_738; // @[RegisterRouter.scala:87:24] wire out_f_roready_738 = out_roready_1_592 & out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7320 = out_f_roready_738; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_738 = out_wivalid_1_592 & out_wimask_738; // @[RegisterRouter.scala:87:24] wire out_f_woready_738 = out_woready_1_592 & out_womask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7321 = ~out_rimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7322 = ~out_wimask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7323 = ~out_romask_738; // @[RegisterRouter.scala:87:24] wire _out_T_7324 = ~out_womask_738; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_627 = {hi_512, flags_0_go, _out_prepend_T_627}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7325 = out_prepend_627; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7326 = _out_T_7325; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_191 = _out_T_7326; // @[MuxLiteral.scala:49:48] wire out_rimask_739 = |_out_rimask_T_739; // @[RegisterRouter.scala:87:24] wire out_wimask_739 = &_out_wimask_T_739; // @[RegisterRouter.scala:87:24] wire out_romask_739 = |_out_romask_T_739; // @[RegisterRouter.scala:87:24] wire out_womask_739 = &_out_womask_T_739; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_739 = out_rivalid_1_593 & out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7328 = out_f_rivalid_739; // @[RegisterRouter.scala:87:24] wire out_f_roready_739 = out_roready_1_593 & out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7329 = out_f_roready_739; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_739 = out_wivalid_1_593 & out_wimask_739; // @[RegisterRouter.scala:87:24] wire out_f_woready_739 = out_woready_1_593 & out_womask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7330 = ~out_rimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7331 = ~out_wimask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7332 = ~out_romask_739; // @[RegisterRouter.scala:87:24] wire _out_T_7333 = ~out_womask_739; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7335 = _out_T_7334; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_628 = _out_T_7335; // @[RegisterRouter.scala:87:24] wire out_rimask_740 = |_out_rimask_T_740; // @[RegisterRouter.scala:87:24] wire out_wimask_740 = &_out_wimask_T_740; // @[RegisterRouter.scala:87:24] wire out_romask_740 = |_out_romask_T_740; // @[RegisterRouter.scala:87:24] wire out_womask_740 = &_out_womask_T_740; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_740 = out_rivalid_1_594 & out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7337 = out_f_rivalid_740; // @[RegisterRouter.scala:87:24] wire out_f_roready_740 = out_roready_1_594 & out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7338 = out_f_roready_740; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_740 = out_wivalid_1_594 & out_wimask_740; // @[RegisterRouter.scala:87:24] wire out_f_woready_740 = out_woready_1_594 & out_womask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7339 = ~out_rimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7340 = ~out_wimask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7341 = ~out_romask_740; // @[RegisterRouter.scala:87:24] wire _out_T_7342 = ~out_womask_740; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_628 = {hi_610, flags_0_go, _out_prepend_T_628}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7343 = out_prepend_628; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7344 = _out_T_7343; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_629 = _out_T_7344; // @[RegisterRouter.scala:87:24] wire out_rimask_741 = |_out_rimask_T_741; // @[RegisterRouter.scala:87:24] wire out_wimask_741 = &_out_wimask_T_741; // @[RegisterRouter.scala:87:24] wire out_romask_741 = |_out_romask_T_741; // @[RegisterRouter.scala:87:24] wire out_womask_741 = &_out_womask_T_741; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_741 = out_rivalid_1_595 & out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7346 = out_f_rivalid_741; // @[RegisterRouter.scala:87:24] wire out_f_roready_741 = out_roready_1_595 & out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7347 = out_f_roready_741; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_741 = out_wivalid_1_595 & out_wimask_741; // @[RegisterRouter.scala:87:24] wire out_f_woready_741 = out_woready_1_595 & out_womask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7348 = ~out_rimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7349 = ~out_wimask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7350 = ~out_romask_741; // @[RegisterRouter.scala:87:24] wire _out_T_7351 = ~out_womask_741; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_629 = {hi_611, flags_0_go, _out_prepend_T_629}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7352 = out_prepend_629; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7353 = _out_T_7352; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_630 = _out_T_7353; // @[RegisterRouter.scala:87:24] wire out_rimask_742 = |_out_rimask_T_742; // @[RegisterRouter.scala:87:24] wire out_wimask_742 = &_out_wimask_T_742; // @[RegisterRouter.scala:87:24] wire out_romask_742 = |_out_romask_T_742; // @[RegisterRouter.scala:87:24] wire out_womask_742 = &_out_womask_T_742; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_742 = out_rivalid_1_596 & out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7355 = out_f_rivalid_742; // @[RegisterRouter.scala:87:24] wire out_f_roready_742 = out_roready_1_596 & out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7356 = out_f_roready_742; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_742 = out_wivalid_1_596 & out_wimask_742; // @[RegisterRouter.scala:87:24] wire out_f_woready_742 = out_woready_1_596 & out_womask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7357 = ~out_rimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7358 = ~out_wimask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7359 = ~out_romask_742; // @[RegisterRouter.scala:87:24] wire _out_T_7360 = ~out_womask_742; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_630 = {hi_612, flags_0_go, _out_prepend_T_630}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7361 = out_prepend_630; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7362 = _out_T_7361; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_631 = _out_T_7362; // @[RegisterRouter.scala:87:24] wire out_rimask_743 = |_out_rimask_T_743; // @[RegisterRouter.scala:87:24] wire out_wimask_743 = &_out_wimask_T_743; // @[RegisterRouter.scala:87:24] wire out_romask_743 = |_out_romask_T_743; // @[RegisterRouter.scala:87:24] wire out_womask_743 = &_out_womask_T_743; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_743 = out_rivalid_1_597 & out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7364 = out_f_rivalid_743; // @[RegisterRouter.scala:87:24] wire out_f_roready_743 = out_roready_1_597 & out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7365 = out_f_roready_743; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_743 = out_wivalid_1_597 & out_wimask_743; // @[RegisterRouter.scala:87:24] wire out_f_woready_743 = out_woready_1_597 & out_womask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7366 = ~out_rimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7367 = ~out_wimask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7368 = ~out_romask_743; // @[RegisterRouter.scala:87:24] wire _out_T_7369 = ~out_womask_743; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_631 = {hi_613, flags_0_go, _out_prepend_T_631}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7370 = out_prepend_631; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7371 = _out_T_7370; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_632 = _out_T_7371; // @[RegisterRouter.scala:87:24] wire out_rimask_744 = |_out_rimask_T_744; // @[RegisterRouter.scala:87:24] wire out_wimask_744 = &_out_wimask_T_744; // @[RegisterRouter.scala:87:24] wire out_romask_744 = |_out_romask_T_744; // @[RegisterRouter.scala:87:24] wire out_womask_744 = &_out_womask_T_744; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_744 = out_rivalid_1_598 & out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7373 = out_f_rivalid_744; // @[RegisterRouter.scala:87:24] wire out_f_roready_744 = out_roready_1_598 & out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7374 = out_f_roready_744; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_744 = out_wivalid_1_598 & out_wimask_744; // @[RegisterRouter.scala:87:24] wire out_f_woready_744 = out_woready_1_598 & out_womask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7375 = ~out_rimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7376 = ~out_wimask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7377 = ~out_romask_744; // @[RegisterRouter.scala:87:24] wire _out_T_7378 = ~out_womask_744; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_632 = {hi_614, flags_0_go, _out_prepend_T_632}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7379 = out_prepend_632; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7380 = _out_T_7379; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_633 = _out_T_7380; // @[RegisterRouter.scala:87:24] wire out_rimask_745 = |_out_rimask_T_745; // @[RegisterRouter.scala:87:24] wire out_wimask_745 = &_out_wimask_T_745; // @[RegisterRouter.scala:87:24] wire out_romask_745 = |_out_romask_T_745; // @[RegisterRouter.scala:87:24] wire out_womask_745 = &_out_womask_T_745; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_745 = out_rivalid_1_599 & out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7382 = out_f_rivalid_745; // @[RegisterRouter.scala:87:24] wire out_f_roready_745 = out_roready_1_599 & out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7383 = out_f_roready_745; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_745 = out_wivalid_1_599 & out_wimask_745; // @[RegisterRouter.scala:87:24] wire out_f_woready_745 = out_woready_1_599 & out_womask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7384 = ~out_rimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7385 = ~out_wimask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7386 = ~out_romask_745; // @[RegisterRouter.scala:87:24] wire _out_T_7387 = ~out_womask_745; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_633 = {hi_615, flags_0_go, _out_prepend_T_633}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7388 = out_prepend_633; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7389 = _out_T_7388; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_634 = _out_T_7389; // @[RegisterRouter.scala:87:24] wire out_rimask_746 = |_out_rimask_T_746; // @[RegisterRouter.scala:87:24] wire out_wimask_746 = &_out_wimask_T_746; // @[RegisterRouter.scala:87:24] wire out_romask_746 = |_out_romask_T_746; // @[RegisterRouter.scala:87:24] wire out_womask_746 = &_out_womask_T_746; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_746 = out_rivalid_1_600 & out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7391 = out_f_rivalid_746; // @[RegisterRouter.scala:87:24] wire out_f_roready_746 = out_roready_1_600 & out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7392 = out_f_roready_746; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_746 = out_wivalid_1_600 & out_wimask_746; // @[RegisterRouter.scala:87:24] wire out_f_woready_746 = out_woready_1_600 & out_womask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7393 = ~out_rimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7394 = ~out_wimask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7395 = ~out_romask_746; // @[RegisterRouter.scala:87:24] wire _out_T_7396 = ~out_womask_746; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_634 = {hi_616, flags_0_go, _out_prepend_T_634}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7397 = out_prepend_634; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7398 = _out_T_7397; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_204 = _out_T_7398; // @[MuxLiteral.scala:49:48] wire out_rimask_747 = |_out_rimask_T_747; // @[RegisterRouter.scala:87:24] wire out_wimask_747 = &_out_wimask_T_747; // @[RegisterRouter.scala:87:24] wire out_romask_747 = |_out_romask_T_747; // @[RegisterRouter.scala:87:24] wire out_womask_747 = &_out_womask_T_747; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_747 = out_rivalid_1_601 & out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7400 = out_f_rivalid_747; // @[RegisterRouter.scala:87:24] wire out_f_roready_747 = out_roready_1_601 & out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7401 = out_f_roready_747; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_747 = out_wivalid_1_601 & out_wimask_747; // @[RegisterRouter.scala:87:24] wire out_f_woready_747 = out_woready_1_601 & out_womask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7402 = ~out_rimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7403 = ~out_wimask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7404 = ~out_romask_747; // @[RegisterRouter.scala:87:24] wire _out_T_7405 = ~out_womask_747; // @[RegisterRouter.scala:87:24] wire out_rimask_748 = |_out_rimask_T_748; // @[RegisterRouter.scala:87:24] wire out_wimask_748 = &_out_wimask_T_748; // @[RegisterRouter.scala:87:24] wire out_romask_748 = |_out_romask_T_748; // @[RegisterRouter.scala:87:24] wire out_womask_748 = &_out_womask_T_748; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_748 = out_rivalid_1_602 & out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7409 = out_f_rivalid_748; // @[RegisterRouter.scala:87:24] wire out_f_roready_748 = out_roready_1_602 & out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7410 = out_f_roready_748; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_748 = out_wivalid_1_602 & out_wimask_748; // @[RegisterRouter.scala:87:24] wire out_f_woready_748 = out_woready_1_602 & out_womask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7411 = ~out_rimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7412 = ~out_wimask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7413 = ~out_romask_748; // @[RegisterRouter.scala:87:24] wire _out_T_7414 = ~out_womask_748; // @[RegisterRouter.scala:87:24] wire out_rimask_749 = |_out_rimask_T_749; // @[RegisterRouter.scala:87:24] wire out_wimask_749 = &_out_wimask_T_749; // @[RegisterRouter.scala:87:24] wire out_romask_749 = |_out_romask_T_749; // @[RegisterRouter.scala:87:24] wire out_womask_749 = &_out_womask_T_749; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_749 = out_rivalid_1_603 & out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7418 = out_f_rivalid_749; // @[RegisterRouter.scala:87:24] wire out_f_roready_749 = out_roready_1_603 & out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7419 = out_f_roready_749; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_749 = out_wivalid_1_603 & out_wimask_749; // @[RegisterRouter.scala:87:24] wire out_f_woready_749 = out_woready_1_603 & out_womask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7420 = ~out_rimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7421 = ~out_wimask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7422 = ~out_romask_749; // @[RegisterRouter.scala:87:24] wire _out_T_7423 = ~out_womask_749; // @[RegisterRouter.scala:87:24] wire out_rimask_750 = |_out_rimask_T_750; // @[RegisterRouter.scala:87:24] wire out_wimask_750 = &_out_wimask_T_750; // @[RegisterRouter.scala:87:24] wire out_romask_750 = |_out_romask_T_750; // @[RegisterRouter.scala:87:24] wire out_womask_750 = &_out_womask_T_750; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_750 = out_rivalid_1_604 & out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7427 = out_f_rivalid_750; // @[RegisterRouter.scala:87:24] wire out_f_roready_750 = out_roready_1_604 & out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7428 = out_f_roready_750; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_750 = out_wivalid_1_604 & out_wimask_750; // @[RegisterRouter.scala:87:24] wire out_f_woready_750 = out_woready_1_604 & out_womask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7429 = ~out_rimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7430 = ~out_wimask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7431 = ~out_romask_750; // @[RegisterRouter.scala:87:24] wire _out_T_7432 = ~out_womask_750; // @[RegisterRouter.scala:87:24] wire out_rimask_751 = |_out_rimask_T_751; // @[RegisterRouter.scala:87:24] wire out_wimask_751 = &_out_wimask_T_751; // @[RegisterRouter.scala:87:24] wire out_romask_751 = |_out_romask_T_751; // @[RegisterRouter.scala:87:24] wire out_womask_751 = &_out_womask_T_751; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_751 = out_rivalid_1_605 & out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7436 = out_f_rivalid_751; // @[RegisterRouter.scala:87:24] wire out_f_roready_751 = out_roready_1_605 & out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7437 = out_f_roready_751; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_751 = out_wivalid_1_605 & out_wimask_751; // @[RegisterRouter.scala:87:24] wire out_f_woready_751 = out_woready_1_605 & out_womask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7438 = ~out_rimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7439 = ~out_wimask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7440 = ~out_romask_751; // @[RegisterRouter.scala:87:24] wire _out_T_7441 = ~out_womask_751; // @[RegisterRouter.scala:87:24] wire out_rimask_752 = |_out_rimask_T_752; // @[RegisterRouter.scala:87:24] wire out_wimask_752 = &_out_wimask_T_752; // @[RegisterRouter.scala:87:24] wire out_romask_752 = |_out_romask_T_752; // @[RegisterRouter.scala:87:24] wire out_womask_752 = &_out_womask_T_752; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_752 = out_rivalid_1_606 & out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7445 = out_f_rivalid_752; // @[RegisterRouter.scala:87:24] wire out_f_roready_752 = out_roready_1_606 & out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7446 = out_f_roready_752; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_752 = out_wivalid_1_606 & out_wimask_752; // @[RegisterRouter.scala:87:24] wire out_f_woready_752 = out_woready_1_606 & out_womask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7447 = ~out_rimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7448 = ~out_wimask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7449 = ~out_romask_752; // @[RegisterRouter.scala:87:24] wire _out_T_7450 = ~out_womask_752; // @[RegisterRouter.scala:87:24] wire out_rimask_753 = |_out_rimask_T_753; // @[RegisterRouter.scala:87:24] wire out_wimask_753 = &_out_wimask_T_753; // @[RegisterRouter.scala:87:24] wire out_romask_753 = |_out_romask_T_753; // @[RegisterRouter.scala:87:24] wire out_womask_753 = &_out_womask_T_753; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_753 = out_rivalid_1_607 & out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7454 = out_f_rivalid_753; // @[RegisterRouter.scala:87:24] wire out_f_roready_753 = out_roready_1_607 & out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7455 = out_f_roready_753; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_753 = out_wivalid_1_607 & out_wimask_753; // @[RegisterRouter.scala:87:24] wire out_f_woready_753 = out_woready_1_607 & out_womask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7456 = ~out_rimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7457 = ~out_wimask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7458 = ~out_romask_753; // @[RegisterRouter.scala:87:24] wire _out_T_7459 = ~out_womask_753; // @[RegisterRouter.scala:87:24] wire out_rimask_754 = |_out_rimask_T_754; // @[RegisterRouter.scala:87:24] wire out_wimask_754 = &_out_wimask_T_754; // @[RegisterRouter.scala:87:24] wire out_romask_754 = |_out_romask_T_754; // @[RegisterRouter.scala:87:24] wire out_womask_754 = &_out_womask_T_754; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_754 = out_rivalid_1_608 & out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7463 = out_f_rivalid_754; // @[RegisterRouter.scala:87:24] wire out_f_roready_754 = out_roready_1_608 & out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7464 = out_f_roready_754; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_754 = out_wivalid_1_608 & out_wimask_754; // @[RegisterRouter.scala:87:24] wire out_f_woready_754 = out_woready_1_608 & out_womask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7465 = ~out_rimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7466 = ~out_wimask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7467 = ~out_romask_754; // @[RegisterRouter.scala:87:24] wire _out_T_7468 = ~out_womask_754; // @[RegisterRouter.scala:87:24] wire out_rimask_755 = |_out_rimask_T_755; // @[RegisterRouter.scala:87:24] wire out_wimask_755 = &_out_wimask_T_755; // @[RegisterRouter.scala:87:24] wire out_romask_755 = |_out_romask_T_755; // @[RegisterRouter.scala:87:24] wire out_womask_755 = &_out_womask_T_755; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_755 = out_rivalid_1_609 & out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7472 = out_f_rivalid_755; // @[RegisterRouter.scala:87:24] wire out_f_roready_755 = out_roready_1_609 & out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7473 = out_f_roready_755; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_755 = out_wivalid_1_609 & out_wimask_755; // @[RegisterRouter.scala:87:24] wire out_f_woready_755 = out_woready_1_609 & out_womask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7474 = ~out_rimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7475 = ~out_wimask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7476 = ~out_romask_755; // @[RegisterRouter.scala:87:24] wire _out_T_7477 = ~out_womask_755; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7479 = _out_T_7478; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_642 = _out_T_7479; // @[RegisterRouter.scala:87:24] wire out_rimask_756 = |_out_rimask_T_756; // @[RegisterRouter.scala:87:24] wire out_wimask_756 = &_out_wimask_T_756; // @[RegisterRouter.scala:87:24] wire out_romask_756 = |_out_romask_T_756; // @[RegisterRouter.scala:87:24] wire out_womask_756 = &_out_womask_T_756; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_756 = out_rivalid_1_610 & out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7481 = out_f_rivalid_756; // @[RegisterRouter.scala:87:24] wire out_f_roready_756 = out_roready_1_610 & out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7482 = out_f_roready_756; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_756 = out_wivalid_1_610 & out_wimask_756; // @[RegisterRouter.scala:87:24] wire out_f_woready_756 = out_woready_1_610 & out_womask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7483 = ~out_rimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7484 = ~out_wimask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7485 = ~out_romask_756; // @[RegisterRouter.scala:87:24] wire _out_T_7486 = ~out_womask_756; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_642 = {hi_130, flags_0_go, _out_prepend_T_642}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7487 = out_prepend_642; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7488 = _out_T_7487; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_643 = _out_T_7488; // @[RegisterRouter.scala:87:24] wire out_rimask_757 = |_out_rimask_T_757; // @[RegisterRouter.scala:87:24] wire out_wimask_757 = &_out_wimask_T_757; // @[RegisterRouter.scala:87:24] wire out_romask_757 = |_out_romask_T_757; // @[RegisterRouter.scala:87:24] wire out_womask_757 = &_out_womask_T_757; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_757 = out_rivalid_1_611 & out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7490 = out_f_rivalid_757; // @[RegisterRouter.scala:87:24] wire out_f_roready_757 = out_roready_1_611 & out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7491 = out_f_roready_757; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_757 = out_wivalid_1_611 & out_wimask_757; // @[RegisterRouter.scala:87:24] wire out_f_woready_757 = out_woready_1_611 & out_womask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7492 = ~out_rimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7493 = ~out_wimask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7494 = ~out_romask_757; // @[RegisterRouter.scala:87:24] wire _out_T_7495 = ~out_womask_757; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_643 = {hi_131, flags_0_go, _out_prepend_T_643}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7496 = out_prepend_643; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7497 = _out_T_7496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_644 = _out_T_7497; // @[RegisterRouter.scala:87:24] wire out_rimask_758 = |_out_rimask_T_758; // @[RegisterRouter.scala:87:24] wire out_wimask_758 = &_out_wimask_T_758; // @[RegisterRouter.scala:87:24] wire out_romask_758 = |_out_romask_T_758; // @[RegisterRouter.scala:87:24] wire out_womask_758 = &_out_womask_T_758; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_758 = out_rivalid_1_612 & out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7499 = out_f_rivalid_758; // @[RegisterRouter.scala:87:24] wire out_f_roready_758 = out_roready_1_612 & out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7500 = out_f_roready_758; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_758 = out_wivalid_1_612 & out_wimask_758; // @[RegisterRouter.scala:87:24] wire out_f_woready_758 = out_woready_1_612 & out_womask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7501 = ~out_rimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7502 = ~out_wimask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7503 = ~out_romask_758; // @[RegisterRouter.scala:87:24] wire _out_T_7504 = ~out_womask_758; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_644 = {hi_132, flags_0_go, _out_prepend_T_644}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7505 = out_prepend_644; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7506 = _out_T_7505; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_645 = _out_T_7506; // @[RegisterRouter.scala:87:24] wire out_rimask_759 = |_out_rimask_T_759; // @[RegisterRouter.scala:87:24] wire out_wimask_759 = &_out_wimask_T_759; // @[RegisterRouter.scala:87:24] wire out_romask_759 = |_out_romask_T_759; // @[RegisterRouter.scala:87:24] wire out_womask_759 = &_out_womask_T_759; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_759 = out_rivalid_1_613 & out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7508 = out_f_rivalid_759; // @[RegisterRouter.scala:87:24] wire out_f_roready_759 = out_roready_1_613 & out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7509 = out_f_roready_759; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_759 = out_wivalid_1_613 & out_wimask_759; // @[RegisterRouter.scala:87:24] wire out_f_woready_759 = out_woready_1_613 & out_womask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7510 = ~out_rimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7511 = ~out_wimask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7512 = ~out_romask_759; // @[RegisterRouter.scala:87:24] wire _out_T_7513 = ~out_womask_759; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_645 = {hi_133, flags_0_go, _out_prepend_T_645}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7514 = out_prepend_645; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7515 = _out_T_7514; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_646 = _out_T_7515; // @[RegisterRouter.scala:87:24] wire out_rimask_760 = |_out_rimask_T_760; // @[RegisterRouter.scala:87:24] wire out_wimask_760 = &_out_wimask_T_760; // @[RegisterRouter.scala:87:24] wire out_romask_760 = |_out_romask_T_760; // @[RegisterRouter.scala:87:24] wire out_womask_760 = &_out_womask_T_760; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_760 = out_rivalid_1_614 & out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7517 = out_f_rivalid_760; // @[RegisterRouter.scala:87:24] wire out_f_roready_760 = out_roready_1_614 & out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7518 = out_f_roready_760; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_760 = out_wivalid_1_614 & out_wimask_760; // @[RegisterRouter.scala:87:24] wire out_f_woready_760 = out_woready_1_614 & out_womask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7519 = ~out_rimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7520 = ~out_wimask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7521 = ~out_romask_760; // @[RegisterRouter.scala:87:24] wire _out_T_7522 = ~out_womask_760; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_646 = {hi_134, flags_0_go, _out_prepend_T_646}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7523 = out_prepend_646; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7524 = _out_T_7523; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_647 = _out_T_7524; // @[RegisterRouter.scala:87:24] wire out_rimask_761 = |_out_rimask_T_761; // @[RegisterRouter.scala:87:24] wire out_wimask_761 = &_out_wimask_T_761; // @[RegisterRouter.scala:87:24] wire out_romask_761 = |_out_romask_T_761; // @[RegisterRouter.scala:87:24] wire out_womask_761 = &_out_womask_T_761; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_761 = out_rivalid_1_615 & out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7526 = out_f_rivalid_761; // @[RegisterRouter.scala:87:24] wire out_f_roready_761 = out_roready_1_615 & out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7527 = out_f_roready_761; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_761 = out_wivalid_1_615 & out_wimask_761; // @[RegisterRouter.scala:87:24] wire out_f_woready_761 = out_woready_1_615 & out_womask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7528 = ~out_rimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7529 = ~out_wimask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7530 = ~out_romask_761; // @[RegisterRouter.scala:87:24] wire _out_T_7531 = ~out_womask_761; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_647 = {hi_135, flags_0_go, _out_prepend_T_647}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7532 = out_prepend_647; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7533 = _out_T_7532; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_648 = _out_T_7533; // @[RegisterRouter.scala:87:24] wire out_rimask_762 = |_out_rimask_T_762; // @[RegisterRouter.scala:87:24] wire out_wimask_762 = &_out_wimask_T_762; // @[RegisterRouter.scala:87:24] wire out_romask_762 = |_out_romask_T_762; // @[RegisterRouter.scala:87:24] wire out_womask_762 = &_out_womask_T_762; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_762 = out_rivalid_1_616 & out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7535 = out_f_rivalid_762; // @[RegisterRouter.scala:87:24] wire out_f_roready_762 = out_roready_1_616 & out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7536 = out_f_roready_762; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_762 = out_wivalid_1_616 & out_wimask_762; // @[RegisterRouter.scala:87:24] wire out_f_woready_762 = out_woready_1_616 & out_womask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7537 = ~out_rimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7538 = ~out_wimask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7539 = ~out_romask_762; // @[RegisterRouter.scala:87:24] wire _out_T_7540 = ~out_womask_762; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_648 = {hi_136, flags_0_go, _out_prepend_T_648}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7541 = out_prepend_648; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7542 = _out_T_7541; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_144 = _out_T_7542; // @[MuxLiteral.scala:49:48] wire out_rimask_763 = |_out_rimask_T_763; // @[RegisterRouter.scala:87:24] wire out_wimask_763 = &_out_wimask_T_763; // @[RegisterRouter.scala:87:24] wire out_romask_763 = |_out_romask_T_763; // @[RegisterRouter.scala:87:24] wire out_womask_763 = &_out_womask_T_763; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_763 = out_rivalid_1_617 & out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7544 = out_f_rivalid_763; // @[RegisterRouter.scala:87:24] wire out_f_roready_763 = out_roready_1_617 & out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7545 = out_f_roready_763; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_763 = out_wivalid_1_617 & out_wimask_763; // @[RegisterRouter.scala:87:24] wire out_f_woready_763 = out_woready_1_617 & out_womask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7546 = ~out_rimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7547 = ~out_wimask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7548 = ~out_romask_763; // @[RegisterRouter.scala:87:24] wire _out_T_7549 = ~out_womask_763; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7551 = _out_T_7550; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_649 = _out_T_7551; // @[RegisterRouter.scala:87:24] wire out_rimask_764 = |_out_rimask_T_764; // @[RegisterRouter.scala:87:24] wire out_wimask_764 = &_out_wimask_T_764; // @[RegisterRouter.scala:87:24] wire out_romask_764 = |_out_romask_T_764; // @[RegisterRouter.scala:87:24] wire out_womask_764 = &_out_womask_T_764; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_764 = out_rivalid_1_618 & out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7553 = out_f_rivalid_764; // @[RegisterRouter.scala:87:24] wire out_f_roready_764 = out_roready_1_618 & out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7554 = out_f_roready_764; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_764 = out_wivalid_1_618 & out_wimask_764; // @[RegisterRouter.scala:87:24] wire out_f_woready_764 = out_woready_1_618 & out_womask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7555 = ~out_rimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7556 = ~out_wimask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7557 = ~out_romask_764; // @[RegisterRouter.scala:87:24] wire _out_T_7558 = ~out_womask_764; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_649 = {hi_866, flags_0_go, _out_prepend_T_649}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7559 = out_prepend_649; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7560 = _out_T_7559; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_650 = _out_T_7560; // @[RegisterRouter.scala:87:24] wire out_rimask_765 = |_out_rimask_T_765; // @[RegisterRouter.scala:87:24] wire out_wimask_765 = &_out_wimask_T_765; // @[RegisterRouter.scala:87:24] wire out_romask_765 = |_out_romask_T_765; // @[RegisterRouter.scala:87:24] wire out_womask_765 = &_out_womask_T_765; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_765 = out_rivalid_1_619 & out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7562 = out_f_rivalid_765; // @[RegisterRouter.scala:87:24] wire out_f_roready_765 = out_roready_1_619 & out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7563 = out_f_roready_765; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_765 = out_wivalid_1_619 & out_wimask_765; // @[RegisterRouter.scala:87:24] wire out_f_woready_765 = out_woready_1_619 & out_womask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7564 = ~out_rimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7565 = ~out_wimask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7566 = ~out_romask_765; // @[RegisterRouter.scala:87:24] wire _out_T_7567 = ~out_womask_765; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_650 = {hi_867, flags_0_go, _out_prepend_T_650}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7568 = out_prepend_650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7569 = _out_T_7568; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_651 = _out_T_7569; // @[RegisterRouter.scala:87:24] wire out_rimask_766 = |_out_rimask_T_766; // @[RegisterRouter.scala:87:24] wire out_wimask_766 = &_out_wimask_T_766; // @[RegisterRouter.scala:87:24] wire out_romask_766 = |_out_romask_T_766; // @[RegisterRouter.scala:87:24] wire out_womask_766 = &_out_womask_T_766; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_766 = out_rivalid_1_620 & out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7571 = out_f_rivalid_766; // @[RegisterRouter.scala:87:24] wire out_f_roready_766 = out_roready_1_620 & out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7572 = out_f_roready_766; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_766 = out_wivalid_1_620 & out_wimask_766; // @[RegisterRouter.scala:87:24] wire out_f_woready_766 = out_woready_1_620 & out_womask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7573 = ~out_rimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7574 = ~out_wimask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7575 = ~out_romask_766; // @[RegisterRouter.scala:87:24] wire _out_T_7576 = ~out_womask_766; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_651 = {hi_868, flags_0_go, _out_prepend_T_651}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7577 = out_prepend_651; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7578 = _out_T_7577; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_652 = _out_T_7578; // @[RegisterRouter.scala:87:24] wire out_rimask_767 = |_out_rimask_T_767; // @[RegisterRouter.scala:87:24] wire out_wimask_767 = &_out_wimask_T_767; // @[RegisterRouter.scala:87:24] wire out_romask_767 = |_out_romask_T_767; // @[RegisterRouter.scala:87:24] wire out_womask_767 = &_out_womask_T_767; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_767 = out_rivalid_1_621 & out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7580 = out_f_rivalid_767; // @[RegisterRouter.scala:87:24] wire out_f_roready_767 = out_roready_1_621 & out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7581 = out_f_roready_767; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_767 = out_wivalid_1_621 & out_wimask_767; // @[RegisterRouter.scala:87:24] wire out_f_woready_767 = out_woready_1_621 & out_womask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7582 = ~out_rimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7583 = ~out_wimask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7584 = ~out_romask_767; // @[RegisterRouter.scala:87:24] wire _out_T_7585 = ~out_womask_767; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_652 = {hi_869, flags_0_go, _out_prepend_T_652}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7586 = out_prepend_652; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7587 = _out_T_7586; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_653 = _out_T_7587; // @[RegisterRouter.scala:87:24] wire out_rimask_768 = |_out_rimask_T_768; // @[RegisterRouter.scala:87:24] wire out_wimask_768 = &_out_wimask_T_768; // @[RegisterRouter.scala:87:24] wire out_romask_768 = |_out_romask_T_768; // @[RegisterRouter.scala:87:24] wire out_womask_768 = &_out_womask_T_768; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_768 = out_rivalid_1_622 & out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7589 = out_f_rivalid_768; // @[RegisterRouter.scala:87:24] wire out_f_roready_768 = out_roready_1_622 & out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7590 = out_f_roready_768; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_768 = out_wivalid_1_622 & out_wimask_768; // @[RegisterRouter.scala:87:24] wire out_f_woready_768 = out_woready_1_622 & out_womask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7591 = ~out_rimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7592 = ~out_wimask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7593 = ~out_romask_768; // @[RegisterRouter.scala:87:24] wire _out_T_7594 = ~out_womask_768; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_653 = {hi_870, flags_0_go, _out_prepend_T_653}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7595 = out_prepend_653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7596 = _out_T_7595; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_654 = _out_T_7596; // @[RegisterRouter.scala:87:24] wire out_rimask_769 = |_out_rimask_T_769; // @[RegisterRouter.scala:87:24] wire out_wimask_769 = &_out_wimask_T_769; // @[RegisterRouter.scala:87:24] wire out_romask_769 = |_out_romask_T_769; // @[RegisterRouter.scala:87:24] wire out_womask_769 = &_out_womask_T_769; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_769 = out_rivalid_1_623 & out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7598 = out_f_rivalid_769; // @[RegisterRouter.scala:87:24] wire out_f_roready_769 = out_roready_1_623 & out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7599 = out_f_roready_769; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_769 = out_wivalid_1_623 & out_wimask_769; // @[RegisterRouter.scala:87:24] wire out_f_woready_769 = out_woready_1_623 & out_womask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7600 = ~out_rimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7601 = ~out_wimask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7602 = ~out_romask_769; // @[RegisterRouter.scala:87:24] wire _out_T_7603 = ~out_womask_769; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_654 = {hi_871, flags_0_go, _out_prepend_T_654}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7604 = out_prepend_654; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7605 = _out_T_7604; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_655 = _out_T_7605; // @[RegisterRouter.scala:87:24] wire out_rimask_770 = |_out_rimask_T_770; // @[RegisterRouter.scala:87:24] wire out_wimask_770 = &_out_wimask_T_770; // @[RegisterRouter.scala:87:24] wire out_romask_770 = |_out_romask_T_770; // @[RegisterRouter.scala:87:24] wire out_womask_770 = &_out_womask_T_770; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_770 = out_rivalid_1_624 & out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7607 = out_f_rivalid_770; // @[RegisterRouter.scala:87:24] wire out_f_roready_770 = out_roready_1_624 & out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7608 = out_f_roready_770; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_770 = out_wivalid_1_624 & out_wimask_770; // @[RegisterRouter.scala:87:24] wire out_f_woready_770 = out_woready_1_624 & out_womask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7609 = ~out_rimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7610 = ~out_wimask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7611 = ~out_romask_770; // @[RegisterRouter.scala:87:24] wire _out_T_7612 = ~out_womask_770; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_655 = {hi_872, flags_0_go, _out_prepend_T_655}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7613 = out_prepend_655; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7614 = _out_T_7613; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_236 = _out_T_7614; // @[MuxLiteral.scala:49:48] wire out_rimask_771 = |_out_rimask_T_771; // @[RegisterRouter.scala:87:24] wire out_wimask_771 = &_out_wimask_T_771; // @[RegisterRouter.scala:87:24] wire out_romask_771 = |_out_romask_T_771; // @[RegisterRouter.scala:87:24] wire out_womask_771 = &_out_womask_T_771; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_771 = out_rivalid_1_625 & out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7616 = out_f_rivalid_771; // @[RegisterRouter.scala:87:24] wire out_f_roready_771 = out_roready_1_625 & out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7617 = out_f_roready_771; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_771 = out_wivalid_1_625 & out_wimask_771; // @[RegisterRouter.scala:87:24] wire out_f_woready_771 = out_woready_1_625 & out_womask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7618 = ~out_rimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7619 = ~out_wimask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7620 = ~out_romask_771; // @[RegisterRouter.scala:87:24] wire _out_T_7621 = ~out_womask_771; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7623 = _out_T_7622; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_656 = _out_T_7623; // @[RegisterRouter.scala:87:24] wire out_rimask_772 = |_out_rimask_T_772; // @[RegisterRouter.scala:87:24] wire out_wimask_772 = &_out_wimask_T_772; // @[RegisterRouter.scala:87:24] wire out_romask_772 = |_out_romask_T_772; // @[RegisterRouter.scala:87:24] wire out_womask_772 = &_out_womask_T_772; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_772 = out_rivalid_1_626 & out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7625 = out_f_rivalid_772; // @[RegisterRouter.scala:87:24] wire out_f_roready_772 = out_roready_1_626 & out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7626 = out_f_roready_772; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_772 = out_wivalid_1_626 & out_wimask_772; // @[RegisterRouter.scala:87:24] wire out_f_woready_772 = out_woready_1_626 & out_womask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7627 = ~out_rimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7628 = ~out_wimask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7629 = ~out_romask_772; // @[RegisterRouter.scala:87:24] wire _out_T_7630 = ~out_womask_772; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_656 = {hi_426, flags_0_go, _out_prepend_T_656}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7631 = out_prepend_656; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7632 = _out_T_7631; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_657 = _out_T_7632; // @[RegisterRouter.scala:87:24] wire out_rimask_773 = |_out_rimask_T_773; // @[RegisterRouter.scala:87:24] wire out_wimask_773 = &_out_wimask_T_773; // @[RegisterRouter.scala:87:24] wire out_romask_773 = |_out_romask_T_773; // @[RegisterRouter.scala:87:24] wire out_womask_773 = &_out_womask_T_773; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_773 = out_rivalid_1_627 & out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7634 = out_f_rivalid_773; // @[RegisterRouter.scala:87:24] wire out_f_roready_773 = out_roready_1_627 & out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7635 = out_f_roready_773; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_773 = out_wivalid_1_627 & out_wimask_773; // @[RegisterRouter.scala:87:24] wire out_f_woready_773 = out_woready_1_627 & out_womask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7636 = ~out_rimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7637 = ~out_wimask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7638 = ~out_romask_773; // @[RegisterRouter.scala:87:24] wire _out_T_7639 = ~out_womask_773; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_657 = {hi_427, flags_0_go, _out_prepend_T_657}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7640 = out_prepend_657; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7641 = _out_T_7640; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_658 = _out_T_7641; // @[RegisterRouter.scala:87:24] wire out_rimask_774 = |_out_rimask_T_774; // @[RegisterRouter.scala:87:24] wire out_wimask_774 = &_out_wimask_T_774; // @[RegisterRouter.scala:87:24] wire out_romask_774 = |_out_romask_T_774; // @[RegisterRouter.scala:87:24] wire out_womask_774 = &_out_womask_T_774; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_774 = out_rivalid_1_628 & out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7643 = out_f_rivalid_774; // @[RegisterRouter.scala:87:24] wire out_f_roready_774 = out_roready_1_628 & out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7644 = out_f_roready_774; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_774 = out_wivalid_1_628 & out_wimask_774; // @[RegisterRouter.scala:87:24] wire out_f_woready_774 = out_woready_1_628 & out_womask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7645 = ~out_rimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7646 = ~out_wimask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7647 = ~out_romask_774; // @[RegisterRouter.scala:87:24] wire _out_T_7648 = ~out_womask_774; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_658 = {hi_428, flags_0_go, _out_prepend_T_658}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7649 = out_prepend_658; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7650 = _out_T_7649; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_659 = _out_T_7650; // @[RegisterRouter.scala:87:24] wire out_rimask_775 = |_out_rimask_T_775; // @[RegisterRouter.scala:87:24] wire out_wimask_775 = &_out_wimask_T_775; // @[RegisterRouter.scala:87:24] wire out_romask_775 = |_out_romask_T_775; // @[RegisterRouter.scala:87:24] wire out_womask_775 = &_out_womask_T_775; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_775 = out_rivalid_1_629 & out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7652 = out_f_rivalid_775; // @[RegisterRouter.scala:87:24] wire out_f_roready_775 = out_roready_1_629 & out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7653 = out_f_roready_775; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_775 = out_wivalid_1_629 & out_wimask_775; // @[RegisterRouter.scala:87:24] wire out_f_woready_775 = out_woready_1_629 & out_womask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7654 = ~out_rimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7655 = ~out_wimask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7656 = ~out_romask_775; // @[RegisterRouter.scala:87:24] wire _out_T_7657 = ~out_womask_775; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_659 = {hi_429, flags_0_go, _out_prepend_T_659}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7658 = out_prepend_659; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7659 = _out_T_7658; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_660 = _out_T_7659; // @[RegisterRouter.scala:87:24] wire out_rimask_776 = |_out_rimask_T_776; // @[RegisterRouter.scala:87:24] wire out_wimask_776 = &_out_wimask_T_776; // @[RegisterRouter.scala:87:24] wire out_romask_776 = |_out_romask_T_776; // @[RegisterRouter.scala:87:24] wire out_womask_776 = &_out_womask_T_776; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_776 = out_rivalid_1_630 & out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7661 = out_f_rivalid_776; // @[RegisterRouter.scala:87:24] wire out_f_roready_776 = out_roready_1_630 & out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7662 = out_f_roready_776; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_776 = out_wivalid_1_630 & out_wimask_776; // @[RegisterRouter.scala:87:24] wire out_f_woready_776 = out_woready_1_630 & out_womask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7663 = ~out_rimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7664 = ~out_wimask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7665 = ~out_romask_776; // @[RegisterRouter.scala:87:24] wire _out_T_7666 = ~out_womask_776; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_660 = {hi_430, flags_0_go, _out_prepend_T_660}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7667 = out_prepend_660; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7668 = _out_T_7667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_661 = _out_T_7668; // @[RegisterRouter.scala:87:24] wire out_rimask_777 = |_out_rimask_T_777; // @[RegisterRouter.scala:87:24] wire out_wimask_777 = &_out_wimask_T_777; // @[RegisterRouter.scala:87:24] wire out_romask_777 = |_out_romask_T_777; // @[RegisterRouter.scala:87:24] wire out_womask_777 = &_out_womask_T_777; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_777 = out_rivalid_1_631 & out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7670 = out_f_rivalid_777; // @[RegisterRouter.scala:87:24] wire out_f_roready_777 = out_roready_1_631 & out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7671 = out_f_roready_777; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_777 = out_wivalid_1_631 & out_wimask_777; // @[RegisterRouter.scala:87:24] wire out_f_woready_777 = out_woready_1_631 & out_womask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7672 = ~out_rimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7673 = ~out_wimask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7674 = ~out_romask_777; // @[RegisterRouter.scala:87:24] wire _out_T_7675 = ~out_womask_777; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_661 = {hi_431, flags_0_go, _out_prepend_T_661}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7676 = out_prepend_661; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7677 = _out_T_7676; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_662 = _out_T_7677; // @[RegisterRouter.scala:87:24] wire out_rimask_778 = |_out_rimask_T_778; // @[RegisterRouter.scala:87:24] wire out_wimask_778 = &_out_wimask_T_778; // @[RegisterRouter.scala:87:24] wire out_romask_778 = |_out_romask_T_778; // @[RegisterRouter.scala:87:24] wire out_womask_778 = &_out_womask_T_778; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_778 = out_rivalid_1_632 & out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7679 = out_f_rivalid_778; // @[RegisterRouter.scala:87:24] wire out_f_roready_778 = out_roready_1_632 & out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7680 = out_f_roready_778; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_778 = out_wivalid_1_632 & out_wimask_778; // @[RegisterRouter.scala:87:24] wire out_f_woready_778 = out_woready_1_632 & out_womask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7681 = ~out_rimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7682 = ~out_wimask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7683 = ~out_romask_778; // @[RegisterRouter.scala:87:24] wire _out_T_7684 = ~out_womask_778; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_662 = {hi_432, flags_0_go, _out_prepend_T_662}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7685 = out_prepend_662; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7686 = _out_T_7685; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_181 = _out_T_7686; // @[MuxLiteral.scala:49:48] wire out_rimask_779 = |_out_rimask_T_779; // @[RegisterRouter.scala:87:24] wire out_wimask_779 = &_out_wimask_T_779; // @[RegisterRouter.scala:87:24] wire out_romask_779 = |_out_romask_T_779; // @[RegisterRouter.scala:87:24] wire out_womask_779 = &_out_womask_T_779; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_779 = out_rivalid_1_633 & out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7688 = out_f_rivalid_779; // @[RegisterRouter.scala:87:24] wire out_f_roready_779 = out_roready_1_633 & out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7689 = out_f_roready_779; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_779 = out_wivalid_1_633 & out_wimask_779; // @[RegisterRouter.scala:87:24] wire out_f_woready_779 = out_woready_1_633 & out_womask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7690 = ~out_rimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7691 = ~out_wimask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7692 = ~out_romask_779; // @[RegisterRouter.scala:87:24] wire _out_T_7693 = ~out_womask_779; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7695 = _out_T_7694; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_663 = _out_T_7695; // @[RegisterRouter.scala:87:24] wire out_rimask_780 = |_out_rimask_T_780; // @[RegisterRouter.scala:87:24] wire out_wimask_780 = &_out_wimask_T_780; // @[RegisterRouter.scala:87:24] wire out_romask_780 = |_out_romask_T_780; // @[RegisterRouter.scala:87:24] wire out_womask_780 = &_out_womask_T_780; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_780 = out_rivalid_1_634 & out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7697 = out_f_rivalid_780; // @[RegisterRouter.scala:87:24] wire out_f_roready_780 = out_roready_1_634 & out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7698 = out_f_roready_780; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_780 = out_wivalid_1_634 & out_wimask_780; // @[RegisterRouter.scala:87:24] wire out_f_woready_780 = out_woready_1_634 & out_womask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7699 = ~out_rimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7700 = ~out_wimask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7701 = ~out_romask_780; // @[RegisterRouter.scala:87:24] wire _out_T_7702 = ~out_womask_780; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_663 = {hi_250, flags_0_go, _out_prepend_T_663}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7703 = out_prepend_663; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7704 = _out_T_7703; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_664 = _out_T_7704; // @[RegisterRouter.scala:87:24] wire out_rimask_781 = |_out_rimask_T_781; // @[RegisterRouter.scala:87:24] wire out_wimask_781 = &_out_wimask_T_781; // @[RegisterRouter.scala:87:24] wire out_romask_781 = |_out_romask_T_781; // @[RegisterRouter.scala:87:24] wire out_womask_781 = &_out_womask_T_781; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_781 = out_rivalid_1_635 & out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7706 = out_f_rivalid_781; // @[RegisterRouter.scala:87:24] wire out_f_roready_781 = out_roready_1_635 & out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7707 = out_f_roready_781; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_781 = out_wivalid_1_635 & out_wimask_781; // @[RegisterRouter.scala:87:24] wire out_f_woready_781 = out_woready_1_635 & out_womask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7708 = ~out_rimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7709 = ~out_wimask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7710 = ~out_romask_781; // @[RegisterRouter.scala:87:24] wire _out_T_7711 = ~out_womask_781; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_664 = {hi_251, flags_0_go, _out_prepend_T_664}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7712 = out_prepend_664; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7713 = _out_T_7712; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_665 = _out_T_7713; // @[RegisterRouter.scala:87:24] wire out_rimask_782 = |_out_rimask_T_782; // @[RegisterRouter.scala:87:24] wire out_wimask_782 = &_out_wimask_T_782; // @[RegisterRouter.scala:87:24] wire out_romask_782 = |_out_romask_T_782; // @[RegisterRouter.scala:87:24] wire out_womask_782 = &_out_womask_T_782; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_782 = out_rivalid_1_636 & out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7715 = out_f_rivalid_782; // @[RegisterRouter.scala:87:24] wire out_f_roready_782 = out_roready_1_636 & out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7716 = out_f_roready_782; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_782 = out_wivalid_1_636 & out_wimask_782; // @[RegisterRouter.scala:87:24] wire out_f_woready_782 = out_woready_1_636 & out_womask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7717 = ~out_rimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7718 = ~out_wimask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7719 = ~out_romask_782; // @[RegisterRouter.scala:87:24] wire _out_T_7720 = ~out_womask_782; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_665 = {hi_252, flags_0_go, _out_prepend_T_665}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7721 = out_prepend_665; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7722 = _out_T_7721; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_666 = _out_T_7722; // @[RegisterRouter.scala:87:24] wire out_rimask_783 = |_out_rimask_T_783; // @[RegisterRouter.scala:87:24] wire out_wimask_783 = &_out_wimask_T_783; // @[RegisterRouter.scala:87:24] wire out_romask_783 = |_out_romask_T_783; // @[RegisterRouter.scala:87:24] wire out_womask_783 = &_out_womask_T_783; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_783 = out_rivalid_1_637 & out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7724 = out_f_rivalid_783; // @[RegisterRouter.scala:87:24] wire out_f_roready_783 = out_roready_1_637 & out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7725 = out_f_roready_783; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_783 = out_wivalid_1_637 & out_wimask_783; // @[RegisterRouter.scala:87:24] wire out_f_woready_783 = out_woready_1_637 & out_womask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7726 = ~out_rimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7727 = ~out_wimask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7728 = ~out_romask_783; // @[RegisterRouter.scala:87:24] wire _out_T_7729 = ~out_womask_783; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_666 = {hi_253, flags_0_go, _out_prepend_T_666}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7730 = out_prepend_666; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7731 = _out_T_7730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_667 = _out_T_7731; // @[RegisterRouter.scala:87:24] wire out_rimask_784 = |_out_rimask_T_784; // @[RegisterRouter.scala:87:24] wire out_wimask_784 = &_out_wimask_T_784; // @[RegisterRouter.scala:87:24] wire out_romask_784 = |_out_romask_T_784; // @[RegisterRouter.scala:87:24] wire out_womask_784 = &_out_womask_T_784; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_784 = out_rivalid_1_638 & out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7733 = out_f_rivalid_784; // @[RegisterRouter.scala:87:24] wire out_f_roready_784 = out_roready_1_638 & out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7734 = out_f_roready_784; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_784 = out_wivalid_1_638 & out_wimask_784; // @[RegisterRouter.scala:87:24] wire out_f_woready_784 = out_woready_1_638 & out_womask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7735 = ~out_rimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7736 = ~out_wimask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7737 = ~out_romask_784; // @[RegisterRouter.scala:87:24] wire _out_T_7738 = ~out_womask_784; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_667 = {hi_254, flags_0_go, _out_prepend_T_667}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7739 = out_prepend_667; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7740 = _out_T_7739; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_668 = _out_T_7740; // @[RegisterRouter.scala:87:24] wire out_rimask_785 = |_out_rimask_T_785; // @[RegisterRouter.scala:87:24] wire out_wimask_785 = &_out_wimask_T_785; // @[RegisterRouter.scala:87:24] wire out_romask_785 = |_out_romask_T_785; // @[RegisterRouter.scala:87:24] wire out_womask_785 = &_out_womask_T_785; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_785 = out_rivalid_1_639 & out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7742 = out_f_rivalid_785; // @[RegisterRouter.scala:87:24] wire out_f_roready_785 = out_roready_1_639 & out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7743 = out_f_roready_785; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_785 = out_wivalid_1_639 & out_wimask_785; // @[RegisterRouter.scala:87:24] wire out_f_woready_785 = out_woready_1_639 & out_womask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7744 = ~out_rimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7745 = ~out_wimask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7746 = ~out_romask_785; // @[RegisterRouter.scala:87:24] wire _out_T_7747 = ~out_womask_785; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_668 = {hi_255, flags_0_go, _out_prepend_T_668}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7748 = out_prepend_668; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7749 = _out_T_7748; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_669 = _out_T_7749; // @[RegisterRouter.scala:87:24] wire out_rimask_786 = |_out_rimask_T_786; // @[RegisterRouter.scala:87:24] wire out_wimask_786 = &_out_wimask_T_786; // @[RegisterRouter.scala:87:24] wire out_romask_786 = |_out_romask_T_786; // @[RegisterRouter.scala:87:24] wire out_womask_786 = &_out_womask_T_786; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_786 = out_rivalid_1_640 & out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7751 = out_f_rivalid_786; // @[RegisterRouter.scala:87:24] wire out_f_roready_786 = out_roready_1_640 & out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7752 = out_f_roready_786; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_786 = out_wivalid_1_640 & out_wimask_786; // @[RegisterRouter.scala:87:24] wire out_f_woready_786 = out_woready_1_640 & out_womask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7753 = ~out_rimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7754 = ~out_wimask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7755 = ~out_romask_786; // @[RegisterRouter.scala:87:24] wire _out_T_7756 = ~out_womask_786; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_669 = {hi_256, flags_0_go, _out_prepend_T_669}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7757 = out_prepend_669; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7758 = _out_T_7757; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_159 = _out_T_7758; // @[MuxLiteral.scala:49:48] wire out_rimask_787 = |_out_rimask_T_787; // @[RegisterRouter.scala:87:24] wire out_wimask_787 = &_out_wimask_T_787; // @[RegisterRouter.scala:87:24] wire out_romask_787 = |_out_romask_T_787; // @[RegisterRouter.scala:87:24] wire out_womask_787 = &_out_womask_T_787; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_787 = out_rivalid_1_641 & out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7760 = out_f_rivalid_787; // @[RegisterRouter.scala:87:24] wire out_f_roready_787 = out_roready_1_641 & out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7761 = out_f_roready_787; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_787 = out_wivalid_1_641 & out_wimask_787; // @[RegisterRouter.scala:87:24] wire out_f_woready_787 = out_woready_1_641 & out_womask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7762 = ~out_rimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7763 = ~out_wimask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7764 = ~out_romask_787; // @[RegisterRouter.scala:87:24] wire _out_T_7765 = ~out_womask_787; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7767 = _out_T_7766; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_670 = _out_T_7767; // @[RegisterRouter.scala:87:24] wire out_rimask_788 = |_out_rimask_T_788; // @[RegisterRouter.scala:87:24] wire out_wimask_788 = &_out_wimask_T_788; // @[RegisterRouter.scala:87:24] wire out_romask_788 = |_out_romask_T_788; // @[RegisterRouter.scala:87:24] wire out_womask_788 = &_out_womask_T_788; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_788 = out_rivalid_1_642 & out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7769 = out_f_rivalid_788; // @[RegisterRouter.scala:87:24] wire out_f_roready_788 = out_roready_1_642 & out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7770 = out_f_roready_788; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_788 = out_wivalid_1_642 & out_wimask_788; // @[RegisterRouter.scala:87:24] wire out_f_woready_788 = out_woready_1_642 & out_womask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7771 = ~out_rimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7772 = ~out_wimask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7773 = ~out_romask_788; // @[RegisterRouter.scala:87:24] wire _out_T_7774 = ~out_womask_788; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_670 = {hi_474, flags_0_go, _out_prepend_T_670}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7775 = out_prepend_670; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7776 = _out_T_7775; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_671 = _out_T_7776; // @[RegisterRouter.scala:87:24] wire out_rimask_789 = |_out_rimask_T_789; // @[RegisterRouter.scala:87:24] wire out_wimask_789 = &_out_wimask_T_789; // @[RegisterRouter.scala:87:24] wire out_romask_789 = |_out_romask_T_789; // @[RegisterRouter.scala:87:24] wire out_womask_789 = &_out_womask_T_789; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_789 = out_rivalid_1_643 & out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7778 = out_f_rivalid_789; // @[RegisterRouter.scala:87:24] wire out_f_roready_789 = out_roready_1_643 & out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7779 = out_f_roready_789; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_789 = out_wivalid_1_643 & out_wimask_789; // @[RegisterRouter.scala:87:24] wire out_f_woready_789 = out_woready_1_643 & out_womask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7780 = ~out_rimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7781 = ~out_wimask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7782 = ~out_romask_789; // @[RegisterRouter.scala:87:24] wire _out_T_7783 = ~out_womask_789; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_671 = {hi_475, flags_0_go, _out_prepend_T_671}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7784 = out_prepend_671; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7785 = _out_T_7784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_672 = _out_T_7785; // @[RegisterRouter.scala:87:24] wire out_rimask_790 = |_out_rimask_T_790; // @[RegisterRouter.scala:87:24] wire out_wimask_790 = &_out_wimask_T_790; // @[RegisterRouter.scala:87:24] wire out_romask_790 = |_out_romask_T_790; // @[RegisterRouter.scala:87:24] wire out_womask_790 = &_out_womask_T_790; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_790 = out_rivalid_1_644 & out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7787 = out_f_rivalid_790; // @[RegisterRouter.scala:87:24] wire out_f_roready_790 = out_roready_1_644 & out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7788 = out_f_roready_790; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_790 = out_wivalid_1_644 & out_wimask_790; // @[RegisterRouter.scala:87:24] wire out_f_woready_790 = out_woready_1_644 & out_womask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7789 = ~out_rimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7790 = ~out_wimask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7791 = ~out_romask_790; // @[RegisterRouter.scala:87:24] wire _out_T_7792 = ~out_womask_790; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_672 = {hi_476, flags_0_go, _out_prepend_T_672}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7793 = out_prepend_672; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7794 = _out_T_7793; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_673 = _out_T_7794; // @[RegisterRouter.scala:87:24] wire out_rimask_791 = |_out_rimask_T_791; // @[RegisterRouter.scala:87:24] wire out_wimask_791 = &_out_wimask_T_791; // @[RegisterRouter.scala:87:24] wire out_romask_791 = |_out_romask_T_791; // @[RegisterRouter.scala:87:24] wire out_womask_791 = &_out_womask_T_791; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_791 = out_rivalid_1_645 & out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7796 = out_f_rivalid_791; // @[RegisterRouter.scala:87:24] wire out_f_roready_791 = out_roready_1_645 & out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7797 = out_f_roready_791; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_791 = out_wivalid_1_645 & out_wimask_791; // @[RegisterRouter.scala:87:24] wire out_f_woready_791 = out_woready_1_645 & out_womask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7798 = ~out_rimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7799 = ~out_wimask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7800 = ~out_romask_791; // @[RegisterRouter.scala:87:24] wire _out_T_7801 = ~out_womask_791; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_673 = {hi_477, flags_0_go, _out_prepend_T_673}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7802 = out_prepend_673; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7803 = _out_T_7802; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_674 = _out_T_7803; // @[RegisterRouter.scala:87:24] wire out_rimask_792 = |_out_rimask_T_792; // @[RegisterRouter.scala:87:24] wire out_wimask_792 = &_out_wimask_T_792; // @[RegisterRouter.scala:87:24] wire out_romask_792 = |_out_romask_T_792; // @[RegisterRouter.scala:87:24] wire out_womask_792 = &_out_womask_T_792; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_792 = out_rivalid_1_646 & out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7805 = out_f_rivalid_792; // @[RegisterRouter.scala:87:24] wire out_f_roready_792 = out_roready_1_646 & out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7806 = out_f_roready_792; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_792 = out_wivalid_1_646 & out_wimask_792; // @[RegisterRouter.scala:87:24] wire out_f_woready_792 = out_woready_1_646 & out_womask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7807 = ~out_rimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7808 = ~out_wimask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7809 = ~out_romask_792; // @[RegisterRouter.scala:87:24] wire _out_T_7810 = ~out_womask_792; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_674 = {hi_478, flags_0_go, _out_prepend_T_674}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7811 = out_prepend_674; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7812 = _out_T_7811; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_675 = _out_T_7812; // @[RegisterRouter.scala:87:24] wire out_rimask_793 = |_out_rimask_T_793; // @[RegisterRouter.scala:87:24] wire out_wimask_793 = &_out_wimask_T_793; // @[RegisterRouter.scala:87:24] wire out_romask_793 = |_out_romask_T_793; // @[RegisterRouter.scala:87:24] wire out_womask_793 = &_out_womask_T_793; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_793 = out_rivalid_1_647 & out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7814 = out_f_rivalid_793; // @[RegisterRouter.scala:87:24] wire out_f_roready_793 = out_roready_1_647 & out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7815 = out_f_roready_793; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_793 = out_wivalid_1_647 & out_wimask_793; // @[RegisterRouter.scala:87:24] wire out_f_woready_793 = out_woready_1_647 & out_womask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7816 = ~out_rimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7817 = ~out_wimask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7818 = ~out_romask_793; // @[RegisterRouter.scala:87:24] wire _out_T_7819 = ~out_womask_793; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_675 = {hi_479, flags_0_go, _out_prepend_T_675}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7820 = out_prepend_675; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7821 = _out_T_7820; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_676 = _out_T_7821; // @[RegisterRouter.scala:87:24] wire out_rimask_794 = |_out_rimask_T_794; // @[RegisterRouter.scala:87:24] wire out_wimask_794 = &_out_wimask_T_794; // @[RegisterRouter.scala:87:24] wire out_romask_794 = |_out_romask_T_794; // @[RegisterRouter.scala:87:24] wire out_womask_794 = &_out_womask_T_794; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_794 = out_rivalid_1_648 & out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7823 = out_f_rivalid_794; // @[RegisterRouter.scala:87:24] wire out_f_roready_794 = out_roready_1_648 & out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7824 = out_f_roready_794; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_794 = out_wivalid_1_648 & out_wimask_794; // @[RegisterRouter.scala:87:24] wire out_f_woready_794 = out_woready_1_648 & out_womask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7825 = ~out_rimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7826 = ~out_wimask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7827 = ~out_romask_794; // @[RegisterRouter.scala:87:24] wire _out_T_7828 = ~out_womask_794; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_676 = {hi_480, flags_0_go, _out_prepend_T_676}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7829 = out_prepend_676; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7830 = _out_T_7829; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_187 = _out_T_7830; // @[MuxLiteral.scala:49:48] wire out_rimask_795 = |_out_rimask_T_795; // @[RegisterRouter.scala:87:24] wire out_wimask_795 = &_out_wimask_T_795; // @[RegisterRouter.scala:87:24] wire out_romask_795 = |_out_romask_T_795; // @[RegisterRouter.scala:87:24] wire out_womask_795 = &_out_womask_T_795; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_795 = out_rivalid_1_649 & out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7832 = out_f_rivalid_795; // @[RegisterRouter.scala:87:24] wire out_f_roready_795 = out_roready_1_649 & out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7833 = out_f_roready_795; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_795 = out_wivalid_1_649 & out_wimask_795; // @[RegisterRouter.scala:87:24] wire out_f_woready_795 = out_woready_1_649 & out_womask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7834 = ~out_rimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7835 = ~out_wimask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7836 = ~out_romask_795; // @[RegisterRouter.scala:87:24] wire _out_T_7837 = ~out_womask_795; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7839 = _out_T_7838; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_677 = _out_T_7839; // @[RegisterRouter.scala:87:24] wire out_rimask_796 = |_out_rimask_T_796; // @[RegisterRouter.scala:87:24] wire out_wimask_796 = &_out_wimask_T_796; // @[RegisterRouter.scala:87:24] wire out_romask_796 = |_out_romask_T_796; // @[RegisterRouter.scala:87:24] wire out_womask_796 = &_out_womask_T_796; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_796 = out_rivalid_1_650 & out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7841 = out_f_rivalid_796; // @[RegisterRouter.scala:87:24] wire out_f_roready_796 = out_roready_1_650 & out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7842 = out_f_roready_796; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_796 = out_wivalid_1_650 & out_wimask_796; // @[RegisterRouter.scala:87:24] wire out_f_woready_796 = out_woready_1_650 & out_womask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7843 = ~out_rimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7844 = ~out_wimask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7845 = ~out_romask_796; // @[RegisterRouter.scala:87:24] wire _out_T_7846 = ~out_womask_796; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_677 = {hi_354, flags_0_go, _out_prepend_T_677}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7847 = out_prepend_677; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7848 = _out_T_7847; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_678 = _out_T_7848; // @[RegisterRouter.scala:87:24] wire out_rimask_797 = |_out_rimask_T_797; // @[RegisterRouter.scala:87:24] wire out_wimask_797 = &_out_wimask_T_797; // @[RegisterRouter.scala:87:24] wire out_romask_797 = |_out_romask_T_797; // @[RegisterRouter.scala:87:24] wire out_womask_797 = &_out_womask_T_797; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_797 = out_rivalid_1_651 & out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7850 = out_f_rivalid_797; // @[RegisterRouter.scala:87:24] wire out_f_roready_797 = out_roready_1_651 & out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7851 = out_f_roready_797; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_797 = out_wivalid_1_651 & out_wimask_797; // @[RegisterRouter.scala:87:24] wire out_f_woready_797 = out_woready_1_651 & out_womask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7852 = ~out_rimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7853 = ~out_wimask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7854 = ~out_romask_797; // @[RegisterRouter.scala:87:24] wire _out_T_7855 = ~out_womask_797; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_678 = {hi_355, flags_0_go, _out_prepend_T_678}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7856 = out_prepend_678; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7857 = _out_T_7856; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_679 = _out_T_7857; // @[RegisterRouter.scala:87:24] wire out_rimask_798 = |_out_rimask_T_798; // @[RegisterRouter.scala:87:24] wire out_wimask_798 = &_out_wimask_T_798; // @[RegisterRouter.scala:87:24] wire out_romask_798 = |_out_romask_T_798; // @[RegisterRouter.scala:87:24] wire out_womask_798 = &_out_womask_T_798; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_798 = out_rivalid_1_652 & out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7859 = out_f_rivalid_798; // @[RegisterRouter.scala:87:24] wire out_f_roready_798 = out_roready_1_652 & out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7860 = out_f_roready_798; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_798 = out_wivalid_1_652 & out_wimask_798; // @[RegisterRouter.scala:87:24] wire out_f_woready_798 = out_woready_1_652 & out_womask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7861 = ~out_rimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7862 = ~out_wimask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7863 = ~out_romask_798; // @[RegisterRouter.scala:87:24] wire _out_T_7864 = ~out_womask_798; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_679 = {hi_356, flags_0_go, _out_prepend_T_679}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7865 = out_prepend_679; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7866 = _out_T_7865; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_680 = _out_T_7866; // @[RegisterRouter.scala:87:24] wire out_rimask_799 = |_out_rimask_T_799; // @[RegisterRouter.scala:87:24] wire out_wimask_799 = &_out_wimask_T_799; // @[RegisterRouter.scala:87:24] wire out_romask_799 = |_out_romask_T_799; // @[RegisterRouter.scala:87:24] wire out_womask_799 = &_out_womask_T_799; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_799 = out_rivalid_1_653 & out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7868 = out_f_rivalid_799; // @[RegisterRouter.scala:87:24] wire out_f_roready_799 = out_roready_1_653 & out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7869 = out_f_roready_799; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_799 = out_wivalid_1_653 & out_wimask_799; // @[RegisterRouter.scala:87:24] wire out_f_woready_799 = out_woready_1_653 & out_womask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7870 = ~out_rimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7871 = ~out_wimask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7872 = ~out_romask_799; // @[RegisterRouter.scala:87:24] wire _out_T_7873 = ~out_womask_799; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_680 = {hi_357, flags_0_go, _out_prepend_T_680}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7874 = out_prepend_680; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7875 = _out_T_7874; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_681 = _out_T_7875; // @[RegisterRouter.scala:87:24] wire out_rimask_800 = |_out_rimask_T_800; // @[RegisterRouter.scala:87:24] wire out_wimask_800 = &_out_wimask_T_800; // @[RegisterRouter.scala:87:24] wire out_romask_800 = |_out_romask_T_800; // @[RegisterRouter.scala:87:24] wire out_womask_800 = &_out_womask_T_800; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_800 = out_rivalid_1_654 & out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7877 = out_f_rivalid_800; // @[RegisterRouter.scala:87:24] wire out_f_roready_800 = out_roready_1_654 & out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7878 = out_f_roready_800; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_800 = out_wivalid_1_654 & out_wimask_800; // @[RegisterRouter.scala:87:24] wire out_f_woready_800 = out_woready_1_654 & out_womask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7879 = ~out_rimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7880 = ~out_wimask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7881 = ~out_romask_800; // @[RegisterRouter.scala:87:24] wire _out_T_7882 = ~out_womask_800; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_681 = {hi_358, flags_0_go, _out_prepend_T_681}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7883 = out_prepend_681; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7884 = _out_T_7883; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_682 = _out_T_7884; // @[RegisterRouter.scala:87:24] wire out_rimask_801 = |_out_rimask_T_801; // @[RegisterRouter.scala:87:24] wire out_wimask_801 = &_out_wimask_T_801; // @[RegisterRouter.scala:87:24] wire out_romask_801 = |_out_romask_T_801; // @[RegisterRouter.scala:87:24] wire out_womask_801 = &_out_womask_T_801; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_801 = out_rivalid_1_655 & out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7886 = out_f_rivalid_801; // @[RegisterRouter.scala:87:24] wire out_f_roready_801 = out_roready_1_655 & out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7887 = out_f_roready_801; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_801 = out_wivalid_1_655 & out_wimask_801; // @[RegisterRouter.scala:87:24] wire out_f_woready_801 = out_woready_1_655 & out_womask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7888 = ~out_rimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7889 = ~out_wimask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7890 = ~out_romask_801; // @[RegisterRouter.scala:87:24] wire _out_T_7891 = ~out_womask_801; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_682 = {hi_359, flags_0_go, _out_prepend_T_682}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7892 = out_prepend_682; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7893 = _out_T_7892; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_683 = _out_T_7893; // @[RegisterRouter.scala:87:24] wire out_rimask_802 = |_out_rimask_T_802; // @[RegisterRouter.scala:87:24] wire out_wimask_802 = &_out_wimask_T_802; // @[RegisterRouter.scala:87:24] wire out_romask_802 = |_out_romask_T_802; // @[RegisterRouter.scala:87:24] wire out_womask_802 = &_out_womask_T_802; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_802 = out_rivalid_1_656 & out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7895 = out_f_rivalid_802; // @[RegisterRouter.scala:87:24] wire out_f_roready_802 = out_roready_1_656 & out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7896 = out_f_roready_802; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_802 = out_wivalid_1_656 & out_wimask_802; // @[RegisterRouter.scala:87:24] wire out_f_woready_802 = out_woready_1_656 & out_womask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7897 = ~out_rimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7898 = ~out_wimask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7899 = ~out_romask_802; // @[RegisterRouter.scala:87:24] wire _out_T_7900 = ~out_womask_802; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_683 = {hi_360, flags_0_go, _out_prepend_T_683}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7901 = out_prepend_683; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7902 = _out_T_7901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_172 = _out_T_7902; // @[MuxLiteral.scala:49:48] wire out_rimask_803 = |_out_rimask_T_803; // @[RegisterRouter.scala:87:24] wire out_wimask_803 = &_out_wimask_T_803; // @[RegisterRouter.scala:87:24] wire out_romask_803 = |_out_romask_T_803; // @[RegisterRouter.scala:87:24] wire out_womask_803 = &_out_womask_T_803; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_803 = out_rivalid_1_657 & out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7904 = out_f_rivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_roready_803 = out_roready_1_657 & out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7905 = out_f_roready_803; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_803 = out_wivalid_1_657 & out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7906 = out_f_wivalid_803; // @[RegisterRouter.scala:87:24] wire out_f_woready_803 = out_woready_1_657 & out_womask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7907 = out_f_woready_803; // @[RegisterRouter.scala:87:24] wire _out_T_7908 = ~out_rimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7909 = ~out_wimask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7910 = ~out_romask_803; // @[RegisterRouter.scala:87:24] wire _out_T_7911 = ~out_womask_803; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7913 = _out_T_7912; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_684 = _out_T_7913; // @[RegisterRouter.scala:87:24] wire out_rimask_804 = |_out_rimask_T_804; // @[RegisterRouter.scala:87:24] wire out_wimask_804 = &_out_wimask_T_804; // @[RegisterRouter.scala:87:24] wire out_romask_804 = |_out_romask_T_804; // @[RegisterRouter.scala:87:24] wire out_womask_804 = &_out_womask_T_804; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_804 = out_rivalid_1_658 & out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7915 = out_f_rivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_roready_804 = out_roready_1_658 & out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7916 = out_f_roready_804; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_804 = out_wivalid_1_658 & out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7917 = out_f_wivalid_804; // @[RegisterRouter.scala:87:24] wire out_f_woready_804 = out_woready_1_658 & out_womask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7918 = out_f_woready_804; // @[RegisterRouter.scala:87:24] wire _out_T_7919 = ~out_rimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7920 = ~out_wimask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7921 = ~out_romask_804; // @[RegisterRouter.scala:87:24] wire _out_T_7922 = ~out_womask_804; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_684 = {abstractDataMem_9, _out_prepend_T_684}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7923 = out_prepend_684; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_7924 = _out_T_7923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_685 = _out_T_7924; // @[RegisterRouter.scala:87:24] wire out_rimask_805 = |_out_rimask_T_805; // @[RegisterRouter.scala:87:24] wire out_wimask_805 = &_out_wimask_T_805; // @[RegisterRouter.scala:87:24] wire out_romask_805 = |_out_romask_T_805; // @[RegisterRouter.scala:87:24] wire out_womask_805 = &_out_womask_T_805; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_805 = out_rivalid_1_659 & out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7926 = out_f_rivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_roready_805 = out_roready_1_659 & out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7927 = out_f_roready_805; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_805 = out_wivalid_1_659 & out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7928 = out_f_wivalid_805; // @[RegisterRouter.scala:87:24] wire out_f_woready_805 = out_woready_1_659 & out_womask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7929 = out_f_woready_805; // @[RegisterRouter.scala:87:24] wire _out_T_7930 = ~out_rimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7931 = ~out_wimask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7932 = ~out_romask_805; // @[RegisterRouter.scala:87:24] wire _out_T_7933 = ~out_womask_805; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_685 = {abstractDataMem_10, _out_prepend_T_685}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7934 = out_prepend_685; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_7935 = _out_T_7934; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_686 = _out_T_7935; // @[RegisterRouter.scala:87:24] wire out_rimask_806 = |_out_rimask_T_806; // @[RegisterRouter.scala:87:24] wire out_wimask_806 = &_out_wimask_T_806; // @[RegisterRouter.scala:87:24] wire out_romask_806 = |_out_romask_T_806; // @[RegisterRouter.scala:87:24] wire out_womask_806 = &_out_womask_T_806; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_806 = out_rivalid_1_660 & out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7937 = out_f_rivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_roready_806 = out_roready_1_660 & out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7938 = out_f_roready_806; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_806 = out_wivalid_1_660 & out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7939 = out_f_wivalid_806; // @[RegisterRouter.scala:87:24] wire out_f_woready_806 = out_woready_1_660 & out_womask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7940 = out_f_woready_806; // @[RegisterRouter.scala:87:24] wire _out_T_7941 = ~out_rimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7942 = ~out_wimask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7943 = ~out_romask_806; // @[RegisterRouter.scala:87:24] wire _out_T_7944 = ~out_womask_806; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_686 = {abstractDataMem_11, _out_prepend_T_686}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7945 = out_prepend_686; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_7946 = _out_T_7945; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_687 = _out_T_7946; // @[RegisterRouter.scala:87:24] wire out_rimask_807 = |_out_rimask_T_807; // @[RegisterRouter.scala:87:24] wire out_wimask_807 = &_out_wimask_T_807; // @[RegisterRouter.scala:87:24] wire out_romask_807 = |_out_romask_T_807; // @[RegisterRouter.scala:87:24] wire out_womask_807 = &_out_womask_T_807; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_807 = out_rivalid_1_661 & out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7948 = out_f_rivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_roready_807 = out_roready_1_661 & out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7949 = out_f_roready_807; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_807 = out_wivalid_1_661 & out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7950 = out_f_wivalid_807; // @[RegisterRouter.scala:87:24] wire out_f_woready_807 = out_woready_1_661 & out_womask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7951 = out_f_woready_807; // @[RegisterRouter.scala:87:24] wire _out_T_7952 = ~out_rimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7953 = ~out_wimask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7954 = ~out_romask_807; // @[RegisterRouter.scala:87:24] wire _out_T_7955 = ~out_womask_807; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_687 = {abstractDataMem_12, _out_prepend_T_687}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7956 = out_prepend_687; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_7957 = _out_T_7956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_688 = _out_T_7957; // @[RegisterRouter.scala:87:24] wire out_rimask_808 = |_out_rimask_T_808; // @[RegisterRouter.scala:87:24] wire out_wimask_808 = &_out_wimask_T_808; // @[RegisterRouter.scala:87:24] wire out_romask_808 = |_out_romask_T_808; // @[RegisterRouter.scala:87:24] wire out_womask_808 = &_out_womask_T_808; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_808 = out_rivalid_1_662 & out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7959 = out_f_rivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_roready_808 = out_roready_1_662 & out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7960 = out_f_roready_808; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_808 = out_wivalid_1_662 & out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7961 = out_f_wivalid_808; // @[RegisterRouter.scala:87:24] wire out_f_woready_808 = out_woready_1_662 & out_womask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7962 = out_f_woready_808; // @[RegisterRouter.scala:87:24] wire _out_T_7963 = ~out_rimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7964 = ~out_wimask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7965 = ~out_romask_808; // @[RegisterRouter.scala:87:24] wire _out_T_7966 = ~out_womask_808; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_688 = {abstractDataMem_13, _out_prepend_T_688}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7967 = out_prepend_688; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_7968 = _out_T_7967; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_689 = _out_T_7968; // @[RegisterRouter.scala:87:24] wire out_rimask_809 = |_out_rimask_T_809; // @[RegisterRouter.scala:87:24] wire out_wimask_809 = &_out_wimask_T_809; // @[RegisterRouter.scala:87:24] wire out_romask_809 = |_out_romask_T_809; // @[RegisterRouter.scala:87:24] wire out_womask_809 = &_out_womask_T_809; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_809 = out_rivalid_1_663 & out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7970 = out_f_rivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_roready_809 = out_roready_1_663 & out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7971 = out_f_roready_809; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_809 = out_wivalid_1_663 & out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7972 = out_f_wivalid_809; // @[RegisterRouter.scala:87:24] wire out_f_woready_809 = out_woready_1_663 & out_womask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7973 = out_f_woready_809; // @[RegisterRouter.scala:87:24] wire _out_T_7974 = ~out_rimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7975 = ~out_wimask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7976 = ~out_romask_809; // @[RegisterRouter.scala:87:24] wire _out_T_7977 = ~out_womask_809; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_689 = {abstractDataMem_14, _out_prepend_T_689}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7978 = out_prepend_689; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_7979 = _out_T_7978; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_690 = _out_T_7979; // @[RegisterRouter.scala:87:24] wire out_rimask_810 = |_out_rimask_T_810; // @[RegisterRouter.scala:87:24] wire out_wimask_810 = &_out_wimask_T_810; // @[RegisterRouter.scala:87:24] wire out_romask_810 = |_out_romask_T_810; // @[RegisterRouter.scala:87:24] wire out_womask_810 = &_out_womask_T_810; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_810 = out_rivalid_1_664 & out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7981 = out_f_rivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_roready_810 = out_roready_1_664 & out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7982 = out_f_roready_810; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_810 = out_wivalid_1_664 & out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7983 = out_f_wivalid_810; // @[RegisterRouter.scala:87:24] wire out_f_woready_810 = out_woready_1_664 & out_womask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7984 = out_f_woready_810; // @[RegisterRouter.scala:87:24] wire _out_T_7985 = ~out_rimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7986 = ~out_wimask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7987 = ~out_romask_810; // @[RegisterRouter.scala:87:24] wire _out_T_7988 = ~out_womask_810; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_690 = {abstractDataMem_15, _out_prepend_T_690}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7989 = out_prepend_690; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_7990 = _out_T_7989; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_113 = _out_T_7990; // @[MuxLiteral.scala:49:48] wire out_rimask_811 = |_out_rimask_T_811; // @[RegisterRouter.scala:87:24] wire out_wimask_811 = &_out_wimask_T_811; // @[RegisterRouter.scala:87:24] wire out_romask_811 = |_out_romask_T_811; // @[RegisterRouter.scala:87:24] wire out_womask_811 = &_out_womask_T_811; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_811 = out_rivalid_1_665 & out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7992 = out_f_rivalid_811; // @[RegisterRouter.scala:87:24] wire out_f_roready_811 = out_roready_1_665 & out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7993 = out_f_roready_811; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_811 = out_wivalid_1_665 & out_wimask_811; // @[RegisterRouter.scala:87:24] wire out_f_woready_811 = out_woready_1_665 & out_womask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7994 = ~out_rimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7995 = ~out_wimask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7996 = ~out_romask_811; // @[RegisterRouter.scala:87:24] wire _out_T_7997 = ~out_womask_811; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_7999 = _out_T_7998; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_691 = _out_T_7999; // @[RegisterRouter.scala:87:24] wire out_rimask_812 = |_out_rimask_T_812; // @[RegisterRouter.scala:87:24] wire out_wimask_812 = &_out_wimask_T_812; // @[RegisterRouter.scala:87:24] wire out_romask_812 = |_out_romask_T_812; // @[RegisterRouter.scala:87:24] wire out_womask_812 = &_out_womask_T_812; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_812 = out_rivalid_1_666 & out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8001 = out_f_rivalid_812; // @[RegisterRouter.scala:87:24] wire out_f_roready_812 = out_roready_1_666 & out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8002 = out_f_roready_812; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_812 = out_wivalid_1_666 & out_wimask_812; // @[RegisterRouter.scala:87:24] wire out_f_woready_812 = out_woready_1_666 & out_womask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8003 = ~out_rimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8004 = ~out_wimask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8005 = ~out_romask_812; // @[RegisterRouter.scala:87:24] wire _out_T_8006 = ~out_womask_812; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_691 = {hi_730, flags_0_go, _out_prepend_T_691}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8007 = out_prepend_691; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8008 = _out_T_8007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_692 = _out_T_8008; // @[RegisterRouter.scala:87:24] wire out_rimask_813 = |_out_rimask_T_813; // @[RegisterRouter.scala:87:24] wire out_wimask_813 = &_out_wimask_T_813; // @[RegisterRouter.scala:87:24] wire out_romask_813 = |_out_romask_T_813; // @[RegisterRouter.scala:87:24] wire out_womask_813 = &_out_womask_T_813; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_813 = out_rivalid_1_667 & out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8010 = out_f_rivalid_813; // @[RegisterRouter.scala:87:24] wire out_f_roready_813 = out_roready_1_667 & out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8011 = out_f_roready_813; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_813 = out_wivalid_1_667 & out_wimask_813; // @[RegisterRouter.scala:87:24] wire out_f_woready_813 = out_woready_1_667 & out_womask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8012 = ~out_rimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8013 = ~out_wimask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8014 = ~out_romask_813; // @[RegisterRouter.scala:87:24] wire _out_T_8015 = ~out_womask_813; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_692 = {hi_731, flags_0_go, _out_prepend_T_692}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8016 = out_prepend_692; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8017 = _out_T_8016; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_693 = _out_T_8017; // @[RegisterRouter.scala:87:24] wire out_rimask_814 = |_out_rimask_T_814; // @[RegisterRouter.scala:87:24] wire out_wimask_814 = &_out_wimask_T_814; // @[RegisterRouter.scala:87:24] wire out_romask_814 = |_out_romask_T_814; // @[RegisterRouter.scala:87:24] wire out_womask_814 = &_out_womask_T_814; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_814 = out_rivalid_1_668 & out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8019 = out_f_rivalid_814; // @[RegisterRouter.scala:87:24] wire out_f_roready_814 = out_roready_1_668 & out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8020 = out_f_roready_814; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_814 = out_wivalid_1_668 & out_wimask_814; // @[RegisterRouter.scala:87:24] wire out_f_woready_814 = out_woready_1_668 & out_womask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8021 = ~out_rimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8022 = ~out_wimask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8023 = ~out_romask_814; // @[RegisterRouter.scala:87:24] wire _out_T_8024 = ~out_womask_814; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_693 = {hi_732, flags_0_go, _out_prepend_T_693}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8025 = out_prepend_693; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8026 = _out_T_8025; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_694 = _out_T_8026; // @[RegisterRouter.scala:87:24] wire out_rimask_815 = |_out_rimask_T_815; // @[RegisterRouter.scala:87:24] wire out_wimask_815 = &_out_wimask_T_815; // @[RegisterRouter.scala:87:24] wire out_romask_815 = |_out_romask_T_815; // @[RegisterRouter.scala:87:24] wire out_womask_815 = &_out_womask_T_815; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_815 = out_rivalid_1_669 & out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8028 = out_f_rivalid_815; // @[RegisterRouter.scala:87:24] wire out_f_roready_815 = out_roready_1_669 & out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8029 = out_f_roready_815; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_815 = out_wivalid_1_669 & out_wimask_815; // @[RegisterRouter.scala:87:24] wire out_f_woready_815 = out_woready_1_669 & out_womask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8030 = ~out_rimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8031 = ~out_wimask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8032 = ~out_romask_815; // @[RegisterRouter.scala:87:24] wire _out_T_8033 = ~out_womask_815; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_694 = {hi_733, flags_0_go, _out_prepend_T_694}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8034 = out_prepend_694; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8035 = _out_T_8034; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_695 = _out_T_8035; // @[RegisterRouter.scala:87:24] wire out_rimask_816 = |_out_rimask_T_816; // @[RegisterRouter.scala:87:24] wire out_wimask_816 = &_out_wimask_T_816; // @[RegisterRouter.scala:87:24] wire out_romask_816 = |_out_romask_T_816; // @[RegisterRouter.scala:87:24] wire out_womask_816 = &_out_womask_T_816; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_816 = out_rivalid_1_670 & out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8037 = out_f_rivalid_816; // @[RegisterRouter.scala:87:24] wire out_f_roready_816 = out_roready_1_670 & out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8038 = out_f_roready_816; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_816 = out_wivalid_1_670 & out_wimask_816; // @[RegisterRouter.scala:87:24] wire out_f_woready_816 = out_woready_1_670 & out_womask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8039 = ~out_rimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8040 = ~out_wimask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8041 = ~out_romask_816; // @[RegisterRouter.scala:87:24] wire _out_T_8042 = ~out_womask_816; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_695 = {hi_734, flags_0_go, _out_prepend_T_695}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8043 = out_prepend_695; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8044 = _out_T_8043; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_696 = _out_T_8044; // @[RegisterRouter.scala:87:24] wire out_rimask_817 = |_out_rimask_T_817; // @[RegisterRouter.scala:87:24] wire out_wimask_817 = &_out_wimask_T_817; // @[RegisterRouter.scala:87:24] wire out_romask_817 = |_out_romask_T_817; // @[RegisterRouter.scala:87:24] wire out_womask_817 = &_out_womask_T_817; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_817 = out_rivalid_1_671 & out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8046 = out_f_rivalid_817; // @[RegisterRouter.scala:87:24] wire out_f_roready_817 = out_roready_1_671 & out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8047 = out_f_roready_817; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_817 = out_wivalid_1_671 & out_wimask_817; // @[RegisterRouter.scala:87:24] wire out_f_woready_817 = out_woready_1_671 & out_womask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8048 = ~out_rimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8049 = ~out_wimask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8050 = ~out_romask_817; // @[RegisterRouter.scala:87:24] wire _out_T_8051 = ~out_womask_817; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_696 = {hi_735, flags_0_go, _out_prepend_T_696}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8052 = out_prepend_696; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8053 = _out_T_8052; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_697 = _out_T_8053; // @[RegisterRouter.scala:87:24] wire out_rimask_818 = |_out_rimask_T_818; // @[RegisterRouter.scala:87:24] wire out_wimask_818 = &_out_wimask_T_818; // @[RegisterRouter.scala:87:24] wire out_romask_818 = |_out_romask_T_818; // @[RegisterRouter.scala:87:24] wire out_womask_818 = &_out_womask_T_818; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_818 = out_rivalid_1_672 & out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8055 = out_f_rivalid_818; // @[RegisterRouter.scala:87:24] wire out_f_roready_818 = out_roready_1_672 & out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8056 = out_f_roready_818; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_818 = out_wivalid_1_672 & out_wimask_818; // @[RegisterRouter.scala:87:24] wire out_f_woready_818 = out_woready_1_672 & out_womask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8057 = ~out_rimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8058 = ~out_wimask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8059 = ~out_romask_818; // @[RegisterRouter.scala:87:24] wire _out_T_8060 = ~out_womask_818; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_697 = {hi_736, flags_0_go, _out_prepend_T_697}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8061 = out_prepend_697; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8062 = _out_T_8061; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_219 = _out_T_8062; // @[MuxLiteral.scala:49:48] wire out_rimask_819 = |_out_rimask_T_819; // @[RegisterRouter.scala:87:24] wire out_wimask_819 = &_out_wimask_T_819; // @[RegisterRouter.scala:87:24] wire out_romask_819 = |_out_romask_T_819; // @[RegisterRouter.scala:87:24] wire out_womask_819 = &_out_womask_T_819; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_819 = out_rivalid_1_673 & out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8064 = out_f_rivalid_819; // @[RegisterRouter.scala:87:24] wire out_f_roready_819 = out_roready_1_673 & out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8065 = out_f_roready_819; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_819 = out_wivalid_1_673 & out_wimask_819; // @[RegisterRouter.scala:87:24] wire out_f_woready_819 = out_woready_1_673 & out_womask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8066 = ~out_rimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8067 = ~out_wimask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8068 = ~out_romask_819; // @[RegisterRouter.scala:87:24] wire _out_T_8069 = ~out_womask_819; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8071 = _out_T_8070; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_698 = _out_T_8071; // @[RegisterRouter.scala:87:24] wire out_rimask_820 = |_out_rimask_T_820; // @[RegisterRouter.scala:87:24] wire out_wimask_820 = &_out_wimask_T_820; // @[RegisterRouter.scala:87:24] wire out_romask_820 = |_out_romask_T_820; // @[RegisterRouter.scala:87:24] wire out_womask_820 = &_out_womask_T_820; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_820 = out_rivalid_1_674 & out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8073 = out_f_rivalid_820; // @[RegisterRouter.scala:87:24] wire out_f_roready_820 = out_roready_1_674 & out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8074 = out_f_roready_820; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_820 = out_wivalid_1_674 & out_wimask_820; // @[RegisterRouter.scala:87:24] wire out_f_woready_820 = out_woready_1_674 & out_womask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8075 = ~out_rimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8076 = ~out_wimask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8077 = ~out_romask_820; // @[RegisterRouter.scala:87:24] wire _out_T_8078 = ~out_womask_820; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_698 = {hi_818, flags_0_go, _out_prepend_T_698}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8079 = out_prepend_698; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8080 = _out_T_8079; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_699 = _out_T_8080; // @[RegisterRouter.scala:87:24] wire out_rimask_821 = |_out_rimask_T_821; // @[RegisterRouter.scala:87:24] wire out_wimask_821 = &_out_wimask_T_821; // @[RegisterRouter.scala:87:24] wire out_romask_821 = |_out_romask_T_821; // @[RegisterRouter.scala:87:24] wire out_womask_821 = &_out_womask_T_821; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_821 = out_rivalid_1_675 & out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8082 = out_f_rivalid_821; // @[RegisterRouter.scala:87:24] wire out_f_roready_821 = out_roready_1_675 & out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8083 = out_f_roready_821; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_821 = out_wivalid_1_675 & out_wimask_821; // @[RegisterRouter.scala:87:24] wire out_f_woready_821 = out_woready_1_675 & out_womask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8084 = ~out_rimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8085 = ~out_wimask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8086 = ~out_romask_821; // @[RegisterRouter.scala:87:24] wire _out_T_8087 = ~out_womask_821; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_699 = {hi_819, flags_0_go, _out_prepend_T_699}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8088 = out_prepend_699; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8089 = _out_T_8088; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_700 = _out_T_8089; // @[RegisterRouter.scala:87:24] wire out_rimask_822 = |_out_rimask_T_822; // @[RegisterRouter.scala:87:24] wire out_wimask_822 = &_out_wimask_T_822; // @[RegisterRouter.scala:87:24] wire out_romask_822 = |_out_romask_T_822; // @[RegisterRouter.scala:87:24] wire out_womask_822 = &_out_womask_T_822; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_822 = out_rivalid_1_676 & out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8091 = out_f_rivalid_822; // @[RegisterRouter.scala:87:24] wire out_f_roready_822 = out_roready_1_676 & out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8092 = out_f_roready_822; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_822 = out_wivalid_1_676 & out_wimask_822; // @[RegisterRouter.scala:87:24] wire out_f_woready_822 = out_woready_1_676 & out_womask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8093 = ~out_rimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8094 = ~out_wimask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8095 = ~out_romask_822; // @[RegisterRouter.scala:87:24] wire _out_T_8096 = ~out_womask_822; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_700 = {hi_820, flags_0_go, _out_prepend_T_700}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8097 = out_prepend_700; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8098 = _out_T_8097; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_701 = _out_T_8098; // @[RegisterRouter.scala:87:24] wire out_rimask_823 = |_out_rimask_T_823; // @[RegisterRouter.scala:87:24] wire out_wimask_823 = &_out_wimask_T_823; // @[RegisterRouter.scala:87:24] wire out_romask_823 = |_out_romask_T_823; // @[RegisterRouter.scala:87:24] wire out_womask_823 = &_out_womask_T_823; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_823 = out_rivalid_1_677 & out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8100 = out_f_rivalid_823; // @[RegisterRouter.scala:87:24] wire out_f_roready_823 = out_roready_1_677 & out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8101 = out_f_roready_823; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_823 = out_wivalid_1_677 & out_wimask_823; // @[RegisterRouter.scala:87:24] wire out_f_woready_823 = out_woready_1_677 & out_womask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8102 = ~out_rimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8103 = ~out_wimask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8104 = ~out_romask_823; // @[RegisterRouter.scala:87:24] wire _out_T_8105 = ~out_womask_823; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_701 = {hi_821, flags_0_go, _out_prepend_T_701}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8106 = out_prepend_701; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8107 = _out_T_8106; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_702 = _out_T_8107; // @[RegisterRouter.scala:87:24] wire out_rimask_824 = |_out_rimask_T_824; // @[RegisterRouter.scala:87:24] wire out_wimask_824 = &_out_wimask_T_824; // @[RegisterRouter.scala:87:24] wire out_romask_824 = |_out_romask_T_824; // @[RegisterRouter.scala:87:24] wire out_womask_824 = &_out_womask_T_824; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_824 = out_rivalid_1_678 & out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8109 = out_f_rivalid_824; // @[RegisterRouter.scala:87:24] wire out_f_roready_824 = out_roready_1_678 & out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8110 = out_f_roready_824; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_824 = out_wivalid_1_678 & out_wimask_824; // @[RegisterRouter.scala:87:24] wire out_f_woready_824 = out_woready_1_678 & out_womask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8111 = ~out_rimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8112 = ~out_wimask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8113 = ~out_romask_824; // @[RegisterRouter.scala:87:24] wire _out_T_8114 = ~out_womask_824; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_702 = {hi_822, flags_0_go, _out_prepend_T_702}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8115 = out_prepend_702; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8116 = _out_T_8115; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_703 = _out_T_8116; // @[RegisterRouter.scala:87:24] wire out_rimask_825 = |_out_rimask_T_825; // @[RegisterRouter.scala:87:24] wire out_wimask_825 = &_out_wimask_T_825; // @[RegisterRouter.scala:87:24] wire out_romask_825 = |_out_romask_T_825; // @[RegisterRouter.scala:87:24] wire out_womask_825 = &_out_womask_T_825; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_825 = out_rivalid_1_679 & out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8118 = out_f_rivalid_825; // @[RegisterRouter.scala:87:24] wire out_f_roready_825 = out_roready_1_679 & out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8119 = out_f_roready_825; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_825 = out_wivalid_1_679 & out_wimask_825; // @[RegisterRouter.scala:87:24] wire out_f_woready_825 = out_woready_1_679 & out_womask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8120 = ~out_rimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8121 = ~out_wimask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8122 = ~out_romask_825; // @[RegisterRouter.scala:87:24] wire _out_T_8123 = ~out_womask_825; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_703 = {hi_823, flags_0_go, _out_prepend_T_703}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8124 = out_prepend_703; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8125 = _out_T_8124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_704 = _out_T_8125; // @[RegisterRouter.scala:87:24] wire out_rimask_826 = |_out_rimask_T_826; // @[RegisterRouter.scala:87:24] wire out_wimask_826 = &_out_wimask_T_826; // @[RegisterRouter.scala:87:24] wire out_romask_826 = |_out_romask_T_826; // @[RegisterRouter.scala:87:24] wire out_womask_826 = &_out_womask_T_826; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_826 = out_rivalid_1_680 & out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8127 = out_f_rivalid_826; // @[RegisterRouter.scala:87:24] wire out_f_roready_826 = out_roready_1_680 & out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8128 = out_f_roready_826; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_826 = out_wivalid_1_680 & out_wimask_826; // @[RegisterRouter.scala:87:24] wire out_f_woready_826 = out_woready_1_680 & out_womask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8129 = ~out_rimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8130 = ~out_wimask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8131 = ~out_romask_826; // @[RegisterRouter.scala:87:24] wire _out_T_8132 = ~out_womask_826; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_704 = {hi_824, flags_0_go, _out_prepend_T_704}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8133 = out_prepend_704; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8134 = _out_T_8133; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_230 = _out_T_8134; // @[MuxLiteral.scala:49:48] wire out_rimask_827 = |_out_rimask_T_827; // @[RegisterRouter.scala:87:24] wire out_wimask_827 = &_out_wimask_T_827; // @[RegisterRouter.scala:87:24] wire out_romask_827 = |_out_romask_T_827; // @[RegisterRouter.scala:87:24] wire out_womask_827 = &_out_womask_T_827; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_827 = out_rivalid_1_681 & out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8136 = out_f_rivalid_827; // @[RegisterRouter.scala:87:24] wire out_f_roready_827 = out_roready_1_681 & out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8137 = out_f_roready_827; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_827 = out_wivalid_1_681 & out_wimask_827; // @[RegisterRouter.scala:87:24] wire out_f_woready_827 = out_woready_1_681 & out_womask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8138 = ~out_rimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8139 = ~out_wimask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8140 = ~out_romask_827; // @[RegisterRouter.scala:87:24] wire _out_T_8141 = ~out_womask_827; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8143 = _out_T_8142; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_705 = _out_T_8143; // @[RegisterRouter.scala:87:24] wire out_rimask_828 = |_out_rimask_T_828; // @[RegisterRouter.scala:87:24] wire out_wimask_828 = &_out_wimask_T_828; // @[RegisterRouter.scala:87:24] wire out_romask_828 = |_out_romask_T_828; // @[RegisterRouter.scala:87:24] wire out_womask_828 = &_out_womask_T_828; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_828 = out_rivalid_1_682 & out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8145 = out_f_rivalid_828; // @[RegisterRouter.scala:87:24] wire out_f_roready_828 = out_roready_1_682 & out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8146 = out_f_roready_828; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_828 = out_wivalid_1_682 & out_wimask_828; // @[RegisterRouter.scala:87:24] wire out_f_woready_828 = out_woready_1_682 & out_womask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8147 = ~out_rimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8148 = ~out_wimask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8149 = ~out_romask_828; // @[RegisterRouter.scala:87:24] wire _out_T_8150 = ~out_womask_828; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_705 = {hi_938, flags_0_go, _out_prepend_T_705}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8151 = out_prepend_705; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8152 = _out_T_8151; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_706 = _out_T_8152; // @[RegisterRouter.scala:87:24] wire out_rimask_829 = |_out_rimask_T_829; // @[RegisterRouter.scala:87:24] wire out_wimask_829 = &_out_wimask_T_829; // @[RegisterRouter.scala:87:24] wire out_romask_829 = |_out_romask_T_829; // @[RegisterRouter.scala:87:24] wire out_womask_829 = &_out_womask_T_829; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_829 = out_rivalid_1_683 & out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8154 = out_f_rivalid_829; // @[RegisterRouter.scala:87:24] wire out_f_roready_829 = out_roready_1_683 & out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8155 = out_f_roready_829; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_829 = out_wivalid_1_683 & out_wimask_829; // @[RegisterRouter.scala:87:24] wire out_f_woready_829 = out_woready_1_683 & out_womask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8156 = ~out_rimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8157 = ~out_wimask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8158 = ~out_romask_829; // @[RegisterRouter.scala:87:24] wire _out_T_8159 = ~out_womask_829; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_706 = {hi_939, flags_0_go, _out_prepend_T_706}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8160 = out_prepend_706; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8161 = _out_T_8160; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_707 = _out_T_8161; // @[RegisterRouter.scala:87:24] wire out_rimask_830 = |_out_rimask_T_830; // @[RegisterRouter.scala:87:24] wire out_wimask_830 = &_out_wimask_T_830; // @[RegisterRouter.scala:87:24] wire out_romask_830 = |_out_romask_T_830; // @[RegisterRouter.scala:87:24] wire out_womask_830 = &_out_womask_T_830; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_830 = out_rivalid_1_684 & out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8163 = out_f_rivalid_830; // @[RegisterRouter.scala:87:24] wire out_f_roready_830 = out_roready_1_684 & out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8164 = out_f_roready_830; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_830 = out_wivalid_1_684 & out_wimask_830; // @[RegisterRouter.scala:87:24] wire out_f_woready_830 = out_woready_1_684 & out_womask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8165 = ~out_rimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8166 = ~out_wimask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8167 = ~out_romask_830; // @[RegisterRouter.scala:87:24] wire _out_T_8168 = ~out_womask_830; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_707 = {hi_940, flags_0_go, _out_prepend_T_707}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8169 = out_prepend_707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8170 = _out_T_8169; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_708 = _out_T_8170; // @[RegisterRouter.scala:87:24] wire out_rimask_831 = |_out_rimask_T_831; // @[RegisterRouter.scala:87:24] wire out_wimask_831 = &_out_wimask_T_831; // @[RegisterRouter.scala:87:24] wire out_romask_831 = |_out_romask_T_831; // @[RegisterRouter.scala:87:24] wire out_womask_831 = &_out_womask_T_831; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_831 = out_rivalid_1_685 & out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8172 = out_f_rivalid_831; // @[RegisterRouter.scala:87:24] wire out_f_roready_831 = out_roready_1_685 & out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8173 = out_f_roready_831; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_831 = out_wivalid_1_685 & out_wimask_831; // @[RegisterRouter.scala:87:24] wire out_f_woready_831 = out_woready_1_685 & out_womask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8174 = ~out_rimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8175 = ~out_wimask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8176 = ~out_romask_831; // @[RegisterRouter.scala:87:24] wire _out_T_8177 = ~out_womask_831; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_708 = {hi_941, flags_0_go, _out_prepend_T_708}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8178 = out_prepend_708; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8179 = _out_T_8178; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_709 = _out_T_8179; // @[RegisterRouter.scala:87:24] wire out_rimask_832 = |_out_rimask_T_832; // @[RegisterRouter.scala:87:24] wire out_wimask_832 = &_out_wimask_T_832; // @[RegisterRouter.scala:87:24] wire out_romask_832 = |_out_romask_T_832; // @[RegisterRouter.scala:87:24] wire out_womask_832 = &_out_womask_T_832; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_832 = out_rivalid_1_686 & out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8181 = out_f_rivalid_832; // @[RegisterRouter.scala:87:24] wire out_f_roready_832 = out_roready_1_686 & out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8182 = out_f_roready_832; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_832 = out_wivalid_1_686 & out_wimask_832; // @[RegisterRouter.scala:87:24] wire out_f_woready_832 = out_woready_1_686 & out_womask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8183 = ~out_rimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8184 = ~out_wimask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8185 = ~out_romask_832; // @[RegisterRouter.scala:87:24] wire _out_T_8186 = ~out_womask_832; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_709 = {hi_942, flags_0_go, _out_prepend_T_709}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8187 = out_prepend_709; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8188 = _out_T_8187; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_710 = _out_T_8188; // @[RegisterRouter.scala:87:24] wire out_rimask_833 = |_out_rimask_T_833; // @[RegisterRouter.scala:87:24] wire out_wimask_833 = &_out_wimask_T_833; // @[RegisterRouter.scala:87:24] wire out_romask_833 = |_out_romask_T_833; // @[RegisterRouter.scala:87:24] wire out_womask_833 = &_out_womask_T_833; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_833 = out_rivalid_1_687 & out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8190 = out_f_rivalid_833; // @[RegisterRouter.scala:87:24] wire out_f_roready_833 = out_roready_1_687 & out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8191 = out_f_roready_833; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_833 = out_wivalid_1_687 & out_wimask_833; // @[RegisterRouter.scala:87:24] wire out_f_woready_833 = out_woready_1_687 & out_womask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8192 = ~out_rimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8193 = ~out_wimask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8194 = ~out_romask_833; // @[RegisterRouter.scala:87:24] wire _out_T_8195 = ~out_womask_833; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_710 = {hi_943, flags_0_go, _out_prepend_T_710}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8196 = out_prepend_710; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8197 = _out_T_8196; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_711 = _out_T_8197; // @[RegisterRouter.scala:87:24] wire out_rimask_834 = |_out_rimask_T_834; // @[RegisterRouter.scala:87:24] wire out_wimask_834 = &_out_wimask_T_834; // @[RegisterRouter.scala:87:24] wire out_romask_834 = |_out_romask_T_834; // @[RegisterRouter.scala:87:24] wire out_womask_834 = &_out_womask_T_834; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_834 = out_rivalid_1_688 & out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8199 = out_f_rivalid_834; // @[RegisterRouter.scala:87:24] wire out_f_roready_834 = out_roready_1_688 & out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8200 = out_f_roready_834; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_834 = out_wivalid_1_688 & out_wimask_834; // @[RegisterRouter.scala:87:24] wire out_f_woready_834 = out_woready_1_688 & out_womask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8201 = ~out_rimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8202 = ~out_wimask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8203 = ~out_romask_834; // @[RegisterRouter.scala:87:24] wire _out_T_8204 = ~out_womask_834; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_711 = {hi_944, flags_0_go, _out_prepend_T_711}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8205 = out_prepend_711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8206 = _out_T_8205; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_245 = _out_T_8206; // @[MuxLiteral.scala:49:48] wire out_rimask_835 = |_out_rimask_T_835; // @[RegisterRouter.scala:87:24] wire out_wimask_835 = &_out_wimask_T_835; // @[RegisterRouter.scala:87:24] wire out_romask_835 = |_out_romask_T_835; // @[RegisterRouter.scala:87:24] wire out_womask_835 = &_out_womask_T_835; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_835 = out_rivalid_1_689 & out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8208 = out_f_rivalid_835; // @[RegisterRouter.scala:87:24] wire out_f_roready_835 = out_roready_1_689 & out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8209 = out_f_roready_835; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_835 = out_wivalid_1_689 & out_wimask_835; // @[RegisterRouter.scala:87:24] wire out_f_woready_835 = out_woready_1_689 & out_womask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8210 = ~out_rimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8211 = ~out_wimask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8212 = ~out_romask_835; // @[RegisterRouter.scala:87:24] wire _out_T_8213 = ~out_womask_835; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8215 = _out_T_8214; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_712 = _out_T_8215; // @[RegisterRouter.scala:87:24] wire out_rimask_836 = |_out_rimask_T_836; // @[RegisterRouter.scala:87:24] wire out_wimask_836 = &_out_wimask_T_836; // @[RegisterRouter.scala:87:24] wire out_romask_836 = |_out_romask_T_836; // @[RegisterRouter.scala:87:24] wire out_womask_836 = &_out_womask_T_836; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_836 = out_rivalid_1_690 & out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8217 = out_f_rivalid_836; // @[RegisterRouter.scala:87:24] wire out_f_roready_836 = out_roready_1_690 & out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8218 = out_f_roready_836; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_836 = out_wivalid_1_690 & out_wimask_836; // @[RegisterRouter.scala:87:24] wire out_f_woready_836 = out_woready_1_690 & out_womask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8219 = ~out_rimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8220 = ~out_wimask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8221 = ~out_romask_836; // @[RegisterRouter.scala:87:24] wire _out_T_8222 = ~out_womask_836; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_712 = {hi_642, flags_0_go, _out_prepend_T_712}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8223 = out_prepend_712; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8224 = _out_T_8223; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_713 = _out_T_8224; // @[RegisterRouter.scala:87:24] wire out_rimask_837 = |_out_rimask_T_837; // @[RegisterRouter.scala:87:24] wire out_wimask_837 = &_out_wimask_T_837; // @[RegisterRouter.scala:87:24] wire out_romask_837 = |_out_romask_T_837; // @[RegisterRouter.scala:87:24] wire out_womask_837 = &_out_womask_T_837; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_837 = out_rivalid_1_691 & out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8226 = out_f_rivalid_837; // @[RegisterRouter.scala:87:24] wire out_f_roready_837 = out_roready_1_691 & out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8227 = out_f_roready_837; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_837 = out_wivalid_1_691 & out_wimask_837; // @[RegisterRouter.scala:87:24] wire out_f_woready_837 = out_woready_1_691 & out_womask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8228 = ~out_rimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8229 = ~out_wimask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8230 = ~out_romask_837; // @[RegisterRouter.scala:87:24] wire _out_T_8231 = ~out_womask_837; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_713 = {hi_643, flags_0_go, _out_prepend_T_713}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8232 = out_prepend_713; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8233 = _out_T_8232; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_714 = _out_T_8233; // @[RegisterRouter.scala:87:24] wire out_rimask_838 = |_out_rimask_T_838; // @[RegisterRouter.scala:87:24] wire out_wimask_838 = &_out_wimask_T_838; // @[RegisterRouter.scala:87:24] wire out_romask_838 = |_out_romask_T_838; // @[RegisterRouter.scala:87:24] wire out_womask_838 = &_out_womask_T_838; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_838 = out_rivalid_1_692 & out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8235 = out_f_rivalid_838; // @[RegisterRouter.scala:87:24] wire out_f_roready_838 = out_roready_1_692 & out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8236 = out_f_roready_838; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_838 = out_wivalid_1_692 & out_wimask_838; // @[RegisterRouter.scala:87:24] wire out_f_woready_838 = out_woready_1_692 & out_womask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8237 = ~out_rimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8238 = ~out_wimask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8239 = ~out_romask_838; // @[RegisterRouter.scala:87:24] wire _out_T_8240 = ~out_womask_838; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_714 = {hi_644, flags_0_go, _out_prepend_T_714}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8241 = out_prepend_714; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8242 = _out_T_8241; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_715 = _out_T_8242; // @[RegisterRouter.scala:87:24] wire out_rimask_839 = |_out_rimask_T_839; // @[RegisterRouter.scala:87:24] wire out_wimask_839 = &_out_wimask_T_839; // @[RegisterRouter.scala:87:24] wire out_romask_839 = |_out_romask_T_839; // @[RegisterRouter.scala:87:24] wire out_womask_839 = &_out_womask_T_839; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_839 = out_rivalid_1_693 & out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8244 = out_f_rivalid_839; // @[RegisterRouter.scala:87:24] wire out_f_roready_839 = out_roready_1_693 & out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8245 = out_f_roready_839; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_839 = out_wivalid_1_693 & out_wimask_839; // @[RegisterRouter.scala:87:24] wire out_f_woready_839 = out_woready_1_693 & out_womask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8246 = ~out_rimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8247 = ~out_wimask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8248 = ~out_romask_839; // @[RegisterRouter.scala:87:24] wire _out_T_8249 = ~out_womask_839; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_715 = {hi_645, flags_0_go, _out_prepend_T_715}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8250 = out_prepend_715; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8251 = _out_T_8250; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_716 = _out_T_8251; // @[RegisterRouter.scala:87:24] wire out_rimask_840 = |_out_rimask_T_840; // @[RegisterRouter.scala:87:24] wire out_wimask_840 = &_out_wimask_T_840; // @[RegisterRouter.scala:87:24] wire out_romask_840 = |_out_romask_T_840; // @[RegisterRouter.scala:87:24] wire out_womask_840 = &_out_womask_T_840; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_840 = out_rivalid_1_694 & out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8253 = out_f_rivalid_840; // @[RegisterRouter.scala:87:24] wire out_f_roready_840 = out_roready_1_694 & out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8254 = out_f_roready_840; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_840 = out_wivalid_1_694 & out_wimask_840; // @[RegisterRouter.scala:87:24] wire out_f_woready_840 = out_woready_1_694 & out_womask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8255 = ~out_rimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8256 = ~out_wimask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8257 = ~out_romask_840; // @[RegisterRouter.scala:87:24] wire _out_T_8258 = ~out_womask_840; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_716 = {hi_646, flags_0_go, _out_prepend_T_716}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8259 = out_prepend_716; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8260 = _out_T_8259; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_717 = _out_T_8260; // @[RegisterRouter.scala:87:24] wire out_rimask_841 = |_out_rimask_T_841; // @[RegisterRouter.scala:87:24] wire out_wimask_841 = &_out_wimask_T_841; // @[RegisterRouter.scala:87:24] wire out_romask_841 = |_out_romask_T_841; // @[RegisterRouter.scala:87:24] wire out_womask_841 = &_out_womask_T_841; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_841 = out_rivalid_1_695 & out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8262 = out_f_rivalid_841; // @[RegisterRouter.scala:87:24] wire out_f_roready_841 = out_roready_1_695 & out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8263 = out_f_roready_841; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_841 = out_wivalid_1_695 & out_wimask_841; // @[RegisterRouter.scala:87:24] wire out_f_woready_841 = out_woready_1_695 & out_womask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8264 = ~out_rimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8265 = ~out_wimask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8266 = ~out_romask_841; // @[RegisterRouter.scala:87:24] wire _out_T_8267 = ~out_womask_841; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_717 = {hi_647, flags_0_go, _out_prepend_T_717}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8268 = out_prepend_717; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8269 = _out_T_8268; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_718 = _out_T_8269; // @[RegisterRouter.scala:87:24] wire out_rimask_842 = |_out_rimask_T_842; // @[RegisterRouter.scala:87:24] wire out_wimask_842 = &_out_wimask_T_842; // @[RegisterRouter.scala:87:24] wire out_romask_842 = |_out_romask_T_842; // @[RegisterRouter.scala:87:24] wire out_womask_842 = &_out_womask_T_842; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_842 = out_rivalid_1_696 & out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8271 = out_f_rivalid_842; // @[RegisterRouter.scala:87:24] wire out_f_roready_842 = out_roready_1_696 & out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8272 = out_f_roready_842; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_842 = out_wivalid_1_696 & out_wimask_842; // @[RegisterRouter.scala:87:24] wire out_f_woready_842 = out_woready_1_696 & out_womask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8273 = ~out_rimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8274 = ~out_wimask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8275 = ~out_romask_842; // @[RegisterRouter.scala:87:24] wire _out_T_8276 = ~out_womask_842; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_718 = {hi_648, flags_0_go, _out_prepend_T_718}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8277 = out_prepend_718; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8278 = _out_T_8277; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_208 = _out_T_8278; // @[MuxLiteral.scala:49:48] wire out_rimask_843 = |_out_rimask_T_843; // @[RegisterRouter.scala:87:24] wire out_wimask_843 = &_out_wimask_T_843; // @[RegisterRouter.scala:87:24] wire out_romask_843 = |_out_romask_T_843; // @[RegisterRouter.scala:87:24] wire out_womask_843 = &_out_womask_T_843; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_843 = out_rivalid_1_697 & out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8280 = out_f_rivalid_843; // @[RegisterRouter.scala:87:24] wire out_f_roready_843 = out_roready_1_697 & out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8281 = out_f_roready_843; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_843 = out_wivalid_1_697 & out_wimask_843; // @[RegisterRouter.scala:87:24] wire out_f_woready_843 = out_woready_1_697 & out_womask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8282 = ~out_rimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8283 = ~out_wimask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8284 = ~out_romask_843; // @[RegisterRouter.scala:87:24] wire _out_T_8285 = ~out_womask_843; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8287 = _out_T_8286; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_719 = _out_T_8287; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_844 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_844 = |_out_rimask_T_844; // @[RegisterRouter.scala:87:24] wire out_wimask_844 = &_out_wimask_T_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_844 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_844 = |_out_romask_T_844; // @[RegisterRouter.scala:87:24] wire out_womask_844 = &_out_womask_T_844; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_844 = out_rivalid_1_698 & out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8289 = out_f_rivalid_844; // @[RegisterRouter.scala:87:24] wire out_f_roready_844 = out_roready_1_698 & out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8290 = out_f_roready_844; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_844 = out_wivalid_1_698 & out_wimask_844; // @[RegisterRouter.scala:87:24] wire out_f_woready_844 = out_woready_1_698 & out_womask_844; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8288 = out_front_1_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_8291 = ~out_rimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8292 = ~out_wimask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8293 = ~out_romask_844; // @[RegisterRouter.scala:87:24] wire _out_T_8294 = ~out_womask_844; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_719 = {abstractGeneratedMem_1, _out_prepend_T_719}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8295 = out_prepend_719; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8296 = _out_T_8295; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_103 = _out_T_8296; // @[MuxLiteral.scala:49:48] wire out_rimask_845 = |_out_rimask_T_845; // @[RegisterRouter.scala:87:24] wire out_wimask_845 = &_out_wimask_T_845; // @[RegisterRouter.scala:87:24] wire out_romask_845 = |_out_romask_T_845; // @[RegisterRouter.scala:87:24] wire out_womask_845 = &_out_womask_T_845; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_845 = out_rivalid_1_699 & out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8298 = out_f_rivalid_845; // @[RegisterRouter.scala:87:24] wire out_f_roready_845 = out_roready_1_699 & out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8299 = out_f_roready_845; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_845 = out_wivalid_1_699 & out_wimask_845; // @[RegisterRouter.scala:87:24] wire out_f_woready_845 = out_woready_1_699 & out_womask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8300 = ~out_rimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8301 = ~out_wimask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8302 = ~out_romask_845; // @[RegisterRouter.scala:87:24] wire _out_T_8303 = ~out_womask_845; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8305 = _out_T_8304; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_720 = _out_T_8305; // @[RegisterRouter.scala:87:24] wire out_rimask_846 = |_out_rimask_T_846; // @[RegisterRouter.scala:87:24] wire out_wimask_846 = &_out_wimask_T_846; // @[RegisterRouter.scala:87:24] wire out_romask_846 = |_out_romask_T_846; // @[RegisterRouter.scala:87:24] wire out_womask_846 = &_out_womask_T_846; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_846 = out_rivalid_1_700 & out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8307 = out_f_rivalid_846; // @[RegisterRouter.scala:87:24] wire out_f_roready_846 = out_roready_1_700 & out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8308 = out_f_roready_846; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_846 = out_wivalid_1_700 & out_wimask_846; // @[RegisterRouter.scala:87:24] wire out_f_woready_846 = out_woready_1_700 & out_womask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8309 = ~out_rimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8310 = ~out_wimask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8311 = ~out_romask_846; // @[RegisterRouter.scala:87:24] wire _out_T_8312 = ~out_womask_846; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_720 = {hi_98, flags_0_go, _out_prepend_T_720}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8313 = out_prepend_720; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8314 = _out_T_8313; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_721 = _out_T_8314; // @[RegisterRouter.scala:87:24] wire out_rimask_847 = |_out_rimask_T_847; // @[RegisterRouter.scala:87:24] wire out_wimask_847 = &_out_wimask_T_847; // @[RegisterRouter.scala:87:24] wire out_romask_847 = |_out_romask_T_847; // @[RegisterRouter.scala:87:24] wire out_womask_847 = &_out_womask_T_847; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_847 = out_rivalid_1_701 & out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8316 = out_f_rivalid_847; // @[RegisterRouter.scala:87:24] wire out_f_roready_847 = out_roready_1_701 & out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8317 = out_f_roready_847; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_847 = out_wivalid_1_701 & out_wimask_847; // @[RegisterRouter.scala:87:24] wire out_f_woready_847 = out_woready_1_701 & out_womask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8318 = ~out_rimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8319 = ~out_wimask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8320 = ~out_romask_847; // @[RegisterRouter.scala:87:24] wire _out_T_8321 = ~out_womask_847; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_721 = {hi_99, flags_0_go, _out_prepend_T_721}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8322 = out_prepend_721; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8323 = _out_T_8322; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_722 = _out_T_8323; // @[RegisterRouter.scala:87:24] wire out_rimask_848 = |_out_rimask_T_848; // @[RegisterRouter.scala:87:24] wire out_wimask_848 = &_out_wimask_T_848; // @[RegisterRouter.scala:87:24] wire out_romask_848 = |_out_romask_T_848; // @[RegisterRouter.scala:87:24] wire out_womask_848 = &_out_womask_T_848; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_848 = out_rivalid_1_702 & out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8325 = out_f_rivalid_848; // @[RegisterRouter.scala:87:24] wire out_f_roready_848 = out_roready_1_702 & out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8326 = out_f_roready_848; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_848 = out_wivalid_1_702 & out_wimask_848; // @[RegisterRouter.scala:87:24] wire out_f_woready_848 = out_woready_1_702 & out_womask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8327 = ~out_rimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8328 = ~out_wimask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8329 = ~out_romask_848; // @[RegisterRouter.scala:87:24] wire _out_T_8330 = ~out_womask_848; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_722 = {hi_100, flags_0_go, _out_prepend_T_722}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8331 = out_prepend_722; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8332 = _out_T_8331; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_723 = _out_T_8332; // @[RegisterRouter.scala:87:24] wire out_rimask_849 = |_out_rimask_T_849; // @[RegisterRouter.scala:87:24] wire out_wimask_849 = &_out_wimask_T_849; // @[RegisterRouter.scala:87:24] wire out_romask_849 = |_out_romask_T_849; // @[RegisterRouter.scala:87:24] wire out_womask_849 = &_out_womask_T_849; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_849 = out_rivalid_1_703 & out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8334 = out_f_rivalid_849; // @[RegisterRouter.scala:87:24] wire out_f_roready_849 = out_roready_1_703 & out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8335 = out_f_roready_849; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_849 = out_wivalid_1_703 & out_wimask_849; // @[RegisterRouter.scala:87:24] wire out_f_woready_849 = out_woready_1_703 & out_womask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8336 = ~out_rimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8337 = ~out_wimask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8338 = ~out_romask_849; // @[RegisterRouter.scala:87:24] wire _out_T_8339 = ~out_womask_849; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_723 = {hi_101, flags_0_go, _out_prepend_T_723}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8340 = out_prepend_723; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8341 = _out_T_8340; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_724 = _out_T_8341; // @[RegisterRouter.scala:87:24] wire out_rimask_850 = |_out_rimask_T_850; // @[RegisterRouter.scala:87:24] wire out_wimask_850 = &_out_wimask_T_850; // @[RegisterRouter.scala:87:24] wire out_romask_850 = |_out_romask_T_850; // @[RegisterRouter.scala:87:24] wire out_womask_850 = &_out_womask_T_850; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_850 = out_rivalid_1_704 & out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8343 = out_f_rivalid_850; // @[RegisterRouter.scala:87:24] wire out_f_roready_850 = out_roready_1_704 & out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8344 = out_f_roready_850; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_850 = out_wivalid_1_704 & out_wimask_850; // @[RegisterRouter.scala:87:24] wire out_f_woready_850 = out_woready_1_704 & out_womask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8345 = ~out_rimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8346 = ~out_wimask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8347 = ~out_romask_850; // @[RegisterRouter.scala:87:24] wire _out_T_8348 = ~out_womask_850; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_724 = {hi_102, flags_0_go, _out_prepend_T_724}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8349 = out_prepend_724; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8350 = _out_T_8349; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_725 = _out_T_8350; // @[RegisterRouter.scala:87:24] wire out_rimask_851 = |_out_rimask_T_851; // @[RegisterRouter.scala:87:24] wire out_wimask_851 = &_out_wimask_T_851; // @[RegisterRouter.scala:87:24] wire out_romask_851 = |_out_romask_T_851; // @[RegisterRouter.scala:87:24] wire out_womask_851 = &_out_womask_T_851; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_851 = out_rivalid_1_705 & out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8352 = out_f_rivalid_851; // @[RegisterRouter.scala:87:24] wire out_f_roready_851 = out_roready_1_705 & out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8353 = out_f_roready_851; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_851 = out_wivalid_1_705 & out_wimask_851; // @[RegisterRouter.scala:87:24] wire out_f_woready_851 = out_woready_1_705 & out_womask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8354 = ~out_rimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8355 = ~out_wimask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8356 = ~out_romask_851; // @[RegisterRouter.scala:87:24] wire _out_T_8357 = ~out_womask_851; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_725 = {hi_103, flags_0_go, _out_prepend_T_725}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8358 = out_prepend_725; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8359 = _out_T_8358; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_726 = _out_T_8359; // @[RegisterRouter.scala:87:24] wire out_rimask_852 = |_out_rimask_T_852; // @[RegisterRouter.scala:87:24] wire out_wimask_852 = &_out_wimask_T_852; // @[RegisterRouter.scala:87:24] wire out_romask_852 = |_out_romask_T_852; // @[RegisterRouter.scala:87:24] wire out_womask_852 = &_out_womask_T_852; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_852 = out_rivalid_1_706 & out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8361 = out_f_rivalid_852; // @[RegisterRouter.scala:87:24] wire out_f_roready_852 = out_roready_1_706 & out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8362 = out_f_roready_852; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_852 = out_wivalid_1_706 & out_wimask_852; // @[RegisterRouter.scala:87:24] wire out_f_woready_852 = out_woready_1_706 & out_womask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8363 = ~out_rimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8364 = ~out_wimask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8365 = ~out_romask_852; // @[RegisterRouter.scala:87:24] wire _out_T_8366 = ~out_womask_852; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_726 = {hi_104, flags_0_go, _out_prepend_T_726}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8367 = out_prepend_726; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8368 = _out_T_8367; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_140 = _out_T_8368; // @[MuxLiteral.scala:49:48] wire out_rimask_853 = |_out_rimask_T_853; // @[RegisterRouter.scala:87:24] wire out_wimask_853 = &_out_wimask_T_853; // @[RegisterRouter.scala:87:24] wire out_romask_853 = |_out_romask_T_853; // @[RegisterRouter.scala:87:24] wire out_womask_853 = &_out_womask_T_853; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_853 = out_rivalid_1_707 & out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8370 = out_f_rivalid_853; // @[RegisterRouter.scala:87:24] wire out_f_roready_853 = out_roready_1_707 & out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8371 = out_f_roready_853; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_853 = out_wivalid_1_707 & out_wimask_853; // @[RegisterRouter.scala:87:24] wire out_f_woready_853 = out_woready_1_707 & out_womask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8372 = ~out_rimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8373 = ~out_wimask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8374 = ~out_romask_853; // @[RegisterRouter.scala:87:24] wire _out_T_8375 = ~out_womask_853; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8377 = _out_T_8376; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_727 = _out_T_8377; // @[RegisterRouter.scala:87:24] wire out_rimask_854 = |_out_rimask_T_854; // @[RegisterRouter.scala:87:24] wire out_wimask_854 = &_out_wimask_T_854; // @[RegisterRouter.scala:87:24] wire out_romask_854 = |_out_romask_T_854; // @[RegisterRouter.scala:87:24] wire out_womask_854 = &_out_womask_T_854; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_854 = out_rivalid_1_708 & out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8379 = out_f_rivalid_854; // @[RegisterRouter.scala:87:24] wire out_f_roready_854 = out_roready_1_708 & out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8380 = out_f_roready_854; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_854 = out_wivalid_1_708 & out_wimask_854; // @[RegisterRouter.scala:87:24] wire out_f_woready_854 = out_woready_1_708 & out_womask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8381 = ~out_rimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8382 = ~out_wimask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8383 = ~out_romask_854; // @[RegisterRouter.scala:87:24] wire _out_T_8384 = ~out_womask_854; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_727 = {hi_682, flags_0_go, _out_prepend_T_727}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8385 = out_prepend_727; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8386 = _out_T_8385; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_728 = _out_T_8386; // @[RegisterRouter.scala:87:24] wire out_rimask_855 = |_out_rimask_T_855; // @[RegisterRouter.scala:87:24] wire out_wimask_855 = &_out_wimask_T_855; // @[RegisterRouter.scala:87:24] wire out_romask_855 = |_out_romask_T_855; // @[RegisterRouter.scala:87:24] wire out_womask_855 = &_out_womask_T_855; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_855 = out_rivalid_1_709 & out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8388 = out_f_rivalid_855; // @[RegisterRouter.scala:87:24] wire out_f_roready_855 = out_roready_1_709 & out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8389 = out_f_roready_855; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_855 = out_wivalid_1_709 & out_wimask_855; // @[RegisterRouter.scala:87:24] wire out_f_woready_855 = out_woready_1_709 & out_womask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8390 = ~out_rimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8391 = ~out_wimask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8392 = ~out_romask_855; // @[RegisterRouter.scala:87:24] wire _out_T_8393 = ~out_womask_855; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_728 = {hi_683, flags_0_go, _out_prepend_T_728}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8394 = out_prepend_728; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8395 = _out_T_8394; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_729 = _out_T_8395; // @[RegisterRouter.scala:87:24] wire out_rimask_856 = |_out_rimask_T_856; // @[RegisterRouter.scala:87:24] wire out_wimask_856 = &_out_wimask_T_856; // @[RegisterRouter.scala:87:24] wire out_romask_856 = |_out_romask_T_856; // @[RegisterRouter.scala:87:24] wire out_womask_856 = &_out_womask_T_856; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_856 = out_rivalid_1_710 & out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8397 = out_f_rivalid_856; // @[RegisterRouter.scala:87:24] wire out_f_roready_856 = out_roready_1_710 & out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8398 = out_f_roready_856; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_856 = out_wivalid_1_710 & out_wimask_856; // @[RegisterRouter.scala:87:24] wire out_f_woready_856 = out_woready_1_710 & out_womask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8399 = ~out_rimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8400 = ~out_wimask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8401 = ~out_romask_856; // @[RegisterRouter.scala:87:24] wire _out_T_8402 = ~out_womask_856; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_729 = {hi_684, flags_0_go, _out_prepend_T_729}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8403 = out_prepend_729; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8404 = _out_T_8403; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_730 = _out_T_8404; // @[RegisterRouter.scala:87:24] wire out_rimask_857 = |_out_rimask_T_857; // @[RegisterRouter.scala:87:24] wire out_wimask_857 = &_out_wimask_T_857; // @[RegisterRouter.scala:87:24] wire out_romask_857 = |_out_romask_T_857; // @[RegisterRouter.scala:87:24] wire out_womask_857 = &_out_womask_T_857; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_857 = out_rivalid_1_711 & out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8406 = out_f_rivalid_857; // @[RegisterRouter.scala:87:24] wire out_f_roready_857 = out_roready_1_711 & out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8407 = out_f_roready_857; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_857 = out_wivalid_1_711 & out_wimask_857; // @[RegisterRouter.scala:87:24] wire out_f_woready_857 = out_woready_1_711 & out_womask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8408 = ~out_rimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8409 = ~out_wimask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8410 = ~out_romask_857; // @[RegisterRouter.scala:87:24] wire _out_T_8411 = ~out_womask_857; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_730 = {hi_685, flags_0_go, _out_prepend_T_730}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8412 = out_prepend_730; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8413 = _out_T_8412; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_731 = _out_T_8413; // @[RegisterRouter.scala:87:24] wire out_rimask_858 = |_out_rimask_T_858; // @[RegisterRouter.scala:87:24] wire out_wimask_858 = &_out_wimask_T_858; // @[RegisterRouter.scala:87:24] wire out_romask_858 = |_out_romask_T_858; // @[RegisterRouter.scala:87:24] wire out_womask_858 = &_out_womask_T_858; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_858 = out_rivalid_1_712 & out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8415 = out_f_rivalid_858; // @[RegisterRouter.scala:87:24] wire out_f_roready_858 = out_roready_1_712 & out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8416 = out_f_roready_858; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_858 = out_wivalid_1_712 & out_wimask_858; // @[RegisterRouter.scala:87:24] wire out_f_woready_858 = out_woready_1_712 & out_womask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8417 = ~out_rimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8418 = ~out_wimask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8419 = ~out_romask_858; // @[RegisterRouter.scala:87:24] wire _out_T_8420 = ~out_womask_858; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_731 = {hi_686, flags_0_go, _out_prepend_T_731}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8421 = out_prepend_731; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8422 = _out_T_8421; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_732 = _out_T_8422; // @[RegisterRouter.scala:87:24] wire out_rimask_859 = |_out_rimask_T_859; // @[RegisterRouter.scala:87:24] wire out_wimask_859 = &_out_wimask_T_859; // @[RegisterRouter.scala:87:24] wire out_romask_859 = |_out_romask_T_859; // @[RegisterRouter.scala:87:24] wire out_womask_859 = &_out_womask_T_859; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_859 = out_rivalid_1_713 & out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8424 = out_f_rivalid_859; // @[RegisterRouter.scala:87:24] wire out_f_roready_859 = out_roready_1_713 & out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8425 = out_f_roready_859; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_859 = out_wivalid_1_713 & out_wimask_859; // @[RegisterRouter.scala:87:24] wire out_f_woready_859 = out_woready_1_713 & out_womask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8426 = ~out_rimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8427 = ~out_wimask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8428 = ~out_romask_859; // @[RegisterRouter.scala:87:24] wire _out_T_8429 = ~out_womask_859; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_732 = {hi_687, flags_0_go, _out_prepend_T_732}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8430 = out_prepend_732; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8431 = _out_T_8430; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_733 = _out_T_8431; // @[RegisterRouter.scala:87:24] wire out_rimask_860 = |_out_rimask_T_860; // @[RegisterRouter.scala:87:24] wire out_wimask_860 = &_out_wimask_T_860; // @[RegisterRouter.scala:87:24] wire out_romask_860 = |_out_romask_T_860; // @[RegisterRouter.scala:87:24] wire out_womask_860 = &_out_womask_T_860; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_860 = out_rivalid_1_714 & out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8433 = out_f_rivalid_860; // @[RegisterRouter.scala:87:24] wire out_f_roready_860 = out_roready_1_714 & out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8434 = out_f_roready_860; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_860 = out_wivalid_1_714 & out_wimask_860; // @[RegisterRouter.scala:87:24] wire out_f_woready_860 = out_woready_1_714 & out_womask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8435 = ~out_rimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8436 = ~out_wimask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8437 = ~out_romask_860; // @[RegisterRouter.scala:87:24] wire _out_T_8438 = ~out_womask_860; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_733 = {hi_688, flags_0_go, _out_prepend_T_733}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8439 = out_prepend_733; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8440 = _out_T_8439; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_213 = _out_T_8440; // @[MuxLiteral.scala:49:48] wire out_rimask_861 = |_out_rimask_T_861; // @[RegisterRouter.scala:87:24] wire out_wimask_861 = &_out_wimask_T_861; // @[RegisterRouter.scala:87:24] wire out_romask_861 = |_out_romask_T_861; // @[RegisterRouter.scala:87:24] wire out_womask_861 = &_out_womask_T_861; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_861 = out_rivalid_1_715 & out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8442 = out_f_rivalid_861; // @[RegisterRouter.scala:87:24] wire out_f_roready_861 = out_roready_1_715 & out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8443 = out_f_roready_861; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_861 = out_wivalid_1_715 & out_wimask_861; // @[RegisterRouter.scala:87:24] wire out_f_woready_861 = out_woready_1_715 & out_womask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8444 = ~out_rimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8445 = ~out_wimask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8446 = ~out_romask_861; // @[RegisterRouter.scala:87:24] wire _out_T_8447 = ~out_womask_861; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8449 = _out_T_8448; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_734 = _out_T_8449; // @[RegisterRouter.scala:87:24] wire out_rimask_862 = |_out_rimask_T_862; // @[RegisterRouter.scala:87:24] wire out_wimask_862 = &_out_wimask_T_862; // @[RegisterRouter.scala:87:24] wire out_romask_862 = |_out_romask_T_862; // @[RegisterRouter.scala:87:24] wire out_womask_862 = &_out_womask_T_862; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_862 = out_rivalid_1_716 & out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8451 = out_f_rivalid_862; // @[RegisterRouter.scala:87:24] wire out_f_roready_862 = out_roready_1_716 & out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8452 = out_f_roready_862; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_862 = out_wivalid_1_716 & out_wimask_862; // @[RegisterRouter.scala:87:24] wire out_f_woready_862 = out_woready_1_716 & out_womask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8453 = ~out_rimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8454 = ~out_wimask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8455 = ~out_romask_862; // @[RegisterRouter.scala:87:24] wire _out_T_8456 = ~out_womask_862; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_734 = {hi_218, flags_0_go, _out_prepend_T_734}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8457 = out_prepend_734; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8458 = _out_T_8457; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_735 = _out_T_8458; // @[RegisterRouter.scala:87:24] wire out_rimask_863 = |_out_rimask_T_863; // @[RegisterRouter.scala:87:24] wire out_wimask_863 = &_out_wimask_T_863; // @[RegisterRouter.scala:87:24] wire out_romask_863 = |_out_romask_T_863; // @[RegisterRouter.scala:87:24] wire out_womask_863 = &_out_womask_T_863; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_863 = out_rivalid_1_717 & out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8460 = out_f_rivalid_863; // @[RegisterRouter.scala:87:24] wire out_f_roready_863 = out_roready_1_717 & out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8461 = out_f_roready_863; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_863 = out_wivalid_1_717 & out_wimask_863; // @[RegisterRouter.scala:87:24] wire out_f_woready_863 = out_woready_1_717 & out_womask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8462 = ~out_rimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8463 = ~out_wimask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8464 = ~out_romask_863; // @[RegisterRouter.scala:87:24] wire _out_T_8465 = ~out_womask_863; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_735 = {hi_219, flags_0_go, _out_prepend_T_735}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8466 = out_prepend_735; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8467 = _out_T_8466; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_736 = _out_T_8467; // @[RegisterRouter.scala:87:24] wire out_rimask_864 = |_out_rimask_T_864; // @[RegisterRouter.scala:87:24] wire out_wimask_864 = &_out_wimask_T_864; // @[RegisterRouter.scala:87:24] wire out_romask_864 = |_out_romask_T_864; // @[RegisterRouter.scala:87:24] wire out_womask_864 = &_out_womask_T_864; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_864 = out_rivalid_1_718 & out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8469 = out_f_rivalid_864; // @[RegisterRouter.scala:87:24] wire out_f_roready_864 = out_roready_1_718 & out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8470 = out_f_roready_864; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_864 = out_wivalid_1_718 & out_wimask_864; // @[RegisterRouter.scala:87:24] wire out_f_woready_864 = out_woready_1_718 & out_womask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8471 = ~out_rimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8472 = ~out_wimask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8473 = ~out_romask_864; // @[RegisterRouter.scala:87:24] wire _out_T_8474 = ~out_womask_864; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_736 = {hi_220, flags_0_go, _out_prepend_T_736}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8475 = out_prepend_736; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8476 = _out_T_8475; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_737 = _out_T_8476; // @[RegisterRouter.scala:87:24] wire out_rimask_865 = |_out_rimask_T_865; // @[RegisterRouter.scala:87:24] wire out_wimask_865 = &_out_wimask_T_865; // @[RegisterRouter.scala:87:24] wire out_romask_865 = |_out_romask_T_865; // @[RegisterRouter.scala:87:24] wire out_womask_865 = &_out_womask_T_865; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_865 = out_rivalid_1_719 & out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8478 = out_f_rivalid_865; // @[RegisterRouter.scala:87:24] wire out_f_roready_865 = out_roready_1_719 & out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8479 = out_f_roready_865; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_865 = out_wivalid_1_719 & out_wimask_865; // @[RegisterRouter.scala:87:24] wire out_f_woready_865 = out_woready_1_719 & out_womask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8480 = ~out_rimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8481 = ~out_wimask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8482 = ~out_romask_865; // @[RegisterRouter.scala:87:24] wire _out_T_8483 = ~out_womask_865; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_737 = {hi_221, flags_0_go, _out_prepend_T_737}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8484 = out_prepend_737; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8485 = _out_T_8484; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_738 = _out_T_8485; // @[RegisterRouter.scala:87:24] wire out_rimask_866 = |_out_rimask_T_866; // @[RegisterRouter.scala:87:24] wire out_wimask_866 = &_out_wimask_T_866; // @[RegisterRouter.scala:87:24] wire out_romask_866 = |_out_romask_T_866; // @[RegisterRouter.scala:87:24] wire out_womask_866 = &_out_womask_T_866; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_866 = out_rivalid_1_720 & out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8487 = out_f_rivalid_866; // @[RegisterRouter.scala:87:24] wire out_f_roready_866 = out_roready_1_720 & out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8488 = out_f_roready_866; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_866 = out_wivalid_1_720 & out_wimask_866; // @[RegisterRouter.scala:87:24] wire out_f_woready_866 = out_woready_1_720 & out_womask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8489 = ~out_rimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8490 = ~out_wimask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8491 = ~out_romask_866; // @[RegisterRouter.scala:87:24] wire _out_T_8492 = ~out_womask_866; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_738 = {hi_222, flags_0_go, _out_prepend_T_738}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8493 = out_prepend_738; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8494 = _out_T_8493; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_739 = _out_T_8494; // @[RegisterRouter.scala:87:24] wire out_rimask_867 = |_out_rimask_T_867; // @[RegisterRouter.scala:87:24] wire out_wimask_867 = &_out_wimask_T_867; // @[RegisterRouter.scala:87:24] wire out_romask_867 = |_out_romask_T_867; // @[RegisterRouter.scala:87:24] wire out_womask_867 = &_out_womask_T_867; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_867 = out_rivalid_1_721 & out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8496 = out_f_rivalid_867; // @[RegisterRouter.scala:87:24] wire out_f_roready_867 = out_roready_1_721 & out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8497 = out_f_roready_867; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_867 = out_wivalid_1_721 & out_wimask_867; // @[RegisterRouter.scala:87:24] wire out_f_woready_867 = out_woready_1_721 & out_womask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8498 = ~out_rimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8499 = ~out_wimask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8500 = ~out_romask_867; // @[RegisterRouter.scala:87:24] wire _out_T_8501 = ~out_womask_867; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_739 = {hi_223, flags_0_go, _out_prepend_T_739}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8502 = out_prepend_739; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8503 = _out_T_8502; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_740 = _out_T_8503; // @[RegisterRouter.scala:87:24] wire out_rimask_868 = |_out_rimask_T_868; // @[RegisterRouter.scala:87:24] wire out_wimask_868 = &_out_wimask_T_868; // @[RegisterRouter.scala:87:24] wire out_romask_868 = |_out_romask_T_868; // @[RegisterRouter.scala:87:24] wire out_womask_868 = &_out_womask_T_868; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_868 = out_rivalid_1_722 & out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8505 = out_f_rivalid_868; // @[RegisterRouter.scala:87:24] wire out_f_roready_868 = out_roready_1_722 & out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8506 = out_f_roready_868; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_868 = out_wivalid_1_722 & out_wimask_868; // @[RegisterRouter.scala:87:24] wire out_f_woready_868 = out_woready_1_722 & out_womask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8507 = ~out_rimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8508 = ~out_wimask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8509 = ~out_romask_868; // @[RegisterRouter.scala:87:24] wire _out_T_8510 = ~out_womask_868; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_740 = {hi_224, flags_0_go, _out_prepend_T_740}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8511 = out_prepend_740; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8512 = _out_T_8511; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_155 = _out_T_8512; // @[MuxLiteral.scala:49:48] wire out_rimask_869 = |_out_rimask_T_869; // @[RegisterRouter.scala:87:24] wire out_wimask_869 = &_out_wimask_T_869; // @[RegisterRouter.scala:87:24] wire out_romask_869 = |_out_romask_T_869; // @[RegisterRouter.scala:87:24] wire out_womask_869 = &_out_womask_T_869; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_869 = out_rivalid_1_723 & out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8514 = out_f_rivalid_869; // @[RegisterRouter.scala:87:24] wire out_f_roready_869 = out_roready_1_723 & out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8515 = out_f_roready_869; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_869 = out_wivalid_1_723 & out_wimask_869; // @[RegisterRouter.scala:87:24] wire out_f_woready_869 = out_woready_1_723 & out_womask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8516 = ~out_rimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8517 = ~out_wimask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8518 = ~out_romask_869; // @[RegisterRouter.scala:87:24] wire _out_T_8519 = ~out_womask_869; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8521 = _out_T_8520; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_741 = _out_T_8521; // @[RegisterRouter.scala:87:24] wire out_rimask_870 = |_out_rimask_T_870; // @[RegisterRouter.scala:87:24] wire out_wimask_870 = &_out_wimask_T_870; // @[RegisterRouter.scala:87:24] wire out_romask_870 = |_out_romask_T_870; // @[RegisterRouter.scala:87:24] wire out_womask_870 = &_out_womask_T_870; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_870 = out_rivalid_1_724 & out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8523 = out_f_rivalid_870; // @[RegisterRouter.scala:87:24] wire out_f_roready_870 = out_roready_1_724 & out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8524 = out_f_roready_870; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_870 = out_wivalid_1_724 & out_wimask_870; // @[RegisterRouter.scala:87:24] wire out_f_woready_870 = out_woready_1_724 & out_womask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8525 = ~out_rimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8526 = ~out_wimask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8527 = ~out_romask_870; // @[RegisterRouter.scala:87:24] wire _out_T_8528 = ~out_womask_870; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_741 = {hi_562, flags_0_go, _out_prepend_T_741}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8529 = out_prepend_741; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8530 = _out_T_8529; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_742 = _out_T_8530; // @[RegisterRouter.scala:87:24] wire out_rimask_871 = |_out_rimask_T_871; // @[RegisterRouter.scala:87:24] wire out_wimask_871 = &_out_wimask_T_871; // @[RegisterRouter.scala:87:24] wire out_romask_871 = |_out_romask_T_871; // @[RegisterRouter.scala:87:24] wire out_womask_871 = &_out_womask_T_871; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_871 = out_rivalid_1_725 & out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8532 = out_f_rivalid_871; // @[RegisterRouter.scala:87:24] wire out_f_roready_871 = out_roready_1_725 & out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8533 = out_f_roready_871; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_871 = out_wivalid_1_725 & out_wimask_871; // @[RegisterRouter.scala:87:24] wire out_f_woready_871 = out_woready_1_725 & out_womask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8534 = ~out_rimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8535 = ~out_wimask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8536 = ~out_romask_871; // @[RegisterRouter.scala:87:24] wire _out_T_8537 = ~out_womask_871; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_742 = {hi_563, flags_0_go, _out_prepend_T_742}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8538 = out_prepend_742; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8539 = _out_T_8538; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_743 = _out_T_8539; // @[RegisterRouter.scala:87:24] wire out_rimask_872 = |_out_rimask_T_872; // @[RegisterRouter.scala:87:24] wire out_wimask_872 = &_out_wimask_T_872; // @[RegisterRouter.scala:87:24] wire out_romask_872 = |_out_romask_T_872; // @[RegisterRouter.scala:87:24] wire out_womask_872 = &_out_womask_T_872; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_872 = out_rivalid_1_726 & out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8541 = out_f_rivalid_872; // @[RegisterRouter.scala:87:24] wire out_f_roready_872 = out_roready_1_726 & out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8542 = out_f_roready_872; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_872 = out_wivalid_1_726 & out_wimask_872; // @[RegisterRouter.scala:87:24] wire out_f_woready_872 = out_woready_1_726 & out_womask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8543 = ~out_rimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8544 = ~out_wimask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8545 = ~out_romask_872; // @[RegisterRouter.scala:87:24] wire _out_T_8546 = ~out_womask_872; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_743 = {hi_564, flags_0_go, _out_prepend_T_743}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8547 = out_prepend_743; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8548 = _out_T_8547; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_744 = _out_T_8548; // @[RegisterRouter.scala:87:24] wire out_rimask_873 = |_out_rimask_T_873; // @[RegisterRouter.scala:87:24] wire out_wimask_873 = &_out_wimask_T_873; // @[RegisterRouter.scala:87:24] wire out_romask_873 = |_out_romask_T_873; // @[RegisterRouter.scala:87:24] wire out_womask_873 = &_out_womask_T_873; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_873 = out_rivalid_1_727 & out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8550 = out_f_rivalid_873; // @[RegisterRouter.scala:87:24] wire out_f_roready_873 = out_roready_1_727 & out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8551 = out_f_roready_873; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_873 = out_wivalid_1_727 & out_wimask_873; // @[RegisterRouter.scala:87:24] wire out_f_woready_873 = out_woready_1_727 & out_womask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8552 = ~out_rimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8553 = ~out_wimask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8554 = ~out_romask_873; // @[RegisterRouter.scala:87:24] wire _out_T_8555 = ~out_womask_873; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_744 = {hi_565, flags_0_go, _out_prepend_T_744}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8556 = out_prepend_744; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8557 = _out_T_8556; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_745 = _out_T_8557; // @[RegisterRouter.scala:87:24] wire out_rimask_874 = |_out_rimask_T_874; // @[RegisterRouter.scala:87:24] wire out_wimask_874 = &_out_wimask_T_874; // @[RegisterRouter.scala:87:24] wire out_romask_874 = |_out_romask_T_874; // @[RegisterRouter.scala:87:24] wire out_womask_874 = &_out_womask_T_874; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_874 = out_rivalid_1_728 & out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8559 = out_f_rivalid_874; // @[RegisterRouter.scala:87:24] wire out_f_roready_874 = out_roready_1_728 & out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8560 = out_f_roready_874; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_874 = out_wivalid_1_728 & out_wimask_874; // @[RegisterRouter.scala:87:24] wire out_f_woready_874 = out_woready_1_728 & out_womask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8561 = ~out_rimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8562 = ~out_wimask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8563 = ~out_romask_874; // @[RegisterRouter.scala:87:24] wire _out_T_8564 = ~out_womask_874; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_745 = {hi_566, flags_0_go, _out_prepend_T_745}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8565 = out_prepend_745; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8566 = _out_T_8565; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_746 = _out_T_8566; // @[RegisterRouter.scala:87:24] wire out_rimask_875 = |_out_rimask_T_875; // @[RegisterRouter.scala:87:24] wire out_wimask_875 = &_out_wimask_T_875; // @[RegisterRouter.scala:87:24] wire out_romask_875 = |_out_romask_T_875; // @[RegisterRouter.scala:87:24] wire out_womask_875 = &_out_womask_T_875; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_875 = out_rivalid_1_729 & out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8568 = out_f_rivalid_875; // @[RegisterRouter.scala:87:24] wire out_f_roready_875 = out_roready_1_729 & out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8569 = out_f_roready_875; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_875 = out_wivalid_1_729 & out_wimask_875; // @[RegisterRouter.scala:87:24] wire out_f_woready_875 = out_woready_1_729 & out_womask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8570 = ~out_rimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8571 = ~out_wimask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8572 = ~out_romask_875; // @[RegisterRouter.scala:87:24] wire _out_T_8573 = ~out_womask_875; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_746 = {hi_567, flags_0_go, _out_prepend_T_746}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8574 = out_prepend_746; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8575 = _out_T_8574; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_747 = _out_T_8575; // @[RegisterRouter.scala:87:24] wire out_rimask_876 = |_out_rimask_T_876; // @[RegisterRouter.scala:87:24] wire out_wimask_876 = &_out_wimask_T_876; // @[RegisterRouter.scala:87:24] wire out_romask_876 = |_out_romask_T_876; // @[RegisterRouter.scala:87:24] wire out_womask_876 = &_out_womask_T_876; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_876 = out_rivalid_1_730 & out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8577 = out_f_rivalid_876; // @[RegisterRouter.scala:87:24] wire out_f_roready_876 = out_roready_1_730 & out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8578 = out_f_roready_876; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_876 = out_wivalid_1_730 & out_wimask_876; // @[RegisterRouter.scala:87:24] wire out_f_woready_876 = out_woready_1_730 & out_womask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8579 = ~out_rimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8580 = ~out_wimask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8581 = ~out_romask_876; // @[RegisterRouter.scala:87:24] wire _out_T_8582 = ~out_womask_876; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_747 = {hi_568, flags_0_go, _out_prepend_T_747}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8583 = out_prepend_747; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8584 = _out_T_8583; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_198 = _out_T_8584; // @[MuxLiteral.scala:49:48] wire out_rimask_877 = |_out_rimask_T_877; // @[RegisterRouter.scala:87:24] wire out_wimask_877 = &_out_wimask_T_877; // @[RegisterRouter.scala:87:24] wire out_romask_877 = |_out_romask_T_877; // @[RegisterRouter.scala:87:24] wire out_womask_877 = &_out_womask_T_877; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_877 = out_rivalid_1_731 & out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8586 = out_f_rivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_roready_877 = out_roready_1_731 & out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8587 = out_f_roready_877; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_877 = out_wivalid_1_731 & out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8588 = out_f_wivalid_877; // @[RegisterRouter.scala:87:24] wire out_f_woready_877 = out_woready_1_731 & out_womask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8589 = out_f_woready_877; // @[RegisterRouter.scala:87:24] wire _out_T_8590 = ~out_rimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8591 = ~out_wimask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8592 = ~out_romask_877; // @[RegisterRouter.scala:87:24] wire _out_T_8593 = ~out_womask_877; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8595 = _out_T_8594; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_748 = _out_T_8595; // @[RegisterRouter.scala:87:24] wire out_rimask_878 = |_out_rimask_T_878; // @[RegisterRouter.scala:87:24] wire out_wimask_878 = &_out_wimask_T_878; // @[RegisterRouter.scala:87:24] wire out_romask_878 = |_out_romask_T_878; // @[RegisterRouter.scala:87:24] wire out_womask_878 = &_out_womask_T_878; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_878 = out_rivalid_1_732 & out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8597 = out_f_rivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_roready_878 = out_roready_1_732 & out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8598 = out_f_roready_878; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_878 = out_wivalid_1_732 & out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8599 = out_f_wivalid_878; // @[RegisterRouter.scala:87:24] wire out_f_woready_878 = out_woready_1_732 & out_womask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8600 = out_f_woready_878; // @[RegisterRouter.scala:87:24] wire _out_T_8601 = ~out_rimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8602 = ~out_wimask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8603 = ~out_romask_878; // @[RegisterRouter.scala:87:24] wire _out_T_8604 = ~out_womask_878; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_748 = {programBufferMem_33, _out_prepend_T_748}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8605 = out_prepend_748; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8606 = _out_T_8605; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_749 = _out_T_8606; // @[RegisterRouter.scala:87:24] wire out_rimask_879 = |_out_rimask_T_879; // @[RegisterRouter.scala:87:24] wire out_wimask_879 = &_out_wimask_T_879; // @[RegisterRouter.scala:87:24] wire out_romask_879 = |_out_romask_T_879; // @[RegisterRouter.scala:87:24] wire out_womask_879 = &_out_womask_T_879; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_879 = out_rivalid_1_733 & out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8608 = out_f_rivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_roready_879 = out_roready_1_733 & out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8609 = out_f_roready_879; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_879 = out_wivalid_1_733 & out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8610 = out_f_wivalid_879; // @[RegisterRouter.scala:87:24] wire out_f_woready_879 = out_woready_1_733 & out_womask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8611 = out_f_woready_879; // @[RegisterRouter.scala:87:24] wire _out_T_8612 = ~out_rimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8613 = ~out_wimask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8614 = ~out_romask_879; // @[RegisterRouter.scala:87:24] wire _out_T_8615 = ~out_womask_879; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_749 = {programBufferMem_34, _out_prepend_T_749}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8616 = out_prepend_749; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8617 = _out_T_8616; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_750 = _out_T_8617; // @[RegisterRouter.scala:87:24] wire out_rimask_880 = |_out_rimask_T_880; // @[RegisterRouter.scala:87:24] wire out_wimask_880 = &_out_wimask_T_880; // @[RegisterRouter.scala:87:24] wire out_romask_880 = |_out_romask_T_880; // @[RegisterRouter.scala:87:24] wire out_womask_880 = &_out_womask_T_880; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_880 = out_rivalid_1_734 & out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8619 = out_f_rivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_roready_880 = out_roready_1_734 & out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8620 = out_f_roready_880; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_880 = out_wivalid_1_734 & out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8621 = out_f_wivalid_880; // @[RegisterRouter.scala:87:24] wire out_f_woready_880 = out_woready_1_734 & out_womask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8622 = out_f_woready_880; // @[RegisterRouter.scala:87:24] wire _out_T_8623 = ~out_rimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8624 = ~out_wimask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8625 = ~out_romask_880; // @[RegisterRouter.scala:87:24] wire _out_T_8626 = ~out_womask_880; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_750 = {programBufferMem_35, _out_prepend_T_750}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8627 = out_prepend_750; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8628 = _out_T_8627; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_751 = _out_T_8628; // @[RegisterRouter.scala:87:24] wire out_rimask_881 = |_out_rimask_T_881; // @[RegisterRouter.scala:87:24] wire out_wimask_881 = &_out_wimask_T_881; // @[RegisterRouter.scala:87:24] wire out_romask_881 = |_out_romask_T_881; // @[RegisterRouter.scala:87:24] wire out_womask_881 = &_out_womask_T_881; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_881 = out_rivalid_1_735 & out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8630 = out_f_rivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_roready_881 = out_roready_1_735 & out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8631 = out_f_roready_881; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_881 = out_wivalid_1_735 & out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8632 = out_f_wivalid_881; // @[RegisterRouter.scala:87:24] wire out_f_woready_881 = out_woready_1_735 & out_womask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8633 = out_f_woready_881; // @[RegisterRouter.scala:87:24] wire _out_T_8634 = ~out_rimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8635 = ~out_wimask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8636 = ~out_romask_881; // @[RegisterRouter.scala:87:24] wire _out_T_8637 = ~out_womask_881; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_751 = {programBufferMem_36, _out_prepend_T_751}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8638 = out_prepend_751; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8639 = _out_T_8638; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_752 = _out_T_8639; // @[RegisterRouter.scala:87:24] wire out_rimask_882 = |_out_rimask_T_882; // @[RegisterRouter.scala:87:24] wire out_wimask_882 = &_out_wimask_T_882; // @[RegisterRouter.scala:87:24] wire out_romask_882 = |_out_romask_T_882; // @[RegisterRouter.scala:87:24] wire out_womask_882 = &_out_womask_T_882; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_882 = out_rivalid_1_736 & out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8641 = out_f_rivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_roready_882 = out_roready_1_736 & out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8642 = out_f_roready_882; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_882 = out_wivalid_1_736 & out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8643 = out_f_wivalid_882; // @[RegisterRouter.scala:87:24] wire out_f_woready_882 = out_woready_1_736 & out_womask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8644 = out_f_woready_882; // @[RegisterRouter.scala:87:24] wire _out_T_8645 = ~out_rimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8646 = ~out_wimask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8647 = ~out_romask_882; // @[RegisterRouter.scala:87:24] wire _out_T_8648 = ~out_womask_882; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_752 = {programBufferMem_37, _out_prepend_T_752}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8649 = out_prepend_752; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8650 = _out_T_8649; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_753 = _out_T_8650; // @[RegisterRouter.scala:87:24] wire out_rimask_883 = |_out_rimask_T_883; // @[RegisterRouter.scala:87:24] wire out_wimask_883 = &_out_wimask_T_883; // @[RegisterRouter.scala:87:24] wire out_romask_883 = |_out_romask_T_883; // @[RegisterRouter.scala:87:24] wire out_womask_883 = &_out_womask_T_883; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_883 = out_rivalid_1_737 & out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8652 = out_f_rivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_roready_883 = out_roready_1_737 & out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8653 = out_f_roready_883; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_883 = out_wivalid_1_737 & out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8654 = out_f_wivalid_883; // @[RegisterRouter.scala:87:24] wire out_f_woready_883 = out_woready_1_737 & out_womask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8655 = out_f_woready_883; // @[RegisterRouter.scala:87:24] wire _out_T_8656 = ~out_rimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8657 = ~out_wimask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8658 = ~out_romask_883; // @[RegisterRouter.scala:87:24] wire _out_T_8659 = ~out_womask_883; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_753 = {programBufferMem_38, _out_prepend_T_753}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8660 = out_prepend_753; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8661 = _out_T_8660; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_754 = _out_T_8661; // @[RegisterRouter.scala:87:24] wire out_rimask_884 = |_out_rimask_T_884; // @[RegisterRouter.scala:87:24] wire out_wimask_884 = &_out_wimask_T_884; // @[RegisterRouter.scala:87:24] wire out_romask_884 = |_out_romask_T_884; // @[RegisterRouter.scala:87:24] wire out_womask_884 = &_out_womask_T_884; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_884 = out_rivalid_1_738 & out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8663 = out_f_rivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_roready_884 = out_roready_1_738 & out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8664 = out_f_roready_884; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_884 = out_wivalid_1_738 & out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8665 = out_f_wivalid_884; // @[RegisterRouter.scala:87:24] wire out_f_woready_884 = out_woready_1_738 & out_womask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8666 = out_f_woready_884; // @[RegisterRouter.scala:87:24] wire _out_T_8667 = ~out_rimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8668 = ~out_wimask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8669 = ~out_romask_884; // @[RegisterRouter.scala:87:24] wire _out_T_8670 = ~out_womask_884; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_754 = {programBufferMem_39, _out_prepend_T_754}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8671 = out_prepend_754; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8672 = _out_T_8671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_108 = _out_T_8672; // @[MuxLiteral.scala:49:48] wire out_rimask_885 = |_out_rimask_T_885; // @[RegisterRouter.scala:87:24] wire out_wimask_885 = &_out_wimask_T_885; // @[RegisterRouter.scala:87:24] wire out_romask_885 = |_out_romask_T_885; // @[RegisterRouter.scala:87:24] wire out_womask_885 = &_out_womask_T_885; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_885 = out_rivalid_1_739 & out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8674 = out_f_rivalid_885; // @[RegisterRouter.scala:87:24] wire out_f_roready_885 = out_roready_1_739 & out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8675 = out_f_roready_885; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_885 = out_wivalid_1_739 & out_wimask_885; // @[RegisterRouter.scala:87:24] wire out_f_woready_885 = out_woready_1_739 & out_womask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8676 = ~out_rimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8677 = ~out_wimask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8678 = ~out_romask_885; // @[RegisterRouter.scala:87:24] wire _out_T_8679 = ~out_womask_885; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8681 = _out_T_8680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_755 = _out_T_8681; // @[RegisterRouter.scala:87:24] wire out_rimask_886 = |_out_rimask_T_886; // @[RegisterRouter.scala:87:24] wire out_wimask_886 = &_out_wimask_T_886; // @[RegisterRouter.scala:87:24] wire out_romask_886 = |_out_romask_T_886; // @[RegisterRouter.scala:87:24] wire out_womask_886 = &_out_womask_T_886; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_886 = out_rivalid_1_740 & out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8683 = out_f_rivalid_886; // @[RegisterRouter.scala:87:24] wire out_f_roready_886 = out_roready_1_740 & out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8684 = out_f_roready_886; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_886 = out_wivalid_1_740 & out_wimask_886; // @[RegisterRouter.scala:87:24] wire out_f_woready_886 = out_woready_1_740 & out_womask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8685 = ~out_rimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8686 = ~out_wimask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8687 = ~out_romask_886; // @[RegisterRouter.scala:87:24] wire _out_T_8688 = ~out_womask_886; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_755 = {hi_898, flags_0_go, _out_prepend_T_755}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8689 = out_prepend_755; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8690 = _out_T_8689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_756 = _out_T_8690; // @[RegisterRouter.scala:87:24] wire out_rimask_887 = |_out_rimask_T_887; // @[RegisterRouter.scala:87:24] wire out_wimask_887 = &_out_wimask_T_887; // @[RegisterRouter.scala:87:24] wire out_romask_887 = |_out_romask_T_887; // @[RegisterRouter.scala:87:24] wire out_womask_887 = &_out_womask_T_887; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_887 = out_rivalid_1_741 & out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8692 = out_f_rivalid_887; // @[RegisterRouter.scala:87:24] wire out_f_roready_887 = out_roready_1_741 & out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8693 = out_f_roready_887; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_887 = out_wivalid_1_741 & out_wimask_887; // @[RegisterRouter.scala:87:24] wire out_f_woready_887 = out_woready_1_741 & out_womask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8694 = ~out_rimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8695 = ~out_wimask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8696 = ~out_romask_887; // @[RegisterRouter.scala:87:24] wire _out_T_8697 = ~out_womask_887; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_756 = {hi_899, flags_0_go, _out_prepend_T_756}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8698 = out_prepend_756; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8699 = _out_T_8698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_757 = _out_T_8699; // @[RegisterRouter.scala:87:24] wire out_rimask_888 = |_out_rimask_T_888; // @[RegisterRouter.scala:87:24] wire out_wimask_888 = &_out_wimask_T_888; // @[RegisterRouter.scala:87:24] wire out_romask_888 = |_out_romask_T_888; // @[RegisterRouter.scala:87:24] wire out_womask_888 = &_out_womask_T_888; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_888 = out_rivalid_1_742 & out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8701 = out_f_rivalid_888; // @[RegisterRouter.scala:87:24] wire out_f_roready_888 = out_roready_1_742 & out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8702 = out_f_roready_888; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_888 = out_wivalid_1_742 & out_wimask_888; // @[RegisterRouter.scala:87:24] wire out_f_woready_888 = out_woready_1_742 & out_womask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8703 = ~out_rimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8704 = ~out_wimask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8705 = ~out_romask_888; // @[RegisterRouter.scala:87:24] wire _out_T_8706 = ~out_womask_888; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_757 = {hi_900, flags_0_go, _out_prepend_T_757}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8707 = out_prepend_757; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8708 = _out_T_8707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_758 = _out_T_8708; // @[RegisterRouter.scala:87:24] wire out_rimask_889 = |_out_rimask_T_889; // @[RegisterRouter.scala:87:24] wire out_wimask_889 = &_out_wimask_T_889; // @[RegisterRouter.scala:87:24] wire out_romask_889 = |_out_romask_T_889; // @[RegisterRouter.scala:87:24] wire out_womask_889 = &_out_womask_T_889; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_889 = out_rivalid_1_743 & out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8710 = out_f_rivalid_889; // @[RegisterRouter.scala:87:24] wire out_f_roready_889 = out_roready_1_743 & out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8711 = out_f_roready_889; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_889 = out_wivalid_1_743 & out_wimask_889; // @[RegisterRouter.scala:87:24] wire out_f_woready_889 = out_woready_1_743 & out_womask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8712 = ~out_rimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8713 = ~out_wimask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8714 = ~out_romask_889; // @[RegisterRouter.scala:87:24] wire _out_T_8715 = ~out_womask_889; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_758 = {hi_901, flags_0_go, _out_prepend_T_758}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8716 = out_prepend_758; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8717 = _out_T_8716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_759 = _out_T_8717; // @[RegisterRouter.scala:87:24] wire out_rimask_890 = |_out_rimask_T_890; // @[RegisterRouter.scala:87:24] wire out_wimask_890 = &_out_wimask_T_890; // @[RegisterRouter.scala:87:24] wire out_romask_890 = |_out_romask_T_890; // @[RegisterRouter.scala:87:24] wire out_womask_890 = &_out_womask_T_890; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_890 = out_rivalid_1_744 & out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8719 = out_f_rivalid_890; // @[RegisterRouter.scala:87:24] wire out_f_roready_890 = out_roready_1_744 & out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8720 = out_f_roready_890; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_890 = out_wivalid_1_744 & out_wimask_890; // @[RegisterRouter.scala:87:24] wire out_f_woready_890 = out_woready_1_744 & out_womask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8721 = ~out_rimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8722 = ~out_wimask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8723 = ~out_romask_890; // @[RegisterRouter.scala:87:24] wire _out_T_8724 = ~out_womask_890; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_759 = {hi_902, flags_0_go, _out_prepend_T_759}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8725 = out_prepend_759; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8726 = _out_T_8725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_760 = _out_T_8726; // @[RegisterRouter.scala:87:24] wire out_rimask_891 = |_out_rimask_T_891; // @[RegisterRouter.scala:87:24] wire out_wimask_891 = &_out_wimask_T_891; // @[RegisterRouter.scala:87:24] wire out_romask_891 = |_out_romask_T_891; // @[RegisterRouter.scala:87:24] wire out_womask_891 = &_out_womask_T_891; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_891 = out_rivalid_1_745 & out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8728 = out_f_rivalid_891; // @[RegisterRouter.scala:87:24] wire out_f_roready_891 = out_roready_1_745 & out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8729 = out_f_roready_891; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_891 = out_wivalid_1_745 & out_wimask_891; // @[RegisterRouter.scala:87:24] wire out_f_woready_891 = out_woready_1_745 & out_womask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8730 = ~out_rimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8731 = ~out_wimask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8732 = ~out_romask_891; // @[RegisterRouter.scala:87:24] wire _out_T_8733 = ~out_womask_891; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_760 = {hi_903, flags_0_go, _out_prepend_T_760}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8734 = out_prepend_760; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8735 = _out_T_8734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_761 = _out_T_8735; // @[RegisterRouter.scala:87:24] wire out_rimask_892 = |_out_rimask_T_892; // @[RegisterRouter.scala:87:24] wire out_wimask_892 = &_out_wimask_T_892; // @[RegisterRouter.scala:87:24] wire out_romask_892 = |_out_romask_T_892; // @[RegisterRouter.scala:87:24] wire out_womask_892 = &_out_womask_T_892; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_892 = out_rivalid_1_746 & out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8737 = out_f_rivalid_892; // @[RegisterRouter.scala:87:24] wire out_f_roready_892 = out_roready_1_746 & out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8738 = out_f_roready_892; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_892 = out_wivalid_1_746 & out_wimask_892; // @[RegisterRouter.scala:87:24] wire out_f_woready_892 = out_woready_1_746 & out_womask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8739 = ~out_rimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8740 = ~out_wimask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8741 = ~out_romask_892; // @[RegisterRouter.scala:87:24] wire _out_T_8742 = ~out_womask_892; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_761 = {hi_904, flags_0_go, _out_prepend_T_761}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8743 = out_prepend_761; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8744 = _out_T_8743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_240 = _out_T_8744; // @[MuxLiteral.scala:49:48] wire out_rimask_893 = |_out_rimask_T_893; // @[RegisterRouter.scala:87:24] wire out_wimask_893 = &_out_wimask_T_893; // @[RegisterRouter.scala:87:24] wire out_romask_893 = |_out_romask_T_893; // @[RegisterRouter.scala:87:24] wire out_womask_893 = &_out_womask_T_893; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_893 = out_rivalid_1_747 & out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8746 = out_f_rivalid_893; // @[RegisterRouter.scala:87:24] wire out_f_roready_893 = out_roready_1_747 & out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8747 = out_f_roready_893; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_893 = out_wivalid_1_747 & out_wimask_893; // @[RegisterRouter.scala:87:24] wire out_f_woready_893 = out_woready_1_747 & out_womask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8748 = ~out_rimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8749 = ~out_wimask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8750 = ~out_romask_893; // @[RegisterRouter.scala:87:24] wire _out_T_8751 = ~out_womask_893; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8753 = _out_T_8752; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_762 = _out_T_8753; // @[RegisterRouter.scala:87:24] wire out_rimask_894 = |_out_rimask_T_894; // @[RegisterRouter.scala:87:24] wire out_wimask_894 = &_out_wimask_T_894; // @[RegisterRouter.scala:87:24] wire out_romask_894 = |_out_romask_T_894; // @[RegisterRouter.scala:87:24] wire out_womask_894 = &_out_womask_T_894; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_894 = out_rivalid_1_748 & out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8755 = out_f_rivalid_894; // @[RegisterRouter.scala:87:24] wire out_f_roready_894 = out_roready_1_748 & out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8756 = out_f_roready_894; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_894 = out_wivalid_1_748 & out_wimask_894; // @[RegisterRouter.scala:87:24] wire out_f_woready_894 = out_woready_1_748 & out_womask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8757 = ~out_rimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8758 = ~out_wimask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8759 = ~out_romask_894; // @[RegisterRouter.scala:87:24] wire _out_T_8760 = ~out_womask_894; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_762 = {hi_986, flags_0_go, _out_prepend_T_762}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8761 = out_prepend_762; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8762 = _out_T_8761; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_763 = _out_T_8762; // @[RegisterRouter.scala:87:24] wire out_rimask_895 = |_out_rimask_T_895; // @[RegisterRouter.scala:87:24] wire out_wimask_895 = &_out_wimask_T_895; // @[RegisterRouter.scala:87:24] wire out_romask_895 = |_out_romask_T_895; // @[RegisterRouter.scala:87:24] wire out_womask_895 = &_out_womask_T_895; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_895 = out_rivalid_1_749 & out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8764 = out_f_rivalid_895; // @[RegisterRouter.scala:87:24] wire out_f_roready_895 = out_roready_1_749 & out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8765 = out_f_roready_895; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_895 = out_wivalid_1_749 & out_wimask_895; // @[RegisterRouter.scala:87:24] wire out_f_woready_895 = out_woready_1_749 & out_womask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8766 = ~out_rimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8767 = ~out_wimask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8768 = ~out_romask_895; // @[RegisterRouter.scala:87:24] wire _out_T_8769 = ~out_womask_895; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_763 = {hi_987, flags_0_go, _out_prepend_T_763}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8770 = out_prepend_763; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8771 = _out_T_8770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_764 = _out_T_8771; // @[RegisterRouter.scala:87:24] wire out_rimask_896 = |_out_rimask_T_896; // @[RegisterRouter.scala:87:24] wire out_wimask_896 = &_out_wimask_T_896; // @[RegisterRouter.scala:87:24] wire out_romask_896 = |_out_romask_T_896; // @[RegisterRouter.scala:87:24] wire out_womask_896 = &_out_womask_T_896; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_896 = out_rivalid_1_750 & out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8773 = out_f_rivalid_896; // @[RegisterRouter.scala:87:24] wire out_f_roready_896 = out_roready_1_750 & out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8774 = out_f_roready_896; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_896 = out_wivalid_1_750 & out_wimask_896; // @[RegisterRouter.scala:87:24] wire out_f_woready_896 = out_woready_1_750 & out_womask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8775 = ~out_rimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8776 = ~out_wimask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8777 = ~out_romask_896; // @[RegisterRouter.scala:87:24] wire _out_T_8778 = ~out_womask_896; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_764 = {hi_988, flags_0_go, _out_prepend_T_764}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8779 = out_prepend_764; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8780 = _out_T_8779; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_765 = _out_T_8780; // @[RegisterRouter.scala:87:24] wire out_rimask_897 = |_out_rimask_T_897; // @[RegisterRouter.scala:87:24] wire out_wimask_897 = &_out_wimask_T_897; // @[RegisterRouter.scala:87:24] wire out_romask_897 = |_out_romask_T_897; // @[RegisterRouter.scala:87:24] wire out_womask_897 = &_out_womask_T_897; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_897 = out_rivalid_1_751 & out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8782 = out_f_rivalid_897; // @[RegisterRouter.scala:87:24] wire out_f_roready_897 = out_roready_1_751 & out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8783 = out_f_roready_897; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_897 = out_wivalid_1_751 & out_wimask_897; // @[RegisterRouter.scala:87:24] wire out_f_woready_897 = out_woready_1_751 & out_womask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8784 = ~out_rimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8785 = ~out_wimask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8786 = ~out_romask_897; // @[RegisterRouter.scala:87:24] wire _out_T_8787 = ~out_womask_897; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_765 = {hi_989, flags_0_go, _out_prepend_T_765}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8788 = out_prepend_765; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8789 = _out_T_8788; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_766 = _out_T_8789; // @[RegisterRouter.scala:87:24] wire out_rimask_898 = |_out_rimask_T_898; // @[RegisterRouter.scala:87:24] wire out_wimask_898 = &_out_wimask_T_898; // @[RegisterRouter.scala:87:24] wire out_romask_898 = |_out_romask_T_898; // @[RegisterRouter.scala:87:24] wire out_womask_898 = &_out_womask_T_898; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_898 = out_rivalid_1_752 & out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8791 = out_f_rivalid_898; // @[RegisterRouter.scala:87:24] wire out_f_roready_898 = out_roready_1_752 & out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8792 = out_f_roready_898; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_898 = out_wivalid_1_752 & out_wimask_898; // @[RegisterRouter.scala:87:24] wire out_f_woready_898 = out_woready_1_752 & out_womask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8793 = ~out_rimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8794 = ~out_wimask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8795 = ~out_romask_898; // @[RegisterRouter.scala:87:24] wire _out_T_8796 = ~out_womask_898; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_766 = {hi_990, flags_0_go, _out_prepend_T_766}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8797 = out_prepend_766; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8798 = _out_T_8797; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_767 = _out_T_8798; // @[RegisterRouter.scala:87:24] wire out_rimask_899 = |_out_rimask_T_899; // @[RegisterRouter.scala:87:24] wire out_wimask_899 = &_out_wimask_T_899; // @[RegisterRouter.scala:87:24] wire out_romask_899 = |_out_romask_T_899; // @[RegisterRouter.scala:87:24] wire out_womask_899 = &_out_womask_T_899; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_899 = out_rivalid_1_753 & out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8800 = out_f_rivalid_899; // @[RegisterRouter.scala:87:24] wire out_f_roready_899 = out_roready_1_753 & out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8801 = out_f_roready_899; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_899 = out_wivalid_1_753 & out_wimask_899; // @[RegisterRouter.scala:87:24] wire out_f_woready_899 = out_woready_1_753 & out_womask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8802 = ~out_rimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8803 = ~out_wimask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8804 = ~out_romask_899; // @[RegisterRouter.scala:87:24] wire _out_T_8805 = ~out_womask_899; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_767 = {hi_991, flags_0_go, _out_prepend_T_767}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8806 = out_prepend_767; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8807 = _out_T_8806; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_768 = _out_T_8807; // @[RegisterRouter.scala:87:24] wire out_rimask_900 = |_out_rimask_T_900; // @[RegisterRouter.scala:87:24] wire out_wimask_900 = &_out_wimask_T_900; // @[RegisterRouter.scala:87:24] wire out_romask_900 = |_out_romask_T_900; // @[RegisterRouter.scala:87:24] wire out_womask_900 = &_out_womask_T_900; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_900 = out_rivalid_1_754 & out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8809 = out_f_rivalid_900; // @[RegisterRouter.scala:87:24] wire out_f_roready_900 = out_roready_1_754 & out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8810 = out_f_roready_900; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_900 = out_wivalid_1_754 & out_wimask_900; // @[RegisterRouter.scala:87:24] wire out_f_woready_900 = out_woready_1_754 & out_womask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8811 = ~out_rimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8812 = ~out_wimask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8813 = ~out_romask_900; // @[RegisterRouter.scala:87:24] wire _out_T_8814 = ~out_womask_900; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_768 = {hi_992, flags_0_go, _out_prepend_T_768}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8815 = out_prepend_768; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8816 = _out_T_8815; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_251 = _out_T_8816; // @[MuxLiteral.scala:49:48] wire out_rimask_901 = |_out_rimask_T_901; // @[RegisterRouter.scala:87:24] wire out_wimask_901 = &_out_wimask_T_901; // @[RegisterRouter.scala:87:24] wire out_romask_901 = |_out_romask_T_901; // @[RegisterRouter.scala:87:24] wire out_womask_901 = &_out_womask_T_901; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_901 = out_rivalid_1_755 & out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8818 = out_f_rivalid_901; // @[RegisterRouter.scala:87:24] wire out_f_roready_901 = out_roready_1_755 & out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8819 = out_f_roready_901; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_901 = out_wivalid_1_755 & out_wimask_901; // @[RegisterRouter.scala:87:24] wire out_f_woready_901 = out_woready_1_755 & out_womask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8820 = ~out_rimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8821 = ~out_wimask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8822 = ~out_romask_901; // @[RegisterRouter.scala:87:24] wire _out_T_8823 = ~out_womask_901; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8825 = _out_T_8824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_769 = _out_T_8825; // @[RegisterRouter.scala:87:24] wire out_rimask_902 = |_out_rimask_T_902; // @[RegisterRouter.scala:87:24] wire out_wimask_902 = &_out_wimask_T_902; // @[RegisterRouter.scala:87:24] wire out_romask_902 = |_out_romask_T_902; // @[RegisterRouter.scala:87:24] wire out_womask_902 = &_out_womask_T_902; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_902 = out_rivalid_1_756 & out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8827 = out_f_rivalid_902; // @[RegisterRouter.scala:87:24] wire out_f_roready_902 = out_roready_1_756 & out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8828 = out_f_roready_902; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_902 = out_wivalid_1_756 & out_wimask_902; // @[RegisterRouter.scala:87:24] wire out_f_woready_902 = out_woready_1_756 & out_womask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8829 = ~out_rimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8830 = ~out_wimask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8831 = ~out_romask_902; // @[RegisterRouter.scala:87:24] wire _out_T_8832 = ~out_womask_902; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_769 = {hi_18, flags_0_go, _out_prepend_T_769}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8833 = out_prepend_769; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8834 = _out_T_8833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_770 = _out_T_8834; // @[RegisterRouter.scala:87:24] wire out_rimask_903 = |_out_rimask_T_903; // @[RegisterRouter.scala:87:24] wire out_wimask_903 = &_out_wimask_T_903; // @[RegisterRouter.scala:87:24] wire out_romask_903 = |_out_romask_T_903; // @[RegisterRouter.scala:87:24] wire out_womask_903 = &_out_womask_T_903; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_903 = out_rivalid_1_757 & out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8836 = out_f_rivalid_903; // @[RegisterRouter.scala:87:24] wire out_f_roready_903 = out_roready_1_757 & out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8837 = out_f_roready_903; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_903 = out_wivalid_1_757 & out_wimask_903; // @[RegisterRouter.scala:87:24] wire out_f_woready_903 = out_woready_1_757 & out_womask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8838 = ~out_rimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8839 = ~out_wimask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8840 = ~out_romask_903; // @[RegisterRouter.scala:87:24] wire _out_T_8841 = ~out_womask_903; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_770 = {hi_19, flags_0_go, _out_prepend_T_770}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8842 = out_prepend_770; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8843 = _out_T_8842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_771 = _out_T_8843; // @[RegisterRouter.scala:87:24] wire out_rimask_904 = |_out_rimask_T_904; // @[RegisterRouter.scala:87:24] wire out_wimask_904 = &_out_wimask_T_904; // @[RegisterRouter.scala:87:24] wire out_romask_904 = |_out_romask_T_904; // @[RegisterRouter.scala:87:24] wire out_womask_904 = &_out_womask_T_904; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_904 = out_rivalid_1_758 & out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8845 = out_f_rivalid_904; // @[RegisterRouter.scala:87:24] wire out_f_roready_904 = out_roready_1_758 & out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8846 = out_f_roready_904; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_904 = out_wivalid_1_758 & out_wimask_904; // @[RegisterRouter.scala:87:24] wire out_f_woready_904 = out_woready_1_758 & out_womask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8847 = ~out_rimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8848 = ~out_wimask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8849 = ~out_romask_904; // @[RegisterRouter.scala:87:24] wire _out_T_8850 = ~out_womask_904; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_771 = {hi_20, flags_0_go, _out_prepend_T_771}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8851 = out_prepend_771; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8852 = _out_T_8851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_772 = _out_T_8852; // @[RegisterRouter.scala:87:24] wire out_rimask_905 = |_out_rimask_T_905; // @[RegisterRouter.scala:87:24] wire out_wimask_905 = &_out_wimask_T_905; // @[RegisterRouter.scala:87:24] wire out_romask_905 = |_out_romask_T_905; // @[RegisterRouter.scala:87:24] wire out_womask_905 = &_out_womask_T_905; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_905 = out_rivalid_1_759 & out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8854 = out_f_rivalid_905; // @[RegisterRouter.scala:87:24] wire out_f_roready_905 = out_roready_1_759 & out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8855 = out_f_roready_905; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_905 = out_wivalid_1_759 & out_wimask_905; // @[RegisterRouter.scala:87:24] wire out_f_woready_905 = out_woready_1_759 & out_womask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8856 = ~out_rimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8857 = ~out_wimask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8858 = ~out_romask_905; // @[RegisterRouter.scala:87:24] wire _out_T_8859 = ~out_womask_905; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_772 = {hi_21, flags_0_go, _out_prepend_T_772}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8860 = out_prepend_772; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8861 = _out_T_8860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_773 = _out_T_8861; // @[RegisterRouter.scala:87:24] wire out_rimask_906 = |_out_rimask_T_906; // @[RegisterRouter.scala:87:24] wire out_wimask_906 = &_out_wimask_T_906; // @[RegisterRouter.scala:87:24] wire out_romask_906 = |_out_romask_T_906; // @[RegisterRouter.scala:87:24] wire out_womask_906 = &_out_womask_T_906; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_906 = out_rivalid_1_760 & out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8863 = out_f_rivalid_906; // @[RegisterRouter.scala:87:24] wire out_f_roready_906 = out_roready_1_760 & out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8864 = out_f_roready_906; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_906 = out_wivalid_1_760 & out_wimask_906; // @[RegisterRouter.scala:87:24] wire out_f_woready_906 = out_woready_1_760 & out_womask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8865 = ~out_rimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8866 = ~out_wimask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8867 = ~out_romask_906; // @[RegisterRouter.scala:87:24] wire _out_T_8868 = ~out_womask_906; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_773 = {hi_22, flags_0_go, _out_prepend_T_773}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8869 = out_prepend_773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8870 = _out_T_8869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_774 = _out_T_8870; // @[RegisterRouter.scala:87:24] wire out_rimask_907 = |_out_rimask_T_907; // @[RegisterRouter.scala:87:24] wire out_wimask_907 = &_out_wimask_T_907; // @[RegisterRouter.scala:87:24] wire out_romask_907 = |_out_romask_T_907; // @[RegisterRouter.scala:87:24] wire out_womask_907 = &_out_womask_T_907; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_907 = out_rivalid_1_761 & out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8872 = out_f_rivalid_907; // @[RegisterRouter.scala:87:24] wire out_f_roready_907 = out_roready_1_761 & out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8873 = out_f_roready_907; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_907 = out_wivalid_1_761 & out_wimask_907; // @[RegisterRouter.scala:87:24] wire out_f_woready_907 = out_woready_1_761 & out_womask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8874 = ~out_rimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8875 = ~out_wimask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8876 = ~out_romask_907; // @[RegisterRouter.scala:87:24] wire _out_T_8877 = ~out_womask_907; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_774 = {hi_23, flags_0_go, _out_prepend_T_774}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8878 = out_prepend_774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8879 = _out_T_8878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_775 = _out_T_8879; // @[RegisterRouter.scala:87:24] wire out_rimask_908 = |_out_rimask_T_908; // @[RegisterRouter.scala:87:24] wire out_wimask_908 = &_out_wimask_T_908; // @[RegisterRouter.scala:87:24] wire out_romask_908 = |_out_romask_T_908; // @[RegisterRouter.scala:87:24] wire out_womask_908 = &_out_womask_T_908; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_908 = out_rivalid_1_762 & out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8881 = out_f_rivalid_908; // @[RegisterRouter.scala:87:24] wire out_f_roready_908 = out_roready_1_762 & out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8882 = out_f_roready_908; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_908 = out_wivalid_1_762 & out_wimask_908; // @[RegisterRouter.scala:87:24] wire out_f_woready_908 = out_woready_1_762 & out_womask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8883 = ~out_rimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8884 = ~out_wimask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8885 = ~out_romask_908; // @[RegisterRouter.scala:87:24] wire _out_T_8886 = ~out_womask_908; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_775 = {hi_24, flags_0_go, _out_prepend_T_775}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8887 = out_prepend_775; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8888 = _out_T_8887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_130 = _out_T_8888; // @[MuxLiteral.scala:49:48] wire out_rimask_909 = |_out_rimask_T_909; // @[RegisterRouter.scala:87:24] wire out_wimask_909 = &_out_wimask_T_909; // @[RegisterRouter.scala:87:24] wire out_romask_909 = |_out_romask_T_909; // @[RegisterRouter.scala:87:24] wire out_womask_909 = &_out_womask_T_909; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_909 = out_rivalid_1_763 & out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8890 = out_f_rivalid_909; // @[RegisterRouter.scala:87:24] wire out_f_roready_909 = out_roready_1_763 & out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8891 = out_f_roready_909; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_909 = out_wivalid_1_763 & out_wimask_909; // @[RegisterRouter.scala:87:24] wire out_f_woready_909 = out_woready_1_763 & out_womask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8892 = ~out_rimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8893 = ~out_wimask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8894 = ~out_romask_909; // @[RegisterRouter.scala:87:24] wire _out_T_8895 = ~out_womask_909; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8897 = _out_T_8896; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_776 = _out_T_8897; // @[RegisterRouter.scala:87:24] wire out_rimask_910 = |_out_rimask_T_910; // @[RegisterRouter.scala:87:24] wire out_wimask_910 = &_out_wimask_T_910; // @[RegisterRouter.scala:87:24] wire out_romask_910 = |_out_romask_T_910; // @[RegisterRouter.scala:87:24] wire out_womask_910 = &_out_womask_T_910; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_910 = out_rivalid_1_764 & out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8899 = out_f_rivalid_910; // @[RegisterRouter.scala:87:24] wire out_f_roready_910 = out_roready_1_764 & out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8900 = out_f_roready_910; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_910 = out_wivalid_1_764 & out_wimask_910; // @[RegisterRouter.scala:87:24] wire out_f_woready_910 = out_woready_1_764 & out_womask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8901 = ~out_rimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8902 = ~out_wimask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8903 = ~out_romask_910; // @[RegisterRouter.scala:87:24] wire _out_T_8904 = ~out_womask_910; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_776 = {hi_762, flags_0_go, _out_prepend_T_776}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8905 = out_prepend_776; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8906 = _out_T_8905; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_777 = _out_T_8906; // @[RegisterRouter.scala:87:24] wire out_rimask_911 = |_out_rimask_T_911; // @[RegisterRouter.scala:87:24] wire out_wimask_911 = &_out_wimask_T_911; // @[RegisterRouter.scala:87:24] wire out_romask_911 = |_out_romask_T_911; // @[RegisterRouter.scala:87:24] wire out_womask_911 = &_out_womask_T_911; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_911 = out_rivalid_1_765 & out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8908 = out_f_rivalid_911; // @[RegisterRouter.scala:87:24] wire out_f_roready_911 = out_roready_1_765 & out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8909 = out_f_roready_911; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_911 = out_wivalid_1_765 & out_wimask_911; // @[RegisterRouter.scala:87:24] wire out_f_woready_911 = out_woready_1_765 & out_womask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8910 = ~out_rimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8911 = ~out_wimask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8912 = ~out_romask_911; // @[RegisterRouter.scala:87:24] wire _out_T_8913 = ~out_womask_911; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_777 = {hi_763, flags_0_go, _out_prepend_T_777}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8914 = out_prepend_777; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8915 = _out_T_8914; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_778 = _out_T_8915; // @[RegisterRouter.scala:87:24] wire out_rimask_912 = |_out_rimask_T_912; // @[RegisterRouter.scala:87:24] wire out_wimask_912 = &_out_wimask_T_912; // @[RegisterRouter.scala:87:24] wire out_romask_912 = |_out_romask_T_912; // @[RegisterRouter.scala:87:24] wire out_womask_912 = &_out_womask_T_912; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_912 = out_rivalid_1_766 & out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8917 = out_f_rivalid_912; // @[RegisterRouter.scala:87:24] wire out_f_roready_912 = out_roready_1_766 & out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8918 = out_f_roready_912; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_912 = out_wivalid_1_766 & out_wimask_912; // @[RegisterRouter.scala:87:24] wire out_f_woready_912 = out_woready_1_766 & out_womask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8919 = ~out_rimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8920 = ~out_wimask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8921 = ~out_romask_912; // @[RegisterRouter.scala:87:24] wire _out_T_8922 = ~out_womask_912; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_778 = {hi_764, flags_0_go, _out_prepend_T_778}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8923 = out_prepend_778; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8924 = _out_T_8923; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_779 = _out_T_8924; // @[RegisterRouter.scala:87:24] wire out_rimask_913 = |_out_rimask_T_913; // @[RegisterRouter.scala:87:24] wire out_wimask_913 = &_out_wimask_T_913; // @[RegisterRouter.scala:87:24] wire out_romask_913 = |_out_romask_T_913; // @[RegisterRouter.scala:87:24] wire out_womask_913 = &_out_womask_T_913; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_913 = out_rivalid_1_767 & out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8926 = out_f_rivalid_913; // @[RegisterRouter.scala:87:24] wire out_f_roready_913 = out_roready_1_767 & out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8927 = out_f_roready_913; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_913 = out_wivalid_1_767 & out_wimask_913; // @[RegisterRouter.scala:87:24] wire out_f_woready_913 = out_woready_1_767 & out_womask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8928 = ~out_rimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8929 = ~out_wimask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8930 = ~out_romask_913; // @[RegisterRouter.scala:87:24] wire _out_T_8931 = ~out_womask_913; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_779 = {hi_765, flags_0_go, _out_prepend_T_779}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8932 = out_prepend_779; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_8933 = _out_T_8932; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_780 = _out_T_8933; // @[RegisterRouter.scala:87:24] wire out_rimask_914 = |_out_rimask_T_914; // @[RegisterRouter.scala:87:24] wire out_wimask_914 = &_out_wimask_T_914; // @[RegisterRouter.scala:87:24] wire out_romask_914 = |_out_romask_T_914; // @[RegisterRouter.scala:87:24] wire out_womask_914 = &_out_womask_T_914; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_914 = out_rivalid_1_768 & out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8935 = out_f_rivalid_914; // @[RegisterRouter.scala:87:24] wire out_f_roready_914 = out_roready_1_768 & out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8936 = out_f_roready_914; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_914 = out_wivalid_1_768 & out_wimask_914; // @[RegisterRouter.scala:87:24] wire out_f_woready_914 = out_woready_1_768 & out_womask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8937 = ~out_rimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8938 = ~out_wimask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8939 = ~out_romask_914; // @[RegisterRouter.scala:87:24] wire _out_T_8940 = ~out_womask_914; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_780 = {hi_766, flags_0_go, _out_prepend_T_780}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8941 = out_prepend_780; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_8942 = _out_T_8941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_781 = _out_T_8942; // @[RegisterRouter.scala:87:24] wire out_rimask_915 = |_out_rimask_T_915; // @[RegisterRouter.scala:87:24] wire out_wimask_915 = &_out_wimask_T_915; // @[RegisterRouter.scala:87:24] wire out_romask_915 = |_out_romask_T_915; // @[RegisterRouter.scala:87:24] wire out_womask_915 = &_out_womask_T_915; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_915 = out_rivalid_1_769 & out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8944 = out_f_rivalid_915; // @[RegisterRouter.scala:87:24] wire out_f_roready_915 = out_roready_1_769 & out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8945 = out_f_roready_915; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_915 = out_wivalid_1_769 & out_wimask_915; // @[RegisterRouter.scala:87:24] wire out_f_woready_915 = out_woready_1_769 & out_womask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8946 = ~out_rimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8947 = ~out_wimask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8948 = ~out_romask_915; // @[RegisterRouter.scala:87:24] wire _out_T_8949 = ~out_womask_915; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_781 = {hi_767, flags_0_go, _out_prepend_T_781}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8950 = out_prepend_781; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_8951 = _out_T_8950; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_782 = _out_T_8951; // @[RegisterRouter.scala:87:24] wire out_rimask_916 = |_out_rimask_T_916; // @[RegisterRouter.scala:87:24] wire out_wimask_916 = &_out_wimask_T_916; // @[RegisterRouter.scala:87:24] wire out_romask_916 = |_out_romask_T_916; // @[RegisterRouter.scala:87:24] wire out_womask_916 = &_out_womask_T_916; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_916 = out_rivalid_1_770 & out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8953 = out_f_rivalid_916; // @[RegisterRouter.scala:87:24] wire out_f_roready_916 = out_roready_1_770 & out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8954 = out_f_roready_916; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_916 = out_wivalid_1_770 & out_wimask_916; // @[RegisterRouter.scala:87:24] wire out_f_woready_916 = out_woready_1_770 & out_womask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8955 = ~out_rimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8956 = ~out_wimask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8957 = ~out_romask_916; // @[RegisterRouter.scala:87:24] wire _out_T_8958 = ~out_womask_916; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_782 = {hi_768, flags_0_go, _out_prepend_T_782}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8959 = out_prepend_782; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_8960 = _out_T_8959; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_223 = _out_T_8960; // @[MuxLiteral.scala:49:48] wire out_rimask_917 = |_out_rimask_T_917; // @[RegisterRouter.scala:87:24] wire out_wimask_917 = &_out_wimask_T_917; // @[RegisterRouter.scala:87:24] wire out_romask_917 = |_out_romask_T_917; // @[RegisterRouter.scala:87:24] wire out_womask_917 = &_out_womask_T_917; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_917 = out_rivalid_1_771 & out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8962 = out_f_rivalid_917; // @[RegisterRouter.scala:87:24] wire out_f_roready_917 = out_roready_1_771 & out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8963 = out_f_roready_917; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_917 = out_wivalid_1_771 & out_wimask_917; // @[RegisterRouter.scala:87:24] wire out_f_woready_917 = out_woready_1_771 & out_womask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8964 = ~out_rimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8965 = ~out_wimask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8966 = ~out_romask_917; // @[RegisterRouter.scala:87:24] wire _out_T_8967 = ~out_womask_917; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8969 = _out_T_8968; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_783 = _out_T_8969; // @[RegisterRouter.scala:87:24] wire out_rimask_918 = |_out_rimask_T_918; // @[RegisterRouter.scala:87:24] wire out_wimask_918 = &_out_wimask_T_918; // @[RegisterRouter.scala:87:24] wire out_romask_918 = |_out_romask_T_918; // @[RegisterRouter.scala:87:24] wire out_womask_918 = &_out_womask_T_918; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_918 = out_rivalid_1_772 & out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8971 = out_f_rivalid_918; // @[RegisterRouter.scala:87:24] wire out_f_roready_918 = out_roready_1_772 & out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8972 = out_f_roready_918; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_918 = out_wivalid_1_772 & out_wimask_918; // @[RegisterRouter.scala:87:24] wire out_f_woready_918 = out_woready_1_772 & out_womask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8973 = ~out_rimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8974 = ~out_wimask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8975 = ~out_romask_918; // @[RegisterRouter.scala:87:24] wire _out_T_8976 = ~out_womask_918; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_783 = {hi_58, flags_0_go, _out_prepend_T_783}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8977 = out_prepend_783; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_8978 = _out_T_8977; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_784 = _out_T_8978; // @[RegisterRouter.scala:87:24] wire out_rimask_919 = |_out_rimask_T_919; // @[RegisterRouter.scala:87:24] wire out_wimask_919 = &_out_wimask_T_919; // @[RegisterRouter.scala:87:24] wire out_romask_919 = |_out_romask_T_919; // @[RegisterRouter.scala:87:24] wire out_womask_919 = &_out_womask_T_919; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_919 = out_rivalid_1_773 & out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8980 = out_f_rivalid_919; // @[RegisterRouter.scala:87:24] wire out_f_roready_919 = out_roready_1_773 & out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8981 = out_f_roready_919; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_919 = out_wivalid_1_773 & out_wimask_919; // @[RegisterRouter.scala:87:24] wire out_f_woready_919 = out_woready_1_773 & out_womask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8982 = ~out_rimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8983 = ~out_wimask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8984 = ~out_romask_919; // @[RegisterRouter.scala:87:24] wire _out_T_8985 = ~out_womask_919; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_784 = {hi_59, flags_0_go, _out_prepend_T_784}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8986 = out_prepend_784; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_8987 = _out_T_8986; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_785 = _out_T_8987; // @[RegisterRouter.scala:87:24] wire out_rimask_920 = |_out_rimask_T_920; // @[RegisterRouter.scala:87:24] wire out_wimask_920 = &_out_wimask_T_920; // @[RegisterRouter.scala:87:24] wire out_romask_920 = |_out_romask_T_920; // @[RegisterRouter.scala:87:24] wire out_womask_920 = &_out_womask_T_920; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_920 = out_rivalid_1_774 & out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8989 = out_f_rivalid_920; // @[RegisterRouter.scala:87:24] wire out_f_roready_920 = out_roready_1_774 & out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8990 = out_f_roready_920; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_920 = out_wivalid_1_774 & out_wimask_920; // @[RegisterRouter.scala:87:24] wire out_f_woready_920 = out_woready_1_774 & out_womask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8991 = ~out_rimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8992 = ~out_wimask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8993 = ~out_romask_920; // @[RegisterRouter.scala:87:24] wire _out_T_8994 = ~out_womask_920; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_785 = {hi_60, flags_0_go, _out_prepend_T_785}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8995 = out_prepend_785; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_8996 = _out_T_8995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_786 = _out_T_8996; // @[RegisterRouter.scala:87:24] wire out_rimask_921 = |_out_rimask_T_921; // @[RegisterRouter.scala:87:24] wire out_wimask_921 = &_out_wimask_T_921; // @[RegisterRouter.scala:87:24] wire out_romask_921 = |_out_romask_T_921; // @[RegisterRouter.scala:87:24] wire out_womask_921 = &_out_womask_T_921; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_921 = out_rivalid_1_775 & out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8998 = out_f_rivalid_921; // @[RegisterRouter.scala:87:24] wire out_f_roready_921 = out_roready_1_775 & out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_8999 = out_f_roready_921; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_921 = out_wivalid_1_775 & out_wimask_921; // @[RegisterRouter.scala:87:24] wire out_f_woready_921 = out_woready_1_775 & out_womask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9000 = ~out_rimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9001 = ~out_wimask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9002 = ~out_romask_921; // @[RegisterRouter.scala:87:24] wire _out_T_9003 = ~out_womask_921; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_786 = {hi_61, flags_0_go, _out_prepend_T_786}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9004 = out_prepend_786; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9005 = _out_T_9004; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_787 = _out_T_9005; // @[RegisterRouter.scala:87:24] wire out_rimask_922 = |_out_rimask_T_922; // @[RegisterRouter.scala:87:24] wire out_wimask_922 = &_out_wimask_T_922; // @[RegisterRouter.scala:87:24] wire out_romask_922 = |_out_romask_T_922; // @[RegisterRouter.scala:87:24] wire out_womask_922 = &_out_womask_T_922; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_922 = out_rivalid_1_776 & out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9007 = out_f_rivalid_922; // @[RegisterRouter.scala:87:24] wire out_f_roready_922 = out_roready_1_776 & out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9008 = out_f_roready_922; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_922 = out_wivalid_1_776 & out_wimask_922; // @[RegisterRouter.scala:87:24] wire out_f_woready_922 = out_woready_1_776 & out_womask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9009 = ~out_rimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9010 = ~out_wimask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9011 = ~out_romask_922; // @[RegisterRouter.scala:87:24] wire _out_T_9012 = ~out_womask_922; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_787 = {hi_62, flags_0_go, _out_prepend_T_787}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9013 = out_prepend_787; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9014 = _out_T_9013; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_788 = _out_T_9014; // @[RegisterRouter.scala:87:24] wire out_rimask_923 = |_out_rimask_T_923; // @[RegisterRouter.scala:87:24] wire out_wimask_923 = &_out_wimask_T_923; // @[RegisterRouter.scala:87:24] wire out_romask_923 = |_out_romask_T_923; // @[RegisterRouter.scala:87:24] wire out_womask_923 = &_out_womask_T_923; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_923 = out_rivalid_1_777 & out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9016 = out_f_rivalid_923; // @[RegisterRouter.scala:87:24] wire out_f_roready_923 = out_roready_1_777 & out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9017 = out_f_roready_923; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_923 = out_wivalid_1_777 & out_wimask_923; // @[RegisterRouter.scala:87:24] wire out_f_woready_923 = out_woready_1_777 & out_womask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9018 = ~out_rimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9019 = ~out_wimask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9020 = ~out_romask_923; // @[RegisterRouter.scala:87:24] wire _out_T_9021 = ~out_womask_923; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_788 = {hi_63, flags_0_go, _out_prepend_T_788}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9022 = out_prepend_788; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9023 = _out_T_9022; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_789 = _out_T_9023; // @[RegisterRouter.scala:87:24] wire out_rimask_924 = |_out_rimask_T_924; // @[RegisterRouter.scala:87:24] wire out_wimask_924 = &_out_wimask_T_924; // @[RegisterRouter.scala:87:24] wire out_romask_924 = |_out_romask_T_924; // @[RegisterRouter.scala:87:24] wire out_womask_924 = &_out_womask_T_924; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_924 = out_rivalid_1_778 & out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9025 = out_f_rivalid_924; // @[RegisterRouter.scala:87:24] wire out_f_roready_924 = out_roready_1_778 & out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9026 = out_f_roready_924; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_924 = out_wivalid_1_778 & out_wimask_924; // @[RegisterRouter.scala:87:24] wire out_f_woready_924 = out_woready_1_778 & out_womask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9027 = ~out_rimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9028 = ~out_wimask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9029 = ~out_romask_924; // @[RegisterRouter.scala:87:24] wire _out_T_9030 = ~out_womask_924; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_789 = {hi_64, flags_0_go, _out_prepend_T_789}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9031 = out_prepend_789; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9032 = _out_T_9031; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_135 = _out_T_9032; // @[MuxLiteral.scala:49:48] wire out_rimask_925 = |_out_rimask_T_925; // @[RegisterRouter.scala:87:24] wire out_wimask_925 = &_out_wimask_T_925; // @[RegisterRouter.scala:87:24] wire out_romask_925 = |_out_romask_T_925; // @[RegisterRouter.scala:87:24] wire out_womask_925 = &_out_womask_T_925; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_925 = out_rivalid_1_779 & out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9034 = out_f_rivalid_925; // @[RegisterRouter.scala:87:24] wire out_f_roready_925 = out_roready_1_779 & out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9035 = out_f_roready_925; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_925 = out_wivalid_1_779 & out_wimask_925; // @[RegisterRouter.scala:87:24] wire out_f_woready_925 = out_woready_1_779 & out_womask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9036 = ~out_rimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9037 = ~out_wimask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9038 = ~out_romask_925; // @[RegisterRouter.scala:87:24] wire _out_T_9039 = ~out_womask_925; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9041 = _out_T_9040; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_790 = _out_T_9041; // @[RegisterRouter.scala:87:24] wire out_rimask_926 = |_out_rimask_T_926; // @[RegisterRouter.scala:87:24] wire out_wimask_926 = &_out_wimask_T_926; // @[RegisterRouter.scala:87:24] wire out_romask_926 = |_out_romask_T_926; // @[RegisterRouter.scala:87:24] wire out_womask_926 = &_out_womask_T_926; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_926 = out_rivalid_1_780 & out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9043 = out_f_rivalid_926; // @[RegisterRouter.scala:87:24] wire out_f_roready_926 = out_roready_1_780 & out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9044 = out_f_roready_926; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_926 = out_wivalid_1_780 & out_wimask_926; // @[RegisterRouter.scala:87:24] wire out_f_woready_926 = out_woready_1_780 & out_womask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9045 = ~out_rimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9046 = ~out_wimask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9047 = ~out_romask_926; // @[RegisterRouter.scala:87:24] wire _out_T_9048 = ~out_womask_926; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_790 = {hi_786, flags_0_go, _out_prepend_T_790}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9049 = out_prepend_790; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9050 = _out_T_9049; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_791 = _out_T_9050; // @[RegisterRouter.scala:87:24] wire out_rimask_927 = |_out_rimask_T_927; // @[RegisterRouter.scala:87:24] wire out_wimask_927 = &_out_wimask_T_927; // @[RegisterRouter.scala:87:24] wire out_romask_927 = |_out_romask_T_927; // @[RegisterRouter.scala:87:24] wire out_womask_927 = &_out_womask_T_927; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_927 = out_rivalid_1_781 & out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9052 = out_f_rivalid_927; // @[RegisterRouter.scala:87:24] wire out_f_roready_927 = out_roready_1_781 & out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9053 = out_f_roready_927; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_927 = out_wivalid_1_781 & out_wimask_927; // @[RegisterRouter.scala:87:24] wire out_f_woready_927 = out_woready_1_781 & out_womask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9054 = ~out_rimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9055 = ~out_wimask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9056 = ~out_romask_927; // @[RegisterRouter.scala:87:24] wire _out_T_9057 = ~out_womask_927; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_791 = {hi_787, flags_0_go, _out_prepend_T_791}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9058 = out_prepend_791; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9059 = _out_T_9058; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_792 = _out_T_9059; // @[RegisterRouter.scala:87:24] wire out_rimask_928 = |_out_rimask_T_928; // @[RegisterRouter.scala:87:24] wire out_wimask_928 = &_out_wimask_T_928; // @[RegisterRouter.scala:87:24] wire out_romask_928 = |_out_romask_T_928; // @[RegisterRouter.scala:87:24] wire out_womask_928 = &_out_womask_T_928; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_928 = out_rivalid_1_782 & out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9061 = out_f_rivalid_928; // @[RegisterRouter.scala:87:24] wire out_f_roready_928 = out_roready_1_782 & out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9062 = out_f_roready_928; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_928 = out_wivalid_1_782 & out_wimask_928; // @[RegisterRouter.scala:87:24] wire out_f_woready_928 = out_woready_1_782 & out_womask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9063 = ~out_rimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9064 = ~out_wimask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9065 = ~out_romask_928; // @[RegisterRouter.scala:87:24] wire _out_T_9066 = ~out_womask_928; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_792 = {hi_788, flags_0_go, _out_prepend_T_792}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9067 = out_prepend_792; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9068 = _out_T_9067; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_793 = _out_T_9068; // @[RegisterRouter.scala:87:24] wire out_rimask_929 = |_out_rimask_T_929; // @[RegisterRouter.scala:87:24] wire out_wimask_929 = &_out_wimask_T_929; // @[RegisterRouter.scala:87:24] wire out_romask_929 = |_out_romask_T_929; // @[RegisterRouter.scala:87:24] wire out_womask_929 = &_out_womask_T_929; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_929 = out_rivalid_1_783 & out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9070 = out_f_rivalid_929; // @[RegisterRouter.scala:87:24] wire out_f_roready_929 = out_roready_1_783 & out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9071 = out_f_roready_929; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_929 = out_wivalid_1_783 & out_wimask_929; // @[RegisterRouter.scala:87:24] wire out_f_woready_929 = out_woready_1_783 & out_womask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9072 = ~out_rimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9073 = ~out_wimask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9074 = ~out_romask_929; // @[RegisterRouter.scala:87:24] wire _out_T_9075 = ~out_womask_929; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_793 = {hi_789, flags_0_go, _out_prepend_T_793}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9076 = out_prepend_793; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9077 = _out_T_9076; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_794 = _out_T_9077; // @[RegisterRouter.scala:87:24] wire out_rimask_930 = |_out_rimask_T_930; // @[RegisterRouter.scala:87:24] wire out_wimask_930 = &_out_wimask_T_930; // @[RegisterRouter.scala:87:24] wire out_romask_930 = |_out_romask_T_930; // @[RegisterRouter.scala:87:24] wire out_womask_930 = &_out_womask_T_930; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_930 = out_rivalid_1_784 & out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9079 = out_f_rivalid_930; // @[RegisterRouter.scala:87:24] wire out_f_roready_930 = out_roready_1_784 & out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9080 = out_f_roready_930; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_930 = out_wivalid_1_784 & out_wimask_930; // @[RegisterRouter.scala:87:24] wire out_f_woready_930 = out_woready_1_784 & out_womask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9081 = ~out_rimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9082 = ~out_wimask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9083 = ~out_romask_930; // @[RegisterRouter.scala:87:24] wire _out_T_9084 = ~out_womask_930; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_794 = {hi_790, flags_0_go, _out_prepend_T_794}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9085 = out_prepend_794; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9086 = _out_T_9085; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_795 = _out_T_9086; // @[RegisterRouter.scala:87:24] wire out_rimask_931 = |_out_rimask_T_931; // @[RegisterRouter.scala:87:24] wire out_wimask_931 = &_out_wimask_T_931; // @[RegisterRouter.scala:87:24] wire out_romask_931 = |_out_romask_T_931; // @[RegisterRouter.scala:87:24] wire out_womask_931 = &_out_womask_T_931; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_931 = out_rivalid_1_785 & out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9088 = out_f_rivalid_931; // @[RegisterRouter.scala:87:24] wire out_f_roready_931 = out_roready_1_785 & out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9089 = out_f_roready_931; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_931 = out_wivalid_1_785 & out_wimask_931; // @[RegisterRouter.scala:87:24] wire out_f_woready_931 = out_woready_1_785 & out_womask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9090 = ~out_rimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9091 = ~out_wimask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9092 = ~out_romask_931; // @[RegisterRouter.scala:87:24] wire _out_T_9093 = ~out_womask_931; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_795 = {hi_791, flags_0_go, _out_prepend_T_795}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9094 = out_prepend_795; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9095 = _out_T_9094; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_796 = _out_T_9095; // @[RegisterRouter.scala:87:24] wire out_rimask_932 = |_out_rimask_T_932; // @[RegisterRouter.scala:87:24] wire out_wimask_932 = &_out_wimask_T_932; // @[RegisterRouter.scala:87:24] wire out_romask_932 = |_out_romask_T_932; // @[RegisterRouter.scala:87:24] wire out_womask_932 = &_out_womask_T_932; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_932 = out_rivalid_1_786 & out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9097 = out_f_rivalid_932; // @[RegisterRouter.scala:87:24] wire out_f_roready_932 = out_roready_1_786 & out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9098 = out_f_roready_932; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_932 = out_wivalid_1_786 & out_wimask_932; // @[RegisterRouter.scala:87:24] wire out_f_woready_932 = out_woready_1_786 & out_womask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9099 = ~out_rimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9100 = ~out_wimask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9101 = ~out_romask_932; // @[RegisterRouter.scala:87:24] wire _out_T_9102 = ~out_womask_932; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_796 = {hi_792, flags_0_go, _out_prepend_T_796}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9103 = out_prepend_796; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9104 = _out_T_9103; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_226 = _out_T_9104; // @[MuxLiteral.scala:49:48] wire out_rimask_933 = |_out_rimask_T_933; // @[RegisterRouter.scala:87:24] wire out_wimask_933 = &_out_wimask_T_933; // @[RegisterRouter.scala:87:24] wire out_romask_933 = |_out_romask_T_933; // @[RegisterRouter.scala:87:24] wire out_womask_933 = &_out_womask_T_933; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_933 = out_rivalid_1_787 & out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9106 = out_f_rivalid_933; // @[RegisterRouter.scala:87:24] wire out_f_roready_933 = out_roready_1_787 & out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9107 = out_f_roready_933; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_933 = out_wivalid_1_787 & out_wimask_933; // @[RegisterRouter.scala:87:24] wire out_f_woready_933 = out_woready_1_787 & out_womask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9108 = ~out_rimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9109 = ~out_wimask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9110 = ~out_romask_933; // @[RegisterRouter.scala:87:24] wire _out_T_9111 = ~out_womask_933; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9113 = _out_T_9112; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_797 = _out_T_9113; // @[RegisterRouter.scala:87:24] wire out_rimask_934 = |_out_rimask_T_934; // @[RegisterRouter.scala:87:24] wire out_wimask_934 = &_out_wimask_T_934; // @[RegisterRouter.scala:87:24] wire out_romask_934 = |_out_romask_T_934; // @[RegisterRouter.scala:87:24] wire out_womask_934 = &_out_womask_T_934; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_934 = out_rivalid_1_788 & out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9115 = out_f_rivalid_934; // @[RegisterRouter.scala:87:24] wire out_f_roready_934 = out_roready_1_788 & out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9116 = out_f_roready_934; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_934 = out_wivalid_1_788 & out_wimask_934; // @[RegisterRouter.scala:87:24] wire out_f_woready_934 = out_woready_1_788 & out_womask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9117 = ~out_rimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9118 = ~out_wimask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9119 = ~out_romask_934; // @[RegisterRouter.scala:87:24] wire _out_T_9120 = ~out_womask_934; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_797 = {hi_906, flags_0_go, _out_prepend_T_797}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9121 = out_prepend_797; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9122 = _out_T_9121; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_798 = _out_T_9122; // @[RegisterRouter.scala:87:24] wire out_rimask_935 = |_out_rimask_T_935; // @[RegisterRouter.scala:87:24] wire out_wimask_935 = &_out_wimask_T_935; // @[RegisterRouter.scala:87:24] wire out_romask_935 = |_out_romask_T_935; // @[RegisterRouter.scala:87:24] wire out_womask_935 = &_out_womask_T_935; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_935 = out_rivalid_1_789 & out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9124 = out_f_rivalid_935; // @[RegisterRouter.scala:87:24] wire out_f_roready_935 = out_roready_1_789 & out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9125 = out_f_roready_935; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_935 = out_wivalid_1_789 & out_wimask_935; // @[RegisterRouter.scala:87:24] wire out_f_woready_935 = out_woready_1_789 & out_womask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9126 = ~out_rimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9127 = ~out_wimask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9128 = ~out_romask_935; // @[RegisterRouter.scala:87:24] wire _out_T_9129 = ~out_womask_935; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_798 = {hi_907, flags_0_go, _out_prepend_T_798}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9130 = out_prepend_798; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9131 = _out_T_9130; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_799 = _out_T_9131; // @[RegisterRouter.scala:87:24] wire out_rimask_936 = |_out_rimask_T_936; // @[RegisterRouter.scala:87:24] wire out_wimask_936 = &_out_wimask_T_936; // @[RegisterRouter.scala:87:24] wire out_romask_936 = |_out_romask_T_936; // @[RegisterRouter.scala:87:24] wire out_womask_936 = &_out_womask_T_936; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_936 = out_rivalid_1_790 & out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9133 = out_f_rivalid_936; // @[RegisterRouter.scala:87:24] wire out_f_roready_936 = out_roready_1_790 & out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9134 = out_f_roready_936; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_936 = out_wivalid_1_790 & out_wimask_936; // @[RegisterRouter.scala:87:24] wire out_f_woready_936 = out_woready_1_790 & out_womask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9135 = ~out_rimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9136 = ~out_wimask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9137 = ~out_romask_936; // @[RegisterRouter.scala:87:24] wire _out_T_9138 = ~out_womask_936; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_799 = {hi_908, flags_0_go, _out_prepend_T_799}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9139 = out_prepend_799; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9140 = _out_T_9139; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_800 = _out_T_9140; // @[RegisterRouter.scala:87:24] wire out_rimask_937 = |_out_rimask_T_937; // @[RegisterRouter.scala:87:24] wire out_wimask_937 = &_out_wimask_T_937; // @[RegisterRouter.scala:87:24] wire out_romask_937 = |_out_romask_T_937; // @[RegisterRouter.scala:87:24] wire out_womask_937 = &_out_womask_T_937; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_937 = out_rivalid_1_791 & out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9142 = out_f_rivalid_937; // @[RegisterRouter.scala:87:24] wire out_f_roready_937 = out_roready_1_791 & out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9143 = out_f_roready_937; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_937 = out_wivalid_1_791 & out_wimask_937; // @[RegisterRouter.scala:87:24] wire out_f_woready_937 = out_woready_1_791 & out_womask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9144 = ~out_rimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9145 = ~out_wimask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9146 = ~out_romask_937; // @[RegisterRouter.scala:87:24] wire _out_T_9147 = ~out_womask_937; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_800 = {hi_909, flags_0_go, _out_prepend_T_800}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9148 = out_prepend_800; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9149 = _out_T_9148; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_801 = _out_T_9149; // @[RegisterRouter.scala:87:24] wire out_rimask_938 = |_out_rimask_T_938; // @[RegisterRouter.scala:87:24] wire out_wimask_938 = &_out_wimask_T_938; // @[RegisterRouter.scala:87:24] wire out_romask_938 = |_out_romask_T_938; // @[RegisterRouter.scala:87:24] wire out_womask_938 = &_out_womask_T_938; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_938 = out_rivalid_1_792 & out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9151 = out_f_rivalid_938; // @[RegisterRouter.scala:87:24] wire out_f_roready_938 = out_roready_1_792 & out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9152 = out_f_roready_938; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_938 = out_wivalid_1_792 & out_wimask_938; // @[RegisterRouter.scala:87:24] wire out_f_woready_938 = out_woready_1_792 & out_womask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9153 = ~out_rimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9154 = ~out_wimask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9155 = ~out_romask_938; // @[RegisterRouter.scala:87:24] wire _out_T_9156 = ~out_womask_938; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_801 = {hi_910, flags_0_go, _out_prepend_T_801}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9157 = out_prepend_801; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9158 = _out_T_9157; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_802 = _out_T_9158; // @[RegisterRouter.scala:87:24] wire out_rimask_939 = |_out_rimask_T_939; // @[RegisterRouter.scala:87:24] wire out_wimask_939 = &_out_wimask_T_939; // @[RegisterRouter.scala:87:24] wire out_romask_939 = |_out_romask_T_939; // @[RegisterRouter.scala:87:24] wire out_womask_939 = &_out_womask_T_939; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_939 = out_rivalid_1_793 & out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9160 = out_f_rivalid_939; // @[RegisterRouter.scala:87:24] wire out_f_roready_939 = out_roready_1_793 & out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9161 = out_f_roready_939; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_939 = out_wivalid_1_793 & out_wimask_939; // @[RegisterRouter.scala:87:24] wire out_f_woready_939 = out_woready_1_793 & out_womask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9162 = ~out_rimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9163 = ~out_wimask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9164 = ~out_romask_939; // @[RegisterRouter.scala:87:24] wire _out_T_9165 = ~out_womask_939; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_802 = {hi_911, flags_0_go, _out_prepend_T_802}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9166 = out_prepend_802; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9167 = _out_T_9166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_803 = _out_T_9167; // @[RegisterRouter.scala:87:24] wire out_rimask_940 = |_out_rimask_T_940; // @[RegisterRouter.scala:87:24] wire out_wimask_940 = &_out_wimask_T_940; // @[RegisterRouter.scala:87:24] wire out_romask_940 = |_out_romask_T_940; // @[RegisterRouter.scala:87:24] wire out_womask_940 = &_out_womask_T_940; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_940 = out_rivalid_1_794 & out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9169 = out_f_rivalid_940; // @[RegisterRouter.scala:87:24] wire out_f_roready_940 = out_roready_1_794 & out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9170 = out_f_roready_940; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_940 = out_wivalid_1_794 & out_wimask_940; // @[RegisterRouter.scala:87:24] wire out_f_woready_940 = out_woready_1_794 & out_womask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9171 = ~out_rimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9172 = ~out_wimask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9173 = ~out_romask_940; // @[RegisterRouter.scala:87:24] wire _out_T_9174 = ~out_womask_940; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_803 = {hi_912, flags_0_go, _out_prepend_T_803}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9175 = out_prepend_803; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9176 = _out_T_9175; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_241 = _out_T_9176; // @[MuxLiteral.scala:49:48] wire out_rimask_941 = |_out_rimask_T_941; // @[RegisterRouter.scala:87:24] wire out_wimask_941 = &_out_wimask_T_941; // @[RegisterRouter.scala:87:24] wire out_romask_941 = |_out_romask_T_941; // @[RegisterRouter.scala:87:24] wire out_womask_941 = &_out_womask_T_941; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_941 = out_rivalid_1_795 & out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9178 = out_f_rivalid_941; // @[RegisterRouter.scala:87:24] wire out_f_roready_941 = out_roready_1_795 & out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9179 = out_f_roready_941; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_941 = out_wivalid_1_795 & out_wimask_941; // @[RegisterRouter.scala:87:24] wire out_f_woready_941 = out_woready_1_795 & out_womask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9180 = ~out_rimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9181 = ~out_wimask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9182 = ~out_romask_941; // @[RegisterRouter.scala:87:24] wire _out_T_9183 = ~out_womask_941; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9185 = _out_T_9184; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_804 = _out_T_9185; // @[RegisterRouter.scala:87:24] wire out_rimask_942 = |_out_rimask_T_942; // @[RegisterRouter.scala:87:24] wire out_wimask_942 = &_out_wimask_T_942; // @[RegisterRouter.scala:87:24] wire out_romask_942 = |_out_romask_T_942; // @[RegisterRouter.scala:87:24] wire out_womask_942 = &_out_womask_T_942; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_942 = out_rivalid_1_796 & out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9187 = out_f_rivalid_942; // @[RegisterRouter.scala:87:24] wire out_f_roready_942 = out_roready_1_796 & out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9188 = out_f_roready_942; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_942 = out_wivalid_1_796 & out_wimask_942; // @[RegisterRouter.scala:87:24] wire out_f_woready_942 = out_woready_1_796 & out_womask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9189 = ~out_rimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9190 = ~out_wimask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9191 = ~out_romask_942; // @[RegisterRouter.scala:87:24] wire _out_T_9192 = ~out_womask_942; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_804 = {hi_314, flags_0_go, _out_prepend_T_804}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9193 = out_prepend_804; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9194 = _out_T_9193; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_805 = _out_T_9194; // @[RegisterRouter.scala:87:24] wire out_rimask_943 = |_out_rimask_T_943; // @[RegisterRouter.scala:87:24] wire out_wimask_943 = &_out_wimask_T_943; // @[RegisterRouter.scala:87:24] wire out_romask_943 = |_out_romask_T_943; // @[RegisterRouter.scala:87:24] wire out_womask_943 = &_out_womask_T_943; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_943 = out_rivalid_1_797 & out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9196 = out_f_rivalid_943; // @[RegisterRouter.scala:87:24] wire out_f_roready_943 = out_roready_1_797 & out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9197 = out_f_roready_943; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_943 = out_wivalid_1_797 & out_wimask_943; // @[RegisterRouter.scala:87:24] wire out_f_woready_943 = out_woready_1_797 & out_womask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9198 = ~out_rimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9199 = ~out_wimask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9200 = ~out_romask_943; // @[RegisterRouter.scala:87:24] wire _out_T_9201 = ~out_womask_943; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_805 = {hi_315, flags_0_go, _out_prepend_T_805}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9202 = out_prepend_805; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9203 = _out_T_9202; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_806 = _out_T_9203; // @[RegisterRouter.scala:87:24] wire out_rimask_944 = |_out_rimask_T_944; // @[RegisterRouter.scala:87:24] wire out_wimask_944 = &_out_wimask_T_944; // @[RegisterRouter.scala:87:24] wire out_romask_944 = |_out_romask_T_944; // @[RegisterRouter.scala:87:24] wire out_womask_944 = &_out_womask_T_944; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_944 = out_rivalid_1_798 & out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9205 = out_f_rivalid_944; // @[RegisterRouter.scala:87:24] wire out_f_roready_944 = out_roready_1_798 & out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9206 = out_f_roready_944; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_944 = out_wivalid_1_798 & out_wimask_944; // @[RegisterRouter.scala:87:24] wire out_f_woready_944 = out_woready_1_798 & out_womask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9207 = ~out_rimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9208 = ~out_wimask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9209 = ~out_romask_944; // @[RegisterRouter.scala:87:24] wire _out_T_9210 = ~out_womask_944; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_806 = {hi_316, flags_0_go, _out_prepend_T_806}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9211 = out_prepend_806; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9212 = _out_T_9211; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_807 = _out_T_9212; // @[RegisterRouter.scala:87:24] wire out_rimask_945 = |_out_rimask_T_945; // @[RegisterRouter.scala:87:24] wire out_wimask_945 = &_out_wimask_T_945; // @[RegisterRouter.scala:87:24] wire out_romask_945 = |_out_romask_T_945; // @[RegisterRouter.scala:87:24] wire out_womask_945 = &_out_womask_T_945; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_945 = out_rivalid_1_799 & out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9214 = out_f_rivalid_945; // @[RegisterRouter.scala:87:24] wire out_f_roready_945 = out_roready_1_799 & out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9215 = out_f_roready_945; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_945 = out_wivalid_1_799 & out_wimask_945; // @[RegisterRouter.scala:87:24] wire out_f_woready_945 = out_woready_1_799 & out_womask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9216 = ~out_rimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9217 = ~out_wimask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9218 = ~out_romask_945; // @[RegisterRouter.scala:87:24] wire _out_T_9219 = ~out_womask_945; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_807 = {hi_317, flags_0_go, _out_prepend_T_807}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9220 = out_prepend_807; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9221 = _out_T_9220; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_808 = _out_T_9221; // @[RegisterRouter.scala:87:24] wire out_rimask_946 = |_out_rimask_T_946; // @[RegisterRouter.scala:87:24] wire out_wimask_946 = &_out_wimask_T_946; // @[RegisterRouter.scala:87:24] wire out_romask_946 = |_out_romask_T_946; // @[RegisterRouter.scala:87:24] wire out_womask_946 = &_out_womask_T_946; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_946 = out_rivalid_1_800 & out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9223 = out_f_rivalid_946; // @[RegisterRouter.scala:87:24] wire out_f_roready_946 = out_roready_1_800 & out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9224 = out_f_roready_946; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_946 = out_wivalid_1_800 & out_wimask_946; // @[RegisterRouter.scala:87:24] wire out_f_woready_946 = out_woready_1_800 & out_womask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9225 = ~out_rimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9226 = ~out_wimask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9227 = ~out_romask_946; // @[RegisterRouter.scala:87:24] wire _out_T_9228 = ~out_womask_946; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_808 = {hi_318, flags_0_go, _out_prepend_T_808}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9229 = out_prepend_808; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9230 = _out_T_9229; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_809 = _out_T_9230; // @[RegisterRouter.scala:87:24] wire out_rimask_947 = |_out_rimask_T_947; // @[RegisterRouter.scala:87:24] wire out_wimask_947 = &_out_wimask_T_947; // @[RegisterRouter.scala:87:24] wire out_romask_947 = |_out_romask_T_947; // @[RegisterRouter.scala:87:24] wire out_womask_947 = &_out_womask_T_947; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_947 = out_rivalid_1_801 & out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9232 = out_f_rivalid_947; // @[RegisterRouter.scala:87:24] wire out_f_roready_947 = out_roready_1_801 & out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9233 = out_f_roready_947; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_947 = out_wivalid_1_801 & out_wimask_947; // @[RegisterRouter.scala:87:24] wire out_f_woready_947 = out_woready_1_801 & out_womask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9234 = ~out_rimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9235 = ~out_wimask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9236 = ~out_romask_947; // @[RegisterRouter.scala:87:24] wire _out_T_9237 = ~out_womask_947; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_809 = {hi_319, flags_0_go, _out_prepend_T_809}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9238 = out_prepend_809; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9239 = _out_T_9238; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_810 = _out_T_9239; // @[RegisterRouter.scala:87:24] wire out_rimask_948 = |_out_rimask_T_948; // @[RegisterRouter.scala:87:24] wire out_wimask_948 = &_out_wimask_T_948; // @[RegisterRouter.scala:87:24] wire out_romask_948 = |_out_romask_T_948; // @[RegisterRouter.scala:87:24] wire out_womask_948 = &_out_womask_T_948; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_948 = out_rivalid_1_802 & out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9241 = out_f_rivalid_948; // @[RegisterRouter.scala:87:24] wire out_f_roready_948 = out_roready_1_802 & out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9242 = out_f_roready_948; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_948 = out_wivalid_1_802 & out_wimask_948; // @[RegisterRouter.scala:87:24] wire out_f_woready_948 = out_woready_1_802 & out_womask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9243 = ~out_rimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9244 = ~out_wimask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9245 = ~out_romask_948; // @[RegisterRouter.scala:87:24] wire _out_T_9246 = ~out_womask_948; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_810 = {hi_320, flags_0_go, _out_prepend_T_810}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9247 = out_prepend_810; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9248 = _out_T_9247; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_167 = _out_T_9248; // @[MuxLiteral.scala:49:48] wire out_rimask_949 = |_out_rimask_T_949; // @[RegisterRouter.scala:87:24] wire out_wimask_949 = &_out_wimask_T_949; // @[RegisterRouter.scala:87:24] wire out_romask_949 = |_out_romask_T_949; // @[RegisterRouter.scala:87:24] wire out_womask_949 = &_out_womask_T_949; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_949 = out_rivalid_1_803 & out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9250 = out_f_rivalid_949; // @[RegisterRouter.scala:87:24] wire out_f_roready_949 = out_roready_1_803 & out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9251 = out_f_roready_949; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_949 = out_wivalid_1_803 & out_wimask_949; // @[RegisterRouter.scala:87:24] wire out_f_woready_949 = out_woready_1_803 & out_womask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9252 = ~out_rimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9253 = ~out_wimask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9254 = ~out_romask_949; // @[RegisterRouter.scala:87:24] wire _out_T_9255 = ~out_womask_949; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9257 = _out_T_9256; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_811 = _out_T_9257; // @[RegisterRouter.scala:87:24] wire out_rimask_950 = |_out_rimask_T_950; // @[RegisterRouter.scala:87:24] wire out_wimask_950 = &_out_wimask_T_950; // @[RegisterRouter.scala:87:24] wire out_romask_950 = |_out_romask_T_950; // @[RegisterRouter.scala:87:24] wire out_womask_950 = &_out_womask_T_950; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_950 = out_rivalid_1_804 & out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9259 = out_f_rivalid_950; // @[RegisterRouter.scala:87:24] wire out_f_roready_950 = out_roready_1_804 & out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9260 = out_f_roready_950; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_950 = out_wivalid_1_804 & out_wimask_950; // @[RegisterRouter.scala:87:24] wire out_f_woready_950 = out_woready_1_804 & out_womask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9261 = ~out_rimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9262 = ~out_wimask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9263 = ~out_romask_950; // @[RegisterRouter.scala:87:24] wire _out_T_9264 = ~out_womask_950; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_811 = {hi_274, flags_0_go, _out_prepend_T_811}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9265 = out_prepend_811; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9266 = _out_T_9265; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_812 = _out_T_9266; // @[RegisterRouter.scala:87:24] wire out_rimask_951 = |_out_rimask_T_951; // @[RegisterRouter.scala:87:24] wire out_wimask_951 = &_out_wimask_T_951; // @[RegisterRouter.scala:87:24] wire out_romask_951 = |_out_romask_T_951; // @[RegisterRouter.scala:87:24] wire out_womask_951 = &_out_womask_T_951; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_951 = out_rivalid_1_805 & out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9268 = out_f_rivalid_951; // @[RegisterRouter.scala:87:24] wire out_f_roready_951 = out_roready_1_805 & out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9269 = out_f_roready_951; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_951 = out_wivalid_1_805 & out_wimask_951; // @[RegisterRouter.scala:87:24] wire out_f_woready_951 = out_woready_1_805 & out_womask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9270 = ~out_rimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9271 = ~out_wimask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9272 = ~out_romask_951; // @[RegisterRouter.scala:87:24] wire _out_T_9273 = ~out_womask_951; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_812 = {hi_275, flags_0_go, _out_prepend_T_812}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9274 = out_prepend_812; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9275 = _out_T_9274; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_813 = _out_T_9275; // @[RegisterRouter.scala:87:24] wire out_rimask_952 = |_out_rimask_T_952; // @[RegisterRouter.scala:87:24] wire out_wimask_952 = &_out_wimask_T_952; // @[RegisterRouter.scala:87:24] wire out_romask_952 = |_out_romask_T_952; // @[RegisterRouter.scala:87:24] wire out_womask_952 = &_out_womask_T_952; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_952 = out_rivalid_1_806 & out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9277 = out_f_rivalid_952; // @[RegisterRouter.scala:87:24] wire out_f_roready_952 = out_roready_1_806 & out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9278 = out_f_roready_952; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_952 = out_wivalid_1_806 & out_wimask_952; // @[RegisterRouter.scala:87:24] wire out_f_woready_952 = out_woready_1_806 & out_womask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9279 = ~out_rimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9280 = ~out_wimask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9281 = ~out_romask_952; // @[RegisterRouter.scala:87:24] wire _out_T_9282 = ~out_womask_952; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_813 = {hi_276, flags_0_go, _out_prepend_T_813}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9283 = out_prepend_813; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9284 = _out_T_9283; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_814 = _out_T_9284; // @[RegisterRouter.scala:87:24] wire out_rimask_953 = |_out_rimask_T_953; // @[RegisterRouter.scala:87:24] wire out_wimask_953 = &_out_wimask_T_953; // @[RegisterRouter.scala:87:24] wire out_romask_953 = |_out_romask_T_953; // @[RegisterRouter.scala:87:24] wire out_womask_953 = &_out_womask_T_953; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_953 = out_rivalid_1_807 & out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9286 = out_f_rivalid_953; // @[RegisterRouter.scala:87:24] wire out_f_roready_953 = out_roready_1_807 & out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9287 = out_f_roready_953; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_953 = out_wivalid_1_807 & out_wimask_953; // @[RegisterRouter.scala:87:24] wire out_f_woready_953 = out_woready_1_807 & out_womask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9288 = ~out_rimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9289 = ~out_wimask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9290 = ~out_romask_953; // @[RegisterRouter.scala:87:24] wire _out_T_9291 = ~out_womask_953; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_814 = {hi_277, flags_0_go, _out_prepend_T_814}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9292 = out_prepend_814; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9293 = _out_T_9292; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_815 = _out_T_9293; // @[RegisterRouter.scala:87:24] wire out_rimask_954 = |_out_rimask_T_954; // @[RegisterRouter.scala:87:24] wire out_wimask_954 = &_out_wimask_T_954; // @[RegisterRouter.scala:87:24] wire out_romask_954 = |_out_romask_T_954; // @[RegisterRouter.scala:87:24] wire out_womask_954 = &_out_womask_T_954; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_954 = out_rivalid_1_808 & out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9295 = out_f_rivalid_954; // @[RegisterRouter.scala:87:24] wire out_f_roready_954 = out_roready_1_808 & out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9296 = out_f_roready_954; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_954 = out_wivalid_1_808 & out_wimask_954; // @[RegisterRouter.scala:87:24] wire out_f_woready_954 = out_woready_1_808 & out_womask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9297 = ~out_rimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9298 = ~out_wimask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9299 = ~out_romask_954; // @[RegisterRouter.scala:87:24] wire _out_T_9300 = ~out_womask_954; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_815 = {hi_278, flags_0_go, _out_prepend_T_815}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9301 = out_prepend_815; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9302 = _out_T_9301; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_816 = _out_T_9302; // @[RegisterRouter.scala:87:24] wire out_rimask_955 = |_out_rimask_T_955; // @[RegisterRouter.scala:87:24] wire out_wimask_955 = &_out_wimask_T_955; // @[RegisterRouter.scala:87:24] wire out_romask_955 = |_out_romask_T_955; // @[RegisterRouter.scala:87:24] wire out_womask_955 = &_out_womask_T_955; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_955 = out_rivalid_1_809 & out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9304 = out_f_rivalid_955; // @[RegisterRouter.scala:87:24] wire out_f_roready_955 = out_roready_1_809 & out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9305 = out_f_roready_955; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_955 = out_wivalid_1_809 & out_wimask_955; // @[RegisterRouter.scala:87:24] wire out_f_woready_955 = out_woready_1_809 & out_womask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9306 = ~out_rimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9307 = ~out_wimask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9308 = ~out_romask_955; // @[RegisterRouter.scala:87:24] wire _out_T_9309 = ~out_womask_955; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_816 = {hi_279, flags_0_go, _out_prepend_T_816}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9310 = out_prepend_816; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9311 = _out_T_9310; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_817 = _out_T_9311; // @[RegisterRouter.scala:87:24] wire out_rimask_956 = |_out_rimask_T_956; // @[RegisterRouter.scala:87:24] wire out_wimask_956 = &_out_wimask_T_956; // @[RegisterRouter.scala:87:24] wire out_romask_956 = |_out_romask_T_956; // @[RegisterRouter.scala:87:24] wire out_womask_956 = &_out_womask_T_956; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_956 = out_rivalid_1_810 & out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9313 = out_f_rivalid_956; // @[RegisterRouter.scala:87:24] wire out_f_roready_956 = out_roready_1_810 & out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9314 = out_f_roready_956; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_956 = out_wivalid_1_810 & out_wimask_956; // @[RegisterRouter.scala:87:24] wire out_f_woready_956 = out_woready_1_810 & out_womask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9315 = ~out_rimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9316 = ~out_wimask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9317 = ~out_romask_956; // @[RegisterRouter.scala:87:24] wire _out_T_9318 = ~out_womask_956; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_817 = {hi_280, flags_0_go, _out_prepend_T_817}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9319 = out_prepend_817; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9320 = _out_T_9319; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_162 = _out_T_9320; // @[MuxLiteral.scala:49:48] wire out_rimask_957 = |_out_rimask_T_957; // @[RegisterRouter.scala:87:24] wire out_wimask_957 = &_out_wimask_T_957; // @[RegisterRouter.scala:87:24] wire out_romask_957 = |_out_romask_T_957; // @[RegisterRouter.scala:87:24] wire out_womask_957 = &_out_womask_T_957; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_957 = out_rivalid_1_811 & out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9322 = out_f_rivalid_957; // @[RegisterRouter.scala:87:24] wire out_f_roready_957 = out_roready_1_811 & out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9323 = out_f_roready_957; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_957 = out_wivalid_1_811 & out_wimask_957; // @[RegisterRouter.scala:87:24] wire out_f_woready_957 = out_woready_1_811 & out_womask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9324 = ~out_rimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9325 = ~out_wimask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9326 = ~out_romask_957; // @[RegisterRouter.scala:87:24] wire _out_T_9327 = ~out_womask_957; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9329 = _out_T_9328; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_818 = _out_T_9329; // @[RegisterRouter.scala:87:24] wire out_rimask_958 = |_out_rimask_T_958; // @[RegisterRouter.scala:87:24] wire out_wimask_958 = &_out_wimask_T_958; // @[RegisterRouter.scala:87:24] wire out_romask_958 = |_out_romask_T_958; // @[RegisterRouter.scala:87:24] wire out_womask_958 = &_out_womask_T_958; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_958 = out_rivalid_1_812 & out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9331 = out_f_rivalid_958; // @[RegisterRouter.scala:87:24] wire out_f_roready_958 = out_roready_1_812 & out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9332 = out_f_roready_958; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_958 = out_wivalid_1_812 & out_wimask_958; // @[RegisterRouter.scala:87:24] wire out_f_woready_958 = out_woready_1_812 & out_womask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9333 = ~out_rimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9334 = ~out_wimask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9335 = ~out_romask_958; // @[RegisterRouter.scala:87:24] wire _out_T_9336 = ~out_womask_958; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_818 = {hi_1018, flags_0_go, _out_prepend_T_818}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9337 = out_prepend_818; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9338 = _out_T_9337; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_819 = _out_T_9338; // @[RegisterRouter.scala:87:24] wire out_rimask_959 = |_out_rimask_T_959; // @[RegisterRouter.scala:87:24] wire out_wimask_959 = &_out_wimask_T_959; // @[RegisterRouter.scala:87:24] wire out_romask_959 = |_out_romask_T_959; // @[RegisterRouter.scala:87:24] wire out_womask_959 = &_out_womask_T_959; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_959 = out_rivalid_1_813 & out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9340 = out_f_rivalid_959; // @[RegisterRouter.scala:87:24] wire out_f_roready_959 = out_roready_1_813 & out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9341 = out_f_roready_959; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_959 = out_wivalid_1_813 & out_wimask_959; // @[RegisterRouter.scala:87:24] wire out_f_woready_959 = out_woready_1_813 & out_womask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9342 = ~out_rimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9343 = ~out_wimask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9344 = ~out_romask_959; // @[RegisterRouter.scala:87:24] wire _out_T_9345 = ~out_womask_959; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_819 = {hi_1019, flags_0_go, _out_prepend_T_819}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9346 = out_prepend_819; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9347 = _out_T_9346; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_820 = _out_T_9347; // @[RegisterRouter.scala:87:24] wire out_rimask_960 = |_out_rimask_T_960; // @[RegisterRouter.scala:87:24] wire out_wimask_960 = &_out_wimask_T_960; // @[RegisterRouter.scala:87:24] wire out_romask_960 = |_out_romask_T_960; // @[RegisterRouter.scala:87:24] wire out_womask_960 = &_out_womask_T_960; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_960 = out_rivalid_1_814 & out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9349 = out_f_rivalid_960; // @[RegisterRouter.scala:87:24] wire out_f_roready_960 = out_roready_1_814 & out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9350 = out_f_roready_960; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_960 = out_wivalid_1_814 & out_wimask_960; // @[RegisterRouter.scala:87:24] wire out_f_woready_960 = out_woready_1_814 & out_womask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9351 = ~out_rimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9352 = ~out_wimask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9353 = ~out_romask_960; // @[RegisterRouter.scala:87:24] wire _out_T_9354 = ~out_womask_960; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_820 = {hi_1020, flags_0_go, _out_prepend_T_820}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9355 = out_prepend_820; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9356 = _out_T_9355; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_821 = _out_T_9356; // @[RegisterRouter.scala:87:24] wire out_rimask_961 = |_out_rimask_T_961; // @[RegisterRouter.scala:87:24] wire out_wimask_961 = &_out_wimask_T_961; // @[RegisterRouter.scala:87:24] wire out_romask_961 = |_out_romask_T_961; // @[RegisterRouter.scala:87:24] wire out_womask_961 = &_out_womask_T_961; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_961 = out_rivalid_1_815 & out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9358 = out_f_rivalid_961; // @[RegisterRouter.scala:87:24] wire out_f_roready_961 = out_roready_1_815 & out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9359 = out_f_roready_961; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_961 = out_wivalid_1_815 & out_wimask_961; // @[RegisterRouter.scala:87:24] wire out_f_woready_961 = out_woready_1_815 & out_womask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9360 = ~out_rimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9361 = ~out_wimask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9362 = ~out_romask_961; // @[RegisterRouter.scala:87:24] wire _out_T_9363 = ~out_womask_961; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_821 = {hi_1021, flags_0_go, _out_prepend_T_821}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9364 = out_prepend_821; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9365 = _out_T_9364; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_822 = _out_T_9365; // @[RegisterRouter.scala:87:24] wire out_rimask_962 = |_out_rimask_T_962; // @[RegisterRouter.scala:87:24] wire out_wimask_962 = &_out_wimask_T_962; // @[RegisterRouter.scala:87:24] wire out_romask_962 = |_out_romask_T_962; // @[RegisterRouter.scala:87:24] wire out_womask_962 = &_out_womask_T_962; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_962 = out_rivalid_1_816 & out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9367 = out_f_rivalid_962; // @[RegisterRouter.scala:87:24] wire out_f_roready_962 = out_roready_1_816 & out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9368 = out_f_roready_962; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_962 = out_wivalid_1_816 & out_wimask_962; // @[RegisterRouter.scala:87:24] wire out_f_woready_962 = out_woready_1_816 & out_womask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9369 = ~out_rimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9370 = ~out_wimask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9371 = ~out_romask_962; // @[RegisterRouter.scala:87:24] wire _out_T_9372 = ~out_womask_962; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_822 = {hi_1022, flags_0_go, _out_prepend_T_822}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9373 = out_prepend_822; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9374 = _out_T_9373; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_823 = _out_T_9374; // @[RegisterRouter.scala:87:24] wire out_rimask_963 = |_out_rimask_T_963; // @[RegisterRouter.scala:87:24] wire out_wimask_963 = &_out_wimask_T_963; // @[RegisterRouter.scala:87:24] wire out_romask_963 = |_out_romask_T_963; // @[RegisterRouter.scala:87:24] wire out_womask_963 = &_out_womask_T_963; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_963 = out_rivalid_1_817 & out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9376 = out_f_rivalid_963; // @[RegisterRouter.scala:87:24] wire out_f_roready_963 = out_roready_1_817 & out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9377 = out_f_roready_963; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_963 = out_wivalid_1_817 & out_wimask_963; // @[RegisterRouter.scala:87:24] wire out_f_woready_963 = out_woready_1_817 & out_womask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9378 = ~out_rimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9379 = ~out_wimask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9380 = ~out_romask_963; // @[RegisterRouter.scala:87:24] wire _out_T_9381 = ~out_womask_963; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_823 = {hi_1023, flags_0_go, _out_prepend_T_823}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9382 = out_prepend_823; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9383 = _out_T_9382; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_824 = _out_T_9383; // @[RegisterRouter.scala:87:24] wire out_rimask_964 = |_out_rimask_T_964; // @[RegisterRouter.scala:87:24] wire out_wimask_964 = &_out_wimask_T_964; // @[RegisterRouter.scala:87:24] wire out_romask_964 = |_out_romask_T_964; // @[RegisterRouter.scala:87:24] wire out_womask_964 = &_out_womask_T_964; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_964 = out_rivalid_1_818 & out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9385 = out_f_rivalid_964; // @[RegisterRouter.scala:87:24] wire out_f_roready_964 = out_roready_1_818 & out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9386 = out_f_roready_964; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_964 = out_wivalid_1_818 & out_wimask_964; // @[RegisterRouter.scala:87:24] wire out_f_woready_964 = out_woready_1_818 & out_womask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9387 = ~out_rimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9388 = ~out_wimask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9389 = ~out_romask_964; // @[RegisterRouter.scala:87:24] wire _out_T_9390 = ~out_womask_964; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_824 = {hi_1024, flags_0_go, _out_prepend_T_824}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9391 = out_prepend_824; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9392 = _out_T_9391; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_255 = _out_T_9392; // @[MuxLiteral.scala:49:48] wire out_rimask_965 = |_out_rimask_T_965; // @[RegisterRouter.scala:87:24] wire out_wimask_965 = &_out_wimask_T_965; // @[RegisterRouter.scala:87:24] wire out_romask_965 = |_out_romask_T_965; // @[RegisterRouter.scala:87:24] wire out_womask_965 = &_out_womask_T_965; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_965 = out_rivalid_1_819 & out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9394 = out_f_rivalid_965; // @[RegisterRouter.scala:87:24] wire out_f_roready_965 = out_roready_1_819 & out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9395 = out_f_roready_965; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_965 = out_wivalid_1_819 & out_wimask_965; // @[RegisterRouter.scala:87:24] wire out_f_woready_965 = out_woready_1_819 & out_womask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9396 = ~out_rimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9397 = ~out_wimask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9398 = ~out_romask_965; // @[RegisterRouter.scala:87:24] wire _out_T_9399 = ~out_womask_965; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9401 = _out_T_9400; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_825 = _out_T_9401; // @[RegisterRouter.scala:87:24] wire out_rimask_966 = |_out_rimask_T_966; // @[RegisterRouter.scala:87:24] wire out_wimask_966 = &_out_wimask_T_966; // @[RegisterRouter.scala:87:24] wire out_romask_966 = |_out_romask_T_966; // @[RegisterRouter.scala:87:24] wire out_womask_966 = &_out_womask_T_966; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_966 = out_rivalid_1_820 & out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9403 = out_f_rivalid_966; // @[RegisterRouter.scala:87:24] wire out_f_roready_966 = out_roready_1_820 & out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9404 = out_f_roready_966; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_966 = out_wivalid_1_820 & out_wimask_966; // @[RegisterRouter.scala:87:24] wire out_f_woready_966 = out_woready_1_820 & out_womask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9405 = ~out_rimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9406 = ~out_wimask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9407 = ~out_romask_966; // @[RegisterRouter.scala:87:24] wire _out_T_9408 = ~out_womask_966; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_825 = {hi_650, flags_0_go, _out_prepend_T_825}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9409 = out_prepend_825; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9410 = _out_T_9409; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_826 = _out_T_9410; // @[RegisterRouter.scala:87:24] wire out_rimask_967 = |_out_rimask_T_967; // @[RegisterRouter.scala:87:24] wire out_wimask_967 = &_out_wimask_T_967; // @[RegisterRouter.scala:87:24] wire out_romask_967 = |_out_romask_T_967; // @[RegisterRouter.scala:87:24] wire out_womask_967 = &_out_womask_T_967; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_967 = out_rivalid_1_821 & out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9412 = out_f_rivalid_967; // @[RegisterRouter.scala:87:24] wire out_f_roready_967 = out_roready_1_821 & out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9413 = out_f_roready_967; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_967 = out_wivalid_1_821 & out_wimask_967; // @[RegisterRouter.scala:87:24] wire out_f_woready_967 = out_woready_1_821 & out_womask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9414 = ~out_rimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9415 = ~out_wimask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9416 = ~out_romask_967; // @[RegisterRouter.scala:87:24] wire _out_T_9417 = ~out_womask_967; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_826 = {hi_651, flags_0_go, _out_prepend_T_826}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9418 = out_prepend_826; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9419 = _out_T_9418; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_827 = _out_T_9419; // @[RegisterRouter.scala:87:24] wire out_rimask_968 = |_out_rimask_T_968; // @[RegisterRouter.scala:87:24] wire out_wimask_968 = &_out_wimask_T_968; // @[RegisterRouter.scala:87:24] wire out_romask_968 = |_out_romask_T_968; // @[RegisterRouter.scala:87:24] wire out_womask_968 = &_out_womask_T_968; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_968 = out_rivalid_1_822 & out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9421 = out_f_rivalid_968; // @[RegisterRouter.scala:87:24] wire out_f_roready_968 = out_roready_1_822 & out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9422 = out_f_roready_968; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_968 = out_wivalid_1_822 & out_wimask_968; // @[RegisterRouter.scala:87:24] wire out_f_woready_968 = out_woready_1_822 & out_womask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9423 = ~out_rimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9424 = ~out_wimask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9425 = ~out_romask_968; // @[RegisterRouter.scala:87:24] wire _out_T_9426 = ~out_womask_968; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_827 = {hi_652, flags_0_go, _out_prepend_T_827}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9427 = out_prepend_827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9428 = _out_T_9427; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_828 = _out_T_9428; // @[RegisterRouter.scala:87:24] wire out_rimask_969 = |_out_rimask_T_969; // @[RegisterRouter.scala:87:24] wire out_wimask_969 = &_out_wimask_T_969; // @[RegisterRouter.scala:87:24] wire out_romask_969 = |_out_romask_T_969; // @[RegisterRouter.scala:87:24] wire out_womask_969 = &_out_womask_T_969; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_969 = out_rivalid_1_823 & out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9430 = out_f_rivalid_969; // @[RegisterRouter.scala:87:24] wire out_f_roready_969 = out_roready_1_823 & out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9431 = out_f_roready_969; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_969 = out_wivalid_1_823 & out_wimask_969; // @[RegisterRouter.scala:87:24] wire out_f_woready_969 = out_woready_1_823 & out_womask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9432 = ~out_rimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9433 = ~out_wimask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9434 = ~out_romask_969; // @[RegisterRouter.scala:87:24] wire _out_T_9435 = ~out_womask_969; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_828 = {hi_653, flags_0_go, _out_prepend_T_828}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9436 = out_prepend_828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9437 = _out_T_9436; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_829 = _out_T_9437; // @[RegisterRouter.scala:87:24] wire out_rimask_970 = |_out_rimask_T_970; // @[RegisterRouter.scala:87:24] wire out_wimask_970 = &_out_wimask_T_970; // @[RegisterRouter.scala:87:24] wire out_romask_970 = |_out_romask_T_970; // @[RegisterRouter.scala:87:24] wire out_womask_970 = &_out_womask_T_970; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_970 = out_rivalid_1_824 & out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9439 = out_f_rivalid_970; // @[RegisterRouter.scala:87:24] wire out_f_roready_970 = out_roready_1_824 & out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9440 = out_f_roready_970; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_970 = out_wivalid_1_824 & out_wimask_970; // @[RegisterRouter.scala:87:24] wire out_f_woready_970 = out_woready_1_824 & out_womask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9441 = ~out_rimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9442 = ~out_wimask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9443 = ~out_romask_970; // @[RegisterRouter.scala:87:24] wire _out_T_9444 = ~out_womask_970; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_829 = {hi_654, flags_0_go, _out_prepend_T_829}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9445 = out_prepend_829; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9446 = _out_T_9445; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_830 = _out_T_9446; // @[RegisterRouter.scala:87:24] wire out_rimask_971 = |_out_rimask_T_971; // @[RegisterRouter.scala:87:24] wire out_wimask_971 = &_out_wimask_T_971; // @[RegisterRouter.scala:87:24] wire out_romask_971 = |_out_romask_T_971; // @[RegisterRouter.scala:87:24] wire out_womask_971 = &_out_womask_T_971; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_971 = out_rivalid_1_825 & out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9448 = out_f_rivalid_971; // @[RegisterRouter.scala:87:24] wire out_f_roready_971 = out_roready_1_825 & out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9449 = out_f_roready_971; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_971 = out_wivalid_1_825 & out_wimask_971; // @[RegisterRouter.scala:87:24] wire out_f_woready_971 = out_woready_1_825 & out_womask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9450 = ~out_rimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9451 = ~out_wimask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9452 = ~out_romask_971; // @[RegisterRouter.scala:87:24] wire _out_T_9453 = ~out_womask_971; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_830 = {hi_655, flags_0_go, _out_prepend_T_830}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9454 = out_prepend_830; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9455 = _out_T_9454; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_831 = _out_T_9455; // @[RegisterRouter.scala:87:24] wire out_rimask_972 = |_out_rimask_T_972; // @[RegisterRouter.scala:87:24] wire out_wimask_972 = &_out_wimask_T_972; // @[RegisterRouter.scala:87:24] wire out_romask_972 = |_out_romask_T_972; // @[RegisterRouter.scala:87:24] wire out_womask_972 = &_out_womask_T_972; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_972 = out_rivalid_1_826 & out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9457 = out_f_rivalid_972; // @[RegisterRouter.scala:87:24] wire out_f_roready_972 = out_roready_1_826 & out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9458 = out_f_roready_972; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_972 = out_wivalid_1_826 & out_wimask_972; // @[RegisterRouter.scala:87:24] wire out_f_woready_972 = out_woready_1_826 & out_womask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9459 = ~out_rimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9460 = ~out_wimask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9461 = ~out_romask_972; // @[RegisterRouter.scala:87:24] wire _out_T_9462 = ~out_womask_972; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_831 = {hi_656, flags_0_go, _out_prepend_T_831}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9463 = out_prepend_831; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9464 = _out_T_9463; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_209 = _out_T_9464; // @[MuxLiteral.scala:49:48] wire out_rimask_973 = |_out_rimask_T_973; // @[RegisterRouter.scala:87:24] wire out_wimask_973 = &_out_wimask_T_973; // @[RegisterRouter.scala:87:24] wire out_romask_973 = |_out_romask_T_973; // @[RegisterRouter.scala:87:24] wire out_womask_973 = &_out_womask_T_973; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_973 = out_rivalid_1_827 & out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9466 = out_f_rivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_roready_973 = out_roready_1_827 & out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9467 = out_f_roready_973; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_973 = out_wivalid_1_827 & out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9468 = out_f_wivalid_973; // @[RegisterRouter.scala:87:24] wire out_f_woready_973 = out_woready_1_827 & out_womask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9469 = out_f_woready_973; // @[RegisterRouter.scala:87:24] wire _out_T_9470 = ~out_rimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9471 = ~out_wimask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9472 = ~out_romask_973; // @[RegisterRouter.scala:87:24] wire _out_T_9473 = ~out_womask_973; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9475 = _out_T_9474; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_832 = _out_T_9475; // @[RegisterRouter.scala:87:24] wire out_rimask_974 = |_out_rimask_T_974; // @[RegisterRouter.scala:87:24] wire out_wimask_974 = &_out_wimask_T_974; // @[RegisterRouter.scala:87:24] wire out_romask_974 = |_out_romask_T_974; // @[RegisterRouter.scala:87:24] wire out_womask_974 = &_out_womask_T_974; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_974 = out_rivalid_1_828 & out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9477 = out_f_rivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_roready_974 = out_roready_1_828 & out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9478 = out_f_roready_974; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_974 = out_wivalid_1_828 & out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9479 = out_f_wivalid_974; // @[RegisterRouter.scala:87:24] wire out_f_woready_974 = out_woready_1_828 & out_womask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9480 = out_f_woready_974; // @[RegisterRouter.scala:87:24] wire _out_T_9481 = ~out_rimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9482 = ~out_wimask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9483 = ~out_romask_974; // @[RegisterRouter.scala:87:24] wire _out_T_9484 = ~out_womask_974; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_832 = {abstractDataMem_1, _out_prepend_T_832}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9485 = out_prepend_832; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9486 = _out_T_9485; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_833 = _out_T_9486; // @[RegisterRouter.scala:87:24] wire out_rimask_975 = |_out_rimask_T_975; // @[RegisterRouter.scala:87:24] wire out_wimask_975 = &_out_wimask_T_975; // @[RegisterRouter.scala:87:24] wire out_romask_975 = |_out_romask_T_975; // @[RegisterRouter.scala:87:24] wire out_womask_975 = &_out_womask_T_975; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_975 = out_rivalid_1_829 & out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9488 = out_f_rivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_roready_975 = out_roready_1_829 & out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9489 = out_f_roready_975; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_975 = out_wivalid_1_829 & out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9490 = out_f_wivalid_975; // @[RegisterRouter.scala:87:24] wire out_f_woready_975 = out_woready_1_829 & out_womask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9491 = out_f_woready_975; // @[RegisterRouter.scala:87:24] wire _out_T_9492 = ~out_rimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9493 = ~out_wimask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9494 = ~out_romask_975; // @[RegisterRouter.scala:87:24] wire _out_T_9495 = ~out_womask_975; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_833 = {abstractDataMem_2, _out_prepend_T_833}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9496 = out_prepend_833; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9497 = _out_T_9496; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_834 = _out_T_9497; // @[RegisterRouter.scala:87:24] wire out_rimask_976 = |_out_rimask_T_976; // @[RegisterRouter.scala:87:24] wire out_wimask_976 = &_out_wimask_T_976; // @[RegisterRouter.scala:87:24] wire out_romask_976 = |_out_romask_T_976; // @[RegisterRouter.scala:87:24] wire out_womask_976 = &_out_womask_T_976; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_976 = out_rivalid_1_830 & out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9499 = out_f_rivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_roready_976 = out_roready_1_830 & out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9500 = out_f_roready_976; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_976 = out_wivalid_1_830 & out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9501 = out_f_wivalid_976; // @[RegisterRouter.scala:87:24] wire out_f_woready_976 = out_woready_1_830 & out_womask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9502 = out_f_woready_976; // @[RegisterRouter.scala:87:24] wire _out_T_9503 = ~out_rimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9504 = ~out_wimask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9505 = ~out_romask_976; // @[RegisterRouter.scala:87:24] wire _out_T_9506 = ~out_womask_976; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_834 = {abstractDataMem_3, _out_prepend_T_834}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9507 = out_prepend_834; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9508 = _out_T_9507; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_835 = _out_T_9508; // @[RegisterRouter.scala:87:24] wire out_rimask_977 = |_out_rimask_T_977; // @[RegisterRouter.scala:87:24] wire out_wimask_977 = &_out_wimask_T_977; // @[RegisterRouter.scala:87:24] wire out_romask_977 = |_out_romask_T_977; // @[RegisterRouter.scala:87:24] wire out_womask_977 = &_out_womask_T_977; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_977 = out_rivalid_1_831 & out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9510 = out_f_rivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_roready_977 = out_roready_1_831 & out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9511 = out_f_roready_977; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_977 = out_wivalid_1_831 & out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9512 = out_f_wivalid_977; // @[RegisterRouter.scala:87:24] wire out_f_woready_977 = out_woready_1_831 & out_womask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9513 = out_f_woready_977; // @[RegisterRouter.scala:87:24] wire _out_T_9514 = ~out_rimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9515 = ~out_wimask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9516 = ~out_romask_977; // @[RegisterRouter.scala:87:24] wire _out_T_9517 = ~out_womask_977; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_835 = {abstractDataMem_4, _out_prepend_T_835}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9518 = out_prepend_835; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9519 = _out_T_9518; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_836 = _out_T_9519; // @[RegisterRouter.scala:87:24] wire out_rimask_978 = |_out_rimask_T_978; // @[RegisterRouter.scala:87:24] wire out_wimask_978 = &_out_wimask_T_978; // @[RegisterRouter.scala:87:24] wire out_romask_978 = |_out_romask_T_978; // @[RegisterRouter.scala:87:24] wire out_womask_978 = &_out_womask_T_978; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_978 = out_rivalid_1_832 & out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9521 = out_f_rivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_roready_978 = out_roready_1_832 & out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9522 = out_f_roready_978; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_978 = out_wivalid_1_832 & out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9523 = out_f_wivalid_978; // @[RegisterRouter.scala:87:24] wire out_f_woready_978 = out_woready_1_832 & out_womask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9524 = out_f_woready_978; // @[RegisterRouter.scala:87:24] wire _out_T_9525 = ~out_rimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9526 = ~out_wimask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9527 = ~out_romask_978; // @[RegisterRouter.scala:87:24] wire _out_T_9528 = ~out_womask_978; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_836 = {abstractDataMem_5, _out_prepend_T_836}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9529 = out_prepend_836; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9530 = _out_T_9529; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_837 = _out_T_9530; // @[RegisterRouter.scala:87:24] wire out_rimask_979 = |_out_rimask_T_979; // @[RegisterRouter.scala:87:24] wire out_wimask_979 = &_out_wimask_T_979; // @[RegisterRouter.scala:87:24] wire out_romask_979 = |_out_romask_T_979; // @[RegisterRouter.scala:87:24] wire out_womask_979 = &_out_womask_T_979; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_979 = out_rivalid_1_833 & out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9532 = out_f_rivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_roready_979 = out_roready_1_833 & out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9533 = out_f_roready_979; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_979 = out_wivalid_1_833 & out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9534 = out_f_wivalid_979; // @[RegisterRouter.scala:87:24] wire out_f_woready_979 = out_woready_1_833 & out_womask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9535 = out_f_woready_979; // @[RegisterRouter.scala:87:24] wire _out_T_9536 = ~out_rimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9537 = ~out_wimask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9538 = ~out_romask_979; // @[RegisterRouter.scala:87:24] wire _out_T_9539 = ~out_womask_979; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_837 = {abstractDataMem_6, _out_prepend_T_837}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9540 = out_prepend_837; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9541 = _out_T_9540; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_838 = _out_T_9541; // @[RegisterRouter.scala:87:24] wire out_rimask_980 = |_out_rimask_T_980; // @[RegisterRouter.scala:87:24] wire out_wimask_980 = &_out_wimask_T_980; // @[RegisterRouter.scala:87:24] wire out_romask_980 = |_out_romask_T_980; // @[RegisterRouter.scala:87:24] wire out_womask_980 = &_out_womask_T_980; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_980 = out_rivalid_1_834 & out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9543 = out_f_rivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_roready_980 = out_roready_1_834 & out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9544 = out_f_roready_980; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_980 = out_wivalid_1_834 & out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9545 = out_f_wivalid_980; // @[RegisterRouter.scala:87:24] wire out_f_woready_980 = out_woready_1_834 & out_womask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9546 = out_f_woready_980; // @[RegisterRouter.scala:87:24] wire _out_T_9547 = ~out_rimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9548 = ~out_wimask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9549 = ~out_romask_980; // @[RegisterRouter.scala:87:24] wire _out_T_9550 = ~out_womask_980; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_838 = {abstractDataMem_7, _out_prepend_T_838}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9551 = out_prepend_838; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9552 = _out_T_9551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_112 = _out_T_9552; // @[MuxLiteral.scala:49:48] wire out_rimask_981 = |_out_rimask_T_981; // @[RegisterRouter.scala:87:24] wire out_wimask_981 = &_out_wimask_T_981; // @[RegisterRouter.scala:87:24] wire out_romask_981 = |_out_romask_T_981; // @[RegisterRouter.scala:87:24] wire out_womask_981 = &_out_womask_T_981; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_981 = out_rivalid_1_835 & out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9554 = out_f_rivalid_981; // @[RegisterRouter.scala:87:24] wire out_f_roready_981 = out_roready_1_835 & out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9555 = out_f_roready_981; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_981 = out_wivalid_1_835 & out_wimask_981; // @[RegisterRouter.scala:87:24] wire out_f_woready_981 = out_woready_1_835 & out_womask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9556 = ~out_rimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9557 = ~out_wimask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9558 = ~out_romask_981; // @[RegisterRouter.scala:87:24] wire _out_T_9559 = ~out_womask_981; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9561 = _out_T_9560; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_839 = _out_T_9561; // @[RegisterRouter.scala:87:24] wire out_rimask_982 = |_out_rimask_T_982; // @[RegisterRouter.scala:87:24] wire out_wimask_982 = &_out_wimask_T_982; // @[RegisterRouter.scala:87:24] wire out_romask_982 = |_out_romask_T_982; // @[RegisterRouter.scala:87:24] wire out_womask_982 = &_out_womask_T_982; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_982 = out_rivalid_1_836 & out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9563 = out_f_rivalid_982; // @[RegisterRouter.scala:87:24] wire out_f_roready_982 = out_roready_1_836 & out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9564 = out_f_roready_982; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_982 = out_wivalid_1_836 & out_wimask_982; // @[RegisterRouter.scala:87:24] wire out_f_woready_982 = out_woready_1_836 & out_womask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9565 = ~out_rimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9566 = ~out_wimask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9567 = ~out_romask_982; // @[RegisterRouter.scala:87:24] wire _out_T_9568 = ~out_womask_982; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_839 = {hi_530, flags_0_go, _out_prepend_T_839}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9569 = out_prepend_839; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9570 = _out_T_9569; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_840 = _out_T_9570; // @[RegisterRouter.scala:87:24] wire out_rimask_983 = |_out_rimask_T_983; // @[RegisterRouter.scala:87:24] wire out_wimask_983 = &_out_wimask_T_983; // @[RegisterRouter.scala:87:24] wire out_romask_983 = |_out_romask_T_983; // @[RegisterRouter.scala:87:24] wire out_womask_983 = &_out_womask_T_983; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_983 = out_rivalid_1_837 & out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9572 = out_f_rivalid_983; // @[RegisterRouter.scala:87:24] wire out_f_roready_983 = out_roready_1_837 & out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9573 = out_f_roready_983; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_983 = out_wivalid_1_837 & out_wimask_983; // @[RegisterRouter.scala:87:24] wire out_f_woready_983 = out_woready_1_837 & out_womask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9574 = ~out_rimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9575 = ~out_wimask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9576 = ~out_romask_983; // @[RegisterRouter.scala:87:24] wire _out_T_9577 = ~out_womask_983; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_840 = {hi_531, flags_0_go, _out_prepend_T_840}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9578 = out_prepend_840; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9579 = _out_T_9578; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_841 = _out_T_9579; // @[RegisterRouter.scala:87:24] wire out_rimask_984 = |_out_rimask_T_984; // @[RegisterRouter.scala:87:24] wire out_wimask_984 = &_out_wimask_T_984; // @[RegisterRouter.scala:87:24] wire out_romask_984 = |_out_romask_T_984; // @[RegisterRouter.scala:87:24] wire out_womask_984 = &_out_womask_T_984; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_984 = out_rivalid_1_838 & out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9581 = out_f_rivalid_984; // @[RegisterRouter.scala:87:24] wire out_f_roready_984 = out_roready_1_838 & out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9582 = out_f_roready_984; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_984 = out_wivalid_1_838 & out_wimask_984; // @[RegisterRouter.scala:87:24] wire out_f_woready_984 = out_woready_1_838 & out_womask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9583 = ~out_rimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9584 = ~out_wimask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9585 = ~out_romask_984; // @[RegisterRouter.scala:87:24] wire _out_T_9586 = ~out_womask_984; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_841 = {hi_532, flags_0_go, _out_prepend_T_841}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9587 = out_prepend_841; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9588 = _out_T_9587; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_842 = _out_T_9588; // @[RegisterRouter.scala:87:24] wire out_rimask_985 = |_out_rimask_T_985; // @[RegisterRouter.scala:87:24] wire out_wimask_985 = &_out_wimask_T_985; // @[RegisterRouter.scala:87:24] wire out_romask_985 = |_out_romask_T_985; // @[RegisterRouter.scala:87:24] wire out_womask_985 = &_out_womask_T_985; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_985 = out_rivalid_1_839 & out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9590 = out_f_rivalid_985; // @[RegisterRouter.scala:87:24] wire out_f_roready_985 = out_roready_1_839 & out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9591 = out_f_roready_985; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_985 = out_wivalid_1_839 & out_wimask_985; // @[RegisterRouter.scala:87:24] wire out_f_woready_985 = out_woready_1_839 & out_womask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9592 = ~out_rimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9593 = ~out_wimask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9594 = ~out_romask_985; // @[RegisterRouter.scala:87:24] wire _out_T_9595 = ~out_womask_985; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_842 = {hi_533, flags_0_go, _out_prepend_T_842}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9596 = out_prepend_842; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9597 = _out_T_9596; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_843 = _out_T_9597; // @[RegisterRouter.scala:87:24] wire out_rimask_986 = |_out_rimask_T_986; // @[RegisterRouter.scala:87:24] wire out_wimask_986 = &_out_wimask_T_986; // @[RegisterRouter.scala:87:24] wire out_romask_986 = |_out_romask_T_986; // @[RegisterRouter.scala:87:24] wire out_womask_986 = &_out_womask_T_986; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_986 = out_rivalid_1_840 & out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9599 = out_f_rivalid_986; // @[RegisterRouter.scala:87:24] wire out_f_roready_986 = out_roready_1_840 & out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9600 = out_f_roready_986; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_986 = out_wivalid_1_840 & out_wimask_986; // @[RegisterRouter.scala:87:24] wire out_f_woready_986 = out_woready_1_840 & out_womask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9601 = ~out_rimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9602 = ~out_wimask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9603 = ~out_romask_986; // @[RegisterRouter.scala:87:24] wire _out_T_9604 = ~out_womask_986; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_843 = {hi_534, flags_0_go, _out_prepend_T_843}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9605 = out_prepend_843; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9606 = _out_T_9605; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_844 = _out_T_9606; // @[RegisterRouter.scala:87:24] wire out_rimask_987 = |_out_rimask_T_987; // @[RegisterRouter.scala:87:24] wire out_wimask_987 = &_out_wimask_T_987; // @[RegisterRouter.scala:87:24] wire out_romask_987 = |_out_romask_T_987; // @[RegisterRouter.scala:87:24] wire out_womask_987 = &_out_womask_T_987; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_987 = out_rivalid_1_841 & out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9608 = out_f_rivalid_987; // @[RegisterRouter.scala:87:24] wire out_f_roready_987 = out_roready_1_841 & out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9609 = out_f_roready_987; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_987 = out_wivalid_1_841 & out_wimask_987; // @[RegisterRouter.scala:87:24] wire out_f_woready_987 = out_woready_1_841 & out_womask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9610 = ~out_rimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9611 = ~out_wimask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9612 = ~out_romask_987; // @[RegisterRouter.scala:87:24] wire _out_T_9613 = ~out_womask_987; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_844 = {hi_535, flags_0_go, _out_prepend_T_844}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9614 = out_prepend_844; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9615 = _out_T_9614; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_845 = _out_T_9615; // @[RegisterRouter.scala:87:24] wire out_rimask_988 = |_out_rimask_T_988; // @[RegisterRouter.scala:87:24] wire out_wimask_988 = &_out_wimask_T_988; // @[RegisterRouter.scala:87:24] wire out_romask_988 = |_out_romask_T_988; // @[RegisterRouter.scala:87:24] wire out_womask_988 = &_out_womask_T_988; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_988 = out_rivalid_1_842 & out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9617 = out_f_rivalid_988; // @[RegisterRouter.scala:87:24] wire out_f_roready_988 = out_roready_1_842 & out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9618 = out_f_roready_988; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_988 = out_wivalid_1_842 & out_wimask_988; // @[RegisterRouter.scala:87:24] wire out_f_woready_988 = out_woready_1_842 & out_womask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9619 = ~out_rimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9620 = ~out_wimask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9621 = ~out_romask_988; // @[RegisterRouter.scala:87:24] wire _out_T_9622 = ~out_womask_988; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_845 = {hi_536, flags_0_go, _out_prepend_T_845}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9623 = out_prepend_845; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9624 = _out_T_9623; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_194 = _out_T_9624; // @[MuxLiteral.scala:49:48] wire out_rimask_989 = |_out_rimask_T_989; // @[RegisterRouter.scala:87:24] wire out_wimask_989 = &_out_wimask_T_989; // @[RegisterRouter.scala:87:24] wire out_romask_989 = |_out_romask_T_989; // @[RegisterRouter.scala:87:24] wire out_womask_989 = &_out_womask_T_989; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_989 = out_rivalid_1_843 & out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9626 = out_f_rivalid_989; // @[RegisterRouter.scala:87:24] wire out_f_roready_989 = out_roready_1_843 & out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9627 = out_f_roready_989; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_989 = out_wivalid_1_843 & out_wimask_989; // @[RegisterRouter.scala:87:24] wire out_f_woready_989 = out_woready_1_843 & out_womask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9628 = ~out_rimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9629 = ~out_wimask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9630 = ~out_romask_989; // @[RegisterRouter.scala:87:24] wire _out_T_9631 = ~out_womask_989; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9633 = _out_T_9632; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_846 = _out_T_9633; // @[RegisterRouter.scala:87:24] wire out_rimask_990 = |_out_rimask_T_990; // @[RegisterRouter.scala:87:24] wire out_wimask_990 = &_out_wimask_T_990; // @[RegisterRouter.scala:87:24] wire out_romask_990 = |_out_romask_T_990; // @[RegisterRouter.scala:87:24] wire out_womask_990 = &_out_womask_T_990; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_990 = out_rivalid_1_844 & out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9635 = out_f_rivalid_990; // @[RegisterRouter.scala:87:24] wire out_f_roready_990 = out_roready_1_844 & out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9636 = out_f_roready_990; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_990 = out_wivalid_1_844 & out_wimask_990; // @[RegisterRouter.scala:87:24] wire out_f_woready_990 = out_woready_1_844 & out_womask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9637 = ~out_rimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9638 = ~out_wimask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9639 = ~out_romask_990; // @[RegisterRouter.scala:87:24] wire _out_T_9640 = ~out_womask_990; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_846 = {hi_138, flags_0_go, _out_prepend_T_846}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9641 = out_prepend_846; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9642 = _out_T_9641; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_847 = _out_T_9642; // @[RegisterRouter.scala:87:24] wire out_rimask_991 = |_out_rimask_T_991; // @[RegisterRouter.scala:87:24] wire out_wimask_991 = &_out_wimask_T_991; // @[RegisterRouter.scala:87:24] wire out_romask_991 = |_out_romask_T_991; // @[RegisterRouter.scala:87:24] wire out_womask_991 = &_out_womask_T_991; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_991 = out_rivalid_1_845 & out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9644 = out_f_rivalid_991; // @[RegisterRouter.scala:87:24] wire out_f_roready_991 = out_roready_1_845 & out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9645 = out_f_roready_991; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_991 = out_wivalid_1_845 & out_wimask_991; // @[RegisterRouter.scala:87:24] wire out_f_woready_991 = out_woready_1_845 & out_womask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9646 = ~out_rimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9647 = ~out_wimask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9648 = ~out_romask_991; // @[RegisterRouter.scala:87:24] wire _out_T_9649 = ~out_womask_991; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_847 = {hi_139, flags_0_go, _out_prepend_T_847}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9650 = out_prepend_847; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9651 = _out_T_9650; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_848 = _out_T_9651; // @[RegisterRouter.scala:87:24] wire out_rimask_992 = |_out_rimask_T_992; // @[RegisterRouter.scala:87:24] wire out_wimask_992 = &_out_wimask_T_992; // @[RegisterRouter.scala:87:24] wire out_romask_992 = |_out_romask_T_992; // @[RegisterRouter.scala:87:24] wire out_womask_992 = &_out_womask_T_992; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_992 = out_rivalid_1_846 & out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9653 = out_f_rivalid_992; // @[RegisterRouter.scala:87:24] wire out_f_roready_992 = out_roready_1_846 & out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9654 = out_f_roready_992; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_992 = out_wivalid_1_846 & out_wimask_992; // @[RegisterRouter.scala:87:24] wire out_f_woready_992 = out_woready_1_846 & out_womask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9655 = ~out_rimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9656 = ~out_wimask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9657 = ~out_romask_992; // @[RegisterRouter.scala:87:24] wire _out_T_9658 = ~out_womask_992; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_848 = {hi_140, flags_0_go, _out_prepend_T_848}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9659 = out_prepend_848; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9660 = _out_T_9659; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_849 = _out_T_9660; // @[RegisterRouter.scala:87:24] wire out_rimask_993 = |_out_rimask_T_993; // @[RegisterRouter.scala:87:24] wire out_wimask_993 = &_out_wimask_T_993; // @[RegisterRouter.scala:87:24] wire out_romask_993 = |_out_romask_T_993; // @[RegisterRouter.scala:87:24] wire out_womask_993 = &_out_womask_T_993; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_993 = out_rivalid_1_847 & out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9662 = out_f_rivalid_993; // @[RegisterRouter.scala:87:24] wire out_f_roready_993 = out_roready_1_847 & out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9663 = out_f_roready_993; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_993 = out_wivalid_1_847 & out_wimask_993; // @[RegisterRouter.scala:87:24] wire out_f_woready_993 = out_woready_1_847 & out_womask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9664 = ~out_rimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9665 = ~out_wimask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9666 = ~out_romask_993; // @[RegisterRouter.scala:87:24] wire _out_T_9667 = ~out_womask_993; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_849 = {hi_141, flags_0_go, _out_prepend_T_849}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9668 = out_prepend_849; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9669 = _out_T_9668; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_850 = _out_T_9669; // @[RegisterRouter.scala:87:24] wire out_rimask_994 = |_out_rimask_T_994; // @[RegisterRouter.scala:87:24] wire out_wimask_994 = &_out_wimask_T_994; // @[RegisterRouter.scala:87:24] wire out_romask_994 = |_out_romask_T_994; // @[RegisterRouter.scala:87:24] wire out_womask_994 = &_out_womask_T_994; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_994 = out_rivalid_1_848 & out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9671 = out_f_rivalid_994; // @[RegisterRouter.scala:87:24] wire out_f_roready_994 = out_roready_1_848 & out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9672 = out_f_roready_994; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_994 = out_wivalid_1_848 & out_wimask_994; // @[RegisterRouter.scala:87:24] wire out_f_woready_994 = out_woready_1_848 & out_womask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9673 = ~out_rimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9674 = ~out_wimask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9675 = ~out_romask_994; // @[RegisterRouter.scala:87:24] wire _out_T_9676 = ~out_womask_994; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_850 = {hi_142, flags_0_go, _out_prepend_T_850}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9677 = out_prepend_850; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9678 = _out_T_9677; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_851 = _out_T_9678; // @[RegisterRouter.scala:87:24] wire out_rimask_995 = |_out_rimask_T_995; // @[RegisterRouter.scala:87:24] wire out_wimask_995 = &_out_wimask_T_995; // @[RegisterRouter.scala:87:24] wire out_romask_995 = |_out_romask_T_995; // @[RegisterRouter.scala:87:24] wire out_womask_995 = &_out_womask_T_995; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_995 = out_rivalid_1_849 & out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9680 = out_f_rivalid_995; // @[RegisterRouter.scala:87:24] wire out_f_roready_995 = out_roready_1_849 & out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9681 = out_f_roready_995; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_995 = out_wivalid_1_849 & out_wimask_995; // @[RegisterRouter.scala:87:24] wire out_f_woready_995 = out_woready_1_849 & out_womask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9682 = ~out_rimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9683 = ~out_wimask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9684 = ~out_romask_995; // @[RegisterRouter.scala:87:24] wire _out_T_9685 = ~out_womask_995; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_851 = {hi_143, flags_0_go, _out_prepend_T_851}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9686 = out_prepend_851; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9687 = _out_T_9686; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_852 = _out_T_9687; // @[RegisterRouter.scala:87:24] wire out_rimask_996 = |_out_rimask_T_996; // @[RegisterRouter.scala:87:24] wire out_wimask_996 = &_out_wimask_T_996; // @[RegisterRouter.scala:87:24] wire out_romask_996 = |_out_romask_T_996; // @[RegisterRouter.scala:87:24] wire out_womask_996 = &_out_womask_T_996; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_996 = out_rivalid_1_850 & out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9689 = out_f_rivalid_996; // @[RegisterRouter.scala:87:24] wire out_f_roready_996 = out_roready_1_850 & out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9690 = out_f_roready_996; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_996 = out_wivalid_1_850 & out_wimask_996; // @[RegisterRouter.scala:87:24] wire out_f_woready_996 = out_woready_1_850 & out_womask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9691 = ~out_rimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9692 = ~out_wimask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9693 = ~out_romask_996; // @[RegisterRouter.scala:87:24] wire _out_T_9694 = ~out_womask_996; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_852 = {hi_144, flags_0_go, _out_prepend_T_852}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9695 = out_prepend_852; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9696 = _out_T_9695; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_145 = _out_T_9696; // @[MuxLiteral.scala:49:48] wire out_rimask_997 = |_out_rimask_T_997; // @[RegisterRouter.scala:87:24] wire out_wimask_997 = &_out_wimask_T_997; // @[RegisterRouter.scala:87:24] wire out_romask_997 = |_out_romask_T_997; // @[RegisterRouter.scala:87:24] wire out_womask_997 = &_out_womask_T_997; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_997 = out_rivalid_1_851 & out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9698 = out_f_rivalid_997; // @[RegisterRouter.scala:87:24] wire out_f_roready_997 = out_roready_1_851 & out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9699 = out_f_roready_997; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_997 = out_wivalid_1_851 & out_wimask_997; // @[RegisterRouter.scala:87:24] wire out_f_woready_997 = out_woready_1_851 & out_womask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9700 = ~out_rimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9701 = ~out_wimask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9702 = ~out_romask_997; // @[RegisterRouter.scala:87:24] wire _out_T_9703 = ~out_womask_997; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9705 = _out_T_9704; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_853 = _out_T_9705; // @[RegisterRouter.scala:87:24] wire out_rimask_998 = |_out_rimask_T_998; // @[RegisterRouter.scala:87:24] wire out_wimask_998 = &_out_wimask_T_998; // @[RegisterRouter.scala:87:24] wire out_romask_998 = |_out_romask_T_998; // @[RegisterRouter.scala:87:24] wire out_womask_998 = &_out_womask_T_998; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_998 = out_rivalid_1_852 & out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9707 = out_f_rivalid_998; // @[RegisterRouter.scala:87:24] wire out_f_roready_998 = out_roready_1_852 & out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9708 = out_f_roready_998; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_998 = out_wivalid_1_852 & out_wimask_998; // @[RegisterRouter.scala:87:24] wire out_f_woready_998 = out_woready_1_852 & out_womask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9709 = ~out_rimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9710 = ~out_wimask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9711 = ~out_romask_998; // @[RegisterRouter.scala:87:24] wire _out_T_9712 = ~out_womask_998; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_853 = {hi_178, flags_0_go, _out_prepend_T_853}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9713 = out_prepend_853; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9714 = _out_T_9713; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_854 = _out_T_9714; // @[RegisterRouter.scala:87:24] wire out_rimask_999 = |_out_rimask_T_999; // @[RegisterRouter.scala:87:24] wire out_wimask_999 = &_out_wimask_T_999; // @[RegisterRouter.scala:87:24] wire out_romask_999 = |_out_romask_T_999; // @[RegisterRouter.scala:87:24] wire out_womask_999 = &_out_womask_T_999; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_999 = out_rivalid_1_853 & out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9716 = out_f_rivalid_999; // @[RegisterRouter.scala:87:24] wire out_f_roready_999 = out_roready_1_853 & out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9717 = out_f_roready_999; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_999 = out_wivalid_1_853 & out_wimask_999; // @[RegisterRouter.scala:87:24] wire out_f_woready_999 = out_woready_1_853 & out_womask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9718 = ~out_rimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9719 = ~out_wimask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9720 = ~out_romask_999; // @[RegisterRouter.scala:87:24] wire _out_T_9721 = ~out_womask_999; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_854 = {hi_179, flags_0_go, _out_prepend_T_854}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9722 = out_prepend_854; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9723 = _out_T_9722; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_855 = _out_T_9723; // @[RegisterRouter.scala:87:24] wire out_rimask_1000 = |_out_rimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_wimask_1000 = &_out_wimask_T_1000; // @[RegisterRouter.scala:87:24] wire out_romask_1000 = |_out_romask_T_1000; // @[RegisterRouter.scala:87:24] wire out_womask_1000 = &_out_womask_T_1000; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1000 = out_rivalid_1_854 & out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9725 = out_f_rivalid_1000; // @[RegisterRouter.scala:87:24] wire out_f_roready_1000 = out_roready_1_854 & out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9726 = out_f_roready_1000; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1000 = out_wivalid_1_854 & out_wimask_1000; // @[RegisterRouter.scala:87:24] wire out_f_woready_1000 = out_woready_1_854 & out_womask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9727 = ~out_rimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9728 = ~out_wimask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9729 = ~out_romask_1000; // @[RegisterRouter.scala:87:24] wire _out_T_9730 = ~out_womask_1000; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_855 = {hi_180, flags_0_go, _out_prepend_T_855}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9731 = out_prepend_855; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9732 = _out_T_9731; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_856 = _out_T_9732; // @[RegisterRouter.scala:87:24] wire out_rimask_1001 = |_out_rimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_wimask_1001 = &_out_wimask_T_1001; // @[RegisterRouter.scala:87:24] wire out_romask_1001 = |_out_romask_T_1001; // @[RegisterRouter.scala:87:24] wire out_womask_1001 = &_out_womask_T_1001; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1001 = out_rivalid_1_855 & out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9734 = out_f_rivalid_1001; // @[RegisterRouter.scala:87:24] wire out_f_roready_1001 = out_roready_1_855 & out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9735 = out_f_roready_1001; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1001 = out_wivalid_1_855 & out_wimask_1001; // @[RegisterRouter.scala:87:24] wire out_f_woready_1001 = out_woready_1_855 & out_womask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9736 = ~out_rimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9737 = ~out_wimask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9738 = ~out_romask_1001; // @[RegisterRouter.scala:87:24] wire _out_T_9739 = ~out_womask_1001; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_856 = {hi_181, flags_0_go, _out_prepend_T_856}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9740 = out_prepend_856; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9741 = _out_T_9740; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_857 = _out_T_9741; // @[RegisterRouter.scala:87:24] wire out_rimask_1002 = |_out_rimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_wimask_1002 = &_out_wimask_T_1002; // @[RegisterRouter.scala:87:24] wire out_romask_1002 = |_out_romask_T_1002; // @[RegisterRouter.scala:87:24] wire out_womask_1002 = &_out_womask_T_1002; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1002 = out_rivalid_1_856 & out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9743 = out_f_rivalid_1002; // @[RegisterRouter.scala:87:24] wire out_f_roready_1002 = out_roready_1_856 & out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9744 = out_f_roready_1002; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1002 = out_wivalid_1_856 & out_wimask_1002; // @[RegisterRouter.scala:87:24] wire out_f_woready_1002 = out_woready_1_856 & out_womask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9745 = ~out_rimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9746 = ~out_wimask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9747 = ~out_romask_1002; // @[RegisterRouter.scala:87:24] wire _out_T_9748 = ~out_womask_1002; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_857 = {hi_182, flags_0_go, _out_prepend_T_857}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9749 = out_prepend_857; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9750 = _out_T_9749; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_858 = _out_T_9750; // @[RegisterRouter.scala:87:24] wire out_rimask_1003 = |_out_rimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_wimask_1003 = &_out_wimask_T_1003; // @[RegisterRouter.scala:87:24] wire out_romask_1003 = |_out_romask_T_1003; // @[RegisterRouter.scala:87:24] wire out_womask_1003 = &_out_womask_T_1003; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1003 = out_rivalid_1_857 & out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9752 = out_f_rivalid_1003; // @[RegisterRouter.scala:87:24] wire out_f_roready_1003 = out_roready_1_857 & out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9753 = out_f_roready_1003; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1003 = out_wivalid_1_857 & out_wimask_1003; // @[RegisterRouter.scala:87:24] wire out_f_woready_1003 = out_woready_1_857 & out_womask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9754 = ~out_rimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9755 = ~out_wimask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9756 = ~out_romask_1003; // @[RegisterRouter.scala:87:24] wire _out_T_9757 = ~out_womask_1003; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_858 = {hi_183, flags_0_go, _out_prepend_T_858}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9758 = out_prepend_858; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9759 = _out_T_9758; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_859 = _out_T_9759; // @[RegisterRouter.scala:87:24] wire out_rimask_1004 = |_out_rimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_wimask_1004 = &_out_wimask_T_1004; // @[RegisterRouter.scala:87:24] wire out_romask_1004 = |_out_romask_T_1004; // @[RegisterRouter.scala:87:24] wire out_womask_1004 = &_out_womask_T_1004; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1004 = out_rivalid_1_858 & out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9761 = out_f_rivalid_1004; // @[RegisterRouter.scala:87:24] wire out_f_roready_1004 = out_roready_1_858 & out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9762 = out_f_roready_1004; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1004 = out_wivalid_1_858 & out_wimask_1004; // @[RegisterRouter.scala:87:24] wire out_f_woready_1004 = out_woready_1_858 & out_womask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9763 = ~out_rimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9764 = ~out_wimask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9765 = ~out_romask_1004; // @[RegisterRouter.scala:87:24] wire _out_T_9766 = ~out_womask_1004; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_859 = {hi_184, flags_0_go, _out_prepend_T_859}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9767 = out_prepend_859; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9768 = _out_T_9767; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_150 = _out_T_9768; // @[MuxLiteral.scala:49:48] wire out_rimask_1005 = |_out_rimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_wimask_1005 = &_out_wimask_T_1005; // @[RegisterRouter.scala:87:24] wire out_romask_1005 = |_out_romask_T_1005; // @[RegisterRouter.scala:87:24] wire out_womask_1005 = &_out_womask_T_1005; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1005 = out_rivalid_1_859 & out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9770 = out_f_rivalid_1005; // @[RegisterRouter.scala:87:24] wire out_f_roready_1005 = out_roready_1_859 & out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9771 = out_f_roready_1005; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1005 = out_wivalid_1_859 & out_wimask_1005; // @[RegisterRouter.scala:87:24] wire out_f_woready_1005 = out_woready_1_859 & out_womask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9772 = ~out_rimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9773 = ~out_wimask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9774 = ~out_romask_1005; // @[RegisterRouter.scala:87:24] wire _out_T_9775 = ~out_womask_1005; // @[RegisterRouter.scala:87:24] wire out_rimask_1006 = |_out_rimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_wimask_1006 = &_out_wimask_T_1006; // @[RegisterRouter.scala:87:24] wire out_romask_1006 = |_out_romask_T_1006; // @[RegisterRouter.scala:87:24] wire out_womask_1006 = &_out_womask_T_1006; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1006 = out_rivalid_1_860 & out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9779 = out_f_rivalid_1006; // @[RegisterRouter.scala:87:24] wire out_f_roready_1006 = out_roready_1_860 & out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9780 = out_f_roready_1006; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1006 = out_wivalid_1_860 & out_wimask_1006; // @[RegisterRouter.scala:87:24] wire out_f_woready_1006 = out_woready_1_860 & out_womask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9781 = ~out_rimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9782 = ~out_wimask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9783 = ~out_romask_1006; // @[RegisterRouter.scala:87:24] wire _out_T_9784 = ~out_womask_1006; // @[RegisterRouter.scala:87:24] wire out_rimask_1007 = |_out_rimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_wimask_1007 = &_out_wimask_T_1007; // @[RegisterRouter.scala:87:24] wire out_romask_1007 = |_out_romask_T_1007; // @[RegisterRouter.scala:87:24] wire out_womask_1007 = &_out_womask_T_1007; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1007 = out_rivalid_1_861 & out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9788 = out_f_rivalid_1007; // @[RegisterRouter.scala:87:24] wire out_f_roready_1007 = out_roready_1_861 & out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9789 = out_f_roready_1007; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1007 = out_wivalid_1_861 & out_wimask_1007; // @[RegisterRouter.scala:87:24] wire out_f_woready_1007 = out_woready_1_861 & out_womask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9790 = ~out_rimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9791 = ~out_wimask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9792 = ~out_romask_1007; // @[RegisterRouter.scala:87:24] wire _out_T_9793 = ~out_womask_1007; // @[RegisterRouter.scala:87:24] wire out_rimask_1008 = |_out_rimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_wimask_1008 = &_out_wimask_T_1008; // @[RegisterRouter.scala:87:24] wire out_romask_1008 = |_out_romask_T_1008; // @[RegisterRouter.scala:87:24] wire out_womask_1008 = &_out_womask_T_1008; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1008 = out_rivalid_1_862 & out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9797 = out_f_rivalid_1008; // @[RegisterRouter.scala:87:24] wire out_f_roready_1008 = out_roready_1_862 & out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9798 = out_f_roready_1008; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1008 = out_wivalid_1_862 & out_wimask_1008; // @[RegisterRouter.scala:87:24] wire out_f_woready_1008 = out_woready_1_862 & out_womask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9799 = ~out_rimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9800 = ~out_wimask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9801 = ~out_romask_1008; // @[RegisterRouter.scala:87:24] wire _out_T_9802 = ~out_womask_1008; // @[RegisterRouter.scala:87:24] wire out_rimask_1009 = |_out_rimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_wimask_1009 = &_out_wimask_T_1009; // @[RegisterRouter.scala:87:24] wire out_romask_1009 = |_out_romask_T_1009; // @[RegisterRouter.scala:87:24] wire out_womask_1009 = &_out_womask_T_1009; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1009 = out_rivalid_1_863 & out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9806 = out_f_rivalid_1009; // @[RegisterRouter.scala:87:24] wire out_f_roready_1009 = out_roready_1_863 & out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9807 = out_f_roready_1009; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1009 = out_wivalid_1_863 & out_wimask_1009; // @[RegisterRouter.scala:87:24] wire out_f_woready_1009 = out_woready_1_863 & out_womask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9808 = ~out_rimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9809 = ~out_wimask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9810 = ~out_romask_1009; // @[RegisterRouter.scala:87:24] wire _out_T_9811 = ~out_womask_1009; // @[RegisterRouter.scala:87:24] wire out_rimask_1010 = |_out_rimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_wimask_1010 = &_out_wimask_T_1010; // @[RegisterRouter.scala:87:24] wire out_romask_1010 = |_out_romask_T_1010; // @[RegisterRouter.scala:87:24] wire out_womask_1010 = &_out_womask_T_1010; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1010 = out_rivalid_1_864 & out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9815 = out_f_rivalid_1010; // @[RegisterRouter.scala:87:24] wire out_f_roready_1010 = out_roready_1_864 & out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9816 = out_f_roready_1010; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1010 = out_wivalid_1_864 & out_wimask_1010; // @[RegisterRouter.scala:87:24] wire out_f_woready_1010 = out_woready_1_864 & out_womask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9817 = ~out_rimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9818 = ~out_wimask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9819 = ~out_romask_1010; // @[RegisterRouter.scala:87:24] wire _out_T_9820 = ~out_womask_1010; // @[RegisterRouter.scala:87:24] wire out_rimask_1011 = |_out_rimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_wimask_1011 = &_out_wimask_T_1011; // @[RegisterRouter.scala:87:24] wire out_romask_1011 = |_out_romask_T_1011; // @[RegisterRouter.scala:87:24] wire out_womask_1011 = &_out_womask_T_1011; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1011 = out_rivalid_1_865 & out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9824 = out_f_rivalid_1011; // @[RegisterRouter.scala:87:24] wire out_f_roready_1011 = out_roready_1_865 & out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9825 = out_f_roready_1011; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1011 = out_wivalid_1_865 & out_wimask_1011; // @[RegisterRouter.scala:87:24] wire out_f_woready_1011 = out_woready_1_865 & out_womask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9826 = ~out_rimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9827 = ~out_wimask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9828 = ~out_romask_1011; // @[RegisterRouter.scala:87:24] wire _out_T_9829 = ~out_womask_1011; // @[RegisterRouter.scala:87:24] wire out_rimask_1012 = |_out_rimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_wimask_1012 = &_out_wimask_T_1012; // @[RegisterRouter.scala:87:24] wire out_romask_1012 = |_out_romask_T_1012; // @[RegisterRouter.scala:87:24] wire out_womask_1012 = &_out_womask_T_1012; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1012 = out_rivalid_1_866 & out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9833 = out_f_rivalid_1012; // @[RegisterRouter.scala:87:24] wire out_f_roready_1012 = out_roready_1_866 & out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9834 = out_f_roready_1012; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1012 = out_wivalid_1_866 & out_wimask_1012; // @[RegisterRouter.scala:87:24] wire out_f_woready_1012 = out_woready_1_866 & out_womask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9835 = ~out_rimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9836 = ~out_wimask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9837 = ~out_romask_1012; // @[RegisterRouter.scala:87:24] wire _out_T_9838 = ~out_womask_1012; // @[RegisterRouter.scala:87:24] wire out_rimask_1013 = |_out_rimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_wimask_1013 = &_out_wimask_T_1013; // @[RegisterRouter.scala:87:24] wire out_romask_1013 = |_out_romask_T_1013; // @[RegisterRouter.scala:87:24] wire out_womask_1013 = &_out_womask_T_1013; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1013 = out_rivalid_1_867 & out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9842 = out_f_rivalid_1013; // @[RegisterRouter.scala:87:24] wire out_f_roready_1013 = out_roready_1_867 & out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9843 = out_f_roready_1013; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1013 = out_wivalid_1_867 & out_wimask_1013; // @[RegisterRouter.scala:87:24] wire out_f_woready_1013 = out_woready_1_867 & out_womask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9844 = ~out_rimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9845 = ~out_wimask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9846 = ~out_romask_1013; // @[RegisterRouter.scala:87:24] wire _out_T_9847 = ~out_womask_1013; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9849 = _out_T_9848; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_867 = _out_T_9849; // @[RegisterRouter.scala:87:24] wire out_rimask_1014 = |_out_rimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_wimask_1014 = &_out_wimask_T_1014; // @[RegisterRouter.scala:87:24] wire out_romask_1014 = |_out_romask_T_1014; // @[RegisterRouter.scala:87:24] wire out_womask_1014 = &_out_womask_T_1014; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1014 = out_rivalid_1_868 & out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9851 = out_f_rivalid_1014; // @[RegisterRouter.scala:87:24] wire out_f_roready_1014 = out_roready_1_868 & out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9852 = out_f_roready_1014; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1014 = out_wivalid_1_868 & out_wimask_1014; // @[RegisterRouter.scala:87:24] wire out_f_woready_1014 = out_woready_1_868 & out_womask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9853 = ~out_rimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9854 = ~out_wimask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9855 = ~out_romask_1014; // @[RegisterRouter.scala:87:24] wire _out_T_9856 = ~out_womask_1014; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_867 = {hi_570, flags_0_go, _out_prepend_T_867}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9857 = out_prepend_867; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9858 = _out_T_9857; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_868 = _out_T_9858; // @[RegisterRouter.scala:87:24] wire out_rimask_1015 = |_out_rimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_wimask_1015 = &_out_wimask_T_1015; // @[RegisterRouter.scala:87:24] wire out_romask_1015 = |_out_romask_T_1015; // @[RegisterRouter.scala:87:24] wire out_womask_1015 = &_out_womask_T_1015; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1015 = out_rivalid_1_869 & out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9860 = out_f_rivalid_1015; // @[RegisterRouter.scala:87:24] wire out_f_roready_1015 = out_roready_1_869 & out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9861 = out_f_roready_1015; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1015 = out_wivalid_1_869 & out_wimask_1015; // @[RegisterRouter.scala:87:24] wire out_f_woready_1015 = out_woready_1_869 & out_womask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9862 = ~out_rimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9863 = ~out_wimask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9864 = ~out_romask_1015; // @[RegisterRouter.scala:87:24] wire _out_T_9865 = ~out_womask_1015; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_868 = {hi_571, flags_0_go, _out_prepend_T_868}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9866 = out_prepend_868; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9867 = _out_T_9866; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_869 = _out_T_9867; // @[RegisterRouter.scala:87:24] wire out_rimask_1016 = |_out_rimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_wimask_1016 = &_out_wimask_T_1016; // @[RegisterRouter.scala:87:24] wire out_romask_1016 = |_out_romask_T_1016; // @[RegisterRouter.scala:87:24] wire out_womask_1016 = &_out_womask_T_1016; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1016 = out_rivalid_1_870 & out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9869 = out_f_rivalid_1016; // @[RegisterRouter.scala:87:24] wire out_f_roready_1016 = out_roready_1_870 & out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9870 = out_f_roready_1016; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1016 = out_wivalid_1_870 & out_wimask_1016; // @[RegisterRouter.scala:87:24] wire out_f_woready_1016 = out_woready_1_870 & out_womask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9871 = ~out_rimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9872 = ~out_wimask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9873 = ~out_romask_1016; // @[RegisterRouter.scala:87:24] wire _out_T_9874 = ~out_womask_1016; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_869 = {hi_572, flags_0_go, _out_prepend_T_869}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9875 = out_prepend_869; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9876 = _out_T_9875; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_870 = _out_T_9876; // @[RegisterRouter.scala:87:24] wire out_rimask_1017 = |_out_rimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_wimask_1017 = &_out_wimask_T_1017; // @[RegisterRouter.scala:87:24] wire out_romask_1017 = |_out_romask_T_1017; // @[RegisterRouter.scala:87:24] wire out_womask_1017 = &_out_womask_T_1017; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1017 = out_rivalid_1_871 & out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9878 = out_f_rivalid_1017; // @[RegisterRouter.scala:87:24] wire out_f_roready_1017 = out_roready_1_871 & out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9879 = out_f_roready_1017; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1017 = out_wivalid_1_871 & out_wimask_1017; // @[RegisterRouter.scala:87:24] wire out_f_woready_1017 = out_woready_1_871 & out_womask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9880 = ~out_rimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9881 = ~out_wimask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9882 = ~out_romask_1017; // @[RegisterRouter.scala:87:24] wire _out_T_9883 = ~out_womask_1017; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_870 = {hi_573, flags_0_go, _out_prepend_T_870}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9884 = out_prepend_870; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9885 = _out_T_9884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_871 = _out_T_9885; // @[RegisterRouter.scala:87:24] wire out_rimask_1018 = |_out_rimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_wimask_1018 = &_out_wimask_T_1018; // @[RegisterRouter.scala:87:24] wire out_romask_1018 = |_out_romask_T_1018; // @[RegisterRouter.scala:87:24] wire out_womask_1018 = &_out_womask_T_1018; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1018 = out_rivalid_1_872 & out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9887 = out_f_rivalid_1018; // @[RegisterRouter.scala:87:24] wire out_f_roready_1018 = out_roready_1_872 & out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9888 = out_f_roready_1018; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1018 = out_wivalid_1_872 & out_wimask_1018; // @[RegisterRouter.scala:87:24] wire out_f_woready_1018 = out_woready_1_872 & out_womask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9889 = ~out_rimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9890 = ~out_wimask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9891 = ~out_romask_1018; // @[RegisterRouter.scala:87:24] wire _out_T_9892 = ~out_womask_1018; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_871 = {hi_574, flags_0_go, _out_prepend_T_871}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9893 = out_prepend_871; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9894 = _out_T_9893; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_872 = _out_T_9894; // @[RegisterRouter.scala:87:24] wire out_rimask_1019 = |_out_rimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_wimask_1019 = &_out_wimask_T_1019; // @[RegisterRouter.scala:87:24] wire out_romask_1019 = |_out_romask_T_1019; // @[RegisterRouter.scala:87:24] wire out_womask_1019 = &_out_womask_T_1019; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1019 = out_rivalid_1_873 & out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9896 = out_f_rivalid_1019; // @[RegisterRouter.scala:87:24] wire out_f_roready_1019 = out_roready_1_873 & out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9897 = out_f_roready_1019; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1019 = out_wivalid_1_873 & out_wimask_1019; // @[RegisterRouter.scala:87:24] wire out_f_woready_1019 = out_woready_1_873 & out_womask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9898 = ~out_rimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9899 = ~out_wimask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9900 = ~out_romask_1019; // @[RegisterRouter.scala:87:24] wire _out_T_9901 = ~out_womask_1019; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_872 = {hi_575, flags_0_go, _out_prepend_T_872}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9902 = out_prepend_872; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9903 = _out_T_9902; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_873 = _out_T_9903; // @[RegisterRouter.scala:87:24] wire out_rimask_1020 = |_out_rimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_wimask_1020 = &_out_wimask_T_1020; // @[RegisterRouter.scala:87:24] wire out_romask_1020 = |_out_romask_T_1020; // @[RegisterRouter.scala:87:24] wire out_womask_1020 = &_out_womask_T_1020; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1020 = out_rivalid_1_874 & out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9905 = out_f_rivalid_1020; // @[RegisterRouter.scala:87:24] wire out_f_roready_1020 = out_roready_1_874 & out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9906 = out_f_roready_1020; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1020 = out_wivalid_1_874 & out_wimask_1020; // @[RegisterRouter.scala:87:24] wire out_f_woready_1020 = out_woready_1_874 & out_womask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9907 = ~out_rimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9908 = ~out_wimask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9909 = ~out_romask_1020; // @[RegisterRouter.scala:87:24] wire _out_T_9910 = ~out_womask_1020; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_873 = {hi_576, flags_0_go, _out_prepend_T_873}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9911 = out_prepend_873; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9912 = _out_T_9911; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_199 = _out_T_9912; // @[MuxLiteral.scala:49:48] wire out_rimask_1021 = |_out_rimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_wimask_1021 = &_out_wimask_T_1021; // @[RegisterRouter.scala:87:24] wire out_romask_1021 = |_out_romask_T_1021; // @[RegisterRouter.scala:87:24] wire out_womask_1021 = &_out_womask_T_1021; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1021 = out_rivalid_1_875 & out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9914 = out_f_rivalid_1021; // @[RegisterRouter.scala:87:24] wire out_f_roready_1021 = out_roready_1_875 & out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9915 = out_f_roready_1021; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1021 = out_wivalid_1_875 & out_wimask_1021; // @[RegisterRouter.scala:87:24] wire out_f_woready_1021 = out_woready_1_875 & out_womask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9916 = ~out_rimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9917 = ~out_wimask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9918 = ~out_romask_1021; // @[RegisterRouter.scala:87:24] wire _out_T_9919 = ~out_womask_1021; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9921 = _out_T_9920; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_874 = _out_T_9921; // @[RegisterRouter.scala:87:24] wire out_rimask_1022 = |_out_rimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_wimask_1022 = &_out_wimask_T_1022; // @[RegisterRouter.scala:87:24] wire out_romask_1022 = |_out_romask_T_1022; // @[RegisterRouter.scala:87:24] wire out_womask_1022 = &_out_womask_T_1022; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1022 = out_rivalid_1_876 & out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9923 = out_f_rivalid_1022; // @[RegisterRouter.scala:87:24] wire out_f_roready_1022 = out_roready_1_876 & out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9924 = out_f_roready_1022; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1022 = out_wivalid_1_876 & out_wimask_1022; // @[RegisterRouter.scala:87:24] wire out_f_woready_1022 = out_woready_1_876 & out_womask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9925 = ~out_rimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9926 = ~out_wimask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9927 = ~out_romask_1022; // @[RegisterRouter.scala:87:24] wire _out_T_9928 = ~out_womask_1022; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_874 = {hi_394, flags_0_go, _out_prepend_T_874}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9929 = out_prepend_874; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_9930 = _out_T_9929; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_875 = _out_T_9930; // @[RegisterRouter.scala:87:24] wire out_rimask_1023 = |_out_rimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_wimask_1023 = &_out_wimask_T_1023; // @[RegisterRouter.scala:87:24] wire out_romask_1023 = |_out_romask_T_1023; // @[RegisterRouter.scala:87:24] wire out_womask_1023 = &_out_womask_T_1023; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1023 = out_rivalid_1_877 & out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9932 = out_f_rivalid_1023; // @[RegisterRouter.scala:87:24] wire out_f_roready_1023 = out_roready_1_877 & out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9933 = out_f_roready_1023; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1023 = out_wivalid_1_877 & out_wimask_1023; // @[RegisterRouter.scala:87:24] wire out_f_woready_1023 = out_woready_1_877 & out_womask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9934 = ~out_rimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9935 = ~out_wimask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9936 = ~out_romask_1023; // @[RegisterRouter.scala:87:24] wire _out_T_9937 = ~out_womask_1023; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_875 = {hi_395, flags_0_go, _out_prepend_T_875}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9938 = out_prepend_875; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_9939 = _out_T_9938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_876 = _out_T_9939; // @[RegisterRouter.scala:87:24] wire out_rimask_1024 = |_out_rimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_wimask_1024 = &_out_wimask_T_1024; // @[RegisterRouter.scala:87:24] wire out_romask_1024 = |_out_romask_T_1024; // @[RegisterRouter.scala:87:24] wire out_womask_1024 = &_out_womask_T_1024; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1024 = out_rivalid_1_878 & out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9941 = out_f_rivalid_1024; // @[RegisterRouter.scala:87:24] wire out_f_roready_1024 = out_roready_1_878 & out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9942 = out_f_roready_1024; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1024 = out_wivalid_1_878 & out_wimask_1024; // @[RegisterRouter.scala:87:24] wire out_f_woready_1024 = out_woready_1_878 & out_womask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9943 = ~out_rimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9944 = ~out_wimask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9945 = ~out_romask_1024; // @[RegisterRouter.scala:87:24] wire _out_T_9946 = ~out_womask_1024; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_876 = {hi_396, flags_0_go, _out_prepend_T_876}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9947 = out_prepend_876; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_9948 = _out_T_9947; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_877 = _out_T_9948; // @[RegisterRouter.scala:87:24] wire out_rimask_1025 = |_out_rimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_wimask_1025 = &_out_wimask_T_1025; // @[RegisterRouter.scala:87:24] wire out_romask_1025 = |_out_romask_T_1025; // @[RegisterRouter.scala:87:24] wire out_womask_1025 = &_out_womask_T_1025; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1025 = out_rivalid_1_879 & out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9950 = out_f_rivalid_1025; // @[RegisterRouter.scala:87:24] wire out_f_roready_1025 = out_roready_1_879 & out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9951 = out_f_roready_1025; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1025 = out_wivalid_1_879 & out_wimask_1025; // @[RegisterRouter.scala:87:24] wire out_f_woready_1025 = out_woready_1_879 & out_womask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9952 = ~out_rimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9953 = ~out_wimask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9954 = ~out_romask_1025; // @[RegisterRouter.scala:87:24] wire _out_T_9955 = ~out_womask_1025; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_877 = {hi_397, flags_0_go, _out_prepend_T_877}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9956 = out_prepend_877; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_9957 = _out_T_9956; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_878 = _out_T_9957; // @[RegisterRouter.scala:87:24] wire out_rimask_1026 = |_out_rimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_wimask_1026 = &_out_wimask_T_1026; // @[RegisterRouter.scala:87:24] wire out_romask_1026 = |_out_romask_T_1026; // @[RegisterRouter.scala:87:24] wire out_womask_1026 = &_out_womask_T_1026; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1026 = out_rivalid_1_880 & out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9959 = out_f_rivalid_1026; // @[RegisterRouter.scala:87:24] wire out_f_roready_1026 = out_roready_1_880 & out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9960 = out_f_roready_1026; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1026 = out_wivalid_1_880 & out_wimask_1026; // @[RegisterRouter.scala:87:24] wire out_f_woready_1026 = out_woready_1_880 & out_womask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9961 = ~out_rimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9962 = ~out_wimask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9963 = ~out_romask_1026; // @[RegisterRouter.scala:87:24] wire _out_T_9964 = ~out_womask_1026; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_878 = {hi_398, flags_0_go, _out_prepend_T_878}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9965 = out_prepend_878; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_9966 = _out_T_9965; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_879 = _out_T_9966; // @[RegisterRouter.scala:87:24] wire out_rimask_1027 = |_out_rimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_wimask_1027 = &_out_wimask_T_1027; // @[RegisterRouter.scala:87:24] wire out_romask_1027 = |_out_romask_T_1027; // @[RegisterRouter.scala:87:24] wire out_womask_1027 = &_out_womask_T_1027; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1027 = out_rivalid_1_881 & out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9968 = out_f_rivalid_1027; // @[RegisterRouter.scala:87:24] wire out_f_roready_1027 = out_roready_1_881 & out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9969 = out_f_roready_1027; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1027 = out_wivalid_1_881 & out_wimask_1027; // @[RegisterRouter.scala:87:24] wire out_f_woready_1027 = out_woready_1_881 & out_womask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9970 = ~out_rimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9971 = ~out_wimask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9972 = ~out_romask_1027; // @[RegisterRouter.scala:87:24] wire _out_T_9973 = ~out_womask_1027; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_879 = {hi_399, flags_0_go, _out_prepend_T_879}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9974 = out_prepend_879; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_9975 = _out_T_9974; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_880 = _out_T_9975; // @[RegisterRouter.scala:87:24] wire out_rimask_1028 = |_out_rimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_wimask_1028 = &_out_wimask_T_1028; // @[RegisterRouter.scala:87:24] wire out_romask_1028 = |_out_romask_T_1028; // @[RegisterRouter.scala:87:24] wire out_womask_1028 = &_out_womask_T_1028; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1028 = out_rivalid_1_882 & out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9977 = out_f_rivalid_1028; // @[RegisterRouter.scala:87:24] wire out_f_roready_1028 = out_roready_1_882 & out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9978 = out_f_roready_1028; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1028 = out_wivalid_1_882 & out_wimask_1028; // @[RegisterRouter.scala:87:24] wire out_f_woready_1028 = out_woready_1_882 & out_womask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9979 = ~out_rimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9980 = ~out_wimask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9981 = ~out_romask_1028; // @[RegisterRouter.scala:87:24] wire _out_T_9982 = ~out_womask_1028; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_880 = {hi_400, flags_0_go, _out_prepend_T_880}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9983 = out_prepend_880; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_9984 = _out_T_9983; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_177 = _out_T_9984; // @[MuxLiteral.scala:49:48] wire out_rimask_1029 = |_out_rimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_wimask_1029 = &_out_wimask_T_1029; // @[RegisterRouter.scala:87:24] wire out_romask_1029 = |_out_romask_T_1029; // @[RegisterRouter.scala:87:24] wire out_womask_1029 = &_out_womask_T_1029; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1029 = out_rivalid_1_883 & out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9986 = out_f_rivalid_1029; // @[RegisterRouter.scala:87:24] wire out_f_roready_1029 = out_roready_1_883 & out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9987 = out_f_roready_1029; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1029 = out_wivalid_1_883 & out_wimask_1029; // @[RegisterRouter.scala:87:24] wire out_f_woready_1029 = out_woready_1_883 & out_womask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9988 = ~out_rimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9989 = ~out_wimask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9990 = ~out_romask_1029; // @[RegisterRouter.scala:87:24] wire _out_T_9991 = ~out_womask_1029; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_9993 = _out_T_9992; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_881 = _out_T_9993; // @[RegisterRouter.scala:87:24] wire out_rimask_1030 = |_out_rimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_wimask_1030 = &_out_wimask_T_1030; // @[RegisterRouter.scala:87:24] wire out_romask_1030 = |_out_romask_T_1030; // @[RegisterRouter.scala:87:24] wire out_womask_1030 = &_out_womask_T_1030; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1030 = out_rivalid_1_884 & out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9995 = out_f_rivalid_1030; // @[RegisterRouter.scala:87:24] wire out_f_roready_1030 = out_roready_1_884 & out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9996 = out_f_roready_1030; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1030 = out_wivalid_1_884 & out_wimask_1030; // @[RegisterRouter.scala:87:24] wire out_f_woready_1030 = out_woready_1_884 & out_womask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9997 = ~out_rimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9998 = ~out_wimask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_9999 = ~out_romask_1030; // @[RegisterRouter.scala:87:24] wire _out_T_10000 = ~out_womask_1030; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_881 = {hi_434, flags_0_go, _out_prepend_T_881}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10001 = out_prepend_881; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10002 = _out_T_10001; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_882 = _out_T_10002; // @[RegisterRouter.scala:87:24] wire out_rimask_1031 = |_out_rimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_wimask_1031 = &_out_wimask_T_1031; // @[RegisterRouter.scala:87:24] wire out_romask_1031 = |_out_romask_T_1031; // @[RegisterRouter.scala:87:24] wire out_womask_1031 = &_out_womask_T_1031; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1031 = out_rivalid_1_885 & out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10004 = out_f_rivalid_1031; // @[RegisterRouter.scala:87:24] wire out_f_roready_1031 = out_roready_1_885 & out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10005 = out_f_roready_1031; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1031 = out_wivalid_1_885 & out_wimask_1031; // @[RegisterRouter.scala:87:24] wire out_f_woready_1031 = out_woready_1_885 & out_womask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10006 = ~out_rimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10007 = ~out_wimask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10008 = ~out_romask_1031; // @[RegisterRouter.scala:87:24] wire _out_T_10009 = ~out_womask_1031; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_882 = {hi_435, flags_0_go, _out_prepend_T_882}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10010 = out_prepend_882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10011 = _out_T_10010; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_883 = _out_T_10011; // @[RegisterRouter.scala:87:24] wire out_rimask_1032 = |_out_rimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_wimask_1032 = &_out_wimask_T_1032; // @[RegisterRouter.scala:87:24] wire out_romask_1032 = |_out_romask_T_1032; // @[RegisterRouter.scala:87:24] wire out_womask_1032 = &_out_womask_T_1032; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1032 = out_rivalid_1_886 & out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10013 = out_f_rivalid_1032; // @[RegisterRouter.scala:87:24] wire out_f_roready_1032 = out_roready_1_886 & out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10014 = out_f_roready_1032; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1032 = out_wivalid_1_886 & out_wimask_1032; // @[RegisterRouter.scala:87:24] wire out_f_woready_1032 = out_woready_1_886 & out_womask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10015 = ~out_rimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10016 = ~out_wimask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10017 = ~out_romask_1032; // @[RegisterRouter.scala:87:24] wire _out_T_10018 = ~out_womask_1032; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_883 = {hi_436, flags_0_go, _out_prepend_T_883}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10019 = out_prepend_883; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10020 = _out_T_10019; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_884 = _out_T_10020; // @[RegisterRouter.scala:87:24] wire out_rimask_1033 = |_out_rimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_wimask_1033 = &_out_wimask_T_1033; // @[RegisterRouter.scala:87:24] wire out_romask_1033 = |_out_romask_T_1033; // @[RegisterRouter.scala:87:24] wire out_womask_1033 = &_out_womask_T_1033; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1033 = out_rivalid_1_887 & out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10022 = out_f_rivalid_1033; // @[RegisterRouter.scala:87:24] wire out_f_roready_1033 = out_roready_1_887 & out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10023 = out_f_roready_1033; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1033 = out_wivalid_1_887 & out_wimask_1033; // @[RegisterRouter.scala:87:24] wire out_f_woready_1033 = out_woready_1_887 & out_womask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10024 = ~out_rimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10025 = ~out_wimask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10026 = ~out_romask_1033; // @[RegisterRouter.scala:87:24] wire _out_T_10027 = ~out_womask_1033; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_884 = {hi_437, flags_0_go, _out_prepend_T_884}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10028 = out_prepend_884; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10029 = _out_T_10028; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_885 = _out_T_10029; // @[RegisterRouter.scala:87:24] wire out_rimask_1034 = |_out_rimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_wimask_1034 = &_out_wimask_T_1034; // @[RegisterRouter.scala:87:24] wire out_romask_1034 = |_out_romask_T_1034; // @[RegisterRouter.scala:87:24] wire out_womask_1034 = &_out_womask_T_1034; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1034 = out_rivalid_1_888 & out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10031 = out_f_rivalid_1034; // @[RegisterRouter.scala:87:24] wire out_f_roready_1034 = out_roready_1_888 & out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10032 = out_f_roready_1034; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1034 = out_wivalid_1_888 & out_wimask_1034; // @[RegisterRouter.scala:87:24] wire out_f_woready_1034 = out_woready_1_888 & out_womask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10033 = ~out_rimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10034 = ~out_wimask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10035 = ~out_romask_1034; // @[RegisterRouter.scala:87:24] wire _out_T_10036 = ~out_womask_1034; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_885 = {hi_438, flags_0_go, _out_prepend_T_885}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10037 = out_prepend_885; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10038 = _out_T_10037; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_886 = _out_T_10038; // @[RegisterRouter.scala:87:24] wire out_rimask_1035 = |_out_rimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_wimask_1035 = &_out_wimask_T_1035; // @[RegisterRouter.scala:87:24] wire out_romask_1035 = |_out_romask_T_1035; // @[RegisterRouter.scala:87:24] wire out_womask_1035 = &_out_womask_T_1035; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1035 = out_rivalid_1_889 & out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10040 = out_f_rivalid_1035; // @[RegisterRouter.scala:87:24] wire out_f_roready_1035 = out_roready_1_889 & out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10041 = out_f_roready_1035; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1035 = out_wivalid_1_889 & out_wimask_1035; // @[RegisterRouter.scala:87:24] wire out_f_woready_1035 = out_woready_1_889 & out_womask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10042 = ~out_rimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10043 = ~out_wimask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10044 = ~out_romask_1035; // @[RegisterRouter.scala:87:24] wire _out_T_10045 = ~out_womask_1035; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_886 = {hi_439, flags_0_go, _out_prepend_T_886}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10046 = out_prepend_886; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10047 = _out_T_10046; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_887 = _out_T_10047; // @[RegisterRouter.scala:87:24] wire out_rimask_1036 = |_out_rimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_wimask_1036 = &_out_wimask_T_1036; // @[RegisterRouter.scala:87:24] wire out_romask_1036 = |_out_romask_T_1036; // @[RegisterRouter.scala:87:24] wire out_womask_1036 = &_out_womask_T_1036; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1036 = out_rivalid_1_890 & out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10049 = out_f_rivalid_1036; // @[RegisterRouter.scala:87:24] wire out_f_roready_1036 = out_roready_1_890 & out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10050 = out_f_roready_1036; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1036 = out_wivalid_1_890 & out_wimask_1036; // @[RegisterRouter.scala:87:24] wire out_f_woready_1036 = out_woready_1_890 & out_womask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10051 = ~out_rimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10052 = ~out_wimask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10053 = ~out_romask_1036; // @[RegisterRouter.scala:87:24] wire _out_T_10054 = ~out_womask_1036; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_887 = {hi_440, flags_0_go, _out_prepend_T_887}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10055 = out_prepend_887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10056 = _out_T_10055; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_182 = _out_T_10056; // @[MuxLiteral.scala:49:48] wire out_rimask_1037 = |_out_rimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_wimask_1037 = &_out_wimask_T_1037; // @[RegisterRouter.scala:87:24] wire out_romask_1037 = |_out_romask_T_1037; // @[RegisterRouter.scala:87:24] wire out_womask_1037 = &_out_womask_T_1037; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1037 = out_rivalid_1_891 & out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10058 = out_f_rivalid_1037; // @[RegisterRouter.scala:87:24] wire out_f_roready_1037 = out_roready_1_891 & out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10059 = out_f_roready_1037; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1037 = out_wivalid_1_891 & out_wimask_1037; // @[RegisterRouter.scala:87:24] wire out_f_woready_1037 = out_woready_1_891 & out_womask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10060 = ~out_rimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10061 = ~out_wimask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10062 = ~out_romask_1037; // @[RegisterRouter.scala:87:24] wire _out_T_10063 = ~out_womask_1037; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10065 = _out_T_10064; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_888 = _out_T_10065; // @[RegisterRouter.scala:87:24] wire out_rimask_1038 = |_out_rimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_wimask_1038 = &_out_wimask_T_1038; // @[RegisterRouter.scala:87:24] wire out_romask_1038 = |_out_romask_T_1038; // @[RegisterRouter.scala:87:24] wire out_womask_1038 = &_out_womask_T_1038; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1038 = out_rivalid_1_892 & out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10067 = out_f_rivalid_1038; // @[RegisterRouter.scala:87:24] wire out_f_roready_1038 = out_roready_1_892 & out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10068 = out_f_roready_1038; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1038 = out_wivalid_1_892 & out_wimask_1038; // @[RegisterRouter.scala:87:24] wire out_f_woready_1038 = out_woready_1_892 & out_womask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10069 = ~out_rimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10070 = ~out_wimask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10071 = ~out_romask_1038; // @[RegisterRouter.scala:87:24] wire _out_T_10072 = ~out_womask_1038; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_888 = {hi_210, flags_0_go, _out_prepend_T_888}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10073 = out_prepend_888; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10074 = _out_T_10073; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_889 = _out_T_10074; // @[RegisterRouter.scala:87:24] wire out_rimask_1039 = |_out_rimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_wimask_1039 = &_out_wimask_T_1039; // @[RegisterRouter.scala:87:24] wire out_romask_1039 = |_out_romask_T_1039; // @[RegisterRouter.scala:87:24] wire out_womask_1039 = &_out_womask_T_1039; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1039 = out_rivalid_1_893 & out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10076 = out_f_rivalid_1039; // @[RegisterRouter.scala:87:24] wire out_f_roready_1039 = out_roready_1_893 & out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10077 = out_f_roready_1039; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1039 = out_wivalid_1_893 & out_wimask_1039; // @[RegisterRouter.scala:87:24] wire out_f_woready_1039 = out_woready_1_893 & out_womask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10078 = ~out_rimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10079 = ~out_wimask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10080 = ~out_romask_1039; // @[RegisterRouter.scala:87:24] wire _out_T_10081 = ~out_womask_1039; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_889 = {hi_211, flags_0_go, _out_prepend_T_889}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10082 = out_prepend_889; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10083 = _out_T_10082; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_890 = _out_T_10083; // @[RegisterRouter.scala:87:24] wire out_rimask_1040 = |_out_rimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_wimask_1040 = &_out_wimask_T_1040; // @[RegisterRouter.scala:87:24] wire out_romask_1040 = |_out_romask_T_1040; // @[RegisterRouter.scala:87:24] wire out_womask_1040 = &_out_womask_T_1040; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1040 = out_rivalid_1_894 & out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10085 = out_f_rivalid_1040; // @[RegisterRouter.scala:87:24] wire out_f_roready_1040 = out_roready_1_894 & out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10086 = out_f_roready_1040; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1040 = out_wivalid_1_894 & out_wimask_1040; // @[RegisterRouter.scala:87:24] wire out_f_woready_1040 = out_woready_1_894 & out_womask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10087 = ~out_rimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10088 = ~out_wimask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10089 = ~out_romask_1040; // @[RegisterRouter.scala:87:24] wire _out_T_10090 = ~out_womask_1040; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_890 = {hi_212, flags_0_go, _out_prepend_T_890}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10091 = out_prepend_890; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10092 = _out_T_10091; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_891 = _out_T_10092; // @[RegisterRouter.scala:87:24] wire out_rimask_1041 = |_out_rimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_wimask_1041 = &_out_wimask_T_1041; // @[RegisterRouter.scala:87:24] wire out_romask_1041 = |_out_romask_T_1041; // @[RegisterRouter.scala:87:24] wire out_womask_1041 = &_out_womask_T_1041; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1041 = out_rivalid_1_895 & out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10094 = out_f_rivalid_1041; // @[RegisterRouter.scala:87:24] wire out_f_roready_1041 = out_roready_1_895 & out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10095 = out_f_roready_1041; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1041 = out_wivalid_1_895 & out_wimask_1041; // @[RegisterRouter.scala:87:24] wire out_f_woready_1041 = out_woready_1_895 & out_womask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10096 = ~out_rimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10097 = ~out_wimask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10098 = ~out_romask_1041; // @[RegisterRouter.scala:87:24] wire _out_T_10099 = ~out_womask_1041; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_891 = {hi_213, flags_0_go, _out_prepend_T_891}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10100 = out_prepend_891; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10101 = _out_T_10100; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_892 = _out_T_10101; // @[RegisterRouter.scala:87:24] wire out_rimask_1042 = |_out_rimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_wimask_1042 = &_out_wimask_T_1042; // @[RegisterRouter.scala:87:24] wire out_romask_1042 = |_out_romask_T_1042; // @[RegisterRouter.scala:87:24] wire out_womask_1042 = &_out_womask_T_1042; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1042 = out_rivalid_1_896 & out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10103 = out_f_rivalid_1042; // @[RegisterRouter.scala:87:24] wire out_f_roready_1042 = out_roready_1_896 & out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10104 = out_f_roready_1042; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1042 = out_wivalid_1_896 & out_wimask_1042; // @[RegisterRouter.scala:87:24] wire out_f_woready_1042 = out_woready_1_896 & out_womask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10105 = ~out_rimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10106 = ~out_wimask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10107 = ~out_romask_1042; // @[RegisterRouter.scala:87:24] wire _out_T_10108 = ~out_womask_1042; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_892 = {hi_214, flags_0_go, _out_prepend_T_892}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10109 = out_prepend_892; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10110 = _out_T_10109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_893 = _out_T_10110; // @[RegisterRouter.scala:87:24] wire out_rimask_1043 = |_out_rimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_wimask_1043 = &_out_wimask_T_1043; // @[RegisterRouter.scala:87:24] wire out_romask_1043 = |_out_romask_T_1043; // @[RegisterRouter.scala:87:24] wire out_womask_1043 = &_out_womask_T_1043; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1043 = out_rivalid_1_897 & out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10112 = out_f_rivalid_1043; // @[RegisterRouter.scala:87:24] wire out_f_roready_1043 = out_roready_1_897 & out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10113 = out_f_roready_1043; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1043 = out_wivalid_1_897 & out_wimask_1043; // @[RegisterRouter.scala:87:24] wire out_f_woready_1043 = out_woready_1_897 & out_womask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10114 = ~out_rimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10115 = ~out_wimask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10116 = ~out_romask_1043; // @[RegisterRouter.scala:87:24] wire _out_T_10117 = ~out_womask_1043; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_893 = {hi_215, flags_0_go, _out_prepend_T_893}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10118 = out_prepend_893; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10119 = _out_T_10118; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_894 = _out_T_10119; // @[RegisterRouter.scala:87:24] wire out_rimask_1044 = |_out_rimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_wimask_1044 = &_out_wimask_T_1044; // @[RegisterRouter.scala:87:24] wire out_romask_1044 = |_out_romask_T_1044; // @[RegisterRouter.scala:87:24] wire out_womask_1044 = &_out_womask_T_1044; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1044 = out_rivalid_1_898 & out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10121 = out_f_rivalid_1044; // @[RegisterRouter.scala:87:24] wire out_f_roready_1044 = out_roready_1_898 & out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10122 = out_f_roready_1044; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1044 = out_wivalid_1_898 & out_wimask_1044; // @[RegisterRouter.scala:87:24] wire out_f_woready_1044 = out_woready_1_898 & out_womask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10123 = ~out_rimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10124 = ~out_wimask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10125 = ~out_romask_1044; // @[RegisterRouter.scala:87:24] wire _out_T_10126 = ~out_womask_1044; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_894 = {hi_216, flags_0_go, _out_prepend_T_894}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10127 = out_prepend_894; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10128 = _out_T_10127; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_154 = _out_T_10128; // @[MuxLiteral.scala:49:48] wire out_rimask_1045 = |_out_rimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_wimask_1045 = &_out_wimask_T_1045; // @[RegisterRouter.scala:87:24] wire out_romask_1045 = |_out_romask_T_1045; // @[RegisterRouter.scala:87:24] wire out_womask_1045 = &_out_womask_T_1045; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1045 = out_rivalid_1_899 & out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10130 = out_f_rivalid_1045; // @[RegisterRouter.scala:87:24] wire out_f_roready_1045 = out_roready_1_899 & out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10131 = out_f_roready_1045; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1045 = out_wivalid_1_899 & out_wimask_1045; // @[RegisterRouter.scala:87:24] wire out_f_woready_1045 = out_woready_1_899 & out_womask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10132 = ~out_rimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10133 = ~out_wimask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10134 = ~out_romask_1045; // @[RegisterRouter.scala:87:24] wire _out_T_10135 = ~out_womask_1045; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10137 = _out_T_10136; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_895 = _out_T_10137; // @[RegisterRouter.scala:87:24] wire out_rimask_1046 = |_out_rimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_wimask_1046 = &_out_wimask_T_1046; // @[RegisterRouter.scala:87:24] wire out_romask_1046 = |_out_romask_T_1046; // @[RegisterRouter.scala:87:24] wire out_womask_1046 = &_out_womask_T_1046; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1046 = out_rivalid_1_900 & out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10139 = out_f_rivalid_1046; // @[RegisterRouter.scala:87:24] wire out_f_roready_1046 = out_roready_1_900 & out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10140 = out_f_roready_1046; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1046 = out_wivalid_1_900 & out_wimask_1046; // @[RegisterRouter.scala:87:24] wire out_f_woready_1046 = out_woready_1_900 & out_womask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10141 = ~out_rimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10142 = ~out_wimask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10143 = ~out_romask_1046; // @[RegisterRouter.scala:87:24] wire _out_T_10144 = ~out_womask_1046; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_895 = {hi_378, flags_0_go, _out_prepend_T_895}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10145 = out_prepend_895; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10146 = _out_T_10145; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_896 = _out_T_10146; // @[RegisterRouter.scala:87:24] wire out_rimask_1047 = |_out_rimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_wimask_1047 = &_out_wimask_T_1047; // @[RegisterRouter.scala:87:24] wire out_romask_1047 = |_out_romask_T_1047; // @[RegisterRouter.scala:87:24] wire out_womask_1047 = &_out_womask_T_1047; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1047 = out_rivalid_1_901 & out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10148 = out_f_rivalid_1047; // @[RegisterRouter.scala:87:24] wire out_f_roready_1047 = out_roready_1_901 & out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10149 = out_f_roready_1047; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1047 = out_wivalid_1_901 & out_wimask_1047; // @[RegisterRouter.scala:87:24] wire out_f_woready_1047 = out_woready_1_901 & out_womask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10150 = ~out_rimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10151 = ~out_wimask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10152 = ~out_romask_1047; // @[RegisterRouter.scala:87:24] wire _out_T_10153 = ~out_womask_1047; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_896 = {hi_379, flags_0_go, _out_prepend_T_896}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10154 = out_prepend_896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10155 = _out_T_10154; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_897 = _out_T_10155; // @[RegisterRouter.scala:87:24] wire out_rimask_1048 = |_out_rimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_wimask_1048 = &_out_wimask_T_1048; // @[RegisterRouter.scala:87:24] wire out_romask_1048 = |_out_romask_T_1048; // @[RegisterRouter.scala:87:24] wire out_womask_1048 = &_out_womask_T_1048; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1048 = out_rivalid_1_902 & out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10157 = out_f_rivalid_1048; // @[RegisterRouter.scala:87:24] wire out_f_roready_1048 = out_roready_1_902 & out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10158 = out_f_roready_1048; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1048 = out_wivalid_1_902 & out_wimask_1048; // @[RegisterRouter.scala:87:24] wire out_f_woready_1048 = out_woready_1_902 & out_womask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10159 = ~out_rimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10160 = ~out_wimask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10161 = ~out_romask_1048; // @[RegisterRouter.scala:87:24] wire _out_T_10162 = ~out_womask_1048; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_897 = {hi_380, flags_0_go, _out_prepend_T_897}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10163 = out_prepend_897; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10164 = _out_T_10163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_898 = _out_T_10164; // @[RegisterRouter.scala:87:24] wire out_rimask_1049 = |_out_rimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_wimask_1049 = &_out_wimask_T_1049; // @[RegisterRouter.scala:87:24] wire out_romask_1049 = |_out_romask_T_1049; // @[RegisterRouter.scala:87:24] wire out_womask_1049 = &_out_womask_T_1049; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1049 = out_rivalid_1_903 & out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10166 = out_f_rivalid_1049; // @[RegisterRouter.scala:87:24] wire out_f_roready_1049 = out_roready_1_903 & out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10167 = out_f_roready_1049; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1049 = out_wivalid_1_903 & out_wimask_1049; // @[RegisterRouter.scala:87:24] wire out_f_woready_1049 = out_woready_1_903 & out_womask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10168 = ~out_rimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10169 = ~out_wimask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10170 = ~out_romask_1049; // @[RegisterRouter.scala:87:24] wire _out_T_10171 = ~out_womask_1049; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_898 = {hi_381, flags_0_go, _out_prepend_T_898}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10172 = out_prepend_898; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10173 = _out_T_10172; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_899 = _out_T_10173; // @[RegisterRouter.scala:87:24] wire out_rimask_1050 = |_out_rimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_wimask_1050 = &_out_wimask_T_1050; // @[RegisterRouter.scala:87:24] wire out_romask_1050 = |_out_romask_T_1050; // @[RegisterRouter.scala:87:24] wire out_womask_1050 = &_out_womask_T_1050; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1050 = out_rivalid_1_904 & out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10175 = out_f_rivalid_1050; // @[RegisterRouter.scala:87:24] wire out_f_roready_1050 = out_roready_1_904 & out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10176 = out_f_roready_1050; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1050 = out_wivalid_1_904 & out_wimask_1050; // @[RegisterRouter.scala:87:24] wire out_f_woready_1050 = out_woready_1_904 & out_womask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10177 = ~out_rimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10178 = ~out_wimask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10179 = ~out_romask_1050; // @[RegisterRouter.scala:87:24] wire _out_T_10180 = ~out_womask_1050; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_899 = {hi_382, flags_0_go, _out_prepend_T_899}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10181 = out_prepend_899; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10182 = _out_T_10181; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_900 = _out_T_10182; // @[RegisterRouter.scala:87:24] wire out_rimask_1051 = |_out_rimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_wimask_1051 = &_out_wimask_T_1051; // @[RegisterRouter.scala:87:24] wire out_romask_1051 = |_out_romask_T_1051; // @[RegisterRouter.scala:87:24] wire out_womask_1051 = &_out_womask_T_1051; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1051 = out_rivalid_1_905 & out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10184 = out_f_rivalid_1051; // @[RegisterRouter.scala:87:24] wire out_f_roready_1051 = out_roready_1_905 & out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10185 = out_f_roready_1051; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1051 = out_wivalid_1_905 & out_wimask_1051; // @[RegisterRouter.scala:87:24] wire out_f_woready_1051 = out_woready_1_905 & out_womask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10186 = ~out_rimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10187 = ~out_wimask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10188 = ~out_romask_1051; // @[RegisterRouter.scala:87:24] wire _out_T_10189 = ~out_womask_1051; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_900 = {hi_383, flags_0_go, _out_prepend_T_900}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10190 = out_prepend_900; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10191 = _out_T_10190; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_901 = _out_T_10191; // @[RegisterRouter.scala:87:24] wire out_rimask_1052 = |_out_rimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_wimask_1052 = &_out_wimask_T_1052; // @[RegisterRouter.scala:87:24] wire out_romask_1052 = |_out_romask_T_1052; // @[RegisterRouter.scala:87:24] wire out_womask_1052 = &_out_womask_T_1052; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1052 = out_rivalid_1_906 & out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10193 = out_f_rivalid_1052; // @[RegisterRouter.scala:87:24] wire out_f_roready_1052 = out_roready_1_906 & out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10194 = out_f_roready_1052; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1052 = out_wivalid_1_906 & out_wimask_1052; // @[RegisterRouter.scala:87:24] wire out_f_woready_1052 = out_woready_1_906 & out_womask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10195 = ~out_rimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10196 = ~out_wimask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10197 = ~out_romask_1052; // @[RegisterRouter.scala:87:24] wire _out_T_10198 = ~out_womask_1052; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_901 = {hi_384, flags_0_go, _out_prepend_T_901}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10199 = out_prepend_901; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10200 = _out_T_10199; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_175 = _out_T_10200; // @[MuxLiteral.scala:49:48] wire out_rimask_1053 = |_out_rimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_wimask_1053 = &_out_wimask_T_1053; // @[RegisterRouter.scala:87:24] wire out_romask_1053 = |_out_romask_T_1053; // @[RegisterRouter.scala:87:24] wire out_womask_1053 = &_out_womask_T_1053; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1053 = out_rivalid_1_907 & out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10202 = out_f_rivalid_1053; // @[RegisterRouter.scala:87:24] wire out_f_roready_1053 = out_roready_1_907 & out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10203 = out_f_roready_1053; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1053 = out_wivalid_1_907 & out_wimask_1053; // @[RegisterRouter.scala:87:24] wire out_f_woready_1053 = out_woready_1_907 & out_womask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10204 = ~out_rimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10205 = ~out_wimask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10206 = ~out_romask_1053; // @[RegisterRouter.scala:87:24] wire _out_T_10207 = ~out_womask_1053; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10209 = _out_T_10208; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_902 = _out_T_10209; // @[RegisterRouter.scala:87:24] wire out_rimask_1054 = |_out_rimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_wimask_1054 = &_out_wimask_T_1054; // @[RegisterRouter.scala:87:24] wire out_romask_1054 = |_out_romask_T_1054; // @[RegisterRouter.scala:87:24] wire out_womask_1054 = &_out_womask_T_1054; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1054 = out_rivalid_1_908 & out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10211 = out_f_rivalid_1054; // @[RegisterRouter.scala:87:24] wire out_f_roready_1054 = out_roready_1_908 & out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10212 = out_f_roready_1054; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1054 = out_wivalid_1_908 & out_wimask_1054; // @[RegisterRouter.scala:87:24] wire out_f_woready_1054 = out_woready_1_908 & out_womask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10213 = ~out_rimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10214 = ~out_wimask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10215 = ~out_romask_1054; // @[RegisterRouter.scala:87:24] wire _out_T_10216 = ~out_womask_1054; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_902 = {hi_122, flags_0_go, _out_prepend_T_902}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10217 = out_prepend_902; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10218 = _out_T_10217; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_903 = _out_T_10218; // @[RegisterRouter.scala:87:24] wire out_rimask_1055 = |_out_rimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_wimask_1055 = &_out_wimask_T_1055; // @[RegisterRouter.scala:87:24] wire out_romask_1055 = |_out_romask_T_1055; // @[RegisterRouter.scala:87:24] wire out_womask_1055 = &_out_womask_T_1055; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1055 = out_rivalid_1_909 & out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10220 = out_f_rivalid_1055; // @[RegisterRouter.scala:87:24] wire out_f_roready_1055 = out_roready_1_909 & out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10221 = out_f_roready_1055; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1055 = out_wivalid_1_909 & out_wimask_1055; // @[RegisterRouter.scala:87:24] wire out_f_woready_1055 = out_woready_1_909 & out_womask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10222 = ~out_rimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10223 = ~out_wimask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10224 = ~out_romask_1055; // @[RegisterRouter.scala:87:24] wire _out_T_10225 = ~out_womask_1055; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_903 = {hi_123, flags_0_go, _out_prepend_T_903}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10226 = out_prepend_903; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10227 = _out_T_10226; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_904 = _out_T_10227; // @[RegisterRouter.scala:87:24] wire out_rimask_1056 = |_out_rimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_wimask_1056 = &_out_wimask_T_1056; // @[RegisterRouter.scala:87:24] wire out_romask_1056 = |_out_romask_T_1056; // @[RegisterRouter.scala:87:24] wire out_womask_1056 = &_out_womask_T_1056; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1056 = out_rivalid_1_910 & out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10229 = out_f_rivalid_1056; // @[RegisterRouter.scala:87:24] wire out_f_roready_1056 = out_roready_1_910 & out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10230 = out_f_roready_1056; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1056 = out_wivalid_1_910 & out_wimask_1056; // @[RegisterRouter.scala:87:24] wire out_f_woready_1056 = out_woready_1_910 & out_womask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10231 = ~out_rimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10232 = ~out_wimask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10233 = ~out_romask_1056; // @[RegisterRouter.scala:87:24] wire _out_T_10234 = ~out_womask_1056; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_904 = {hi_124, flags_0_go, _out_prepend_T_904}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10235 = out_prepend_904; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10236 = _out_T_10235; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_905 = _out_T_10236; // @[RegisterRouter.scala:87:24] wire out_rimask_1057 = |_out_rimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_wimask_1057 = &_out_wimask_T_1057; // @[RegisterRouter.scala:87:24] wire out_romask_1057 = |_out_romask_T_1057; // @[RegisterRouter.scala:87:24] wire out_womask_1057 = &_out_womask_T_1057; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1057 = out_rivalid_1_911 & out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10238 = out_f_rivalid_1057; // @[RegisterRouter.scala:87:24] wire out_f_roready_1057 = out_roready_1_911 & out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10239 = out_f_roready_1057; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1057 = out_wivalid_1_911 & out_wimask_1057; // @[RegisterRouter.scala:87:24] wire out_f_woready_1057 = out_woready_1_911 & out_womask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10240 = ~out_rimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10241 = ~out_wimask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10242 = ~out_romask_1057; // @[RegisterRouter.scala:87:24] wire _out_T_10243 = ~out_womask_1057; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_905 = {hi_125, flags_0_go, _out_prepend_T_905}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10244 = out_prepend_905; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10245 = _out_T_10244; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_906 = _out_T_10245; // @[RegisterRouter.scala:87:24] wire out_rimask_1058 = |_out_rimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_wimask_1058 = &_out_wimask_T_1058; // @[RegisterRouter.scala:87:24] wire out_romask_1058 = |_out_romask_T_1058; // @[RegisterRouter.scala:87:24] wire out_womask_1058 = &_out_womask_T_1058; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1058 = out_rivalid_1_912 & out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10247 = out_f_rivalid_1058; // @[RegisterRouter.scala:87:24] wire out_f_roready_1058 = out_roready_1_912 & out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10248 = out_f_roready_1058; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1058 = out_wivalid_1_912 & out_wimask_1058; // @[RegisterRouter.scala:87:24] wire out_f_woready_1058 = out_woready_1_912 & out_womask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10249 = ~out_rimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10250 = ~out_wimask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10251 = ~out_romask_1058; // @[RegisterRouter.scala:87:24] wire _out_T_10252 = ~out_womask_1058; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_906 = {hi_126, flags_0_go, _out_prepend_T_906}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10253 = out_prepend_906; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10254 = _out_T_10253; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_907 = _out_T_10254; // @[RegisterRouter.scala:87:24] wire out_rimask_1059 = |_out_rimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_wimask_1059 = &_out_wimask_T_1059; // @[RegisterRouter.scala:87:24] wire out_romask_1059 = |_out_romask_T_1059; // @[RegisterRouter.scala:87:24] wire out_womask_1059 = &_out_womask_T_1059; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1059 = out_rivalid_1_913 & out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10256 = out_f_rivalid_1059; // @[RegisterRouter.scala:87:24] wire out_f_roready_1059 = out_roready_1_913 & out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10257 = out_f_roready_1059; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1059 = out_wivalid_1_913 & out_wimask_1059; // @[RegisterRouter.scala:87:24] wire out_f_woready_1059 = out_woready_1_913 & out_womask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10258 = ~out_rimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10259 = ~out_wimask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10260 = ~out_romask_1059; // @[RegisterRouter.scala:87:24] wire _out_T_10261 = ~out_womask_1059; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_907 = {hi_127, flags_0_go, _out_prepend_T_907}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10262 = out_prepend_907; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10263 = _out_T_10262; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_908 = _out_T_10263; // @[RegisterRouter.scala:87:24] wire out_rimask_1060 = |_out_rimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_wimask_1060 = &_out_wimask_T_1060; // @[RegisterRouter.scala:87:24] wire out_romask_1060 = |_out_romask_T_1060; // @[RegisterRouter.scala:87:24] wire out_womask_1060 = &_out_womask_T_1060; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1060 = out_rivalid_1_914 & out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10265 = out_f_rivalid_1060; // @[RegisterRouter.scala:87:24] wire out_f_roready_1060 = out_roready_1_914 & out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10266 = out_f_roready_1060; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1060 = out_wivalid_1_914 & out_wimask_1060; // @[RegisterRouter.scala:87:24] wire out_f_woready_1060 = out_woready_1_914 & out_womask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10267 = ~out_rimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10268 = ~out_wimask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10269 = ~out_romask_1060; // @[RegisterRouter.scala:87:24] wire _out_T_10270 = ~out_womask_1060; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_908 = {hi_128, flags_0_go, _out_prepend_T_908}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10271 = out_prepend_908; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10272 = _out_T_10271; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_143 = _out_T_10272; // @[MuxLiteral.scala:49:48] wire out_rimask_1061 = |_out_rimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_wimask_1061 = &_out_wimask_T_1061; // @[RegisterRouter.scala:87:24] wire out_romask_1061 = |_out_romask_T_1061; // @[RegisterRouter.scala:87:24] wire out_womask_1061 = &_out_womask_T_1061; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1061 = out_rivalid_1_915 & out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10274 = out_f_rivalid_1061; // @[RegisterRouter.scala:87:24] wire out_f_roready_1061 = out_roready_1_915 & out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10275 = out_f_roready_1061; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1061 = out_wivalid_1_915 & out_wimask_1061; // @[RegisterRouter.scala:87:24] wire out_f_woready_1061 = out_woready_1_915 & out_womask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10276 = ~out_rimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10277 = ~out_wimask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10278 = ~out_romask_1061; // @[RegisterRouter.scala:87:24] wire _out_T_10279 = ~out_womask_1061; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10281 = _out_T_10280; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_909 = _out_T_10281; // @[RegisterRouter.scala:87:24] wire out_rimask_1062 = |_out_rimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_wimask_1062 = &_out_wimask_T_1062; // @[RegisterRouter.scala:87:24] wire out_romask_1062 = |_out_romask_T_1062; // @[RegisterRouter.scala:87:24] wire out_womask_1062 = &_out_womask_T_1062; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1062 = out_rivalid_1_916 & out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10283 = out_f_rivalid_1062; // @[RegisterRouter.scala:87:24] wire out_f_roready_1062 = out_roready_1_916 & out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10284 = out_f_roready_1062; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1062 = out_wivalid_1_916 & out_wimask_1062; // @[RegisterRouter.scala:87:24] wire out_f_woready_1062 = out_woready_1_916 & out_womask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10285 = ~out_rimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10286 = ~out_wimask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10287 = ~out_romask_1062; // @[RegisterRouter.scala:87:24] wire _out_T_10288 = ~out_womask_1062; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_909 = {hi_602, flags_0_go, _out_prepend_T_909}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10289 = out_prepend_909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10290 = _out_T_10289; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_910 = _out_T_10290; // @[RegisterRouter.scala:87:24] wire out_rimask_1063 = |_out_rimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_wimask_1063 = &_out_wimask_T_1063; // @[RegisterRouter.scala:87:24] wire out_romask_1063 = |_out_romask_T_1063; // @[RegisterRouter.scala:87:24] wire out_womask_1063 = &_out_womask_T_1063; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1063 = out_rivalid_1_917 & out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10292 = out_f_rivalid_1063; // @[RegisterRouter.scala:87:24] wire out_f_roready_1063 = out_roready_1_917 & out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10293 = out_f_roready_1063; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1063 = out_wivalid_1_917 & out_wimask_1063; // @[RegisterRouter.scala:87:24] wire out_f_woready_1063 = out_woready_1_917 & out_womask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10294 = ~out_rimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10295 = ~out_wimask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10296 = ~out_romask_1063; // @[RegisterRouter.scala:87:24] wire _out_T_10297 = ~out_womask_1063; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_910 = {hi_603, flags_0_go, _out_prepend_T_910}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10298 = out_prepend_910; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10299 = _out_T_10298; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_911 = _out_T_10299; // @[RegisterRouter.scala:87:24] wire out_rimask_1064 = |_out_rimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_wimask_1064 = &_out_wimask_T_1064; // @[RegisterRouter.scala:87:24] wire out_romask_1064 = |_out_romask_T_1064; // @[RegisterRouter.scala:87:24] wire out_womask_1064 = &_out_womask_T_1064; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1064 = out_rivalid_1_918 & out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10301 = out_f_rivalid_1064; // @[RegisterRouter.scala:87:24] wire out_f_roready_1064 = out_roready_1_918 & out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10302 = out_f_roready_1064; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1064 = out_wivalid_1_918 & out_wimask_1064; // @[RegisterRouter.scala:87:24] wire out_f_woready_1064 = out_woready_1_918 & out_womask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10303 = ~out_rimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10304 = ~out_wimask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10305 = ~out_romask_1064; // @[RegisterRouter.scala:87:24] wire _out_T_10306 = ~out_womask_1064; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_911 = {hi_604, flags_0_go, _out_prepend_T_911}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10307 = out_prepend_911; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10308 = _out_T_10307; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_912 = _out_T_10308; // @[RegisterRouter.scala:87:24] wire out_rimask_1065 = |_out_rimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_wimask_1065 = &_out_wimask_T_1065; // @[RegisterRouter.scala:87:24] wire out_romask_1065 = |_out_romask_T_1065; // @[RegisterRouter.scala:87:24] wire out_womask_1065 = &_out_womask_T_1065; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1065 = out_rivalid_1_919 & out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10310 = out_f_rivalid_1065; // @[RegisterRouter.scala:87:24] wire out_f_roready_1065 = out_roready_1_919 & out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10311 = out_f_roready_1065; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1065 = out_wivalid_1_919 & out_wimask_1065; // @[RegisterRouter.scala:87:24] wire out_f_woready_1065 = out_woready_1_919 & out_womask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10312 = ~out_rimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10313 = ~out_wimask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10314 = ~out_romask_1065; // @[RegisterRouter.scala:87:24] wire _out_T_10315 = ~out_womask_1065; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_912 = {hi_605, flags_0_go, _out_prepend_T_912}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10316 = out_prepend_912; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10317 = _out_T_10316; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_913 = _out_T_10317; // @[RegisterRouter.scala:87:24] wire out_rimask_1066 = |_out_rimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_wimask_1066 = &_out_wimask_T_1066; // @[RegisterRouter.scala:87:24] wire out_romask_1066 = |_out_romask_T_1066; // @[RegisterRouter.scala:87:24] wire out_womask_1066 = &_out_womask_T_1066; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1066 = out_rivalid_1_920 & out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10319 = out_f_rivalid_1066; // @[RegisterRouter.scala:87:24] wire out_f_roready_1066 = out_roready_1_920 & out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10320 = out_f_roready_1066; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1066 = out_wivalid_1_920 & out_wimask_1066; // @[RegisterRouter.scala:87:24] wire out_f_woready_1066 = out_woready_1_920 & out_womask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10321 = ~out_rimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10322 = ~out_wimask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10323 = ~out_romask_1066; // @[RegisterRouter.scala:87:24] wire _out_T_10324 = ~out_womask_1066; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_913 = {hi_606, flags_0_go, _out_prepend_T_913}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10325 = out_prepend_913; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10326 = _out_T_10325; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_914 = _out_T_10326; // @[RegisterRouter.scala:87:24] wire out_rimask_1067 = |_out_rimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_wimask_1067 = &_out_wimask_T_1067; // @[RegisterRouter.scala:87:24] wire out_romask_1067 = |_out_romask_T_1067; // @[RegisterRouter.scala:87:24] wire out_womask_1067 = &_out_womask_T_1067; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1067 = out_rivalid_1_921 & out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10328 = out_f_rivalid_1067; // @[RegisterRouter.scala:87:24] wire out_f_roready_1067 = out_roready_1_921 & out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10329 = out_f_roready_1067; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1067 = out_wivalid_1_921 & out_wimask_1067; // @[RegisterRouter.scala:87:24] wire out_f_woready_1067 = out_woready_1_921 & out_womask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10330 = ~out_rimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10331 = ~out_wimask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10332 = ~out_romask_1067; // @[RegisterRouter.scala:87:24] wire _out_T_10333 = ~out_womask_1067; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_914 = {hi_607, flags_0_go, _out_prepend_T_914}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10334 = out_prepend_914; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10335 = _out_T_10334; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_915 = _out_T_10335; // @[RegisterRouter.scala:87:24] wire out_rimask_1068 = |_out_rimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_wimask_1068 = &_out_wimask_T_1068; // @[RegisterRouter.scala:87:24] wire out_romask_1068 = |_out_romask_T_1068; // @[RegisterRouter.scala:87:24] wire out_womask_1068 = &_out_womask_T_1068; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1068 = out_rivalid_1_922 & out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10337 = out_f_rivalid_1068; // @[RegisterRouter.scala:87:24] wire out_f_roready_1068 = out_roready_1_922 & out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10338 = out_f_roready_1068; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1068 = out_wivalid_1_922 & out_wimask_1068; // @[RegisterRouter.scala:87:24] wire out_f_woready_1068 = out_woready_1_922 & out_womask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10339 = ~out_rimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10340 = ~out_wimask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10341 = ~out_romask_1068; // @[RegisterRouter.scala:87:24] wire _out_T_10342 = ~out_womask_1068; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_915 = {hi_608, flags_0_go, _out_prepend_T_915}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10343 = out_prepend_915; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10344 = _out_T_10343; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_203 = _out_T_10344; // @[MuxLiteral.scala:49:48] wire out_rimask_1069 = |_out_rimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_wimask_1069 = &_out_wimask_T_1069; // @[RegisterRouter.scala:87:24] wire out_romask_1069 = |_out_romask_T_1069; // @[RegisterRouter.scala:87:24] wire out_womask_1069 = &_out_womask_T_1069; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1069 = out_rivalid_1_923 & out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10346 = out_f_rivalid_1069; // @[RegisterRouter.scala:87:24] wire out_f_roready_1069 = out_roready_1_923 & out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10347 = out_f_roready_1069; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1069 = out_wivalid_1_923 & out_wimask_1069; // @[RegisterRouter.scala:87:24] wire out_f_woready_1069 = out_woready_1_923 & out_womask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10348 = ~out_rimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10349 = ~out_wimask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10350 = ~out_romask_1069; // @[RegisterRouter.scala:87:24] wire _out_T_10351 = ~out_womask_1069; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10353 = _out_T_10352; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_916 = _out_T_10353; // @[RegisterRouter.scala:87:24] wire out_rimask_1070 = |_out_rimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_wimask_1070 = &_out_wimask_T_1070; // @[RegisterRouter.scala:87:24] wire out_romask_1070 = |_out_romask_T_1070; // @[RegisterRouter.scala:87:24] wire out_womask_1070 = &_out_womask_T_1070; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1070 = out_rivalid_1_924 & out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10355 = out_f_rivalid_1070; // @[RegisterRouter.scala:87:24] wire out_f_roready_1070 = out_roready_1_924 & out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10356 = out_f_roready_1070; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1070 = out_wivalid_1_924 & out_wimask_1070; // @[RegisterRouter.scala:87:24] wire out_f_woready_1070 = out_woready_1_924 & out_womask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10357 = ~out_rimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10358 = ~out_wimask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10359 = ~out_romask_1070; // @[RegisterRouter.scala:87:24] wire _out_T_10360 = ~out_womask_1070; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_916 = {hi_722, flags_0_go, _out_prepend_T_916}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10361 = out_prepend_916; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10362 = _out_T_10361; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_917 = _out_T_10362; // @[RegisterRouter.scala:87:24] wire out_rimask_1071 = |_out_rimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_wimask_1071 = &_out_wimask_T_1071; // @[RegisterRouter.scala:87:24] wire out_romask_1071 = |_out_romask_T_1071; // @[RegisterRouter.scala:87:24] wire out_womask_1071 = &_out_womask_T_1071; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1071 = out_rivalid_1_925 & out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10364 = out_f_rivalid_1071; // @[RegisterRouter.scala:87:24] wire out_f_roready_1071 = out_roready_1_925 & out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10365 = out_f_roready_1071; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1071 = out_wivalid_1_925 & out_wimask_1071; // @[RegisterRouter.scala:87:24] wire out_f_woready_1071 = out_woready_1_925 & out_womask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10366 = ~out_rimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10367 = ~out_wimask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10368 = ~out_romask_1071; // @[RegisterRouter.scala:87:24] wire _out_T_10369 = ~out_womask_1071; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_917 = {hi_723, flags_0_go, _out_prepend_T_917}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10370 = out_prepend_917; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10371 = _out_T_10370; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_918 = _out_T_10371; // @[RegisterRouter.scala:87:24] wire out_rimask_1072 = |_out_rimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_wimask_1072 = &_out_wimask_T_1072; // @[RegisterRouter.scala:87:24] wire out_romask_1072 = |_out_romask_T_1072; // @[RegisterRouter.scala:87:24] wire out_womask_1072 = &_out_womask_T_1072; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1072 = out_rivalid_1_926 & out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10373 = out_f_rivalid_1072; // @[RegisterRouter.scala:87:24] wire out_f_roready_1072 = out_roready_1_926 & out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10374 = out_f_roready_1072; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1072 = out_wivalid_1_926 & out_wimask_1072; // @[RegisterRouter.scala:87:24] wire out_f_woready_1072 = out_woready_1_926 & out_womask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10375 = ~out_rimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10376 = ~out_wimask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10377 = ~out_romask_1072; // @[RegisterRouter.scala:87:24] wire _out_T_10378 = ~out_womask_1072; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_918 = {hi_724, flags_0_go, _out_prepend_T_918}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10379 = out_prepend_918; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10380 = _out_T_10379; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_919 = _out_T_10380; // @[RegisterRouter.scala:87:24] wire out_rimask_1073 = |_out_rimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_wimask_1073 = &_out_wimask_T_1073; // @[RegisterRouter.scala:87:24] wire out_romask_1073 = |_out_romask_T_1073; // @[RegisterRouter.scala:87:24] wire out_womask_1073 = &_out_womask_T_1073; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1073 = out_rivalid_1_927 & out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10382 = out_f_rivalid_1073; // @[RegisterRouter.scala:87:24] wire out_f_roready_1073 = out_roready_1_927 & out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10383 = out_f_roready_1073; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1073 = out_wivalid_1_927 & out_wimask_1073; // @[RegisterRouter.scala:87:24] wire out_f_woready_1073 = out_woready_1_927 & out_womask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10384 = ~out_rimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10385 = ~out_wimask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10386 = ~out_romask_1073; // @[RegisterRouter.scala:87:24] wire _out_T_10387 = ~out_womask_1073; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_919 = {hi_725, flags_0_go, _out_prepend_T_919}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10388 = out_prepend_919; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10389 = _out_T_10388; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_920 = _out_T_10389; // @[RegisterRouter.scala:87:24] wire out_rimask_1074 = |_out_rimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_wimask_1074 = &_out_wimask_T_1074; // @[RegisterRouter.scala:87:24] wire out_romask_1074 = |_out_romask_T_1074; // @[RegisterRouter.scala:87:24] wire out_womask_1074 = &_out_womask_T_1074; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1074 = out_rivalid_1_928 & out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10391 = out_f_rivalid_1074; // @[RegisterRouter.scala:87:24] wire out_f_roready_1074 = out_roready_1_928 & out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10392 = out_f_roready_1074; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1074 = out_wivalid_1_928 & out_wimask_1074; // @[RegisterRouter.scala:87:24] wire out_f_woready_1074 = out_woready_1_928 & out_womask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10393 = ~out_rimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10394 = ~out_wimask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10395 = ~out_romask_1074; // @[RegisterRouter.scala:87:24] wire _out_T_10396 = ~out_womask_1074; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_920 = {hi_726, flags_0_go, _out_prepend_T_920}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10397 = out_prepend_920; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10398 = _out_T_10397; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_921 = _out_T_10398; // @[RegisterRouter.scala:87:24] wire out_rimask_1075 = |_out_rimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_wimask_1075 = &_out_wimask_T_1075; // @[RegisterRouter.scala:87:24] wire out_romask_1075 = |_out_romask_T_1075; // @[RegisterRouter.scala:87:24] wire out_womask_1075 = &_out_womask_T_1075; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1075 = out_rivalid_1_929 & out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10400 = out_f_rivalid_1075; // @[RegisterRouter.scala:87:24] wire out_f_roready_1075 = out_roready_1_929 & out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10401 = out_f_roready_1075; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1075 = out_wivalid_1_929 & out_wimask_1075; // @[RegisterRouter.scala:87:24] wire out_f_woready_1075 = out_woready_1_929 & out_womask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10402 = ~out_rimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10403 = ~out_wimask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10404 = ~out_romask_1075; // @[RegisterRouter.scala:87:24] wire _out_T_10405 = ~out_womask_1075; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_921 = {hi_727, flags_0_go, _out_prepend_T_921}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10406 = out_prepend_921; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10407 = _out_T_10406; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_922 = _out_T_10407; // @[RegisterRouter.scala:87:24] wire out_rimask_1076 = |_out_rimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_wimask_1076 = &_out_wimask_T_1076; // @[RegisterRouter.scala:87:24] wire out_romask_1076 = |_out_romask_T_1076; // @[RegisterRouter.scala:87:24] wire out_womask_1076 = &_out_womask_T_1076; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1076 = out_rivalid_1_930 & out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10409 = out_f_rivalid_1076; // @[RegisterRouter.scala:87:24] wire out_f_roready_1076 = out_roready_1_930 & out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10410 = out_f_roready_1076; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1076 = out_wivalid_1_930 & out_wimask_1076; // @[RegisterRouter.scala:87:24] wire out_f_woready_1076 = out_woready_1_930 & out_womask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10411 = ~out_rimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10412 = ~out_wimask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10413 = ~out_romask_1076; // @[RegisterRouter.scala:87:24] wire _out_T_10414 = ~out_womask_1076; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_922 = {hi_728, flags_0_go, _out_prepend_T_922}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10415 = out_prepend_922; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10416 = _out_T_10415; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_218 = _out_T_10416; // @[MuxLiteral.scala:49:48] wire out_rimask_1077 = |_out_rimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_wimask_1077 = &_out_wimask_T_1077; // @[RegisterRouter.scala:87:24] wire out_romask_1077 = |_out_romask_T_1077; // @[RegisterRouter.scala:87:24] wire out_womask_1077 = &_out_womask_T_1077; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1077 = out_rivalid_1_931 & out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10418 = out_f_rivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_roready_1077 = out_roready_1_931 & out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10419 = out_f_roready_1077; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1077 = out_wivalid_1_931 & out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10420 = out_f_wivalid_1077; // @[RegisterRouter.scala:87:24] wire out_f_woready_1077 = out_woready_1_931 & out_womask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10421 = out_f_woready_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10422 = ~out_rimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10423 = ~out_wimask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10424 = ~out_romask_1077; // @[RegisterRouter.scala:87:24] wire _out_T_10425 = ~out_womask_1077; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10427 = _out_T_10426; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_923 = _out_T_10427; // @[RegisterRouter.scala:87:24] wire out_rimask_1078 = |_out_rimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_wimask_1078 = &_out_wimask_T_1078; // @[RegisterRouter.scala:87:24] wire out_romask_1078 = |_out_romask_T_1078; // @[RegisterRouter.scala:87:24] wire out_womask_1078 = &_out_womask_T_1078; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1078 = out_rivalid_1_932 & out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10429 = out_f_rivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_roready_1078 = out_roready_1_932 & out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10430 = out_f_roready_1078; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1078 = out_wivalid_1_932 & out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10431 = out_f_wivalid_1078; // @[RegisterRouter.scala:87:24] wire out_f_woready_1078 = out_woready_1_932 & out_womask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10432 = out_f_woready_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10433 = ~out_rimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10434 = ~out_wimask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10435 = ~out_romask_1078; // @[RegisterRouter.scala:87:24] wire _out_T_10436 = ~out_womask_1078; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_923 = {programBufferMem_1, _out_prepend_T_923}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10437 = out_prepend_923; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10438 = _out_T_10437; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_924 = _out_T_10438; // @[RegisterRouter.scala:87:24] wire out_rimask_1079 = |_out_rimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_wimask_1079 = &_out_wimask_T_1079; // @[RegisterRouter.scala:87:24] wire out_romask_1079 = |_out_romask_T_1079; // @[RegisterRouter.scala:87:24] wire out_womask_1079 = &_out_womask_T_1079; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1079 = out_rivalid_1_933 & out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10440 = out_f_rivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_roready_1079 = out_roready_1_933 & out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10441 = out_f_roready_1079; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1079 = out_wivalid_1_933 & out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10442 = out_f_wivalid_1079; // @[RegisterRouter.scala:87:24] wire out_f_woready_1079 = out_woready_1_933 & out_womask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10443 = out_f_woready_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10444 = ~out_rimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10445 = ~out_wimask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10446 = ~out_romask_1079; // @[RegisterRouter.scala:87:24] wire _out_T_10447 = ~out_womask_1079; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_924 = {programBufferMem_2, _out_prepend_T_924}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10448 = out_prepend_924; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10449 = _out_T_10448; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_925 = _out_T_10449; // @[RegisterRouter.scala:87:24] wire out_rimask_1080 = |_out_rimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_wimask_1080 = &_out_wimask_T_1080; // @[RegisterRouter.scala:87:24] wire out_romask_1080 = |_out_romask_T_1080; // @[RegisterRouter.scala:87:24] wire out_womask_1080 = &_out_womask_T_1080; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1080 = out_rivalid_1_934 & out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10451 = out_f_rivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_roready_1080 = out_roready_1_934 & out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10452 = out_f_roready_1080; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1080 = out_wivalid_1_934 & out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10453 = out_f_wivalid_1080; // @[RegisterRouter.scala:87:24] wire out_f_woready_1080 = out_woready_1_934 & out_womask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10454 = out_f_woready_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10455 = ~out_rimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10456 = ~out_wimask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10457 = ~out_romask_1080; // @[RegisterRouter.scala:87:24] wire _out_T_10458 = ~out_womask_1080; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_925 = {programBufferMem_3, _out_prepend_T_925}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10459 = out_prepend_925; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10460 = _out_T_10459; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_926 = _out_T_10460; // @[RegisterRouter.scala:87:24] wire out_rimask_1081 = |_out_rimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_wimask_1081 = &_out_wimask_T_1081; // @[RegisterRouter.scala:87:24] wire out_romask_1081 = |_out_romask_T_1081; // @[RegisterRouter.scala:87:24] wire out_womask_1081 = &_out_womask_T_1081; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1081 = out_rivalid_1_935 & out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10462 = out_f_rivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_roready_1081 = out_roready_1_935 & out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10463 = out_f_roready_1081; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1081 = out_wivalid_1_935 & out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10464 = out_f_wivalid_1081; // @[RegisterRouter.scala:87:24] wire out_f_woready_1081 = out_woready_1_935 & out_womask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10465 = out_f_woready_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10466 = ~out_rimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10467 = ~out_wimask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10468 = ~out_romask_1081; // @[RegisterRouter.scala:87:24] wire _out_T_10469 = ~out_womask_1081; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_926 = {programBufferMem_4, _out_prepend_T_926}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10470 = out_prepend_926; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10471 = _out_T_10470; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_927 = _out_T_10471; // @[RegisterRouter.scala:87:24] wire out_rimask_1082 = |_out_rimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_wimask_1082 = &_out_wimask_T_1082; // @[RegisterRouter.scala:87:24] wire out_romask_1082 = |_out_romask_T_1082; // @[RegisterRouter.scala:87:24] wire out_womask_1082 = &_out_womask_T_1082; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1082 = out_rivalid_1_936 & out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10473 = out_f_rivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_roready_1082 = out_roready_1_936 & out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10474 = out_f_roready_1082; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1082 = out_wivalid_1_936 & out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10475 = out_f_wivalid_1082; // @[RegisterRouter.scala:87:24] wire out_f_woready_1082 = out_woready_1_936 & out_womask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10476 = out_f_woready_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10477 = ~out_rimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10478 = ~out_wimask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10479 = ~out_romask_1082; // @[RegisterRouter.scala:87:24] wire _out_T_10480 = ~out_womask_1082; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_927 = {programBufferMem_5, _out_prepend_T_927}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10481 = out_prepend_927; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10482 = _out_T_10481; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_928 = _out_T_10482; // @[RegisterRouter.scala:87:24] wire out_rimask_1083 = |_out_rimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_wimask_1083 = &_out_wimask_T_1083; // @[RegisterRouter.scala:87:24] wire out_romask_1083 = |_out_romask_T_1083; // @[RegisterRouter.scala:87:24] wire out_womask_1083 = &_out_womask_T_1083; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1083 = out_rivalid_1_937 & out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10484 = out_f_rivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_roready_1083 = out_roready_1_937 & out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10485 = out_f_roready_1083; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1083 = out_wivalid_1_937 & out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10486 = out_f_wivalid_1083; // @[RegisterRouter.scala:87:24] wire out_f_woready_1083 = out_woready_1_937 & out_womask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10487 = out_f_woready_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10488 = ~out_rimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10489 = ~out_wimask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10490 = ~out_romask_1083; // @[RegisterRouter.scala:87:24] wire _out_T_10491 = ~out_womask_1083; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_928 = {programBufferMem_6, _out_prepend_T_928}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10492 = out_prepend_928; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10493 = _out_T_10492; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_929 = _out_T_10493; // @[RegisterRouter.scala:87:24] wire out_rimask_1084 = |_out_rimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_wimask_1084 = &_out_wimask_T_1084; // @[RegisterRouter.scala:87:24] wire out_romask_1084 = |_out_romask_T_1084; // @[RegisterRouter.scala:87:24] wire out_womask_1084 = &_out_womask_T_1084; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1084 = out_rivalid_1_938 & out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10495 = out_f_rivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_roready_1084 = out_roready_1_938 & out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10496 = out_f_roready_1084; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1084 = out_wivalid_1_938 & out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10497 = out_f_wivalid_1084; // @[RegisterRouter.scala:87:24] wire out_f_woready_1084 = out_woready_1_938 & out_womask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10498 = out_f_woready_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10499 = ~out_rimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10500 = ~out_wimask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10501 = ~out_romask_1084; // @[RegisterRouter.scala:87:24] wire _out_T_10502 = ~out_womask_1084; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_929 = {programBufferMem_7, _out_prepend_T_929}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10503 = out_prepend_929; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10504 = _out_T_10503; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_104 = _out_T_10504; // @[MuxLiteral.scala:49:48] wire out_rimask_1085 = |_out_rimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_wimask_1085 = &_out_wimask_T_1085; // @[RegisterRouter.scala:87:24] wire out_romask_1085 = |_out_romask_T_1085; // @[RegisterRouter.scala:87:24] wire out_womask_1085 = &_out_womask_T_1085; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1085 = out_rivalid_1_939 & out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10506 = out_f_rivalid_1085; // @[RegisterRouter.scala:87:24] wire out_f_roready_1085 = out_roready_1_939 & out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10507 = out_f_roready_1085; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1085 = out_wivalid_1_939 & out_wimask_1085; // @[RegisterRouter.scala:87:24] wire out_f_woready_1085 = out_woready_1_939 & out_womask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10508 = ~out_rimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10509 = ~out_wimask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10510 = ~out_romask_1085; // @[RegisterRouter.scala:87:24] wire _out_T_10511 = ~out_womask_1085; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10513 = _out_T_10512; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_930 = _out_T_10513; // @[RegisterRouter.scala:87:24] wire out_rimask_1086 = |_out_rimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_wimask_1086 = &_out_wimask_T_1086; // @[RegisterRouter.scala:87:24] wire out_romask_1086 = |_out_romask_T_1086; // @[RegisterRouter.scala:87:24] wire out_womask_1086 = &_out_womask_T_1086; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1086 = out_rivalid_1_940 & out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10515 = out_f_rivalid_1086; // @[RegisterRouter.scala:87:24] wire out_f_roready_1086 = out_roready_1_940 & out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10516 = out_f_roready_1086; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1086 = out_wivalid_1_940 & out_wimask_1086; // @[RegisterRouter.scala:87:24] wire out_f_woready_1086 = out_woready_1_940 & out_womask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10517 = ~out_rimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10518 = ~out_wimask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10519 = ~out_romask_1086; // @[RegisterRouter.scala:87:24] wire _out_T_10520 = ~out_womask_1086; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_930 = {hi_978, flags_0_go, _out_prepend_T_930}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10521 = out_prepend_930; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10522 = _out_T_10521; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_931 = _out_T_10522; // @[RegisterRouter.scala:87:24] wire out_rimask_1087 = |_out_rimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_wimask_1087 = &_out_wimask_T_1087; // @[RegisterRouter.scala:87:24] wire out_romask_1087 = |_out_romask_T_1087; // @[RegisterRouter.scala:87:24] wire out_womask_1087 = &_out_womask_T_1087; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1087 = out_rivalid_1_941 & out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10524 = out_f_rivalid_1087; // @[RegisterRouter.scala:87:24] wire out_f_roready_1087 = out_roready_1_941 & out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10525 = out_f_roready_1087; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1087 = out_wivalid_1_941 & out_wimask_1087; // @[RegisterRouter.scala:87:24] wire out_f_woready_1087 = out_woready_1_941 & out_womask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10526 = ~out_rimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10527 = ~out_wimask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10528 = ~out_romask_1087; // @[RegisterRouter.scala:87:24] wire _out_T_10529 = ~out_womask_1087; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_931 = {hi_979, flags_0_go, _out_prepend_T_931}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10530 = out_prepend_931; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10531 = _out_T_10530; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_932 = _out_T_10531; // @[RegisterRouter.scala:87:24] wire out_rimask_1088 = |_out_rimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_wimask_1088 = &_out_wimask_T_1088; // @[RegisterRouter.scala:87:24] wire out_romask_1088 = |_out_romask_T_1088; // @[RegisterRouter.scala:87:24] wire out_womask_1088 = &_out_womask_T_1088; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1088 = out_rivalid_1_942 & out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10533 = out_f_rivalid_1088; // @[RegisterRouter.scala:87:24] wire out_f_roready_1088 = out_roready_1_942 & out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10534 = out_f_roready_1088; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1088 = out_wivalid_1_942 & out_wimask_1088; // @[RegisterRouter.scala:87:24] wire out_f_woready_1088 = out_woready_1_942 & out_womask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10535 = ~out_rimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10536 = ~out_wimask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10537 = ~out_romask_1088; // @[RegisterRouter.scala:87:24] wire _out_T_10538 = ~out_womask_1088; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_932 = {hi_980, flags_0_go, _out_prepend_T_932}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10539 = out_prepend_932; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10540 = _out_T_10539; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_933 = _out_T_10540; // @[RegisterRouter.scala:87:24] wire out_rimask_1089 = |_out_rimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_wimask_1089 = &_out_wimask_T_1089; // @[RegisterRouter.scala:87:24] wire out_romask_1089 = |_out_romask_T_1089; // @[RegisterRouter.scala:87:24] wire out_womask_1089 = &_out_womask_T_1089; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1089 = out_rivalid_1_943 & out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10542 = out_f_rivalid_1089; // @[RegisterRouter.scala:87:24] wire out_f_roready_1089 = out_roready_1_943 & out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10543 = out_f_roready_1089; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1089 = out_wivalid_1_943 & out_wimask_1089; // @[RegisterRouter.scala:87:24] wire out_f_woready_1089 = out_woready_1_943 & out_womask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10544 = ~out_rimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10545 = ~out_wimask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10546 = ~out_romask_1089; // @[RegisterRouter.scala:87:24] wire _out_T_10547 = ~out_womask_1089; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_933 = {hi_981, flags_0_go, _out_prepend_T_933}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10548 = out_prepend_933; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10549 = _out_T_10548; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_934 = _out_T_10549; // @[RegisterRouter.scala:87:24] wire out_rimask_1090 = |_out_rimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_wimask_1090 = &_out_wimask_T_1090; // @[RegisterRouter.scala:87:24] wire out_romask_1090 = |_out_romask_T_1090; // @[RegisterRouter.scala:87:24] wire out_womask_1090 = &_out_womask_T_1090; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1090 = out_rivalid_1_944 & out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10551 = out_f_rivalid_1090; // @[RegisterRouter.scala:87:24] wire out_f_roready_1090 = out_roready_1_944 & out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10552 = out_f_roready_1090; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1090 = out_wivalid_1_944 & out_wimask_1090; // @[RegisterRouter.scala:87:24] wire out_f_woready_1090 = out_woready_1_944 & out_womask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10553 = ~out_rimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10554 = ~out_wimask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10555 = ~out_romask_1090; // @[RegisterRouter.scala:87:24] wire _out_T_10556 = ~out_womask_1090; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_934 = {hi_982, flags_0_go, _out_prepend_T_934}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10557 = out_prepend_934; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10558 = _out_T_10557; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_935 = _out_T_10558; // @[RegisterRouter.scala:87:24] wire out_rimask_1091 = |_out_rimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_wimask_1091 = &_out_wimask_T_1091; // @[RegisterRouter.scala:87:24] wire out_romask_1091 = |_out_romask_T_1091; // @[RegisterRouter.scala:87:24] wire out_womask_1091 = &_out_womask_T_1091; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1091 = out_rivalid_1_945 & out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10560 = out_f_rivalid_1091; // @[RegisterRouter.scala:87:24] wire out_f_roready_1091 = out_roready_1_945 & out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10561 = out_f_roready_1091; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1091 = out_wivalid_1_945 & out_wimask_1091; // @[RegisterRouter.scala:87:24] wire out_f_woready_1091 = out_woready_1_945 & out_womask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10562 = ~out_rimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10563 = ~out_wimask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10564 = ~out_romask_1091; // @[RegisterRouter.scala:87:24] wire _out_T_10565 = ~out_womask_1091; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_935 = {hi_983, flags_0_go, _out_prepend_T_935}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10566 = out_prepend_935; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10567 = _out_T_10566; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_936 = _out_T_10567; // @[RegisterRouter.scala:87:24] wire out_rimask_1092 = |_out_rimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_wimask_1092 = &_out_wimask_T_1092; // @[RegisterRouter.scala:87:24] wire out_romask_1092 = |_out_romask_T_1092; // @[RegisterRouter.scala:87:24] wire out_womask_1092 = &_out_womask_T_1092; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1092 = out_rivalid_1_946 & out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10569 = out_f_rivalid_1092; // @[RegisterRouter.scala:87:24] wire out_f_roready_1092 = out_roready_1_946 & out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10570 = out_f_roready_1092; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1092 = out_wivalid_1_946 & out_wimask_1092; // @[RegisterRouter.scala:87:24] wire out_f_woready_1092 = out_woready_1_946 & out_womask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10571 = ~out_rimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10572 = ~out_wimask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10573 = ~out_romask_1092; // @[RegisterRouter.scala:87:24] wire _out_T_10574 = ~out_womask_1092; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_936 = {hi_984, flags_0_go, _out_prepend_T_936}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10575 = out_prepend_936; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10576 = _out_T_10575; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_250 = _out_T_10576; // @[MuxLiteral.scala:49:48] wire out_rimask_1093 = |_out_rimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_wimask_1093 = &_out_wimask_T_1093; // @[RegisterRouter.scala:87:24] wire out_romask_1093 = |_out_romask_T_1093; // @[RegisterRouter.scala:87:24] wire out_womask_1093 = &_out_womask_T_1093; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1093 = out_rivalid_1_947 & out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10578 = out_f_rivalid_1093; // @[RegisterRouter.scala:87:24] wire out_f_roready_1093 = out_roready_1_947 & out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10579 = out_f_roready_1093; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1093 = out_wivalid_1_947 & out_wimask_1093; // @[RegisterRouter.scala:87:24] wire out_f_woready_1093 = out_woready_1_947 & out_womask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10580 = ~out_rimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10581 = ~out_wimask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10582 = ~out_romask_1093; // @[RegisterRouter.scala:87:24] wire _out_T_10583 = ~out_womask_1093; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10585 = _out_T_10584; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_937 = _out_T_10585; // @[RegisterRouter.scala:87:24] wire out_rimask_1094 = |_out_rimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_wimask_1094 = &_out_wimask_T_1094; // @[RegisterRouter.scala:87:24] wire out_romask_1094 = |_out_romask_T_1094; // @[RegisterRouter.scala:87:24] wire out_womask_1094 = &_out_womask_T_1094; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1094 = out_rivalid_1_948 & out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10587 = out_f_rivalid_1094; // @[RegisterRouter.scala:87:24] wire out_f_roready_1094 = out_roready_1_948 & out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10588 = out_f_roready_1094; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1094 = out_wivalid_1_948 & out_wimask_1094; // @[RegisterRouter.scala:87:24] wire out_f_woready_1094 = out_woready_1_948 & out_womask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10589 = ~out_rimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10590 = ~out_wimask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10591 = ~out_romask_1094; // @[RegisterRouter.scala:87:24] wire _out_T_10592 = ~out_womask_1094; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_937 = {hi_826, flags_0_go, _out_prepend_T_937}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10593 = out_prepend_937; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10594 = _out_T_10593; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_938 = _out_T_10594; // @[RegisterRouter.scala:87:24] wire out_rimask_1095 = |_out_rimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_wimask_1095 = &_out_wimask_T_1095; // @[RegisterRouter.scala:87:24] wire out_romask_1095 = |_out_romask_T_1095; // @[RegisterRouter.scala:87:24] wire out_womask_1095 = &_out_womask_T_1095; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1095 = out_rivalid_1_949 & out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10596 = out_f_rivalid_1095; // @[RegisterRouter.scala:87:24] wire out_f_roready_1095 = out_roready_1_949 & out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10597 = out_f_roready_1095; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1095 = out_wivalid_1_949 & out_wimask_1095; // @[RegisterRouter.scala:87:24] wire out_f_woready_1095 = out_woready_1_949 & out_womask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10598 = ~out_rimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10599 = ~out_wimask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10600 = ~out_romask_1095; // @[RegisterRouter.scala:87:24] wire _out_T_10601 = ~out_womask_1095; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_938 = {hi_827, flags_0_go, _out_prepend_T_938}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10602 = out_prepend_938; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10603 = _out_T_10602; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_939 = _out_T_10603; // @[RegisterRouter.scala:87:24] wire out_rimask_1096 = |_out_rimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_wimask_1096 = &_out_wimask_T_1096; // @[RegisterRouter.scala:87:24] wire out_romask_1096 = |_out_romask_T_1096; // @[RegisterRouter.scala:87:24] wire out_womask_1096 = &_out_womask_T_1096; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1096 = out_rivalid_1_950 & out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10605 = out_f_rivalid_1096; // @[RegisterRouter.scala:87:24] wire out_f_roready_1096 = out_roready_1_950 & out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10606 = out_f_roready_1096; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1096 = out_wivalid_1_950 & out_wimask_1096; // @[RegisterRouter.scala:87:24] wire out_f_woready_1096 = out_woready_1_950 & out_womask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10607 = ~out_rimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10608 = ~out_wimask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10609 = ~out_romask_1096; // @[RegisterRouter.scala:87:24] wire _out_T_10610 = ~out_womask_1096; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_939 = {hi_828, flags_0_go, _out_prepend_T_939}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10611 = out_prepend_939; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10612 = _out_T_10611; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_940 = _out_T_10612; // @[RegisterRouter.scala:87:24] wire out_rimask_1097 = |_out_rimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_wimask_1097 = &_out_wimask_T_1097; // @[RegisterRouter.scala:87:24] wire out_romask_1097 = |_out_romask_T_1097; // @[RegisterRouter.scala:87:24] wire out_womask_1097 = &_out_womask_T_1097; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1097 = out_rivalid_1_951 & out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10614 = out_f_rivalid_1097; // @[RegisterRouter.scala:87:24] wire out_f_roready_1097 = out_roready_1_951 & out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10615 = out_f_roready_1097; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1097 = out_wivalid_1_951 & out_wimask_1097; // @[RegisterRouter.scala:87:24] wire out_f_woready_1097 = out_woready_1_951 & out_womask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10616 = ~out_rimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10617 = ~out_wimask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10618 = ~out_romask_1097; // @[RegisterRouter.scala:87:24] wire _out_T_10619 = ~out_womask_1097; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_940 = {hi_829, flags_0_go, _out_prepend_T_940}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10620 = out_prepend_940; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10621 = _out_T_10620; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_941 = _out_T_10621; // @[RegisterRouter.scala:87:24] wire out_rimask_1098 = |_out_rimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_wimask_1098 = &_out_wimask_T_1098; // @[RegisterRouter.scala:87:24] wire out_romask_1098 = |_out_romask_T_1098; // @[RegisterRouter.scala:87:24] wire out_womask_1098 = &_out_womask_T_1098; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1098 = out_rivalid_1_952 & out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10623 = out_f_rivalid_1098; // @[RegisterRouter.scala:87:24] wire out_f_roready_1098 = out_roready_1_952 & out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10624 = out_f_roready_1098; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1098 = out_wivalid_1_952 & out_wimask_1098; // @[RegisterRouter.scala:87:24] wire out_f_woready_1098 = out_woready_1_952 & out_womask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10625 = ~out_rimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10626 = ~out_wimask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10627 = ~out_romask_1098; // @[RegisterRouter.scala:87:24] wire _out_T_10628 = ~out_womask_1098; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_941 = {hi_830, flags_0_go, _out_prepend_T_941}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10629 = out_prepend_941; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10630 = _out_T_10629; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_942 = _out_T_10630; // @[RegisterRouter.scala:87:24] wire out_rimask_1099 = |_out_rimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_wimask_1099 = &_out_wimask_T_1099; // @[RegisterRouter.scala:87:24] wire out_romask_1099 = |_out_romask_T_1099; // @[RegisterRouter.scala:87:24] wire out_womask_1099 = &_out_womask_T_1099; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1099 = out_rivalid_1_953 & out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10632 = out_f_rivalid_1099; // @[RegisterRouter.scala:87:24] wire out_f_roready_1099 = out_roready_1_953 & out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10633 = out_f_roready_1099; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1099 = out_wivalid_1_953 & out_wimask_1099; // @[RegisterRouter.scala:87:24] wire out_f_woready_1099 = out_woready_1_953 & out_womask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10634 = ~out_rimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10635 = ~out_wimask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10636 = ~out_romask_1099; // @[RegisterRouter.scala:87:24] wire _out_T_10637 = ~out_womask_1099; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_942 = {hi_831, flags_0_go, _out_prepend_T_942}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10638 = out_prepend_942; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10639 = _out_T_10638; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_943 = _out_T_10639; // @[RegisterRouter.scala:87:24] wire out_rimask_1100 = |_out_rimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_wimask_1100 = &_out_wimask_T_1100; // @[RegisterRouter.scala:87:24] wire out_romask_1100 = |_out_romask_T_1100; // @[RegisterRouter.scala:87:24] wire out_womask_1100 = &_out_womask_T_1100; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1100 = out_rivalid_1_954 & out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10641 = out_f_rivalid_1100; // @[RegisterRouter.scala:87:24] wire out_f_roready_1100 = out_roready_1_954 & out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10642 = out_f_roready_1100; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1100 = out_wivalid_1_954 & out_wimask_1100; // @[RegisterRouter.scala:87:24] wire out_f_woready_1100 = out_woready_1_954 & out_womask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10643 = ~out_rimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10644 = ~out_wimask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10645 = ~out_romask_1100; // @[RegisterRouter.scala:87:24] wire _out_T_10646 = ~out_womask_1100; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_943 = {hi_832, flags_0_go, _out_prepend_T_943}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10647 = out_prepend_943; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10648 = _out_T_10647; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_231 = _out_T_10648; // @[MuxLiteral.scala:49:48] wire out_rimask_1101 = |_out_rimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_wimask_1101 = &_out_wimask_T_1101; // @[RegisterRouter.scala:87:24] wire out_romask_1101 = |_out_romask_T_1101; // @[RegisterRouter.scala:87:24] wire out_womask_1101 = &_out_womask_T_1101; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1101 = out_rivalid_1_955 & out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10650 = out_f_rivalid_1101; // @[RegisterRouter.scala:87:24] wire out_f_roready_1101 = out_roready_1_955 & out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10651 = out_f_roready_1101; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1101 = out_wivalid_1_955 & out_wimask_1101; // @[RegisterRouter.scala:87:24] wire out_f_woready_1101 = out_woready_1_955 & out_womask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10652 = ~out_rimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10653 = ~out_wimask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10654 = ~out_romask_1101; // @[RegisterRouter.scala:87:24] wire _out_T_10655 = ~out_womask_1101; // @[RegisterRouter.scala:87:24] wire out_rimask_1102 = |_out_rimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_wimask_1102 = &_out_wimask_T_1102; // @[RegisterRouter.scala:87:24] wire out_romask_1102 = |_out_romask_T_1102; // @[RegisterRouter.scala:87:24] wire out_womask_1102 = &_out_womask_T_1102; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1102 = out_rivalid_1_956 & out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10659 = out_f_rivalid_1102; // @[RegisterRouter.scala:87:24] wire out_f_roready_1102 = out_roready_1_956 & out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10660 = out_f_roready_1102; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1102 = out_wivalid_1_956 & out_wimask_1102; // @[RegisterRouter.scala:87:24] wire out_f_woready_1102 = out_woready_1_956 & out_womask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10661 = ~out_rimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10662 = ~out_wimask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10663 = ~out_romask_1102; // @[RegisterRouter.scala:87:24] wire _out_T_10664 = ~out_womask_1102; // @[RegisterRouter.scala:87:24] wire out_rimask_1103 = |_out_rimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_wimask_1103 = &_out_wimask_T_1103; // @[RegisterRouter.scala:87:24] wire out_romask_1103 = |_out_romask_T_1103; // @[RegisterRouter.scala:87:24] wire out_womask_1103 = &_out_womask_T_1103; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1103 = out_rivalid_1_957 & out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10668 = out_f_rivalid_1103; // @[RegisterRouter.scala:87:24] wire out_f_roready_1103 = out_roready_1_957 & out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10669 = out_f_roready_1103; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1103 = out_wivalid_1_957 & out_wimask_1103; // @[RegisterRouter.scala:87:24] wire out_f_woready_1103 = out_woready_1_957 & out_womask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10670 = ~out_rimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10671 = ~out_wimask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10672 = ~out_romask_1103; // @[RegisterRouter.scala:87:24] wire _out_T_10673 = ~out_womask_1103; // @[RegisterRouter.scala:87:24] wire out_rimask_1104 = |_out_rimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_wimask_1104 = &_out_wimask_T_1104; // @[RegisterRouter.scala:87:24] wire out_romask_1104 = |_out_romask_T_1104; // @[RegisterRouter.scala:87:24] wire out_womask_1104 = &_out_womask_T_1104; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1104 = out_rivalid_1_958 & out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10677 = out_f_rivalid_1104; // @[RegisterRouter.scala:87:24] wire out_f_roready_1104 = out_roready_1_958 & out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10678 = out_f_roready_1104; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1104 = out_wivalid_1_958 & out_wimask_1104; // @[RegisterRouter.scala:87:24] wire out_f_woready_1104 = out_woready_1_958 & out_womask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10679 = ~out_rimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10680 = ~out_wimask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10681 = ~out_romask_1104; // @[RegisterRouter.scala:87:24] wire _out_T_10682 = ~out_womask_1104; // @[RegisterRouter.scala:87:24] wire out_rimask_1105 = |_out_rimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_wimask_1105 = &_out_wimask_T_1105; // @[RegisterRouter.scala:87:24] wire out_romask_1105 = |_out_romask_T_1105; // @[RegisterRouter.scala:87:24] wire out_womask_1105 = &_out_womask_T_1105; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1105 = out_rivalid_1_959 & out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10686 = out_f_rivalid_1105; // @[RegisterRouter.scala:87:24] wire out_f_roready_1105 = out_roready_1_959 & out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10687 = out_f_roready_1105; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1105 = out_wivalid_1_959 & out_wimask_1105; // @[RegisterRouter.scala:87:24] wire out_f_woready_1105 = out_woready_1_959 & out_womask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10688 = ~out_rimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10689 = ~out_wimask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10690 = ~out_romask_1105; // @[RegisterRouter.scala:87:24] wire _out_T_10691 = ~out_womask_1105; // @[RegisterRouter.scala:87:24] wire out_rimask_1106 = |_out_rimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_wimask_1106 = &_out_wimask_T_1106; // @[RegisterRouter.scala:87:24] wire out_romask_1106 = |_out_romask_T_1106; // @[RegisterRouter.scala:87:24] wire out_womask_1106 = &_out_womask_T_1106; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1106 = out_rivalid_1_960 & out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10695 = out_f_rivalid_1106; // @[RegisterRouter.scala:87:24] wire out_f_roready_1106 = out_roready_1_960 & out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10696 = out_f_roready_1106; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1106 = out_wivalid_1_960 & out_wimask_1106; // @[RegisterRouter.scala:87:24] wire out_f_woready_1106 = out_woready_1_960 & out_womask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10697 = ~out_rimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10698 = ~out_wimask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10699 = ~out_romask_1106; // @[RegisterRouter.scala:87:24] wire _out_T_10700 = ~out_womask_1106; // @[RegisterRouter.scala:87:24] wire out_rimask_1107 = |_out_rimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_wimask_1107 = &_out_wimask_T_1107; // @[RegisterRouter.scala:87:24] wire out_romask_1107 = |_out_romask_T_1107; // @[RegisterRouter.scala:87:24] wire out_womask_1107 = &_out_womask_T_1107; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1107 = out_rivalid_1_961 & out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10704 = out_f_rivalid_1107; // @[RegisterRouter.scala:87:24] wire out_f_roready_1107 = out_roready_1_961 & out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10705 = out_f_roready_1107; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1107 = out_wivalid_1_961 & out_wimask_1107; // @[RegisterRouter.scala:87:24] wire out_f_woready_1107 = out_woready_1_961 & out_womask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10706 = ~out_rimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10707 = ~out_wimask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10708 = ~out_romask_1107; // @[RegisterRouter.scala:87:24] wire _out_T_10709 = ~out_womask_1107; // @[RegisterRouter.scala:87:24] wire out_rimask_1108 = |_out_rimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_wimask_1108 = &_out_wimask_T_1108; // @[RegisterRouter.scala:87:24] wire out_romask_1108 = |_out_romask_T_1108; // @[RegisterRouter.scala:87:24] wire out_womask_1108 = &_out_womask_T_1108; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1108 = out_rivalid_1_962 & out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10713 = out_f_rivalid_1108; // @[RegisterRouter.scala:87:24] wire out_f_roready_1108 = out_roready_1_962 & out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10714 = out_f_roready_1108; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1108 = out_wivalid_1_962 & out_wimask_1108; // @[RegisterRouter.scala:87:24] wire out_f_woready_1108 = out_woready_1_962 & out_womask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10715 = ~out_rimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10716 = ~out_wimask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10717 = ~out_romask_1108; // @[RegisterRouter.scala:87:24] wire _out_T_10718 = ~out_womask_1108; // @[RegisterRouter.scala:87:24] wire out_rimask_1109 = |_out_rimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_wimask_1109 = &_out_wimask_T_1109; // @[RegisterRouter.scala:87:24] wire out_romask_1109 = |_out_romask_T_1109; // @[RegisterRouter.scala:87:24] wire out_womask_1109 = &_out_womask_T_1109; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1109 = out_rivalid_1_963 & out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10722 = out_f_rivalid_1109; // @[RegisterRouter.scala:87:24] wire out_f_roready_1109 = out_roready_1_963 & out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10723 = out_f_roready_1109; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1109 = out_wivalid_1_963 & out_wimask_1109; // @[RegisterRouter.scala:87:24] wire out_f_woready_1109 = out_woready_1_963 & out_womask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10724 = ~out_rimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10725 = ~out_wimask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10726 = ~out_romask_1109; // @[RegisterRouter.scala:87:24] wire _out_T_10727 = ~out_womask_1109; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10729 = _out_T_10728; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_951 = _out_T_10729; // @[RegisterRouter.scala:87:24] wire out_rimask_1110 = |_out_rimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_wimask_1110 = &_out_wimask_T_1110; // @[RegisterRouter.scala:87:24] wire out_romask_1110 = |_out_romask_T_1110; // @[RegisterRouter.scala:87:24] wire out_womask_1110 = &_out_womask_T_1110; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1110 = out_rivalid_1_964 & out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10731 = out_f_rivalid_1110; // @[RegisterRouter.scala:87:24] wire out_f_roready_1110 = out_roready_1_964 & out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10732 = out_f_roready_1110; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1110 = out_wivalid_1_964 & out_wimask_1110; // @[RegisterRouter.scala:87:24] wire out_f_woready_1110 = out_woready_1_964 & out_womask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10733 = ~out_rimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10734 = ~out_wimask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10735 = ~out_romask_1110; // @[RegisterRouter.scala:87:24] wire _out_T_10736 = ~out_womask_1110; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_951 = {hi_242, flags_0_go, _out_prepend_T_951}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10737 = out_prepend_951; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10738 = _out_T_10737; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_952 = _out_T_10738; // @[RegisterRouter.scala:87:24] wire out_rimask_1111 = |_out_rimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_wimask_1111 = &_out_wimask_T_1111; // @[RegisterRouter.scala:87:24] wire out_romask_1111 = |_out_romask_T_1111; // @[RegisterRouter.scala:87:24] wire out_womask_1111 = &_out_womask_T_1111; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1111 = out_rivalid_1_965 & out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10740 = out_f_rivalid_1111; // @[RegisterRouter.scala:87:24] wire out_f_roready_1111 = out_roready_1_965 & out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10741 = out_f_roready_1111; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1111 = out_wivalid_1_965 & out_wimask_1111; // @[RegisterRouter.scala:87:24] wire out_f_woready_1111 = out_woready_1_965 & out_womask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10742 = ~out_rimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10743 = ~out_wimask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10744 = ~out_romask_1111; // @[RegisterRouter.scala:87:24] wire _out_T_10745 = ~out_womask_1111; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_952 = {hi_243, flags_0_go, _out_prepend_T_952}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10746 = out_prepend_952; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10747 = _out_T_10746; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_953 = _out_T_10747; // @[RegisterRouter.scala:87:24] wire out_rimask_1112 = |_out_rimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_wimask_1112 = &_out_wimask_T_1112; // @[RegisterRouter.scala:87:24] wire out_romask_1112 = |_out_romask_T_1112; // @[RegisterRouter.scala:87:24] wire out_womask_1112 = &_out_womask_T_1112; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1112 = out_rivalid_1_966 & out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10749 = out_f_rivalid_1112; // @[RegisterRouter.scala:87:24] wire out_f_roready_1112 = out_roready_1_966 & out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10750 = out_f_roready_1112; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1112 = out_wivalid_1_966 & out_wimask_1112; // @[RegisterRouter.scala:87:24] wire out_f_woready_1112 = out_woready_1_966 & out_womask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10751 = ~out_rimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10752 = ~out_wimask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10753 = ~out_romask_1112; // @[RegisterRouter.scala:87:24] wire _out_T_10754 = ~out_womask_1112; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_953 = {hi_244, flags_0_go, _out_prepend_T_953}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10755 = out_prepend_953; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10756 = _out_T_10755; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_954 = _out_T_10756; // @[RegisterRouter.scala:87:24] wire out_rimask_1113 = |_out_rimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_wimask_1113 = &_out_wimask_T_1113; // @[RegisterRouter.scala:87:24] wire out_romask_1113 = |_out_romask_T_1113; // @[RegisterRouter.scala:87:24] wire out_womask_1113 = &_out_womask_T_1113; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1113 = out_rivalid_1_967 & out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10758 = out_f_rivalid_1113; // @[RegisterRouter.scala:87:24] wire out_f_roready_1113 = out_roready_1_967 & out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10759 = out_f_roready_1113; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1113 = out_wivalid_1_967 & out_wimask_1113; // @[RegisterRouter.scala:87:24] wire out_f_woready_1113 = out_woready_1_967 & out_womask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10760 = ~out_rimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10761 = ~out_wimask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10762 = ~out_romask_1113; // @[RegisterRouter.scala:87:24] wire _out_T_10763 = ~out_womask_1113; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_954 = {hi_245, flags_0_go, _out_prepend_T_954}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10764 = out_prepend_954; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10765 = _out_T_10764; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_955 = _out_T_10765; // @[RegisterRouter.scala:87:24] wire out_rimask_1114 = |_out_rimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_wimask_1114 = &_out_wimask_T_1114; // @[RegisterRouter.scala:87:24] wire out_romask_1114 = |_out_romask_T_1114; // @[RegisterRouter.scala:87:24] wire out_womask_1114 = &_out_womask_T_1114; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1114 = out_rivalid_1_968 & out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10767 = out_f_rivalid_1114; // @[RegisterRouter.scala:87:24] wire out_f_roready_1114 = out_roready_1_968 & out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10768 = out_f_roready_1114; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1114 = out_wivalid_1_968 & out_wimask_1114; // @[RegisterRouter.scala:87:24] wire out_f_woready_1114 = out_woready_1_968 & out_womask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10769 = ~out_rimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10770 = ~out_wimask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10771 = ~out_romask_1114; // @[RegisterRouter.scala:87:24] wire _out_T_10772 = ~out_womask_1114; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_955 = {hi_246, flags_0_go, _out_prepend_T_955}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10773 = out_prepend_955; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10774 = _out_T_10773; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_956 = _out_T_10774; // @[RegisterRouter.scala:87:24] wire out_rimask_1115 = |_out_rimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_wimask_1115 = &_out_wimask_T_1115; // @[RegisterRouter.scala:87:24] wire out_romask_1115 = |_out_romask_T_1115; // @[RegisterRouter.scala:87:24] wire out_womask_1115 = &_out_womask_T_1115; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1115 = out_rivalid_1_969 & out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10776 = out_f_rivalid_1115; // @[RegisterRouter.scala:87:24] wire out_f_roready_1115 = out_roready_1_969 & out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10777 = out_f_roready_1115; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1115 = out_wivalid_1_969 & out_wimask_1115; // @[RegisterRouter.scala:87:24] wire out_f_woready_1115 = out_woready_1_969 & out_womask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10778 = ~out_rimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10779 = ~out_wimask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10780 = ~out_romask_1115; // @[RegisterRouter.scala:87:24] wire _out_T_10781 = ~out_womask_1115; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_956 = {hi_247, flags_0_go, _out_prepend_T_956}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10782 = out_prepend_956; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10783 = _out_T_10782; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_957 = _out_T_10783; // @[RegisterRouter.scala:87:24] wire out_rimask_1116 = |_out_rimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_wimask_1116 = &_out_wimask_T_1116; // @[RegisterRouter.scala:87:24] wire out_romask_1116 = |_out_romask_T_1116; // @[RegisterRouter.scala:87:24] wire out_womask_1116 = &_out_womask_T_1116; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1116 = out_rivalid_1_970 & out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10785 = out_f_rivalid_1116; // @[RegisterRouter.scala:87:24] wire out_f_roready_1116 = out_roready_1_970 & out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10786 = out_f_roready_1116; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1116 = out_wivalid_1_970 & out_wimask_1116; // @[RegisterRouter.scala:87:24] wire out_f_woready_1116 = out_woready_1_970 & out_womask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10787 = ~out_rimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10788 = ~out_wimask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10789 = ~out_romask_1116; // @[RegisterRouter.scala:87:24] wire _out_T_10790 = ~out_womask_1116; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_957 = {hi_248, flags_0_go, _out_prepend_T_957}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10791 = out_prepend_957; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10792 = _out_T_10791; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_158 = _out_T_10792; // @[MuxLiteral.scala:49:48] wire out_rimask_1117 = |_out_rimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_wimask_1117 = &_out_wimask_T_1117; // @[RegisterRouter.scala:87:24] wire out_romask_1117 = |_out_romask_T_1117; // @[RegisterRouter.scala:87:24] wire out_womask_1117 = &_out_womask_T_1117; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1117 = out_rivalid_1_971 & out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10794 = out_f_rivalid_1117; // @[RegisterRouter.scala:87:24] wire out_f_roready_1117 = out_roready_1_971 & out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10795 = out_f_roready_1117; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1117 = out_wivalid_1_971 & out_wimask_1117; // @[RegisterRouter.scala:87:24] wire out_f_woready_1117 = out_woready_1_971 & out_womask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10796 = ~out_rimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10797 = ~out_wimask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10798 = ~out_romask_1117; // @[RegisterRouter.scala:87:24] wire _out_T_10799 = ~out_womask_1117; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10801 = _out_T_10800; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_958 = _out_T_10801; // @[RegisterRouter.scala:87:24] wire out_rimask_1118 = |_out_rimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_wimask_1118 = &_out_wimask_T_1118; // @[RegisterRouter.scala:87:24] wire out_romask_1118 = |_out_romask_T_1118; // @[RegisterRouter.scala:87:24] wire out_womask_1118 = &_out_womask_T_1118; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1118 = out_rivalid_1_972 & out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10803 = out_f_rivalid_1118; // @[RegisterRouter.scala:87:24] wire out_f_roready_1118 = out_roready_1_972 & out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10804 = out_f_roready_1118; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1118 = out_wivalid_1_972 & out_wimask_1118; // @[RegisterRouter.scala:87:24] wire out_f_woready_1118 = out_woready_1_972 & out_womask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10805 = ~out_rimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10806 = ~out_wimask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10807 = ~out_romask_1118; // @[RegisterRouter.scala:87:24] wire _out_T_10808 = ~out_womask_1118; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_958 = {hi_466, flags_0_go, _out_prepend_T_958}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10809 = out_prepend_958; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10810 = _out_T_10809; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_959 = _out_T_10810; // @[RegisterRouter.scala:87:24] wire out_rimask_1119 = |_out_rimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_wimask_1119 = &_out_wimask_T_1119; // @[RegisterRouter.scala:87:24] wire out_romask_1119 = |_out_romask_T_1119; // @[RegisterRouter.scala:87:24] wire out_womask_1119 = &_out_womask_T_1119; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1119 = out_rivalid_1_973 & out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10812 = out_f_rivalid_1119; // @[RegisterRouter.scala:87:24] wire out_f_roready_1119 = out_roready_1_973 & out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10813 = out_f_roready_1119; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1119 = out_wivalid_1_973 & out_wimask_1119; // @[RegisterRouter.scala:87:24] wire out_f_woready_1119 = out_woready_1_973 & out_womask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10814 = ~out_rimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10815 = ~out_wimask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10816 = ~out_romask_1119; // @[RegisterRouter.scala:87:24] wire _out_T_10817 = ~out_womask_1119; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_959 = {hi_467, flags_0_go, _out_prepend_T_959}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10818 = out_prepend_959; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10819 = _out_T_10818; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_960 = _out_T_10819; // @[RegisterRouter.scala:87:24] wire out_rimask_1120 = |_out_rimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_wimask_1120 = &_out_wimask_T_1120; // @[RegisterRouter.scala:87:24] wire out_romask_1120 = |_out_romask_T_1120; // @[RegisterRouter.scala:87:24] wire out_womask_1120 = &_out_womask_T_1120; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1120 = out_rivalid_1_974 & out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10821 = out_f_rivalid_1120; // @[RegisterRouter.scala:87:24] wire out_f_roready_1120 = out_roready_1_974 & out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10822 = out_f_roready_1120; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1120 = out_wivalid_1_974 & out_wimask_1120; // @[RegisterRouter.scala:87:24] wire out_f_woready_1120 = out_woready_1_974 & out_womask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10823 = ~out_rimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10824 = ~out_wimask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10825 = ~out_romask_1120; // @[RegisterRouter.scala:87:24] wire _out_T_10826 = ~out_womask_1120; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_960 = {hi_468, flags_0_go, _out_prepend_T_960}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10827 = out_prepend_960; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10828 = _out_T_10827; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_961 = _out_T_10828; // @[RegisterRouter.scala:87:24] wire out_rimask_1121 = |_out_rimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_wimask_1121 = &_out_wimask_T_1121; // @[RegisterRouter.scala:87:24] wire out_romask_1121 = |_out_romask_T_1121; // @[RegisterRouter.scala:87:24] wire out_womask_1121 = &_out_womask_T_1121; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1121 = out_rivalid_1_975 & out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10830 = out_f_rivalid_1121; // @[RegisterRouter.scala:87:24] wire out_f_roready_1121 = out_roready_1_975 & out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10831 = out_f_roready_1121; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1121 = out_wivalid_1_975 & out_wimask_1121; // @[RegisterRouter.scala:87:24] wire out_f_woready_1121 = out_woready_1_975 & out_womask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10832 = ~out_rimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10833 = ~out_wimask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10834 = ~out_romask_1121; // @[RegisterRouter.scala:87:24] wire _out_T_10835 = ~out_womask_1121; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_961 = {hi_469, flags_0_go, _out_prepend_T_961}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10836 = out_prepend_961; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10837 = _out_T_10836; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_962 = _out_T_10837; // @[RegisterRouter.scala:87:24] wire out_rimask_1122 = |_out_rimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_wimask_1122 = &_out_wimask_T_1122; // @[RegisterRouter.scala:87:24] wire out_romask_1122 = |_out_romask_T_1122; // @[RegisterRouter.scala:87:24] wire out_womask_1122 = &_out_womask_T_1122; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1122 = out_rivalid_1_976 & out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10839 = out_f_rivalid_1122; // @[RegisterRouter.scala:87:24] wire out_f_roready_1122 = out_roready_1_976 & out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10840 = out_f_roready_1122; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1122 = out_wivalid_1_976 & out_wimask_1122; // @[RegisterRouter.scala:87:24] wire out_f_woready_1122 = out_woready_1_976 & out_womask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10841 = ~out_rimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10842 = ~out_wimask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10843 = ~out_romask_1122; // @[RegisterRouter.scala:87:24] wire _out_T_10844 = ~out_womask_1122; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_962 = {hi_470, flags_0_go, _out_prepend_T_962}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10845 = out_prepend_962; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10846 = _out_T_10845; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_963 = _out_T_10846; // @[RegisterRouter.scala:87:24] wire out_rimask_1123 = |_out_rimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_wimask_1123 = &_out_wimask_T_1123; // @[RegisterRouter.scala:87:24] wire out_romask_1123 = |_out_romask_T_1123; // @[RegisterRouter.scala:87:24] wire out_womask_1123 = &_out_womask_T_1123; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1123 = out_rivalid_1_977 & out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10848 = out_f_rivalid_1123; // @[RegisterRouter.scala:87:24] wire out_f_roready_1123 = out_roready_1_977 & out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10849 = out_f_roready_1123; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1123 = out_wivalid_1_977 & out_wimask_1123; // @[RegisterRouter.scala:87:24] wire out_f_woready_1123 = out_woready_1_977 & out_womask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10850 = ~out_rimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10851 = ~out_wimask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10852 = ~out_romask_1123; // @[RegisterRouter.scala:87:24] wire _out_T_10853 = ~out_womask_1123; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_963 = {hi_471, flags_0_go, _out_prepend_T_963}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10854 = out_prepend_963; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10855 = _out_T_10854; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_964 = _out_T_10855; // @[RegisterRouter.scala:87:24] wire out_rimask_1124 = |_out_rimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_wimask_1124 = &_out_wimask_T_1124; // @[RegisterRouter.scala:87:24] wire out_romask_1124 = |_out_romask_T_1124; // @[RegisterRouter.scala:87:24] wire out_womask_1124 = &_out_womask_T_1124; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1124 = out_rivalid_1_978 & out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10857 = out_f_rivalid_1124; // @[RegisterRouter.scala:87:24] wire out_f_roready_1124 = out_roready_1_978 & out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10858 = out_f_roready_1124; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1124 = out_wivalid_1_978 & out_wimask_1124; // @[RegisterRouter.scala:87:24] wire out_f_woready_1124 = out_woready_1_978 & out_womask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10859 = ~out_rimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10860 = ~out_wimask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10861 = ~out_romask_1124; // @[RegisterRouter.scala:87:24] wire _out_T_10862 = ~out_womask_1124; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_964 = {hi_472, flags_0_go, _out_prepend_T_964}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10863 = out_prepend_964; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10864 = _out_T_10863; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_186 = _out_T_10864; // @[MuxLiteral.scala:49:48] wire out_rimask_1125 = |_out_rimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_wimask_1125 = &_out_wimask_T_1125; // @[RegisterRouter.scala:87:24] wire out_romask_1125 = |_out_romask_T_1125; // @[RegisterRouter.scala:87:24] wire out_womask_1125 = &_out_womask_T_1125; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1125 = out_rivalid_1_979 & out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10866 = out_f_rivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_roready_1125 = out_roready_1_979 & out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10867 = out_f_roready_1125; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1125 = out_wivalid_1_979 & out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10868 = out_f_wivalid_1125; // @[RegisterRouter.scala:87:24] wire out_f_woready_1125 = out_woready_1_979 & out_womask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10869 = out_f_woready_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10870 = ~out_rimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10871 = ~out_wimask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10872 = ~out_romask_1125; // @[RegisterRouter.scala:87:24] wire _out_T_10873 = ~out_womask_1125; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10875 = _out_T_10874; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_965 = _out_T_10875; // @[RegisterRouter.scala:87:24] wire out_rimask_1126 = |_out_rimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_wimask_1126 = &_out_wimask_T_1126; // @[RegisterRouter.scala:87:24] wire out_romask_1126 = |_out_romask_T_1126; // @[RegisterRouter.scala:87:24] wire out_womask_1126 = &_out_womask_T_1126; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1126 = out_rivalid_1_980 & out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10877 = out_f_rivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_roready_1126 = out_roready_1_980 & out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10878 = out_f_roready_1126; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1126 = out_wivalid_1_980 & out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10879 = out_f_wivalid_1126; // @[RegisterRouter.scala:87:24] wire out_f_woready_1126 = out_woready_1_980 & out_womask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10880 = out_f_woready_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10881 = ~out_rimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10882 = ~out_wimask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10883 = ~out_romask_1126; // @[RegisterRouter.scala:87:24] wire _out_T_10884 = ~out_womask_1126; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_965 = {abstractDataMem_17, _out_prepend_T_965}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10885 = out_prepend_965; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10886 = _out_T_10885; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_966 = _out_T_10886; // @[RegisterRouter.scala:87:24] wire out_rimask_1127 = |_out_rimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_wimask_1127 = &_out_wimask_T_1127; // @[RegisterRouter.scala:87:24] wire out_romask_1127 = |_out_romask_T_1127; // @[RegisterRouter.scala:87:24] wire out_womask_1127 = &_out_womask_T_1127; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1127 = out_rivalid_1_981 & out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10888 = out_f_rivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_roready_1127 = out_roready_1_981 & out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10889 = out_f_roready_1127; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1127 = out_wivalid_1_981 & out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10890 = out_f_wivalid_1127; // @[RegisterRouter.scala:87:24] wire out_f_woready_1127 = out_woready_1_981 & out_womask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10891 = out_f_woready_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10892 = ~out_rimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10893 = ~out_wimask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10894 = ~out_romask_1127; // @[RegisterRouter.scala:87:24] wire _out_T_10895 = ~out_womask_1127; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_966 = {abstractDataMem_18, _out_prepend_T_966}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10896 = out_prepend_966; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10897 = _out_T_10896; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_967 = _out_T_10897; // @[RegisterRouter.scala:87:24] wire out_rimask_1128 = |_out_rimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_wimask_1128 = &_out_wimask_T_1128; // @[RegisterRouter.scala:87:24] wire out_romask_1128 = |_out_romask_T_1128; // @[RegisterRouter.scala:87:24] wire out_womask_1128 = &_out_womask_T_1128; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1128 = out_rivalid_1_982 & out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10899 = out_f_rivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_roready_1128 = out_roready_1_982 & out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10900 = out_f_roready_1128; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1128 = out_wivalid_1_982 & out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10901 = out_f_wivalid_1128; // @[RegisterRouter.scala:87:24] wire out_f_woready_1128 = out_woready_1_982 & out_womask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10902 = out_f_woready_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10903 = ~out_rimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10904 = ~out_wimask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10905 = ~out_romask_1128; // @[RegisterRouter.scala:87:24] wire _out_T_10906 = ~out_womask_1128; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_967 = {abstractDataMem_19, _out_prepend_T_967}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10907 = out_prepend_967; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10908 = _out_T_10907; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_968 = _out_T_10908; // @[RegisterRouter.scala:87:24] wire out_rimask_1129 = |_out_rimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_wimask_1129 = &_out_wimask_T_1129; // @[RegisterRouter.scala:87:24] wire out_romask_1129 = |_out_romask_T_1129; // @[RegisterRouter.scala:87:24] wire out_womask_1129 = &_out_womask_T_1129; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1129 = out_rivalid_1_983 & out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10910 = out_f_rivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_roready_1129 = out_roready_1_983 & out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10911 = out_f_roready_1129; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1129 = out_wivalid_1_983 & out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10912 = out_f_wivalid_1129; // @[RegisterRouter.scala:87:24] wire out_f_woready_1129 = out_woready_1_983 & out_womask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10913 = out_f_woready_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10914 = ~out_rimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10915 = ~out_wimask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10916 = ~out_romask_1129; // @[RegisterRouter.scala:87:24] wire _out_T_10917 = ~out_womask_1129; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_968 = {abstractDataMem_20, _out_prepend_T_968}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10918 = out_prepend_968; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10919 = _out_T_10918; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_969 = _out_T_10919; // @[RegisterRouter.scala:87:24] wire out_rimask_1130 = |_out_rimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_wimask_1130 = &_out_wimask_T_1130; // @[RegisterRouter.scala:87:24] wire out_romask_1130 = |_out_romask_T_1130; // @[RegisterRouter.scala:87:24] wire out_womask_1130 = &_out_womask_T_1130; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1130 = out_rivalid_1_984 & out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10921 = out_f_rivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_roready_1130 = out_roready_1_984 & out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10922 = out_f_roready_1130; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1130 = out_wivalid_1_984 & out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10923 = out_f_wivalid_1130; // @[RegisterRouter.scala:87:24] wire out_f_woready_1130 = out_woready_1_984 & out_womask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10924 = out_f_woready_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10925 = ~out_rimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10926 = ~out_wimask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10927 = ~out_romask_1130; // @[RegisterRouter.scala:87:24] wire _out_T_10928 = ~out_womask_1130; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_969 = {abstractDataMem_21, _out_prepend_T_969}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10929 = out_prepend_969; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_10930 = _out_T_10929; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_970 = _out_T_10930; // @[RegisterRouter.scala:87:24] wire out_rimask_1131 = |_out_rimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_wimask_1131 = &_out_wimask_T_1131; // @[RegisterRouter.scala:87:24] wire out_romask_1131 = |_out_romask_T_1131; // @[RegisterRouter.scala:87:24] wire out_womask_1131 = &_out_womask_T_1131; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1131 = out_rivalid_1_985 & out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10932 = out_f_rivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_roready_1131 = out_roready_1_985 & out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10933 = out_f_roready_1131; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1131 = out_wivalid_1_985 & out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10934 = out_f_wivalid_1131; // @[RegisterRouter.scala:87:24] wire out_f_woready_1131 = out_woready_1_985 & out_womask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10935 = out_f_woready_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10936 = ~out_rimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10937 = ~out_wimask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10938 = ~out_romask_1131; // @[RegisterRouter.scala:87:24] wire _out_T_10939 = ~out_womask_1131; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_970 = {abstractDataMem_22, _out_prepend_T_970}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10940 = out_prepend_970; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_10941 = _out_T_10940; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_971 = _out_T_10941; // @[RegisterRouter.scala:87:24] wire out_rimask_1132 = |_out_rimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_wimask_1132 = &_out_wimask_T_1132; // @[RegisterRouter.scala:87:24] wire out_romask_1132 = |_out_romask_T_1132; // @[RegisterRouter.scala:87:24] wire out_womask_1132 = &_out_womask_T_1132; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1132 = out_rivalid_1_986 & out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10943 = out_f_rivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_roready_1132 = out_roready_1_986 & out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10944 = out_f_roready_1132; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1132 = out_wivalid_1_986 & out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10945 = out_f_wivalid_1132; // @[RegisterRouter.scala:87:24] wire out_f_woready_1132 = out_woready_1_986 & out_womask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10946 = out_f_woready_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10947 = ~out_rimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10948 = ~out_wimask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10949 = ~out_romask_1132; // @[RegisterRouter.scala:87:24] wire _out_T_10950 = ~out_womask_1132; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_971 = {abstractDataMem_23, _out_prepend_T_971}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10951 = out_prepend_971; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_10952 = _out_T_10951; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_114 = _out_T_10952; // @[MuxLiteral.scala:49:48] wire out_rimask_1133 = |_out_rimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_wimask_1133 = &_out_wimask_T_1133; // @[RegisterRouter.scala:87:24] wire out_romask_1133 = |_out_romask_T_1133; // @[RegisterRouter.scala:87:24] wire out_womask_1133 = &_out_womask_T_1133; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1133 = out_rivalid_1_987 & out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10954 = out_f_rivalid_1133; // @[RegisterRouter.scala:87:24] wire out_f_roready_1133 = out_roready_1_987 & out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10955 = out_f_roready_1133; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1133 = out_wivalid_1_987 & out_wimask_1133; // @[RegisterRouter.scala:87:24] wire out_f_woready_1133 = out_woready_1_987 & out_womask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10956 = ~out_rimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10957 = ~out_wimask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10958 = ~out_romask_1133; // @[RegisterRouter.scala:87:24] wire _out_T_10959 = ~out_womask_1133; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_10961 = _out_T_10960; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_972 = _out_T_10961; // @[RegisterRouter.scala:87:24] wire out_rimask_1134 = |_out_rimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_wimask_1134 = &_out_wimask_T_1134; // @[RegisterRouter.scala:87:24] wire out_romask_1134 = |_out_romask_T_1134; // @[RegisterRouter.scala:87:24] wire out_womask_1134 = &_out_womask_T_1134; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1134 = out_rivalid_1_988 & out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10963 = out_f_rivalid_1134; // @[RegisterRouter.scala:87:24] wire out_f_roready_1134 = out_roready_1_988 & out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10964 = out_f_roready_1134; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1134 = out_wivalid_1_988 & out_wimask_1134; // @[RegisterRouter.scala:87:24] wire out_f_woready_1134 = out_woready_1_988 & out_womask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10965 = ~out_rimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10966 = ~out_wimask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10967 = ~out_romask_1134; // @[RegisterRouter.scala:87:24] wire _out_T_10968 = ~out_womask_1134; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_972 = {hi_346, flags_0_go, _out_prepend_T_972}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10969 = out_prepend_972; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_10970 = _out_T_10969; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_973 = _out_T_10970; // @[RegisterRouter.scala:87:24] wire out_rimask_1135 = |_out_rimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_wimask_1135 = &_out_wimask_T_1135; // @[RegisterRouter.scala:87:24] wire out_romask_1135 = |_out_romask_T_1135; // @[RegisterRouter.scala:87:24] wire out_womask_1135 = &_out_womask_T_1135; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1135 = out_rivalid_1_989 & out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10972 = out_f_rivalid_1135; // @[RegisterRouter.scala:87:24] wire out_f_roready_1135 = out_roready_1_989 & out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10973 = out_f_roready_1135; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1135 = out_wivalid_1_989 & out_wimask_1135; // @[RegisterRouter.scala:87:24] wire out_f_woready_1135 = out_woready_1_989 & out_womask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10974 = ~out_rimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10975 = ~out_wimask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10976 = ~out_romask_1135; // @[RegisterRouter.scala:87:24] wire _out_T_10977 = ~out_womask_1135; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_973 = {hi_347, flags_0_go, _out_prepend_T_973}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10978 = out_prepend_973; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_10979 = _out_T_10978; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_974 = _out_T_10979; // @[RegisterRouter.scala:87:24] wire out_rimask_1136 = |_out_rimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_wimask_1136 = &_out_wimask_T_1136; // @[RegisterRouter.scala:87:24] wire out_romask_1136 = |_out_romask_T_1136; // @[RegisterRouter.scala:87:24] wire out_womask_1136 = &_out_womask_T_1136; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1136 = out_rivalid_1_990 & out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10981 = out_f_rivalid_1136; // @[RegisterRouter.scala:87:24] wire out_f_roready_1136 = out_roready_1_990 & out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10982 = out_f_roready_1136; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1136 = out_wivalid_1_990 & out_wimask_1136; // @[RegisterRouter.scala:87:24] wire out_f_woready_1136 = out_woready_1_990 & out_womask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10983 = ~out_rimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10984 = ~out_wimask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10985 = ~out_romask_1136; // @[RegisterRouter.scala:87:24] wire _out_T_10986 = ~out_womask_1136; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_974 = {hi_348, flags_0_go, _out_prepend_T_974}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10987 = out_prepend_974; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_10988 = _out_T_10987; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_975 = _out_T_10988; // @[RegisterRouter.scala:87:24] wire out_rimask_1137 = |_out_rimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_wimask_1137 = &_out_wimask_T_1137; // @[RegisterRouter.scala:87:24] wire out_romask_1137 = |_out_romask_T_1137; // @[RegisterRouter.scala:87:24] wire out_womask_1137 = &_out_womask_T_1137; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1137 = out_rivalid_1_991 & out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10990 = out_f_rivalid_1137; // @[RegisterRouter.scala:87:24] wire out_f_roready_1137 = out_roready_1_991 & out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10991 = out_f_roready_1137; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1137 = out_wivalid_1_991 & out_wimask_1137; // @[RegisterRouter.scala:87:24] wire out_f_woready_1137 = out_woready_1_991 & out_womask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10992 = ~out_rimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10993 = ~out_wimask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10994 = ~out_romask_1137; // @[RegisterRouter.scala:87:24] wire _out_T_10995 = ~out_womask_1137; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_975 = {hi_349, flags_0_go, _out_prepend_T_975}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10996 = out_prepend_975; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_10997 = _out_T_10996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_976 = _out_T_10997; // @[RegisterRouter.scala:87:24] wire out_rimask_1138 = |_out_rimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_wimask_1138 = &_out_wimask_T_1138; // @[RegisterRouter.scala:87:24] wire out_romask_1138 = |_out_romask_T_1138; // @[RegisterRouter.scala:87:24] wire out_womask_1138 = &_out_womask_T_1138; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1138 = out_rivalid_1_992 & out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_10999 = out_f_rivalid_1138; // @[RegisterRouter.scala:87:24] wire out_f_roready_1138 = out_roready_1_992 & out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11000 = out_f_roready_1138; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1138 = out_wivalid_1_992 & out_wimask_1138; // @[RegisterRouter.scala:87:24] wire out_f_woready_1138 = out_woready_1_992 & out_womask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11001 = ~out_rimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11002 = ~out_wimask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11003 = ~out_romask_1138; // @[RegisterRouter.scala:87:24] wire _out_T_11004 = ~out_womask_1138; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_976 = {hi_350, flags_0_go, _out_prepend_T_976}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11005 = out_prepend_976; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11006 = _out_T_11005; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_977 = _out_T_11006; // @[RegisterRouter.scala:87:24] wire out_rimask_1139 = |_out_rimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_wimask_1139 = &_out_wimask_T_1139; // @[RegisterRouter.scala:87:24] wire out_romask_1139 = |_out_romask_T_1139; // @[RegisterRouter.scala:87:24] wire out_womask_1139 = &_out_womask_T_1139; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1139 = out_rivalid_1_993 & out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11008 = out_f_rivalid_1139; // @[RegisterRouter.scala:87:24] wire out_f_roready_1139 = out_roready_1_993 & out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11009 = out_f_roready_1139; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1139 = out_wivalid_1_993 & out_wimask_1139; // @[RegisterRouter.scala:87:24] wire out_f_woready_1139 = out_woready_1_993 & out_womask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11010 = ~out_rimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11011 = ~out_wimask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11012 = ~out_romask_1139; // @[RegisterRouter.scala:87:24] wire _out_T_11013 = ~out_womask_1139; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_977 = {hi_351, flags_0_go, _out_prepend_T_977}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11014 = out_prepend_977; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11015 = _out_T_11014; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_978 = _out_T_11015; // @[RegisterRouter.scala:87:24] wire out_rimask_1140 = |_out_rimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_wimask_1140 = &_out_wimask_T_1140; // @[RegisterRouter.scala:87:24] wire out_romask_1140 = |_out_romask_T_1140; // @[RegisterRouter.scala:87:24] wire out_womask_1140 = &_out_womask_T_1140; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1140 = out_rivalid_1_994 & out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11017 = out_f_rivalid_1140; // @[RegisterRouter.scala:87:24] wire out_f_roready_1140 = out_roready_1_994 & out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11018 = out_f_roready_1140; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1140 = out_wivalid_1_994 & out_wimask_1140; // @[RegisterRouter.scala:87:24] wire out_f_woready_1140 = out_woready_1_994 & out_womask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11019 = ~out_rimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11020 = ~out_wimask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11021 = ~out_romask_1140; // @[RegisterRouter.scala:87:24] wire _out_T_11022 = ~out_womask_1140; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_978 = {hi_352, flags_0_go, _out_prepend_T_978}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11023 = out_prepend_978; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11024 = _out_T_11023; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_171 = _out_T_11024; // @[MuxLiteral.scala:49:48] wire out_rimask_1141 = |_out_rimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_wimask_1141 = &_out_wimask_T_1141; // @[RegisterRouter.scala:87:24] wire out_romask_1141 = |_out_romask_T_1141; // @[RegisterRouter.scala:87:24] wire out_womask_1141 = &_out_womask_T_1141; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1141 = out_rivalid_1_995 & out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11026 = out_f_rivalid_1141; // @[RegisterRouter.scala:87:24] wire out_f_roready_1141 = out_roready_1_995 & out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11027 = out_f_roready_1141; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1141 = out_wivalid_1_995 & out_wimask_1141; // @[RegisterRouter.scala:87:24] wire out_f_woready_1141 = out_woready_1_995 & out_womask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11028 = ~out_rimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11029 = ~out_wimask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11030 = ~out_romask_1141; // @[RegisterRouter.scala:87:24] wire _out_T_11031 = ~out_womask_1141; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11033 = _out_T_11032; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_979 = _out_T_11033; // @[RegisterRouter.scala:87:24] wire out_rimask_1142 = |_out_rimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_wimask_1142 = &_out_wimask_T_1142; // @[RegisterRouter.scala:87:24] wire out_romask_1142 = |_out_romask_T_1142; // @[RegisterRouter.scala:87:24] wire out_womask_1142 = &_out_womask_T_1142; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1142 = out_rivalid_1_996 & out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11035 = out_f_rivalid_1142; // @[RegisterRouter.scala:87:24] wire out_f_roready_1142 = out_roready_1_996 & out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11036 = out_f_roready_1142; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1142 = out_wivalid_1_996 & out_wimask_1142; // @[RegisterRouter.scala:87:24] wire out_f_woready_1142 = out_woready_1_996 & out_womask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11037 = ~out_rimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11038 = ~out_wimask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11039 = ~out_romask_1142; // @[RegisterRouter.scala:87:24] wire _out_T_11040 = ~out_womask_1142; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_979 = {hi_90, flags_0_go, _out_prepend_T_979}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11041 = out_prepend_979; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11042 = _out_T_11041; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_980 = _out_T_11042; // @[RegisterRouter.scala:87:24] wire out_rimask_1143 = |_out_rimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_wimask_1143 = &_out_wimask_T_1143; // @[RegisterRouter.scala:87:24] wire out_romask_1143 = |_out_romask_T_1143; // @[RegisterRouter.scala:87:24] wire out_womask_1143 = &_out_womask_T_1143; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1143 = out_rivalid_1_997 & out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11044 = out_f_rivalid_1143; // @[RegisterRouter.scala:87:24] wire out_f_roready_1143 = out_roready_1_997 & out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11045 = out_f_roready_1143; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1143 = out_wivalid_1_997 & out_wimask_1143; // @[RegisterRouter.scala:87:24] wire out_f_woready_1143 = out_woready_1_997 & out_womask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11046 = ~out_rimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11047 = ~out_wimask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11048 = ~out_romask_1143; // @[RegisterRouter.scala:87:24] wire _out_T_11049 = ~out_womask_1143; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_980 = {hi_91, flags_0_go, _out_prepend_T_980}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11050 = out_prepend_980; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11051 = _out_T_11050; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_981 = _out_T_11051; // @[RegisterRouter.scala:87:24] wire out_rimask_1144 = |_out_rimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_wimask_1144 = &_out_wimask_T_1144; // @[RegisterRouter.scala:87:24] wire out_romask_1144 = |_out_romask_T_1144; // @[RegisterRouter.scala:87:24] wire out_womask_1144 = &_out_womask_T_1144; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1144 = out_rivalid_1_998 & out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11053 = out_f_rivalid_1144; // @[RegisterRouter.scala:87:24] wire out_f_roready_1144 = out_roready_1_998 & out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11054 = out_f_roready_1144; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1144 = out_wivalid_1_998 & out_wimask_1144; // @[RegisterRouter.scala:87:24] wire out_f_woready_1144 = out_woready_1_998 & out_womask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11055 = ~out_rimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11056 = ~out_wimask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11057 = ~out_romask_1144; // @[RegisterRouter.scala:87:24] wire _out_T_11058 = ~out_womask_1144; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_981 = {hi_92, flags_0_go, _out_prepend_T_981}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11059 = out_prepend_981; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11060 = _out_T_11059; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_982 = _out_T_11060; // @[RegisterRouter.scala:87:24] wire out_rimask_1145 = |_out_rimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_wimask_1145 = &_out_wimask_T_1145; // @[RegisterRouter.scala:87:24] wire out_romask_1145 = |_out_romask_T_1145; // @[RegisterRouter.scala:87:24] wire out_womask_1145 = &_out_womask_T_1145; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1145 = out_rivalid_1_999 & out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11062 = out_f_rivalid_1145; // @[RegisterRouter.scala:87:24] wire out_f_roready_1145 = out_roready_1_999 & out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11063 = out_f_roready_1145; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1145 = out_wivalid_1_999 & out_wimask_1145; // @[RegisterRouter.scala:87:24] wire out_f_woready_1145 = out_woready_1_999 & out_womask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11064 = ~out_rimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11065 = ~out_wimask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11066 = ~out_romask_1145; // @[RegisterRouter.scala:87:24] wire _out_T_11067 = ~out_womask_1145; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_982 = {hi_93, flags_0_go, _out_prepend_T_982}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11068 = out_prepend_982; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11069 = _out_T_11068; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_983 = _out_T_11069; // @[RegisterRouter.scala:87:24] wire out_rimask_1146 = |_out_rimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_wimask_1146 = &_out_wimask_T_1146; // @[RegisterRouter.scala:87:24] wire out_romask_1146 = |_out_romask_T_1146; // @[RegisterRouter.scala:87:24] wire out_womask_1146 = &_out_womask_T_1146; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1146 = out_rivalid_1_1000 & out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11071 = out_f_rivalid_1146; // @[RegisterRouter.scala:87:24] wire out_f_roready_1146 = out_roready_1_1000 & out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11072 = out_f_roready_1146; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1146 = out_wivalid_1_1000 & out_wimask_1146; // @[RegisterRouter.scala:87:24] wire out_f_woready_1146 = out_woready_1_1000 & out_womask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11073 = ~out_rimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11074 = ~out_wimask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11075 = ~out_romask_1146; // @[RegisterRouter.scala:87:24] wire _out_T_11076 = ~out_womask_1146; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_983 = {hi_94, flags_0_go, _out_prepend_T_983}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11077 = out_prepend_983; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11078 = _out_T_11077; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_984 = _out_T_11078; // @[RegisterRouter.scala:87:24] wire out_rimask_1147 = |_out_rimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_wimask_1147 = &_out_wimask_T_1147; // @[RegisterRouter.scala:87:24] wire out_romask_1147 = |_out_romask_T_1147; // @[RegisterRouter.scala:87:24] wire out_womask_1147 = &_out_womask_T_1147; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1147 = out_rivalid_1_1001 & out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11080 = out_f_rivalid_1147; // @[RegisterRouter.scala:87:24] wire out_f_roready_1147 = out_roready_1_1001 & out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11081 = out_f_roready_1147; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1147 = out_wivalid_1_1001 & out_wimask_1147; // @[RegisterRouter.scala:87:24] wire out_f_woready_1147 = out_woready_1_1001 & out_womask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11082 = ~out_rimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11083 = ~out_wimask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11084 = ~out_romask_1147; // @[RegisterRouter.scala:87:24] wire _out_T_11085 = ~out_womask_1147; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_984 = {hi_95, flags_0_go, _out_prepend_T_984}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11086 = out_prepend_984; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11087 = _out_T_11086; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_985 = _out_T_11087; // @[RegisterRouter.scala:87:24] wire out_rimask_1148 = |_out_rimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_wimask_1148 = &_out_wimask_T_1148; // @[RegisterRouter.scala:87:24] wire out_romask_1148 = |_out_romask_T_1148; // @[RegisterRouter.scala:87:24] wire out_womask_1148 = &_out_womask_T_1148; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1148 = out_rivalid_1_1002 & out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11089 = out_f_rivalid_1148; // @[RegisterRouter.scala:87:24] wire out_f_roready_1148 = out_roready_1_1002 & out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11090 = out_f_roready_1148; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1148 = out_wivalid_1_1002 & out_wimask_1148; // @[RegisterRouter.scala:87:24] wire out_f_woready_1148 = out_woready_1_1002 & out_womask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11091 = ~out_rimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11092 = ~out_wimask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11093 = ~out_romask_1148; // @[RegisterRouter.scala:87:24] wire _out_T_11094 = ~out_womask_1148; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_985 = {hi_96, flags_0_go, _out_prepend_T_985}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11095 = out_prepend_985; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11096 = _out_T_11095; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_139 = _out_T_11096; // @[MuxLiteral.scala:49:48] wire out_rimask_1149 = |_out_rimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_wimask_1149 = &_out_wimask_T_1149; // @[RegisterRouter.scala:87:24] wire out_romask_1149 = |_out_romask_T_1149; // @[RegisterRouter.scala:87:24] wire out_womask_1149 = &_out_womask_T_1149; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1149 = out_rivalid_1_1003 & out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11098 = out_f_rivalid_1149; // @[RegisterRouter.scala:87:24] wire out_f_roready_1149 = out_roready_1_1003 & out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11099 = out_f_roready_1149; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1149 = out_wivalid_1_1003 & out_wimask_1149; // @[RegisterRouter.scala:87:24] wire out_f_woready_1149 = out_woready_1_1003 & out_womask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11100 = ~out_rimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11101 = ~out_wimask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11102 = ~out_romask_1149; // @[RegisterRouter.scala:87:24] wire _out_T_11103 = ~out_womask_1149; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11105 = _out_T_11104; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_986 = _out_T_11105; // @[RegisterRouter.scala:87:24] wire out_rimask_1150 = |_out_rimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_wimask_1150 = &_out_wimask_T_1150; // @[RegisterRouter.scala:87:24] wire out_romask_1150 = |_out_romask_T_1150; // @[RegisterRouter.scala:87:24] wire out_womask_1150 = &_out_womask_T_1150; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1150 = out_rivalid_1_1004 & out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11107 = out_f_rivalid_1150; // @[RegisterRouter.scala:87:24] wire out_f_roready_1150 = out_roready_1_1004 & out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11108 = out_f_roready_1150; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1150 = out_wivalid_1_1004 & out_wimask_1150; // @[RegisterRouter.scala:87:24] wire out_f_woready_1150 = out_woready_1_1004 & out_womask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11109 = ~out_rimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11110 = ~out_wimask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11111 = ~out_romask_1150; // @[RegisterRouter.scala:87:24] wire _out_T_11112 = ~out_womask_1150; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_986 = {hi_634, flags_0_go, _out_prepend_T_986}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11113 = out_prepend_986; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11114 = _out_T_11113; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_987 = _out_T_11114; // @[RegisterRouter.scala:87:24] wire out_rimask_1151 = |_out_rimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_wimask_1151 = &_out_wimask_T_1151; // @[RegisterRouter.scala:87:24] wire out_romask_1151 = |_out_romask_T_1151; // @[RegisterRouter.scala:87:24] wire out_womask_1151 = &_out_womask_T_1151; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1151 = out_rivalid_1_1005 & out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11116 = out_f_rivalid_1151; // @[RegisterRouter.scala:87:24] wire out_f_roready_1151 = out_roready_1_1005 & out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11117 = out_f_roready_1151; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1151 = out_wivalid_1_1005 & out_wimask_1151; // @[RegisterRouter.scala:87:24] wire out_f_woready_1151 = out_woready_1_1005 & out_womask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11118 = ~out_rimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11119 = ~out_wimask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11120 = ~out_romask_1151; // @[RegisterRouter.scala:87:24] wire _out_T_11121 = ~out_womask_1151; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_987 = {hi_635, flags_0_go, _out_prepend_T_987}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11122 = out_prepend_987; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11123 = _out_T_11122; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_988 = _out_T_11123; // @[RegisterRouter.scala:87:24] wire out_rimask_1152 = |_out_rimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_wimask_1152 = &_out_wimask_T_1152; // @[RegisterRouter.scala:87:24] wire out_romask_1152 = |_out_romask_T_1152; // @[RegisterRouter.scala:87:24] wire out_womask_1152 = &_out_womask_T_1152; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1152 = out_rivalid_1_1006 & out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11125 = out_f_rivalid_1152; // @[RegisterRouter.scala:87:24] wire out_f_roready_1152 = out_roready_1_1006 & out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11126 = out_f_roready_1152; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1152 = out_wivalid_1_1006 & out_wimask_1152; // @[RegisterRouter.scala:87:24] wire out_f_woready_1152 = out_woready_1_1006 & out_womask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11127 = ~out_rimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11128 = ~out_wimask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11129 = ~out_romask_1152; // @[RegisterRouter.scala:87:24] wire _out_T_11130 = ~out_womask_1152; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_988 = {hi_636, flags_0_go, _out_prepend_T_988}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11131 = out_prepend_988; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11132 = _out_T_11131; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_989 = _out_T_11132; // @[RegisterRouter.scala:87:24] wire out_rimask_1153 = |_out_rimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_wimask_1153 = &_out_wimask_T_1153; // @[RegisterRouter.scala:87:24] wire out_romask_1153 = |_out_romask_T_1153; // @[RegisterRouter.scala:87:24] wire out_womask_1153 = &_out_womask_T_1153; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1153 = out_rivalid_1_1007 & out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11134 = out_f_rivalid_1153; // @[RegisterRouter.scala:87:24] wire out_f_roready_1153 = out_roready_1_1007 & out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11135 = out_f_roready_1153; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1153 = out_wivalid_1_1007 & out_wimask_1153; // @[RegisterRouter.scala:87:24] wire out_f_woready_1153 = out_woready_1_1007 & out_womask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11136 = ~out_rimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11137 = ~out_wimask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11138 = ~out_romask_1153; // @[RegisterRouter.scala:87:24] wire _out_T_11139 = ~out_womask_1153; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_989 = {hi_637, flags_0_go, _out_prepend_T_989}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11140 = out_prepend_989; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11141 = _out_T_11140; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_990 = _out_T_11141; // @[RegisterRouter.scala:87:24] wire out_rimask_1154 = |_out_rimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_wimask_1154 = &_out_wimask_T_1154; // @[RegisterRouter.scala:87:24] wire out_romask_1154 = |_out_romask_T_1154; // @[RegisterRouter.scala:87:24] wire out_womask_1154 = &_out_womask_T_1154; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1154 = out_rivalid_1_1008 & out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11143 = out_f_rivalid_1154; // @[RegisterRouter.scala:87:24] wire out_f_roready_1154 = out_roready_1_1008 & out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11144 = out_f_roready_1154; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1154 = out_wivalid_1_1008 & out_wimask_1154; // @[RegisterRouter.scala:87:24] wire out_f_woready_1154 = out_woready_1_1008 & out_womask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11145 = ~out_rimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11146 = ~out_wimask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11147 = ~out_romask_1154; // @[RegisterRouter.scala:87:24] wire _out_T_11148 = ~out_womask_1154; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_990 = {hi_638, flags_0_go, _out_prepend_T_990}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11149 = out_prepend_990; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11150 = _out_T_11149; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_991 = _out_T_11150; // @[RegisterRouter.scala:87:24] wire out_rimask_1155 = |_out_rimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_wimask_1155 = &_out_wimask_T_1155; // @[RegisterRouter.scala:87:24] wire out_romask_1155 = |_out_romask_T_1155; // @[RegisterRouter.scala:87:24] wire out_womask_1155 = &_out_womask_T_1155; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1155 = out_rivalid_1_1009 & out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11152 = out_f_rivalid_1155; // @[RegisterRouter.scala:87:24] wire out_f_roready_1155 = out_roready_1_1009 & out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11153 = out_f_roready_1155; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1155 = out_wivalid_1_1009 & out_wimask_1155; // @[RegisterRouter.scala:87:24] wire out_f_woready_1155 = out_woready_1_1009 & out_womask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11154 = ~out_rimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11155 = ~out_wimask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11156 = ~out_romask_1155; // @[RegisterRouter.scala:87:24] wire _out_T_11157 = ~out_womask_1155; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_991 = {hi_639, flags_0_go, _out_prepend_T_991}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11158 = out_prepend_991; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11159 = _out_T_11158; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_992 = _out_T_11159; // @[RegisterRouter.scala:87:24] wire out_rimask_1156 = |_out_rimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_wimask_1156 = &_out_wimask_T_1156; // @[RegisterRouter.scala:87:24] wire out_romask_1156 = |_out_romask_T_1156; // @[RegisterRouter.scala:87:24] wire out_womask_1156 = &_out_womask_T_1156; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1156 = out_rivalid_1_1010 & out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11161 = out_f_rivalid_1156; // @[RegisterRouter.scala:87:24] wire out_f_roready_1156 = out_roready_1_1010 & out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11162 = out_f_roready_1156; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1156 = out_wivalid_1_1010 & out_wimask_1156; // @[RegisterRouter.scala:87:24] wire out_f_woready_1156 = out_woready_1_1010 & out_womask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11163 = ~out_rimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11164 = ~out_wimask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11165 = ~out_romask_1156; // @[RegisterRouter.scala:87:24] wire _out_T_11166 = ~out_womask_1156; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_992 = {hi_640, flags_0_go, _out_prepend_T_992}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11167 = out_prepend_992; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11168 = _out_T_11167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_207 = _out_T_11168; // @[MuxLiteral.scala:49:48] wire out_rimask_1157 = |_out_rimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_wimask_1157 = &_out_wimask_T_1157; // @[RegisterRouter.scala:87:24] wire out_romask_1157 = |_out_romask_T_1157; // @[RegisterRouter.scala:87:24] wire out_womask_1157 = &_out_womask_T_1157; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1157 = out_rivalid_1_1011 & out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11170 = out_f_rivalid_1157; // @[RegisterRouter.scala:87:24] wire out_f_roready_1157 = out_roready_1_1011 & out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11171 = out_f_roready_1157; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1157 = out_wivalid_1_1011 & out_wimask_1157; // @[RegisterRouter.scala:87:24] wire out_f_woready_1157 = out_woready_1_1011 & out_womask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11172 = ~out_rimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11173 = ~out_wimask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11174 = ~out_romask_1157; // @[RegisterRouter.scala:87:24] wire _out_T_11175 = ~out_womask_1157; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11177 = _out_T_11176; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_993 = _out_T_11177; // @[RegisterRouter.scala:87:24] wire out_rimask_1158 = |_out_rimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_wimask_1158 = &_out_wimask_T_1158; // @[RegisterRouter.scala:87:24] wire out_romask_1158 = |_out_romask_T_1158; // @[RegisterRouter.scala:87:24] wire out_womask_1158 = &_out_womask_T_1158; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1158 = out_rivalid_1_1012 & out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11179 = out_f_rivalid_1158; // @[RegisterRouter.scala:87:24] wire out_f_roready_1158 = out_roready_1_1012 & out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11180 = out_f_roready_1158; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1158 = out_wivalid_1_1012 & out_wimask_1158; // @[RegisterRouter.scala:87:24] wire out_f_woready_1158 = out_woready_1_1012 & out_womask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11181 = ~out_rimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11182 = ~out_wimask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11183 = ~out_romask_1158; // @[RegisterRouter.scala:87:24] wire _out_T_11184 = ~out_womask_1158; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_993 = {hi_690, flags_0_go, _out_prepend_T_993}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11185 = out_prepend_993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11186 = _out_T_11185; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_994 = _out_T_11186; // @[RegisterRouter.scala:87:24] wire out_rimask_1159 = |_out_rimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_wimask_1159 = &_out_wimask_T_1159; // @[RegisterRouter.scala:87:24] wire out_romask_1159 = |_out_romask_T_1159; // @[RegisterRouter.scala:87:24] wire out_womask_1159 = &_out_womask_T_1159; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1159 = out_rivalid_1_1013 & out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11188 = out_f_rivalid_1159; // @[RegisterRouter.scala:87:24] wire out_f_roready_1159 = out_roready_1_1013 & out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11189 = out_f_roready_1159; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1159 = out_wivalid_1_1013 & out_wimask_1159; // @[RegisterRouter.scala:87:24] wire out_f_woready_1159 = out_woready_1_1013 & out_womask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11190 = ~out_rimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11191 = ~out_wimask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11192 = ~out_romask_1159; // @[RegisterRouter.scala:87:24] wire _out_T_11193 = ~out_womask_1159; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_994 = {hi_691, flags_0_go, _out_prepend_T_994}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11194 = out_prepend_994; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11195 = _out_T_11194; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_995 = _out_T_11195; // @[RegisterRouter.scala:87:24] wire out_rimask_1160 = |_out_rimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_wimask_1160 = &_out_wimask_T_1160; // @[RegisterRouter.scala:87:24] wire out_romask_1160 = |_out_romask_T_1160; // @[RegisterRouter.scala:87:24] wire out_womask_1160 = &_out_womask_T_1160; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1160 = out_rivalid_1_1014 & out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11197 = out_f_rivalid_1160; // @[RegisterRouter.scala:87:24] wire out_f_roready_1160 = out_roready_1_1014 & out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11198 = out_f_roready_1160; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1160 = out_wivalid_1_1014 & out_wimask_1160; // @[RegisterRouter.scala:87:24] wire out_f_woready_1160 = out_woready_1_1014 & out_womask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11199 = ~out_rimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11200 = ~out_wimask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11201 = ~out_romask_1160; // @[RegisterRouter.scala:87:24] wire _out_T_11202 = ~out_womask_1160; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_995 = {hi_692, flags_0_go, _out_prepend_T_995}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11203 = out_prepend_995; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11204 = _out_T_11203; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_996 = _out_T_11204; // @[RegisterRouter.scala:87:24] wire out_rimask_1161 = |_out_rimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_wimask_1161 = &_out_wimask_T_1161; // @[RegisterRouter.scala:87:24] wire out_romask_1161 = |_out_romask_T_1161; // @[RegisterRouter.scala:87:24] wire out_womask_1161 = &_out_womask_T_1161; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1161 = out_rivalid_1_1015 & out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11206 = out_f_rivalid_1161; // @[RegisterRouter.scala:87:24] wire out_f_roready_1161 = out_roready_1_1015 & out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11207 = out_f_roready_1161; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1161 = out_wivalid_1_1015 & out_wimask_1161; // @[RegisterRouter.scala:87:24] wire out_f_woready_1161 = out_woready_1_1015 & out_womask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11208 = ~out_rimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11209 = ~out_wimask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11210 = ~out_romask_1161; // @[RegisterRouter.scala:87:24] wire _out_T_11211 = ~out_womask_1161; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_996 = {hi_693, flags_0_go, _out_prepend_T_996}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11212 = out_prepend_996; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11213 = _out_T_11212; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_997 = _out_T_11213; // @[RegisterRouter.scala:87:24] wire out_rimask_1162 = |_out_rimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_wimask_1162 = &_out_wimask_T_1162; // @[RegisterRouter.scala:87:24] wire out_romask_1162 = |_out_romask_T_1162; // @[RegisterRouter.scala:87:24] wire out_womask_1162 = &_out_womask_T_1162; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1162 = out_rivalid_1_1016 & out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11215 = out_f_rivalid_1162; // @[RegisterRouter.scala:87:24] wire out_f_roready_1162 = out_roready_1_1016 & out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11216 = out_f_roready_1162; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1162 = out_wivalid_1_1016 & out_wimask_1162; // @[RegisterRouter.scala:87:24] wire out_f_woready_1162 = out_woready_1_1016 & out_womask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11217 = ~out_rimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11218 = ~out_wimask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11219 = ~out_romask_1162; // @[RegisterRouter.scala:87:24] wire _out_T_11220 = ~out_womask_1162; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_997 = {hi_694, flags_0_go, _out_prepend_T_997}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11221 = out_prepend_997; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11222 = _out_T_11221; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_998 = _out_T_11222; // @[RegisterRouter.scala:87:24] wire out_rimask_1163 = |_out_rimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_wimask_1163 = &_out_wimask_T_1163; // @[RegisterRouter.scala:87:24] wire out_romask_1163 = |_out_romask_T_1163; // @[RegisterRouter.scala:87:24] wire out_womask_1163 = &_out_womask_T_1163; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1163 = out_rivalid_1_1017 & out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11224 = out_f_rivalid_1163; // @[RegisterRouter.scala:87:24] wire out_f_roready_1163 = out_roready_1_1017 & out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11225 = out_f_roready_1163; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1163 = out_wivalid_1_1017 & out_wimask_1163; // @[RegisterRouter.scala:87:24] wire out_f_woready_1163 = out_woready_1_1017 & out_womask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11226 = ~out_rimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11227 = ~out_wimask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11228 = ~out_romask_1163; // @[RegisterRouter.scala:87:24] wire _out_T_11229 = ~out_womask_1163; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_998 = {hi_695, flags_0_go, _out_prepend_T_998}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11230 = out_prepend_998; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11231 = _out_T_11230; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_999 = _out_T_11231; // @[RegisterRouter.scala:87:24] wire out_rimask_1164 = |_out_rimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_wimask_1164 = &_out_wimask_T_1164; // @[RegisterRouter.scala:87:24] wire out_romask_1164 = |_out_romask_T_1164; // @[RegisterRouter.scala:87:24] wire out_womask_1164 = &_out_womask_T_1164; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1164 = out_rivalid_1_1018 & out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11233 = out_f_rivalid_1164; // @[RegisterRouter.scala:87:24] wire out_f_roready_1164 = out_roready_1_1018 & out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11234 = out_f_roready_1164; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1164 = out_wivalid_1_1018 & out_wimask_1164; // @[RegisterRouter.scala:87:24] wire out_f_woready_1164 = out_woready_1_1018 & out_womask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11235 = ~out_rimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11236 = ~out_wimask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11237 = ~out_romask_1164; // @[RegisterRouter.scala:87:24] wire _out_T_11238 = ~out_womask_1164; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_999 = {hi_696, flags_0_go, _out_prepend_T_999}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11239 = out_prepend_999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11240 = _out_T_11239; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_214 = _out_T_11240; // @[MuxLiteral.scala:49:48] wire out_rimask_1165 = |_out_rimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_wimask_1165 = &_out_wimask_T_1165; // @[RegisterRouter.scala:87:24] wire out_romask_1165 = |_out_romask_T_1165; // @[RegisterRouter.scala:87:24] wire out_womask_1165 = &_out_womask_T_1165; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1165 = out_rivalid_1_1019 & out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11242 = out_f_rivalid_1165; // @[RegisterRouter.scala:87:24] wire out_f_roready_1165 = out_roready_1_1019 & out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11243 = out_f_roready_1165; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1165 = out_wivalid_1_1019 & out_wimask_1165; // @[RegisterRouter.scala:87:24] wire out_f_woready_1165 = out_woready_1_1019 & out_womask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11244 = ~out_rimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11245 = ~out_wimask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11246 = ~out_romask_1165; // @[RegisterRouter.scala:87:24] wire _out_T_11247 = ~out_womask_1165; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11249 = _out_T_11248; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1000 = _out_T_11249; // @[RegisterRouter.scala:87:24] wire out_rimask_1166 = |_out_rimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_wimask_1166 = &_out_wimask_T_1166; // @[RegisterRouter.scala:87:24] wire out_romask_1166 = |_out_romask_T_1166; // @[RegisterRouter.scala:87:24] wire out_womask_1166 = &_out_womask_T_1166; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1166 = out_rivalid_1_1020 & out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11251 = out_f_rivalid_1166; // @[RegisterRouter.scala:87:24] wire out_f_roready_1166 = out_roready_1_1020 & out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11252 = out_f_roready_1166; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1166 = out_wivalid_1_1020 & out_wimask_1166; // @[RegisterRouter.scala:87:24] wire out_f_woready_1166 = out_woready_1_1020 & out_womask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11253 = ~out_rimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11254 = ~out_wimask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11255 = ~out_romask_1166; // @[RegisterRouter.scala:87:24] wire _out_T_11256 = ~out_womask_1166; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1000 = {hi_858, flags_0_go, _out_prepend_T_1000}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11257 = out_prepend_1000; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11258 = _out_T_11257; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1001 = _out_T_11258; // @[RegisterRouter.scala:87:24] wire out_rimask_1167 = |_out_rimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_wimask_1167 = &_out_wimask_T_1167; // @[RegisterRouter.scala:87:24] wire out_romask_1167 = |_out_romask_T_1167; // @[RegisterRouter.scala:87:24] wire out_womask_1167 = &_out_womask_T_1167; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1167 = out_rivalid_1_1021 & out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11260 = out_f_rivalid_1167; // @[RegisterRouter.scala:87:24] wire out_f_roready_1167 = out_roready_1_1021 & out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11261 = out_f_roready_1167; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1167 = out_wivalid_1_1021 & out_wimask_1167; // @[RegisterRouter.scala:87:24] wire out_f_woready_1167 = out_woready_1_1021 & out_womask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11262 = ~out_rimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11263 = ~out_wimask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11264 = ~out_romask_1167; // @[RegisterRouter.scala:87:24] wire _out_T_11265 = ~out_womask_1167; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1001 = {hi_859, flags_0_go, _out_prepend_T_1001}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11266 = out_prepend_1001; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11267 = _out_T_11266; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1002 = _out_T_11267; // @[RegisterRouter.scala:87:24] wire out_rimask_1168 = |_out_rimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_wimask_1168 = &_out_wimask_T_1168; // @[RegisterRouter.scala:87:24] wire out_romask_1168 = |_out_romask_T_1168; // @[RegisterRouter.scala:87:24] wire out_womask_1168 = &_out_womask_T_1168; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1168 = out_rivalid_1_1022 & out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11269 = out_f_rivalid_1168; // @[RegisterRouter.scala:87:24] wire out_f_roready_1168 = out_roready_1_1022 & out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11270 = out_f_roready_1168; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1168 = out_wivalid_1_1022 & out_wimask_1168; // @[RegisterRouter.scala:87:24] wire out_f_woready_1168 = out_woready_1_1022 & out_womask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11271 = ~out_rimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11272 = ~out_wimask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11273 = ~out_romask_1168; // @[RegisterRouter.scala:87:24] wire _out_T_11274 = ~out_womask_1168; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1002 = {hi_860, flags_0_go, _out_prepend_T_1002}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11275 = out_prepend_1002; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11276 = _out_T_11275; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1003 = _out_T_11276; // @[RegisterRouter.scala:87:24] wire out_rimask_1169 = |_out_rimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_wimask_1169 = &_out_wimask_T_1169; // @[RegisterRouter.scala:87:24] wire out_romask_1169 = |_out_romask_T_1169; // @[RegisterRouter.scala:87:24] wire out_womask_1169 = &_out_womask_T_1169; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1169 = out_rivalid_1_1023 & out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11278 = out_f_rivalid_1169; // @[RegisterRouter.scala:87:24] wire out_f_roready_1169 = out_roready_1_1023 & out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11279 = out_f_roready_1169; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1169 = out_wivalid_1_1023 & out_wimask_1169; // @[RegisterRouter.scala:87:24] wire out_f_woready_1169 = out_woready_1_1023 & out_womask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11280 = ~out_rimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11281 = ~out_wimask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11282 = ~out_romask_1169; // @[RegisterRouter.scala:87:24] wire _out_T_11283 = ~out_womask_1169; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1003 = {hi_861, flags_0_go, _out_prepend_T_1003}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11284 = out_prepend_1003; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11285 = _out_T_11284; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1004 = _out_T_11285; // @[RegisterRouter.scala:87:24] wire out_rimask_1170 = |_out_rimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_wimask_1170 = &_out_wimask_T_1170; // @[RegisterRouter.scala:87:24] wire out_romask_1170 = |_out_romask_T_1170; // @[RegisterRouter.scala:87:24] wire out_womask_1170 = &_out_womask_T_1170; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1170 = out_rivalid_1_1024 & out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11287 = out_f_rivalid_1170; // @[RegisterRouter.scala:87:24] wire out_f_roready_1170 = out_roready_1_1024 & out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11288 = out_f_roready_1170; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1170 = out_wivalid_1_1024 & out_wimask_1170; // @[RegisterRouter.scala:87:24] wire out_f_woready_1170 = out_woready_1_1024 & out_womask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11289 = ~out_rimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11290 = ~out_wimask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11291 = ~out_romask_1170; // @[RegisterRouter.scala:87:24] wire _out_T_11292 = ~out_womask_1170; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1004 = {hi_862, flags_0_go, _out_prepend_T_1004}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11293 = out_prepend_1004; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11294 = _out_T_11293; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1005 = _out_T_11294; // @[RegisterRouter.scala:87:24] wire out_rimask_1171 = |_out_rimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_wimask_1171 = &_out_wimask_T_1171; // @[RegisterRouter.scala:87:24] wire out_romask_1171 = |_out_romask_T_1171; // @[RegisterRouter.scala:87:24] wire out_womask_1171 = &_out_womask_T_1171; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1171 = out_rivalid_1_1025 & out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11296 = out_f_rivalid_1171; // @[RegisterRouter.scala:87:24] wire out_f_roready_1171 = out_roready_1_1025 & out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11297 = out_f_roready_1171; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1171 = out_wivalid_1_1025 & out_wimask_1171; // @[RegisterRouter.scala:87:24] wire out_f_woready_1171 = out_woready_1_1025 & out_womask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11298 = ~out_rimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11299 = ~out_wimask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11300 = ~out_romask_1171; // @[RegisterRouter.scala:87:24] wire _out_T_11301 = ~out_womask_1171; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1005 = {hi_863, flags_0_go, _out_prepend_T_1005}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11302 = out_prepend_1005; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11303 = _out_T_11302; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1006 = _out_T_11303; // @[RegisterRouter.scala:87:24] wire out_rimask_1172 = |_out_rimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_wimask_1172 = &_out_wimask_T_1172; // @[RegisterRouter.scala:87:24] wire out_romask_1172 = |_out_romask_T_1172; // @[RegisterRouter.scala:87:24] wire out_womask_1172 = &_out_womask_T_1172; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1172 = out_rivalid_1_1026 & out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11305 = out_f_rivalid_1172; // @[RegisterRouter.scala:87:24] wire out_f_roready_1172 = out_roready_1_1026 & out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11306 = out_f_roready_1172; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1172 = out_wivalid_1_1026 & out_wimask_1172; // @[RegisterRouter.scala:87:24] wire out_f_woready_1172 = out_woready_1_1026 & out_womask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11307 = ~out_rimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11308 = ~out_wimask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11309 = ~out_romask_1172; // @[RegisterRouter.scala:87:24] wire _out_T_11310 = ~out_womask_1172; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1006 = {hi_864, flags_0_go, _out_prepend_T_1006}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11311 = out_prepend_1006; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11312 = _out_T_11311; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_235 = _out_T_11312; // @[MuxLiteral.scala:49:48] wire out_rimask_1173 = |_out_rimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_wimask_1173 = &_out_wimask_T_1173; // @[RegisterRouter.scala:87:24] wire out_romask_1173 = |_out_romask_T_1173; // @[RegisterRouter.scala:87:24] wire out_womask_1173 = &_out_womask_T_1173; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1173 = out_rivalid_1_1027 & out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11314 = out_f_rivalid_1173; // @[RegisterRouter.scala:87:24] wire out_f_roready_1173 = out_roready_1_1027 & out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11315 = out_f_roready_1173; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1173 = out_wivalid_1_1027 & out_wimask_1173; // @[RegisterRouter.scala:87:24] wire out_f_woready_1173 = out_woready_1_1027 & out_womask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11316 = ~out_rimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11317 = ~out_wimask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11318 = ~out_romask_1173; // @[RegisterRouter.scala:87:24] wire _out_T_11319 = ~out_womask_1173; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11321 = _out_T_11320; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1007 = _out_T_11321; // @[RegisterRouter.scala:87:24] wire out_rimask_1174 = |_out_rimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_wimask_1174 = &_out_wimask_T_1174; // @[RegisterRouter.scala:87:24] wire out_romask_1174 = |_out_romask_T_1174; // @[RegisterRouter.scala:87:24] wire out_womask_1174 = &_out_womask_T_1174; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1174 = out_rivalid_1_1028 & out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11323 = out_f_rivalid_1174; // @[RegisterRouter.scala:87:24] wire out_f_roready_1174 = out_roready_1_1028 & out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11324 = out_f_roready_1174; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1174 = out_wivalid_1_1028 & out_wimask_1174; // @[RegisterRouter.scala:87:24] wire out_f_woready_1174 = out_woready_1_1028 & out_womask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11325 = ~out_rimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11326 = ~out_wimask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11327 = ~out_romask_1174; // @[RegisterRouter.scala:87:24] wire _out_T_11328 = ~out_womask_1174; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1007 = {hi_946, flags_0_go, _out_prepend_T_1007}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11329 = out_prepend_1007; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11330 = _out_T_11329; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1008 = _out_T_11330; // @[RegisterRouter.scala:87:24] wire out_rimask_1175 = |_out_rimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_wimask_1175 = &_out_wimask_T_1175; // @[RegisterRouter.scala:87:24] wire out_romask_1175 = |_out_romask_T_1175; // @[RegisterRouter.scala:87:24] wire out_womask_1175 = &_out_womask_T_1175; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1175 = out_rivalid_1_1029 & out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11332 = out_f_rivalid_1175; // @[RegisterRouter.scala:87:24] wire out_f_roready_1175 = out_roready_1_1029 & out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11333 = out_f_roready_1175; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1175 = out_wivalid_1_1029 & out_wimask_1175; // @[RegisterRouter.scala:87:24] wire out_f_woready_1175 = out_woready_1_1029 & out_womask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11334 = ~out_rimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11335 = ~out_wimask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11336 = ~out_romask_1175; // @[RegisterRouter.scala:87:24] wire _out_T_11337 = ~out_womask_1175; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1008 = {hi_947, flags_0_go, _out_prepend_T_1008}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11338 = out_prepend_1008; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11339 = _out_T_11338; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1009 = _out_T_11339; // @[RegisterRouter.scala:87:24] wire out_rimask_1176 = |_out_rimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_wimask_1176 = &_out_wimask_T_1176; // @[RegisterRouter.scala:87:24] wire out_romask_1176 = |_out_romask_T_1176; // @[RegisterRouter.scala:87:24] wire out_womask_1176 = &_out_womask_T_1176; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1176 = out_rivalid_1_1030 & out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11341 = out_f_rivalid_1176; // @[RegisterRouter.scala:87:24] wire out_f_roready_1176 = out_roready_1_1030 & out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11342 = out_f_roready_1176; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1176 = out_wivalid_1_1030 & out_wimask_1176; // @[RegisterRouter.scala:87:24] wire out_f_woready_1176 = out_woready_1_1030 & out_womask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11343 = ~out_rimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11344 = ~out_wimask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11345 = ~out_romask_1176; // @[RegisterRouter.scala:87:24] wire _out_T_11346 = ~out_womask_1176; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1009 = {hi_948, flags_0_go, _out_prepend_T_1009}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11347 = out_prepend_1009; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11348 = _out_T_11347; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1010 = _out_T_11348; // @[RegisterRouter.scala:87:24] wire out_rimask_1177 = |_out_rimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_wimask_1177 = &_out_wimask_T_1177; // @[RegisterRouter.scala:87:24] wire out_romask_1177 = |_out_romask_T_1177; // @[RegisterRouter.scala:87:24] wire out_womask_1177 = &_out_womask_T_1177; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1177 = out_rivalid_1_1031 & out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11350 = out_f_rivalid_1177; // @[RegisterRouter.scala:87:24] wire out_f_roready_1177 = out_roready_1_1031 & out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11351 = out_f_roready_1177; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1177 = out_wivalid_1_1031 & out_wimask_1177; // @[RegisterRouter.scala:87:24] wire out_f_woready_1177 = out_woready_1_1031 & out_womask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11352 = ~out_rimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11353 = ~out_wimask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11354 = ~out_romask_1177; // @[RegisterRouter.scala:87:24] wire _out_T_11355 = ~out_womask_1177; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1010 = {hi_949, flags_0_go, _out_prepend_T_1010}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11356 = out_prepend_1010; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11357 = _out_T_11356; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1011 = _out_T_11357; // @[RegisterRouter.scala:87:24] wire out_rimask_1178 = |_out_rimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_wimask_1178 = &_out_wimask_T_1178; // @[RegisterRouter.scala:87:24] wire out_romask_1178 = |_out_romask_T_1178; // @[RegisterRouter.scala:87:24] wire out_womask_1178 = &_out_womask_T_1178; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1178 = out_rivalid_1_1032 & out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11359 = out_f_rivalid_1178; // @[RegisterRouter.scala:87:24] wire out_f_roready_1178 = out_roready_1_1032 & out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11360 = out_f_roready_1178; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1178 = out_wivalid_1_1032 & out_wimask_1178; // @[RegisterRouter.scala:87:24] wire out_f_woready_1178 = out_woready_1_1032 & out_womask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11361 = ~out_rimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11362 = ~out_wimask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11363 = ~out_romask_1178; // @[RegisterRouter.scala:87:24] wire _out_T_11364 = ~out_womask_1178; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1011 = {hi_950, flags_0_go, _out_prepend_T_1011}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11365 = out_prepend_1011; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11366 = _out_T_11365; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1012 = _out_T_11366; // @[RegisterRouter.scala:87:24] wire out_rimask_1179 = |_out_rimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_wimask_1179 = &_out_wimask_T_1179; // @[RegisterRouter.scala:87:24] wire out_romask_1179 = |_out_romask_T_1179; // @[RegisterRouter.scala:87:24] wire out_womask_1179 = &_out_womask_T_1179; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1179 = out_rivalid_1_1033 & out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11368 = out_f_rivalid_1179; // @[RegisterRouter.scala:87:24] wire out_f_roready_1179 = out_roready_1_1033 & out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11369 = out_f_roready_1179; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1179 = out_wivalid_1_1033 & out_wimask_1179; // @[RegisterRouter.scala:87:24] wire out_f_woready_1179 = out_woready_1_1033 & out_womask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11370 = ~out_rimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11371 = ~out_wimask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11372 = ~out_romask_1179; // @[RegisterRouter.scala:87:24] wire _out_T_11373 = ~out_womask_1179; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1012 = {hi_951, flags_0_go, _out_prepend_T_1012}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11374 = out_prepend_1012; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11375 = _out_T_11374; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1013 = _out_T_11375; // @[RegisterRouter.scala:87:24] wire out_rimask_1180 = |_out_rimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_wimask_1180 = &_out_wimask_T_1180; // @[RegisterRouter.scala:87:24] wire out_romask_1180 = |_out_romask_T_1180; // @[RegisterRouter.scala:87:24] wire out_womask_1180 = &_out_womask_T_1180; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1180 = out_rivalid_1_1034 & out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11377 = out_f_rivalid_1180; // @[RegisterRouter.scala:87:24] wire out_f_roready_1180 = out_roready_1_1034 & out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11378 = out_f_roready_1180; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1180 = out_wivalid_1_1034 & out_wimask_1180; // @[RegisterRouter.scala:87:24] wire out_f_woready_1180 = out_woready_1_1034 & out_womask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11379 = ~out_rimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11380 = ~out_wimask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11381 = ~out_romask_1180; // @[RegisterRouter.scala:87:24] wire _out_T_11382 = ~out_womask_1180; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1013 = {hi_952, flags_0_go, _out_prepend_T_1013}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11383 = out_prepend_1013; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11384 = _out_T_11383; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_246 = _out_T_11384; // @[MuxLiteral.scala:49:48] wire out_rimask_1181 = |_out_rimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_wimask_1181 = &_out_wimask_T_1181; // @[RegisterRouter.scala:87:24] wire out_romask_1181 = |_out_romask_T_1181; // @[RegisterRouter.scala:87:24] wire out_womask_1181 = &_out_womask_T_1181; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1181 = out_rivalid_1_1035 & out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11386 = out_f_rivalid_1181; // @[RegisterRouter.scala:87:24] wire out_f_roready_1181 = out_roready_1_1035 & out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11387 = out_f_roready_1181; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1181 = out_wivalid_1_1035 & out_wimask_1181; // @[RegisterRouter.scala:87:24] wire out_f_woready_1181 = out_woready_1_1035 & out_womask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11388 = ~out_rimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11389 = ~out_wimask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11390 = ~out_romask_1181; // @[RegisterRouter.scala:87:24] wire _out_T_11391 = ~out_womask_1181; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11393 = _out_T_11392; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1014 = _out_T_11393; // @[RegisterRouter.scala:87:24] wire out_rimask_1182 = |_out_rimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_wimask_1182 = &_out_wimask_T_1182; // @[RegisterRouter.scala:87:24] wire out_romask_1182 = |_out_romask_T_1182; // @[RegisterRouter.scala:87:24] wire out_womask_1182 = &_out_womask_T_1182; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1182 = out_rivalid_1_1036 & out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11395 = out_f_rivalid_1182; // @[RegisterRouter.scala:87:24] wire out_f_roready_1182 = out_roready_1_1036 & out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11396 = out_f_roready_1182; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1182 = out_wivalid_1_1036 & out_wimask_1182; // @[RegisterRouter.scala:87:24] wire out_f_woready_1182 = out_woready_1_1036 & out_womask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11397 = ~out_rimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11398 = ~out_wimask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11399 = ~out_romask_1182; // @[RegisterRouter.scala:87:24] wire _out_T_11400 = ~out_womask_1182; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1014 = {hi_186, flags_0_go, _out_prepend_T_1014}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11401 = out_prepend_1014; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11402 = _out_T_11401; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1015 = _out_T_11402; // @[RegisterRouter.scala:87:24] wire out_rimask_1183 = |_out_rimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_wimask_1183 = &_out_wimask_T_1183; // @[RegisterRouter.scala:87:24] wire out_romask_1183 = |_out_romask_T_1183; // @[RegisterRouter.scala:87:24] wire out_womask_1183 = &_out_womask_T_1183; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1183 = out_rivalid_1_1037 & out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11404 = out_f_rivalid_1183; // @[RegisterRouter.scala:87:24] wire out_f_roready_1183 = out_roready_1_1037 & out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11405 = out_f_roready_1183; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1183 = out_wivalid_1_1037 & out_wimask_1183; // @[RegisterRouter.scala:87:24] wire out_f_woready_1183 = out_woready_1_1037 & out_womask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11406 = ~out_rimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11407 = ~out_wimask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11408 = ~out_romask_1183; // @[RegisterRouter.scala:87:24] wire _out_T_11409 = ~out_womask_1183; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1015 = {hi_187, flags_0_go, _out_prepend_T_1015}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11410 = out_prepend_1015; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11411 = _out_T_11410; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1016 = _out_T_11411; // @[RegisterRouter.scala:87:24] wire out_rimask_1184 = |_out_rimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_wimask_1184 = &_out_wimask_T_1184; // @[RegisterRouter.scala:87:24] wire out_romask_1184 = |_out_romask_T_1184; // @[RegisterRouter.scala:87:24] wire out_womask_1184 = &_out_womask_T_1184; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1184 = out_rivalid_1_1038 & out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11413 = out_f_rivalid_1184; // @[RegisterRouter.scala:87:24] wire out_f_roready_1184 = out_roready_1_1038 & out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11414 = out_f_roready_1184; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1184 = out_wivalid_1_1038 & out_wimask_1184; // @[RegisterRouter.scala:87:24] wire out_f_woready_1184 = out_woready_1_1038 & out_womask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11415 = ~out_rimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11416 = ~out_wimask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11417 = ~out_romask_1184; // @[RegisterRouter.scala:87:24] wire _out_T_11418 = ~out_womask_1184; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1016 = {hi_188, flags_0_go, _out_prepend_T_1016}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11419 = out_prepend_1016; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11420 = _out_T_11419; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1017 = _out_T_11420; // @[RegisterRouter.scala:87:24] wire out_rimask_1185 = |_out_rimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_wimask_1185 = &_out_wimask_T_1185; // @[RegisterRouter.scala:87:24] wire out_romask_1185 = |_out_romask_T_1185; // @[RegisterRouter.scala:87:24] wire out_womask_1185 = &_out_womask_T_1185; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1185 = out_rivalid_1_1039 & out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11422 = out_f_rivalid_1185; // @[RegisterRouter.scala:87:24] wire out_f_roready_1185 = out_roready_1_1039 & out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11423 = out_f_roready_1185; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1185 = out_wivalid_1_1039 & out_wimask_1185; // @[RegisterRouter.scala:87:24] wire out_f_woready_1185 = out_woready_1_1039 & out_womask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11424 = ~out_rimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11425 = ~out_wimask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11426 = ~out_romask_1185; // @[RegisterRouter.scala:87:24] wire _out_T_11427 = ~out_womask_1185; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1017 = {hi_189, flags_0_go, _out_prepend_T_1017}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11428 = out_prepend_1017; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11429 = _out_T_11428; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1018 = _out_T_11429; // @[RegisterRouter.scala:87:24] wire out_rimask_1186 = |_out_rimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_wimask_1186 = &_out_wimask_T_1186; // @[RegisterRouter.scala:87:24] wire out_romask_1186 = |_out_romask_T_1186; // @[RegisterRouter.scala:87:24] wire out_womask_1186 = &_out_womask_T_1186; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1186 = out_rivalid_1_1040 & out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11431 = out_f_rivalid_1186; // @[RegisterRouter.scala:87:24] wire out_f_roready_1186 = out_roready_1_1040 & out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11432 = out_f_roready_1186; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1186 = out_wivalid_1_1040 & out_wimask_1186; // @[RegisterRouter.scala:87:24] wire out_f_woready_1186 = out_woready_1_1040 & out_womask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11433 = ~out_rimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11434 = ~out_wimask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11435 = ~out_romask_1186; // @[RegisterRouter.scala:87:24] wire _out_T_11436 = ~out_womask_1186; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1018 = {hi_190, flags_0_go, _out_prepend_T_1018}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11437 = out_prepend_1018; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11438 = _out_T_11437; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1019 = _out_T_11438; // @[RegisterRouter.scala:87:24] wire out_rimask_1187 = |_out_rimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_wimask_1187 = &_out_wimask_T_1187; // @[RegisterRouter.scala:87:24] wire out_romask_1187 = |_out_romask_T_1187; // @[RegisterRouter.scala:87:24] wire out_womask_1187 = &_out_womask_T_1187; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1187 = out_rivalid_1_1041 & out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11440 = out_f_rivalid_1187; // @[RegisterRouter.scala:87:24] wire out_f_roready_1187 = out_roready_1_1041 & out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11441 = out_f_roready_1187; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1187 = out_wivalid_1_1041 & out_wimask_1187; // @[RegisterRouter.scala:87:24] wire out_f_woready_1187 = out_woready_1_1041 & out_womask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11442 = ~out_rimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11443 = ~out_wimask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11444 = ~out_romask_1187; // @[RegisterRouter.scala:87:24] wire _out_T_11445 = ~out_womask_1187; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1019 = {hi_191, flags_0_go, _out_prepend_T_1019}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11446 = out_prepend_1019; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11447 = _out_T_11446; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1020 = _out_T_11447; // @[RegisterRouter.scala:87:24] wire out_rimask_1188 = |_out_rimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_wimask_1188 = &_out_wimask_T_1188; // @[RegisterRouter.scala:87:24] wire out_romask_1188 = |_out_romask_T_1188; // @[RegisterRouter.scala:87:24] wire out_womask_1188 = &_out_womask_T_1188; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1188 = out_rivalid_1_1042 & out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11449 = out_f_rivalid_1188; // @[RegisterRouter.scala:87:24] wire out_f_roready_1188 = out_roready_1_1042 & out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11450 = out_f_roready_1188; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1188 = out_wivalid_1_1042 & out_wimask_1188; // @[RegisterRouter.scala:87:24] wire out_f_woready_1188 = out_woready_1_1042 & out_womask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11451 = ~out_rimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11452 = ~out_wimask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11453 = ~out_romask_1188; // @[RegisterRouter.scala:87:24] wire _out_T_11454 = ~out_womask_1188; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1020 = {hi_192, flags_0_go, _out_prepend_T_1020}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11455 = out_prepend_1020; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11456 = _out_T_11455; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_151 = _out_T_11456; // @[MuxLiteral.scala:49:48] wire out_rimask_1189 = |_out_rimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_wimask_1189 = &_out_wimask_T_1189; // @[RegisterRouter.scala:87:24] wire out_romask_1189 = |_out_romask_T_1189; // @[RegisterRouter.scala:87:24] wire out_womask_1189 = &_out_womask_T_1189; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1189 = out_rivalid_1_1043 & out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11458 = out_f_rivalid_1189; // @[RegisterRouter.scala:87:24] wire out_f_roready_1189 = out_roready_1_1043 & out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11459 = out_f_roready_1189; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1189 = out_wivalid_1_1043 & out_wimask_1189; // @[RegisterRouter.scala:87:24] wire out_f_woready_1189 = out_woready_1_1043 & out_womask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11460 = ~out_rimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11461 = ~out_wimask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11462 = ~out_romask_1189; // @[RegisterRouter.scala:87:24] wire _out_T_11463 = ~out_womask_1189; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11465 = _out_T_11464; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1021 = _out_T_11465; // @[RegisterRouter.scala:87:24] wire out_rimask_1190 = |_out_rimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_wimask_1190 = &_out_wimask_T_1190; // @[RegisterRouter.scala:87:24] wire out_romask_1190 = |_out_romask_T_1190; // @[RegisterRouter.scala:87:24] wire out_womask_1190 = &_out_womask_T_1190; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1190 = out_rivalid_1_1044 & out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11467 = out_f_rivalid_1190; // @[RegisterRouter.scala:87:24] wire out_f_roready_1190 = out_roready_1_1044 & out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11468 = out_f_roready_1190; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1190 = out_wivalid_1_1044 & out_wimask_1190; // @[RegisterRouter.scala:87:24] wire out_f_woready_1190 = out_woready_1_1044 & out_womask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11469 = ~out_rimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11470 = ~out_wimask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11471 = ~out_romask_1190; // @[RegisterRouter.scala:87:24] wire _out_T_11472 = ~out_womask_1190; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1021 = {hi_146, flags_0_go, _out_prepend_T_1021}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11473 = out_prepend_1021; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11474 = _out_T_11473; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1022 = _out_T_11474; // @[RegisterRouter.scala:87:24] wire out_rimask_1191 = |_out_rimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_wimask_1191 = &_out_wimask_T_1191; // @[RegisterRouter.scala:87:24] wire out_romask_1191 = |_out_romask_T_1191; // @[RegisterRouter.scala:87:24] wire out_womask_1191 = &_out_womask_T_1191; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1191 = out_rivalid_1_1045 & out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11476 = out_f_rivalid_1191; // @[RegisterRouter.scala:87:24] wire out_f_roready_1191 = out_roready_1_1045 & out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11477 = out_f_roready_1191; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1191 = out_wivalid_1_1045 & out_wimask_1191; // @[RegisterRouter.scala:87:24] wire out_f_woready_1191 = out_woready_1_1045 & out_womask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11478 = ~out_rimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11479 = ~out_wimask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11480 = ~out_romask_1191; // @[RegisterRouter.scala:87:24] wire _out_T_11481 = ~out_womask_1191; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1022 = {hi_147, flags_0_go, _out_prepend_T_1022}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11482 = out_prepend_1022; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11483 = _out_T_11482; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1023 = _out_T_11483; // @[RegisterRouter.scala:87:24] wire out_rimask_1192 = |_out_rimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_wimask_1192 = &_out_wimask_T_1192; // @[RegisterRouter.scala:87:24] wire out_romask_1192 = |_out_romask_T_1192; // @[RegisterRouter.scala:87:24] wire out_womask_1192 = &_out_womask_T_1192; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1192 = out_rivalid_1_1046 & out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11485 = out_f_rivalid_1192; // @[RegisterRouter.scala:87:24] wire out_f_roready_1192 = out_roready_1_1046 & out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11486 = out_f_roready_1192; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1192 = out_wivalid_1_1046 & out_wimask_1192; // @[RegisterRouter.scala:87:24] wire out_f_woready_1192 = out_woready_1_1046 & out_womask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11487 = ~out_rimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11488 = ~out_wimask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11489 = ~out_romask_1192; // @[RegisterRouter.scala:87:24] wire _out_T_11490 = ~out_womask_1192; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1023 = {hi_148, flags_0_go, _out_prepend_T_1023}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11491 = out_prepend_1023; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11492 = _out_T_11491; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1024 = _out_T_11492; // @[RegisterRouter.scala:87:24] wire out_rimask_1193 = |_out_rimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_wimask_1193 = &_out_wimask_T_1193; // @[RegisterRouter.scala:87:24] wire out_romask_1193 = |_out_romask_T_1193; // @[RegisterRouter.scala:87:24] wire out_womask_1193 = &_out_womask_T_1193; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1193 = out_rivalid_1_1047 & out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11494 = out_f_rivalid_1193; // @[RegisterRouter.scala:87:24] wire out_f_roready_1193 = out_roready_1_1047 & out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11495 = out_f_roready_1193; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1193 = out_wivalid_1_1047 & out_wimask_1193; // @[RegisterRouter.scala:87:24] wire out_f_woready_1193 = out_woready_1_1047 & out_womask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11496 = ~out_rimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11497 = ~out_wimask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11498 = ~out_romask_1193; // @[RegisterRouter.scala:87:24] wire _out_T_11499 = ~out_womask_1193; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1024 = {hi_149, flags_0_go, _out_prepend_T_1024}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11500 = out_prepend_1024; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11501 = _out_T_11500; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1025 = _out_T_11501; // @[RegisterRouter.scala:87:24] wire out_rimask_1194 = |_out_rimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_wimask_1194 = &_out_wimask_T_1194; // @[RegisterRouter.scala:87:24] wire out_romask_1194 = |_out_romask_T_1194; // @[RegisterRouter.scala:87:24] wire out_womask_1194 = &_out_womask_T_1194; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1194 = out_rivalid_1_1048 & out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11503 = out_f_rivalid_1194; // @[RegisterRouter.scala:87:24] wire out_f_roready_1194 = out_roready_1_1048 & out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11504 = out_f_roready_1194; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1194 = out_wivalid_1_1048 & out_wimask_1194; // @[RegisterRouter.scala:87:24] wire out_f_woready_1194 = out_woready_1_1048 & out_womask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11505 = ~out_rimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11506 = ~out_wimask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11507 = ~out_romask_1194; // @[RegisterRouter.scala:87:24] wire _out_T_11508 = ~out_womask_1194; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1025 = {hi_150, flags_0_go, _out_prepend_T_1025}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11509 = out_prepend_1025; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11510 = _out_T_11509; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1026 = _out_T_11510; // @[RegisterRouter.scala:87:24] wire out_rimask_1195 = |_out_rimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_wimask_1195 = &_out_wimask_T_1195; // @[RegisterRouter.scala:87:24] wire out_romask_1195 = |_out_romask_T_1195; // @[RegisterRouter.scala:87:24] wire out_womask_1195 = &_out_womask_T_1195; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1195 = out_rivalid_1_1049 & out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11512 = out_f_rivalid_1195; // @[RegisterRouter.scala:87:24] wire out_f_roready_1195 = out_roready_1_1049 & out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11513 = out_f_roready_1195; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1195 = out_wivalid_1_1049 & out_wimask_1195; // @[RegisterRouter.scala:87:24] wire out_f_woready_1195 = out_woready_1_1049 & out_womask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11514 = ~out_rimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11515 = ~out_wimask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11516 = ~out_romask_1195; // @[RegisterRouter.scala:87:24] wire _out_T_11517 = ~out_womask_1195; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1026 = {hi_151, flags_0_go, _out_prepend_T_1026}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11518 = out_prepend_1026; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11519 = _out_T_11518; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1027 = _out_T_11519; // @[RegisterRouter.scala:87:24] wire out_rimask_1196 = |_out_rimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_wimask_1196 = &_out_wimask_T_1196; // @[RegisterRouter.scala:87:24] wire out_romask_1196 = |_out_romask_T_1196; // @[RegisterRouter.scala:87:24] wire out_womask_1196 = &_out_womask_T_1196; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1196 = out_rivalid_1_1050 & out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11521 = out_f_rivalid_1196; // @[RegisterRouter.scala:87:24] wire out_f_roready_1196 = out_roready_1_1050 & out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11522 = out_f_roready_1196; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1196 = out_wivalid_1_1050 & out_wimask_1196; // @[RegisterRouter.scala:87:24] wire out_f_woready_1196 = out_woready_1_1050 & out_womask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11523 = ~out_rimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11524 = ~out_wimask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11525 = ~out_romask_1196; // @[RegisterRouter.scala:87:24] wire _out_T_11526 = ~out_womask_1196; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1027 = {hi_152, flags_0_go, _out_prepend_T_1027}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11527 = out_prepend_1027; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11528 = _out_T_11527; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_146 = _out_T_11528; // @[MuxLiteral.scala:49:48] wire out_rimask_1197 = |_out_rimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_wimask_1197 = &_out_wimask_T_1197; // @[RegisterRouter.scala:87:24] wire out_romask_1197 = |_out_romask_T_1197; // @[RegisterRouter.scala:87:24] wire out_womask_1197 = &_out_womask_T_1197; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1197 = out_rivalid_1_1051 & out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11530 = out_f_rivalid_1197; // @[RegisterRouter.scala:87:24] wire out_f_roready_1197 = out_roready_1_1051 & out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11531 = out_f_roready_1197; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1197 = out_wivalid_1_1051 & out_wimask_1197; // @[RegisterRouter.scala:87:24] wire out_f_woready_1197 = out_woready_1_1051 & out_womask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11532 = ~out_rimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11533 = ~out_wimask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11534 = ~out_romask_1197; // @[RegisterRouter.scala:87:24] wire _out_T_11535 = ~out_womask_1197; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11537 = _out_T_11536; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1028 = _out_T_11537; // @[RegisterRouter.scala:87:24] wire out_rimask_1198 = |_out_rimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_wimask_1198 = &_out_wimask_T_1198; // @[RegisterRouter.scala:87:24] wire out_romask_1198 = |_out_romask_T_1198; // @[RegisterRouter.scala:87:24] wire out_womask_1198 = &_out_womask_T_1198; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1198 = out_rivalid_1_1052 & out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11539 = out_f_rivalid_1198; // @[RegisterRouter.scala:87:24] wire out_f_roready_1198 = out_roready_1_1052 & out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11540 = out_f_roready_1198; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1198 = out_wivalid_1_1052 & out_wimask_1198; // @[RegisterRouter.scala:87:24] wire out_f_woready_1198 = out_woready_1_1052 & out_womask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11541 = ~out_rimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11542 = ~out_wimask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11543 = ~out_romask_1198; // @[RegisterRouter.scala:87:24] wire _out_T_11544 = ~out_womask_1198; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1028 = {hi_498, flags_0_go, _out_prepend_T_1028}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11545 = out_prepend_1028; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11546 = _out_T_11545; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1029 = _out_T_11546; // @[RegisterRouter.scala:87:24] wire out_rimask_1199 = |_out_rimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_wimask_1199 = &_out_wimask_T_1199; // @[RegisterRouter.scala:87:24] wire out_romask_1199 = |_out_romask_T_1199; // @[RegisterRouter.scala:87:24] wire out_womask_1199 = &_out_womask_T_1199; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1199 = out_rivalid_1_1053 & out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11548 = out_f_rivalid_1199; // @[RegisterRouter.scala:87:24] wire out_f_roready_1199 = out_roready_1_1053 & out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11549 = out_f_roready_1199; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1199 = out_wivalid_1_1053 & out_wimask_1199; // @[RegisterRouter.scala:87:24] wire out_f_woready_1199 = out_woready_1_1053 & out_womask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11550 = ~out_rimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11551 = ~out_wimask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11552 = ~out_romask_1199; // @[RegisterRouter.scala:87:24] wire _out_T_11553 = ~out_womask_1199; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1029 = {hi_499, flags_0_go, _out_prepend_T_1029}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11554 = out_prepend_1029; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11555 = _out_T_11554; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1030 = _out_T_11555; // @[RegisterRouter.scala:87:24] wire out_rimask_1200 = |_out_rimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_wimask_1200 = &_out_wimask_T_1200; // @[RegisterRouter.scala:87:24] wire out_romask_1200 = |_out_romask_T_1200; // @[RegisterRouter.scala:87:24] wire out_womask_1200 = &_out_womask_T_1200; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1200 = out_rivalid_1_1054 & out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11557 = out_f_rivalid_1200; // @[RegisterRouter.scala:87:24] wire out_f_roready_1200 = out_roready_1_1054 & out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11558 = out_f_roready_1200; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1200 = out_wivalid_1_1054 & out_wimask_1200; // @[RegisterRouter.scala:87:24] wire out_f_woready_1200 = out_woready_1_1054 & out_womask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11559 = ~out_rimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11560 = ~out_wimask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11561 = ~out_romask_1200; // @[RegisterRouter.scala:87:24] wire _out_T_11562 = ~out_womask_1200; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1030 = {hi_500, flags_0_go, _out_prepend_T_1030}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11563 = out_prepend_1030; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11564 = _out_T_11563; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1031 = _out_T_11564; // @[RegisterRouter.scala:87:24] wire out_rimask_1201 = |_out_rimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_wimask_1201 = &_out_wimask_T_1201; // @[RegisterRouter.scala:87:24] wire out_romask_1201 = |_out_romask_T_1201; // @[RegisterRouter.scala:87:24] wire out_womask_1201 = &_out_womask_T_1201; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1201 = out_rivalid_1_1055 & out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11566 = out_f_rivalid_1201; // @[RegisterRouter.scala:87:24] wire out_f_roready_1201 = out_roready_1_1055 & out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11567 = out_f_roready_1201; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1201 = out_wivalid_1_1055 & out_wimask_1201; // @[RegisterRouter.scala:87:24] wire out_f_woready_1201 = out_woready_1_1055 & out_womask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11568 = ~out_rimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11569 = ~out_wimask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11570 = ~out_romask_1201; // @[RegisterRouter.scala:87:24] wire _out_T_11571 = ~out_womask_1201; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1031 = {hi_501, flags_0_go, _out_prepend_T_1031}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11572 = out_prepend_1031; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11573 = _out_T_11572; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1032 = _out_T_11573; // @[RegisterRouter.scala:87:24] wire out_rimask_1202 = |_out_rimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_wimask_1202 = &_out_wimask_T_1202; // @[RegisterRouter.scala:87:24] wire out_romask_1202 = |_out_romask_T_1202; // @[RegisterRouter.scala:87:24] wire out_womask_1202 = &_out_womask_T_1202; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1202 = out_rivalid_1_1056 & out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11575 = out_f_rivalid_1202; // @[RegisterRouter.scala:87:24] wire out_f_roready_1202 = out_roready_1_1056 & out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11576 = out_f_roready_1202; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1202 = out_wivalid_1_1056 & out_wimask_1202; // @[RegisterRouter.scala:87:24] wire out_f_woready_1202 = out_woready_1_1056 & out_womask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11577 = ~out_rimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11578 = ~out_wimask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11579 = ~out_romask_1202; // @[RegisterRouter.scala:87:24] wire _out_T_11580 = ~out_womask_1202; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1032 = {hi_502, flags_0_go, _out_prepend_T_1032}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11581 = out_prepend_1032; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11582 = _out_T_11581; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1033 = _out_T_11582; // @[RegisterRouter.scala:87:24] wire out_rimask_1203 = |_out_rimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_wimask_1203 = &_out_wimask_T_1203; // @[RegisterRouter.scala:87:24] wire out_romask_1203 = |_out_romask_T_1203; // @[RegisterRouter.scala:87:24] wire out_womask_1203 = &_out_womask_T_1203; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1203 = out_rivalid_1_1057 & out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11584 = out_f_rivalid_1203; // @[RegisterRouter.scala:87:24] wire out_f_roready_1203 = out_roready_1_1057 & out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11585 = out_f_roready_1203; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1203 = out_wivalid_1_1057 & out_wimask_1203; // @[RegisterRouter.scala:87:24] wire out_f_woready_1203 = out_woready_1_1057 & out_womask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11586 = ~out_rimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11587 = ~out_wimask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11588 = ~out_romask_1203; // @[RegisterRouter.scala:87:24] wire _out_T_11589 = ~out_womask_1203; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1033 = {hi_503, flags_0_go, _out_prepend_T_1033}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11590 = out_prepend_1033; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11591 = _out_T_11590; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1034 = _out_T_11591; // @[RegisterRouter.scala:87:24] wire out_rimask_1204 = |_out_rimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_wimask_1204 = &_out_wimask_T_1204; // @[RegisterRouter.scala:87:24] wire out_romask_1204 = |_out_romask_T_1204; // @[RegisterRouter.scala:87:24] wire out_womask_1204 = &_out_womask_T_1204; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1204 = out_rivalid_1_1058 & out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11593 = out_f_rivalid_1204; // @[RegisterRouter.scala:87:24] wire out_f_roready_1204 = out_roready_1_1058 & out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11594 = out_f_roready_1204; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1204 = out_wivalid_1_1058 & out_wimask_1204; // @[RegisterRouter.scala:87:24] wire out_f_woready_1204 = out_woready_1_1058 & out_womask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11595 = ~out_rimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11596 = ~out_wimask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11597 = ~out_romask_1204; // @[RegisterRouter.scala:87:24] wire _out_T_11598 = ~out_womask_1204; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1034 = {hi_504, flags_0_go, _out_prepend_T_1034}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11599 = out_prepend_1034; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11600 = _out_T_11599; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_190 = _out_T_11600; // @[MuxLiteral.scala:49:48] wire out_rimask_1205 = |_out_rimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_wimask_1205 = &_out_wimask_T_1205; // @[RegisterRouter.scala:87:24] wire out_romask_1205 = |_out_romask_T_1205; // @[RegisterRouter.scala:87:24] wire out_womask_1205 = &_out_womask_T_1205; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1205 = out_rivalid_1_1059 & out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11602 = out_f_rivalid_1205; // @[RegisterRouter.scala:87:24] wire out_f_roready_1205 = out_roready_1_1059 & out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11603 = out_f_roready_1205; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1205 = out_wivalid_1_1059 & out_wimask_1205; // @[RegisterRouter.scala:87:24] wire out_f_woready_1205 = out_woready_1_1059 & out_womask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11604 = ~out_rimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11605 = ~out_wimask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11606 = ~out_romask_1205; // @[RegisterRouter.scala:87:24] wire _out_T_11607 = ~out_womask_1205; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11609 = _out_T_11608; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1035 = _out_T_11609; // @[RegisterRouter.scala:87:24] wire out_rimask_1206 = |_out_rimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_wimask_1206 = &_out_wimask_T_1206; // @[RegisterRouter.scala:87:24] wire out_romask_1206 = |_out_romask_T_1206; // @[RegisterRouter.scala:87:24] wire out_womask_1206 = &_out_womask_T_1206; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1206 = out_rivalid_1_1060 & out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11611 = out_f_rivalid_1206; // @[RegisterRouter.scala:87:24] wire out_f_roready_1206 = out_roready_1_1060 & out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11612 = out_f_roready_1206; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1206 = out_wivalid_1_1060 & out_wimask_1206; // @[RegisterRouter.scala:87:24] wire out_f_woready_1206 = out_woready_1_1060 & out_womask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11613 = ~out_rimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11614 = ~out_wimask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11615 = ~out_romask_1206; // @[RegisterRouter.scala:87:24] wire _out_T_11616 = ~out_womask_1206; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1035 = {hi_442, flags_0_go, _out_prepend_T_1035}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11617 = out_prepend_1035; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11618 = _out_T_11617; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1036 = _out_T_11618; // @[RegisterRouter.scala:87:24] wire out_rimask_1207 = |_out_rimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_wimask_1207 = &_out_wimask_T_1207; // @[RegisterRouter.scala:87:24] wire out_romask_1207 = |_out_romask_T_1207; // @[RegisterRouter.scala:87:24] wire out_womask_1207 = &_out_womask_T_1207; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1207 = out_rivalid_1_1061 & out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11620 = out_f_rivalid_1207; // @[RegisterRouter.scala:87:24] wire out_f_roready_1207 = out_roready_1_1061 & out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11621 = out_f_roready_1207; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1207 = out_wivalid_1_1061 & out_wimask_1207; // @[RegisterRouter.scala:87:24] wire out_f_woready_1207 = out_woready_1_1061 & out_womask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11622 = ~out_rimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11623 = ~out_wimask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11624 = ~out_romask_1207; // @[RegisterRouter.scala:87:24] wire _out_T_11625 = ~out_womask_1207; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1036 = {hi_443, flags_0_go, _out_prepend_T_1036}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11626 = out_prepend_1036; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11627 = _out_T_11626; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1037 = _out_T_11627; // @[RegisterRouter.scala:87:24] wire out_rimask_1208 = |_out_rimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_wimask_1208 = &_out_wimask_T_1208; // @[RegisterRouter.scala:87:24] wire out_romask_1208 = |_out_romask_T_1208; // @[RegisterRouter.scala:87:24] wire out_womask_1208 = &_out_womask_T_1208; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1208 = out_rivalid_1_1062 & out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11629 = out_f_rivalid_1208; // @[RegisterRouter.scala:87:24] wire out_f_roready_1208 = out_roready_1_1062 & out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11630 = out_f_roready_1208; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1208 = out_wivalid_1_1062 & out_wimask_1208; // @[RegisterRouter.scala:87:24] wire out_f_woready_1208 = out_woready_1_1062 & out_womask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11631 = ~out_rimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11632 = ~out_wimask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11633 = ~out_romask_1208; // @[RegisterRouter.scala:87:24] wire _out_T_11634 = ~out_womask_1208; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1037 = {hi_444, flags_0_go, _out_prepend_T_1037}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11635 = out_prepend_1037; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11636 = _out_T_11635; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1038 = _out_T_11636; // @[RegisterRouter.scala:87:24] wire out_rimask_1209 = |_out_rimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_wimask_1209 = &_out_wimask_T_1209; // @[RegisterRouter.scala:87:24] wire out_romask_1209 = |_out_romask_T_1209; // @[RegisterRouter.scala:87:24] wire out_womask_1209 = &_out_womask_T_1209; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1209 = out_rivalid_1_1063 & out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11638 = out_f_rivalid_1209; // @[RegisterRouter.scala:87:24] wire out_f_roready_1209 = out_roready_1_1063 & out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11639 = out_f_roready_1209; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1209 = out_wivalid_1_1063 & out_wimask_1209; // @[RegisterRouter.scala:87:24] wire out_f_woready_1209 = out_woready_1_1063 & out_womask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11640 = ~out_rimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11641 = ~out_wimask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11642 = ~out_romask_1209; // @[RegisterRouter.scala:87:24] wire _out_T_11643 = ~out_womask_1209; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1038 = {hi_445, flags_0_go, _out_prepend_T_1038}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11644 = out_prepend_1038; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11645 = _out_T_11644; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1039 = _out_T_11645; // @[RegisterRouter.scala:87:24] wire out_rimask_1210 = |_out_rimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_wimask_1210 = &_out_wimask_T_1210; // @[RegisterRouter.scala:87:24] wire out_romask_1210 = |_out_romask_T_1210; // @[RegisterRouter.scala:87:24] wire out_womask_1210 = &_out_womask_T_1210; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1210 = out_rivalid_1_1064 & out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11647 = out_f_rivalid_1210; // @[RegisterRouter.scala:87:24] wire out_f_roready_1210 = out_roready_1_1064 & out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11648 = out_f_roready_1210; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1210 = out_wivalid_1_1064 & out_wimask_1210; // @[RegisterRouter.scala:87:24] wire out_f_woready_1210 = out_woready_1_1064 & out_womask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11649 = ~out_rimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11650 = ~out_wimask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11651 = ~out_romask_1210; // @[RegisterRouter.scala:87:24] wire _out_T_11652 = ~out_womask_1210; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1039 = {hi_446, flags_0_go, _out_prepend_T_1039}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11653 = out_prepend_1039; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11654 = _out_T_11653; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1040 = _out_T_11654; // @[RegisterRouter.scala:87:24] wire out_rimask_1211 = |_out_rimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_wimask_1211 = &_out_wimask_T_1211; // @[RegisterRouter.scala:87:24] wire out_romask_1211 = |_out_romask_T_1211; // @[RegisterRouter.scala:87:24] wire out_womask_1211 = &_out_womask_T_1211; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1211 = out_rivalid_1_1065 & out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11656 = out_f_rivalid_1211; // @[RegisterRouter.scala:87:24] wire out_f_roready_1211 = out_roready_1_1065 & out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11657 = out_f_roready_1211; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1211 = out_wivalid_1_1065 & out_wimask_1211; // @[RegisterRouter.scala:87:24] wire out_f_woready_1211 = out_woready_1_1065 & out_womask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11658 = ~out_rimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11659 = ~out_wimask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11660 = ~out_romask_1211; // @[RegisterRouter.scala:87:24] wire _out_T_11661 = ~out_womask_1211; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1040 = {hi_447, flags_0_go, _out_prepend_T_1040}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11662 = out_prepend_1040; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11663 = _out_T_11662; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1041 = _out_T_11663; // @[RegisterRouter.scala:87:24] wire out_rimask_1212 = |_out_rimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_wimask_1212 = &_out_wimask_T_1212; // @[RegisterRouter.scala:87:24] wire out_romask_1212 = |_out_romask_T_1212; // @[RegisterRouter.scala:87:24] wire out_womask_1212 = &_out_womask_T_1212; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1212 = out_rivalid_1_1066 & out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11665 = out_f_rivalid_1212; // @[RegisterRouter.scala:87:24] wire out_f_roready_1212 = out_roready_1_1066 & out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11666 = out_f_roready_1212; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1212 = out_wivalid_1_1066 & out_wimask_1212; // @[RegisterRouter.scala:87:24] wire out_f_woready_1212 = out_woready_1_1066 & out_womask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11667 = ~out_rimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11668 = ~out_wimask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11669 = ~out_romask_1212; // @[RegisterRouter.scala:87:24] wire _out_T_11670 = ~out_womask_1212; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1041 = {hi_448, flags_0_go, _out_prepend_T_1041}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11671 = out_prepend_1041; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11672 = _out_T_11671; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_183 = _out_T_11672; // @[MuxLiteral.scala:49:48] wire out_rimask_1213 = |_out_rimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_wimask_1213 = &_out_wimask_T_1213; // @[RegisterRouter.scala:87:24] wire out_romask_1213 = |_out_romask_T_1213; // @[RegisterRouter.scala:87:24] wire out_womask_1213 = &_out_womask_T_1213; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1213 = out_rivalid_1_1067 & out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11674 = out_f_rivalid_1213; // @[RegisterRouter.scala:87:24] wire out_f_roready_1213 = out_roready_1_1067 & out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11675 = out_f_roready_1213; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1213 = out_wivalid_1_1067 & out_wimask_1213; // @[RegisterRouter.scala:87:24] wire out_f_woready_1213 = out_woready_1_1067 & out_womask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11676 = ~out_rimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11677 = ~out_wimask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11678 = ~out_romask_1213; // @[RegisterRouter.scala:87:24] wire _out_T_11679 = ~out_womask_1213; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11681 = _out_T_11680; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1042 = _out_T_11681; // @[RegisterRouter.scala:87:24] wire out_rimask_1214 = |_out_rimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_wimask_1214 = &_out_wimask_T_1214; // @[RegisterRouter.scala:87:24] wire out_romask_1214 = |_out_romask_T_1214; // @[RegisterRouter.scala:87:24] wire out_womask_1214 = &_out_womask_T_1214; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1214 = out_rivalid_1_1068 & out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11683 = out_f_rivalid_1214; // @[RegisterRouter.scala:87:24] wire out_f_roready_1214 = out_roready_1_1068 & out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11684 = out_f_roready_1214; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1214 = out_wivalid_1_1068 & out_wimask_1214; // @[RegisterRouter.scala:87:24] wire out_f_woready_1214 = out_woready_1_1068 & out_womask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11685 = ~out_rimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11686 = ~out_wimask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11687 = ~out_romask_1214; // @[RegisterRouter.scala:87:24] wire _out_T_11688 = ~out_womask_1214; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1042 = {hi_322, flags_0_go, _out_prepend_T_1042}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11689 = out_prepend_1042; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11690 = _out_T_11689; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1043 = _out_T_11690; // @[RegisterRouter.scala:87:24] wire out_rimask_1215 = |_out_rimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_wimask_1215 = &_out_wimask_T_1215; // @[RegisterRouter.scala:87:24] wire out_romask_1215 = |_out_romask_T_1215; // @[RegisterRouter.scala:87:24] wire out_womask_1215 = &_out_womask_T_1215; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1215 = out_rivalid_1_1069 & out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11692 = out_f_rivalid_1215; // @[RegisterRouter.scala:87:24] wire out_f_roready_1215 = out_roready_1_1069 & out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11693 = out_f_roready_1215; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1215 = out_wivalid_1_1069 & out_wimask_1215; // @[RegisterRouter.scala:87:24] wire out_f_woready_1215 = out_woready_1_1069 & out_womask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11694 = ~out_rimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11695 = ~out_wimask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11696 = ~out_romask_1215; // @[RegisterRouter.scala:87:24] wire _out_T_11697 = ~out_womask_1215; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1043 = {hi_323, flags_0_go, _out_prepend_T_1043}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11698 = out_prepend_1043; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11699 = _out_T_11698; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1044 = _out_T_11699; // @[RegisterRouter.scala:87:24] wire out_rimask_1216 = |_out_rimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_wimask_1216 = &_out_wimask_T_1216; // @[RegisterRouter.scala:87:24] wire out_romask_1216 = |_out_romask_T_1216; // @[RegisterRouter.scala:87:24] wire out_womask_1216 = &_out_womask_T_1216; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1216 = out_rivalid_1_1070 & out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11701 = out_f_rivalid_1216; // @[RegisterRouter.scala:87:24] wire out_f_roready_1216 = out_roready_1_1070 & out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11702 = out_f_roready_1216; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1216 = out_wivalid_1_1070 & out_wimask_1216; // @[RegisterRouter.scala:87:24] wire out_f_woready_1216 = out_woready_1_1070 & out_womask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11703 = ~out_rimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11704 = ~out_wimask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11705 = ~out_romask_1216; // @[RegisterRouter.scala:87:24] wire _out_T_11706 = ~out_womask_1216; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1044 = {hi_324, flags_0_go, _out_prepend_T_1044}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11707 = out_prepend_1044; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11708 = _out_T_11707; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1045 = _out_T_11708; // @[RegisterRouter.scala:87:24] wire out_rimask_1217 = |_out_rimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_wimask_1217 = &_out_wimask_T_1217; // @[RegisterRouter.scala:87:24] wire out_romask_1217 = |_out_romask_T_1217; // @[RegisterRouter.scala:87:24] wire out_womask_1217 = &_out_womask_T_1217; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1217 = out_rivalid_1_1071 & out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11710 = out_f_rivalid_1217; // @[RegisterRouter.scala:87:24] wire out_f_roready_1217 = out_roready_1_1071 & out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11711 = out_f_roready_1217; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1217 = out_wivalid_1_1071 & out_wimask_1217; // @[RegisterRouter.scala:87:24] wire out_f_woready_1217 = out_woready_1_1071 & out_womask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11712 = ~out_rimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11713 = ~out_wimask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11714 = ~out_romask_1217; // @[RegisterRouter.scala:87:24] wire _out_T_11715 = ~out_womask_1217; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1045 = {hi_325, flags_0_go, _out_prepend_T_1045}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11716 = out_prepend_1045; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11717 = _out_T_11716; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1046 = _out_T_11717; // @[RegisterRouter.scala:87:24] wire out_rimask_1218 = |_out_rimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_wimask_1218 = &_out_wimask_T_1218; // @[RegisterRouter.scala:87:24] wire out_romask_1218 = |_out_romask_T_1218; // @[RegisterRouter.scala:87:24] wire out_womask_1218 = &_out_womask_T_1218; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1218 = out_rivalid_1_1072 & out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11719 = out_f_rivalid_1218; // @[RegisterRouter.scala:87:24] wire out_f_roready_1218 = out_roready_1_1072 & out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11720 = out_f_roready_1218; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1218 = out_wivalid_1_1072 & out_wimask_1218; // @[RegisterRouter.scala:87:24] wire out_f_woready_1218 = out_woready_1_1072 & out_womask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11721 = ~out_rimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11722 = ~out_wimask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11723 = ~out_romask_1218; // @[RegisterRouter.scala:87:24] wire _out_T_11724 = ~out_womask_1218; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1046 = {hi_326, flags_0_go, _out_prepend_T_1046}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11725 = out_prepend_1046; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11726 = _out_T_11725; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1047 = _out_T_11726; // @[RegisterRouter.scala:87:24] wire out_rimask_1219 = |_out_rimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_wimask_1219 = &_out_wimask_T_1219; // @[RegisterRouter.scala:87:24] wire out_romask_1219 = |_out_romask_T_1219; // @[RegisterRouter.scala:87:24] wire out_womask_1219 = &_out_womask_T_1219; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1219 = out_rivalid_1_1073 & out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11728 = out_f_rivalid_1219; // @[RegisterRouter.scala:87:24] wire out_f_roready_1219 = out_roready_1_1073 & out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11729 = out_f_roready_1219; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1219 = out_wivalid_1_1073 & out_wimask_1219; // @[RegisterRouter.scala:87:24] wire out_f_woready_1219 = out_woready_1_1073 & out_womask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11730 = ~out_rimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11731 = ~out_wimask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11732 = ~out_romask_1219; // @[RegisterRouter.scala:87:24] wire _out_T_11733 = ~out_womask_1219; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1047 = {hi_327, flags_0_go, _out_prepend_T_1047}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11734 = out_prepend_1047; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11735 = _out_T_11734; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1048 = _out_T_11735; // @[RegisterRouter.scala:87:24] wire out_rimask_1220 = |_out_rimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_wimask_1220 = &_out_wimask_T_1220; // @[RegisterRouter.scala:87:24] wire out_romask_1220 = |_out_romask_T_1220; // @[RegisterRouter.scala:87:24] wire out_womask_1220 = &_out_womask_T_1220; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1220 = out_rivalid_1_1074 & out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11737 = out_f_rivalid_1220; // @[RegisterRouter.scala:87:24] wire out_f_roready_1220 = out_roready_1_1074 & out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11738 = out_f_roready_1220; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1220 = out_wivalid_1_1074 & out_wimask_1220; // @[RegisterRouter.scala:87:24] wire out_f_woready_1220 = out_woready_1_1074 & out_womask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11739 = ~out_rimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11740 = ~out_wimask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11741 = ~out_romask_1220; // @[RegisterRouter.scala:87:24] wire _out_T_11742 = ~out_womask_1220; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1048 = {hi_328, flags_0_go, _out_prepend_T_1048}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11743 = out_prepend_1048; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11744 = _out_T_11743; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_168 = _out_T_11744; // @[MuxLiteral.scala:49:48] wire out_rimask_1221 = |_out_rimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_wimask_1221 = &_out_wimask_T_1221; // @[RegisterRouter.scala:87:24] wire out_romask_1221 = |_out_romask_T_1221; // @[RegisterRouter.scala:87:24] wire out_womask_1221 = &_out_womask_T_1221; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1221 = out_rivalid_1_1075 & out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11746 = out_f_rivalid_1221; // @[RegisterRouter.scala:87:24] wire out_f_roready_1221 = out_roready_1_1075 & out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11747 = out_f_roready_1221; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1221 = out_wivalid_1_1075 & out_wimask_1221; // @[RegisterRouter.scala:87:24] wire out_f_woready_1221 = out_woready_1_1075 & out_womask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11748 = ~out_rimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11749 = ~out_wimask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11750 = ~out_romask_1221; // @[RegisterRouter.scala:87:24] wire _out_T_11751 = ~out_womask_1221; // @[RegisterRouter.scala:87:24] wire out_rimask_1222 = |_out_rimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_wimask_1222 = &_out_wimask_T_1222; // @[RegisterRouter.scala:87:24] wire out_romask_1222 = |_out_romask_T_1222; // @[RegisterRouter.scala:87:24] wire out_womask_1222 = &_out_womask_T_1222; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1222 = out_rivalid_1_1076 & out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11755 = out_f_rivalid_1222; // @[RegisterRouter.scala:87:24] wire out_f_roready_1222 = out_roready_1_1076 & out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11756 = out_f_roready_1222; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1222 = out_wivalid_1_1076 & out_wimask_1222; // @[RegisterRouter.scala:87:24] wire out_f_woready_1222 = out_woready_1_1076 & out_womask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11757 = ~out_rimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11758 = ~out_wimask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11759 = ~out_romask_1222; // @[RegisterRouter.scala:87:24] wire _out_T_11760 = ~out_womask_1222; // @[RegisterRouter.scala:87:24] wire out_rimask_1223 = |_out_rimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_wimask_1223 = &_out_wimask_T_1223; // @[RegisterRouter.scala:87:24] wire out_romask_1223 = |_out_romask_T_1223; // @[RegisterRouter.scala:87:24] wire out_womask_1223 = &_out_womask_T_1223; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1223 = out_rivalid_1_1077 & out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11764 = out_f_rivalid_1223; // @[RegisterRouter.scala:87:24] wire out_f_roready_1223 = out_roready_1_1077 & out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11765 = out_f_roready_1223; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1223 = out_wivalid_1_1077 & out_wimask_1223; // @[RegisterRouter.scala:87:24] wire out_f_woready_1223 = out_woready_1_1077 & out_womask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11766 = ~out_rimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11767 = ~out_wimask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11768 = ~out_romask_1223; // @[RegisterRouter.scala:87:24] wire _out_T_11769 = ~out_womask_1223; // @[RegisterRouter.scala:87:24] wire out_rimask_1224 = |_out_rimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_wimask_1224 = &_out_wimask_T_1224; // @[RegisterRouter.scala:87:24] wire out_romask_1224 = |_out_romask_T_1224; // @[RegisterRouter.scala:87:24] wire out_womask_1224 = &_out_womask_T_1224; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1224 = out_rivalid_1_1078 & out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11773 = out_f_rivalid_1224; // @[RegisterRouter.scala:87:24] wire out_f_roready_1224 = out_roready_1_1078 & out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11774 = out_f_roready_1224; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1224 = out_wivalid_1_1078 & out_wimask_1224; // @[RegisterRouter.scala:87:24] wire out_f_woready_1224 = out_woready_1_1078 & out_womask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11775 = ~out_rimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11776 = ~out_wimask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11777 = ~out_romask_1224; // @[RegisterRouter.scala:87:24] wire _out_T_11778 = ~out_womask_1224; // @[RegisterRouter.scala:87:24] wire out_rimask_1225 = |_out_rimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_wimask_1225 = &_out_wimask_T_1225; // @[RegisterRouter.scala:87:24] wire out_romask_1225 = |_out_romask_T_1225; // @[RegisterRouter.scala:87:24] wire out_womask_1225 = &_out_womask_T_1225; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1225 = out_rivalid_1_1079 & out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11782 = out_f_rivalid_1225; // @[RegisterRouter.scala:87:24] wire out_f_roready_1225 = out_roready_1_1079 & out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11783 = out_f_roready_1225; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1225 = out_wivalid_1_1079 & out_wimask_1225; // @[RegisterRouter.scala:87:24] wire out_f_woready_1225 = out_woready_1_1079 & out_womask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11784 = ~out_rimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11785 = ~out_wimask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11786 = ~out_romask_1225; // @[RegisterRouter.scala:87:24] wire _out_T_11787 = ~out_womask_1225; // @[RegisterRouter.scala:87:24] wire out_rimask_1226 = |_out_rimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_wimask_1226 = &_out_wimask_T_1226; // @[RegisterRouter.scala:87:24] wire out_romask_1226 = |_out_romask_T_1226; // @[RegisterRouter.scala:87:24] wire out_womask_1226 = &_out_womask_T_1226; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1226 = out_rivalid_1_1080 & out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11791 = out_f_rivalid_1226; // @[RegisterRouter.scala:87:24] wire out_f_roready_1226 = out_roready_1_1080 & out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11792 = out_f_roready_1226; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1226 = out_wivalid_1_1080 & out_wimask_1226; // @[RegisterRouter.scala:87:24] wire out_f_woready_1226 = out_woready_1_1080 & out_womask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11793 = ~out_rimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11794 = ~out_wimask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11795 = ~out_romask_1226; // @[RegisterRouter.scala:87:24] wire _out_T_11796 = ~out_womask_1226; // @[RegisterRouter.scala:87:24] wire out_rimask_1227 = |_out_rimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_wimask_1227 = &_out_wimask_T_1227; // @[RegisterRouter.scala:87:24] wire out_romask_1227 = |_out_romask_T_1227; // @[RegisterRouter.scala:87:24] wire out_womask_1227 = &_out_womask_T_1227; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1227 = out_rivalid_1_1081 & out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11800 = out_f_rivalid_1227; // @[RegisterRouter.scala:87:24] wire out_f_roready_1227 = out_roready_1_1081 & out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11801 = out_f_roready_1227; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1227 = out_wivalid_1_1081 & out_wimask_1227; // @[RegisterRouter.scala:87:24] wire out_f_woready_1227 = out_woready_1_1081 & out_womask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11802 = ~out_rimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11803 = ~out_wimask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11804 = ~out_romask_1227; // @[RegisterRouter.scala:87:24] wire _out_T_11805 = ~out_womask_1227; // @[RegisterRouter.scala:87:24] wire out_rimask_1228 = |_out_rimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_wimask_1228 = &_out_wimask_T_1228; // @[RegisterRouter.scala:87:24] wire out_romask_1228 = |_out_romask_T_1228; // @[RegisterRouter.scala:87:24] wire out_womask_1228 = &_out_womask_T_1228; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1228 = out_rivalid_1_1082 & out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11809 = out_f_rivalid_1228; // @[RegisterRouter.scala:87:24] wire out_f_roready_1228 = out_roready_1_1082 & out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11810 = out_f_roready_1228; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1228 = out_wivalid_1_1082 & out_wimask_1228; // @[RegisterRouter.scala:87:24] wire out_f_woready_1228 = out_woready_1_1082 & out_womask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11811 = ~out_rimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11812 = ~out_wimask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11813 = ~out_romask_1228; // @[RegisterRouter.scala:87:24] wire _out_T_11814 = ~out_womask_1228; // @[RegisterRouter.scala:87:24] wire out_rimask_1229 = |_out_rimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_wimask_1229 = &_out_wimask_T_1229; // @[RegisterRouter.scala:87:24] wire out_romask_1229 = |_out_romask_T_1229; // @[RegisterRouter.scala:87:24] wire out_womask_1229 = &_out_womask_T_1229; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1229 = out_rivalid_1_1083 & out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11818 = out_f_rivalid_1229; // @[RegisterRouter.scala:87:24] wire out_f_roready_1229 = out_roready_1_1083 & out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11819 = out_f_roready_1229; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1229 = out_wivalid_1_1083 & out_wimask_1229; // @[RegisterRouter.scala:87:24] wire out_f_woready_1229 = out_woready_1_1083 & out_womask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11820 = ~out_rimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11821 = ~out_wimask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11822 = ~out_romask_1229; // @[RegisterRouter.scala:87:24] wire _out_T_11823 = ~out_womask_1229; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11825 = _out_T_11824; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1056 = _out_T_11825; // @[RegisterRouter.scala:87:24] wire out_rimask_1230 = |_out_rimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_wimask_1230 = &_out_wimask_T_1230; // @[RegisterRouter.scala:87:24] wire out_romask_1230 = |_out_romask_T_1230; // @[RegisterRouter.scala:87:24] wire out_womask_1230 = &_out_womask_T_1230; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1230 = out_rivalid_1_1084 & out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11827 = out_f_rivalid_1230; // @[RegisterRouter.scala:87:24] wire out_f_roready_1230 = out_roready_1_1084 & out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11828 = out_f_roready_1230; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1230 = out_wivalid_1_1084 & out_wimask_1230; // @[RegisterRouter.scala:87:24] wire out_f_woready_1230 = out_woready_1_1084 & out_womask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11829 = ~out_rimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11830 = ~out_wimask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11831 = ~out_romask_1230; // @[RegisterRouter.scala:87:24] wire _out_T_11832 = ~out_womask_1230; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1056 = {hi_658, flags_0_go, _out_prepend_T_1056}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11833 = out_prepend_1056; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11834 = _out_T_11833; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1057 = _out_T_11834; // @[RegisterRouter.scala:87:24] wire out_rimask_1231 = |_out_rimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_wimask_1231 = &_out_wimask_T_1231; // @[RegisterRouter.scala:87:24] wire out_romask_1231 = |_out_romask_T_1231; // @[RegisterRouter.scala:87:24] wire out_womask_1231 = &_out_womask_T_1231; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1231 = out_rivalid_1_1085 & out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11836 = out_f_rivalid_1231; // @[RegisterRouter.scala:87:24] wire out_f_roready_1231 = out_roready_1_1085 & out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11837 = out_f_roready_1231; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1231 = out_wivalid_1_1085 & out_wimask_1231; // @[RegisterRouter.scala:87:24] wire out_f_woready_1231 = out_woready_1_1085 & out_womask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11838 = ~out_rimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11839 = ~out_wimask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11840 = ~out_romask_1231; // @[RegisterRouter.scala:87:24] wire _out_T_11841 = ~out_womask_1231; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1057 = {hi_659, flags_0_go, _out_prepend_T_1057}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11842 = out_prepend_1057; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11843 = _out_T_11842; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1058 = _out_T_11843; // @[RegisterRouter.scala:87:24] wire out_rimask_1232 = |_out_rimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_wimask_1232 = &_out_wimask_T_1232; // @[RegisterRouter.scala:87:24] wire out_romask_1232 = |_out_romask_T_1232; // @[RegisterRouter.scala:87:24] wire out_womask_1232 = &_out_womask_T_1232; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1232 = out_rivalid_1_1086 & out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11845 = out_f_rivalid_1232; // @[RegisterRouter.scala:87:24] wire out_f_roready_1232 = out_roready_1_1086 & out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11846 = out_f_roready_1232; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1232 = out_wivalid_1_1086 & out_wimask_1232; // @[RegisterRouter.scala:87:24] wire out_f_woready_1232 = out_woready_1_1086 & out_womask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11847 = ~out_rimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11848 = ~out_wimask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11849 = ~out_romask_1232; // @[RegisterRouter.scala:87:24] wire _out_T_11850 = ~out_womask_1232; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1058 = {hi_660, flags_0_go, _out_prepend_T_1058}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11851 = out_prepend_1058; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11852 = _out_T_11851; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1059 = _out_T_11852; // @[RegisterRouter.scala:87:24] wire out_rimask_1233 = |_out_rimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_wimask_1233 = &_out_wimask_T_1233; // @[RegisterRouter.scala:87:24] wire out_romask_1233 = |_out_romask_T_1233; // @[RegisterRouter.scala:87:24] wire out_womask_1233 = &_out_womask_T_1233; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1233 = out_rivalid_1_1087 & out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11854 = out_f_rivalid_1233; // @[RegisterRouter.scala:87:24] wire out_f_roready_1233 = out_roready_1_1087 & out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11855 = out_f_roready_1233; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1233 = out_wivalid_1_1087 & out_wimask_1233; // @[RegisterRouter.scala:87:24] wire out_f_woready_1233 = out_woready_1_1087 & out_womask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11856 = ~out_rimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11857 = ~out_wimask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11858 = ~out_romask_1233; // @[RegisterRouter.scala:87:24] wire _out_T_11859 = ~out_womask_1233; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1059 = {hi_661, flags_0_go, _out_prepend_T_1059}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11860 = out_prepend_1059; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11861 = _out_T_11860; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1060 = _out_T_11861; // @[RegisterRouter.scala:87:24] wire out_rimask_1234 = |_out_rimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_wimask_1234 = &_out_wimask_T_1234; // @[RegisterRouter.scala:87:24] wire out_romask_1234 = |_out_romask_T_1234; // @[RegisterRouter.scala:87:24] wire out_womask_1234 = &_out_womask_T_1234; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1234 = out_rivalid_1_1088 & out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11863 = out_f_rivalid_1234; // @[RegisterRouter.scala:87:24] wire out_f_roready_1234 = out_roready_1_1088 & out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11864 = out_f_roready_1234; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1234 = out_wivalid_1_1088 & out_wimask_1234; // @[RegisterRouter.scala:87:24] wire out_f_woready_1234 = out_woready_1_1088 & out_womask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11865 = ~out_rimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11866 = ~out_wimask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11867 = ~out_romask_1234; // @[RegisterRouter.scala:87:24] wire _out_T_11868 = ~out_womask_1234; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1060 = {hi_662, flags_0_go, _out_prepend_T_1060}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11869 = out_prepend_1060; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11870 = _out_T_11869; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1061 = _out_T_11870; // @[RegisterRouter.scala:87:24] wire out_rimask_1235 = |_out_rimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_wimask_1235 = &_out_wimask_T_1235; // @[RegisterRouter.scala:87:24] wire out_romask_1235 = |_out_romask_T_1235; // @[RegisterRouter.scala:87:24] wire out_womask_1235 = &_out_womask_T_1235; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1235 = out_rivalid_1_1089 & out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11872 = out_f_rivalid_1235; // @[RegisterRouter.scala:87:24] wire out_f_roready_1235 = out_roready_1_1089 & out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11873 = out_f_roready_1235; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1235 = out_wivalid_1_1089 & out_wimask_1235; // @[RegisterRouter.scala:87:24] wire out_f_woready_1235 = out_woready_1_1089 & out_womask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11874 = ~out_rimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11875 = ~out_wimask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11876 = ~out_romask_1235; // @[RegisterRouter.scala:87:24] wire _out_T_11877 = ~out_womask_1235; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1061 = {hi_663, flags_0_go, _out_prepend_T_1061}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11878 = out_prepend_1061; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11879 = _out_T_11878; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1062 = _out_T_11879; // @[RegisterRouter.scala:87:24] wire out_rimask_1236 = |_out_rimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_wimask_1236 = &_out_wimask_T_1236; // @[RegisterRouter.scala:87:24] wire out_romask_1236 = |_out_romask_T_1236; // @[RegisterRouter.scala:87:24] wire out_womask_1236 = &_out_womask_T_1236; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1236 = out_rivalid_1_1090 & out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11881 = out_f_rivalid_1236; // @[RegisterRouter.scala:87:24] wire out_f_roready_1236 = out_roready_1_1090 & out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11882 = out_f_roready_1236; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1236 = out_wivalid_1_1090 & out_wimask_1236; // @[RegisterRouter.scala:87:24] wire out_f_woready_1236 = out_woready_1_1090 & out_womask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11883 = ~out_rimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11884 = ~out_wimask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11885 = ~out_romask_1236; // @[RegisterRouter.scala:87:24] wire _out_T_11886 = ~out_womask_1236; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1062 = {hi_664, flags_0_go, _out_prepend_T_1062}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11887 = out_prepend_1062; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11888 = _out_T_11887; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_210 = _out_T_11888; // @[MuxLiteral.scala:49:48] wire out_rimask_1237 = |_out_rimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_wimask_1237 = &_out_wimask_T_1237; // @[RegisterRouter.scala:87:24] wire out_romask_1237 = |_out_romask_T_1237; // @[RegisterRouter.scala:87:24] wire out_womask_1237 = &_out_womask_T_1237; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1237 = out_rivalid_1_1091 & out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11890 = out_f_rivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_roready_1237 = out_roready_1_1091 & out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11891 = out_f_roready_1237; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1237 = out_wivalid_1_1091 & out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11892 = out_f_wivalid_1237; // @[RegisterRouter.scala:87:24] wire out_f_woready_1237 = out_woready_1_1091 & out_womask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11893 = out_f_woready_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11894 = ~out_rimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11895 = ~out_wimask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11896 = ~out_romask_1237; // @[RegisterRouter.scala:87:24] wire _out_T_11897 = ~out_womask_1237; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11899 = _out_T_11898; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1063 = _out_T_11899; // @[RegisterRouter.scala:87:24] wire out_rimask_1238 = |_out_rimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_wimask_1238 = &_out_wimask_T_1238; // @[RegisterRouter.scala:87:24] wire out_romask_1238 = |_out_romask_T_1238; // @[RegisterRouter.scala:87:24] wire out_womask_1238 = &_out_womask_T_1238; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1238 = out_rivalid_1_1092 & out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11901 = out_f_rivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_roready_1238 = out_roready_1_1092 & out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11902 = out_f_roready_1238; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1238 = out_wivalid_1_1092 & out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11903 = out_f_wivalid_1238; // @[RegisterRouter.scala:87:24] wire out_f_woready_1238 = out_woready_1_1092 & out_womask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11904 = out_f_woready_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11905 = ~out_rimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11906 = ~out_wimask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11907 = ~out_romask_1238; // @[RegisterRouter.scala:87:24] wire _out_T_11908 = ~out_womask_1238; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1063 = {programBufferMem_25, _out_prepend_T_1063}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11909 = out_prepend_1063; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11910 = _out_T_11909; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1064 = _out_T_11910; // @[RegisterRouter.scala:87:24] wire out_rimask_1239 = |_out_rimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_wimask_1239 = &_out_wimask_T_1239; // @[RegisterRouter.scala:87:24] wire out_romask_1239 = |_out_romask_T_1239; // @[RegisterRouter.scala:87:24] wire out_womask_1239 = &_out_womask_T_1239; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1239 = out_rivalid_1_1093 & out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11912 = out_f_rivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_roready_1239 = out_roready_1_1093 & out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11913 = out_f_roready_1239; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1239 = out_wivalid_1_1093 & out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11914 = out_f_wivalid_1239; // @[RegisterRouter.scala:87:24] wire out_f_woready_1239 = out_woready_1_1093 & out_womask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11915 = out_f_woready_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11916 = ~out_rimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11917 = ~out_wimask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11918 = ~out_romask_1239; // @[RegisterRouter.scala:87:24] wire _out_T_11919 = ~out_womask_1239; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1064 = {programBufferMem_26, _out_prepend_T_1064}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11920 = out_prepend_1064; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_11921 = _out_T_11920; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1065 = _out_T_11921; // @[RegisterRouter.scala:87:24] wire out_rimask_1240 = |_out_rimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_wimask_1240 = &_out_wimask_T_1240; // @[RegisterRouter.scala:87:24] wire out_romask_1240 = |_out_romask_T_1240; // @[RegisterRouter.scala:87:24] wire out_womask_1240 = &_out_womask_T_1240; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1240 = out_rivalid_1_1094 & out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11923 = out_f_rivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_roready_1240 = out_roready_1_1094 & out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11924 = out_f_roready_1240; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1240 = out_wivalid_1_1094 & out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11925 = out_f_wivalid_1240; // @[RegisterRouter.scala:87:24] wire out_f_woready_1240 = out_woready_1_1094 & out_womask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11926 = out_f_woready_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11927 = ~out_rimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11928 = ~out_wimask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11929 = ~out_romask_1240; // @[RegisterRouter.scala:87:24] wire _out_T_11930 = ~out_womask_1240; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1065 = {programBufferMem_27, _out_prepend_T_1065}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11931 = out_prepend_1065; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_11932 = _out_T_11931; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1066 = _out_T_11932; // @[RegisterRouter.scala:87:24] wire out_rimask_1241 = |_out_rimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_wimask_1241 = &_out_wimask_T_1241; // @[RegisterRouter.scala:87:24] wire out_romask_1241 = |_out_romask_T_1241; // @[RegisterRouter.scala:87:24] wire out_womask_1241 = &_out_womask_T_1241; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1241 = out_rivalid_1_1095 & out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11934 = out_f_rivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_roready_1241 = out_roready_1_1095 & out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11935 = out_f_roready_1241; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1241 = out_wivalid_1_1095 & out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11936 = out_f_wivalid_1241; // @[RegisterRouter.scala:87:24] wire out_f_woready_1241 = out_woready_1_1095 & out_womask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11937 = out_f_woready_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11938 = ~out_rimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11939 = ~out_wimask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11940 = ~out_romask_1241; // @[RegisterRouter.scala:87:24] wire _out_T_11941 = ~out_womask_1241; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1066 = {programBufferMem_28, _out_prepend_T_1066}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11942 = out_prepend_1066; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_11943 = _out_T_11942; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1067 = _out_T_11943; // @[RegisterRouter.scala:87:24] wire out_rimask_1242 = |_out_rimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_wimask_1242 = &_out_wimask_T_1242; // @[RegisterRouter.scala:87:24] wire out_romask_1242 = |_out_romask_T_1242; // @[RegisterRouter.scala:87:24] wire out_womask_1242 = &_out_womask_T_1242; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1242 = out_rivalid_1_1096 & out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11945 = out_f_rivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_roready_1242 = out_roready_1_1096 & out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11946 = out_f_roready_1242; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1242 = out_wivalid_1_1096 & out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11947 = out_f_wivalid_1242; // @[RegisterRouter.scala:87:24] wire out_f_woready_1242 = out_woready_1_1096 & out_womask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11948 = out_f_woready_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11949 = ~out_rimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11950 = ~out_wimask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11951 = ~out_romask_1242; // @[RegisterRouter.scala:87:24] wire _out_T_11952 = ~out_womask_1242; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1067 = {programBufferMem_29, _out_prepend_T_1067}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11953 = out_prepend_1067; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_11954 = _out_T_11953; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1068 = _out_T_11954; // @[RegisterRouter.scala:87:24] wire out_rimask_1243 = |_out_rimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_wimask_1243 = &_out_wimask_T_1243; // @[RegisterRouter.scala:87:24] wire out_romask_1243 = |_out_romask_T_1243; // @[RegisterRouter.scala:87:24] wire out_womask_1243 = &_out_womask_T_1243; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1243 = out_rivalid_1_1097 & out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11956 = out_f_rivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_roready_1243 = out_roready_1_1097 & out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11957 = out_f_roready_1243; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1243 = out_wivalid_1_1097 & out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11958 = out_f_wivalid_1243; // @[RegisterRouter.scala:87:24] wire out_f_woready_1243 = out_woready_1_1097 & out_womask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11959 = out_f_woready_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11960 = ~out_rimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11961 = ~out_wimask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11962 = ~out_romask_1243; // @[RegisterRouter.scala:87:24] wire _out_T_11963 = ~out_womask_1243; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1068 = {programBufferMem_30, _out_prepend_T_1068}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11964 = out_prepend_1068; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_11965 = _out_T_11964; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1069 = _out_T_11965; // @[RegisterRouter.scala:87:24] wire out_rimask_1244 = |_out_rimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_wimask_1244 = &_out_wimask_T_1244; // @[RegisterRouter.scala:87:24] wire out_romask_1244 = |_out_romask_T_1244; // @[RegisterRouter.scala:87:24] wire out_womask_1244 = &_out_womask_T_1244; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1244 = out_rivalid_1_1098 & out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11967 = out_f_rivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_roready_1244 = out_roready_1_1098 & out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11968 = out_f_roready_1244; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1244 = out_wivalid_1_1098 & out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11969 = out_f_wivalid_1244; // @[RegisterRouter.scala:87:24] wire out_f_woready_1244 = out_woready_1_1098 & out_womask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11970 = out_f_woready_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11971 = ~out_rimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11972 = ~out_wimask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11973 = ~out_romask_1244; // @[RegisterRouter.scala:87:24] wire _out_T_11974 = ~out_womask_1244; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1069 = {programBufferMem_31, _out_prepend_T_1069}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11975 = out_prepend_1069; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_11976 = _out_T_11975; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_107 = _out_T_11976; // @[MuxLiteral.scala:49:48] wire out_rimask_1245 = |_out_rimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_wimask_1245 = &_out_wimask_T_1245; // @[RegisterRouter.scala:87:24] wire out_romask_1245 = |_out_romask_T_1245; // @[RegisterRouter.scala:87:24] wire out_womask_1245 = &_out_womask_T_1245; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1245 = out_rivalid_1_1099 & out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11978 = out_f_rivalid_1245; // @[RegisterRouter.scala:87:24] wire out_f_roready_1245 = out_roready_1_1099 & out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11979 = out_f_roready_1245; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1245 = out_wivalid_1_1099 & out_wimask_1245; // @[RegisterRouter.scala:87:24] wire out_f_woready_1245 = out_woready_1_1099 & out_womask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11980 = ~out_rimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11981 = ~out_wimask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11982 = ~out_romask_1245; // @[RegisterRouter.scala:87:24] wire _out_T_11983 = ~out_womask_1245; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_11985 = _out_T_11984; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1070 = _out_T_11985; // @[RegisterRouter.scala:87:24] wire out_rimask_1246 = |_out_rimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_wimask_1246 = &_out_wimask_T_1246; // @[RegisterRouter.scala:87:24] wire out_romask_1246 = |_out_romask_T_1246; // @[RegisterRouter.scala:87:24] wire out_womask_1246 = &_out_womask_T_1246; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1246 = out_rivalid_1_1100 & out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11987 = out_f_rivalid_1246; // @[RegisterRouter.scala:87:24] wire out_f_roready_1246 = out_roready_1_1100 & out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11988 = out_f_roready_1246; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1246 = out_wivalid_1_1100 & out_wimask_1246; // @[RegisterRouter.scala:87:24] wire out_f_woready_1246 = out_woready_1_1100 & out_womask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11989 = ~out_rimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11990 = ~out_wimask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11991 = ~out_romask_1246; // @[RegisterRouter.scala:87:24] wire _out_T_11992 = ~out_womask_1246; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1070 = {hi_66, flags_0_go, _out_prepend_T_1070}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11993 = out_prepend_1070; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_11994 = _out_T_11993; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1071 = _out_T_11994; // @[RegisterRouter.scala:87:24] wire out_rimask_1247 = |_out_rimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_wimask_1247 = &_out_wimask_T_1247; // @[RegisterRouter.scala:87:24] wire out_romask_1247 = |_out_romask_T_1247; // @[RegisterRouter.scala:87:24] wire out_womask_1247 = &_out_womask_T_1247; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1247 = out_rivalid_1_1101 & out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11996 = out_f_rivalid_1247; // @[RegisterRouter.scala:87:24] wire out_f_roready_1247 = out_roready_1_1101 & out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11997 = out_f_roready_1247; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1247 = out_wivalid_1_1101 & out_wimask_1247; // @[RegisterRouter.scala:87:24] wire out_f_woready_1247 = out_woready_1_1101 & out_womask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11998 = ~out_rimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_11999 = ~out_wimask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12000 = ~out_romask_1247; // @[RegisterRouter.scala:87:24] wire _out_T_12001 = ~out_womask_1247; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1071 = {hi_67, flags_0_go, _out_prepend_T_1071}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12002 = out_prepend_1071; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12003 = _out_T_12002; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1072 = _out_T_12003; // @[RegisterRouter.scala:87:24] wire out_rimask_1248 = |_out_rimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_wimask_1248 = &_out_wimask_T_1248; // @[RegisterRouter.scala:87:24] wire out_romask_1248 = |_out_romask_T_1248; // @[RegisterRouter.scala:87:24] wire out_womask_1248 = &_out_womask_T_1248; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1248 = out_rivalid_1_1102 & out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12005 = out_f_rivalid_1248; // @[RegisterRouter.scala:87:24] wire out_f_roready_1248 = out_roready_1_1102 & out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12006 = out_f_roready_1248; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1248 = out_wivalid_1_1102 & out_wimask_1248; // @[RegisterRouter.scala:87:24] wire out_f_woready_1248 = out_woready_1_1102 & out_womask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12007 = ~out_rimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12008 = ~out_wimask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12009 = ~out_romask_1248; // @[RegisterRouter.scala:87:24] wire _out_T_12010 = ~out_womask_1248; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1072 = {hi_68, flags_0_go, _out_prepend_T_1072}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12011 = out_prepend_1072; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12012 = _out_T_12011; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1073 = _out_T_12012; // @[RegisterRouter.scala:87:24] wire out_rimask_1249 = |_out_rimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_wimask_1249 = &_out_wimask_T_1249; // @[RegisterRouter.scala:87:24] wire out_romask_1249 = |_out_romask_T_1249; // @[RegisterRouter.scala:87:24] wire out_womask_1249 = &_out_womask_T_1249; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1249 = out_rivalid_1_1103 & out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12014 = out_f_rivalid_1249; // @[RegisterRouter.scala:87:24] wire out_f_roready_1249 = out_roready_1_1103 & out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12015 = out_f_roready_1249; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1249 = out_wivalid_1_1103 & out_wimask_1249; // @[RegisterRouter.scala:87:24] wire out_f_woready_1249 = out_woready_1_1103 & out_womask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12016 = ~out_rimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12017 = ~out_wimask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12018 = ~out_romask_1249; // @[RegisterRouter.scala:87:24] wire _out_T_12019 = ~out_womask_1249; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1073 = {hi_69, flags_0_go, _out_prepend_T_1073}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12020 = out_prepend_1073; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12021 = _out_T_12020; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1074 = _out_T_12021; // @[RegisterRouter.scala:87:24] wire out_rimask_1250 = |_out_rimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_wimask_1250 = &_out_wimask_T_1250; // @[RegisterRouter.scala:87:24] wire out_romask_1250 = |_out_romask_T_1250; // @[RegisterRouter.scala:87:24] wire out_womask_1250 = &_out_womask_T_1250; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1250 = out_rivalid_1_1104 & out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12023 = out_f_rivalid_1250; // @[RegisterRouter.scala:87:24] wire out_f_roready_1250 = out_roready_1_1104 & out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12024 = out_f_roready_1250; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1250 = out_wivalid_1_1104 & out_wimask_1250; // @[RegisterRouter.scala:87:24] wire out_f_woready_1250 = out_woready_1_1104 & out_womask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12025 = ~out_rimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12026 = ~out_wimask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12027 = ~out_romask_1250; // @[RegisterRouter.scala:87:24] wire _out_T_12028 = ~out_womask_1250; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1074 = {hi_70, flags_0_go, _out_prepend_T_1074}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12029 = out_prepend_1074; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12030 = _out_T_12029; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1075 = _out_T_12030; // @[RegisterRouter.scala:87:24] wire out_rimask_1251 = |_out_rimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_wimask_1251 = &_out_wimask_T_1251; // @[RegisterRouter.scala:87:24] wire out_romask_1251 = |_out_romask_T_1251; // @[RegisterRouter.scala:87:24] wire out_womask_1251 = &_out_womask_T_1251; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1251 = out_rivalid_1_1105 & out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12032 = out_f_rivalid_1251; // @[RegisterRouter.scala:87:24] wire out_f_roready_1251 = out_roready_1_1105 & out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12033 = out_f_roready_1251; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1251 = out_wivalid_1_1105 & out_wimask_1251; // @[RegisterRouter.scala:87:24] wire out_f_woready_1251 = out_woready_1_1105 & out_womask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12034 = ~out_rimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12035 = ~out_wimask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12036 = ~out_romask_1251; // @[RegisterRouter.scala:87:24] wire _out_T_12037 = ~out_womask_1251; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1075 = {hi_71, flags_0_go, _out_prepend_T_1075}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12038 = out_prepend_1075; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12039 = _out_T_12038; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1076 = _out_T_12039; // @[RegisterRouter.scala:87:24] wire out_rimask_1252 = |_out_rimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_wimask_1252 = &_out_wimask_T_1252; // @[RegisterRouter.scala:87:24] wire out_romask_1252 = |_out_romask_T_1252; // @[RegisterRouter.scala:87:24] wire out_womask_1252 = &_out_womask_T_1252; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1252 = out_rivalid_1_1106 & out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12041 = out_f_rivalid_1252; // @[RegisterRouter.scala:87:24] wire out_f_roready_1252 = out_roready_1_1106 & out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12042 = out_f_roready_1252; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1252 = out_wivalid_1_1106 & out_wimask_1252; // @[RegisterRouter.scala:87:24] wire out_f_woready_1252 = out_woready_1_1106 & out_womask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12043 = ~out_rimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12044 = ~out_wimask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12045 = ~out_romask_1252; // @[RegisterRouter.scala:87:24] wire _out_T_12046 = ~out_womask_1252; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1076 = {hi_72, flags_0_go, _out_prepend_T_1076}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12047 = out_prepend_1076; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12048 = _out_T_12047; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_136 = _out_T_12048; // @[MuxLiteral.scala:49:48] wire out_rimask_1253 = |_out_rimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_wimask_1253 = &_out_wimask_T_1253; // @[RegisterRouter.scala:87:24] wire out_romask_1253 = |_out_romask_T_1253; // @[RegisterRouter.scala:87:24] wire out_womask_1253 = &_out_womask_T_1253; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1253 = out_rivalid_1_1107 & out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12050 = out_f_rivalid_1253; // @[RegisterRouter.scala:87:24] wire out_f_roready_1253 = out_roready_1_1107 & out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12051 = out_f_roready_1253; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1253 = out_wivalid_1_1107 & out_wimask_1253; // @[RegisterRouter.scala:87:24] wire out_f_woready_1253 = out_woready_1_1107 & out_womask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12052 = ~out_rimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12053 = ~out_wimask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12054 = ~out_romask_1253; // @[RegisterRouter.scala:87:24] wire _out_T_12055 = ~out_womask_1253; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12057 = _out_T_12056; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1077 = _out_T_12057; // @[RegisterRouter.scala:87:24] wire out_rimask_1254 = |_out_rimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_wimask_1254 = &_out_wimask_T_1254; // @[RegisterRouter.scala:87:24] wire out_romask_1254 = |_out_romask_T_1254; // @[RegisterRouter.scala:87:24] wire out_womask_1254 = &_out_womask_T_1254; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1254 = out_rivalid_1_1108 & out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12059 = out_f_rivalid_1254; // @[RegisterRouter.scala:87:24] wire out_f_roready_1254 = out_roready_1_1108 & out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12060 = out_f_roready_1254; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1254 = out_wivalid_1_1108 & out_wimask_1254; // @[RegisterRouter.scala:87:24] wire out_f_woready_1254 = out_woready_1_1108 & out_womask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12061 = ~out_rimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12062 = ~out_wimask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12063 = ~out_romask_1254; // @[RegisterRouter.scala:87:24] wire _out_T_12064 = ~out_womask_1254; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1077 = {hi_538, flags_0_go, _out_prepend_T_1077}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12065 = out_prepend_1077; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12066 = _out_T_12065; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1078 = _out_T_12066; // @[RegisterRouter.scala:87:24] wire out_rimask_1255 = |_out_rimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_wimask_1255 = &_out_wimask_T_1255; // @[RegisterRouter.scala:87:24] wire out_romask_1255 = |_out_romask_T_1255; // @[RegisterRouter.scala:87:24] wire out_womask_1255 = &_out_womask_T_1255; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1255 = out_rivalid_1_1109 & out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12068 = out_f_rivalid_1255; // @[RegisterRouter.scala:87:24] wire out_f_roready_1255 = out_roready_1_1109 & out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12069 = out_f_roready_1255; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1255 = out_wivalid_1_1109 & out_wimask_1255; // @[RegisterRouter.scala:87:24] wire out_f_woready_1255 = out_woready_1_1109 & out_womask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12070 = ~out_rimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12071 = ~out_wimask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12072 = ~out_romask_1255; // @[RegisterRouter.scala:87:24] wire _out_T_12073 = ~out_womask_1255; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1078 = {hi_539, flags_0_go, _out_prepend_T_1078}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12074 = out_prepend_1078; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12075 = _out_T_12074; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1079 = _out_T_12075; // @[RegisterRouter.scala:87:24] wire out_rimask_1256 = |_out_rimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_wimask_1256 = &_out_wimask_T_1256; // @[RegisterRouter.scala:87:24] wire out_romask_1256 = |_out_romask_T_1256; // @[RegisterRouter.scala:87:24] wire out_womask_1256 = &_out_womask_T_1256; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1256 = out_rivalid_1_1110 & out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12077 = out_f_rivalid_1256; // @[RegisterRouter.scala:87:24] wire out_f_roready_1256 = out_roready_1_1110 & out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12078 = out_f_roready_1256; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1256 = out_wivalid_1_1110 & out_wimask_1256; // @[RegisterRouter.scala:87:24] wire out_f_woready_1256 = out_woready_1_1110 & out_womask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12079 = ~out_rimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12080 = ~out_wimask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12081 = ~out_romask_1256; // @[RegisterRouter.scala:87:24] wire _out_T_12082 = ~out_womask_1256; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1079 = {hi_540, flags_0_go, _out_prepend_T_1079}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12083 = out_prepend_1079; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12084 = _out_T_12083; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1080 = _out_T_12084; // @[RegisterRouter.scala:87:24] wire out_rimask_1257 = |_out_rimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_wimask_1257 = &_out_wimask_T_1257; // @[RegisterRouter.scala:87:24] wire out_romask_1257 = |_out_romask_T_1257; // @[RegisterRouter.scala:87:24] wire out_womask_1257 = &_out_womask_T_1257; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1257 = out_rivalid_1_1111 & out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12086 = out_f_rivalid_1257; // @[RegisterRouter.scala:87:24] wire out_f_roready_1257 = out_roready_1_1111 & out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12087 = out_f_roready_1257; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1257 = out_wivalid_1_1111 & out_wimask_1257; // @[RegisterRouter.scala:87:24] wire out_f_woready_1257 = out_woready_1_1111 & out_womask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12088 = ~out_rimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12089 = ~out_wimask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12090 = ~out_romask_1257; // @[RegisterRouter.scala:87:24] wire _out_T_12091 = ~out_womask_1257; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1080 = {hi_541, flags_0_go, _out_prepend_T_1080}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12092 = out_prepend_1080; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12093 = _out_T_12092; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1081 = _out_T_12093; // @[RegisterRouter.scala:87:24] wire out_rimask_1258 = |_out_rimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_wimask_1258 = &_out_wimask_T_1258; // @[RegisterRouter.scala:87:24] wire out_romask_1258 = |_out_romask_T_1258; // @[RegisterRouter.scala:87:24] wire out_womask_1258 = &_out_womask_T_1258; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1258 = out_rivalid_1_1112 & out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12095 = out_f_rivalid_1258; // @[RegisterRouter.scala:87:24] wire out_f_roready_1258 = out_roready_1_1112 & out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12096 = out_f_roready_1258; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1258 = out_wivalid_1_1112 & out_wimask_1258; // @[RegisterRouter.scala:87:24] wire out_f_woready_1258 = out_woready_1_1112 & out_womask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12097 = ~out_rimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12098 = ~out_wimask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12099 = ~out_romask_1258; // @[RegisterRouter.scala:87:24] wire _out_T_12100 = ~out_womask_1258; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1081 = {hi_542, flags_0_go, _out_prepend_T_1081}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12101 = out_prepend_1081; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12102 = _out_T_12101; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1082 = _out_T_12102; // @[RegisterRouter.scala:87:24] wire out_rimask_1259 = |_out_rimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_wimask_1259 = &_out_wimask_T_1259; // @[RegisterRouter.scala:87:24] wire out_romask_1259 = |_out_romask_T_1259; // @[RegisterRouter.scala:87:24] wire out_womask_1259 = &_out_womask_T_1259; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1259 = out_rivalid_1_1113 & out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12104 = out_f_rivalid_1259; // @[RegisterRouter.scala:87:24] wire out_f_roready_1259 = out_roready_1_1113 & out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12105 = out_f_roready_1259; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1259 = out_wivalid_1_1113 & out_wimask_1259; // @[RegisterRouter.scala:87:24] wire out_f_woready_1259 = out_woready_1_1113 & out_womask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12106 = ~out_rimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12107 = ~out_wimask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12108 = ~out_romask_1259; // @[RegisterRouter.scala:87:24] wire _out_T_12109 = ~out_womask_1259; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1082 = {hi_543, flags_0_go, _out_prepend_T_1082}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12110 = out_prepend_1082; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12111 = _out_T_12110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1083 = _out_T_12111; // @[RegisterRouter.scala:87:24] wire out_rimask_1260 = |_out_rimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_wimask_1260 = &_out_wimask_T_1260; // @[RegisterRouter.scala:87:24] wire out_romask_1260 = |_out_romask_T_1260; // @[RegisterRouter.scala:87:24] wire out_womask_1260 = &_out_womask_T_1260; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1260 = out_rivalid_1_1114 & out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12113 = out_f_rivalid_1260; // @[RegisterRouter.scala:87:24] wire out_f_roready_1260 = out_roready_1_1114 & out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12114 = out_f_roready_1260; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1260 = out_wivalid_1_1114 & out_wimask_1260; // @[RegisterRouter.scala:87:24] wire out_f_woready_1260 = out_woready_1_1114 & out_womask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12115 = ~out_rimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12116 = ~out_wimask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12117 = ~out_romask_1260; // @[RegisterRouter.scala:87:24] wire _out_T_12118 = ~out_womask_1260; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1083 = {hi_544, flags_0_go, _out_prepend_T_1083}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12119 = out_prepend_1083; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12120 = _out_T_12119; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_195 = _out_T_12120; // @[MuxLiteral.scala:49:48] wire out_rimask_1261 = |_out_rimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_wimask_1261 = &_out_wimask_T_1261; // @[RegisterRouter.scala:87:24] wire out_romask_1261 = |_out_romask_T_1261; // @[RegisterRouter.scala:87:24] wire out_womask_1261 = &_out_womask_T_1261; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1261 = out_rivalid_1_1115 & out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12122 = out_f_rivalid_1261; // @[RegisterRouter.scala:87:24] wire out_f_roready_1261 = out_roready_1_1115 & out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12123 = out_f_roready_1261; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1261 = out_wivalid_1_1115 & out_wimask_1261; // @[RegisterRouter.scala:87:24] wire out_f_woready_1261 = out_woready_1_1115 & out_womask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12124 = ~out_rimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12125 = ~out_wimask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12126 = ~out_romask_1261; // @[RegisterRouter.scala:87:24] wire _out_T_12127 = ~out_womask_1261; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12129 = _out_T_12128; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1084 = _out_T_12129; // @[RegisterRouter.scala:87:24] wire out_rimask_1262 = |_out_rimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_wimask_1262 = &_out_wimask_T_1262; // @[RegisterRouter.scala:87:24] wire out_romask_1262 = |_out_romask_T_1262; // @[RegisterRouter.scala:87:24] wire out_womask_1262 = &_out_womask_T_1262; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1262 = out_rivalid_1_1116 & out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12131 = out_f_rivalid_1262; // @[RegisterRouter.scala:87:24] wire out_f_roready_1262 = out_roready_1_1116 & out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12132 = out_f_roready_1262; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1262 = out_wivalid_1_1116 & out_wimask_1262; // @[RegisterRouter.scala:87:24] wire out_f_woready_1262 = out_woready_1_1116 & out_womask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12133 = ~out_rimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12134 = ~out_wimask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12135 = ~out_romask_1262; // @[RegisterRouter.scala:87:24] wire _out_T_12136 = ~out_womask_1262; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1084 = {hi_890, flags_0_go, _out_prepend_T_1084}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12137 = out_prepend_1084; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12138 = _out_T_12137; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1085 = _out_T_12138; // @[RegisterRouter.scala:87:24] wire out_rimask_1263 = |_out_rimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_wimask_1263 = &_out_wimask_T_1263; // @[RegisterRouter.scala:87:24] wire out_romask_1263 = |_out_romask_T_1263; // @[RegisterRouter.scala:87:24] wire out_womask_1263 = &_out_womask_T_1263; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1263 = out_rivalid_1_1117 & out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12140 = out_f_rivalid_1263; // @[RegisterRouter.scala:87:24] wire out_f_roready_1263 = out_roready_1_1117 & out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12141 = out_f_roready_1263; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1263 = out_wivalid_1_1117 & out_wimask_1263; // @[RegisterRouter.scala:87:24] wire out_f_woready_1263 = out_woready_1_1117 & out_womask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12142 = ~out_rimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12143 = ~out_wimask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12144 = ~out_romask_1263; // @[RegisterRouter.scala:87:24] wire _out_T_12145 = ~out_womask_1263; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1085 = {hi_891, flags_0_go, _out_prepend_T_1085}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12146 = out_prepend_1085; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12147 = _out_T_12146; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1086 = _out_T_12147; // @[RegisterRouter.scala:87:24] wire out_rimask_1264 = |_out_rimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_wimask_1264 = &_out_wimask_T_1264; // @[RegisterRouter.scala:87:24] wire out_romask_1264 = |_out_romask_T_1264; // @[RegisterRouter.scala:87:24] wire out_womask_1264 = &_out_womask_T_1264; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1264 = out_rivalid_1_1118 & out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12149 = out_f_rivalid_1264; // @[RegisterRouter.scala:87:24] wire out_f_roready_1264 = out_roready_1_1118 & out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12150 = out_f_roready_1264; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1264 = out_wivalid_1_1118 & out_wimask_1264; // @[RegisterRouter.scala:87:24] wire out_f_woready_1264 = out_woready_1_1118 & out_womask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12151 = ~out_rimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12152 = ~out_wimask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12153 = ~out_romask_1264; // @[RegisterRouter.scala:87:24] wire _out_T_12154 = ~out_womask_1264; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1086 = {hi_892, flags_0_go, _out_prepend_T_1086}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12155 = out_prepend_1086; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12156 = _out_T_12155; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1087 = _out_T_12156; // @[RegisterRouter.scala:87:24] wire out_rimask_1265 = |_out_rimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_wimask_1265 = &_out_wimask_T_1265; // @[RegisterRouter.scala:87:24] wire out_romask_1265 = |_out_romask_T_1265; // @[RegisterRouter.scala:87:24] wire out_womask_1265 = &_out_womask_T_1265; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1265 = out_rivalid_1_1119 & out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12158 = out_f_rivalid_1265; // @[RegisterRouter.scala:87:24] wire out_f_roready_1265 = out_roready_1_1119 & out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12159 = out_f_roready_1265; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1265 = out_wivalid_1_1119 & out_wimask_1265; // @[RegisterRouter.scala:87:24] wire out_f_woready_1265 = out_woready_1_1119 & out_womask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12160 = ~out_rimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12161 = ~out_wimask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12162 = ~out_romask_1265; // @[RegisterRouter.scala:87:24] wire _out_T_12163 = ~out_womask_1265; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1087 = {hi_893, flags_0_go, _out_prepend_T_1087}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12164 = out_prepend_1087; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12165 = _out_T_12164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1088 = _out_T_12165; // @[RegisterRouter.scala:87:24] wire out_rimask_1266 = |_out_rimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_wimask_1266 = &_out_wimask_T_1266; // @[RegisterRouter.scala:87:24] wire out_romask_1266 = |_out_romask_T_1266; // @[RegisterRouter.scala:87:24] wire out_womask_1266 = &_out_womask_T_1266; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1266 = out_rivalid_1_1120 & out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12167 = out_f_rivalid_1266; // @[RegisterRouter.scala:87:24] wire out_f_roready_1266 = out_roready_1_1120 & out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12168 = out_f_roready_1266; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1266 = out_wivalid_1_1120 & out_wimask_1266; // @[RegisterRouter.scala:87:24] wire out_f_woready_1266 = out_woready_1_1120 & out_womask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12169 = ~out_rimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12170 = ~out_wimask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12171 = ~out_romask_1266; // @[RegisterRouter.scala:87:24] wire _out_T_12172 = ~out_womask_1266; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1088 = {hi_894, flags_0_go, _out_prepend_T_1088}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12173 = out_prepend_1088; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12174 = _out_T_12173; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1089 = _out_T_12174; // @[RegisterRouter.scala:87:24] wire out_rimask_1267 = |_out_rimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_wimask_1267 = &_out_wimask_T_1267; // @[RegisterRouter.scala:87:24] wire out_romask_1267 = |_out_romask_T_1267; // @[RegisterRouter.scala:87:24] wire out_womask_1267 = &_out_womask_T_1267; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1267 = out_rivalid_1_1121 & out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12176 = out_f_rivalid_1267; // @[RegisterRouter.scala:87:24] wire out_f_roready_1267 = out_roready_1_1121 & out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12177 = out_f_roready_1267; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1267 = out_wivalid_1_1121 & out_wimask_1267; // @[RegisterRouter.scala:87:24] wire out_f_woready_1267 = out_woready_1_1121 & out_womask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12178 = ~out_rimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12179 = ~out_wimask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12180 = ~out_romask_1267; // @[RegisterRouter.scala:87:24] wire _out_T_12181 = ~out_womask_1267; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1089 = {hi_895, flags_0_go, _out_prepend_T_1089}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12182 = out_prepend_1089; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12183 = _out_T_12182; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1090 = _out_T_12183; // @[RegisterRouter.scala:87:24] wire out_rimask_1268 = |_out_rimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_wimask_1268 = &_out_wimask_T_1268; // @[RegisterRouter.scala:87:24] wire out_romask_1268 = |_out_romask_T_1268; // @[RegisterRouter.scala:87:24] wire out_womask_1268 = &_out_womask_T_1268; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1268 = out_rivalid_1_1122 & out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12185 = out_f_rivalid_1268; // @[RegisterRouter.scala:87:24] wire out_f_roready_1268 = out_roready_1_1122 & out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12186 = out_f_roready_1268; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1268 = out_wivalid_1_1122 & out_wimask_1268; // @[RegisterRouter.scala:87:24] wire out_f_woready_1268 = out_woready_1_1122 & out_womask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12187 = ~out_rimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12188 = ~out_wimask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12189 = ~out_romask_1268; // @[RegisterRouter.scala:87:24] wire _out_T_12190 = ~out_womask_1268; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1090 = {hi_896, flags_0_go, _out_prepend_T_1090}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12191 = out_prepend_1090; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12192 = _out_T_12191; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_239 = _out_T_12192; // @[MuxLiteral.scala:49:48] wire out_rimask_1269 = |_out_rimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_wimask_1269 = &_out_wimask_T_1269; // @[RegisterRouter.scala:87:24] wire out_romask_1269 = |_out_romask_T_1269; // @[RegisterRouter.scala:87:24] wire out_womask_1269 = &_out_womask_T_1269; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1269 = out_rivalid_1_1123 & out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12194 = out_f_rivalid_1269; // @[RegisterRouter.scala:87:24] wire out_f_roready_1269 = out_roready_1_1123 & out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12195 = out_f_roready_1269; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1269 = out_wivalid_1_1123 & out_wimask_1269; // @[RegisterRouter.scala:87:24] wire out_f_woready_1269 = out_woready_1_1123 & out_womask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12196 = ~out_rimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12197 = ~out_wimask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12198 = ~out_romask_1269; // @[RegisterRouter.scala:87:24] wire _out_T_12199 = ~out_womask_1269; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12201 = _out_T_12200; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1091 = _out_T_12201; // @[RegisterRouter.scala:87:24] wire out_rimask_1270 = |_out_rimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_wimask_1270 = &_out_wimask_T_1270; // @[RegisterRouter.scala:87:24] wire out_romask_1270 = |_out_romask_T_1270; // @[RegisterRouter.scala:87:24] wire out_womask_1270 = &_out_womask_T_1270; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1270 = out_rivalid_1_1124 & out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12203 = out_f_rivalid_1270; // @[RegisterRouter.scala:87:24] wire out_f_roready_1270 = out_roready_1_1124 & out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12204 = out_f_roready_1270; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1270 = out_wivalid_1_1124 & out_wimask_1270; // @[RegisterRouter.scala:87:24] wire out_f_woready_1270 = out_woready_1_1124 & out_womask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12205 = ~out_rimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12206 = ~out_wimask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12207 = ~out_romask_1270; // @[RegisterRouter.scala:87:24] wire _out_T_12208 = ~out_womask_1270; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1091 = {hi_914, flags_0_go, _out_prepend_T_1091}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12209 = out_prepend_1091; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12210 = _out_T_12209; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1092 = _out_T_12210; // @[RegisterRouter.scala:87:24] wire out_rimask_1271 = |_out_rimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_wimask_1271 = &_out_wimask_T_1271; // @[RegisterRouter.scala:87:24] wire out_romask_1271 = |_out_romask_T_1271; // @[RegisterRouter.scala:87:24] wire out_womask_1271 = &_out_womask_T_1271; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1271 = out_rivalid_1_1125 & out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12212 = out_f_rivalid_1271; // @[RegisterRouter.scala:87:24] wire out_f_roready_1271 = out_roready_1_1125 & out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12213 = out_f_roready_1271; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1271 = out_wivalid_1_1125 & out_wimask_1271; // @[RegisterRouter.scala:87:24] wire out_f_woready_1271 = out_woready_1_1125 & out_womask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12214 = ~out_rimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12215 = ~out_wimask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12216 = ~out_romask_1271; // @[RegisterRouter.scala:87:24] wire _out_T_12217 = ~out_womask_1271; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1092 = {hi_915, flags_0_go, _out_prepend_T_1092}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12218 = out_prepend_1092; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12219 = _out_T_12218; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1093 = _out_T_12219; // @[RegisterRouter.scala:87:24] wire out_rimask_1272 = |_out_rimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_wimask_1272 = &_out_wimask_T_1272; // @[RegisterRouter.scala:87:24] wire out_romask_1272 = |_out_romask_T_1272; // @[RegisterRouter.scala:87:24] wire out_womask_1272 = &_out_womask_T_1272; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1272 = out_rivalid_1_1126 & out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12221 = out_f_rivalid_1272; // @[RegisterRouter.scala:87:24] wire out_f_roready_1272 = out_roready_1_1126 & out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12222 = out_f_roready_1272; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1272 = out_wivalid_1_1126 & out_wimask_1272; // @[RegisterRouter.scala:87:24] wire out_f_woready_1272 = out_woready_1_1126 & out_womask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12223 = ~out_rimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12224 = ~out_wimask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12225 = ~out_romask_1272; // @[RegisterRouter.scala:87:24] wire _out_T_12226 = ~out_womask_1272; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1093 = {hi_916, flags_0_go, _out_prepend_T_1093}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12227 = out_prepend_1093; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12228 = _out_T_12227; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1094 = _out_T_12228; // @[RegisterRouter.scala:87:24] wire out_rimask_1273 = |_out_rimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_wimask_1273 = &_out_wimask_T_1273; // @[RegisterRouter.scala:87:24] wire out_romask_1273 = |_out_romask_T_1273; // @[RegisterRouter.scala:87:24] wire out_womask_1273 = &_out_womask_T_1273; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1273 = out_rivalid_1_1127 & out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12230 = out_f_rivalid_1273; // @[RegisterRouter.scala:87:24] wire out_f_roready_1273 = out_roready_1_1127 & out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12231 = out_f_roready_1273; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1273 = out_wivalid_1_1127 & out_wimask_1273; // @[RegisterRouter.scala:87:24] wire out_f_woready_1273 = out_woready_1_1127 & out_womask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12232 = ~out_rimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12233 = ~out_wimask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12234 = ~out_romask_1273; // @[RegisterRouter.scala:87:24] wire _out_T_12235 = ~out_womask_1273; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1094 = {hi_917, flags_0_go, _out_prepend_T_1094}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12236 = out_prepend_1094; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12237 = _out_T_12236; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1095 = _out_T_12237; // @[RegisterRouter.scala:87:24] wire out_rimask_1274 = |_out_rimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_wimask_1274 = &_out_wimask_T_1274; // @[RegisterRouter.scala:87:24] wire out_romask_1274 = |_out_romask_T_1274; // @[RegisterRouter.scala:87:24] wire out_womask_1274 = &_out_womask_T_1274; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1274 = out_rivalid_1_1128 & out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12239 = out_f_rivalid_1274; // @[RegisterRouter.scala:87:24] wire out_f_roready_1274 = out_roready_1_1128 & out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12240 = out_f_roready_1274; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1274 = out_wivalid_1_1128 & out_wimask_1274; // @[RegisterRouter.scala:87:24] wire out_f_woready_1274 = out_woready_1_1128 & out_womask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12241 = ~out_rimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12242 = ~out_wimask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12243 = ~out_romask_1274; // @[RegisterRouter.scala:87:24] wire _out_T_12244 = ~out_womask_1274; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1095 = {hi_918, flags_0_go, _out_prepend_T_1095}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12245 = out_prepend_1095; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12246 = _out_T_12245; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1096 = _out_T_12246; // @[RegisterRouter.scala:87:24] wire out_rimask_1275 = |_out_rimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_wimask_1275 = &_out_wimask_T_1275; // @[RegisterRouter.scala:87:24] wire out_romask_1275 = |_out_romask_T_1275; // @[RegisterRouter.scala:87:24] wire out_womask_1275 = &_out_womask_T_1275; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1275 = out_rivalid_1_1129 & out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12248 = out_f_rivalid_1275; // @[RegisterRouter.scala:87:24] wire out_f_roready_1275 = out_roready_1_1129 & out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12249 = out_f_roready_1275; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1275 = out_wivalid_1_1129 & out_wimask_1275; // @[RegisterRouter.scala:87:24] wire out_f_woready_1275 = out_woready_1_1129 & out_womask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12250 = ~out_rimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12251 = ~out_wimask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12252 = ~out_romask_1275; // @[RegisterRouter.scala:87:24] wire _out_T_12253 = ~out_womask_1275; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1096 = {hi_919, flags_0_go, _out_prepend_T_1096}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12254 = out_prepend_1096; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12255 = _out_T_12254; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1097 = _out_T_12255; // @[RegisterRouter.scala:87:24] wire out_rimask_1276 = |_out_rimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_wimask_1276 = &_out_wimask_T_1276; // @[RegisterRouter.scala:87:24] wire out_romask_1276 = |_out_romask_T_1276; // @[RegisterRouter.scala:87:24] wire out_womask_1276 = &_out_womask_T_1276; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1276 = out_rivalid_1_1130 & out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12257 = out_f_rivalid_1276; // @[RegisterRouter.scala:87:24] wire out_f_roready_1276 = out_roready_1_1130 & out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12258 = out_f_roready_1276; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1276 = out_wivalid_1_1130 & out_wimask_1276; // @[RegisterRouter.scala:87:24] wire out_f_woready_1276 = out_woready_1_1130 & out_womask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12259 = ~out_rimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12260 = ~out_wimask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12261 = ~out_romask_1276; // @[RegisterRouter.scala:87:24] wire _out_T_12262 = ~out_womask_1276; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1097 = {hi_920, flags_0_go, _out_prepend_T_1097}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12263 = out_prepend_1097; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12264 = _out_T_12263; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_242 = _out_T_12264; // @[MuxLiteral.scala:49:48] wire out_rimask_1277 = |_out_rimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_wimask_1277 = &_out_wimask_T_1277; // @[RegisterRouter.scala:87:24] wire out_romask_1277 = |_out_romask_T_1277; // @[RegisterRouter.scala:87:24] wire out_womask_1277 = &_out_womask_T_1277; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1277 = out_rivalid_1_1131 & out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12266 = out_f_rivalid_1277; // @[RegisterRouter.scala:87:24] wire out_f_roready_1277 = out_roready_1_1131 & out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12267 = out_f_roready_1277; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1277 = out_wivalid_1_1131 & out_wimask_1277; // @[RegisterRouter.scala:87:24] wire out_f_woready_1277 = out_woready_1_1131 & out_womask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12268 = ~out_rimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12269 = ~out_wimask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12270 = ~out_romask_1277; // @[RegisterRouter.scala:87:24] wire _out_T_12271 = ~out_womask_1277; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12273 = _out_T_12272; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1098 = _out_T_12273; // @[RegisterRouter.scala:87:24] wire out_rimask_1278 = |_out_rimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_wimask_1278 = &_out_wimask_T_1278; // @[RegisterRouter.scala:87:24] wire out_romask_1278 = |_out_romask_T_1278; // @[RegisterRouter.scala:87:24] wire out_womask_1278 = &_out_womask_T_1278; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1278 = out_rivalid_1_1132 & out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12275 = out_f_rivalid_1278; // @[RegisterRouter.scala:87:24] wire out_f_roready_1278 = out_roready_1_1132 & out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12276 = out_f_roready_1278; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1278 = out_wivalid_1_1132 & out_wimask_1278; // @[RegisterRouter.scala:87:24] wire out_f_woready_1278 = out_woready_1_1132 & out_womask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12277 = ~out_rimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12278 = ~out_wimask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12279 = ~out_romask_1278; // @[RegisterRouter.scala:87:24] wire _out_T_12280 = ~out_womask_1278; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1098 = {hi_26, flags_0_go, _out_prepend_T_1098}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12281 = out_prepend_1098; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12282 = _out_T_12281; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1099 = _out_T_12282; // @[RegisterRouter.scala:87:24] wire out_rimask_1279 = |_out_rimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_wimask_1279 = &_out_wimask_T_1279; // @[RegisterRouter.scala:87:24] wire out_romask_1279 = |_out_romask_T_1279; // @[RegisterRouter.scala:87:24] wire out_womask_1279 = &_out_womask_T_1279; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1279 = out_rivalid_1_1133 & out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12284 = out_f_rivalid_1279; // @[RegisterRouter.scala:87:24] wire out_f_roready_1279 = out_roready_1_1133 & out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12285 = out_f_roready_1279; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1279 = out_wivalid_1_1133 & out_wimask_1279; // @[RegisterRouter.scala:87:24] wire out_f_woready_1279 = out_woready_1_1133 & out_womask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12286 = ~out_rimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12287 = ~out_wimask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12288 = ~out_romask_1279; // @[RegisterRouter.scala:87:24] wire _out_T_12289 = ~out_womask_1279; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1099 = {hi_27, flags_0_go, _out_prepend_T_1099}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12290 = out_prepend_1099; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12291 = _out_T_12290; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1100 = _out_T_12291; // @[RegisterRouter.scala:87:24] wire out_rimask_1280 = |_out_rimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_wimask_1280 = &_out_wimask_T_1280; // @[RegisterRouter.scala:87:24] wire out_romask_1280 = |_out_romask_T_1280; // @[RegisterRouter.scala:87:24] wire out_womask_1280 = &_out_womask_T_1280; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1280 = out_rivalid_1_1134 & out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12293 = out_f_rivalid_1280; // @[RegisterRouter.scala:87:24] wire out_f_roready_1280 = out_roready_1_1134 & out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12294 = out_f_roready_1280; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1280 = out_wivalid_1_1134 & out_wimask_1280; // @[RegisterRouter.scala:87:24] wire out_f_woready_1280 = out_woready_1_1134 & out_womask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12295 = ~out_rimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12296 = ~out_wimask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12297 = ~out_romask_1280; // @[RegisterRouter.scala:87:24] wire _out_T_12298 = ~out_womask_1280; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1100 = {hi_28, flags_0_go, _out_prepend_T_1100}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12299 = out_prepend_1100; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12300 = _out_T_12299; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1101 = _out_T_12300; // @[RegisterRouter.scala:87:24] wire out_rimask_1281 = |_out_rimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_wimask_1281 = &_out_wimask_T_1281; // @[RegisterRouter.scala:87:24] wire out_romask_1281 = |_out_romask_T_1281; // @[RegisterRouter.scala:87:24] wire out_womask_1281 = &_out_womask_T_1281; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1281 = out_rivalid_1_1135 & out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12302 = out_f_rivalid_1281; // @[RegisterRouter.scala:87:24] wire out_f_roready_1281 = out_roready_1_1135 & out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12303 = out_f_roready_1281; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1281 = out_wivalid_1_1135 & out_wimask_1281; // @[RegisterRouter.scala:87:24] wire out_f_woready_1281 = out_woready_1_1135 & out_womask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12304 = ~out_rimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12305 = ~out_wimask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12306 = ~out_romask_1281; // @[RegisterRouter.scala:87:24] wire _out_T_12307 = ~out_womask_1281; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1101 = {hi_29, flags_0_go, _out_prepend_T_1101}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12308 = out_prepend_1101; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12309 = _out_T_12308; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1102 = _out_T_12309; // @[RegisterRouter.scala:87:24] wire out_rimask_1282 = |_out_rimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_wimask_1282 = &_out_wimask_T_1282; // @[RegisterRouter.scala:87:24] wire out_romask_1282 = |_out_romask_T_1282; // @[RegisterRouter.scala:87:24] wire out_womask_1282 = &_out_womask_T_1282; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1282 = out_rivalid_1_1136 & out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12311 = out_f_rivalid_1282; // @[RegisterRouter.scala:87:24] wire out_f_roready_1282 = out_roready_1_1136 & out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12312 = out_f_roready_1282; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1282 = out_wivalid_1_1136 & out_wimask_1282; // @[RegisterRouter.scala:87:24] wire out_f_woready_1282 = out_woready_1_1136 & out_womask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12313 = ~out_rimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12314 = ~out_wimask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12315 = ~out_romask_1282; // @[RegisterRouter.scala:87:24] wire _out_T_12316 = ~out_womask_1282; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1102 = {hi_30, flags_0_go, _out_prepend_T_1102}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12317 = out_prepend_1102; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12318 = _out_T_12317; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1103 = _out_T_12318; // @[RegisterRouter.scala:87:24] wire out_rimask_1283 = |_out_rimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_wimask_1283 = &_out_wimask_T_1283; // @[RegisterRouter.scala:87:24] wire out_romask_1283 = |_out_romask_T_1283; // @[RegisterRouter.scala:87:24] wire out_womask_1283 = &_out_womask_T_1283; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1283 = out_rivalid_1_1137 & out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12320 = out_f_rivalid_1283; // @[RegisterRouter.scala:87:24] wire out_f_roready_1283 = out_roready_1_1137 & out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12321 = out_f_roready_1283; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1283 = out_wivalid_1_1137 & out_wimask_1283; // @[RegisterRouter.scala:87:24] wire out_f_woready_1283 = out_woready_1_1137 & out_womask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12322 = ~out_rimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12323 = ~out_wimask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12324 = ~out_romask_1283; // @[RegisterRouter.scala:87:24] wire _out_T_12325 = ~out_womask_1283; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1103 = {hi_31, flags_0_go, _out_prepend_T_1103}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12326 = out_prepend_1103; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12327 = _out_T_12326; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1104 = _out_T_12327; // @[RegisterRouter.scala:87:24] wire out_rimask_1284 = |_out_rimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_wimask_1284 = &_out_wimask_T_1284; // @[RegisterRouter.scala:87:24] wire out_romask_1284 = |_out_romask_T_1284; // @[RegisterRouter.scala:87:24] wire out_womask_1284 = &_out_womask_T_1284; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1284 = out_rivalid_1_1138 & out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12329 = out_f_rivalid_1284; // @[RegisterRouter.scala:87:24] wire out_f_roready_1284 = out_roready_1_1138 & out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12330 = out_f_roready_1284; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1284 = out_wivalid_1_1138 & out_wimask_1284; // @[RegisterRouter.scala:87:24] wire out_f_woready_1284 = out_woready_1_1138 & out_womask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12331 = ~out_rimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12332 = ~out_wimask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12333 = ~out_romask_1284; // @[RegisterRouter.scala:87:24] wire _out_T_12334 = ~out_womask_1284; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1104 = {hi_32, flags_0_go, _out_prepend_T_1104}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12335 = out_prepend_1104; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12336 = _out_T_12335; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_131 = _out_T_12336; // @[MuxLiteral.scala:49:48] wire out_rimask_1285 = |_out_rimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_wimask_1285 = &_out_wimask_T_1285; // @[RegisterRouter.scala:87:24] wire out_romask_1285 = |_out_romask_T_1285; // @[RegisterRouter.scala:87:24] wire out_womask_1285 = &_out_womask_T_1285; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1285 = out_rivalid_1_1139 & out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12338 = out_f_rivalid_1285; // @[RegisterRouter.scala:87:24] wire out_f_roready_1285 = out_roready_1_1139 & out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12339 = out_f_roready_1285; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1285 = out_wivalid_1_1139 & out_wimask_1285; // @[RegisterRouter.scala:87:24] wire out_f_woready_1285 = out_woready_1_1139 & out_womask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12340 = ~out_rimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12341 = ~out_wimask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12342 = ~out_romask_1285; // @[RegisterRouter.scala:87:24] wire _out_T_12343 = ~out_womask_1285; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12345 = _out_T_12344; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1105 = _out_T_12345; // @[RegisterRouter.scala:87:24] wire out_rimask_1286 = |_out_rimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_wimask_1286 = &_out_wimask_T_1286; // @[RegisterRouter.scala:87:24] wire out_romask_1286 = |_out_romask_T_1286; // @[RegisterRouter.scala:87:24] wire out_womask_1286 = &_out_womask_T_1286; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1286 = out_rivalid_1_1140 & out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12347 = out_f_rivalid_1286; // @[RegisterRouter.scala:87:24] wire out_f_roready_1286 = out_roready_1_1140 & out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12348 = out_f_roready_1286; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1286 = out_wivalid_1_1140 & out_wimask_1286; // @[RegisterRouter.scala:87:24] wire out_f_woready_1286 = out_woready_1_1140 & out_womask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12349 = ~out_rimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12350 = ~out_wimask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12351 = ~out_romask_1286; // @[RegisterRouter.scala:87:24] wire _out_T_12352 = ~out_womask_1286; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1105 = {hi_402, flags_0_go, _out_prepend_T_1105}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12353 = out_prepend_1105; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12354 = _out_T_12353; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1106 = _out_T_12354; // @[RegisterRouter.scala:87:24] wire out_rimask_1287 = |_out_rimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_wimask_1287 = &_out_wimask_T_1287; // @[RegisterRouter.scala:87:24] wire out_romask_1287 = |_out_romask_T_1287; // @[RegisterRouter.scala:87:24] wire out_womask_1287 = &_out_womask_T_1287; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1287 = out_rivalid_1_1141 & out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12356 = out_f_rivalid_1287; // @[RegisterRouter.scala:87:24] wire out_f_roready_1287 = out_roready_1_1141 & out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12357 = out_f_roready_1287; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1287 = out_wivalid_1_1141 & out_wimask_1287; // @[RegisterRouter.scala:87:24] wire out_f_woready_1287 = out_woready_1_1141 & out_womask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12358 = ~out_rimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12359 = ~out_wimask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12360 = ~out_romask_1287; // @[RegisterRouter.scala:87:24] wire _out_T_12361 = ~out_womask_1287; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1106 = {hi_403, flags_0_go, _out_prepend_T_1106}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12362 = out_prepend_1106; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12363 = _out_T_12362; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1107 = _out_T_12363; // @[RegisterRouter.scala:87:24] wire out_rimask_1288 = |_out_rimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_wimask_1288 = &_out_wimask_T_1288; // @[RegisterRouter.scala:87:24] wire out_romask_1288 = |_out_romask_T_1288; // @[RegisterRouter.scala:87:24] wire out_womask_1288 = &_out_womask_T_1288; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1288 = out_rivalid_1_1142 & out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12365 = out_f_rivalid_1288; // @[RegisterRouter.scala:87:24] wire out_f_roready_1288 = out_roready_1_1142 & out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12366 = out_f_roready_1288; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1288 = out_wivalid_1_1142 & out_wimask_1288; // @[RegisterRouter.scala:87:24] wire out_f_woready_1288 = out_woready_1_1142 & out_womask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12367 = ~out_rimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12368 = ~out_wimask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12369 = ~out_romask_1288; // @[RegisterRouter.scala:87:24] wire _out_T_12370 = ~out_womask_1288; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1107 = {hi_404, flags_0_go, _out_prepend_T_1107}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12371 = out_prepend_1107; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12372 = _out_T_12371; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1108 = _out_T_12372; // @[RegisterRouter.scala:87:24] wire out_rimask_1289 = |_out_rimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_wimask_1289 = &_out_wimask_T_1289; // @[RegisterRouter.scala:87:24] wire out_romask_1289 = |_out_romask_T_1289; // @[RegisterRouter.scala:87:24] wire out_womask_1289 = &_out_womask_T_1289; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1289 = out_rivalid_1_1143 & out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12374 = out_f_rivalid_1289; // @[RegisterRouter.scala:87:24] wire out_f_roready_1289 = out_roready_1_1143 & out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12375 = out_f_roready_1289; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1289 = out_wivalid_1_1143 & out_wimask_1289; // @[RegisterRouter.scala:87:24] wire out_f_woready_1289 = out_woready_1_1143 & out_womask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12376 = ~out_rimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12377 = ~out_wimask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12378 = ~out_romask_1289; // @[RegisterRouter.scala:87:24] wire _out_T_12379 = ~out_womask_1289; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1108 = {hi_405, flags_0_go, _out_prepend_T_1108}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12380 = out_prepend_1108; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12381 = _out_T_12380; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1109 = _out_T_12381; // @[RegisterRouter.scala:87:24] wire out_rimask_1290 = |_out_rimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_wimask_1290 = &_out_wimask_T_1290; // @[RegisterRouter.scala:87:24] wire out_romask_1290 = |_out_romask_T_1290; // @[RegisterRouter.scala:87:24] wire out_womask_1290 = &_out_womask_T_1290; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1290 = out_rivalid_1_1144 & out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12383 = out_f_rivalid_1290; // @[RegisterRouter.scala:87:24] wire out_f_roready_1290 = out_roready_1_1144 & out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12384 = out_f_roready_1290; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1290 = out_wivalid_1_1144 & out_wimask_1290; // @[RegisterRouter.scala:87:24] wire out_f_woready_1290 = out_woready_1_1144 & out_womask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12385 = ~out_rimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12386 = ~out_wimask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12387 = ~out_romask_1290; // @[RegisterRouter.scala:87:24] wire _out_T_12388 = ~out_womask_1290; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1109 = {hi_406, flags_0_go, _out_prepend_T_1109}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12389 = out_prepend_1109; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12390 = _out_T_12389; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1110 = _out_T_12390; // @[RegisterRouter.scala:87:24] wire out_rimask_1291 = |_out_rimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_wimask_1291 = &_out_wimask_T_1291; // @[RegisterRouter.scala:87:24] wire out_romask_1291 = |_out_romask_T_1291; // @[RegisterRouter.scala:87:24] wire out_womask_1291 = &_out_womask_T_1291; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1291 = out_rivalid_1_1145 & out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12392 = out_f_rivalid_1291; // @[RegisterRouter.scala:87:24] wire out_f_roready_1291 = out_roready_1_1145 & out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12393 = out_f_roready_1291; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1291 = out_wivalid_1_1145 & out_wimask_1291; // @[RegisterRouter.scala:87:24] wire out_f_woready_1291 = out_woready_1_1145 & out_womask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12394 = ~out_rimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12395 = ~out_wimask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12396 = ~out_romask_1291; // @[RegisterRouter.scala:87:24] wire _out_T_12397 = ~out_womask_1291; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1110 = {hi_407, flags_0_go, _out_prepend_T_1110}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12398 = out_prepend_1110; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12399 = _out_T_12398; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1111 = _out_T_12399; // @[RegisterRouter.scala:87:24] wire out_rimask_1292 = |_out_rimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_wimask_1292 = &_out_wimask_T_1292; // @[RegisterRouter.scala:87:24] wire out_romask_1292 = |_out_romask_T_1292; // @[RegisterRouter.scala:87:24] wire out_womask_1292 = &_out_womask_T_1292; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1292 = out_rivalid_1_1146 & out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12401 = out_f_rivalid_1292; // @[RegisterRouter.scala:87:24] wire out_f_roready_1292 = out_roready_1_1146 & out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12402 = out_f_roready_1292; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1292 = out_wivalid_1_1146 & out_wimask_1292; // @[RegisterRouter.scala:87:24] wire out_f_woready_1292 = out_woready_1_1146 & out_womask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12403 = ~out_rimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12404 = ~out_wimask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12405 = ~out_romask_1292; // @[RegisterRouter.scala:87:24] wire _out_T_12406 = ~out_womask_1292; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1111 = {hi_408, flags_0_go, _out_prepend_T_1111}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12407 = out_prepend_1111; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12408 = _out_T_12407; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_178 = _out_T_12408; // @[MuxLiteral.scala:49:48] wire out_rimask_1293 = |_out_rimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_wimask_1293 = &_out_wimask_T_1293; // @[RegisterRouter.scala:87:24] wire out_romask_1293 = |_out_romask_T_1293; // @[RegisterRouter.scala:87:24] wire out_womask_1293 = &_out_womask_T_1293; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1293 = out_rivalid_1_1147 & out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12410 = out_f_rivalid_1293; // @[RegisterRouter.scala:87:24] wire out_f_roready_1293 = out_roready_1_1147 & out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12411 = out_f_roready_1293; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1293 = out_wivalid_1_1147 & out_wimask_1293; // @[RegisterRouter.scala:87:24] wire out_f_woready_1293 = out_woready_1_1147 & out_womask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12412 = ~out_rimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12413 = ~out_wimask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12414 = ~out_romask_1293; // @[RegisterRouter.scala:87:24] wire _out_T_12415 = ~out_womask_1293; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12417 = _out_T_12416; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1112 = _out_T_12417; // @[RegisterRouter.scala:87:24] wire out_rimask_1294 = |_out_rimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_wimask_1294 = &_out_wimask_T_1294; // @[RegisterRouter.scala:87:24] wire out_romask_1294 = |_out_romask_T_1294; // @[RegisterRouter.scala:87:24] wire out_womask_1294 = &_out_womask_T_1294; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1294 = out_rivalid_1_1148 & out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12419 = out_f_rivalid_1294; // @[RegisterRouter.scala:87:24] wire out_f_roready_1294 = out_roready_1_1148 & out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12420 = out_f_roready_1294; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1294 = out_wivalid_1_1148 & out_wimask_1294; // @[RegisterRouter.scala:87:24] wire out_f_woready_1294 = out_woready_1_1148 & out_womask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12421 = ~out_rimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12422 = ~out_wimask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12423 = ~out_romask_1294; // @[RegisterRouter.scala:87:24] wire _out_T_12424 = ~out_womask_1294; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1112 = {hi_282, flags_0_go, _out_prepend_T_1112}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12425 = out_prepend_1112; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12426 = _out_T_12425; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1113 = _out_T_12426; // @[RegisterRouter.scala:87:24] wire out_rimask_1295 = |_out_rimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_wimask_1295 = &_out_wimask_T_1295; // @[RegisterRouter.scala:87:24] wire out_romask_1295 = |_out_romask_T_1295; // @[RegisterRouter.scala:87:24] wire out_womask_1295 = &_out_womask_T_1295; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1295 = out_rivalid_1_1149 & out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12428 = out_f_rivalid_1295; // @[RegisterRouter.scala:87:24] wire out_f_roready_1295 = out_roready_1_1149 & out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12429 = out_f_roready_1295; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1295 = out_wivalid_1_1149 & out_wimask_1295; // @[RegisterRouter.scala:87:24] wire out_f_woready_1295 = out_woready_1_1149 & out_womask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12430 = ~out_rimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12431 = ~out_wimask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12432 = ~out_romask_1295; // @[RegisterRouter.scala:87:24] wire _out_T_12433 = ~out_womask_1295; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1113 = {hi_283, flags_0_go, _out_prepend_T_1113}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12434 = out_prepend_1113; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12435 = _out_T_12434; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1114 = _out_T_12435; // @[RegisterRouter.scala:87:24] wire out_rimask_1296 = |_out_rimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_wimask_1296 = &_out_wimask_T_1296; // @[RegisterRouter.scala:87:24] wire out_romask_1296 = |_out_romask_T_1296; // @[RegisterRouter.scala:87:24] wire out_womask_1296 = &_out_womask_T_1296; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1296 = out_rivalid_1_1150 & out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12437 = out_f_rivalid_1296; // @[RegisterRouter.scala:87:24] wire out_f_roready_1296 = out_roready_1_1150 & out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12438 = out_f_roready_1296; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1296 = out_wivalid_1_1150 & out_wimask_1296; // @[RegisterRouter.scala:87:24] wire out_f_woready_1296 = out_woready_1_1150 & out_womask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12439 = ~out_rimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12440 = ~out_wimask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12441 = ~out_romask_1296; // @[RegisterRouter.scala:87:24] wire _out_T_12442 = ~out_womask_1296; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1114 = {hi_284, flags_0_go, _out_prepend_T_1114}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12443 = out_prepend_1114; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12444 = _out_T_12443; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1115 = _out_T_12444; // @[RegisterRouter.scala:87:24] wire out_rimask_1297 = |_out_rimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_wimask_1297 = &_out_wimask_T_1297; // @[RegisterRouter.scala:87:24] wire out_romask_1297 = |_out_romask_T_1297; // @[RegisterRouter.scala:87:24] wire out_womask_1297 = &_out_womask_T_1297; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1297 = out_rivalid_1_1151 & out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12446 = out_f_rivalid_1297; // @[RegisterRouter.scala:87:24] wire out_f_roready_1297 = out_roready_1_1151 & out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12447 = out_f_roready_1297; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1297 = out_wivalid_1_1151 & out_wimask_1297; // @[RegisterRouter.scala:87:24] wire out_f_woready_1297 = out_woready_1_1151 & out_womask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12448 = ~out_rimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12449 = ~out_wimask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12450 = ~out_romask_1297; // @[RegisterRouter.scala:87:24] wire _out_T_12451 = ~out_womask_1297; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1115 = {hi_285, flags_0_go, _out_prepend_T_1115}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12452 = out_prepend_1115; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12453 = _out_T_12452; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1116 = _out_T_12453; // @[RegisterRouter.scala:87:24] wire out_rimask_1298 = |_out_rimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_wimask_1298 = &_out_wimask_T_1298; // @[RegisterRouter.scala:87:24] wire out_romask_1298 = |_out_romask_T_1298; // @[RegisterRouter.scala:87:24] wire out_womask_1298 = &_out_womask_T_1298; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1298 = out_rivalid_1_1152 & out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12455 = out_f_rivalid_1298; // @[RegisterRouter.scala:87:24] wire out_f_roready_1298 = out_roready_1_1152 & out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12456 = out_f_roready_1298; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1298 = out_wivalid_1_1152 & out_wimask_1298; // @[RegisterRouter.scala:87:24] wire out_f_woready_1298 = out_woready_1_1152 & out_womask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12457 = ~out_rimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12458 = ~out_wimask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12459 = ~out_romask_1298; // @[RegisterRouter.scala:87:24] wire _out_T_12460 = ~out_womask_1298; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1116 = {hi_286, flags_0_go, _out_prepend_T_1116}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12461 = out_prepend_1116; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12462 = _out_T_12461; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1117 = _out_T_12462; // @[RegisterRouter.scala:87:24] wire out_rimask_1299 = |_out_rimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_wimask_1299 = &_out_wimask_T_1299; // @[RegisterRouter.scala:87:24] wire out_romask_1299 = |_out_romask_T_1299; // @[RegisterRouter.scala:87:24] wire out_womask_1299 = &_out_womask_T_1299; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1299 = out_rivalid_1_1153 & out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12464 = out_f_rivalid_1299; // @[RegisterRouter.scala:87:24] wire out_f_roready_1299 = out_roready_1_1153 & out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12465 = out_f_roready_1299; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1299 = out_wivalid_1_1153 & out_wimask_1299; // @[RegisterRouter.scala:87:24] wire out_f_woready_1299 = out_woready_1_1153 & out_womask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12466 = ~out_rimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12467 = ~out_wimask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12468 = ~out_romask_1299; // @[RegisterRouter.scala:87:24] wire _out_T_12469 = ~out_womask_1299; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1117 = {hi_287, flags_0_go, _out_prepend_T_1117}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12470 = out_prepend_1117; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12471 = _out_T_12470; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1118 = _out_T_12471; // @[RegisterRouter.scala:87:24] wire out_rimask_1300 = |_out_rimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_wimask_1300 = &_out_wimask_T_1300; // @[RegisterRouter.scala:87:24] wire out_romask_1300 = |_out_romask_T_1300; // @[RegisterRouter.scala:87:24] wire out_womask_1300 = &_out_womask_T_1300; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1300 = out_rivalid_1_1154 & out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12473 = out_f_rivalid_1300; // @[RegisterRouter.scala:87:24] wire out_f_roready_1300 = out_roready_1_1154 & out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12474 = out_f_roready_1300; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1300 = out_wivalid_1_1154 & out_wimask_1300; // @[RegisterRouter.scala:87:24] wire out_f_woready_1300 = out_woready_1_1154 & out_womask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12475 = ~out_rimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12476 = ~out_wimask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12477 = ~out_romask_1300; // @[RegisterRouter.scala:87:24] wire _out_T_12478 = ~out_womask_1300; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1118 = {hi_288, flags_0_go, _out_prepend_T_1118}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12479 = out_prepend_1118; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12480 = _out_T_12479; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_163 = _out_T_12480; // @[MuxLiteral.scala:49:48] wire out_rimask_1301 = |_out_rimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_wimask_1301 = &_out_wimask_T_1301; // @[RegisterRouter.scala:87:24] wire out_romask_1301 = |_out_romask_T_1301; // @[RegisterRouter.scala:87:24] wire out_womask_1301 = &_out_womask_T_1301; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1301 = out_rivalid_1_1155 & out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12482 = out_f_rivalid_1301; // @[RegisterRouter.scala:87:24] wire out_f_roready_1301 = out_roready_1_1155 & out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12483 = out_f_roready_1301; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1301 = out_wivalid_1_1155 & out_wimask_1301; // @[RegisterRouter.scala:87:24] wire out_f_woready_1301 = out_woready_1_1155 & out_womask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12484 = ~out_rimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12485 = ~out_wimask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12486 = ~out_romask_1301; // @[RegisterRouter.scala:87:24] wire _out_T_12487 = ~out_womask_1301; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12489 = _out_T_12488; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1119 = _out_T_12489; // @[RegisterRouter.scala:87:24] wire out_rimask_1302 = |_out_rimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_wimask_1302 = &_out_wimask_T_1302; // @[RegisterRouter.scala:87:24] wire out_romask_1302 = |_out_romask_T_1302; // @[RegisterRouter.scala:87:24] wire out_womask_1302 = &_out_womask_T_1302; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1302 = out_rivalid_1_1156 & out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12491 = out_f_rivalid_1302; // @[RegisterRouter.scala:87:24] wire out_f_roready_1302 = out_roready_1_1156 & out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12492 = out_f_roready_1302; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1302 = out_wivalid_1_1156 & out_wimask_1302; // @[RegisterRouter.scala:87:24] wire out_f_woready_1302 = out_woready_1_1156 & out_womask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12493 = ~out_rimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12494 = ~out_wimask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12495 = ~out_romask_1302; // @[RegisterRouter.scala:87:24] wire _out_T_12496 = ~out_womask_1302; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1119 = {hi_578, flags_0_go, _out_prepend_T_1119}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12497 = out_prepend_1119; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12498 = _out_T_12497; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1120 = _out_T_12498; // @[RegisterRouter.scala:87:24] wire out_rimask_1303 = |_out_rimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_wimask_1303 = &_out_wimask_T_1303; // @[RegisterRouter.scala:87:24] wire out_romask_1303 = |_out_romask_T_1303; // @[RegisterRouter.scala:87:24] wire out_womask_1303 = &_out_womask_T_1303; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1303 = out_rivalid_1_1157 & out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12500 = out_f_rivalid_1303; // @[RegisterRouter.scala:87:24] wire out_f_roready_1303 = out_roready_1_1157 & out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12501 = out_f_roready_1303; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1303 = out_wivalid_1_1157 & out_wimask_1303; // @[RegisterRouter.scala:87:24] wire out_f_woready_1303 = out_woready_1_1157 & out_womask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12502 = ~out_rimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12503 = ~out_wimask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12504 = ~out_romask_1303; // @[RegisterRouter.scala:87:24] wire _out_T_12505 = ~out_womask_1303; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1120 = {hi_579, flags_0_go, _out_prepend_T_1120}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12506 = out_prepend_1120; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12507 = _out_T_12506; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1121 = _out_T_12507; // @[RegisterRouter.scala:87:24] wire out_rimask_1304 = |_out_rimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_wimask_1304 = &_out_wimask_T_1304; // @[RegisterRouter.scala:87:24] wire out_romask_1304 = |_out_romask_T_1304; // @[RegisterRouter.scala:87:24] wire out_womask_1304 = &_out_womask_T_1304; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1304 = out_rivalid_1_1158 & out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12509 = out_f_rivalid_1304; // @[RegisterRouter.scala:87:24] wire out_f_roready_1304 = out_roready_1_1158 & out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12510 = out_f_roready_1304; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1304 = out_wivalid_1_1158 & out_wimask_1304; // @[RegisterRouter.scala:87:24] wire out_f_woready_1304 = out_woready_1_1158 & out_womask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12511 = ~out_rimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12512 = ~out_wimask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12513 = ~out_romask_1304; // @[RegisterRouter.scala:87:24] wire _out_T_12514 = ~out_womask_1304; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1121 = {hi_580, flags_0_go, _out_prepend_T_1121}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12515 = out_prepend_1121; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12516 = _out_T_12515; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1122 = _out_T_12516; // @[RegisterRouter.scala:87:24] wire out_rimask_1305 = |_out_rimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_wimask_1305 = &_out_wimask_T_1305; // @[RegisterRouter.scala:87:24] wire out_romask_1305 = |_out_romask_T_1305; // @[RegisterRouter.scala:87:24] wire out_womask_1305 = &_out_womask_T_1305; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1305 = out_rivalid_1_1159 & out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12518 = out_f_rivalid_1305; // @[RegisterRouter.scala:87:24] wire out_f_roready_1305 = out_roready_1_1159 & out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12519 = out_f_roready_1305; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1305 = out_wivalid_1_1159 & out_wimask_1305; // @[RegisterRouter.scala:87:24] wire out_f_woready_1305 = out_woready_1_1159 & out_womask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12520 = ~out_rimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12521 = ~out_wimask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12522 = ~out_romask_1305; // @[RegisterRouter.scala:87:24] wire _out_T_12523 = ~out_womask_1305; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1122 = {hi_581, flags_0_go, _out_prepend_T_1122}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12524 = out_prepend_1122; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12525 = _out_T_12524; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1123 = _out_T_12525; // @[RegisterRouter.scala:87:24] wire out_rimask_1306 = |_out_rimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_wimask_1306 = &_out_wimask_T_1306; // @[RegisterRouter.scala:87:24] wire out_romask_1306 = |_out_romask_T_1306; // @[RegisterRouter.scala:87:24] wire out_womask_1306 = &_out_womask_T_1306; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1306 = out_rivalid_1_1160 & out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12527 = out_f_rivalid_1306; // @[RegisterRouter.scala:87:24] wire out_f_roready_1306 = out_roready_1_1160 & out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12528 = out_f_roready_1306; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1306 = out_wivalid_1_1160 & out_wimask_1306; // @[RegisterRouter.scala:87:24] wire out_f_woready_1306 = out_woready_1_1160 & out_womask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12529 = ~out_rimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12530 = ~out_wimask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12531 = ~out_romask_1306; // @[RegisterRouter.scala:87:24] wire _out_T_12532 = ~out_womask_1306; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1123 = {hi_582, flags_0_go, _out_prepend_T_1123}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12533 = out_prepend_1123; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12534 = _out_T_12533; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1124 = _out_T_12534; // @[RegisterRouter.scala:87:24] wire out_rimask_1307 = |_out_rimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_wimask_1307 = &_out_wimask_T_1307; // @[RegisterRouter.scala:87:24] wire out_romask_1307 = |_out_romask_T_1307; // @[RegisterRouter.scala:87:24] wire out_womask_1307 = &_out_womask_T_1307; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1307 = out_rivalid_1_1161 & out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12536 = out_f_rivalid_1307; // @[RegisterRouter.scala:87:24] wire out_f_roready_1307 = out_roready_1_1161 & out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12537 = out_f_roready_1307; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1307 = out_wivalid_1_1161 & out_wimask_1307; // @[RegisterRouter.scala:87:24] wire out_f_woready_1307 = out_woready_1_1161 & out_womask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12538 = ~out_rimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12539 = ~out_wimask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12540 = ~out_romask_1307; // @[RegisterRouter.scala:87:24] wire _out_T_12541 = ~out_womask_1307; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1124 = {hi_583, flags_0_go, _out_prepend_T_1124}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12542 = out_prepend_1124; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12543 = _out_T_12542; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1125 = _out_T_12543; // @[RegisterRouter.scala:87:24] wire out_rimask_1308 = |_out_rimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_wimask_1308 = &_out_wimask_T_1308; // @[RegisterRouter.scala:87:24] wire out_romask_1308 = |_out_romask_T_1308; // @[RegisterRouter.scala:87:24] wire out_womask_1308 = &_out_womask_T_1308; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1308 = out_rivalid_1_1162 & out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12545 = out_f_rivalid_1308; // @[RegisterRouter.scala:87:24] wire out_f_roready_1308 = out_roready_1_1162 & out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12546 = out_f_roready_1308; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1308 = out_wivalid_1_1162 & out_wimask_1308; // @[RegisterRouter.scala:87:24] wire out_f_woready_1308 = out_woready_1_1162 & out_womask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12547 = ~out_rimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12548 = ~out_wimask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12549 = ~out_romask_1308; // @[RegisterRouter.scala:87:24] wire _out_T_12550 = ~out_womask_1308; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1125 = {hi_584, flags_0_go, _out_prepend_T_1125}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12551 = out_prepend_1125; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12552 = _out_T_12551; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_200 = _out_T_12552; // @[MuxLiteral.scala:49:48] wire out_rimask_1309 = |_out_rimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_wimask_1309 = &_out_wimask_T_1309; // @[RegisterRouter.scala:87:24] wire out_romask_1309 = |_out_romask_T_1309; // @[RegisterRouter.scala:87:24] wire out_womask_1309 = &_out_womask_T_1309; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1309 = out_rivalid_1_1163 & out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12554 = out_f_rivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_roready_1309 = out_roready_1_1163 & out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12555 = out_f_roready_1309; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1309 = out_wivalid_1_1163 & out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12556 = out_f_wivalid_1309; // @[RegisterRouter.scala:87:24] wire out_f_woready_1309 = out_woready_1_1163 & out_womask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12557 = out_f_woready_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12558 = ~out_rimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12559 = ~out_wimask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12560 = ~out_romask_1309; // @[RegisterRouter.scala:87:24] wire _out_T_12561 = ~out_womask_1309; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12563 = _out_T_12562; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1126 = _out_T_12563; // @[RegisterRouter.scala:87:24] wire out_rimask_1310 = |_out_rimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_wimask_1310 = &_out_wimask_T_1310; // @[RegisterRouter.scala:87:24] wire out_romask_1310 = |_out_romask_T_1310; // @[RegisterRouter.scala:87:24] wire out_womask_1310 = &_out_womask_T_1310; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1310 = out_rivalid_1_1164 & out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12565 = out_f_rivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_roready_1310 = out_roready_1_1164 & out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12566 = out_f_roready_1310; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1310 = out_wivalid_1_1164 & out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12567 = out_f_wivalid_1310; // @[RegisterRouter.scala:87:24] wire out_f_woready_1310 = out_woready_1_1164 & out_womask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12568 = out_f_woready_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12569 = ~out_rimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12570 = ~out_wimask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12571 = ~out_romask_1310; // @[RegisterRouter.scala:87:24] wire _out_T_12572 = ~out_womask_1310; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1126 = {programBufferMem_57, _out_prepend_T_1126}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12573 = out_prepend_1126; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12574 = _out_T_12573; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1127 = _out_T_12574; // @[RegisterRouter.scala:87:24] wire out_rimask_1311 = |_out_rimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_wimask_1311 = &_out_wimask_T_1311; // @[RegisterRouter.scala:87:24] wire out_romask_1311 = |_out_romask_T_1311; // @[RegisterRouter.scala:87:24] wire out_womask_1311 = &_out_womask_T_1311; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1311 = out_rivalid_1_1165 & out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12576 = out_f_rivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_roready_1311 = out_roready_1_1165 & out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12577 = out_f_roready_1311; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1311 = out_wivalid_1_1165 & out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12578 = out_f_wivalid_1311; // @[RegisterRouter.scala:87:24] wire out_f_woready_1311 = out_woready_1_1165 & out_womask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12579 = out_f_woready_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12580 = ~out_rimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12581 = ~out_wimask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12582 = ~out_romask_1311; // @[RegisterRouter.scala:87:24] wire _out_T_12583 = ~out_womask_1311; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1127 = {programBufferMem_58, _out_prepend_T_1127}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12584 = out_prepend_1127; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12585 = _out_T_12584; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1128 = _out_T_12585; // @[RegisterRouter.scala:87:24] wire out_rimask_1312 = |_out_rimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_wimask_1312 = &_out_wimask_T_1312; // @[RegisterRouter.scala:87:24] wire out_romask_1312 = |_out_romask_T_1312; // @[RegisterRouter.scala:87:24] wire out_womask_1312 = &_out_womask_T_1312; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1312 = out_rivalid_1_1166 & out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12587 = out_f_rivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_roready_1312 = out_roready_1_1166 & out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12588 = out_f_roready_1312; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1312 = out_wivalid_1_1166 & out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12589 = out_f_wivalid_1312; // @[RegisterRouter.scala:87:24] wire out_f_woready_1312 = out_woready_1_1166 & out_womask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12590 = out_f_woready_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12591 = ~out_rimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12592 = ~out_wimask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12593 = ~out_romask_1312; // @[RegisterRouter.scala:87:24] wire _out_T_12594 = ~out_womask_1312; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1128 = {programBufferMem_59, _out_prepend_T_1128}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12595 = out_prepend_1128; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12596 = _out_T_12595; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1129 = _out_T_12596; // @[RegisterRouter.scala:87:24] wire out_rimask_1313 = |_out_rimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_wimask_1313 = &_out_wimask_T_1313; // @[RegisterRouter.scala:87:24] wire out_romask_1313 = |_out_romask_T_1313; // @[RegisterRouter.scala:87:24] wire out_womask_1313 = &_out_womask_T_1313; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1313 = out_rivalid_1_1167 & out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12598 = out_f_rivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_roready_1313 = out_roready_1_1167 & out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12599 = out_f_roready_1313; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1313 = out_wivalid_1_1167 & out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12600 = out_f_wivalid_1313; // @[RegisterRouter.scala:87:24] wire out_f_woready_1313 = out_woready_1_1167 & out_womask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12601 = out_f_woready_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12602 = ~out_rimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12603 = ~out_wimask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12604 = ~out_romask_1313; // @[RegisterRouter.scala:87:24] wire _out_T_12605 = ~out_womask_1313; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1129 = {programBufferMem_60, _out_prepend_T_1129}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12606 = out_prepend_1129; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12607 = _out_T_12606; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1130 = _out_T_12607; // @[RegisterRouter.scala:87:24] wire out_rimask_1314 = |_out_rimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_wimask_1314 = &_out_wimask_T_1314; // @[RegisterRouter.scala:87:24] wire out_romask_1314 = |_out_romask_T_1314; // @[RegisterRouter.scala:87:24] wire out_womask_1314 = &_out_womask_T_1314; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1314 = out_rivalid_1_1168 & out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12609 = out_f_rivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_roready_1314 = out_roready_1_1168 & out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12610 = out_f_roready_1314; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1314 = out_wivalid_1_1168 & out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12611 = out_f_wivalid_1314; // @[RegisterRouter.scala:87:24] wire out_f_woready_1314 = out_woready_1_1168 & out_womask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12612 = out_f_woready_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12613 = ~out_rimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12614 = ~out_wimask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12615 = ~out_romask_1314; // @[RegisterRouter.scala:87:24] wire _out_T_12616 = ~out_womask_1314; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1130 = {programBufferMem_61, _out_prepend_T_1130}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12617 = out_prepend_1130; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12618 = _out_T_12617; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1131 = _out_T_12618; // @[RegisterRouter.scala:87:24] wire out_rimask_1315 = |_out_rimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_wimask_1315 = &_out_wimask_T_1315; // @[RegisterRouter.scala:87:24] wire out_romask_1315 = |_out_romask_T_1315; // @[RegisterRouter.scala:87:24] wire out_womask_1315 = &_out_womask_T_1315; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1315 = out_rivalid_1_1169 & out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12620 = out_f_rivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_roready_1315 = out_roready_1_1169 & out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12621 = out_f_roready_1315; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1315 = out_wivalid_1_1169 & out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12622 = out_f_wivalid_1315; // @[RegisterRouter.scala:87:24] wire out_f_woready_1315 = out_woready_1_1169 & out_womask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12623 = out_f_woready_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12624 = ~out_rimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12625 = ~out_wimask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12626 = ~out_romask_1315; // @[RegisterRouter.scala:87:24] wire _out_T_12627 = ~out_womask_1315; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1131 = {programBufferMem_62, _out_prepend_T_1131}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12628 = out_prepend_1131; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12629 = _out_T_12628; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1132 = _out_T_12629; // @[RegisterRouter.scala:87:24] wire out_rimask_1316 = |_out_rimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_wimask_1316 = &_out_wimask_T_1316; // @[RegisterRouter.scala:87:24] wire out_romask_1316 = |_out_romask_T_1316; // @[RegisterRouter.scala:87:24] wire out_womask_1316 = &_out_womask_T_1316; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1316 = out_rivalid_1_1170 & out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12631 = out_f_rivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_roready_1316 = out_roready_1_1170 & out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12632 = out_f_roready_1316; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1316 = out_wivalid_1_1170 & out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12633 = out_f_wivalid_1316; // @[RegisterRouter.scala:87:24] wire out_f_woready_1316 = out_woready_1_1170 & out_womask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12634 = out_f_woready_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12635 = ~out_rimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12636 = ~out_wimask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12637 = ~out_romask_1316; // @[RegisterRouter.scala:87:24] wire _out_T_12638 = ~out_womask_1316; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1132 = {programBufferMem_63, _out_prepend_T_1132}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12639 = out_prepend_1132; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12640 = _out_T_12639; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_111 = _out_T_12640; // @[MuxLiteral.scala:49:48] wire out_rimask_1317 = |_out_rimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_wimask_1317 = &_out_wimask_T_1317; // @[RegisterRouter.scala:87:24] wire out_romask_1317 = |_out_romask_T_1317; // @[RegisterRouter.scala:87:24] wire out_womask_1317 = &_out_womask_T_1317; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1317 = out_rivalid_1_1171 & out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12642 = out_f_rivalid_1317; // @[RegisterRouter.scala:87:24] wire out_f_roready_1317 = out_roready_1_1171 & out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12643 = out_f_roready_1317; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1317 = out_wivalid_1_1171 & out_wimask_1317; // @[RegisterRouter.scala:87:24] wire out_f_woready_1317 = out_woready_1_1171 & out_womask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12644 = ~out_rimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12645 = ~out_wimask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12646 = ~out_romask_1317; // @[RegisterRouter.scala:87:24] wire _out_T_12647 = ~out_womask_1317; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12649 = _out_T_12648; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1133 = _out_T_12649; // @[RegisterRouter.scala:87:24] wire out_rimask_1318 = |_out_rimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_wimask_1318 = &_out_wimask_T_1318; // @[RegisterRouter.scala:87:24] wire out_romask_1318 = |_out_romask_T_1318; // @[RegisterRouter.scala:87:24] wire out_womask_1318 = &_out_womask_T_1318; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1318 = out_rivalid_1_1172 & out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12651 = out_f_rivalid_1318; // @[RegisterRouter.scala:87:24] wire out_f_roready_1318 = out_roready_1_1172 & out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12652 = out_f_roready_1318; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1318 = out_wivalid_1_1172 & out_wimask_1318; // @[RegisterRouter.scala:87:24] wire out_f_woready_1318 = out_woready_1_1172 & out_womask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12653 = ~out_rimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12654 = ~out_wimask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12655 = ~out_romask_1318; // @[RegisterRouter.scala:87:24] wire _out_T_12656 = ~out_womask_1318; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1133 = {hi_698, flags_0_go, _out_prepend_T_1133}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12657 = out_prepend_1133; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12658 = _out_T_12657; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1134 = _out_T_12658; // @[RegisterRouter.scala:87:24] wire out_rimask_1319 = |_out_rimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_wimask_1319 = &_out_wimask_T_1319; // @[RegisterRouter.scala:87:24] wire out_romask_1319 = |_out_romask_T_1319; // @[RegisterRouter.scala:87:24] wire out_womask_1319 = &_out_womask_T_1319; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1319 = out_rivalid_1_1173 & out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12660 = out_f_rivalid_1319; // @[RegisterRouter.scala:87:24] wire out_f_roready_1319 = out_roready_1_1173 & out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12661 = out_f_roready_1319; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1319 = out_wivalid_1_1173 & out_wimask_1319; // @[RegisterRouter.scala:87:24] wire out_f_woready_1319 = out_woready_1_1173 & out_womask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12662 = ~out_rimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12663 = ~out_wimask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12664 = ~out_romask_1319; // @[RegisterRouter.scala:87:24] wire _out_T_12665 = ~out_womask_1319; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1134 = {hi_699, flags_0_go, _out_prepend_T_1134}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12666 = out_prepend_1134; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12667 = _out_T_12666; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1135 = _out_T_12667; // @[RegisterRouter.scala:87:24] wire out_rimask_1320 = |_out_rimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_wimask_1320 = &_out_wimask_T_1320; // @[RegisterRouter.scala:87:24] wire out_romask_1320 = |_out_romask_T_1320; // @[RegisterRouter.scala:87:24] wire out_womask_1320 = &_out_womask_T_1320; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1320 = out_rivalid_1_1174 & out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12669 = out_f_rivalid_1320; // @[RegisterRouter.scala:87:24] wire out_f_roready_1320 = out_roready_1_1174 & out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12670 = out_f_roready_1320; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1320 = out_wivalid_1_1174 & out_wimask_1320; // @[RegisterRouter.scala:87:24] wire out_f_woready_1320 = out_woready_1_1174 & out_womask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12671 = ~out_rimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12672 = ~out_wimask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12673 = ~out_romask_1320; // @[RegisterRouter.scala:87:24] wire _out_T_12674 = ~out_womask_1320; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1135 = {hi_700, flags_0_go, _out_prepend_T_1135}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12675 = out_prepend_1135; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12676 = _out_T_12675; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1136 = _out_T_12676; // @[RegisterRouter.scala:87:24] wire out_rimask_1321 = |_out_rimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_wimask_1321 = &_out_wimask_T_1321; // @[RegisterRouter.scala:87:24] wire out_romask_1321 = |_out_romask_T_1321; // @[RegisterRouter.scala:87:24] wire out_womask_1321 = &_out_womask_T_1321; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1321 = out_rivalid_1_1175 & out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12678 = out_f_rivalid_1321; // @[RegisterRouter.scala:87:24] wire out_f_roready_1321 = out_roready_1_1175 & out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12679 = out_f_roready_1321; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1321 = out_wivalid_1_1175 & out_wimask_1321; // @[RegisterRouter.scala:87:24] wire out_f_woready_1321 = out_woready_1_1175 & out_womask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12680 = ~out_rimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12681 = ~out_wimask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12682 = ~out_romask_1321; // @[RegisterRouter.scala:87:24] wire _out_T_12683 = ~out_womask_1321; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1136 = {hi_701, flags_0_go, _out_prepend_T_1136}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12684 = out_prepend_1136; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12685 = _out_T_12684; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1137 = _out_T_12685; // @[RegisterRouter.scala:87:24] wire out_rimask_1322 = |_out_rimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_wimask_1322 = &_out_wimask_T_1322; // @[RegisterRouter.scala:87:24] wire out_romask_1322 = |_out_romask_T_1322; // @[RegisterRouter.scala:87:24] wire out_womask_1322 = &_out_womask_T_1322; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1322 = out_rivalid_1_1176 & out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12687 = out_f_rivalid_1322; // @[RegisterRouter.scala:87:24] wire out_f_roready_1322 = out_roready_1_1176 & out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12688 = out_f_roready_1322; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1322 = out_wivalid_1_1176 & out_wimask_1322; // @[RegisterRouter.scala:87:24] wire out_f_woready_1322 = out_woready_1_1176 & out_womask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12689 = ~out_rimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12690 = ~out_wimask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12691 = ~out_romask_1322; // @[RegisterRouter.scala:87:24] wire _out_T_12692 = ~out_womask_1322; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1137 = {hi_702, flags_0_go, _out_prepend_T_1137}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12693 = out_prepend_1137; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12694 = _out_T_12693; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1138 = _out_T_12694; // @[RegisterRouter.scala:87:24] wire out_rimask_1323 = |_out_rimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_wimask_1323 = &_out_wimask_T_1323; // @[RegisterRouter.scala:87:24] wire out_romask_1323 = |_out_romask_T_1323; // @[RegisterRouter.scala:87:24] wire out_womask_1323 = &_out_womask_T_1323; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1323 = out_rivalid_1_1177 & out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12696 = out_f_rivalid_1323; // @[RegisterRouter.scala:87:24] wire out_f_roready_1323 = out_roready_1_1177 & out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12697 = out_f_roready_1323; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1323 = out_wivalid_1_1177 & out_wimask_1323; // @[RegisterRouter.scala:87:24] wire out_f_woready_1323 = out_woready_1_1177 & out_womask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12698 = ~out_rimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12699 = ~out_wimask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12700 = ~out_romask_1323; // @[RegisterRouter.scala:87:24] wire _out_T_12701 = ~out_womask_1323; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1138 = {hi_703, flags_0_go, _out_prepend_T_1138}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12702 = out_prepend_1138; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12703 = _out_T_12702; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1139 = _out_T_12703; // @[RegisterRouter.scala:87:24] wire out_rimask_1324 = |_out_rimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_wimask_1324 = &_out_wimask_T_1324; // @[RegisterRouter.scala:87:24] wire out_romask_1324 = |_out_romask_T_1324; // @[RegisterRouter.scala:87:24] wire out_womask_1324 = &_out_womask_T_1324; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1324 = out_rivalid_1_1178 & out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12705 = out_f_rivalid_1324; // @[RegisterRouter.scala:87:24] wire out_f_roready_1324 = out_roready_1_1178 & out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12706 = out_f_roready_1324; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1324 = out_wivalid_1_1178 & out_wimask_1324; // @[RegisterRouter.scala:87:24] wire out_f_woready_1324 = out_woready_1_1178 & out_womask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12707 = ~out_rimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12708 = ~out_wimask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12709 = ~out_romask_1324; // @[RegisterRouter.scala:87:24] wire _out_T_12710 = ~out_womask_1324; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1139 = {hi_704, flags_0_go, _out_prepend_T_1139}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12711 = out_prepend_1139; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12712 = _out_T_12711; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_215 = _out_T_12712; // @[MuxLiteral.scala:49:48] wire out_rimask_1325 = |_out_rimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_wimask_1325 = &_out_wimask_T_1325; // @[RegisterRouter.scala:87:24] wire out_romask_1325 = |_out_romask_T_1325; // @[RegisterRouter.scala:87:24] wire out_womask_1325 = &_out_womask_T_1325; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1325 = out_rivalid_1_1179 & out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12714 = out_f_rivalid_1325; // @[RegisterRouter.scala:87:24] wire out_f_roready_1325 = out_roready_1_1179 & out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12715 = out_f_roready_1325; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1325 = out_wivalid_1_1179 & out_wimask_1325; // @[RegisterRouter.scala:87:24] wire out_f_woready_1325 = out_woready_1_1179 & out_womask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12716 = ~out_rimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12717 = ~out_wimask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12718 = ~out_romask_1325; // @[RegisterRouter.scala:87:24] wire _out_T_12719 = ~out_womask_1325; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12721 = _out_T_12720; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1140 = _out_T_12721; // @[RegisterRouter.scala:87:24] wire out_rimask_1326 = |_out_rimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_wimask_1326 = &_out_wimask_T_1326; // @[RegisterRouter.scala:87:24] wire out_romask_1326 = |_out_romask_T_1326; // @[RegisterRouter.scala:87:24] wire out_womask_1326 = &_out_womask_T_1326; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1326 = out_rivalid_1_1180 & out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12723 = out_f_rivalid_1326; // @[RegisterRouter.scala:87:24] wire out_f_roready_1326 = out_roready_1_1180 & out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12724 = out_f_roready_1326; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1326 = out_wivalid_1_1180 & out_wimask_1326; // @[RegisterRouter.scala:87:24] wire out_f_woready_1326 = out_woready_1_1180 & out_womask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12725 = ~out_rimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12726 = ~out_wimask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12727 = ~out_romask_1326; // @[RegisterRouter.scala:87:24] wire _out_T_12728 = ~out_womask_1326; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1140 = {hi_754, flags_0_go, _out_prepend_T_1140}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12729 = out_prepend_1140; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12730 = _out_T_12729; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1141 = _out_T_12730; // @[RegisterRouter.scala:87:24] wire out_rimask_1327 = |_out_rimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_wimask_1327 = &_out_wimask_T_1327; // @[RegisterRouter.scala:87:24] wire out_romask_1327 = |_out_romask_T_1327; // @[RegisterRouter.scala:87:24] wire out_womask_1327 = &_out_womask_T_1327; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1327 = out_rivalid_1_1181 & out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12732 = out_f_rivalid_1327; // @[RegisterRouter.scala:87:24] wire out_f_roready_1327 = out_roready_1_1181 & out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12733 = out_f_roready_1327; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1327 = out_wivalid_1_1181 & out_wimask_1327; // @[RegisterRouter.scala:87:24] wire out_f_woready_1327 = out_woready_1_1181 & out_womask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12734 = ~out_rimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12735 = ~out_wimask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12736 = ~out_romask_1327; // @[RegisterRouter.scala:87:24] wire _out_T_12737 = ~out_womask_1327; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1141 = {hi_755, flags_0_go, _out_prepend_T_1141}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12738 = out_prepend_1141; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12739 = _out_T_12738; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1142 = _out_T_12739; // @[RegisterRouter.scala:87:24] wire out_rimask_1328 = |_out_rimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_wimask_1328 = &_out_wimask_T_1328; // @[RegisterRouter.scala:87:24] wire out_romask_1328 = |_out_romask_T_1328; // @[RegisterRouter.scala:87:24] wire out_womask_1328 = &_out_womask_T_1328; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1328 = out_rivalid_1_1182 & out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12741 = out_f_rivalid_1328; // @[RegisterRouter.scala:87:24] wire out_f_roready_1328 = out_roready_1_1182 & out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12742 = out_f_roready_1328; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1328 = out_wivalid_1_1182 & out_wimask_1328; // @[RegisterRouter.scala:87:24] wire out_f_woready_1328 = out_woready_1_1182 & out_womask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12743 = ~out_rimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12744 = ~out_wimask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12745 = ~out_romask_1328; // @[RegisterRouter.scala:87:24] wire _out_T_12746 = ~out_womask_1328; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1142 = {hi_756, flags_0_go, _out_prepend_T_1142}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12747 = out_prepend_1142; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12748 = _out_T_12747; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1143 = _out_T_12748; // @[RegisterRouter.scala:87:24] wire out_rimask_1329 = |_out_rimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_wimask_1329 = &_out_wimask_T_1329; // @[RegisterRouter.scala:87:24] wire out_romask_1329 = |_out_romask_T_1329; // @[RegisterRouter.scala:87:24] wire out_womask_1329 = &_out_womask_T_1329; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1329 = out_rivalid_1_1183 & out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12750 = out_f_rivalid_1329; // @[RegisterRouter.scala:87:24] wire out_f_roready_1329 = out_roready_1_1183 & out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12751 = out_f_roready_1329; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1329 = out_wivalid_1_1183 & out_wimask_1329; // @[RegisterRouter.scala:87:24] wire out_f_woready_1329 = out_woready_1_1183 & out_womask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12752 = ~out_rimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12753 = ~out_wimask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12754 = ~out_romask_1329; // @[RegisterRouter.scala:87:24] wire _out_T_12755 = ~out_womask_1329; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1143 = {hi_757, flags_0_go, _out_prepend_T_1143}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12756 = out_prepend_1143; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12757 = _out_T_12756; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1144 = _out_T_12757; // @[RegisterRouter.scala:87:24] wire out_rimask_1330 = |_out_rimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_wimask_1330 = &_out_wimask_T_1330; // @[RegisterRouter.scala:87:24] wire out_romask_1330 = |_out_romask_T_1330; // @[RegisterRouter.scala:87:24] wire out_womask_1330 = &_out_womask_T_1330; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1330 = out_rivalid_1_1184 & out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12759 = out_f_rivalid_1330; // @[RegisterRouter.scala:87:24] wire out_f_roready_1330 = out_roready_1_1184 & out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12760 = out_f_roready_1330; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1330 = out_wivalid_1_1184 & out_wimask_1330; // @[RegisterRouter.scala:87:24] wire out_f_woready_1330 = out_woready_1_1184 & out_womask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12761 = ~out_rimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12762 = ~out_wimask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12763 = ~out_romask_1330; // @[RegisterRouter.scala:87:24] wire _out_T_12764 = ~out_womask_1330; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1144 = {hi_758, flags_0_go, _out_prepend_T_1144}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12765 = out_prepend_1144; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12766 = _out_T_12765; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1145 = _out_T_12766; // @[RegisterRouter.scala:87:24] wire out_rimask_1331 = |_out_rimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_wimask_1331 = &_out_wimask_T_1331; // @[RegisterRouter.scala:87:24] wire out_romask_1331 = |_out_romask_T_1331; // @[RegisterRouter.scala:87:24] wire out_womask_1331 = &_out_womask_T_1331; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1331 = out_rivalid_1_1185 & out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12768 = out_f_rivalid_1331; // @[RegisterRouter.scala:87:24] wire out_f_roready_1331 = out_roready_1_1185 & out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12769 = out_f_roready_1331; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1331 = out_wivalid_1_1185 & out_wimask_1331; // @[RegisterRouter.scala:87:24] wire out_f_woready_1331 = out_woready_1_1185 & out_womask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12770 = ~out_rimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12771 = ~out_wimask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12772 = ~out_romask_1331; // @[RegisterRouter.scala:87:24] wire _out_T_12773 = ~out_womask_1331; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1145 = {hi_759, flags_0_go, _out_prepend_T_1145}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12774 = out_prepend_1145; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12775 = _out_T_12774; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1146 = _out_T_12775; // @[RegisterRouter.scala:87:24] wire out_rimask_1332 = |_out_rimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_wimask_1332 = &_out_wimask_T_1332; // @[RegisterRouter.scala:87:24] wire out_romask_1332 = |_out_romask_T_1332; // @[RegisterRouter.scala:87:24] wire out_womask_1332 = &_out_womask_T_1332; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1332 = out_rivalid_1_1186 & out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12777 = out_f_rivalid_1332; // @[RegisterRouter.scala:87:24] wire out_f_roready_1332 = out_roready_1_1186 & out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12778 = out_f_roready_1332; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1332 = out_wivalid_1_1186 & out_wimask_1332; // @[RegisterRouter.scala:87:24] wire out_f_woready_1332 = out_woready_1_1186 & out_womask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12779 = ~out_rimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12780 = ~out_wimask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12781 = ~out_romask_1332; // @[RegisterRouter.scala:87:24] wire _out_T_12782 = ~out_womask_1332; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1146 = {hi_760, flags_0_go, _out_prepend_T_1146}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12783 = out_prepend_1146; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12784 = _out_T_12783; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_222 = _out_T_12784; // @[MuxLiteral.scala:49:48] wire out_rimask_1333 = |_out_rimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_wimask_1333 = &_out_wimask_T_1333; // @[RegisterRouter.scala:87:24] wire out_romask_1333 = |_out_romask_T_1333; // @[RegisterRouter.scala:87:24] wire out_womask_1333 = &_out_womask_T_1333; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1333 = out_rivalid_1_1187 & out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12786 = out_f_rivalid_1333; // @[RegisterRouter.scala:87:24] wire out_f_roready_1333 = out_roready_1_1187 & out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12787 = out_f_roready_1333; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1333 = out_wivalid_1_1187 & out_wimask_1333; // @[RegisterRouter.scala:87:24] wire out_f_woready_1333 = out_woready_1_1187 & out_womask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12788 = ~out_rimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12789 = ~out_wimask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12790 = ~out_romask_1333; // @[RegisterRouter.scala:87:24] wire _out_T_12791 = ~out_womask_1333; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12793 = _out_T_12792; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1147 = _out_T_12793; // @[RegisterRouter.scala:87:24] wire out_rimask_1334 = |_out_rimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_wimask_1334 = &_out_wimask_T_1334; // @[RegisterRouter.scala:87:24] wire out_romask_1334 = |_out_romask_T_1334; // @[RegisterRouter.scala:87:24] wire out_womask_1334 = &_out_womask_T_1334; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1334 = out_rivalid_1_1188 & out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12795 = out_f_rivalid_1334; // @[RegisterRouter.scala:87:24] wire out_f_roready_1334 = out_roready_1_1188 & out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12796 = out_f_roready_1334; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1334 = out_wivalid_1_1188 & out_wimask_1334; // @[RegisterRouter.scala:87:24] wire out_f_woready_1334 = out_woready_1_1188 & out_womask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12797 = ~out_rimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12798 = ~out_wimask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12799 = ~out_romask_1334; // @[RegisterRouter.scala:87:24] wire _out_T_12800 = ~out_womask_1334; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1147 = {hi_834, flags_0_go, _out_prepend_T_1147}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12801 = out_prepend_1147; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12802 = _out_T_12801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1148 = _out_T_12802; // @[RegisterRouter.scala:87:24] wire out_rimask_1335 = |_out_rimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_wimask_1335 = &_out_wimask_T_1335; // @[RegisterRouter.scala:87:24] wire out_romask_1335 = |_out_romask_T_1335; // @[RegisterRouter.scala:87:24] wire out_womask_1335 = &_out_womask_T_1335; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1335 = out_rivalid_1_1189 & out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12804 = out_f_rivalid_1335; // @[RegisterRouter.scala:87:24] wire out_f_roready_1335 = out_roready_1_1189 & out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12805 = out_f_roready_1335; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1335 = out_wivalid_1_1189 & out_wimask_1335; // @[RegisterRouter.scala:87:24] wire out_f_woready_1335 = out_woready_1_1189 & out_womask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12806 = ~out_rimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12807 = ~out_wimask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12808 = ~out_romask_1335; // @[RegisterRouter.scala:87:24] wire _out_T_12809 = ~out_womask_1335; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1148 = {hi_835, flags_0_go, _out_prepend_T_1148}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12810 = out_prepend_1148; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12811 = _out_T_12810; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1149 = _out_T_12811; // @[RegisterRouter.scala:87:24] wire out_rimask_1336 = |_out_rimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_wimask_1336 = &_out_wimask_T_1336; // @[RegisterRouter.scala:87:24] wire out_romask_1336 = |_out_romask_T_1336; // @[RegisterRouter.scala:87:24] wire out_womask_1336 = &_out_womask_T_1336; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1336 = out_rivalid_1_1190 & out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12813 = out_f_rivalid_1336; // @[RegisterRouter.scala:87:24] wire out_f_roready_1336 = out_roready_1_1190 & out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12814 = out_f_roready_1336; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1336 = out_wivalid_1_1190 & out_wimask_1336; // @[RegisterRouter.scala:87:24] wire out_f_woready_1336 = out_woready_1_1190 & out_womask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12815 = ~out_rimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12816 = ~out_wimask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12817 = ~out_romask_1336; // @[RegisterRouter.scala:87:24] wire _out_T_12818 = ~out_womask_1336; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1149 = {hi_836, flags_0_go, _out_prepend_T_1149}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12819 = out_prepend_1149; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12820 = _out_T_12819; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1150 = _out_T_12820; // @[RegisterRouter.scala:87:24] wire out_rimask_1337 = |_out_rimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_wimask_1337 = &_out_wimask_T_1337; // @[RegisterRouter.scala:87:24] wire out_romask_1337 = |_out_romask_T_1337; // @[RegisterRouter.scala:87:24] wire out_womask_1337 = &_out_womask_T_1337; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1337 = out_rivalid_1_1191 & out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12822 = out_f_rivalid_1337; // @[RegisterRouter.scala:87:24] wire out_f_roready_1337 = out_roready_1_1191 & out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12823 = out_f_roready_1337; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1337 = out_wivalid_1_1191 & out_wimask_1337; // @[RegisterRouter.scala:87:24] wire out_f_woready_1337 = out_woready_1_1191 & out_womask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12824 = ~out_rimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12825 = ~out_wimask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12826 = ~out_romask_1337; // @[RegisterRouter.scala:87:24] wire _out_T_12827 = ~out_womask_1337; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1150 = {hi_837, flags_0_go, _out_prepend_T_1150}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12828 = out_prepend_1150; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12829 = _out_T_12828; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1151 = _out_T_12829; // @[RegisterRouter.scala:87:24] wire out_rimask_1338 = |_out_rimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_wimask_1338 = &_out_wimask_T_1338; // @[RegisterRouter.scala:87:24] wire out_romask_1338 = |_out_romask_T_1338; // @[RegisterRouter.scala:87:24] wire out_womask_1338 = &_out_womask_T_1338; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1338 = out_rivalid_1_1192 & out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12831 = out_f_rivalid_1338; // @[RegisterRouter.scala:87:24] wire out_f_roready_1338 = out_roready_1_1192 & out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12832 = out_f_roready_1338; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1338 = out_wivalid_1_1192 & out_wimask_1338; // @[RegisterRouter.scala:87:24] wire out_f_woready_1338 = out_woready_1_1192 & out_womask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12833 = ~out_rimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12834 = ~out_wimask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12835 = ~out_romask_1338; // @[RegisterRouter.scala:87:24] wire _out_T_12836 = ~out_womask_1338; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1151 = {hi_838, flags_0_go, _out_prepend_T_1151}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12837 = out_prepend_1151; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12838 = _out_T_12837; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1152 = _out_T_12838; // @[RegisterRouter.scala:87:24] wire out_rimask_1339 = |_out_rimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_wimask_1339 = &_out_wimask_T_1339; // @[RegisterRouter.scala:87:24] wire out_romask_1339 = |_out_romask_T_1339; // @[RegisterRouter.scala:87:24] wire out_womask_1339 = &_out_womask_T_1339; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1339 = out_rivalid_1_1193 & out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12840 = out_f_rivalid_1339; // @[RegisterRouter.scala:87:24] wire out_f_roready_1339 = out_roready_1_1193 & out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12841 = out_f_roready_1339; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1339 = out_wivalid_1_1193 & out_wimask_1339; // @[RegisterRouter.scala:87:24] wire out_f_woready_1339 = out_woready_1_1193 & out_womask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12842 = ~out_rimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12843 = ~out_wimask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12844 = ~out_romask_1339; // @[RegisterRouter.scala:87:24] wire _out_T_12845 = ~out_womask_1339; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1152 = {hi_839, flags_0_go, _out_prepend_T_1152}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12846 = out_prepend_1152; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12847 = _out_T_12846; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1153 = _out_T_12847; // @[RegisterRouter.scala:87:24] wire out_rimask_1340 = |_out_rimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_wimask_1340 = &_out_wimask_T_1340; // @[RegisterRouter.scala:87:24] wire out_romask_1340 = |_out_romask_T_1340; // @[RegisterRouter.scala:87:24] wire out_womask_1340 = &_out_womask_T_1340; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1340 = out_rivalid_1_1194 & out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12849 = out_f_rivalid_1340; // @[RegisterRouter.scala:87:24] wire out_f_roready_1340 = out_roready_1_1194 & out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12850 = out_f_roready_1340; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1340 = out_wivalid_1_1194 & out_wimask_1340; // @[RegisterRouter.scala:87:24] wire out_f_woready_1340 = out_woready_1_1194 & out_womask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12851 = ~out_rimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12852 = ~out_wimask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12853 = ~out_romask_1340; // @[RegisterRouter.scala:87:24] wire _out_T_12854 = ~out_womask_1340; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1153 = {hi_840, flags_0_go, _out_prepend_T_1153}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12855 = out_prepend_1153; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12856 = _out_T_12855; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_232 = _out_T_12856; // @[MuxLiteral.scala:49:48] wire out_rimask_1341 = |_out_rimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_wimask_1341 = &_out_wimask_T_1341; // @[RegisterRouter.scala:87:24] wire out_romask_1341 = |_out_romask_T_1341; // @[RegisterRouter.scala:87:24] wire out_womask_1341 = &_out_womask_T_1341; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1341 = out_rivalid_1_1195 & out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12858 = out_f_rivalid_1341; // @[RegisterRouter.scala:87:24] wire out_f_roready_1341 = out_roready_1_1195 & out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12859 = out_f_roready_1341; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1341 = out_wivalid_1_1195 & out_wimask_1341; // @[RegisterRouter.scala:87:24] wire out_f_woready_1341 = out_woready_1_1195 & out_womask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12860 = ~out_rimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12861 = ~out_wimask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12862 = ~out_romask_1341; // @[RegisterRouter.scala:87:24] wire _out_T_12863 = ~out_womask_1341; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12865 = _out_T_12864; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1154 = _out_T_12865; // @[RegisterRouter.scala:87:24] wire out_rimask_1342 = |_out_rimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_wimask_1342 = &_out_wimask_T_1342; // @[RegisterRouter.scala:87:24] wire out_romask_1342 = |_out_romask_T_1342; // @[RegisterRouter.scala:87:24] wire out_womask_1342 = &_out_womask_T_1342; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1342 = out_rivalid_1_1196 & out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12867 = out_f_rivalid_1342; // @[RegisterRouter.scala:87:24] wire out_f_roready_1342 = out_roready_1_1196 & out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12868 = out_f_roready_1342; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1342 = out_wivalid_1_1196 & out_wimask_1342; // @[RegisterRouter.scala:87:24] wire out_f_woready_1342 = out_woready_1_1196 & out_womask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12869 = ~out_rimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12870 = ~out_wimask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12871 = ~out_romask_1342; // @[RegisterRouter.scala:87:24] wire _out_T_12872 = ~out_womask_1342; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1154 = {hi_1010, flags_0_go, _out_prepend_T_1154}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12873 = out_prepend_1154; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12874 = _out_T_12873; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1155 = _out_T_12874; // @[RegisterRouter.scala:87:24] wire out_rimask_1343 = |_out_rimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_wimask_1343 = &_out_wimask_T_1343; // @[RegisterRouter.scala:87:24] wire out_romask_1343 = |_out_romask_T_1343; // @[RegisterRouter.scala:87:24] wire out_womask_1343 = &_out_womask_T_1343; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1343 = out_rivalid_1_1197 & out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12876 = out_f_rivalid_1343; // @[RegisterRouter.scala:87:24] wire out_f_roready_1343 = out_roready_1_1197 & out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12877 = out_f_roready_1343; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1343 = out_wivalid_1_1197 & out_wimask_1343; // @[RegisterRouter.scala:87:24] wire out_f_woready_1343 = out_woready_1_1197 & out_womask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12878 = ~out_rimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12879 = ~out_wimask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12880 = ~out_romask_1343; // @[RegisterRouter.scala:87:24] wire _out_T_12881 = ~out_womask_1343; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1155 = {hi_1011, flags_0_go, _out_prepend_T_1155}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12882 = out_prepend_1155; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12883 = _out_T_12882; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1156 = _out_T_12883; // @[RegisterRouter.scala:87:24] wire out_rimask_1344 = |_out_rimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_wimask_1344 = &_out_wimask_T_1344; // @[RegisterRouter.scala:87:24] wire out_romask_1344 = |_out_romask_T_1344; // @[RegisterRouter.scala:87:24] wire out_womask_1344 = &_out_womask_T_1344; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1344 = out_rivalid_1_1198 & out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12885 = out_f_rivalid_1344; // @[RegisterRouter.scala:87:24] wire out_f_roready_1344 = out_roready_1_1198 & out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12886 = out_f_roready_1344; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1344 = out_wivalid_1_1198 & out_wimask_1344; // @[RegisterRouter.scala:87:24] wire out_f_woready_1344 = out_woready_1_1198 & out_womask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12887 = ~out_rimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12888 = ~out_wimask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12889 = ~out_romask_1344; // @[RegisterRouter.scala:87:24] wire _out_T_12890 = ~out_womask_1344; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1156 = {hi_1012, flags_0_go, _out_prepend_T_1156}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12891 = out_prepend_1156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12892 = _out_T_12891; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1157 = _out_T_12892; // @[RegisterRouter.scala:87:24] wire out_rimask_1345 = |_out_rimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_wimask_1345 = &_out_wimask_T_1345; // @[RegisterRouter.scala:87:24] wire out_romask_1345 = |_out_romask_T_1345; // @[RegisterRouter.scala:87:24] wire out_womask_1345 = &_out_womask_T_1345; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1345 = out_rivalid_1_1199 & out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12894 = out_f_rivalid_1345; // @[RegisterRouter.scala:87:24] wire out_f_roready_1345 = out_roready_1_1199 & out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12895 = out_f_roready_1345; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1345 = out_wivalid_1_1199 & out_wimask_1345; // @[RegisterRouter.scala:87:24] wire out_f_woready_1345 = out_woready_1_1199 & out_womask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12896 = ~out_rimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12897 = ~out_wimask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12898 = ~out_romask_1345; // @[RegisterRouter.scala:87:24] wire _out_T_12899 = ~out_womask_1345; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1157 = {hi_1013, flags_0_go, _out_prepend_T_1157}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12900 = out_prepend_1157; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12901 = _out_T_12900; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1158 = _out_T_12901; // @[RegisterRouter.scala:87:24] wire out_rimask_1346 = |_out_rimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_wimask_1346 = &_out_wimask_T_1346; // @[RegisterRouter.scala:87:24] wire out_romask_1346 = |_out_romask_T_1346; // @[RegisterRouter.scala:87:24] wire out_womask_1346 = &_out_womask_T_1346; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1346 = out_rivalid_1_1200 & out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12903 = out_f_rivalid_1346; // @[RegisterRouter.scala:87:24] wire out_f_roready_1346 = out_roready_1_1200 & out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12904 = out_f_roready_1346; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1346 = out_wivalid_1_1200 & out_wimask_1346; // @[RegisterRouter.scala:87:24] wire out_f_woready_1346 = out_woready_1_1200 & out_womask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12905 = ~out_rimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12906 = ~out_wimask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12907 = ~out_romask_1346; // @[RegisterRouter.scala:87:24] wire _out_T_12908 = ~out_womask_1346; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1158 = {hi_1014, flags_0_go, _out_prepend_T_1158}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12909 = out_prepend_1158; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12910 = _out_T_12909; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1159 = _out_T_12910; // @[RegisterRouter.scala:87:24] wire out_rimask_1347 = |_out_rimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_wimask_1347 = &_out_wimask_T_1347; // @[RegisterRouter.scala:87:24] wire out_romask_1347 = |_out_romask_T_1347; // @[RegisterRouter.scala:87:24] wire out_womask_1347 = &_out_womask_T_1347; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1347 = out_rivalid_1_1201 & out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12912 = out_f_rivalid_1347; // @[RegisterRouter.scala:87:24] wire out_f_roready_1347 = out_roready_1_1201 & out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12913 = out_f_roready_1347; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1347 = out_wivalid_1_1201 & out_wimask_1347; // @[RegisterRouter.scala:87:24] wire out_f_woready_1347 = out_woready_1_1201 & out_womask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12914 = ~out_rimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12915 = ~out_wimask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12916 = ~out_romask_1347; // @[RegisterRouter.scala:87:24] wire _out_T_12917 = ~out_womask_1347; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1159 = {hi_1015, flags_0_go, _out_prepend_T_1159}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12918 = out_prepend_1159; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12919 = _out_T_12918; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1160 = _out_T_12919; // @[RegisterRouter.scala:87:24] wire out_rimask_1348 = |_out_rimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_wimask_1348 = &_out_wimask_T_1348; // @[RegisterRouter.scala:87:24] wire out_romask_1348 = |_out_romask_T_1348; // @[RegisterRouter.scala:87:24] wire out_womask_1348 = &_out_womask_T_1348; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1348 = out_rivalid_1_1202 & out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12921 = out_f_rivalid_1348; // @[RegisterRouter.scala:87:24] wire out_f_roready_1348 = out_roready_1_1202 & out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12922 = out_f_roready_1348; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1348 = out_wivalid_1_1202 & out_wimask_1348; // @[RegisterRouter.scala:87:24] wire out_f_woready_1348 = out_woready_1_1202 & out_womask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12923 = ~out_rimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12924 = ~out_wimask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12925 = ~out_romask_1348; // @[RegisterRouter.scala:87:24] wire _out_T_12926 = ~out_womask_1348; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1160 = {hi_1016, flags_0_go, _out_prepend_T_1160}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12927 = out_prepend_1160; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12928 = _out_T_12927; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_254 = _out_T_12928; // @[MuxLiteral.scala:49:48] wire out_rimask_1349 = |_out_rimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_wimask_1349 = &_out_wimask_T_1349; // @[RegisterRouter.scala:87:24] wire out_romask_1349 = |_out_romask_T_1349; // @[RegisterRouter.scala:87:24] wire out_womask_1349 = &_out_womask_T_1349; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1349 = out_rivalid_1_1203 & out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12930 = out_f_rivalid_1349; // @[RegisterRouter.scala:87:24] wire out_f_roready_1349 = out_roready_1_1203 & out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12931 = out_f_roready_1349; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1349 = out_wivalid_1_1203 & out_wimask_1349; // @[RegisterRouter.scala:87:24] wire out_f_woready_1349 = out_woready_1_1203 & out_womask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12932 = ~out_rimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12933 = ~out_wimask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12934 = ~out_romask_1349; // @[RegisterRouter.scala:87:24] wire _out_T_12935 = ~out_womask_1349; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_12937 = _out_T_12936; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1161 = _out_T_12937; // @[RegisterRouter.scala:87:24] wire out_rimask_1350 = |_out_rimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_wimask_1350 = &_out_wimask_T_1350; // @[RegisterRouter.scala:87:24] wire out_romask_1350 = |_out_romask_T_1350; // @[RegisterRouter.scala:87:24] wire out_womask_1350 = &_out_womask_T_1350; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1350 = out_rivalid_1_1204 & out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12939 = out_f_rivalid_1350; // @[RegisterRouter.scala:87:24] wire out_f_roready_1350 = out_roready_1_1204 & out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12940 = out_f_roready_1350; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1350 = out_wivalid_1_1204 & out_wimask_1350; // @[RegisterRouter.scala:87:24] wire out_f_woready_1350 = out_woready_1_1204 & out_womask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12941 = ~out_rimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12942 = ~out_wimask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12943 = ~out_romask_1350; // @[RegisterRouter.scala:87:24] wire _out_T_12944 = ~out_womask_1350; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1161 = {hi_794, flags_0_go, _out_prepend_T_1161}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12945 = out_prepend_1161; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_12946 = _out_T_12945; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1162 = _out_T_12946; // @[RegisterRouter.scala:87:24] wire out_rimask_1351 = |_out_rimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_wimask_1351 = &_out_wimask_T_1351; // @[RegisterRouter.scala:87:24] wire out_romask_1351 = |_out_romask_T_1351; // @[RegisterRouter.scala:87:24] wire out_womask_1351 = &_out_womask_T_1351; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1351 = out_rivalid_1_1205 & out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12948 = out_f_rivalid_1351; // @[RegisterRouter.scala:87:24] wire out_f_roready_1351 = out_roready_1_1205 & out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12949 = out_f_roready_1351; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1351 = out_wivalid_1_1205 & out_wimask_1351; // @[RegisterRouter.scala:87:24] wire out_f_woready_1351 = out_woready_1_1205 & out_womask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12950 = ~out_rimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12951 = ~out_wimask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12952 = ~out_romask_1351; // @[RegisterRouter.scala:87:24] wire _out_T_12953 = ~out_womask_1351; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_1162 = {hi_795, flags_0_go, _out_prepend_T_1162}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12954 = out_prepend_1162; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_12955 = _out_T_12954; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_1163 = _out_T_12955; // @[RegisterRouter.scala:87:24] wire out_rimask_1352 = |_out_rimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_wimask_1352 = &_out_wimask_T_1352; // @[RegisterRouter.scala:87:24] wire out_romask_1352 = |_out_romask_T_1352; // @[RegisterRouter.scala:87:24] wire out_womask_1352 = &_out_womask_T_1352; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1352 = out_rivalid_1_1206 & out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12957 = out_f_rivalid_1352; // @[RegisterRouter.scala:87:24] wire out_f_roready_1352 = out_roready_1_1206 & out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12958 = out_f_roready_1352; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1352 = out_wivalid_1_1206 & out_wimask_1352; // @[RegisterRouter.scala:87:24] wire out_f_woready_1352 = out_woready_1_1206 & out_womask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12959 = ~out_rimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12960 = ~out_wimask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12961 = ~out_romask_1352; // @[RegisterRouter.scala:87:24] wire _out_T_12962 = ~out_womask_1352; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1163 = {hi_796, flags_0_go, _out_prepend_T_1163}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12963 = out_prepend_1163; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_12964 = _out_T_12963; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1164 = _out_T_12964; // @[RegisterRouter.scala:87:24] wire out_rimask_1353 = |_out_rimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_wimask_1353 = &_out_wimask_T_1353; // @[RegisterRouter.scala:87:24] wire out_romask_1353 = |_out_romask_T_1353; // @[RegisterRouter.scala:87:24] wire out_womask_1353 = &_out_womask_T_1353; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1353 = out_rivalid_1_1207 & out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12966 = out_f_rivalid_1353; // @[RegisterRouter.scala:87:24] wire out_f_roready_1353 = out_roready_1_1207 & out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12967 = out_f_roready_1353; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1353 = out_wivalid_1_1207 & out_wimask_1353; // @[RegisterRouter.scala:87:24] wire out_f_woready_1353 = out_woready_1_1207 & out_womask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12968 = ~out_rimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12969 = ~out_wimask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12970 = ~out_romask_1353; // @[RegisterRouter.scala:87:24] wire _out_T_12971 = ~out_womask_1353; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_1164 = {hi_797, flags_0_go, _out_prepend_T_1164}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12972 = out_prepend_1164; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_12973 = _out_T_12972; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_1165 = _out_T_12973; // @[RegisterRouter.scala:87:24] wire out_rimask_1354 = |_out_rimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_wimask_1354 = &_out_wimask_T_1354; // @[RegisterRouter.scala:87:24] wire out_romask_1354 = |_out_romask_T_1354; // @[RegisterRouter.scala:87:24] wire out_womask_1354 = &_out_womask_T_1354; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1354 = out_rivalid_1_1208 & out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12975 = out_f_rivalid_1354; // @[RegisterRouter.scala:87:24] wire out_f_roready_1354 = out_roready_1_1208 & out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12976 = out_f_roready_1354; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1354 = out_wivalid_1_1208 & out_wimask_1354; // @[RegisterRouter.scala:87:24] wire out_f_woready_1354 = out_woready_1_1208 & out_womask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12977 = ~out_rimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12978 = ~out_wimask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12979 = ~out_romask_1354; // @[RegisterRouter.scala:87:24] wire _out_T_12980 = ~out_womask_1354; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_1165 = {hi_798, flags_0_go, _out_prepend_T_1165}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12981 = out_prepend_1165; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_12982 = _out_T_12981; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_1166 = _out_T_12982; // @[RegisterRouter.scala:87:24] wire out_rimask_1355 = |_out_rimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_wimask_1355 = &_out_wimask_T_1355; // @[RegisterRouter.scala:87:24] wire out_romask_1355 = |_out_romask_T_1355; // @[RegisterRouter.scala:87:24] wire out_womask_1355 = &_out_womask_T_1355; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1355 = out_rivalid_1_1209 & out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12984 = out_f_rivalid_1355; // @[RegisterRouter.scala:87:24] wire out_f_roready_1355 = out_roready_1_1209 & out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12985 = out_f_roready_1355; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1355 = out_wivalid_1_1209 & out_wimask_1355; // @[RegisterRouter.scala:87:24] wire out_f_woready_1355 = out_woready_1_1209 & out_womask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12986 = ~out_rimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12987 = ~out_wimask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12988 = ~out_romask_1355; // @[RegisterRouter.scala:87:24] wire _out_T_12989 = ~out_womask_1355; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_1166 = {hi_799, flags_0_go, _out_prepend_T_1166}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12990 = out_prepend_1166; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_12991 = _out_T_12990; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_1167 = _out_T_12991; // @[RegisterRouter.scala:87:24] wire out_rimask_1356 = |_out_rimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_wimask_1356 = &_out_wimask_T_1356; // @[RegisterRouter.scala:87:24] wire out_romask_1356 = |_out_romask_T_1356; // @[RegisterRouter.scala:87:24] wire out_womask_1356 = &_out_womask_T_1356; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1356 = out_rivalid_1_1210 & out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12993 = out_f_rivalid_1356; // @[RegisterRouter.scala:87:24] wire out_f_roready_1356 = out_roready_1_1210 & out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12994 = out_f_roready_1356; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1356 = out_wivalid_1_1210 & out_wimask_1356; // @[RegisterRouter.scala:87:24] wire out_f_woready_1356 = out_woready_1_1210 & out_womask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12995 = ~out_rimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12996 = ~out_wimask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12997 = ~out_romask_1356; // @[RegisterRouter.scala:87:24] wire _out_T_12998 = ~out_womask_1356; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_1167 = {hi_800, flags_0_go, _out_prepend_T_1167}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_12999 = out_prepend_1167; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_13000 = _out_T_12999; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_3_227 = _out_T_13000; // @[MuxLiteral.scala:49:48] wire _out_iindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_lo = {_out_iindex_T_8, _out_iindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_lo_hi_1 = {_out_iindex_T_10, _out_iindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_lo_1 = {out_iindex_lo_hi_1, out_iindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_lo = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi_hi_1 = {_out_iindex_T_14, _out_iindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_iindex_hi_1 = {out_iindex_hi_hi_1, out_iindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_iindex_1 = {out_iindex_hi_1, out_iindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_lo = {_out_oindex_T_8, _out_oindex_T_7}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_lo_hi_1 = {_out_oindex_T_10, _out_oindex_T_9}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_lo_1 = {out_oindex_lo_hi_1, out_oindex_lo_lo}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_lo = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi_hi_1 = {_out_oindex_T_14, _out_oindex_T_13}; // @[RegisterRouter.scala:87:24] wire [3:0] out_oindex_hi_1 = {out_oindex_hi_hi_1, out_oindex_hi_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] out_oindex_1 = {out_oindex_hi_1, out_oindex_lo_1}; // @[RegisterRouter.scala:87:24] wire [255:0] _out_frontSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala:58:35] wire out_frontSel_0_1 = _out_frontSel_T_1[0]; // @[OneHot.scala:58:35] wire out_frontSel_1_1 = _out_frontSel_T_1[1]; // @[OneHot.scala:58:35] wire out_frontSel_2_1 = _out_frontSel_T_1[2]; // @[OneHot.scala:58:35] wire out_frontSel_3_1 = _out_frontSel_T_1[3]; // @[OneHot.scala:58:35] wire out_frontSel_4_1 = _out_frontSel_T_1[4]; // @[OneHot.scala:58:35] wire out_frontSel_5_1 = _out_frontSel_T_1[5]; // @[OneHot.scala:58:35] wire out_frontSel_6_1 = _out_frontSel_T_1[6]; // @[OneHot.scala:58:35] wire out_frontSel_7_1 = _out_frontSel_T_1[7]; // @[OneHot.scala:58:35] wire out_frontSel_8_1 = _out_frontSel_T_1[8]; // @[OneHot.scala:58:35] wire out_frontSel_9_1 = _out_frontSel_T_1[9]; // @[OneHot.scala:58:35] wire out_frontSel_10_1 = _out_frontSel_T_1[10]; // @[OneHot.scala:58:35] wire out_frontSel_11_1 = _out_frontSel_T_1[11]; // @[OneHot.scala:58:35] wire out_frontSel_12_1 = _out_frontSel_T_1[12]; // @[OneHot.scala:58:35] wire out_frontSel_13_1 = _out_frontSel_T_1[13]; // @[OneHot.scala:58:35] wire out_frontSel_14_1 = _out_frontSel_T_1[14]; // @[OneHot.scala:58:35] wire out_frontSel_15_1 = _out_frontSel_T_1[15]; // @[OneHot.scala:58:35] wire out_frontSel_16_1 = _out_frontSel_T_1[16]; // @[OneHot.scala:58:35] wire out_frontSel_17_1 = _out_frontSel_T_1[17]; // @[OneHot.scala:58:35] wire out_frontSel_18_1 = _out_frontSel_T_1[18]; // @[OneHot.scala:58:35] wire out_frontSel_19_1 = _out_frontSel_T_1[19]; // @[OneHot.scala:58:35] wire out_frontSel_20_1 = _out_frontSel_T_1[20]; // @[OneHot.scala:58:35] wire out_frontSel_21_1 = _out_frontSel_T_1[21]; // @[OneHot.scala:58:35] wire out_frontSel_22_1 = _out_frontSel_T_1[22]; // @[OneHot.scala:58:35] wire out_frontSel_23_1 = _out_frontSel_T_1[23]; // @[OneHot.scala:58:35] wire out_frontSel_24_1 = _out_frontSel_T_1[24]; // @[OneHot.scala:58:35] wire out_frontSel_25_1 = _out_frontSel_T_1[25]; // @[OneHot.scala:58:35] wire out_frontSel_26_1 = _out_frontSel_T_1[26]; // @[OneHot.scala:58:35] wire out_frontSel_27_1 = _out_frontSel_T_1[27]; // @[OneHot.scala:58:35] wire out_frontSel_28_1 = _out_frontSel_T_1[28]; // @[OneHot.scala:58:35] wire out_frontSel_29_1 = _out_frontSel_T_1[29]; // @[OneHot.scala:58:35] wire out_frontSel_30_1 = _out_frontSel_T_1[30]; // @[OneHot.scala:58:35] wire out_frontSel_31_1 = _out_frontSel_T_1[31]; // @[OneHot.scala:58:35] wire out_frontSel_32_1 = _out_frontSel_T_1[32]; // @[OneHot.scala:58:35] wire out_frontSel_33_1 = _out_frontSel_T_1[33]; // @[OneHot.scala:58:35] wire out_frontSel_34_1 = _out_frontSel_T_1[34]; // @[OneHot.scala:58:35] wire out_frontSel_35_1 = _out_frontSel_T_1[35]; // @[OneHot.scala:58:35] wire out_frontSel_36_1 = _out_frontSel_T_1[36]; // @[OneHot.scala:58:35] wire out_frontSel_37_1 = _out_frontSel_T_1[37]; // @[OneHot.scala:58:35] wire out_frontSel_38_1 = _out_frontSel_T_1[38]; // @[OneHot.scala:58:35] wire out_frontSel_39_1 = _out_frontSel_T_1[39]; // @[OneHot.scala:58:35] wire out_frontSel_40_1 = _out_frontSel_T_1[40]; // @[OneHot.scala:58:35] wire out_frontSel_41_1 = _out_frontSel_T_1[41]; // @[OneHot.scala:58:35] wire out_frontSel_42_1 = _out_frontSel_T_1[42]; // @[OneHot.scala:58:35] wire out_frontSel_43_1 = _out_frontSel_T_1[43]; // @[OneHot.scala:58:35] wire out_frontSel_44_1 = _out_frontSel_T_1[44]; // @[OneHot.scala:58:35] wire out_frontSel_45_1 = _out_frontSel_T_1[45]; // @[OneHot.scala:58:35] wire out_frontSel_46_1 = _out_frontSel_T_1[46]; // @[OneHot.scala:58:35] wire out_frontSel_47_1 = _out_frontSel_T_1[47]; // @[OneHot.scala:58:35] wire out_frontSel_48_1 = _out_frontSel_T_1[48]; // @[OneHot.scala:58:35] wire out_frontSel_49_1 = _out_frontSel_T_1[49]; // @[OneHot.scala:58:35] wire out_frontSel_50_1 = _out_frontSel_T_1[50]; // @[OneHot.scala:58:35] wire out_frontSel_51_1 = _out_frontSel_T_1[51]; // @[OneHot.scala:58:35] wire out_frontSel_52_1 = _out_frontSel_T_1[52]; // @[OneHot.scala:58:35] wire out_frontSel_53_1 = _out_frontSel_T_1[53]; // @[OneHot.scala:58:35] wire out_frontSel_54_1 = _out_frontSel_T_1[54]; // @[OneHot.scala:58:35] wire out_frontSel_55_1 = _out_frontSel_T_1[55]; // @[OneHot.scala:58:35] wire out_frontSel_56_1 = _out_frontSel_T_1[56]; // @[OneHot.scala:58:35] wire out_frontSel_57_1 = _out_frontSel_T_1[57]; // @[OneHot.scala:58:35] wire out_frontSel_58_1 = _out_frontSel_T_1[58]; // @[OneHot.scala:58:35] wire out_frontSel_59_1 = _out_frontSel_T_1[59]; // @[OneHot.scala:58:35] wire out_frontSel_60_1 = _out_frontSel_T_1[60]; // @[OneHot.scala:58:35] wire out_frontSel_61_1 = _out_frontSel_T_1[61]; // @[OneHot.scala:58:35] wire out_frontSel_62_1 = _out_frontSel_T_1[62]; // @[OneHot.scala:58:35] wire out_frontSel_63_1 = _out_frontSel_T_1[63]; // @[OneHot.scala:58:35] wire out_frontSel_64 = _out_frontSel_T_1[64]; // @[OneHot.scala:58:35] wire out_frontSel_65 = _out_frontSel_T_1[65]; // @[OneHot.scala:58:35] wire out_frontSel_66 = _out_frontSel_T_1[66]; // @[OneHot.scala:58:35] wire out_frontSel_67 = _out_frontSel_T_1[67]; // @[OneHot.scala:58:35] wire out_frontSel_68 = _out_frontSel_T_1[68]; // @[OneHot.scala:58:35] wire out_frontSel_69 = _out_frontSel_T_1[69]; // @[OneHot.scala:58:35] wire out_frontSel_70 = _out_frontSel_T_1[70]; // @[OneHot.scala:58:35] wire out_frontSel_71 = _out_frontSel_T_1[71]; // @[OneHot.scala:58:35] wire out_frontSel_72 = _out_frontSel_T_1[72]; // @[OneHot.scala:58:35] wire out_frontSel_73 = _out_frontSel_T_1[73]; // @[OneHot.scala:58:35] wire out_frontSel_74 = _out_frontSel_T_1[74]; // @[OneHot.scala:58:35] wire out_frontSel_75 = _out_frontSel_T_1[75]; // @[OneHot.scala:58:35] wire out_frontSel_76 = _out_frontSel_T_1[76]; // @[OneHot.scala:58:35] wire out_frontSel_77 = _out_frontSel_T_1[77]; // @[OneHot.scala:58:35] wire out_frontSel_78 = _out_frontSel_T_1[78]; // @[OneHot.scala:58:35] wire out_frontSel_79 = _out_frontSel_T_1[79]; // @[OneHot.scala:58:35] wire out_frontSel_80 = _out_frontSel_T_1[80]; // @[OneHot.scala:58:35] wire out_frontSel_81 = _out_frontSel_T_1[81]; // @[OneHot.scala:58:35] wire out_frontSel_82 = _out_frontSel_T_1[82]; // @[OneHot.scala:58:35] wire out_frontSel_83 = _out_frontSel_T_1[83]; // @[OneHot.scala:58:35] wire out_frontSel_84 = _out_frontSel_T_1[84]; // @[OneHot.scala:58:35] wire out_frontSel_85 = _out_frontSel_T_1[85]; // @[OneHot.scala:58:35] wire out_frontSel_86 = _out_frontSel_T_1[86]; // @[OneHot.scala:58:35] wire out_frontSel_87 = _out_frontSel_T_1[87]; // @[OneHot.scala:58:35] wire out_frontSel_88 = _out_frontSel_T_1[88]; // @[OneHot.scala:58:35] wire out_frontSel_89 = _out_frontSel_T_1[89]; // @[OneHot.scala:58:35] wire out_frontSel_90 = _out_frontSel_T_1[90]; // @[OneHot.scala:58:35] wire out_frontSel_91 = _out_frontSel_T_1[91]; // @[OneHot.scala:58:35] wire out_frontSel_92 = _out_frontSel_T_1[92]; // @[OneHot.scala:58:35] wire out_frontSel_93 = _out_frontSel_T_1[93]; // @[OneHot.scala:58:35] wire out_frontSel_94 = _out_frontSel_T_1[94]; // @[OneHot.scala:58:35] wire out_frontSel_95 = _out_frontSel_T_1[95]; // @[OneHot.scala:58:35] wire out_frontSel_96 = _out_frontSel_T_1[96]; // @[OneHot.scala:58:35] wire out_frontSel_97 = _out_frontSel_T_1[97]; // @[OneHot.scala:58:35] wire out_frontSel_98 = _out_frontSel_T_1[98]; // @[OneHot.scala:58:35] wire out_frontSel_99 = _out_frontSel_T_1[99]; // @[OneHot.scala:58:35] wire out_frontSel_100 = _out_frontSel_T_1[100]; // @[OneHot.scala:58:35] wire out_frontSel_101 = _out_frontSel_T_1[101]; // @[OneHot.scala:58:35] wire out_frontSel_102 = _out_frontSel_T_1[102]; // @[OneHot.scala:58:35] wire out_frontSel_103 = _out_frontSel_T_1[103]; // @[OneHot.scala:58:35] wire out_frontSel_104 = _out_frontSel_T_1[104]; // @[OneHot.scala:58:35] wire out_frontSel_105 = _out_frontSel_T_1[105]; // @[OneHot.scala:58:35] wire out_frontSel_106 = _out_frontSel_T_1[106]; // @[OneHot.scala:58:35] wire out_frontSel_107 = _out_frontSel_T_1[107]; // @[OneHot.scala:58:35] wire out_frontSel_108 = _out_frontSel_T_1[108]; // @[OneHot.scala:58:35] wire out_frontSel_109 = _out_frontSel_T_1[109]; // @[OneHot.scala:58:35] wire out_frontSel_110 = _out_frontSel_T_1[110]; // @[OneHot.scala:58:35] wire out_frontSel_111 = _out_frontSel_T_1[111]; // @[OneHot.scala:58:35] wire out_frontSel_112 = _out_frontSel_T_1[112]; // @[OneHot.scala:58:35] wire out_frontSel_113 = _out_frontSel_T_1[113]; // @[OneHot.scala:58:35] wire out_frontSel_114 = _out_frontSel_T_1[114]; // @[OneHot.scala:58:35] wire out_frontSel_115 = _out_frontSel_T_1[115]; // @[OneHot.scala:58:35] wire out_frontSel_116 = _out_frontSel_T_1[116]; // @[OneHot.scala:58:35] wire out_frontSel_117 = _out_frontSel_T_1[117]; // @[OneHot.scala:58:35] wire out_frontSel_118 = _out_frontSel_T_1[118]; // @[OneHot.scala:58:35] wire out_frontSel_119 = _out_frontSel_T_1[119]; // @[OneHot.scala:58:35] wire out_frontSel_120 = _out_frontSel_T_1[120]; // @[OneHot.scala:58:35] wire out_frontSel_121 = _out_frontSel_T_1[121]; // @[OneHot.scala:58:35] wire out_frontSel_122 = _out_frontSel_T_1[122]; // @[OneHot.scala:58:35] wire out_frontSel_123 = _out_frontSel_T_1[123]; // @[OneHot.scala:58:35] wire out_frontSel_124 = _out_frontSel_T_1[124]; // @[OneHot.scala:58:35] wire out_frontSel_125 = _out_frontSel_T_1[125]; // @[OneHot.scala:58:35] wire out_frontSel_126 = _out_frontSel_T_1[126]; // @[OneHot.scala:58:35] wire out_frontSel_127 = _out_frontSel_T_1[127]; // @[OneHot.scala:58:35] wire out_frontSel_128 = _out_frontSel_T_1[128]; // @[OneHot.scala:58:35] wire out_frontSel_129 = _out_frontSel_T_1[129]; // @[OneHot.scala:58:35] wire out_frontSel_130 = _out_frontSel_T_1[130]; // @[OneHot.scala:58:35] wire out_frontSel_131 = _out_frontSel_T_1[131]; // @[OneHot.scala:58:35] wire out_frontSel_132 = _out_frontSel_T_1[132]; // @[OneHot.scala:58:35] wire out_frontSel_133 = _out_frontSel_T_1[133]; // @[OneHot.scala:58:35] wire out_frontSel_134 = _out_frontSel_T_1[134]; // @[OneHot.scala:58:35] wire out_frontSel_135 = _out_frontSel_T_1[135]; // @[OneHot.scala:58:35] wire out_frontSel_136 = _out_frontSel_T_1[136]; // @[OneHot.scala:58:35] wire out_frontSel_137 = _out_frontSel_T_1[137]; // @[OneHot.scala:58:35] wire out_frontSel_138 = _out_frontSel_T_1[138]; // @[OneHot.scala:58:35] wire out_frontSel_139 = _out_frontSel_T_1[139]; // @[OneHot.scala:58:35] wire out_frontSel_140 = _out_frontSel_T_1[140]; // @[OneHot.scala:58:35] wire out_frontSel_141 = _out_frontSel_T_1[141]; // @[OneHot.scala:58:35] wire out_frontSel_142 = _out_frontSel_T_1[142]; // @[OneHot.scala:58:35] wire out_frontSel_143 = _out_frontSel_T_1[143]; // @[OneHot.scala:58:35] wire out_frontSel_144 = _out_frontSel_T_1[144]; // @[OneHot.scala:58:35] wire out_frontSel_145 = _out_frontSel_T_1[145]; // @[OneHot.scala:58:35] wire out_frontSel_146 = _out_frontSel_T_1[146]; // @[OneHot.scala:58:35] wire out_frontSel_147 = _out_frontSel_T_1[147]; // @[OneHot.scala:58:35] wire out_frontSel_148 = _out_frontSel_T_1[148]; // @[OneHot.scala:58:35] wire out_frontSel_149 = _out_frontSel_T_1[149]; // @[OneHot.scala:58:35] wire out_frontSel_150 = _out_frontSel_T_1[150]; // @[OneHot.scala:58:35] wire out_frontSel_151 = _out_frontSel_T_1[151]; // @[OneHot.scala:58:35] wire out_frontSel_152 = _out_frontSel_T_1[152]; // @[OneHot.scala:58:35] wire out_frontSel_153 = _out_frontSel_T_1[153]; // @[OneHot.scala:58:35] wire out_frontSel_154 = _out_frontSel_T_1[154]; // @[OneHot.scala:58:35] wire out_frontSel_155 = _out_frontSel_T_1[155]; // @[OneHot.scala:58:35] wire out_frontSel_156 = _out_frontSel_T_1[156]; // @[OneHot.scala:58:35] wire out_frontSel_157 = _out_frontSel_T_1[157]; // @[OneHot.scala:58:35] wire out_frontSel_158 = _out_frontSel_T_1[158]; // @[OneHot.scala:58:35] wire out_frontSel_159 = _out_frontSel_T_1[159]; // @[OneHot.scala:58:35] wire out_frontSel_160 = _out_frontSel_T_1[160]; // @[OneHot.scala:58:35] wire out_frontSel_161 = _out_frontSel_T_1[161]; // @[OneHot.scala:58:35] wire out_frontSel_162 = _out_frontSel_T_1[162]; // @[OneHot.scala:58:35] wire out_frontSel_163 = _out_frontSel_T_1[163]; // @[OneHot.scala:58:35] wire out_frontSel_164 = _out_frontSel_T_1[164]; // @[OneHot.scala:58:35] wire out_frontSel_165 = _out_frontSel_T_1[165]; // @[OneHot.scala:58:35] wire out_frontSel_166 = _out_frontSel_T_1[166]; // @[OneHot.scala:58:35] wire out_frontSel_167 = _out_frontSel_T_1[167]; // @[OneHot.scala:58:35] wire out_frontSel_168 = _out_frontSel_T_1[168]; // @[OneHot.scala:58:35] wire out_frontSel_169 = _out_frontSel_T_1[169]; // @[OneHot.scala:58:35] wire out_frontSel_170 = _out_frontSel_T_1[170]; // @[OneHot.scala:58:35] wire out_frontSel_171 = _out_frontSel_T_1[171]; // @[OneHot.scala:58:35] wire out_frontSel_172 = _out_frontSel_T_1[172]; // @[OneHot.scala:58:35] wire out_frontSel_173 = _out_frontSel_T_1[173]; // @[OneHot.scala:58:35] wire out_frontSel_174 = _out_frontSel_T_1[174]; // @[OneHot.scala:58:35] wire out_frontSel_175 = _out_frontSel_T_1[175]; // @[OneHot.scala:58:35] wire out_frontSel_176 = _out_frontSel_T_1[176]; // @[OneHot.scala:58:35] wire out_frontSel_177 = _out_frontSel_T_1[177]; // @[OneHot.scala:58:35] wire out_frontSel_178 = _out_frontSel_T_1[178]; // @[OneHot.scala:58:35] wire out_frontSel_179 = _out_frontSel_T_1[179]; // @[OneHot.scala:58:35] wire out_frontSel_180 = _out_frontSel_T_1[180]; // @[OneHot.scala:58:35] wire out_frontSel_181 = _out_frontSel_T_1[181]; // @[OneHot.scala:58:35] wire out_frontSel_182 = _out_frontSel_T_1[182]; // @[OneHot.scala:58:35] wire out_frontSel_183 = _out_frontSel_T_1[183]; // @[OneHot.scala:58:35] wire out_frontSel_184 = _out_frontSel_T_1[184]; // @[OneHot.scala:58:35] wire out_frontSel_185 = _out_frontSel_T_1[185]; // @[OneHot.scala:58:35] wire out_frontSel_186 = _out_frontSel_T_1[186]; // @[OneHot.scala:58:35] wire out_frontSel_187 = _out_frontSel_T_1[187]; // @[OneHot.scala:58:35] wire out_frontSel_188 = _out_frontSel_T_1[188]; // @[OneHot.scala:58:35] wire out_frontSel_189 = _out_frontSel_T_1[189]; // @[OneHot.scala:58:35] wire out_frontSel_190 = _out_frontSel_T_1[190]; // @[OneHot.scala:58:35] wire out_frontSel_191 = _out_frontSel_T_1[191]; // @[OneHot.scala:58:35] wire out_frontSel_192 = _out_frontSel_T_1[192]; // @[OneHot.scala:58:35] wire out_frontSel_193 = _out_frontSel_T_1[193]; // @[OneHot.scala:58:35] wire out_frontSel_194 = _out_frontSel_T_1[194]; // @[OneHot.scala:58:35] wire out_frontSel_195 = _out_frontSel_T_1[195]; // @[OneHot.scala:58:35] wire out_frontSel_196 = _out_frontSel_T_1[196]; // @[OneHot.scala:58:35] wire out_frontSel_197 = _out_frontSel_T_1[197]; // @[OneHot.scala:58:35] wire out_frontSel_198 = _out_frontSel_T_1[198]; // @[OneHot.scala:58:35] wire out_frontSel_199 = _out_frontSel_T_1[199]; // @[OneHot.scala:58:35] wire out_frontSel_200 = _out_frontSel_T_1[200]; // @[OneHot.scala:58:35] wire out_frontSel_201 = _out_frontSel_T_1[201]; // @[OneHot.scala:58:35] wire out_frontSel_202 = _out_frontSel_T_1[202]; // @[OneHot.scala:58:35] wire out_frontSel_203 = _out_frontSel_T_1[203]; // @[OneHot.scala:58:35] wire out_frontSel_204 = _out_frontSel_T_1[204]; // @[OneHot.scala:58:35] wire out_frontSel_205 = _out_frontSel_T_1[205]; // @[OneHot.scala:58:35] wire out_frontSel_206 = _out_frontSel_T_1[206]; // @[OneHot.scala:58:35] wire out_frontSel_207 = _out_frontSel_T_1[207]; // @[OneHot.scala:58:35] wire out_frontSel_208 = _out_frontSel_T_1[208]; // @[OneHot.scala:58:35] wire out_frontSel_209 = _out_frontSel_T_1[209]; // @[OneHot.scala:58:35] wire out_frontSel_210 = _out_frontSel_T_1[210]; // @[OneHot.scala:58:35] wire out_frontSel_211 = _out_frontSel_T_1[211]; // @[OneHot.scala:58:35] wire out_frontSel_212 = _out_frontSel_T_1[212]; // @[OneHot.scala:58:35] wire out_frontSel_213 = _out_frontSel_T_1[213]; // @[OneHot.scala:58:35] wire out_frontSel_214 = _out_frontSel_T_1[214]; // @[OneHot.scala:58:35] wire out_frontSel_215 = _out_frontSel_T_1[215]; // @[OneHot.scala:58:35] wire out_frontSel_216 = _out_frontSel_T_1[216]; // @[OneHot.scala:58:35] wire out_frontSel_217 = _out_frontSel_T_1[217]; // @[OneHot.scala:58:35] wire out_frontSel_218 = _out_frontSel_T_1[218]; // @[OneHot.scala:58:35] wire out_frontSel_219 = _out_frontSel_T_1[219]; // @[OneHot.scala:58:35] wire out_frontSel_220 = _out_frontSel_T_1[220]; // @[OneHot.scala:58:35] wire out_frontSel_221 = _out_frontSel_T_1[221]; // @[OneHot.scala:58:35] wire out_frontSel_222 = _out_frontSel_T_1[222]; // @[OneHot.scala:58:35] wire out_frontSel_223 = _out_frontSel_T_1[223]; // @[OneHot.scala:58:35] wire out_frontSel_224 = _out_frontSel_T_1[224]; // @[OneHot.scala:58:35] wire out_frontSel_225 = _out_frontSel_T_1[225]; // @[OneHot.scala:58:35] wire out_frontSel_226 = _out_frontSel_T_1[226]; // @[OneHot.scala:58:35] wire out_frontSel_227 = _out_frontSel_T_1[227]; // @[OneHot.scala:58:35] wire out_frontSel_228 = _out_frontSel_T_1[228]; // @[OneHot.scala:58:35] wire out_frontSel_229 = _out_frontSel_T_1[229]; // @[OneHot.scala:58:35] wire out_frontSel_230 = _out_frontSel_T_1[230]; // @[OneHot.scala:58:35] wire out_frontSel_231 = _out_frontSel_T_1[231]; // @[OneHot.scala:58:35] wire out_frontSel_232 = _out_frontSel_T_1[232]; // @[OneHot.scala:58:35] wire out_frontSel_233 = _out_frontSel_T_1[233]; // @[OneHot.scala:58:35] wire out_frontSel_234 = _out_frontSel_T_1[234]; // @[OneHot.scala:58:35] wire out_frontSel_235 = _out_frontSel_T_1[235]; // @[OneHot.scala:58:35] wire out_frontSel_236 = _out_frontSel_T_1[236]; // @[OneHot.scala:58:35] wire out_frontSel_237 = _out_frontSel_T_1[237]; // @[OneHot.scala:58:35] wire out_frontSel_238 = _out_frontSel_T_1[238]; // @[OneHot.scala:58:35] wire out_frontSel_239 = _out_frontSel_T_1[239]; // @[OneHot.scala:58:35] wire out_frontSel_240 = _out_frontSel_T_1[240]; // @[OneHot.scala:58:35] wire out_frontSel_241 = _out_frontSel_T_1[241]; // @[OneHot.scala:58:35] wire out_frontSel_242 = _out_frontSel_T_1[242]; // @[OneHot.scala:58:35] wire out_frontSel_243 = _out_frontSel_T_1[243]; // @[OneHot.scala:58:35] wire out_frontSel_244 = _out_frontSel_T_1[244]; // @[OneHot.scala:58:35] wire out_frontSel_245 = _out_frontSel_T_1[245]; // @[OneHot.scala:58:35] wire out_frontSel_246 = _out_frontSel_T_1[246]; // @[OneHot.scala:58:35] wire out_frontSel_247 = _out_frontSel_T_1[247]; // @[OneHot.scala:58:35] wire out_frontSel_248 = _out_frontSel_T_1[248]; // @[OneHot.scala:58:35] wire out_frontSel_249 = _out_frontSel_T_1[249]; // @[OneHot.scala:58:35] wire out_frontSel_250 = _out_frontSel_T_1[250]; // @[OneHot.scala:58:35] wire out_frontSel_251 = _out_frontSel_T_1[251]; // @[OneHot.scala:58:35] wire out_frontSel_252 = _out_frontSel_T_1[252]; // @[OneHot.scala:58:35] wire out_frontSel_253 = _out_frontSel_T_1[253]; // @[OneHot.scala:58:35] wire out_frontSel_254 = _out_frontSel_T_1[254]; // @[OneHot.scala:58:35] wire out_frontSel_255 = _out_frontSel_T_1[255]; // @[OneHot.scala:58:35] wire [255:0] _out_backSel_T_1 = 256'h1 << out_oindex_1; // @[OneHot.scala:58:35] wire out_backSel_0_1 = _out_backSel_T_1[0]; // @[OneHot.scala:58:35] wire out_backSel_1_1 = _out_backSel_T_1[1]; // @[OneHot.scala:58:35] wire out_backSel_2_1 = _out_backSel_T_1[2]; // @[OneHot.scala:58:35] wire out_backSel_3_1 = _out_backSel_T_1[3]; // @[OneHot.scala:58:35] wire out_backSel_4_1 = _out_backSel_T_1[4]; // @[OneHot.scala:58:35] wire out_backSel_5_1 = _out_backSel_T_1[5]; // @[OneHot.scala:58:35] wire out_backSel_6_1 = _out_backSel_T_1[6]; // @[OneHot.scala:58:35] wire out_backSel_7_1 = _out_backSel_T_1[7]; // @[OneHot.scala:58:35] wire out_backSel_8_1 = _out_backSel_T_1[8]; // @[OneHot.scala:58:35] wire out_backSel_9_1 = _out_backSel_T_1[9]; // @[OneHot.scala:58:35] wire out_backSel_10_1 = _out_backSel_T_1[10]; // @[OneHot.scala:58:35] wire out_backSel_11_1 = _out_backSel_T_1[11]; // @[OneHot.scala:58:35] wire out_backSel_12_1 = _out_backSel_T_1[12]; // @[OneHot.scala:58:35] wire out_backSel_13_1 = _out_backSel_T_1[13]; // @[OneHot.scala:58:35] wire out_backSel_14_1 = _out_backSel_T_1[14]; // @[OneHot.scala:58:35] wire out_backSel_15_1 = _out_backSel_T_1[15]; // @[OneHot.scala:58:35] wire out_backSel_16_1 = _out_backSel_T_1[16]; // @[OneHot.scala:58:35] wire out_backSel_17_1 = _out_backSel_T_1[17]; // @[OneHot.scala:58:35] wire out_backSel_18_1 = _out_backSel_T_1[18]; // @[OneHot.scala:58:35] wire out_backSel_19_1 = _out_backSel_T_1[19]; // @[OneHot.scala:58:35] wire out_backSel_20_1 = _out_backSel_T_1[20]; // @[OneHot.scala:58:35] wire out_backSel_21_1 = _out_backSel_T_1[21]; // @[OneHot.scala:58:35] wire out_backSel_22_1 = _out_backSel_T_1[22]; // @[OneHot.scala:58:35] wire out_backSel_23_1 = _out_backSel_T_1[23]; // @[OneHot.scala:58:35] wire out_backSel_24_1 = _out_backSel_T_1[24]; // @[OneHot.scala:58:35] wire out_backSel_25_1 = _out_backSel_T_1[25]; // @[OneHot.scala:58:35] wire out_backSel_26_1 = _out_backSel_T_1[26]; // @[OneHot.scala:58:35] wire out_backSel_27_1 = _out_backSel_T_1[27]; // @[OneHot.scala:58:35] wire out_backSel_28_1 = _out_backSel_T_1[28]; // @[OneHot.scala:58:35] wire out_backSel_29_1 = _out_backSel_T_1[29]; // @[OneHot.scala:58:35] wire out_backSel_30_1 = _out_backSel_T_1[30]; // @[OneHot.scala:58:35] wire out_backSel_31_1 = _out_backSel_T_1[31]; // @[OneHot.scala:58:35] wire out_backSel_32_1 = _out_backSel_T_1[32]; // @[OneHot.scala:58:35] wire out_backSel_33_1 = _out_backSel_T_1[33]; // @[OneHot.scala:58:35] wire out_backSel_34_1 = _out_backSel_T_1[34]; // @[OneHot.scala:58:35] wire out_backSel_35_1 = _out_backSel_T_1[35]; // @[OneHot.scala:58:35] wire out_backSel_36_1 = _out_backSel_T_1[36]; // @[OneHot.scala:58:35] wire out_backSel_37_1 = _out_backSel_T_1[37]; // @[OneHot.scala:58:35] wire out_backSel_38_1 = _out_backSel_T_1[38]; // @[OneHot.scala:58:35] wire out_backSel_39_1 = _out_backSel_T_1[39]; // @[OneHot.scala:58:35] wire out_backSel_40_1 = _out_backSel_T_1[40]; // @[OneHot.scala:58:35] wire out_backSel_41_1 = _out_backSel_T_1[41]; // @[OneHot.scala:58:35] wire out_backSel_42_1 = _out_backSel_T_1[42]; // @[OneHot.scala:58:35] wire out_backSel_43_1 = _out_backSel_T_1[43]; // @[OneHot.scala:58:35] wire out_backSel_44_1 = _out_backSel_T_1[44]; // @[OneHot.scala:58:35] wire out_backSel_45_1 = _out_backSel_T_1[45]; // @[OneHot.scala:58:35] wire out_backSel_46_1 = _out_backSel_T_1[46]; // @[OneHot.scala:58:35] wire out_backSel_47_1 = _out_backSel_T_1[47]; // @[OneHot.scala:58:35] wire out_backSel_48_1 = _out_backSel_T_1[48]; // @[OneHot.scala:58:35] wire out_backSel_49_1 = _out_backSel_T_1[49]; // @[OneHot.scala:58:35] wire out_backSel_50_1 = _out_backSel_T_1[50]; // @[OneHot.scala:58:35] wire out_backSel_51_1 = _out_backSel_T_1[51]; // @[OneHot.scala:58:35] wire out_backSel_52_1 = _out_backSel_T_1[52]; // @[OneHot.scala:58:35] wire out_backSel_53_1 = _out_backSel_T_1[53]; // @[OneHot.scala:58:35] wire out_backSel_54_1 = _out_backSel_T_1[54]; // @[OneHot.scala:58:35] wire out_backSel_55_1 = _out_backSel_T_1[55]; // @[OneHot.scala:58:35] wire out_backSel_56_1 = _out_backSel_T_1[56]; // @[OneHot.scala:58:35] wire out_backSel_57_1 = _out_backSel_T_1[57]; // @[OneHot.scala:58:35] wire out_backSel_58_1 = _out_backSel_T_1[58]; // @[OneHot.scala:58:35] wire out_backSel_59_1 = _out_backSel_T_1[59]; // @[OneHot.scala:58:35] wire out_backSel_60_1 = _out_backSel_T_1[60]; // @[OneHot.scala:58:35] wire out_backSel_61_1 = _out_backSel_T_1[61]; // @[OneHot.scala:58:35] wire out_backSel_62_1 = _out_backSel_T_1[62]; // @[OneHot.scala:58:35] wire out_backSel_63_1 = _out_backSel_T_1[63]; // @[OneHot.scala:58:35] wire out_backSel_64 = _out_backSel_T_1[64]; // @[OneHot.scala:58:35] wire out_backSel_65 = _out_backSel_T_1[65]; // @[OneHot.scala:58:35] wire out_backSel_66 = _out_backSel_T_1[66]; // @[OneHot.scala:58:35] wire out_backSel_67 = _out_backSel_T_1[67]; // @[OneHot.scala:58:35] wire out_backSel_68 = _out_backSel_T_1[68]; // @[OneHot.scala:58:35] wire out_backSel_69 = _out_backSel_T_1[69]; // @[OneHot.scala:58:35] wire out_backSel_70 = _out_backSel_T_1[70]; // @[OneHot.scala:58:35] wire out_backSel_71 = _out_backSel_T_1[71]; // @[OneHot.scala:58:35] wire out_backSel_72 = _out_backSel_T_1[72]; // @[OneHot.scala:58:35] wire out_backSel_73 = _out_backSel_T_1[73]; // @[OneHot.scala:58:35] wire out_backSel_74 = _out_backSel_T_1[74]; // @[OneHot.scala:58:35] wire out_backSel_75 = _out_backSel_T_1[75]; // @[OneHot.scala:58:35] wire out_backSel_76 = _out_backSel_T_1[76]; // @[OneHot.scala:58:35] wire out_backSel_77 = _out_backSel_T_1[77]; // @[OneHot.scala:58:35] wire out_backSel_78 = _out_backSel_T_1[78]; // @[OneHot.scala:58:35] wire out_backSel_79 = _out_backSel_T_1[79]; // @[OneHot.scala:58:35] wire out_backSel_80 = _out_backSel_T_1[80]; // @[OneHot.scala:58:35] wire out_backSel_81 = _out_backSel_T_1[81]; // @[OneHot.scala:58:35] wire out_backSel_82 = _out_backSel_T_1[82]; // @[OneHot.scala:58:35] wire out_backSel_83 = _out_backSel_T_1[83]; // @[OneHot.scala:58:35] wire out_backSel_84 = _out_backSel_T_1[84]; // @[OneHot.scala:58:35] wire out_backSel_85 = _out_backSel_T_1[85]; // @[OneHot.scala:58:35] wire out_backSel_86 = _out_backSel_T_1[86]; // @[OneHot.scala:58:35] wire out_backSel_87 = _out_backSel_T_1[87]; // @[OneHot.scala:58:35] wire out_backSel_88 = _out_backSel_T_1[88]; // @[OneHot.scala:58:35] wire out_backSel_89 = _out_backSel_T_1[89]; // @[OneHot.scala:58:35] wire out_backSel_90 = _out_backSel_T_1[90]; // @[OneHot.scala:58:35] wire out_backSel_91 = _out_backSel_T_1[91]; // @[OneHot.scala:58:35] wire out_backSel_92 = _out_backSel_T_1[92]; // @[OneHot.scala:58:35] wire out_backSel_93 = _out_backSel_T_1[93]; // @[OneHot.scala:58:35] wire out_backSel_94 = _out_backSel_T_1[94]; // @[OneHot.scala:58:35] wire out_backSel_95 = _out_backSel_T_1[95]; // @[OneHot.scala:58:35] wire out_backSel_96 = _out_backSel_T_1[96]; // @[OneHot.scala:58:35] wire out_backSel_97 = _out_backSel_T_1[97]; // @[OneHot.scala:58:35] wire out_backSel_98 = _out_backSel_T_1[98]; // @[OneHot.scala:58:35] wire out_backSel_99 = _out_backSel_T_1[99]; // @[OneHot.scala:58:35] wire out_backSel_100 = _out_backSel_T_1[100]; // @[OneHot.scala:58:35] wire out_backSel_101 = _out_backSel_T_1[101]; // @[OneHot.scala:58:35] wire out_backSel_102 = _out_backSel_T_1[102]; // @[OneHot.scala:58:35] wire out_backSel_103 = _out_backSel_T_1[103]; // @[OneHot.scala:58:35] wire out_backSel_104 = _out_backSel_T_1[104]; // @[OneHot.scala:58:35] wire out_backSel_105 = _out_backSel_T_1[105]; // @[OneHot.scala:58:35] wire out_backSel_106 = _out_backSel_T_1[106]; // @[OneHot.scala:58:35] wire out_backSel_107 = _out_backSel_T_1[107]; // @[OneHot.scala:58:35] wire out_backSel_108 = _out_backSel_T_1[108]; // @[OneHot.scala:58:35] wire out_backSel_109 = _out_backSel_T_1[109]; // @[OneHot.scala:58:35] wire out_backSel_110 = _out_backSel_T_1[110]; // @[OneHot.scala:58:35] wire out_backSel_111 = _out_backSel_T_1[111]; // @[OneHot.scala:58:35] wire out_backSel_112 = _out_backSel_T_1[112]; // @[OneHot.scala:58:35] wire out_backSel_113 = _out_backSel_T_1[113]; // @[OneHot.scala:58:35] wire out_backSel_114 = _out_backSel_T_1[114]; // @[OneHot.scala:58:35] wire out_backSel_115 = _out_backSel_T_1[115]; // @[OneHot.scala:58:35] wire out_backSel_116 = _out_backSel_T_1[116]; // @[OneHot.scala:58:35] wire out_backSel_117 = _out_backSel_T_1[117]; // @[OneHot.scala:58:35] wire out_backSel_118 = _out_backSel_T_1[118]; // @[OneHot.scala:58:35] wire out_backSel_119 = _out_backSel_T_1[119]; // @[OneHot.scala:58:35] wire out_backSel_120 = _out_backSel_T_1[120]; // @[OneHot.scala:58:35] wire out_backSel_121 = _out_backSel_T_1[121]; // @[OneHot.scala:58:35] wire out_backSel_122 = _out_backSel_T_1[122]; // @[OneHot.scala:58:35] wire out_backSel_123 = _out_backSel_T_1[123]; // @[OneHot.scala:58:35] wire out_backSel_124 = _out_backSel_T_1[124]; // @[OneHot.scala:58:35] wire out_backSel_125 = _out_backSel_T_1[125]; // @[OneHot.scala:58:35] wire out_backSel_126 = _out_backSel_T_1[126]; // @[OneHot.scala:58:35] wire out_backSel_127 = _out_backSel_T_1[127]; // @[OneHot.scala:58:35] wire out_backSel_128 = _out_backSel_T_1[128]; // @[OneHot.scala:58:35] wire out_backSel_129 = _out_backSel_T_1[129]; // @[OneHot.scala:58:35] wire out_backSel_130 = _out_backSel_T_1[130]; // @[OneHot.scala:58:35] wire out_backSel_131 = _out_backSel_T_1[131]; // @[OneHot.scala:58:35] wire out_backSel_132 = _out_backSel_T_1[132]; // @[OneHot.scala:58:35] wire out_backSel_133 = _out_backSel_T_1[133]; // @[OneHot.scala:58:35] wire out_backSel_134 = _out_backSel_T_1[134]; // @[OneHot.scala:58:35] wire out_backSel_135 = _out_backSel_T_1[135]; // @[OneHot.scala:58:35] wire out_backSel_136 = _out_backSel_T_1[136]; // @[OneHot.scala:58:35] wire out_backSel_137 = _out_backSel_T_1[137]; // @[OneHot.scala:58:35] wire out_backSel_138 = _out_backSel_T_1[138]; // @[OneHot.scala:58:35] wire out_backSel_139 = _out_backSel_T_1[139]; // @[OneHot.scala:58:35] wire out_backSel_140 = _out_backSel_T_1[140]; // @[OneHot.scala:58:35] wire out_backSel_141 = _out_backSel_T_1[141]; // @[OneHot.scala:58:35] wire out_backSel_142 = _out_backSel_T_1[142]; // @[OneHot.scala:58:35] wire out_backSel_143 = _out_backSel_T_1[143]; // @[OneHot.scala:58:35] wire out_backSel_144 = _out_backSel_T_1[144]; // @[OneHot.scala:58:35] wire out_backSel_145 = _out_backSel_T_1[145]; // @[OneHot.scala:58:35] wire out_backSel_146 = _out_backSel_T_1[146]; // @[OneHot.scala:58:35] wire out_backSel_147 = _out_backSel_T_1[147]; // @[OneHot.scala:58:35] wire out_backSel_148 = _out_backSel_T_1[148]; // @[OneHot.scala:58:35] wire out_backSel_149 = _out_backSel_T_1[149]; // @[OneHot.scala:58:35] wire out_backSel_150 = _out_backSel_T_1[150]; // @[OneHot.scala:58:35] wire out_backSel_151 = _out_backSel_T_1[151]; // @[OneHot.scala:58:35] wire out_backSel_152 = _out_backSel_T_1[152]; // @[OneHot.scala:58:35] wire out_backSel_153 = _out_backSel_T_1[153]; // @[OneHot.scala:58:35] wire out_backSel_154 = _out_backSel_T_1[154]; // @[OneHot.scala:58:35] wire out_backSel_155 = _out_backSel_T_1[155]; // @[OneHot.scala:58:35] wire out_backSel_156 = _out_backSel_T_1[156]; // @[OneHot.scala:58:35] wire out_backSel_157 = _out_backSel_T_1[157]; // @[OneHot.scala:58:35] wire out_backSel_158 = _out_backSel_T_1[158]; // @[OneHot.scala:58:35] wire out_backSel_159 = _out_backSel_T_1[159]; // @[OneHot.scala:58:35] wire out_backSel_160 = _out_backSel_T_1[160]; // @[OneHot.scala:58:35] wire out_backSel_161 = _out_backSel_T_1[161]; // @[OneHot.scala:58:35] wire out_backSel_162 = _out_backSel_T_1[162]; // @[OneHot.scala:58:35] wire out_backSel_163 = _out_backSel_T_1[163]; // @[OneHot.scala:58:35] wire out_backSel_164 = _out_backSel_T_1[164]; // @[OneHot.scala:58:35] wire out_backSel_165 = _out_backSel_T_1[165]; // @[OneHot.scala:58:35] wire out_backSel_166 = _out_backSel_T_1[166]; // @[OneHot.scala:58:35] wire out_backSel_167 = _out_backSel_T_1[167]; // @[OneHot.scala:58:35] wire out_backSel_168 = _out_backSel_T_1[168]; // @[OneHot.scala:58:35] wire out_backSel_169 = _out_backSel_T_1[169]; // @[OneHot.scala:58:35] wire out_backSel_170 = _out_backSel_T_1[170]; // @[OneHot.scala:58:35] wire out_backSel_171 = _out_backSel_T_1[171]; // @[OneHot.scala:58:35] wire out_backSel_172 = _out_backSel_T_1[172]; // @[OneHot.scala:58:35] wire out_backSel_173 = _out_backSel_T_1[173]; // @[OneHot.scala:58:35] wire out_backSel_174 = _out_backSel_T_1[174]; // @[OneHot.scala:58:35] wire out_backSel_175 = _out_backSel_T_1[175]; // @[OneHot.scala:58:35] wire out_backSel_176 = _out_backSel_T_1[176]; // @[OneHot.scala:58:35] wire out_backSel_177 = _out_backSel_T_1[177]; // @[OneHot.scala:58:35] wire out_backSel_178 = _out_backSel_T_1[178]; // @[OneHot.scala:58:35] wire out_backSel_179 = _out_backSel_T_1[179]; // @[OneHot.scala:58:35] wire out_backSel_180 = _out_backSel_T_1[180]; // @[OneHot.scala:58:35] wire out_backSel_181 = _out_backSel_T_1[181]; // @[OneHot.scala:58:35] wire out_backSel_182 = _out_backSel_T_1[182]; // @[OneHot.scala:58:35] wire out_backSel_183 = _out_backSel_T_1[183]; // @[OneHot.scala:58:35] wire out_backSel_184 = _out_backSel_T_1[184]; // @[OneHot.scala:58:35] wire out_backSel_185 = _out_backSel_T_1[185]; // @[OneHot.scala:58:35] wire out_backSel_186 = _out_backSel_T_1[186]; // @[OneHot.scala:58:35] wire out_backSel_187 = _out_backSel_T_1[187]; // @[OneHot.scala:58:35] wire out_backSel_188 = _out_backSel_T_1[188]; // @[OneHot.scala:58:35] wire out_backSel_189 = _out_backSel_T_1[189]; // @[OneHot.scala:58:35] wire out_backSel_190 = _out_backSel_T_1[190]; // @[OneHot.scala:58:35] wire out_backSel_191 = _out_backSel_T_1[191]; // @[OneHot.scala:58:35] wire out_backSel_192 = _out_backSel_T_1[192]; // @[OneHot.scala:58:35] wire out_backSel_193 = _out_backSel_T_1[193]; // @[OneHot.scala:58:35] wire out_backSel_194 = _out_backSel_T_1[194]; // @[OneHot.scala:58:35] wire out_backSel_195 = _out_backSel_T_1[195]; // @[OneHot.scala:58:35] wire out_backSel_196 = _out_backSel_T_1[196]; // @[OneHot.scala:58:35] wire out_backSel_197 = _out_backSel_T_1[197]; // @[OneHot.scala:58:35] wire out_backSel_198 = _out_backSel_T_1[198]; // @[OneHot.scala:58:35] wire out_backSel_199 = _out_backSel_T_1[199]; // @[OneHot.scala:58:35] wire out_backSel_200 = _out_backSel_T_1[200]; // @[OneHot.scala:58:35] wire out_backSel_201 = _out_backSel_T_1[201]; // @[OneHot.scala:58:35] wire out_backSel_202 = _out_backSel_T_1[202]; // @[OneHot.scala:58:35] wire out_backSel_203 = _out_backSel_T_1[203]; // @[OneHot.scala:58:35] wire out_backSel_204 = _out_backSel_T_1[204]; // @[OneHot.scala:58:35] wire out_backSel_205 = _out_backSel_T_1[205]; // @[OneHot.scala:58:35] wire out_backSel_206 = _out_backSel_T_1[206]; // @[OneHot.scala:58:35] wire out_backSel_207 = _out_backSel_T_1[207]; // @[OneHot.scala:58:35] wire out_backSel_208 = _out_backSel_T_1[208]; // @[OneHot.scala:58:35] wire out_backSel_209 = _out_backSel_T_1[209]; // @[OneHot.scala:58:35] wire out_backSel_210 = _out_backSel_T_1[210]; // @[OneHot.scala:58:35] wire out_backSel_211 = _out_backSel_T_1[211]; // @[OneHot.scala:58:35] wire out_backSel_212 = _out_backSel_T_1[212]; // @[OneHot.scala:58:35] wire out_backSel_213 = _out_backSel_T_1[213]; // @[OneHot.scala:58:35] wire out_backSel_214 = _out_backSel_T_1[214]; // @[OneHot.scala:58:35] wire out_backSel_215 = _out_backSel_T_1[215]; // @[OneHot.scala:58:35] wire out_backSel_216 = _out_backSel_T_1[216]; // @[OneHot.scala:58:35] wire out_backSel_217 = _out_backSel_T_1[217]; // @[OneHot.scala:58:35] wire out_backSel_218 = _out_backSel_T_1[218]; // @[OneHot.scala:58:35] wire out_backSel_219 = _out_backSel_T_1[219]; // @[OneHot.scala:58:35] wire out_backSel_220 = _out_backSel_T_1[220]; // @[OneHot.scala:58:35] wire out_backSel_221 = _out_backSel_T_1[221]; // @[OneHot.scala:58:35] wire out_backSel_222 = _out_backSel_T_1[222]; // @[OneHot.scala:58:35] wire out_backSel_223 = _out_backSel_T_1[223]; // @[OneHot.scala:58:35] wire out_backSel_224 = _out_backSel_T_1[224]; // @[OneHot.scala:58:35] wire out_backSel_225 = _out_backSel_T_1[225]; // @[OneHot.scala:58:35] wire out_backSel_226 = _out_backSel_T_1[226]; // @[OneHot.scala:58:35] wire out_backSel_227 = _out_backSel_T_1[227]; // @[OneHot.scala:58:35] wire out_backSel_228 = _out_backSel_T_1[228]; // @[OneHot.scala:58:35] wire out_backSel_229 = _out_backSel_T_1[229]; // @[OneHot.scala:58:35] wire out_backSel_230 = _out_backSel_T_1[230]; // @[OneHot.scala:58:35] wire out_backSel_231 = _out_backSel_T_1[231]; // @[OneHot.scala:58:35] wire out_backSel_232 = _out_backSel_T_1[232]; // @[OneHot.scala:58:35] wire out_backSel_233 = _out_backSel_T_1[233]; // @[OneHot.scala:58:35] wire out_backSel_234 = _out_backSel_T_1[234]; // @[OneHot.scala:58:35] wire out_backSel_235 = _out_backSel_T_1[235]; // @[OneHot.scala:58:35] wire out_backSel_236 = _out_backSel_T_1[236]; // @[OneHot.scala:58:35] wire out_backSel_237 = _out_backSel_T_1[237]; // @[OneHot.scala:58:35] wire out_backSel_238 = _out_backSel_T_1[238]; // @[OneHot.scala:58:35] wire out_backSel_239 = _out_backSel_T_1[239]; // @[OneHot.scala:58:35] wire out_backSel_240 = _out_backSel_T_1[240]; // @[OneHot.scala:58:35] wire out_backSel_241 = _out_backSel_T_1[241]; // @[OneHot.scala:58:35] wire out_backSel_242 = _out_backSel_T_1[242]; // @[OneHot.scala:58:35] wire out_backSel_243 = _out_backSel_T_1[243]; // @[OneHot.scala:58:35] wire out_backSel_244 = _out_backSel_T_1[244]; // @[OneHot.scala:58:35] wire out_backSel_245 = _out_backSel_T_1[245]; // @[OneHot.scala:58:35] wire out_backSel_246 = _out_backSel_T_1[246]; // @[OneHot.scala:58:35] wire out_backSel_247 = _out_backSel_T_1[247]; // @[OneHot.scala:58:35] wire out_backSel_248 = _out_backSel_T_1[248]; // @[OneHot.scala:58:35] wire out_backSel_249 = _out_backSel_T_1[249]; // @[OneHot.scala:58:35] wire out_backSel_250 = _out_backSel_T_1[250]; // @[OneHot.scala:58:35] wire out_backSel_251 = _out_backSel_T_1[251]; // @[OneHot.scala:58:35] wire out_backSel_252 = _out_backSel_T_1[252]; // @[OneHot.scala:58:35] wire out_backSel_253 = _out_backSel_T_1[253]; // @[OneHot.scala:58:35] wire out_backSel_254 = _out_backSel_T_1[254]; // @[OneHot.scala:58:35] wire out_backSel_255 = _out_backSel_T_1[255]; // @[OneHot.scala:58:35] wire _GEN_22 = in_1_valid & out_front_1_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_259 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_260 = _GEN_22; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_260 = _out_rifireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_261 = _out_rifireMux_T_260 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_262 = _out_rifireMux_T_261 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_451 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_452 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_453 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_454 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_455 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_456 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_457 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_458 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_263 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_265 = _out_rifireMux_T_260 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_266 = _out_rifireMux_T_265 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_96 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_97 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_98 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_99 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_100 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_101 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_102 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_103 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_267 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_269 = _out_rifireMux_T_260 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_270 = _out_rifireMux_T_269 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_955 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_956 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_957 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_958 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_959 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_960 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_961 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_962 = _out_rifireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_271 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_273 = _out_rifireMux_T_260 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_274 = _out_rifireMux_T_273 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_601 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_602 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_603 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_604 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_605 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_606 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_607 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_608 = _out_rifireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_275 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_277 = _out_rifireMux_T_260 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_278 = _out_rifireMux_T_277 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_312 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_313 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_314 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_315 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_316 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_317 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_318 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_319 = _out_rifireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_279 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_281 = _out_rifireMux_T_260 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_282 = _out_rifireMux_T_281 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_160 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_161 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_162 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_163 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_164 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_165 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_166 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_167 = _out_rifireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_283 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_285 = _out_rifireMux_T_260 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_286 = _out_rifireMux_T_285 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1075 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1076 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1077 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1078 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1079 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1080 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1081 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1082 = _out_rifireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_287 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_289 = _out_rifireMux_T_260 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_290 = _out_rifireMux_T_289 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_859 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_860 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_861 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_862 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_863 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_864 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_865 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_866 = _out_rifireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_291 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_293 = _out_rifireMux_T_260 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_294 = _out_rifireMux_T_293 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_545 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_546 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_547 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_548 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_549 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_550 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_551 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_552 = _out_rifireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_295 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_297 = _out_rifireMux_T_260 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_298 = _out_rifireMux_T_297 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_264 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_265 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_266 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_267 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_268 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_269 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_270 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_271 = _out_rifireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_299 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_301 = _out_rifireMux_T_260 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_302 = _out_rifireMux_T_301 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_483 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_484 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_485 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_486 = _out_rifireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_303 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_305 = _out_rifireMux_T_260 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_306 = _out_rifireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_309 = _out_rifireMux_T_260 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_310 = _out_rifireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_313 = _out_rifireMux_T_260 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_314 = _out_rifireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_317 = _out_rifireMux_T_260 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_318 = _out_rifireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_321 = _out_rifireMux_T_260 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_322 = _out_rifireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_325 = _out_rifireMux_T_260 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_326 = _out_rifireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_329 = _out_rifireMux_T_260 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_330 = _out_rifireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_333 = _out_rifireMux_T_260 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_334 = _out_rifireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_337 = _out_rifireMux_T_260 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_338 = _out_rifireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_341 = _out_rifireMux_T_260 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_342 = _out_rifireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_345 = _out_rifireMux_T_260 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_346 = _out_rifireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_349 = _out_rifireMux_T_260 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_350 = _out_rifireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_353 = _out_rifireMux_T_260 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_354 = _out_rifireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_357 = _out_rifireMux_T_260 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_358 = _out_rifireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_361 = _out_rifireMux_T_260 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_362 = _out_rifireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_365 = _out_rifireMux_T_260 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_366 = _out_rifireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_369 = _out_rifireMux_T_260 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_370 = _out_rifireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_373 = _out_rifireMux_T_260 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_374 = _out_rifireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_377 = _out_rifireMux_T_260 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_378 = _out_rifireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_381 = _out_rifireMux_T_260 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_382 = _out_rifireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_385 = _out_rifireMux_T_260 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_386 = _out_rifireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_389 = _out_rifireMux_T_260 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_390 = _out_rifireMux_T_389 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_535 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_536 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_391 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_393 = _out_rifireMux_T_260 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_394 = _out_rifireMux_T_393 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_352 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_353 = _out_rifireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_395 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_397 = _out_rifireMux_T_260 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_398 = _out_rifireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_401 = _out_rifireMux_T_260 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_402 = _out_rifireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_405 = _out_rifireMux_T_260 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_406 = _out_rifireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_409 = _out_rifireMux_T_260 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_410 = _out_rifireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_413 = _out_rifireMux_T_260 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_414 = _out_rifireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_417 = _out_rifireMux_T_260 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_418 = _out_rifireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_421 = _out_rifireMux_T_260 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_422 = _out_rifireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_425 = _out_rifireMux_T_260 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_426 = _out_rifireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_429 = _out_rifireMux_T_260 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_430 = _out_rifireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_433 = _out_rifireMux_T_260 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_434 = _out_rifireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_437 = _out_rifireMux_T_260 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_438 = _out_rifireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_441 = _out_rifireMux_T_260 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_442 = _out_rifireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_445 = _out_rifireMux_T_260 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_446 = _out_rifireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_449 = _out_rifireMux_T_260 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_450 = _out_rifireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_453 = _out_rifireMux_T_260 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_454 = _out_rifireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_457 = _out_rifireMux_T_260 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_458 = _out_rifireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_461 = _out_rifireMux_T_260 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_462 = _out_rifireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_465 = _out_rifireMux_T_260 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_466 = _out_rifireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_469 = _out_rifireMux_T_260 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_470 = _out_rifireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_473 = _out_rifireMux_T_260 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_474 = _out_rifireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_477 = _out_rifireMux_T_260 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_478 = _out_rifireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_481 = _out_rifireMux_T_260 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_482 = _out_rifireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_485 = _out_rifireMux_T_260 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_486 = _out_rifireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_489 = _out_rifireMux_T_260 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_490 = _out_rifireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_493 = _out_rifireMux_T_260 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_494 = _out_rifireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_497 = _out_rifireMux_T_260 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_498 = _out_rifireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_501 = _out_rifireMux_T_260 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_502 = _out_rifireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_505 = _out_rifireMux_T_260 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_506 = _out_rifireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_509 = _out_rifireMux_T_260 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_510 = _out_rifireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_513 = _out_rifireMux_T_260 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_514 = _out_rifireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_517 = _out_rifireMux_T_260 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_518 = _out_rifireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_521 = _out_rifireMux_T_260 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_522 = _out_rifireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_525 = _out_rifireMux_T_260 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_526 = _out_rifireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_529 = _out_rifireMux_T_260 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_530 = _out_rifireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_533 = _out_rifireMux_T_260 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_534 = _out_rifireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_537 = _out_rifireMux_T_260 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_538 = _out_rifireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_541 = _out_rifireMux_T_260 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_542 = _out_rifireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_545 = _out_rifireMux_T_260 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_546 = _out_rifireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_549 = _out_rifireMux_T_260 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_550 = _out_rifireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_553 = _out_rifireMux_T_260 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_554 = _out_rifireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_557 = _out_rifireMux_T_260 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_558 = _out_rifireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_561 = _out_rifireMux_T_260 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_562 = _out_rifireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_565 = _out_rifireMux_T_260 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_566 = _out_rifireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_569 = _out_rifireMux_T_260 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_570 = _out_rifireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_573 = _out_rifireMux_T_260 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_574 = _out_rifireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_577 = _out_rifireMux_T_260 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_578 = _out_rifireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_581 = _out_rifireMux_T_260 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_582 = _out_rifireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_585 = _out_rifireMux_T_260 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_586 = _out_rifireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_589 = _out_rifireMux_T_260 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_590 = _out_rifireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_593 = _out_rifireMux_T_260 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_594 = _out_rifireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_597 = _out_rifireMux_T_260 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_598 = _out_rifireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_601 = _out_rifireMux_T_260 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_602 = _out_rifireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_605 = _out_rifireMux_T_260 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_606 = _out_rifireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_609 = _out_rifireMux_T_260 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_610 = _out_rifireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_613 = _out_rifireMux_T_260 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_614 = _out_rifireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_617 = _out_rifireMux_T_260 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_618 = _out_rifireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_621 = _out_rifireMux_T_260 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_622 = _out_rifireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_625 = _out_rifireMux_T_260 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_626 = _out_rifireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_629 = _out_rifireMux_T_260 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_630 = _out_rifireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_633 = _out_rifireMux_T_260 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_634 = _out_rifireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_637 = _out_rifireMux_T_260 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_638 = _out_rifireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_641 = _out_rifireMux_T_260 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_642 = _out_rifireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_645 = _out_rifireMux_T_260 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_646 = _out_rifireMux_T_645 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_442 = _out_rifireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_647 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_649 = _out_rifireMux_T_260 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_650 = _out_rifireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_653 = _out_rifireMux_T_260 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_654 = _out_rifireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_657 = _out_rifireMux_T_260 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_658 = _out_rifireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_661 = _out_rifireMux_T_260 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_662 = _out_rifireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_665 = _out_rifireMux_T_260 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_666 = _out_rifireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_669 = _out_rifireMux_T_260 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_670 = _out_rifireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_673 = _out_rifireMux_T_260 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_674 = _out_rifireMux_T_673 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_697 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_698 = _out_rifireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_675 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_677 = _out_rifireMux_T_260 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_678 = _out_rifireMux_T_677 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_931 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_932 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_933 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_934 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_935 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_936 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_937 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_938 = _out_rifireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_679 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_681 = _out_rifireMux_T_260 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_682 = _out_rifireMux_T_681 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_511 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_512 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_513 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_514 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_515 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_516 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_517 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_518 = _out_rifireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_683 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_685 = _out_rifireMux_T_260 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_686 = _out_rifireMux_T_685 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_192 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_193 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_194 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_195 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_196 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_197 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_198 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_199 = _out_rifireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_687 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_689 = _out_rifireMux_T_260 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_690 = _out_rifireMux_T_689 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1091 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1092 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1093 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1094 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1095 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1096 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1097 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1098 = _out_rifireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_691 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_693 = _out_rifireMux_T_260 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_694 = _out_rifireMux_T_693 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_731 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_732 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_733 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_734 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_735 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_736 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_737 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_738 = _out_rifireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_695 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_697 = _out_rifireMux_T_260 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_698 = _out_rifireMux_T_697 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_443 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_444 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_445 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_446 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_447 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_448 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_449 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_450 = _out_rifireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_699 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_701 = _out_rifireMux_T_260 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_702 = _out_rifireMux_T_701 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_112 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_113 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_114 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_115 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_116 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_117 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_118 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_119 = _out_rifireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_703 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_705 = _out_rifireMux_T_260 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_706 = _out_rifireMux_T_705 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1163 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1164 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1165 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1166 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1167 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1168 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1169 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1170 = _out_rifireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_707 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_709 = _out_rifireMux_T_260 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_710 = _out_rifireMux_T_709 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_827 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_828 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_829 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_830 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_831 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_832 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_833 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_834 = _out_rifireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_711 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_713 = _out_rifireMux_T_260 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_714 = _out_rifireMux_T_713 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_657 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_658 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_659 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_660 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_661 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_662 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_663 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_664 = _out_rifireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_715 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_717 = _out_rifireMux_T_260 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_718 = _out_rifireMux_T_717 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_979 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_980 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_981 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_982 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_983 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_984 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_985 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_986 = _out_rifireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_719 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_721 = _out_rifireMux_T_260 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_722 = _out_rifireMux_T_721 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_32 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_33 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_34 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_35 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_36 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_37 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_38 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_39 = _out_rifireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_723 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_725 = _out_rifireMux_T_260 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_726 = _out_rifireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_729 = _out_rifireMux_T_260 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_730 = _out_rifireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_733 = _out_rifireMux_T_260 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_734 = _out_rifireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_737 = _out_rifireMux_T_260 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_738 = _out_rifireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_741 = _out_rifireMux_T_260 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_742 = _out_rifireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_745 = _out_rifireMux_T_260 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_746 = _out_rifireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_749 = _out_rifireMux_T_260 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_750 = _out_rifireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_753 = _out_rifireMux_T_260 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_754 = _out_rifireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_757 = _out_rifireMux_T_260 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_758 = _out_rifireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_761 = _out_rifireMux_T_260 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_762 = _out_rifireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_765 = _out_rifireMux_T_260 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_766 = _out_rifireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_769 = _out_rifireMux_T_260 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_770 = _out_rifireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_773 = _out_rifireMux_T_260 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_774 = _out_rifireMux_T_773 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_495 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_496 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_497 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_498 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_499 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_500 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_501 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_502 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_775 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_777 = _out_rifireMux_T_260 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_778 = _out_rifireMux_T_777 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_467 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_468 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_469 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_470 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_471 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_472 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_473 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_474 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_779 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_781 = _out_rifireMux_T_260 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_782 = _out_rifireMux_T_781 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_755 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_756 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_757 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_758 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_759 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_760 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_761 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_762 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_783 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_785 = _out_rifireMux_T_260 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_786 = _out_rifireMux_T_785 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1131 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1132 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1133 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1134 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1135 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1136 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1137 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1138 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_787 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_789 = _out_rifireMux_T_260 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_790 = _out_rifireMux_T_789 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_240 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_241 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_242 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_243 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_244 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_245 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_246 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_247 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_791 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_793 = _out_rifireMux_T_260 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_794 = _out_rifireMux_T_793 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_248 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_249 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_250 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_251 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_252 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_253 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_254 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_255 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_795 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_797 = _out_rifireMux_T_260 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_798 = _out_rifireMux_T_797 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_475 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_476 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_477 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_478 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_479 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_480 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_481 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_482 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_799 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_801 = _out_rifireMux_T_260 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_802 = _out_rifireMux_T_801 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_771 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_772 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_773 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_774 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_775 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_776 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_777 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_778 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_803 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_805 = _out_rifireMux_T_260 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_806 = _out_rifireMux_T_805 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1099 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1100 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1101 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1102 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1103 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1104 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1105 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1106 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_807 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_809 = _out_rifireMux_T_260 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_810 = _out_rifireMux_T_809 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_336 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_337 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_338 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_339 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_340 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_341 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_342 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_343 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_811 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_813 = _out_rifireMux_T_260 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_814 = _out_rifireMux_T_813 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_0 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_2 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_3 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_4 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_5 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_6 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_7 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_815 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_817 = _out_rifireMux_T_260 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_818 = _out_rifireMux_T_817 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_995 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_996 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_997 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_998 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_999 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1000 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1001 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1002 = _out_rifireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_819 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_821 = _out_rifireMux_T_260 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_822 = _out_rifireMux_T_821 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_699 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_700 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_701 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_702 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_703 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_704 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_705 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_706 = _out_rifireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_823 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_825 = _out_rifireMux_T_260 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_826 = _out_rifireMux_T_825 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_410 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_411 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_412 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_413 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_414 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_415 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_416 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_417 = _out_rifireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_827 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_829 = _out_rifireMux_T_260 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_830 = _out_rifireMux_T_829 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_64 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_65 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_66 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_67 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_68 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_69 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_70 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_71 = _out_rifireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_831 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_833 = _out_rifireMux_T_260 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_834 = _out_rifireMux_T_833 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_907 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_908 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_909 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_910 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_911 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_912 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_913 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_914 = _out_rifireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_835 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_837 = _out_rifireMux_T_260 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_838 = _out_rifireMux_T_837 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_609 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_610 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_611 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_612 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_613 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_614 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_615 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_616 = _out_rifireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_839 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_841 = _out_rifireMux_T_260 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_842 = _out_rifireMux_T_841 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_843 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_844 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_845 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_846 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_847 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_848 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_849 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_850 = _out_rifireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_843 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_845 = _out_rifireMux_T_260 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_846 = _out_rifireMux_T_845 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1043 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1044 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1045 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1046 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1047 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1048 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1049 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1050 = _out_rifireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_847 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_849 = _out_rifireMux_T_260 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_850 = _out_rifireMux_T_849 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_224 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_225 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_226 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_227 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_228 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_229 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_230 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_231 = _out_rifireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_851 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_853 = _out_rifireMux_T_260 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_854 = _out_rifireMux_T_853 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_537 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_538 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_539 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_540 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_541 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_542 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_543 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_544 = _out_rifireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_855 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_857 = _out_rifireMux_T_260 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_858 = _out_rifireMux_T_857 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_569 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_570 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_571 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_572 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_573 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_574 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_575 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_576 = _out_rifireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_859 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_861 = _out_rifireMux_T_260 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_862 = _out_rifireMux_T_861 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_851 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_852 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_853 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_854 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_855 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_856 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_857 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_858 = _out_rifireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_863 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_865 = _out_rifireMux_T_260 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_866 = _out_rifireMux_T_865 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1035 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1036 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1037 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1038 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1039 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1040 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1041 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1042 = _out_rifireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_867 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_869 = _out_rifireMux_T_260 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_870 = _out_rifireMux_T_869 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_144 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_145 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_146 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_147 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_148 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_149 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_150 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_151 = _out_rifireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_871 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_873 = _out_rifireMux_T_260 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_874 = _out_rifireMux_T_873 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_72 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_73 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_74 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_75 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_76 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_77 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_78 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_79 = _out_rifireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_875 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_877 = _out_rifireMux_T_260 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_878 = _out_rifireMux_T_877 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_891 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_892 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_893 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_894 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_895 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_896 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_897 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_898 = _out_rifireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_879 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_881 = _out_rifireMux_T_260 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_882 = _out_rifireMux_T_881 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_715 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_716 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_717 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_718 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_719 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_720 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_721 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_722 = _out_rifireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_883 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_885 = _out_rifireMux_T_260 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_886 = _out_rifireMux_T_885 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_386 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_387 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_388 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_389 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_390 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_391 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_392 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_393 = _out_rifireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_887 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_889 = _out_rifireMux_T_260 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_890 = _out_rifireMux_T_889 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_128 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_129 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_130 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_131 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_132 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_133 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_134 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_135 = _out_rifireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_891 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_893 = _out_rifireMux_T_260 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_894 = _out_rifireMux_T_893 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_963 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_964 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_965 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_966 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_967 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_968 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_969 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_970 = _out_rifireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_895 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_897 = _out_rifireMux_T_260 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_898 = _out_rifireMux_T_897 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_633 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_634 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_635 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_636 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_637 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_638 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_639 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_640 = _out_rifireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_899 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_901 = _out_rifireMux_T_260 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_902 = _out_rifireMux_T_901 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_320 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_321 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_322 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_323 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_324 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_325 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_326 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_327 = _out_rifireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_903 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_905 = _out_rifireMux_T_260 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_906 = _out_rifireMux_T_905 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_553 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_554 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_555 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_556 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_557 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_558 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_559 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_560 = _out_rifireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_907 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_909 = _out_rifireMux_T_260 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_910 = _out_rifireMux_T_909 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_803 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_804 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_805 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_806 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_807 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_808 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_809 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_810 = _out_rifireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_911 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_913 = _out_rifireMux_T_260 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_914 = _out_rifireMux_T_913 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1147 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1148 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1149 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1150 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1151 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1152 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1153 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1154 = _out_rifireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_915 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_917 = _out_rifireMux_T_260 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_918 = _out_rifireMux_T_917 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_176 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_177 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_178 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_179 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_180 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_181 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_182 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_183 = _out_rifireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_919 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_921 = _out_rifireMux_T_260 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_922 = _out_rifireMux_T_921 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_344 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_345 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_346 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_347 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_348 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_349 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_350 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_351 = _out_rifireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_923 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_925 = _out_rifireMux_T_260 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_926 = _out_rifireMux_T_925 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_527 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_528 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_529 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_530 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_531 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_532 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_533 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_534 = _out_rifireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_927 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_929 = _out_rifireMux_T_260 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_930 = _out_rifireMux_T_929 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_795 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_796 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_797 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_798 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_799 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_800 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_801 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_802 = _out_rifireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_931 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_933 = _out_rifireMux_T_260 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_934 = _out_rifireMux_T_933 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1067 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1068 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1069 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1070 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1071 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1072 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1073 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1074 = _out_rifireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_935 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_937 = _out_rifireMux_T_260 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_938 = _out_rifireMux_T_937 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_402 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_403 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_404 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_405 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_406 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_407 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_408 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_409 = _out_rifireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_939 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_941 = _out_rifireMux_T_260 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_942 = _out_rifireMux_T_941 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_24 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_25 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_26 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_27 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_28 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_29 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_30 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_31 = _out_rifireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_943 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_945 = _out_rifireMux_T_260 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_946 = _out_rifireMux_T_945 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_987 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_988 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_989 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_990 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_991 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_992 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_993 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_994 = _out_rifireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_947 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_949 = _out_rifireMux_T_260 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_950 = _out_rifireMux_T_949 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_649 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_650 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_651 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_652 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_653 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_654 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_655 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_656 = _out_rifireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_951 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_953 = _out_rifireMux_T_260 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_954 = _out_rifireMux_T_953 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_459 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_460 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_461 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_462 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_463 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_464 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_465 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_466 = _out_rifireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_955 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_957 = _out_rifireMux_T_260 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_958 = _out_rifireMux_T_957 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_80 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_81 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_82 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_83 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_84 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_85 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_86 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_87 = _out_rifireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_959 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_961 = _out_rifireMux_T_260 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_962 = _out_rifireMux_T_961 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_899 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_900 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_901 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_902 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_903 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_904 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_905 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_906 = _out_rifireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_963 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_965 = _out_rifireMux_T_260 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_966 = _out_rifireMux_T_965 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_577 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_578 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_579 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_580 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_581 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_582 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_583 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_584 = _out_rifireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_967 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_969 = _out_rifireMux_T_260 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_970 = _out_rifireMux_T_969 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_875 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_876 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_877 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_878 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_879 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_880 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_881 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_882 = _out_rifireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_971 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_973 = _out_rifireMux_T_260 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_974 = _out_rifireMux_T_973 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1139 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1140 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1141 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1142 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1143 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1144 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1145 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1146 = _out_rifireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_975 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_977 = _out_rifireMux_T_260 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_978 = _out_rifireMux_T_977 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_184 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_185 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_186 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_187 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_188 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_189 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_190 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_191 = _out_rifireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_979 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_981 = _out_rifireMux_T_260 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_982 = _out_rifireMux_T_981 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_561 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_562 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_563 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_564 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_565 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_566 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_567 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_568 = _out_rifireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_983 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_985 = _out_rifireMux_T_260 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_986 = _out_rifireMux_T_985 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_625 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_626 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_627 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_628 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_629 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_630 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_631 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_632 = _out_rifireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_987 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_989 = _out_rifireMux_T_260 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_990 = _out_rifireMux_T_989 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_883 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_884 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_885 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_886 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_887 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_888 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_889 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_890 = _out_rifireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_991 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_993 = _out_rifireMux_T_260 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_994 = _out_rifireMux_T_993 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1059 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1060 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1061 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1062 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1063 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1064 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1065 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1066 = _out_rifireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_995 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_997 = _out_rifireMux_T_260 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_998 = _out_rifireMux_T_997 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_104 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_105 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_106 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_107 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_108 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_109 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_110 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_111 = _out_rifireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_999 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1001 = _out_rifireMux_T_260 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1002 = _out_rifireMux_T_1001 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_88 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_89 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_90 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_91 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_92 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_93 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_94 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_95 = _out_rifireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1003 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1005 = _out_rifireMux_T_260 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1006 = _out_rifireMux_T_1005 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_971 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_972 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_973 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_974 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_975 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_976 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_977 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_978 = _out_rifireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1007 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1009 = _out_rifireMux_T_260 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1010 = _out_rifireMux_T_1009 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_641 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_642 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_643 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_644 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_645 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_646 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_647 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_648 = _out_rifireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1011 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1013 = _out_rifireMux_T_260 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1014 = _out_rifireMux_T_1013 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_394 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_395 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_396 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_397 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_398 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_399 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_400 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_401 = _out_rifireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1015 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1017 = _out_rifireMux_T_260 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1018 = _out_rifireMux_T_1017 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_136 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_137 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_138 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_139 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_140 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_141 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_142 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_143 = _out_rifireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1019 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1021 = _out_rifireMux_T_260 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1022 = _out_rifireMux_T_1021 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1051 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1052 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1053 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1054 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1055 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1056 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1057 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1058 = _out_rifireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1023 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1025 = _out_rifireMux_T_260 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1026 = _out_rifireMux_T_1025 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_585 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_586 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_587 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_588 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_589 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_590 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_591 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_592 = _out_rifireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1027 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1029 = _out_rifireMux_T_260 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1030 = _out_rifireMux_T_1029 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_328 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_329 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_330 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_331 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_332 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_333 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_334 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_335 = _out_rifireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1031 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1033 = _out_rifireMux_T_260 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1034 = _out_rifireMux_T_1033 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_426 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_427 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_428 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_429 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_430 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_431 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_432 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_433 = _out_rifireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1035 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1037 = _out_rifireMux_T_260 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1038 = _out_rifireMux_T_1037 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_835 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_836 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_837 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_838 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_839 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_840 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_841 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_842 = _out_rifireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1039 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1041 = _out_rifireMux_T_260 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1042 = _out_rifireMux_T_1041 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1107 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1108 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1109 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1110 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1111 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1112 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1113 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1114 = _out_rifireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1043 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1045 = _out_rifireMux_T_260 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1046 = _out_rifireMux_T_1045 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_120 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_121 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_122 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_123 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_124 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_125 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_126 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_127 = _out_rifireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1047 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1049 = _out_rifireMux_T_260 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1050 = _out_rifireMux_T_1049 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_370 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_371 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_372 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_373 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_374 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_375 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_376 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_377 = _out_rifireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1051 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1053 = _out_rifireMux_T_260 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1054 = _out_rifireMux_T_1053 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_723 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_724 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_725 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_726 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_727 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_728 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_729 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_730 = _out_rifireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1055 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1057 = _out_rifireMux_T_260 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1058 = _out_rifireMux_T_1057 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_867 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_868 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_869 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_870 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_871 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_872 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_873 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_874 = _out_rifireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1059 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1061 = _out_rifireMux_T_260 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1062 = _out_rifireMux_T_1061 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1155 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1156 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1157 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1158 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1159 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1160 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1161 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1162 = _out_rifireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1063 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1065 = _out_rifireMux_T_260 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1066 = _out_rifireMux_T_1065 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_296 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_297 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_298 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_299 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_300 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_301 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_302 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_303 = _out_rifireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1067 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1069 = _out_rifireMux_T_260 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1070 = _out_rifireMux_T_1069 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_56 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_57 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_58 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_59 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_60 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_61 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_62 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_63 = _out_rifireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1071 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1073 = _out_rifireMux_T_260 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1074 = _out_rifireMux_T_1073 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_915 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_916 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_917 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_918 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_919 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_920 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_921 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_922 = _out_rifireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1075 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1077 = _out_rifireMux_T_260 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1078 = _out_rifireMux_T_1077 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_593 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_594 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_595 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_596 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_597 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_598 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_599 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_600 = _out_rifireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1079 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1081 = _out_rifireMux_T_260 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1082 = _out_rifireMux_T_1081 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_487 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_488 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_489 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_490 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_491 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_492 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_493 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_494 = _out_rifireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1083 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1085 = _out_rifireMux_T_260 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1086 = _out_rifireMux_T_1085 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_272 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_273 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_274 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_275 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_276 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_277 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_278 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_279 = _out_rifireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1087 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1089 = _out_rifireMux_T_260 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1090 = _out_rifireMux_T_1089 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1003 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1004 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1005 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1006 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1007 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1008 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1009 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1010 = _out_rifireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1091 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1093 = _out_rifireMux_T_260 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1094 = _out_rifireMux_T_1093 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_689 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_690 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_691 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_692 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_693 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_694 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_695 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_696 = _out_rifireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1095 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1097 = _out_rifireMux_T_260 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1098 = _out_rifireMux_T_1097 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_819 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_820 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_821 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_822 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_823 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_824 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_825 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_826 = _out_rifireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1099 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1101 = _out_rifireMux_T_260 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1102 = _out_rifireMux_T_1101 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1083 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1084 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1085 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1086 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1087 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1088 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1089 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1090 = _out_rifireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1103 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1105 = _out_rifireMux_T_260 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1106 = _out_rifireMux_T_1105 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_208 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_209 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_210 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_211 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_212 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_213 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_214 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_215 = _out_rifireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1107 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1109 = _out_rifireMux_T_260 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1110 = _out_rifireMux_T_1109 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_434 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_435 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_436 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_437 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_438 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_439 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_440 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_441 = _out_rifireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1111 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1113 = _out_rifireMux_T_260 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1114 = _out_rifireMux_T_1113 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_707 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_708 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_709 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_710 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_711 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_712 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_713 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_714 = _out_rifireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1115 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1117 = _out_rifireMux_T_260 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1118 = _out_rifireMux_T_1117 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1011 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1012 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1013 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1014 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1015 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1016 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1017 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1018 = _out_rifireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1119 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1121 = _out_rifireMux_T_260 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1122 = _out_rifireMux_T_1121 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1171 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1172 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1173 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1174 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1175 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1176 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1177 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1178 = _out_rifireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1123 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1125 = _out_rifireMux_T_260 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1126 = _out_rifireMux_T_1125 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_168 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_169 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_170 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_171 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_172 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_173 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_174 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_175 = _out_rifireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1127 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1129 = _out_rifireMux_T_260 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1130 = _out_rifireMux_T_1129 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_40 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_41 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_42 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_43 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_44 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_45 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_46 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_47 = _out_rifireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1131 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1133 = _out_rifireMux_T_260 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1134 = _out_rifireMux_T_1133 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_923 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_924 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_925 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_926 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_927 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_928 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_929 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_930 = _out_rifireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1135 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1137 = _out_rifireMux_T_260 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1138 = _out_rifireMux_T_1137 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_665 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_666 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_667 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_668 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_669 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_670 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_671 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_672 = _out_rifireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1139 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1141 = _out_rifireMux_T_260 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1142 = _out_rifireMux_T_1141 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_304 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_305 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_306 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_307 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_308 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_309 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_310 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_311 = _out_rifireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1143 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1145 = _out_rifireMux_T_260 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1146 = _out_rifireMux_T_1145 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_232 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_233 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_234 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_235 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_236 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_237 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_238 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_239 = _out_rifireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1147 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1149 = _out_rifireMux_T_260 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1150 = _out_rifireMux_T_1149 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1179 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1180 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1181 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1182 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1183 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1184 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1185 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1186 = _out_rifireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1151 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1153 = _out_rifireMux_T_260 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1154 = _out_rifireMux_T_1153 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_763 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_764 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_765 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_766 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_767 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_768 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_769 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_770 = _out_rifireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1155 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1157 = _out_rifireMux_T_260 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1158 = _out_rifireMux_T_1157 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_378 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_379 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_380 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_381 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_382 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_383 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_384 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_385 = _out_rifireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1159 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1161 = _out_rifireMux_T_260 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1162 = _out_rifireMux_T_1161 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_418 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_419 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_420 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_421 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_422 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_423 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_424 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_425 = _out_rifireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1163 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1165 = _out_rifireMux_T_260 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1166 = _out_rifireMux_T_1165 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_779 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_780 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_781 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_782 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_783 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_784 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_785 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_786 = _out_rifireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1167 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1169 = _out_rifireMux_T_260 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1170 = _out_rifireMux_T_1169 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1203 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1204 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1205 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1206 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1207 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1208 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1209 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1210 = _out_rifireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1171 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1173 = _out_rifireMux_T_260 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1174 = _out_rifireMux_T_1173 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_152 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_153 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_154 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_155 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_156 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_157 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_158 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_159 = _out_rifireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1175 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1177 = _out_rifireMux_T_260 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1178 = _out_rifireMux_T_1177 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_354 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_355 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_356 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_357 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_358 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_359 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_360 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_361 = _out_rifireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1179 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1181 = _out_rifireMux_T_260 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1182 = _out_rifireMux_T_1181 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_673 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_674 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_675 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_676 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_677 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_678 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_679 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_680 = _out_rifireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1183 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1185 = _out_rifireMux_T_260 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1186 = _out_rifireMux_T_1185 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_947 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_948 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_949 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_950 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_951 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_952 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_953 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_954 = _out_rifireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1187 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1189 = _out_rifireMux_T_260 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1190 = _out_rifireMux_T_1189 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1187 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1188 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1189 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1190 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1191 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1192 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1193 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1194 = _out_rifireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1191 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1193 = _out_rifireMux_T_260 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1194 = _out_rifireMux_T_1193 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_280 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_281 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_282 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_283 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_284 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_285 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_286 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_287 = _out_rifireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1195 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1197 = _out_rifireMux_T_260 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1198 = _out_rifireMux_T_1197 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_16 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_17 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_18 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_19 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_20 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_21 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_22 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_23 = _out_rifireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1199 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1201 = _out_rifireMux_T_260 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1202 = _out_rifireMux_T_1201 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1019 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1020 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1021 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1022 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1023 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1024 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1025 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1026 = _out_rifireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1203 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1205 = _out_rifireMux_T_260 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1206 = _out_rifireMux_T_1205 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_617 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_618 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_619 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_620 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_621 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_622 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_623 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_624 = _out_rifireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1207 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1209 = _out_rifireMux_T_260 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1210 = _out_rifireMux_T_1209 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_503 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_504 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_505 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_506 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_507 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_508 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_509 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_510 = _out_rifireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1211 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1213 = _out_rifireMux_T_260 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1214 = _out_rifireMux_T_1213 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_200 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_201 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_202 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_203 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_204 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_205 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_206 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_207 = _out_rifireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1215 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1217 = _out_rifireMux_T_260 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1218 = _out_rifireMux_T_1217 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1115 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1116 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1117 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1118 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1119 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1120 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1121 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1122 = _out_rifireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1219 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1221 = _out_rifireMux_T_260 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1222 = _out_rifireMux_T_1221 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_739 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_740 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_741 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_742 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_743 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_744 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_745 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_746 = _out_rifireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1223 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1225 = _out_rifireMux_T_260 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1226 = _out_rifireMux_T_1225 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_787 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_788 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_789 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_790 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_791 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_792 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_793 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_794 = _out_rifireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1227 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1229 = _out_rifireMux_T_260 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1230 = _out_rifireMux_T_1229 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1123 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1124 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1125 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1126 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1127 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1128 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1129 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1130 = _out_rifireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1231 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1233 = _out_rifireMux_T_260 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1234 = _out_rifireMux_T_1233 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_256 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_257 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_258 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_259 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_260 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_261 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_262 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_263 = _out_rifireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1235 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1237 = _out_rifireMux_T_260 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1238 = _out_rifireMux_T_1237 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_519 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_520 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_521 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_522 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_523 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_524 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_525 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_526 = _out_rifireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1239 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1241 = _out_rifireMux_T_260 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1242 = _out_rifireMux_T_1241 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_681 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_682 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_683 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_684 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_685 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_686 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_687 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_688 = _out_rifireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1243 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1245 = _out_rifireMux_T_260 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1246 = _out_rifireMux_T_1245 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1027 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1028 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1029 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1030 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1031 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1032 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1033 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1034 = _out_rifireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1247 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1249 = _out_rifireMux_T_260 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1250 = _out_rifireMux_T_1249 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_48 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_49 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_50 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_51 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_52 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_53 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_54 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_55 = _out_rifireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1251 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1253 = _out_rifireMux_T_260 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1254 = _out_rifireMux_T_1253 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_288 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_289 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_290 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_291 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_292 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_293 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_294 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_295 = _out_rifireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1255 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1257 = _out_rifireMux_T_260 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1258 = _out_rifireMux_T_1257 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_8 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_9 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_10 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_11 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_12 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_13 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_14 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_15 = _out_rifireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1259 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1261 = _out_rifireMux_T_260 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1262 = _out_rifireMux_T_1261 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_939 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_940 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_941 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_942 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_943 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_944 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_945 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_946 = _out_rifireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1263 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1265 = _out_rifireMux_T_260 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1266 = _out_rifireMux_T_1265 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_747 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_748 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_749 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_750 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_751 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_752 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_753 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_754 = _out_rifireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1267 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1269 = _out_rifireMux_T_260 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1270 = _out_rifireMux_T_1269 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_362 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_363 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_364 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_365 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_366 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_367 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_368 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_369 = _out_rifireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1271 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1273 = _out_rifireMux_T_260 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1274 = _out_rifireMux_T_1273 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_216 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_217 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_218 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_219 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_220 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_221 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_222 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_223 = _out_rifireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1275 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1277 = _out_rifireMux_T_260 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1278 = _out_rifireMux_T_1277 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1195 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1196 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1197 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1198 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1199 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1200 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1201 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_1202 = _out_rifireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1279 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1281 = _out_rifireMux_T_260 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_1282 = _out_rifireMux_T_1281 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_811 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_812 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_813 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_814 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_815 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_816 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_817 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_rivalid_1_818 = _out_rifireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1283 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_262 = _out_wifireMux_T_260 & _out_wifireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_263 = _out_wifireMux_T_262 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_264 = _out_wifireMux_T_263 & _out_T_1716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_451 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_452 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_453 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_454 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_455 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_456 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_457 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_458 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_265 = ~_out_T_1716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_267 = _out_wifireMux_T_262 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_268 = _out_wifireMux_T_267 & _out_T_1624; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_96 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_97 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_98 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_99 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_100 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_101 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_102 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_103 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_269 = ~_out_T_1624; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_271 = _out_wifireMux_T_262 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_272 = _out_wifireMux_T_271 & _out_T_1846; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_955 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_956 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_957 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_958 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_959 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_960 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_961 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_962 = _out_wifireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_273 = ~_out_T_1846; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_275 = _out_wifireMux_T_262 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_276 = _out_wifireMux_T_275 & _out_T_1756; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_601 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_602 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_603 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_604 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_605 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_606 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_607 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_608 = _out_wifireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_277 = ~_out_T_1756; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_279 = _out_wifireMux_T_262 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_280 = _out_wifireMux_T_279 & _out_T_1678; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_312 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_313 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_314 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_315 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_316 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_317 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_318 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_319 = _out_wifireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_281 = ~_out_T_1678; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_283 = _out_wifireMux_T_262 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_284 = _out_wifireMux_T_283 & _out_T_1640; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_160 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_161 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_162 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_163 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_164 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_165 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_166 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_167 = _out_wifireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_285 = ~_out_T_1640; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_287 = _out_wifireMux_T_262 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_288 = _out_wifireMux_T_287 & _out_T_1876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1075 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1076 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1077 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1078 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1079 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1080 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1081 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1082 = _out_wifireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_289 = ~_out_T_1876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_291 = _out_wifireMux_T_262 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_292 = _out_wifireMux_T_291 & _out_T_1822; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_859 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_860 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_861 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_862 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_863 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_864 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_865 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_866 = _out_wifireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_293 = ~_out_T_1822; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_295 = _out_wifireMux_T_262 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_296 = _out_wifireMux_T_295 & _out_T_1742; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_545 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_546 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_547 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_548 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_549 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_550 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_551 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_552 = _out_wifireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_297 = ~_out_T_1742; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_299 = _out_wifireMux_T_262 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_300 = _out_wifireMux_T_299 & _out_T_1666; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_264 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_265 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_266 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_267 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_268 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_269 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_270 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_271 = _out_wifireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_301 = ~_out_T_1666; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_303 = _out_wifireMux_T_262 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_304 = _out_wifireMux_T_303 & _out_T_1724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_483 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_484 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_485 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_486 = _out_wifireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_305 = ~_out_T_1724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_307 = _out_wifireMux_T_262 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_308 = _out_wifireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_311 = _out_wifireMux_T_262 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_312 = _out_wifireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_315 = _out_wifireMux_T_262 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_316 = _out_wifireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_319 = _out_wifireMux_T_262 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_320 = _out_wifireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_323 = _out_wifireMux_T_262 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_324 = _out_wifireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_327 = _out_wifireMux_T_262 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_328 = _out_wifireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_331 = _out_wifireMux_T_262 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_332 = _out_wifireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_335 = _out_wifireMux_T_262 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_336 = _out_wifireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_339 = _out_wifireMux_T_262 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_340 = _out_wifireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_343 = _out_wifireMux_T_262 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_344 = _out_wifireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_347 = _out_wifireMux_T_262 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_348 = _out_wifireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_351 = _out_wifireMux_T_262 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_352 = _out_wifireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_355 = _out_wifireMux_T_262 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_356 = _out_wifireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_359 = _out_wifireMux_T_262 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_360 = _out_wifireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_363 = _out_wifireMux_T_262 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_364 = _out_wifireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_367 = _out_wifireMux_T_262 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_368 = _out_wifireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_371 = _out_wifireMux_T_262 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_372 = _out_wifireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_375 = _out_wifireMux_T_262 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_376 = _out_wifireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_379 = _out_wifireMux_T_262 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_380 = _out_wifireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_383 = _out_wifireMux_T_262 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_384 = _out_wifireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_387 = _out_wifireMux_T_262 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_388 = _out_wifireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_391 = _out_wifireMux_T_262 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_392 = _out_wifireMux_T_391 & _out_T_1738; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_535 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_536 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_393 = ~_out_T_1738; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_395 = _out_wifireMux_T_262 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_396 = _out_wifireMux_T_395 & _out_T_1688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_352 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_353 = _out_wifireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_397 = ~_out_T_1688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_399 = _out_wifireMux_T_262 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_400 = _out_wifireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_403 = _out_wifireMux_T_262 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_404 = _out_wifireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_407 = _out_wifireMux_T_262 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_408 = _out_wifireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_411 = _out_wifireMux_T_262 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_412 = _out_wifireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_415 = _out_wifireMux_T_262 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_416 = _out_wifireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_419 = _out_wifireMux_T_262 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_420 = _out_wifireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_423 = _out_wifireMux_T_262 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_424 = _out_wifireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_427 = _out_wifireMux_T_262 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_428 = _out_wifireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_431 = _out_wifireMux_T_262 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_432 = _out_wifireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_435 = _out_wifireMux_T_262 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_436 = _out_wifireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_439 = _out_wifireMux_T_262 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_440 = _out_wifireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_443 = _out_wifireMux_T_262 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_444 = _out_wifireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_447 = _out_wifireMux_T_262 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_448 = _out_wifireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_451 = _out_wifireMux_T_262 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_452 = _out_wifireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_455 = _out_wifireMux_T_262 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_456 = _out_wifireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_459 = _out_wifireMux_T_262 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_460 = _out_wifireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_463 = _out_wifireMux_T_262 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_464 = _out_wifireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_467 = _out_wifireMux_T_262 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_468 = _out_wifireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_471 = _out_wifireMux_T_262 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_472 = _out_wifireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_475 = _out_wifireMux_T_262 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_476 = _out_wifireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_479 = _out_wifireMux_T_262 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_480 = _out_wifireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_483 = _out_wifireMux_T_262 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_484 = _out_wifireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_487 = _out_wifireMux_T_262 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_488 = _out_wifireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_491 = _out_wifireMux_T_262 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_492 = _out_wifireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_495 = _out_wifireMux_T_262 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_496 = _out_wifireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_499 = _out_wifireMux_T_262 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_500 = _out_wifireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_503 = _out_wifireMux_T_262 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_504 = _out_wifireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_507 = _out_wifireMux_T_262 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_508 = _out_wifireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_511 = _out_wifireMux_T_262 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_512 = _out_wifireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_515 = _out_wifireMux_T_262 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_516 = _out_wifireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_519 = _out_wifireMux_T_262 & out_frontSel_64; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_520 = _out_wifireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_523 = _out_wifireMux_T_262 & out_frontSel_65; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_524 = _out_wifireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_527 = _out_wifireMux_T_262 & out_frontSel_66; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_528 = _out_wifireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_531 = _out_wifireMux_T_262 & out_frontSel_67; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_532 = _out_wifireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_535 = _out_wifireMux_T_262 & out_frontSel_68; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_536 = _out_wifireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_539 = _out_wifireMux_T_262 & out_frontSel_69; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_540 = _out_wifireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_543 = _out_wifireMux_T_262 & out_frontSel_70; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_544 = _out_wifireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_547 = _out_wifireMux_T_262 & out_frontSel_71; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_548 = _out_wifireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_551 = _out_wifireMux_T_262 & out_frontSel_72; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_552 = _out_wifireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_555 = _out_wifireMux_T_262 & out_frontSel_73; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_556 = _out_wifireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_559 = _out_wifireMux_T_262 & out_frontSel_74; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_560 = _out_wifireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_563 = _out_wifireMux_T_262 & out_frontSel_75; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_564 = _out_wifireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_567 = _out_wifireMux_T_262 & out_frontSel_76; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_568 = _out_wifireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_571 = _out_wifireMux_T_262 & out_frontSel_77; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_572 = _out_wifireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_575 = _out_wifireMux_T_262 & out_frontSel_78; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_576 = _out_wifireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_579 = _out_wifireMux_T_262 & out_frontSel_79; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_580 = _out_wifireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_583 = _out_wifireMux_T_262 & out_frontSel_80; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_584 = _out_wifireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_587 = _out_wifireMux_T_262 & out_frontSel_81; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_588 = _out_wifireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_591 = _out_wifireMux_T_262 & out_frontSel_82; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_592 = _out_wifireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_595 = _out_wifireMux_T_262 & out_frontSel_83; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_596 = _out_wifireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_599 = _out_wifireMux_T_262 & out_frontSel_84; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_600 = _out_wifireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_603 = _out_wifireMux_T_262 & out_frontSel_85; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_604 = _out_wifireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_607 = _out_wifireMux_T_262 & out_frontSel_86; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_608 = _out_wifireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_611 = _out_wifireMux_T_262 & out_frontSel_87; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_612 = _out_wifireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_615 = _out_wifireMux_T_262 & out_frontSel_88; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_616 = _out_wifireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_619 = _out_wifireMux_T_262 & out_frontSel_89; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_620 = _out_wifireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_623 = _out_wifireMux_T_262 & out_frontSel_90; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_624 = _out_wifireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_627 = _out_wifireMux_T_262 & out_frontSel_91; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_628 = _out_wifireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_631 = _out_wifireMux_T_262 & out_frontSel_92; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_632 = _out_wifireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_635 = _out_wifireMux_T_262 & out_frontSel_93; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_636 = _out_wifireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_639 = _out_wifireMux_T_262 & out_frontSel_94; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_640 = _out_wifireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_643 = _out_wifireMux_T_262 & out_frontSel_95; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_644 = _out_wifireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_647 = _out_wifireMux_T_262 & out_frontSel_96; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_648 = _out_wifireMux_T_647 & _out_T_1712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_442 = _out_wifireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_649 = ~_out_T_1712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_651 = _out_wifireMux_T_262 & out_frontSel_97; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_652 = _out_wifireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_655 = _out_wifireMux_T_262 & out_frontSel_98; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_656 = _out_wifireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_659 = _out_wifireMux_T_262 & out_frontSel_99; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_660 = _out_wifireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_663 = _out_wifireMux_T_262 & out_frontSel_100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_664 = _out_wifireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_667 = _out_wifireMux_T_262 & out_frontSel_101; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_668 = _out_wifireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_671 = _out_wifireMux_T_262 & out_frontSel_102; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_672 = _out_wifireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_675 = _out_wifireMux_T_262 & out_frontSel_103; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_676 = _out_wifireMux_T_675 & _out_T_1780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_697 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_698 = _out_wifireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_677 = ~_out_T_1780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_679 = _out_wifireMux_T_262 & out_frontSel_104; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_680 = _out_wifireMux_T_679 & _out_T_1840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_931 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_932 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_933 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_934 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_935 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_936 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_937 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_938 = _out_wifireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_681 = ~_out_T_1840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_683 = _out_wifireMux_T_262 & out_frontSel_105; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_684 = _out_wifireMux_T_683 & _out_T_1732; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_511 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_512 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_513 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_514 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_515 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_516 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_517 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_518 = _out_wifireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_685 = ~_out_T_1732; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_687 = _out_wifireMux_T_262 & out_frontSel_106; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_688 = _out_wifireMux_T_687 & _out_T_1648; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_192 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_193 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_194 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_195 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_196 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_197 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_198 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_199 = _out_wifireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_689 = ~_out_T_1648; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_691 = _out_wifireMux_T_262 & out_frontSel_107; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_692 = _out_wifireMux_T_691 & _out_T_1880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1091 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1092 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1093 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1094 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1095 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1096 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1097 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1098 = _out_wifireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_693 = ~_out_T_1880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_695 = _out_wifireMux_T_262 & out_frontSel_108; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_696 = _out_wifireMux_T_695 & _out_T_1790; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_731 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_732 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_733 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_734 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_735 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_736 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_737 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_738 = _out_wifireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_697 = ~_out_T_1790; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_699 = _out_wifireMux_T_262 & out_frontSel_109; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_700 = _out_wifireMux_T_699 & _out_T_1714; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_443 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_444 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_445 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_446 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_447 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_448 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_449 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_450 = _out_wifireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_701 = ~_out_T_1714; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_703 = _out_wifireMux_T_262 & out_frontSel_110; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_704 = _out_wifireMux_T_703 & _out_T_1628; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_112 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_113 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_114 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_115 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_116 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_117 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_118 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_119 = _out_wifireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_705 = ~_out_T_1628; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_707 = _out_wifireMux_T_262 & out_frontSel_111; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_708 = _out_wifireMux_T_707 & _out_T_1898; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1163 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1164 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1165 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1166 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1167 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1168 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1169 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1170 = _out_wifireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_709 = ~_out_T_1898; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_711 = _out_wifireMux_T_262 & out_frontSel_112; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_712 = _out_wifireMux_T_711 & _out_T_1814; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_827 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_828 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_829 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_830 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_831 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_832 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_833 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_834 = _out_wifireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_713 = ~_out_T_1814; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_715 = _out_wifireMux_T_262 & out_frontSel_113; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_716 = _out_wifireMux_T_715 & _out_T_1770; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_657 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_658 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_659 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_660 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_661 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_662 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_663 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_664 = _out_wifireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_717 = ~_out_T_1770; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_719 = _out_wifireMux_T_262 & out_frontSel_114; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_720 = _out_wifireMux_T_719 & _out_T_1852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_979 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_980 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_981 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_982 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_983 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_984 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_985 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_986 = _out_wifireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_721 = ~_out_T_1852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_723 = _out_wifireMux_T_262 & out_frontSel_115; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_724 = _out_wifireMux_T_723 & _out_T_1608; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_32 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_33 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_34 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_35 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_36 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_37 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_38 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_39 = _out_wifireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_725 = ~_out_T_1608; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_727 = _out_wifireMux_T_262 & out_frontSel_116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_728 = _out_wifireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_731 = _out_wifireMux_T_262 & out_frontSel_117; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_732 = _out_wifireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_735 = _out_wifireMux_T_262 & out_frontSel_118; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_736 = _out_wifireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_739 = _out_wifireMux_T_262 & out_frontSel_119; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_740 = _out_wifireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_743 = _out_wifireMux_T_262 & out_frontSel_120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_744 = _out_wifireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_747 = _out_wifireMux_T_262 & out_frontSel_121; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_748 = _out_wifireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_751 = _out_wifireMux_T_262 & out_frontSel_122; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_752 = _out_wifireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_755 = _out_wifireMux_T_262 & out_frontSel_123; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_756 = _out_wifireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_759 = _out_wifireMux_T_262 & out_frontSel_124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_760 = _out_wifireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_763 = _out_wifireMux_T_262 & out_frontSel_125; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_764 = _out_wifireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_767 = _out_wifireMux_T_262 & out_frontSel_126; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_768 = _out_wifireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_771 = _out_wifireMux_T_262 & out_frontSel_127; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_772 = _out_wifireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_775 = _out_wifireMux_T_262 & out_frontSel_128; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_776 = _out_wifireMux_T_775 & _out_T_1728; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_495 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_496 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_497 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_498 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_499 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_500 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_501 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_502 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_777 = ~_out_T_1728; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_779 = _out_wifireMux_T_262 & out_frontSel_129; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_780 = _out_wifireMux_T_779 & _out_T_1720; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_467 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_468 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_469 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_470 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_471 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_472 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_473 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_474 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_781 = ~_out_T_1720; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_783 = _out_wifireMux_T_262 & out_frontSel_130; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_784 = _out_wifireMux_T_783 & _out_T_1796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_755 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_756 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_757 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_758 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_759 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_760 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_761 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_762 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_785 = ~_out_T_1796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_787 = _out_wifireMux_T_262 & out_frontSel_131; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_788 = _out_wifireMux_T_787 & _out_T_1890; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1131 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1132 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1133 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1134 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1135 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1136 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1137 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1138 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_789 = ~_out_T_1890; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_791 = _out_wifireMux_T_262 & out_frontSel_132; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_792 = _out_wifireMux_T_791 & _out_T_1660; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_240 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_241 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_242 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_243 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_244 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_245 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_246 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_247 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_793 = ~_out_T_1660; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_795 = _out_wifireMux_T_262 & out_frontSel_133; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_796 = _out_wifireMux_T_795 & _out_T_1662; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_248 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_249 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_250 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_251 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_252 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_253 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_254 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_255 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_797 = ~_out_T_1662; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_799 = _out_wifireMux_T_262 & out_frontSel_134; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_800 = _out_wifireMux_T_799 & _out_T_1722; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_475 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_476 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_477 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_478 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_479 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_480 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_481 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_482 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_801 = ~_out_T_1722; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_803 = _out_wifireMux_T_262 & out_frontSel_135; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_804 = _out_wifireMux_T_803 & _out_T_1800; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_771 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_772 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_773 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_774 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_775 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_776 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_777 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_778 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_805 = ~_out_T_1800; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_807 = _out_wifireMux_T_262 & out_frontSel_136; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_808 = _out_wifireMux_T_807 & _out_T_1882; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1099 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1100 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1101 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1102 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1103 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1104 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1105 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1106 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_809 = ~_out_T_1882; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_811 = _out_wifireMux_T_262 & out_frontSel_137; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_812 = _out_wifireMux_T_811 & _out_T_1684; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_336 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_337 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_338 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_339 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_340 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_341 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_342 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_343 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_813 = ~_out_T_1684; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_815 = _out_wifireMux_T_262 & out_frontSel_138; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_816 = _out_wifireMux_T_815 & _out_T_1600; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_0 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_2 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_3 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_4 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_5 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_6 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_7 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_817 = ~_out_T_1600; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_819 = _out_wifireMux_T_262 & out_frontSel_139; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_820 = _out_wifireMux_T_819 & _out_T_1856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_995 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_996 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_997 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_998 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_999 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1000 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1001 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1002 = _out_wifireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_821 = ~_out_T_1856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_823 = _out_wifireMux_T_262 & out_frontSel_140; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_824 = _out_wifireMux_T_823 & _out_T_1782; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_699 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_700 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_701 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_702 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_703 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_704 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_705 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_706 = _out_wifireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_825 = ~_out_T_1782; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_827 = _out_wifireMux_T_262 & out_frontSel_141; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_828 = _out_wifireMux_T_827 & _out_T_1704; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_410 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_411 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_412 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_413 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_414 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_415 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_416 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_417 = _out_wifireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_829 = ~_out_T_1704; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_831 = _out_wifireMux_T_262 & out_frontSel_142; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_832 = _out_wifireMux_T_831 & _out_T_1616; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_64 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_65 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_66 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_67 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_68 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_69 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_70 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_71 = _out_wifireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_833 = ~_out_T_1616; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_835 = _out_wifireMux_T_262 & out_frontSel_143; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_836 = _out_wifireMux_T_835 & _out_T_1834; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_907 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_908 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_909 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_910 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_911 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_912 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_913 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_914 = _out_wifireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_837 = ~_out_T_1834; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_839 = _out_wifireMux_T_262 & out_frontSel_144; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_840 = _out_wifireMux_T_839 & _out_T_1758; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_609 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_610 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_611 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_612 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_613 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_614 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_615 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_616 = _out_wifireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_841 = ~_out_T_1758; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_843 = _out_wifireMux_T_262 & out_frontSel_145; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_844 = _out_wifireMux_T_843 & _out_T_1818; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_843 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_844 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_845 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_846 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_847 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_848 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_849 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_850 = _out_wifireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_845 = ~_out_T_1818; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_847 = _out_wifireMux_T_262 & out_frontSel_146; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_848 = _out_wifireMux_T_847 & _out_T_1868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1043 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1044 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1045 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1046 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1047 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1048 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1049 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1050 = _out_wifireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_849 = ~_out_T_1868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_851 = _out_wifireMux_T_262 & out_frontSel_147; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_852 = _out_wifireMux_T_851 & _out_T_1656; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_224 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_225 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_226 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_227 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_228 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_229 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_230 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_231 = _out_wifireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_853 = ~_out_T_1656; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_855 = _out_wifireMux_T_262 & out_frontSel_148; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_856 = _out_wifireMux_T_855 & _out_T_1740; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_537 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_538 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_539 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_540 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_541 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_542 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_543 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_544 = _out_wifireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_857 = ~_out_T_1740; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_859 = _out_wifireMux_T_262 & out_frontSel_149; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_860 = _out_wifireMux_T_859 & _out_T_1748; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_569 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_570 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_571 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_572 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_573 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_574 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_575 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_576 = _out_wifireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_861 = ~_out_T_1748; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_863 = _out_wifireMux_T_262 & out_frontSel_150; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_864 = _out_wifireMux_T_863 & _out_T_1820; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_851 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_852 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_853 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_854 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_855 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_856 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_857 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_858 = _out_wifireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_865 = ~_out_T_1820; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_867 = _out_wifireMux_T_262 & out_frontSel_151; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_868 = _out_wifireMux_T_867 & _out_T_1866; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1035 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1036 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1037 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1038 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1039 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1040 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1041 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1042 = _out_wifireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_869 = ~_out_T_1866; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_871 = _out_wifireMux_T_262 & out_frontSel_152; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_872 = _out_wifireMux_T_871 & _out_T_1636; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_144 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_145 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_146 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_147 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_148 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_149 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_150 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_151 = _out_wifireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_873 = ~_out_T_1636; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_875 = _out_wifireMux_T_262 & out_frontSel_153; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_876 = _out_wifireMux_T_875 & _out_T_1618; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_72 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_73 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_74 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_75 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_76 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_77 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_78 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_79 = _out_wifireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_877 = ~_out_T_1618; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_879 = _out_wifireMux_T_262 & out_frontSel_154; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_880 = _out_wifireMux_T_879 & _out_T_1830; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_891 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_892 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_893 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_894 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_895 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_896 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_897 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_898 = _out_wifireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_881 = ~_out_T_1830; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_883 = _out_wifireMux_T_262 & out_frontSel_155; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_884 = _out_wifireMux_T_883 & _out_T_1786; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_715 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_716 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_717 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_718 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_719 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_720 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_721 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_722 = _out_wifireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_885 = ~_out_T_1786; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_887 = _out_wifireMux_T_262 & out_frontSel_156; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_888 = _out_wifireMux_T_887 & _out_T_1698; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_386 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_387 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_388 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_389 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_390 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_391 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_392 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_393 = _out_wifireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_889 = ~_out_T_1698; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_891 = _out_wifireMux_T_262 & out_frontSel_157; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_892 = _out_wifireMux_T_891 & _out_T_1632; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_128 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_129 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_130 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_131 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_132 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_133 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_134 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_135 = _out_wifireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_893 = ~_out_T_1632; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_895 = _out_wifireMux_T_262 & out_frontSel_158; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_896 = _out_wifireMux_T_895 & _out_T_1848; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_963 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_964 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_965 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_966 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_967 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_968 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_969 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_970 = _out_wifireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_897 = ~_out_T_1848; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_899 = _out_wifireMux_T_262 & out_frontSel_159; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_900 = _out_wifireMux_T_899 & _out_T_1764; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_633 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_634 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_635 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_636 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_637 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_638 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_639 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_640 = _out_wifireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_901 = ~_out_T_1764; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_903 = _out_wifireMux_T_262 & out_frontSel_160; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_904 = _out_wifireMux_T_903 & _out_T_1680; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_320 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_321 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_322 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_323 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_324 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_325 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_326 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_327 = _out_wifireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_905 = ~_out_T_1680; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_907 = _out_wifireMux_T_262 & out_frontSel_161; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_908 = _out_wifireMux_T_907 & _out_T_1744; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_553 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_554 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_555 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_556 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_557 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_558 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_559 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_560 = _out_wifireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_909 = ~_out_T_1744; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_911 = _out_wifireMux_T_262 & out_frontSel_162; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_912 = _out_wifireMux_T_911 & _out_T_1808; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_803 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_804 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_805 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_806 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_807 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_808 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_809 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_810 = _out_wifireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_913 = ~_out_T_1808; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_915 = _out_wifireMux_T_262 & out_frontSel_163; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_916 = _out_wifireMux_T_915 & _out_T_1894; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1147 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1148 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1149 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1150 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1151 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1152 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1153 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1154 = _out_wifireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_917 = ~_out_T_1894; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_919 = _out_wifireMux_T_262 & out_frontSel_164; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_920 = _out_wifireMux_T_919 & _out_T_1644; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_176 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_177 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_178 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_179 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_180 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_181 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_182 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_183 = _out_wifireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_921 = ~_out_T_1644; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_923 = _out_wifireMux_T_262 & out_frontSel_165; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_924 = _out_wifireMux_T_923 & _out_T_1686; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_344 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_345 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_346 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_347 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_348 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_349 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_350 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_351 = _out_wifireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_925 = ~_out_T_1686; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_927 = _out_wifireMux_T_262 & out_frontSel_166; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_928 = _out_wifireMux_T_927 & _out_T_1736; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_527 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_528 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_529 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_530 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_531 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_532 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_533 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_534 = _out_wifireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_929 = ~_out_T_1736; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_931 = _out_wifireMux_T_262 & out_frontSel_167; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_932 = _out_wifireMux_T_931 & _out_T_1806; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_795 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_796 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_797 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_798 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_799 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_800 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_801 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_802 = _out_wifireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_933 = ~_out_T_1806; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_935 = _out_wifireMux_T_262 & out_frontSel_168; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_936 = _out_wifireMux_T_935 & _out_T_1874; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1067 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1068 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1069 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1070 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1071 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1072 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1073 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1074 = _out_wifireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_937 = ~_out_T_1874; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_939 = _out_wifireMux_T_262 & out_frontSel_169; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_940 = _out_wifireMux_T_939 & _out_T_1702; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_402 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_403 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_404 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_405 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_406 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_407 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_408 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_409 = _out_wifireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_941 = ~_out_T_1702; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_943 = _out_wifireMux_T_262 & out_frontSel_170; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_944 = _out_wifireMux_T_943 & _out_T_1606; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_24 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_25 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_26 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_27 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_28 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_29 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_30 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_31 = _out_wifireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_945 = ~_out_T_1606; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_947 = _out_wifireMux_T_262 & out_frontSel_171; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_948 = _out_wifireMux_T_947 & _out_T_1854; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_987 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_988 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_989 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_990 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_991 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_992 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_993 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_994 = _out_wifireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_949 = ~_out_T_1854; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_951 = _out_wifireMux_T_262 & out_frontSel_172; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_952 = _out_wifireMux_T_951 & _out_T_1768; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_649 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_650 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_651 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_652 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_653 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_654 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_655 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_656 = _out_wifireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_953 = ~_out_T_1768; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_955 = _out_wifireMux_T_262 & out_frontSel_173; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_956 = _out_wifireMux_T_955 & _out_T_1718; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_459 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_460 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_461 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_462 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_463 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_464 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_465 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_466 = _out_wifireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_957 = ~_out_T_1718; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_959 = _out_wifireMux_T_262 & out_frontSel_174; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_960 = _out_wifireMux_T_959 & _out_T_1620; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_80 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_81 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_82 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_83 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_84 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_85 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_86 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_87 = _out_wifireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_961 = ~_out_T_1620; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_963 = _out_wifireMux_T_262 & out_frontSel_175; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_964 = _out_wifireMux_T_963 & _out_T_1832; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_899 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_900 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_901 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_902 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_903 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_904 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_905 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_906 = _out_wifireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_965 = ~_out_T_1832; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_967 = _out_wifireMux_T_262 & out_frontSel_176; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_968 = _out_wifireMux_T_967 & _out_T_1750; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_577 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_578 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_579 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_580 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_581 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_582 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_583 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_584 = _out_wifireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_969 = ~_out_T_1750; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_971 = _out_wifireMux_T_262 & out_frontSel_177; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_972 = _out_wifireMux_T_971 & _out_T_1826; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_875 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_876 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_877 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_878 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_879 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_880 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_881 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_882 = _out_wifireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_973 = ~_out_T_1826; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_975 = _out_wifireMux_T_262 & out_frontSel_178; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_976 = _out_wifireMux_T_975 & _out_T_1892; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1139 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1140 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1141 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1142 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1143 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1144 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1145 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1146 = _out_wifireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_977 = ~_out_T_1892; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_979 = _out_wifireMux_T_262 & out_frontSel_179; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_980 = _out_wifireMux_T_979 & _out_T_1646; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_184 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_185 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_186 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_187 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_188 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_189 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_190 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_191 = _out_wifireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_981 = ~_out_T_1646; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_983 = _out_wifireMux_T_262 & out_frontSel_180; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_984 = _out_wifireMux_T_983 & _out_T_1746; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_561 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_562 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_563 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_564 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_565 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_566 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_567 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_568 = _out_wifireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_985 = ~_out_T_1746; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_987 = _out_wifireMux_T_262 & out_frontSel_181; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_988 = _out_wifireMux_T_987 & _out_T_1762; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_625 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_626 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_627 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_628 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_629 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_630 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_631 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_632 = _out_wifireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_989 = ~_out_T_1762; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_991 = _out_wifireMux_T_262 & out_frontSel_182; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_992 = _out_wifireMux_T_991 & _out_T_1828; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_883 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_884 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_885 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_886 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_887 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_888 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_889 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_890 = _out_wifireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_993 = ~_out_T_1828; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_995 = _out_wifireMux_T_262 & out_frontSel_183; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_996 = _out_wifireMux_T_995 & _out_T_1872; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1059 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1060 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1061 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1062 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1063 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1064 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1065 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1066 = _out_wifireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_997 = ~_out_T_1872; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_999 = _out_wifireMux_T_262 & out_frontSel_184; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1000 = _out_wifireMux_T_999 & _out_T_1626; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_104 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_105 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_106 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_107 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_108 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_109 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_110 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_111 = _out_wifireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1001 = ~_out_T_1626; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1003 = _out_wifireMux_T_262 & out_frontSel_185; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1004 = _out_wifireMux_T_1003 & _out_T_1622; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_88 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_89 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_90 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_91 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_92 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_93 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_94 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_95 = _out_wifireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1005 = ~_out_T_1622; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1007 = _out_wifireMux_T_262 & out_frontSel_186; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1008 = _out_wifireMux_T_1007 & _out_T_1850; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_971 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_972 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_973 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_974 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_975 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_976 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_977 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_978 = _out_wifireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1009 = ~_out_T_1850; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1011 = _out_wifireMux_T_262 & out_frontSel_187; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1012 = _out_wifireMux_T_1011 & _out_T_1766; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_641 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_642 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_643 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_644 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_645 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_646 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_647 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_648 = _out_wifireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1013 = ~_out_T_1766; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1015 = _out_wifireMux_T_262 & out_frontSel_188; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1016 = _out_wifireMux_T_1015 & _out_T_1700; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_394 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_395 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_396 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_397 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_398 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_399 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_400 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_401 = _out_wifireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1017 = ~_out_T_1700; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1019 = _out_wifireMux_T_262 & out_frontSel_189; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1020 = _out_wifireMux_T_1019 & _out_T_1634; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_136 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_137 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_138 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_139 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_140 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_141 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_142 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_143 = _out_wifireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1021 = ~_out_T_1634; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1023 = _out_wifireMux_T_262 & out_frontSel_190; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1024 = _out_wifireMux_T_1023 & _out_T_1870; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1051 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1052 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1053 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1054 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1055 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1056 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1057 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1058 = _out_wifireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1025 = ~_out_T_1870; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1027 = _out_wifireMux_T_262 & out_frontSel_191; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1028 = _out_wifireMux_T_1027 & _out_T_1752; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_585 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_586 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_587 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_588 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_589 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_590 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_591 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_592 = _out_wifireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1029 = ~_out_T_1752; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1031 = _out_wifireMux_T_262 & out_frontSel_192; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1032 = _out_wifireMux_T_1031 & _out_T_1682; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_328 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_329 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_330 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_331 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_332 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_333 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_334 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_335 = _out_wifireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1033 = ~_out_T_1682; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1035 = _out_wifireMux_T_262 & out_frontSel_193; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1036 = _out_wifireMux_T_1035 & _out_T_1708; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_426 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_427 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_428 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_429 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_430 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_431 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_432 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_433 = _out_wifireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1037 = ~_out_T_1708; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1039 = _out_wifireMux_T_262 & out_frontSel_194; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1040 = _out_wifireMux_T_1039 & _out_T_1816; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_835 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_836 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_837 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_838 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_839 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_840 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_841 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_842 = _out_wifireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1041 = ~_out_T_1816; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1043 = _out_wifireMux_T_262 & out_frontSel_195; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1044 = _out_wifireMux_T_1043 & _out_T_1884; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1107 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1108 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1109 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1110 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1111 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1112 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1113 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1114 = _out_wifireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1045 = ~_out_T_1884; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1047 = _out_wifireMux_T_262 & out_frontSel_196; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1048 = _out_wifireMux_T_1047 & _out_T_1630; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_120 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_121 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_122 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_123 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_124 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_125 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_126 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_127 = _out_wifireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1049 = ~_out_T_1630; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1051 = _out_wifireMux_T_262 & out_frontSel_197; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1052 = _out_wifireMux_T_1051 & _out_T_1694; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_370 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_371 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_372 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_373 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_374 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_375 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_376 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_377 = _out_wifireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1053 = ~_out_T_1694; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1055 = _out_wifireMux_T_262 & out_frontSel_198; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1056 = _out_wifireMux_T_1055 & _out_T_1788; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_723 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_724 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_725 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_726 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_727 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_728 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_729 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_730 = _out_wifireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1057 = ~_out_T_1788; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1059 = _out_wifireMux_T_262 & out_frontSel_199; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1060 = _out_wifireMux_T_1059 & _out_T_1824; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_867 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_868 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_869 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_870 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_871 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_872 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_873 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_874 = _out_wifireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1061 = ~_out_T_1824; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1063 = _out_wifireMux_T_262 & out_frontSel_200; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1064 = _out_wifireMux_T_1063 & _out_T_1896; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1155 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1156 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1157 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1158 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1159 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1160 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1161 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1162 = _out_wifireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1065 = ~_out_T_1896; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1067 = _out_wifireMux_T_262 & out_frontSel_201; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1068 = _out_wifireMux_T_1067 & _out_T_1674; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_296 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_297 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_298 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_299 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_300 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_301 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_302 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_303 = _out_wifireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1069 = ~_out_T_1674; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1071 = _out_wifireMux_T_262 & out_frontSel_202; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1072 = _out_wifireMux_T_1071 & _out_T_1614; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_56 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_57 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_58 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_59 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_60 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_61 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_62 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_63 = _out_wifireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1073 = ~_out_T_1614; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1075 = _out_wifireMux_T_262 & out_frontSel_203; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1076 = _out_wifireMux_T_1075 & _out_T_1836; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_915 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_916 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_917 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_918 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_919 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_920 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_921 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_922 = _out_wifireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1077 = ~_out_T_1836; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1079 = _out_wifireMux_T_262 & out_frontSel_204; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1080 = _out_wifireMux_T_1079 & _out_T_1754; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_593 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_594 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_595 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_596 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_597 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_598 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_599 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_600 = _out_wifireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1081 = ~_out_T_1754; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1083 = _out_wifireMux_T_262 & out_frontSel_205; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1084 = _out_wifireMux_T_1083 & _out_T_1726; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_487 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_488 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_489 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_490 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_491 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_492 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_493 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_494 = _out_wifireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1085 = ~_out_T_1726; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1087 = _out_wifireMux_T_262 & out_frontSel_206; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1088 = _out_wifireMux_T_1087 & _out_T_1668; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_272 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_273 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_274 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_275 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_276 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_277 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_278 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_279 = _out_wifireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1089 = ~_out_T_1668; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1091 = _out_wifireMux_T_262 & out_frontSel_207; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1092 = _out_wifireMux_T_1091 & _out_T_1858; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1003 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1004 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1005 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1006 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1007 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1008 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1009 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1010 = _out_wifireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1093 = ~_out_T_1858; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1095 = _out_wifireMux_T_262 & out_frontSel_208; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1096 = _out_wifireMux_T_1095 & _out_T_1778; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_689 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_690 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_691 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_692 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_693 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_694 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_695 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_696 = _out_wifireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1097 = ~_out_T_1778; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1099 = _out_wifireMux_T_262 & out_frontSel_209; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1100 = _out_wifireMux_T_1099 & _out_T_1812; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_819 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_820 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_821 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_822 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_823 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_824 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_825 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_826 = _out_wifireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1101 = ~_out_T_1812; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1103 = _out_wifireMux_T_262 & out_frontSel_210; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1104 = _out_wifireMux_T_1103 & _out_T_1878; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1083 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1084 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1085 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1086 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1087 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1088 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1089 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1090 = _out_wifireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1105 = ~_out_T_1878; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1107 = _out_wifireMux_T_262 & out_frontSel_211; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1108 = _out_wifireMux_T_1107 & _out_T_1652; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_208 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_209 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_210 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_211 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_212 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_213 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_214 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_215 = _out_wifireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1109 = ~_out_T_1652; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1111 = _out_wifireMux_T_262 & out_frontSel_212; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1112 = _out_wifireMux_T_1111 & _out_T_1710; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_434 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_435 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_436 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_437 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_438 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_439 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_440 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_441 = _out_wifireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1113 = ~_out_T_1710; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1115 = _out_wifireMux_T_262 & out_frontSel_213; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1116 = _out_wifireMux_T_1115 & _out_T_1784; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_707 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_708 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_709 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_710 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_711 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_712 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_713 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_714 = _out_wifireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1117 = ~_out_T_1784; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1119 = _out_wifireMux_T_262 & out_frontSel_214; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1120 = _out_wifireMux_T_1119 & _out_T_1860; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1011 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1012 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1013 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1014 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1015 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1016 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1017 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1018 = _out_wifireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1121 = ~_out_T_1860; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1123 = _out_wifireMux_T_262 & out_frontSel_215; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1124 = _out_wifireMux_T_1123 & _out_T_1900; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1171 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1172 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1173 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1174 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1175 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1176 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1177 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1178 = _out_wifireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1125 = ~_out_T_1900; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1127 = _out_wifireMux_T_262 & out_frontSel_216; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1128 = _out_wifireMux_T_1127 & _out_T_1642; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_168 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_169 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_170 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_171 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_172 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_173 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_174 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_175 = _out_wifireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1129 = ~_out_T_1642; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1131 = _out_wifireMux_T_262 & out_frontSel_217; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1132 = _out_wifireMux_T_1131 & _out_T_1610; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_40 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_41 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_42 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_43 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_44 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_45 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_46 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_47 = _out_wifireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1133 = ~_out_T_1610; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1135 = _out_wifireMux_T_262 & out_frontSel_218; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1136 = _out_wifireMux_T_1135 & _out_T_1838; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_923 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_924 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_925 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_926 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_927 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_928 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_929 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_930 = _out_wifireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1137 = ~_out_T_1838; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1139 = _out_wifireMux_T_262 & out_frontSel_219; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1140 = _out_wifireMux_T_1139 & _out_T_1772; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_665 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_666 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_667 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_668 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_669 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_670 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_671 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_672 = _out_wifireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1141 = ~_out_T_1772; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1143 = _out_wifireMux_T_262 & out_frontSel_220; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1144 = _out_wifireMux_T_1143 & _out_T_1676; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_304 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_305 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_306 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_307 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_308 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_309 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_310 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_311 = _out_wifireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1145 = ~_out_T_1676; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1147 = _out_wifireMux_T_262 & out_frontSel_221; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1148 = _out_wifireMux_T_1147 & _out_T_1658; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_232 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_233 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_234 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_235 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_236 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_237 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_238 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_239 = _out_wifireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1149 = ~_out_T_1658; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1151 = _out_wifireMux_T_262 & out_frontSel_222; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1152 = _out_wifireMux_T_1151 & _out_T_1902; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1179 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1180 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1181 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1182 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1183 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1184 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1185 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1186 = _out_wifireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1153 = ~_out_T_1902; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1155 = _out_wifireMux_T_262 & out_frontSel_223; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1156 = _out_wifireMux_T_1155 & _out_T_1798; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_763 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_764 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_765 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_766 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_767 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_768 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_769 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_770 = _out_wifireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1157 = ~_out_T_1798; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1159 = _out_wifireMux_T_262 & out_frontSel_224; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1160 = _out_wifireMux_T_1159 & _out_T_1696; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_378 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_379 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_380 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_381 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_382 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_383 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_384 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_385 = _out_wifireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1161 = ~_out_T_1696; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1163 = _out_wifireMux_T_262 & out_frontSel_225; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1164 = _out_wifireMux_T_1163 & _out_T_1706; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_418 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_419 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_420 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_421 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_422 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_423 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_424 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_425 = _out_wifireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1165 = ~_out_T_1706; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1167 = _out_wifireMux_T_262 & out_frontSel_226; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1168 = _out_wifireMux_T_1167 & _out_T_1802; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_779 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_780 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_781 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_782 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_783 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_784 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_785 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_786 = _out_wifireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1169 = ~_out_T_1802; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1171 = _out_wifireMux_T_262 & out_frontSel_227; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1172 = _out_wifireMux_T_1171 & _out_T_1908; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1203 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1204 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1205 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1206 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1207 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1208 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1209 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1210 = _out_wifireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1173 = ~_out_T_1908; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1175 = _out_wifireMux_T_262 & out_frontSel_228; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1176 = _out_wifireMux_T_1175 & _out_T_1638; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_152 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_153 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_154 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_155 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_156 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_157 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_158 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_159 = _out_wifireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1177 = ~_out_T_1638; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1179 = _out_wifireMux_T_262 & out_frontSel_229; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1180 = _out_wifireMux_T_1179 & _out_T_1690; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_354 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_355 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_356 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_357 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_358 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_359 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_360 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_361 = _out_wifireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1181 = ~_out_T_1690; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1183 = _out_wifireMux_T_262 & out_frontSel_230; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1184 = _out_wifireMux_T_1183 & _out_T_1774; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_673 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_674 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_675 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_676 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_677 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_678 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_679 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_680 = _out_wifireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1185 = ~_out_T_1774; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1187 = _out_wifireMux_T_262 & out_frontSel_231; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1188 = _out_wifireMux_T_1187 & _out_T_1844; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_947 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_948 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_949 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_950 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_951 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_952 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_953 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_954 = _out_wifireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1189 = ~_out_T_1844; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1191 = _out_wifireMux_T_262 & out_frontSel_232; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1192 = _out_wifireMux_T_1191 & _out_T_1904; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1187 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1188 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1189 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1190 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1191 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1192 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1193 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1194 = _out_wifireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1193 = ~_out_T_1904; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1195 = _out_wifireMux_T_262 & out_frontSel_233; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1196 = _out_wifireMux_T_1195 & _out_T_1670; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_280 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_281 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_282 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_283 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_284 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_285 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_286 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_287 = _out_wifireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1197 = ~_out_T_1670; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1199 = _out_wifireMux_T_262 & out_frontSel_234; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1200 = _out_wifireMux_T_1199 & _out_T_1604; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_16 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_17 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_18 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_19 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_20 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_21 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_22 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_23 = _out_wifireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1201 = ~_out_T_1604; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1203 = _out_wifireMux_T_262 & out_frontSel_235; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1204 = _out_wifireMux_T_1203 & _out_T_1862; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1019 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1020 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1021 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1022 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1023 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1024 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1025 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1026 = _out_wifireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1205 = ~_out_T_1862; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1207 = _out_wifireMux_T_262 & out_frontSel_236; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1208 = _out_wifireMux_T_1207 & _out_T_1760; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_617 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_618 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_619 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_620 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_621 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_622 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_623 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_624 = _out_wifireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1209 = ~_out_T_1760; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1211 = _out_wifireMux_T_262 & out_frontSel_237; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1212 = _out_wifireMux_T_1211 & _out_T_1730; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_503 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_504 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_505 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_506 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_507 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_508 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_509 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_510 = _out_wifireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1213 = ~_out_T_1730; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1215 = _out_wifireMux_T_262 & out_frontSel_238; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1216 = _out_wifireMux_T_1215 & _out_T_1650; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_200 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_201 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_202 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_203 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_204 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_205 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_206 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_207 = _out_wifireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1217 = ~_out_T_1650; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1219 = _out_wifireMux_T_262 & out_frontSel_239; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1220 = _out_wifireMux_T_1219 & _out_T_1886; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1115 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1116 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1117 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1118 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1119 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1120 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1121 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1122 = _out_wifireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1221 = ~_out_T_1886; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1223 = _out_wifireMux_T_262 & out_frontSel_240; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1224 = _out_wifireMux_T_1223 & _out_T_1792; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_739 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_740 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_741 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_742 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_743 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_744 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_745 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_746 = _out_wifireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1225 = ~_out_T_1792; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1227 = _out_wifireMux_T_262 & out_frontSel_241; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1228 = _out_wifireMux_T_1227 & _out_T_1804; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_787 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_788 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_789 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_790 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_791 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_792 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_793 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_794 = _out_wifireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1229 = ~_out_T_1804; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1231 = _out_wifireMux_T_262 & out_frontSel_242; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1232 = _out_wifireMux_T_1231 & _out_T_1888; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1123 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1124 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1125 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1126 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1127 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1128 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1129 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1130 = _out_wifireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1233 = ~_out_T_1888; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1235 = _out_wifireMux_T_262 & out_frontSel_243; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1236 = _out_wifireMux_T_1235 & _out_T_1664; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_256 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_257 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_258 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_259 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_260 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_261 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_262 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_263 = _out_wifireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1237 = ~_out_T_1664; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1239 = _out_wifireMux_T_262 & out_frontSel_244; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1240 = _out_wifireMux_T_1239 & _out_T_1734; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_519 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_520 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_521 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_522 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_523 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_524 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_525 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_526 = _out_wifireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1241 = ~_out_T_1734; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1243 = _out_wifireMux_T_262 & out_frontSel_245; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1244 = _out_wifireMux_T_1243 & _out_T_1776; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_681 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_682 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_683 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_684 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_685 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_686 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_687 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_688 = _out_wifireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1245 = ~_out_T_1776; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1247 = _out_wifireMux_T_262 & out_frontSel_246; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1248 = _out_wifireMux_T_1247 & _out_T_1864; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1027 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1028 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1029 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1030 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1031 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1032 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1033 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1034 = _out_wifireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1249 = ~_out_T_1864; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1251 = _out_wifireMux_T_262 & out_frontSel_247; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1252 = _out_wifireMux_T_1251 & _out_T_1612; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_48 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_49 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_50 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_51 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_52 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_53 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_54 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_55 = _out_wifireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1253 = ~_out_T_1612; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1255 = _out_wifireMux_T_262 & out_frontSel_248; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1256 = _out_wifireMux_T_1255 & _out_T_1672; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_288 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_289 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_290 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_291 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_292 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_293 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_294 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_295 = _out_wifireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1257 = ~_out_T_1672; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1259 = _out_wifireMux_T_262 & out_frontSel_249; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1260 = _out_wifireMux_T_1259 & _out_T_1602; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_8 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_9 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_10 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_11 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_12 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_13 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_14 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_15 = _out_wifireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1261 = ~_out_T_1602; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1263 = _out_wifireMux_T_262 & out_frontSel_250; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1264 = _out_wifireMux_T_1263 & _out_T_1842; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_939 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_940 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_941 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_942 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_943 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_944 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_945 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_946 = _out_wifireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1265 = ~_out_T_1842; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1267 = _out_wifireMux_T_262 & out_frontSel_251; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1268 = _out_wifireMux_T_1267 & _out_T_1794; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_747 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_748 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_749 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_750 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_751 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_752 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_753 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_754 = _out_wifireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1269 = ~_out_T_1794; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1271 = _out_wifireMux_T_262 & out_frontSel_252; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1272 = _out_wifireMux_T_1271 & _out_T_1692; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_362 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_363 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_364 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_365 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_366 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_367 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_368 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_369 = _out_wifireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1273 = ~_out_T_1692; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1275 = _out_wifireMux_T_262 & out_frontSel_253; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1276 = _out_wifireMux_T_1275 & _out_T_1654; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_216 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_217 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_218 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_219 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_220 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_221 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_222 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_223 = _out_wifireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1277 = ~_out_T_1654; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1279 = _out_wifireMux_T_262 & out_frontSel_254; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1280 = _out_wifireMux_T_1279 & _out_T_1906; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1195 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1196 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1197 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1198 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1199 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1200 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1201 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_1202 = _out_wifireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1281 = ~_out_T_1906; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1283 = _out_wifireMux_T_262 & out_frontSel_255; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_1284 = _out_wifireMux_T_1283 & _out_T_1810; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_811 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_812 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_813 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_814 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_815 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_816 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_817 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_wivalid_1_818 = _out_wifireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1285 = ~_out_T_1810; // @[RegisterRouter.scala:87:24] wire _GEN_23 = out_front_1_valid & out_1_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_259 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_260 = _GEN_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_260 = _out_rofireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_261 = _out_rofireMux_T_260 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_262 = _out_rofireMux_T_261 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_roready_1_451 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_452 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_453 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_454 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_455 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_456 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_457 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] assign out_roready_1_458 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_263 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_265 = _out_rofireMux_T_260 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_266 = _out_rofireMux_T_265 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_roready_1_96 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_97 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_98 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_99 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_100 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_101 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_102 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] assign out_roready_1_103 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_267 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_269 = _out_rofireMux_T_260 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_270 = _out_rofireMux_T_269 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_roready_1_955 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_956 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_957 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_958 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_959 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_960 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_961 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] assign out_roready_1_962 = _out_rofireMux_T_270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_271 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_273 = _out_rofireMux_T_260 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_274 = _out_rofireMux_T_273 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_roready_1_601 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_602 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_603 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_604 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_605 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_606 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_607 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] assign out_roready_1_608 = _out_rofireMux_T_274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_275 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_277 = _out_rofireMux_T_260 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_278 = _out_rofireMux_T_277 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_roready_1_312 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_313 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_314 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_315 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_316 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_317 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_318 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] assign out_roready_1_319 = _out_rofireMux_T_278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_279 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_281 = _out_rofireMux_T_260 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_282 = _out_rofireMux_T_281 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_roready_1_160 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_161 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_162 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_163 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_164 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_165 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_166 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] assign out_roready_1_167 = _out_rofireMux_T_282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_283 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_285 = _out_rofireMux_T_260 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_286 = _out_rofireMux_T_285 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_roready_1_1075 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1076 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1077 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1078 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1079 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1080 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1081 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] assign out_roready_1_1082 = _out_rofireMux_T_286; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_287 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_289 = _out_rofireMux_T_260 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_290 = _out_rofireMux_T_289 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_roready_1_859 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_860 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_861 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_862 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_863 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_864 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_865 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] assign out_roready_1_866 = _out_rofireMux_T_290; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_291 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_293 = _out_rofireMux_T_260 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_294 = _out_rofireMux_T_293 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_roready_1_545 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_546 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_547 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_548 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_549 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_550 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_551 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] assign out_roready_1_552 = _out_rofireMux_T_294; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_295 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_297 = _out_rofireMux_T_260 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_298 = _out_rofireMux_T_297 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_roready_1_264 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_265 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_266 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_267 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_268 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_269 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_270 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] assign out_roready_1_271 = _out_rofireMux_T_298; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_299 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_301 = _out_rofireMux_T_260 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_302 = _out_rofireMux_T_301 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_roready_1_483 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_484 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_485 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] assign out_roready_1_486 = _out_rofireMux_T_302; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_303 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_305 = _out_rofireMux_T_260 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_306 = _out_rofireMux_T_305; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_309 = _out_rofireMux_T_260 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_310 = _out_rofireMux_T_309; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_313 = _out_rofireMux_T_260 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_314 = _out_rofireMux_T_313; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_317 = _out_rofireMux_T_260 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_318 = _out_rofireMux_T_317; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_321 = _out_rofireMux_T_260 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_322 = _out_rofireMux_T_321; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_325 = _out_rofireMux_T_260 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_326 = _out_rofireMux_T_325; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_329 = _out_rofireMux_T_260 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_330 = _out_rofireMux_T_329; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_333 = _out_rofireMux_T_260 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_334 = _out_rofireMux_T_333; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_337 = _out_rofireMux_T_260 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_338 = _out_rofireMux_T_337; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_341 = _out_rofireMux_T_260 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_342 = _out_rofireMux_T_341; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_345 = _out_rofireMux_T_260 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_346 = _out_rofireMux_T_345; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_349 = _out_rofireMux_T_260 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_350 = _out_rofireMux_T_349; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_353 = _out_rofireMux_T_260 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_354 = _out_rofireMux_T_353; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_357 = _out_rofireMux_T_260 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_358 = _out_rofireMux_T_357; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_361 = _out_rofireMux_T_260 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_362 = _out_rofireMux_T_361; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_365 = _out_rofireMux_T_260 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_366 = _out_rofireMux_T_365; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_369 = _out_rofireMux_T_260 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_370 = _out_rofireMux_T_369; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_373 = _out_rofireMux_T_260 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_374 = _out_rofireMux_T_373; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_377 = _out_rofireMux_T_260 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_378 = _out_rofireMux_T_377; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_381 = _out_rofireMux_T_260 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_382 = _out_rofireMux_T_381; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_385 = _out_rofireMux_T_260 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_386 = _out_rofireMux_T_385; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_389 = _out_rofireMux_T_260 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_390 = _out_rofireMux_T_389 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_roready_1_535 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] assign out_roready_1_536 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_391 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_393 = _out_rofireMux_T_260 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_394 = _out_rofireMux_T_393 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_roready_1_352 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] assign out_roready_1_353 = _out_rofireMux_T_394; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_395 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_397 = _out_rofireMux_T_260 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_398 = _out_rofireMux_T_397; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_401 = _out_rofireMux_T_260 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_402 = _out_rofireMux_T_401; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_405 = _out_rofireMux_T_260 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_406 = _out_rofireMux_T_405; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_409 = _out_rofireMux_T_260 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_410 = _out_rofireMux_T_409; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_413 = _out_rofireMux_T_260 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_414 = _out_rofireMux_T_413; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_417 = _out_rofireMux_T_260 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_418 = _out_rofireMux_T_417; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_421 = _out_rofireMux_T_260 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_422 = _out_rofireMux_T_421; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_425 = _out_rofireMux_T_260 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_426 = _out_rofireMux_T_425; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_429 = _out_rofireMux_T_260 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_430 = _out_rofireMux_T_429; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_433 = _out_rofireMux_T_260 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_434 = _out_rofireMux_T_433; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_437 = _out_rofireMux_T_260 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_438 = _out_rofireMux_T_437; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_441 = _out_rofireMux_T_260 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_442 = _out_rofireMux_T_441; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_445 = _out_rofireMux_T_260 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_446 = _out_rofireMux_T_445; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_449 = _out_rofireMux_T_260 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_450 = _out_rofireMux_T_449; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_453 = _out_rofireMux_T_260 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_454 = _out_rofireMux_T_453; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_457 = _out_rofireMux_T_260 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_458 = _out_rofireMux_T_457; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_461 = _out_rofireMux_T_260 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_462 = _out_rofireMux_T_461; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_465 = _out_rofireMux_T_260 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_466 = _out_rofireMux_T_465; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_469 = _out_rofireMux_T_260 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_470 = _out_rofireMux_T_469; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_473 = _out_rofireMux_T_260 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_474 = _out_rofireMux_T_473; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_477 = _out_rofireMux_T_260 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_478 = _out_rofireMux_T_477; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_481 = _out_rofireMux_T_260 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_482 = _out_rofireMux_T_481; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_485 = _out_rofireMux_T_260 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_486 = _out_rofireMux_T_485; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_489 = _out_rofireMux_T_260 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_490 = _out_rofireMux_T_489; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_493 = _out_rofireMux_T_260 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_494 = _out_rofireMux_T_493; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_497 = _out_rofireMux_T_260 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_498 = _out_rofireMux_T_497; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_501 = _out_rofireMux_T_260 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_502 = _out_rofireMux_T_501; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_505 = _out_rofireMux_T_260 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_506 = _out_rofireMux_T_505; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_509 = _out_rofireMux_T_260 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_510 = _out_rofireMux_T_509; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_513 = _out_rofireMux_T_260 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_514 = _out_rofireMux_T_513; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_517 = _out_rofireMux_T_260 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_518 = _out_rofireMux_T_517; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_521 = _out_rofireMux_T_260 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_522 = _out_rofireMux_T_521; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_525 = _out_rofireMux_T_260 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_526 = _out_rofireMux_T_525; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_529 = _out_rofireMux_T_260 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_530 = _out_rofireMux_T_529; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_533 = _out_rofireMux_T_260 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_534 = _out_rofireMux_T_533; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_537 = _out_rofireMux_T_260 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_538 = _out_rofireMux_T_537; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_541 = _out_rofireMux_T_260 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_542 = _out_rofireMux_T_541; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_545 = _out_rofireMux_T_260 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_546 = _out_rofireMux_T_545; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_549 = _out_rofireMux_T_260 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_550 = _out_rofireMux_T_549; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_553 = _out_rofireMux_T_260 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_554 = _out_rofireMux_T_553; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_557 = _out_rofireMux_T_260 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_558 = _out_rofireMux_T_557; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_561 = _out_rofireMux_T_260 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_562 = _out_rofireMux_T_561; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_565 = _out_rofireMux_T_260 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_566 = _out_rofireMux_T_565; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_569 = _out_rofireMux_T_260 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_570 = _out_rofireMux_T_569; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_573 = _out_rofireMux_T_260 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_574 = _out_rofireMux_T_573; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_577 = _out_rofireMux_T_260 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_578 = _out_rofireMux_T_577; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_581 = _out_rofireMux_T_260 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_582 = _out_rofireMux_T_581; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_585 = _out_rofireMux_T_260 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_586 = _out_rofireMux_T_585; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_589 = _out_rofireMux_T_260 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_590 = _out_rofireMux_T_589; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_593 = _out_rofireMux_T_260 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_594 = _out_rofireMux_T_593; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_597 = _out_rofireMux_T_260 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_598 = _out_rofireMux_T_597; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_601 = _out_rofireMux_T_260 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_602 = _out_rofireMux_T_601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_605 = _out_rofireMux_T_260 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_606 = _out_rofireMux_T_605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_609 = _out_rofireMux_T_260 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_610 = _out_rofireMux_T_609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_613 = _out_rofireMux_T_260 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_614 = _out_rofireMux_T_613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_617 = _out_rofireMux_T_260 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_618 = _out_rofireMux_T_617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_621 = _out_rofireMux_T_260 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_622 = _out_rofireMux_T_621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_625 = _out_rofireMux_T_260 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_626 = _out_rofireMux_T_625; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_629 = _out_rofireMux_T_260 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_630 = _out_rofireMux_T_629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_633 = _out_rofireMux_T_260 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_634 = _out_rofireMux_T_633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_637 = _out_rofireMux_T_260 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_638 = _out_rofireMux_T_637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_641 = _out_rofireMux_T_260 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_642 = _out_rofireMux_T_641; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_645 = _out_rofireMux_T_260 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_646 = _out_rofireMux_T_645 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_roready_1_442 = _out_rofireMux_T_646; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_647 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_649 = _out_rofireMux_T_260 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_650 = _out_rofireMux_T_649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_653 = _out_rofireMux_T_260 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_654 = _out_rofireMux_T_653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_657 = _out_rofireMux_T_260 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_658 = _out_rofireMux_T_657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_661 = _out_rofireMux_T_260 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_662 = _out_rofireMux_T_661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_665 = _out_rofireMux_T_260 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_666 = _out_rofireMux_T_665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_669 = _out_rofireMux_T_260 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_670 = _out_rofireMux_T_669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_673 = _out_rofireMux_T_260 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_674 = _out_rofireMux_T_673 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_roready_1_697 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] assign out_roready_1_698 = _out_rofireMux_T_674; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_675 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_677 = _out_rofireMux_T_260 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_678 = _out_rofireMux_T_677 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_roready_1_931 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_932 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_933 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_934 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_935 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_936 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_937 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] assign out_roready_1_938 = _out_rofireMux_T_678; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_679 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_681 = _out_rofireMux_T_260 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_682 = _out_rofireMux_T_681 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_roready_1_511 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_512 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_513 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_514 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_515 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_516 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_517 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] assign out_roready_1_518 = _out_rofireMux_T_682; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_683 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_685 = _out_rofireMux_T_260 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_686 = _out_rofireMux_T_685 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_roready_1_192 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_193 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_194 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_195 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_196 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_197 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_198 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] assign out_roready_1_199 = _out_rofireMux_T_686; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_687 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_689 = _out_rofireMux_T_260 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_690 = _out_rofireMux_T_689 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_roready_1_1091 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1092 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1093 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1094 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1095 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1096 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1097 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] assign out_roready_1_1098 = _out_rofireMux_T_690; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_691 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_693 = _out_rofireMux_T_260 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_694 = _out_rofireMux_T_693 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_roready_1_731 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_732 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_733 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_734 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_735 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_736 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_737 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] assign out_roready_1_738 = _out_rofireMux_T_694; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_695 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_697 = _out_rofireMux_T_260 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_698 = _out_rofireMux_T_697 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_roready_1_443 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_444 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_445 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_446 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_447 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_448 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_449 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] assign out_roready_1_450 = _out_rofireMux_T_698; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_699 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_701 = _out_rofireMux_T_260 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_702 = _out_rofireMux_T_701 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_roready_1_112 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_113 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_114 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_115 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_116 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_117 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_118 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] assign out_roready_1_119 = _out_rofireMux_T_702; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_703 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_705 = _out_rofireMux_T_260 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_706 = _out_rofireMux_T_705 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_roready_1_1163 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1164 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1165 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1166 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1167 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1168 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1169 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] assign out_roready_1_1170 = _out_rofireMux_T_706; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_707 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_709 = _out_rofireMux_T_260 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_710 = _out_rofireMux_T_709 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_roready_1_827 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_828 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_829 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_830 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_831 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_832 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_833 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] assign out_roready_1_834 = _out_rofireMux_T_710; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_711 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_713 = _out_rofireMux_T_260 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_714 = _out_rofireMux_T_713 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_roready_1_657 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_658 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_659 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_660 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_661 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_662 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_663 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] assign out_roready_1_664 = _out_rofireMux_T_714; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_715 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_717 = _out_rofireMux_T_260 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_718 = _out_rofireMux_T_717 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_roready_1_979 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_980 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_981 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_982 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_983 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_984 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_985 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] assign out_roready_1_986 = _out_rofireMux_T_718; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_719 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_721 = _out_rofireMux_T_260 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_722 = _out_rofireMux_T_721 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_roready_1_32 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_33 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_34 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_35 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_36 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_37 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_38 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] assign out_roready_1_39 = _out_rofireMux_T_722; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_723 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_725 = _out_rofireMux_T_260 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_726 = _out_rofireMux_T_725; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_729 = _out_rofireMux_T_260 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_730 = _out_rofireMux_T_729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_733 = _out_rofireMux_T_260 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_734 = _out_rofireMux_T_733; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_737 = _out_rofireMux_T_260 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_738 = _out_rofireMux_T_737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_741 = _out_rofireMux_T_260 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_742 = _out_rofireMux_T_741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_745 = _out_rofireMux_T_260 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_746 = _out_rofireMux_T_745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_749 = _out_rofireMux_T_260 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_750 = _out_rofireMux_T_749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_753 = _out_rofireMux_T_260 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_754 = _out_rofireMux_T_753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_757 = _out_rofireMux_T_260 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_758 = _out_rofireMux_T_757; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_761 = _out_rofireMux_T_260 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_762 = _out_rofireMux_T_761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_765 = _out_rofireMux_T_260 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_766 = _out_rofireMux_T_765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_769 = _out_rofireMux_T_260 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_770 = _out_rofireMux_T_769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_773 = _out_rofireMux_T_260 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_774 = _out_rofireMux_T_773 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_roready_1_495 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_496 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_497 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_498 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_499 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_500 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_501 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] assign out_roready_1_502 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_775 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_777 = _out_rofireMux_T_260 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_778 = _out_rofireMux_T_777 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_roready_1_467 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_468 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_469 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_470 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_471 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_472 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_473 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] assign out_roready_1_474 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_779 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_781 = _out_rofireMux_T_260 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_782 = _out_rofireMux_T_781 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_roready_1_755 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_756 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_757 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_758 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_759 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_760 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_761 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] assign out_roready_1_762 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_783 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_785 = _out_rofireMux_T_260 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_786 = _out_rofireMux_T_785 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_roready_1_1131 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1132 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1133 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1134 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1135 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1136 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1137 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] assign out_roready_1_1138 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_787 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_789 = _out_rofireMux_T_260 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_790 = _out_rofireMux_T_789 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_roready_1_240 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_241 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_242 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_243 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_244 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_245 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_246 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] assign out_roready_1_247 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_791 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_793 = _out_rofireMux_T_260 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_794 = _out_rofireMux_T_793 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_roready_1_248 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_249 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_250 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_251 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_252 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_253 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_254 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] assign out_roready_1_255 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_795 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_797 = _out_rofireMux_T_260 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_798 = _out_rofireMux_T_797 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_roready_1_475 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_476 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_477 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_478 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_479 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_480 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_481 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] assign out_roready_1_482 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_799 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_801 = _out_rofireMux_T_260 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_802 = _out_rofireMux_T_801 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_roready_1_771 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_772 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_773 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_774 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_775 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_776 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_777 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] assign out_roready_1_778 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_803 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_805 = _out_rofireMux_T_260 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_806 = _out_rofireMux_T_805 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_roready_1_1099 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1100 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1101 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1102 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1103 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1104 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1105 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] assign out_roready_1_1106 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_807 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_809 = _out_rofireMux_T_260 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_810 = _out_rofireMux_T_809 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_roready_1_336 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_337 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_338 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_339 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_340 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_341 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_342 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] assign out_roready_1_343 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_811 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_813 = _out_rofireMux_T_260 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_814 = _out_rofireMux_T_813 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_roready_1_0 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_1 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_2 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_3 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_4 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_5 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_6 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] assign out_roready_1_7 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_815 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_817 = _out_rofireMux_T_260 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_818 = _out_rofireMux_T_817 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_roready_1_995 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_996 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_997 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_998 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_999 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1000 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1001 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] assign out_roready_1_1002 = _out_rofireMux_T_818; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_819 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_821 = _out_rofireMux_T_260 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_822 = _out_rofireMux_T_821 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_roready_1_699 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_700 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_701 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_702 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_703 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_704 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_705 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] assign out_roready_1_706 = _out_rofireMux_T_822; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_823 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_825 = _out_rofireMux_T_260 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_826 = _out_rofireMux_T_825 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_roready_1_410 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_411 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_412 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_413 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_414 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_415 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_416 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] assign out_roready_1_417 = _out_rofireMux_T_826; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_827 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_829 = _out_rofireMux_T_260 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_830 = _out_rofireMux_T_829 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_roready_1_64 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_65 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_66 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_67 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_68 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_69 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_70 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] assign out_roready_1_71 = _out_rofireMux_T_830; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_831 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_833 = _out_rofireMux_T_260 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_834 = _out_rofireMux_T_833 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_roready_1_907 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_908 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_909 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_910 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_911 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_912 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_913 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] assign out_roready_1_914 = _out_rofireMux_T_834; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_835 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_837 = _out_rofireMux_T_260 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_838 = _out_rofireMux_T_837 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_roready_1_609 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_610 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_611 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_612 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_613 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_614 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_615 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] assign out_roready_1_616 = _out_rofireMux_T_838; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_839 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_841 = _out_rofireMux_T_260 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_842 = _out_rofireMux_T_841 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_roready_1_843 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_844 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_845 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_846 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_847 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_848 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_849 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] assign out_roready_1_850 = _out_rofireMux_T_842; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_843 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_845 = _out_rofireMux_T_260 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_846 = _out_rofireMux_T_845 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_roready_1_1043 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1044 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1045 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1046 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1047 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1048 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1049 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] assign out_roready_1_1050 = _out_rofireMux_T_846; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_847 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_849 = _out_rofireMux_T_260 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_850 = _out_rofireMux_T_849 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_roready_1_224 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_225 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_226 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_227 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_228 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_229 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_230 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] assign out_roready_1_231 = _out_rofireMux_T_850; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_851 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_853 = _out_rofireMux_T_260 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_854 = _out_rofireMux_T_853 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_roready_1_537 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_538 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_539 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_540 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_541 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_542 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_543 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] assign out_roready_1_544 = _out_rofireMux_T_854; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_855 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_857 = _out_rofireMux_T_260 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_858 = _out_rofireMux_T_857 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_roready_1_569 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_570 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_571 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_572 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_573 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_574 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_575 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] assign out_roready_1_576 = _out_rofireMux_T_858; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_859 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_861 = _out_rofireMux_T_260 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_862 = _out_rofireMux_T_861 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_roready_1_851 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_852 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_853 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_854 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_855 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_856 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_857 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] assign out_roready_1_858 = _out_rofireMux_T_862; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_863 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_865 = _out_rofireMux_T_260 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_866 = _out_rofireMux_T_865 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_roready_1_1035 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1036 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1037 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1038 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1039 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1040 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1041 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] assign out_roready_1_1042 = _out_rofireMux_T_866; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_867 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_869 = _out_rofireMux_T_260 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_870 = _out_rofireMux_T_869 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_roready_1_144 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_145 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_146 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_147 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_148 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_149 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_150 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] assign out_roready_1_151 = _out_rofireMux_T_870; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_871 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_873 = _out_rofireMux_T_260 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_874 = _out_rofireMux_T_873 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_roready_1_72 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_73 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_74 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_75 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_76 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_77 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_78 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] assign out_roready_1_79 = _out_rofireMux_T_874; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_875 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_877 = _out_rofireMux_T_260 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_878 = _out_rofireMux_T_877 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_roready_1_891 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_892 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_893 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_894 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_895 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_896 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_897 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] assign out_roready_1_898 = _out_rofireMux_T_878; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_879 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_881 = _out_rofireMux_T_260 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_882 = _out_rofireMux_T_881 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_roready_1_715 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_716 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_717 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_718 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_719 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_720 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_721 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] assign out_roready_1_722 = _out_rofireMux_T_882; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_883 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_885 = _out_rofireMux_T_260 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_886 = _out_rofireMux_T_885 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_roready_1_386 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_387 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_388 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_389 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_390 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_391 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_392 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] assign out_roready_1_393 = _out_rofireMux_T_886; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_887 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_889 = _out_rofireMux_T_260 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_890 = _out_rofireMux_T_889 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_roready_1_128 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_129 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_130 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_131 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_132 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_133 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_134 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] assign out_roready_1_135 = _out_rofireMux_T_890; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_891 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_893 = _out_rofireMux_T_260 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_894 = _out_rofireMux_T_893 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_roready_1_963 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_964 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_965 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_966 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_967 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_968 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_969 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] assign out_roready_1_970 = _out_rofireMux_T_894; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_895 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_897 = _out_rofireMux_T_260 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_898 = _out_rofireMux_T_897 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_roready_1_633 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_634 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_635 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_636 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_637 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_638 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_639 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] assign out_roready_1_640 = _out_rofireMux_T_898; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_899 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_901 = _out_rofireMux_T_260 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_902 = _out_rofireMux_T_901 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_roready_1_320 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_321 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_322 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_323 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_324 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_325 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_326 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] assign out_roready_1_327 = _out_rofireMux_T_902; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_903 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_905 = _out_rofireMux_T_260 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_906 = _out_rofireMux_T_905 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_roready_1_553 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_554 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_555 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_556 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_557 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_558 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_559 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] assign out_roready_1_560 = _out_rofireMux_T_906; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_907 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_909 = _out_rofireMux_T_260 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_910 = _out_rofireMux_T_909 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_roready_1_803 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_804 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_805 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_806 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_807 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_808 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_809 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] assign out_roready_1_810 = _out_rofireMux_T_910; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_911 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_913 = _out_rofireMux_T_260 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_914 = _out_rofireMux_T_913 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_roready_1_1147 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1148 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1149 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1150 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1151 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1152 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1153 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] assign out_roready_1_1154 = _out_rofireMux_T_914; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_915 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_917 = _out_rofireMux_T_260 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_918 = _out_rofireMux_T_917 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_roready_1_176 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_177 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_178 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_179 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_180 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_181 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_182 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] assign out_roready_1_183 = _out_rofireMux_T_918; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_919 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_921 = _out_rofireMux_T_260 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_922 = _out_rofireMux_T_921 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_roready_1_344 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_345 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_346 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_347 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_348 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_349 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_350 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] assign out_roready_1_351 = _out_rofireMux_T_922; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_923 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_925 = _out_rofireMux_T_260 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_926 = _out_rofireMux_T_925 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_roready_1_527 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_528 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_529 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_530 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_531 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_532 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_533 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] assign out_roready_1_534 = _out_rofireMux_T_926; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_927 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_929 = _out_rofireMux_T_260 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_930 = _out_rofireMux_T_929 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_roready_1_795 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_796 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_797 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_798 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_799 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_800 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_801 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] assign out_roready_1_802 = _out_rofireMux_T_930; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_931 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_933 = _out_rofireMux_T_260 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_934 = _out_rofireMux_T_933 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_roready_1_1067 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1068 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1069 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1070 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1071 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1072 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1073 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] assign out_roready_1_1074 = _out_rofireMux_T_934; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_935 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_937 = _out_rofireMux_T_260 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_938 = _out_rofireMux_T_937 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_roready_1_402 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_403 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_404 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_405 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_406 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_407 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_408 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] assign out_roready_1_409 = _out_rofireMux_T_938; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_939 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_941 = _out_rofireMux_T_260 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_942 = _out_rofireMux_T_941 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_roready_1_24 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_25 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_26 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_27 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_28 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_29 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_30 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] assign out_roready_1_31 = _out_rofireMux_T_942; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_943 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_945 = _out_rofireMux_T_260 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_946 = _out_rofireMux_T_945 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_roready_1_987 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_988 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_989 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_990 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_991 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_992 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_993 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] assign out_roready_1_994 = _out_rofireMux_T_946; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_947 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_949 = _out_rofireMux_T_260 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_950 = _out_rofireMux_T_949 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_roready_1_649 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_650 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_651 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_652 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_653 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_654 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_655 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] assign out_roready_1_656 = _out_rofireMux_T_950; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_951 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_953 = _out_rofireMux_T_260 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_954 = _out_rofireMux_T_953 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_roready_1_459 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_460 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_461 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_462 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_463 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_464 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_465 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] assign out_roready_1_466 = _out_rofireMux_T_954; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_955 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_957 = _out_rofireMux_T_260 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_958 = _out_rofireMux_T_957 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_roready_1_80 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_81 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_82 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_83 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_84 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_85 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_86 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] assign out_roready_1_87 = _out_rofireMux_T_958; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_959 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_961 = _out_rofireMux_T_260 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_962 = _out_rofireMux_T_961 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_roready_1_899 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_900 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_901 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_902 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_903 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_904 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_905 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] assign out_roready_1_906 = _out_rofireMux_T_962; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_963 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_965 = _out_rofireMux_T_260 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_966 = _out_rofireMux_T_965 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_roready_1_577 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_578 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_579 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_580 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_581 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_582 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_583 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] assign out_roready_1_584 = _out_rofireMux_T_966; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_967 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_969 = _out_rofireMux_T_260 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_970 = _out_rofireMux_T_969 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_roready_1_875 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_876 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_877 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_878 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_879 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_880 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_881 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] assign out_roready_1_882 = _out_rofireMux_T_970; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_971 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_973 = _out_rofireMux_T_260 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_974 = _out_rofireMux_T_973 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_roready_1_1139 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1140 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1141 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1142 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1143 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1144 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1145 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] assign out_roready_1_1146 = _out_rofireMux_T_974; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_975 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_977 = _out_rofireMux_T_260 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_978 = _out_rofireMux_T_977 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_roready_1_184 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_185 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_186 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_187 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_188 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_189 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_190 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] assign out_roready_1_191 = _out_rofireMux_T_978; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_979 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_981 = _out_rofireMux_T_260 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_982 = _out_rofireMux_T_981 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_roready_1_561 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_562 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_563 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_564 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_565 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_566 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_567 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] assign out_roready_1_568 = _out_rofireMux_T_982; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_983 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_985 = _out_rofireMux_T_260 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_986 = _out_rofireMux_T_985 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_roready_1_625 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_626 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_627 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_628 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_629 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_630 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_631 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] assign out_roready_1_632 = _out_rofireMux_T_986; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_987 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_989 = _out_rofireMux_T_260 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_990 = _out_rofireMux_T_989 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_roready_1_883 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_884 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_885 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_886 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_887 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_888 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_889 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] assign out_roready_1_890 = _out_rofireMux_T_990; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_991 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_993 = _out_rofireMux_T_260 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_994 = _out_rofireMux_T_993 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_roready_1_1059 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1060 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1061 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1062 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1063 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1064 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1065 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] assign out_roready_1_1066 = _out_rofireMux_T_994; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_995 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_997 = _out_rofireMux_T_260 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_998 = _out_rofireMux_T_997 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_roready_1_104 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_105 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_106 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_107 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_108 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_109 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_110 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] assign out_roready_1_111 = _out_rofireMux_T_998; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_999 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1001 = _out_rofireMux_T_260 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1002 = _out_rofireMux_T_1001 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_roready_1_88 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_89 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_90 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_91 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_92 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_93 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_94 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] assign out_roready_1_95 = _out_rofireMux_T_1002; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1003 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1005 = _out_rofireMux_T_260 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1006 = _out_rofireMux_T_1005 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_roready_1_971 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_972 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_973 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_974 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_975 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_976 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_977 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] assign out_roready_1_978 = _out_rofireMux_T_1006; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1007 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1009 = _out_rofireMux_T_260 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1010 = _out_rofireMux_T_1009 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_roready_1_641 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_642 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_643 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_644 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_645 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_646 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_647 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] assign out_roready_1_648 = _out_rofireMux_T_1010; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1011 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1013 = _out_rofireMux_T_260 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1014 = _out_rofireMux_T_1013 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_roready_1_394 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_395 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_396 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_397 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_398 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_399 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_400 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] assign out_roready_1_401 = _out_rofireMux_T_1014; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1015 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1017 = _out_rofireMux_T_260 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1018 = _out_rofireMux_T_1017 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_roready_1_136 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_137 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_138 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_139 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_140 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_141 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_142 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] assign out_roready_1_143 = _out_rofireMux_T_1018; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1019 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1021 = _out_rofireMux_T_260 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1022 = _out_rofireMux_T_1021 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_roready_1_1051 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1052 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1053 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1054 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1055 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1056 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1057 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] assign out_roready_1_1058 = _out_rofireMux_T_1022; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1023 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1025 = _out_rofireMux_T_260 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1026 = _out_rofireMux_T_1025 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_roready_1_585 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_586 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_587 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_588 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_589 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_590 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_591 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] assign out_roready_1_592 = _out_rofireMux_T_1026; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1027 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1029 = _out_rofireMux_T_260 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1030 = _out_rofireMux_T_1029 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_roready_1_328 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_329 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_330 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_331 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_332 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_333 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_334 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] assign out_roready_1_335 = _out_rofireMux_T_1030; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1031 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1033 = _out_rofireMux_T_260 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1034 = _out_rofireMux_T_1033 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_roready_1_426 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_427 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_428 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_429 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_430 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_431 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_432 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] assign out_roready_1_433 = _out_rofireMux_T_1034; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1035 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1037 = _out_rofireMux_T_260 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1038 = _out_rofireMux_T_1037 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_roready_1_835 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_836 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_837 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_838 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_839 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_840 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_841 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] assign out_roready_1_842 = _out_rofireMux_T_1038; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1039 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1041 = _out_rofireMux_T_260 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1042 = _out_rofireMux_T_1041 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_roready_1_1107 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1108 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1109 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1110 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1111 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1112 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1113 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] assign out_roready_1_1114 = _out_rofireMux_T_1042; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1043 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1045 = _out_rofireMux_T_260 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1046 = _out_rofireMux_T_1045 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_roready_1_120 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_121 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_122 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_123 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_124 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_125 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_126 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] assign out_roready_1_127 = _out_rofireMux_T_1046; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1047 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1049 = _out_rofireMux_T_260 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1050 = _out_rofireMux_T_1049 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_roready_1_370 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_371 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_372 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_373 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_374 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_375 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_376 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] assign out_roready_1_377 = _out_rofireMux_T_1050; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1051 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1053 = _out_rofireMux_T_260 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1054 = _out_rofireMux_T_1053 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_roready_1_723 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_724 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_725 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_726 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_727 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_728 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_729 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] assign out_roready_1_730 = _out_rofireMux_T_1054; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1055 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1057 = _out_rofireMux_T_260 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1058 = _out_rofireMux_T_1057 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_roready_1_867 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_868 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_869 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_870 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_871 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_872 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_873 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] assign out_roready_1_874 = _out_rofireMux_T_1058; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1059 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1061 = _out_rofireMux_T_260 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1062 = _out_rofireMux_T_1061 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_roready_1_1155 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1156 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1157 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1158 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1159 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1160 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1161 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] assign out_roready_1_1162 = _out_rofireMux_T_1062; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1063 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1065 = _out_rofireMux_T_260 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1066 = _out_rofireMux_T_1065 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_roready_1_296 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_297 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_298 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_299 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_300 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_301 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_302 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] assign out_roready_1_303 = _out_rofireMux_T_1066; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1067 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1069 = _out_rofireMux_T_260 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1070 = _out_rofireMux_T_1069 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_roready_1_56 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_57 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_58 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_59 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_60 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_61 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_62 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] assign out_roready_1_63 = _out_rofireMux_T_1070; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1071 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1073 = _out_rofireMux_T_260 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1074 = _out_rofireMux_T_1073 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_roready_1_915 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_916 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_917 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_918 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_919 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_920 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_921 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] assign out_roready_1_922 = _out_rofireMux_T_1074; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1075 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1077 = _out_rofireMux_T_260 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1078 = _out_rofireMux_T_1077 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_roready_1_593 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_594 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_595 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_596 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_597 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_598 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_599 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] assign out_roready_1_600 = _out_rofireMux_T_1078; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1079 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1081 = _out_rofireMux_T_260 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1082 = _out_rofireMux_T_1081 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_roready_1_487 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_488 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_489 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_490 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_491 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_492 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_493 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] assign out_roready_1_494 = _out_rofireMux_T_1082; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1083 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1085 = _out_rofireMux_T_260 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1086 = _out_rofireMux_T_1085 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_roready_1_272 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_273 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_274 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_275 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_276 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_277 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_278 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] assign out_roready_1_279 = _out_rofireMux_T_1086; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1087 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1089 = _out_rofireMux_T_260 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1090 = _out_rofireMux_T_1089 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_roready_1_1003 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1004 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1005 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1006 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1007 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1008 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1009 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] assign out_roready_1_1010 = _out_rofireMux_T_1090; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1091 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1093 = _out_rofireMux_T_260 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1094 = _out_rofireMux_T_1093 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_roready_1_689 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_690 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_691 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_692 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_693 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_694 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_695 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] assign out_roready_1_696 = _out_rofireMux_T_1094; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1095 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1097 = _out_rofireMux_T_260 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1098 = _out_rofireMux_T_1097 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_roready_1_819 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_820 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_821 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_822 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_823 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_824 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_825 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] assign out_roready_1_826 = _out_rofireMux_T_1098; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1099 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1101 = _out_rofireMux_T_260 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1102 = _out_rofireMux_T_1101 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_roready_1_1083 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1084 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1085 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1086 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1087 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1088 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1089 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] assign out_roready_1_1090 = _out_rofireMux_T_1102; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1103 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1105 = _out_rofireMux_T_260 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1106 = _out_rofireMux_T_1105 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_roready_1_208 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_209 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_210 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_211 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_212 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_213 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_214 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] assign out_roready_1_215 = _out_rofireMux_T_1106; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1107 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1109 = _out_rofireMux_T_260 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1110 = _out_rofireMux_T_1109 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_roready_1_434 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_435 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_436 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_437 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_438 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_439 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_440 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] assign out_roready_1_441 = _out_rofireMux_T_1110; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1111 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1113 = _out_rofireMux_T_260 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1114 = _out_rofireMux_T_1113 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_roready_1_707 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_708 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_709 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_710 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_711 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_712 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_713 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] assign out_roready_1_714 = _out_rofireMux_T_1114; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1115 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1117 = _out_rofireMux_T_260 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1118 = _out_rofireMux_T_1117 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_roready_1_1011 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1012 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1013 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1014 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1015 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1016 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1017 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] assign out_roready_1_1018 = _out_rofireMux_T_1118; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1119 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1121 = _out_rofireMux_T_260 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1122 = _out_rofireMux_T_1121 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_roready_1_1171 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1172 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1173 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1174 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1175 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1176 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1177 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] assign out_roready_1_1178 = _out_rofireMux_T_1122; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1123 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1125 = _out_rofireMux_T_260 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1126 = _out_rofireMux_T_1125 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_roready_1_168 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_169 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_170 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_171 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_172 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_173 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_174 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] assign out_roready_1_175 = _out_rofireMux_T_1126; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1127 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1129 = _out_rofireMux_T_260 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1130 = _out_rofireMux_T_1129 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_roready_1_40 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_41 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_42 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_43 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_44 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_45 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_46 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] assign out_roready_1_47 = _out_rofireMux_T_1130; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1131 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1133 = _out_rofireMux_T_260 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1134 = _out_rofireMux_T_1133 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_roready_1_923 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_924 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_925 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_926 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_927 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_928 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_929 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] assign out_roready_1_930 = _out_rofireMux_T_1134; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1135 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1137 = _out_rofireMux_T_260 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1138 = _out_rofireMux_T_1137 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_roready_1_665 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_666 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_667 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_668 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_669 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_670 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_671 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] assign out_roready_1_672 = _out_rofireMux_T_1138; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1139 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1141 = _out_rofireMux_T_260 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1142 = _out_rofireMux_T_1141 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_roready_1_304 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_305 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_306 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_307 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_308 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_309 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_310 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] assign out_roready_1_311 = _out_rofireMux_T_1142; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1143 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1145 = _out_rofireMux_T_260 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1146 = _out_rofireMux_T_1145 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_roready_1_232 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_233 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_234 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_235 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_236 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_237 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_238 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] assign out_roready_1_239 = _out_rofireMux_T_1146; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1147 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1149 = _out_rofireMux_T_260 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1150 = _out_rofireMux_T_1149 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_roready_1_1179 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1180 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1181 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1182 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1183 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1184 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1185 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] assign out_roready_1_1186 = _out_rofireMux_T_1150; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1151 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1153 = _out_rofireMux_T_260 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1154 = _out_rofireMux_T_1153 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_roready_1_763 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_764 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_765 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_766 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_767 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_768 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_769 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] assign out_roready_1_770 = _out_rofireMux_T_1154; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1155 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1157 = _out_rofireMux_T_260 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1158 = _out_rofireMux_T_1157 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_roready_1_378 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_379 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_380 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_381 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_382 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_383 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_384 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] assign out_roready_1_385 = _out_rofireMux_T_1158; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1159 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1161 = _out_rofireMux_T_260 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1162 = _out_rofireMux_T_1161 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_roready_1_418 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_419 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_420 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_421 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_422 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_423 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_424 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] assign out_roready_1_425 = _out_rofireMux_T_1162; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1163 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1165 = _out_rofireMux_T_260 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1166 = _out_rofireMux_T_1165 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_roready_1_779 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_780 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_781 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_782 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_783 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_784 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_785 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] assign out_roready_1_786 = _out_rofireMux_T_1166; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1167 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1169 = _out_rofireMux_T_260 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1170 = _out_rofireMux_T_1169 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_roready_1_1203 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1204 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1205 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1206 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1207 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1208 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1209 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] assign out_roready_1_1210 = _out_rofireMux_T_1170; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1171 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1173 = _out_rofireMux_T_260 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1174 = _out_rofireMux_T_1173 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_roready_1_152 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_153 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_154 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_155 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_156 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_157 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_158 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] assign out_roready_1_159 = _out_rofireMux_T_1174; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1175 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1177 = _out_rofireMux_T_260 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1178 = _out_rofireMux_T_1177 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_roready_1_354 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_355 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_356 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_357 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_358 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_359 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_360 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] assign out_roready_1_361 = _out_rofireMux_T_1178; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1179 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1181 = _out_rofireMux_T_260 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1182 = _out_rofireMux_T_1181 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_roready_1_673 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_674 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_675 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_676 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_677 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_678 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_679 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] assign out_roready_1_680 = _out_rofireMux_T_1182; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1183 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1185 = _out_rofireMux_T_260 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1186 = _out_rofireMux_T_1185 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_roready_1_947 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_948 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_949 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_950 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_951 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_952 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_953 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] assign out_roready_1_954 = _out_rofireMux_T_1186; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1187 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1189 = _out_rofireMux_T_260 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1190 = _out_rofireMux_T_1189 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_roready_1_1187 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1188 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1189 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1190 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1191 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1192 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1193 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] assign out_roready_1_1194 = _out_rofireMux_T_1190; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1191 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1193 = _out_rofireMux_T_260 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1194 = _out_rofireMux_T_1193 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_roready_1_280 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_281 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_282 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_283 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_284 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_285 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_286 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] assign out_roready_1_287 = _out_rofireMux_T_1194; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1195 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1197 = _out_rofireMux_T_260 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1198 = _out_rofireMux_T_1197 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_roready_1_16 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_17 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_18 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_19 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_20 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_21 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_22 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] assign out_roready_1_23 = _out_rofireMux_T_1198; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1199 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1201 = _out_rofireMux_T_260 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1202 = _out_rofireMux_T_1201 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_roready_1_1019 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1020 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1021 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1022 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1023 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1024 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1025 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] assign out_roready_1_1026 = _out_rofireMux_T_1202; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1203 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1205 = _out_rofireMux_T_260 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1206 = _out_rofireMux_T_1205 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_roready_1_617 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_618 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_619 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_620 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_621 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_622 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_623 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] assign out_roready_1_624 = _out_rofireMux_T_1206; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1207 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1209 = _out_rofireMux_T_260 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1210 = _out_rofireMux_T_1209 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_roready_1_503 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_504 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_505 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_506 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_507 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_508 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_509 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] assign out_roready_1_510 = _out_rofireMux_T_1210; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1211 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1213 = _out_rofireMux_T_260 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1214 = _out_rofireMux_T_1213 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_roready_1_200 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_201 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_202 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_203 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_204 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_205 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_206 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] assign out_roready_1_207 = _out_rofireMux_T_1214; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1215 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1217 = _out_rofireMux_T_260 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1218 = _out_rofireMux_T_1217 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_roready_1_1115 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1116 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1117 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1118 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1119 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1120 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1121 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] assign out_roready_1_1122 = _out_rofireMux_T_1218; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1219 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1221 = _out_rofireMux_T_260 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1222 = _out_rofireMux_T_1221 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_roready_1_739 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_740 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_741 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_742 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_743 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_744 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_745 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] assign out_roready_1_746 = _out_rofireMux_T_1222; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1223 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1225 = _out_rofireMux_T_260 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1226 = _out_rofireMux_T_1225 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_roready_1_787 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_788 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_789 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_790 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_791 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_792 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_793 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] assign out_roready_1_794 = _out_rofireMux_T_1226; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1227 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1229 = _out_rofireMux_T_260 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1230 = _out_rofireMux_T_1229 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_roready_1_1123 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1124 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1125 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1126 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1127 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1128 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1129 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] assign out_roready_1_1130 = _out_rofireMux_T_1230; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1231 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1233 = _out_rofireMux_T_260 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1234 = _out_rofireMux_T_1233 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_roready_1_256 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_257 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_258 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_259 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_260 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_261 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_262 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] assign out_roready_1_263 = _out_rofireMux_T_1234; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1235 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1237 = _out_rofireMux_T_260 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1238 = _out_rofireMux_T_1237 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_roready_1_519 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_520 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_521 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_522 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_523 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_524 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_525 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] assign out_roready_1_526 = _out_rofireMux_T_1238; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1239 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1241 = _out_rofireMux_T_260 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1242 = _out_rofireMux_T_1241 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_roready_1_681 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_682 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_683 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_684 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_685 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_686 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_687 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] assign out_roready_1_688 = _out_rofireMux_T_1242; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1243 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1245 = _out_rofireMux_T_260 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1246 = _out_rofireMux_T_1245 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_roready_1_1027 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1028 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1029 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1030 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1031 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1032 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1033 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] assign out_roready_1_1034 = _out_rofireMux_T_1246; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1247 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1249 = _out_rofireMux_T_260 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1250 = _out_rofireMux_T_1249 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_roready_1_48 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_49 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_50 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_51 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_52 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_53 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_54 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] assign out_roready_1_55 = _out_rofireMux_T_1250; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1251 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1253 = _out_rofireMux_T_260 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1254 = _out_rofireMux_T_1253 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_roready_1_288 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_289 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_290 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_291 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_292 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_293 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_294 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] assign out_roready_1_295 = _out_rofireMux_T_1254; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1255 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1257 = _out_rofireMux_T_260 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1258 = _out_rofireMux_T_1257 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_roready_1_8 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_9 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_10 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_11 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_12 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_13 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_14 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] assign out_roready_1_15 = _out_rofireMux_T_1258; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1259 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1261 = _out_rofireMux_T_260 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1262 = _out_rofireMux_T_1261 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_roready_1_939 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_940 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_941 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_942 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_943 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_944 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_945 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] assign out_roready_1_946 = _out_rofireMux_T_1262; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1263 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1265 = _out_rofireMux_T_260 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1266 = _out_rofireMux_T_1265 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_roready_1_747 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_748 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_749 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_750 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_751 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_752 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_753 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] assign out_roready_1_754 = _out_rofireMux_T_1266; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1267 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1269 = _out_rofireMux_T_260 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1270 = _out_rofireMux_T_1269 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_roready_1_362 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_363 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_364 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_365 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_366 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_367 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_368 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] assign out_roready_1_369 = _out_rofireMux_T_1270; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1271 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1273 = _out_rofireMux_T_260 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1274 = _out_rofireMux_T_1273 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_roready_1_216 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_217 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_218 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_219 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_220 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_221 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_222 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] assign out_roready_1_223 = _out_rofireMux_T_1274; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1275 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1277 = _out_rofireMux_T_260 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1278 = _out_rofireMux_T_1277 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_roready_1_1195 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1196 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1197 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1198 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1199 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1200 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1201 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] assign out_roready_1_1202 = _out_rofireMux_T_1278; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1279 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1281 = _out_rofireMux_T_260 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_1282 = _out_rofireMux_T_1281 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_roready_1_811 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_812 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_813 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_814 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_815 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_816 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_817 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] assign out_roready_1_818 = _out_rofireMux_T_1282; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1283 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_262 = _out_wofireMux_T_260 & _out_wofireMux_T_261; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_263 = _out_wofireMux_T_262 & out_backSel_0_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_264 = _out_wofireMux_T_263 & _out_T_1717; // @[RegisterRouter.scala:87:24] assign out_woready_1_451 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_452 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_453 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_454 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_455 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_456 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_457 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] assign out_woready_1_458 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_265 = ~_out_T_1717; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_267 = _out_wofireMux_T_262 & out_backSel_1_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_268 = _out_wofireMux_T_267 & _out_T_1625; // @[RegisterRouter.scala:87:24] assign out_woready_1_96 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_97 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_98 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_99 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_100 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_101 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_102 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] assign out_woready_1_103 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_269 = ~_out_T_1625; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_271 = _out_wofireMux_T_262 & out_backSel_2_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_272 = _out_wofireMux_T_271 & _out_T_1847; // @[RegisterRouter.scala:87:24] assign out_woready_1_955 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_956 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_957 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_958 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_959 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_960 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_961 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] assign out_woready_1_962 = _out_wofireMux_T_272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_273 = ~_out_T_1847; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_275 = _out_wofireMux_T_262 & out_backSel_3_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_276 = _out_wofireMux_T_275 & _out_T_1757; // @[RegisterRouter.scala:87:24] assign out_woready_1_601 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_602 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_603 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_604 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_605 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_606 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_607 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] assign out_woready_1_608 = _out_wofireMux_T_276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_277 = ~_out_T_1757; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_279 = _out_wofireMux_T_262 & out_backSel_4_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_280 = _out_wofireMux_T_279 & _out_T_1679; // @[RegisterRouter.scala:87:24] assign out_woready_1_312 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_313 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_314 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_315 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_316 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_317 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_318 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] assign out_woready_1_319 = _out_wofireMux_T_280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_281 = ~_out_T_1679; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_283 = _out_wofireMux_T_262 & out_backSel_5_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_284 = _out_wofireMux_T_283 & _out_T_1641; // @[RegisterRouter.scala:87:24] assign out_woready_1_160 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_161 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_162 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_163 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_164 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_165 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_166 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] assign out_woready_1_167 = _out_wofireMux_T_284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_285 = ~_out_T_1641; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_287 = _out_wofireMux_T_262 & out_backSel_6_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_288 = _out_wofireMux_T_287 & _out_T_1877; // @[RegisterRouter.scala:87:24] assign out_woready_1_1075 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1076 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1077 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1078 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1079 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1080 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1081 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] assign out_woready_1_1082 = _out_wofireMux_T_288; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_289 = ~_out_T_1877; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_291 = _out_wofireMux_T_262 & out_backSel_7_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_292 = _out_wofireMux_T_291 & _out_T_1823; // @[RegisterRouter.scala:87:24] assign out_woready_1_859 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_860 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_861 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_862 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_863 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_864 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_865 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] assign out_woready_1_866 = _out_wofireMux_T_292; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_293 = ~_out_T_1823; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_295 = _out_wofireMux_T_262 & out_backSel_8_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_296 = _out_wofireMux_T_295 & _out_T_1743; // @[RegisterRouter.scala:87:24] assign out_woready_1_545 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_546 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_547 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_548 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_549 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_550 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_551 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] assign out_woready_1_552 = _out_wofireMux_T_296; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_297 = ~_out_T_1743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_299 = _out_wofireMux_T_262 & out_backSel_9_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_300 = _out_wofireMux_T_299 & _out_T_1667; // @[RegisterRouter.scala:87:24] assign out_woready_1_264 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_265 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_266 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_267 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_268 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_269 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_270 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] assign out_woready_1_271 = _out_wofireMux_T_300; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_301 = ~_out_T_1667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_303 = _out_wofireMux_T_262 & out_backSel_10_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_304 = _out_wofireMux_T_303 & _out_T_1725; // @[RegisterRouter.scala:87:24] assign out_woready_1_483 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_484 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_485 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] assign out_woready_1_486 = _out_wofireMux_T_304; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_305 = ~_out_T_1725; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_307 = _out_wofireMux_T_262 & out_backSel_11_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_308 = _out_wofireMux_T_307; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_311 = _out_wofireMux_T_262 & out_backSel_12_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_312 = _out_wofireMux_T_311; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_315 = _out_wofireMux_T_262 & out_backSel_13_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_316 = _out_wofireMux_T_315; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_319 = _out_wofireMux_T_262 & out_backSel_14_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_320 = _out_wofireMux_T_319; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_323 = _out_wofireMux_T_262 & out_backSel_15_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_324 = _out_wofireMux_T_323; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_327 = _out_wofireMux_T_262 & out_backSel_16_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_328 = _out_wofireMux_T_327; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_331 = _out_wofireMux_T_262 & out_backSel_17_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_332 = _out_wofireMux_T_331; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_335 = _out_wofireMux_T_262 & out_backSel_18_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_336 = _out_wofireMux_T_335; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_339 = _out_wofireMux_T_262 & out_backSel_19_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_340 = _out_wofireMux_T_339; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_343 = _out_wofireMux_T_262 & out_backSel_20_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_344 = _out_wofireMux_T_343; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_347 = _out_wofireMux_T_262 & out_backSel_21_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_348 = _out_wofireMux_T_347; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_351 = _out_wofireMux_T_262 & out_backSel_22_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_352 = _out_wofireMux_T_351; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_355 = _out_wofireMux_T_262 & out_backSel_23_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_356 = _out_wofireMux_T_355; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_359 = _out_wofireMux_T_262 & out_backSel_24_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_360 = _out_wofireMux_T_359; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_363 = _out_wofireMux_T_262 & out_backSel_25_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_364 = _out_wofireMux_T_363; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_367 = _out_wofireMux_T_262 & out_backSel_26_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_368 = _out_wofireMux_T_367; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_371 = _out_wofireMux_T_262 & out_backSel_27_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_372 = _out_wofireMux_T_371; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_375 = _out_wofireMux_T_262 & out_backSel_28_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_376 = _out_wofireMux_T_375; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_379 = _out_wofireMux_T_262 & out_backSel_29_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_380 = _out_wofireMux_T_379; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_383 = _out_wofireMux_T_262 & out_backSel_30_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_384 = _out_wofireMux_T_383; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_387 = _out_wofireMux_T_262 & out_backSel_31_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_388 = _out_wofireMux_T_387; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_391 = _out_wofireMux_T_262 & out_backSel_32_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_392 = _out_wofireMux_T_391 & _out_T_1739; // @[RegisterRouter.scala:87:24] assign out_woready_1_535 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] assign out_woready_1_536 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_393 = ~_out_T_1739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_395 = _out_wofireMux_T_262 & out_backSel_33_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_396 = _out_wofireMux_T_395 & _out_T_1689; // @[RegisterRouter.scala:87:24] assign out_woready_1_352 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] assign out_woready_1_353 = _out_wofireMux_T_396; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_397 = ~_out_T_1689; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_399 = _out_wofireMux_T_262 & out_backSel_34_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_400 = _out_wofireMux_T_399; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_403 = _out_wofireMux_T_262 & out_backSel_35_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_404 = _out_wofireMux_T_403; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_407 = _out_wofireMux_T_262 & out_backSel_36_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_408 = _out_wofireMux_T_407; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_411 = _out_wofireMux_T_262 & out_backSel_37_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_412 = _out_wofireMux_T_411; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_415 = _out_wofireMux_T_262 & out_backSel_38_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_416 = _out_wofireMux_T_415; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_419 = _out_wofireMux_T_262 & out_backSel_39_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_420 = _out_wofireMux_T_419; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_423 = _out_wofireMux_T_262 & out_backSel_40_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_424 = _out_wofireMux_T_423; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_427 = _out_wofireMux_T_262 & out_backSel_41_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_428 = _out_wofireMux_T_427; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_431 = _out_wofireMux_T_262 & out_backSel_42_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_432 = _out_wofireMux_T_431; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_435 = _out_wofireMux_T_262 & out_backSel_43_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_436 = _out_wofireMux_T_435; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_439 = _out_wofireMux_T_262 & out_backSel_44_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_440 = _out_wofireMux_T_439; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_443 = _out_wofireMux_T_262 & out_backSel_45_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_444 = _out_wofireMux_T_443; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_447 = _out_wofireMux_T_262 & out_backSel_46_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_448 = _out_wofireMux_T_447; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_451 = _out_wofireMux_T_262 & out_backSel_47_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_452 = _out_wofireMux_T_451; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_455 = _out_wofireMux_T_262 & out_backSel_48_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_456 = _out_wofireMux_T_455; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_459 = _out_wofireMux_T_262 & out_backSel_49_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_460 = _out_wofireMux_T_459; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_463 = _out_wofireMux_T_262 & out_backSel_50_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_464 = _out_wofireMux_T_463; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_467 = _out_wofireMux_T_262 & out_backSel_51_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_468 = _out_wofireMux_T_467; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_471 = _out_wofireMux_T_262 & out_backSel_52_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_472 = _out_wofireMux_T_471; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_475 = _out_wofireMux_T_262 & out_backSel_53_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_476 = _out_wofireMux_T_475; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_479 = _out_wofireMux_T_262 & out_backSel_54_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_480 = _out_wofireMux_T_479; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_483 = _out_wofireMux_T_262 & out_backSel_55_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_484 = _out_wofireMux_T_483; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_487 = _out_wofireMux_T_262 & out_backSel_56_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_488 = _out_wofireMux_T_487; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_491 = _out_wofireMux_T_262 & out_backSel_57_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_492 = _out_wofireMux_T_491; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_495 = _out_wofireMux_T_262 & out_backSel_58_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_496 = _out_wofireMux_T_495; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_499 = _out_wofireMux_T_262 & out_backSel_59_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_500 = _out_wofireMux_T_499; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_503 = _out_wofireMux_T_262 & out_backSel_60_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_504 = _out_wofireMux_T_503; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_507 = _out_wofireMux_T_262 & out_backSel_61_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_508 = _out_wofireMux_T_507; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_511 = _out_wofireMux_T_262 & out_backSel_62_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_512 = _out_wofireMux_T_511; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_515 = _out_wofireMux_T_262 & out_backSel_63_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_516 = _out_wofireMux_T_515; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_519 = _out_wofireMux_T_262 & out_backSel_64; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_520 = _out_wofireMux_T_519; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_523 = _out_wofireMux_T_262 & out_backSel_65; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_524 = _out_wofireMux_T_523; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_527 = _out_wofireMux_T_262 & out_backSel_66; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_528 = _out_wofireMux_T_527; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_531 = _out_wofireMux_T_262 & out_backSel_67; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_532 = _out_wofireMux_T_531; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_535 = _out_wofireMux_T_262 & out_backSel_68; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_536 = _out_wofireMux_T_535; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_539 = _out_wofireMux_T_262 & out_backSel_69; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_540 = _out_wofireMux_T_539; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_543 = _out_wofireMux_T_262 & out_backSel_70; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_544 = _out_wofireMux_T_543; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_547 = _out_wofireMux_T_262 & out_backSel_71; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_548 = _out_wofireMux_T_547; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_551 = _out_wofireMux_T_262 & out_backSel_72; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_552 = _out_wofireMux_T_551; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_555 = _out_wofireMux_T_262 & out_backSel_73; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_556 = _out_wofireMux_T_555; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_559 = _out_wofireMux_T_262 & out_backSel_74; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_560 = _out_wofireMux_T_559; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_563 = _out_wofireMux_T_262 & out_backSel_75; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_564 = _out_wofireMux_T_563; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_567 = _out_wofireMux_T_262 & out_backSel_76; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_568 = _out_wofireMux_T_567; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_571 = _out_wofireMux_T_262 & out_backSel_77; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_572 = _out_wofireMux_T_571; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_575 = _out_wofireMux_T_262 & out_backSel_78; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_576 = _out_wofireMux_T_575; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_579 = _out_wofireMux_T_262 & out_backSel_79; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_580 = _out_wofireMux_T_579; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_583 = _out_wofireMux_T_262 & out_backSel_80; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_584 = _out_wofireMux_T_583; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_587 = _out_wofireMux_T_262 & out_backSel_81; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_588 = _out_wofireMux_T_587; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_591 = _out_wofireMux_T_262 & out_backSel_82; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_592 = _out_wofireMux_T_591; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_595 = _out_wofireMux_T_262 & out_backSel_83; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_596 = _out_wofireMux_T_595; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_599 = _out_wofireMux_T_262 & out_backSel_84; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_600 = _out_wofireMux_T_599; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_603 = _out_wofireMux_T_262 & out_backSel_85; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_604 = _out_wofireMux_T_603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_607 = _out_wofireMux_T_262 & out_backSel_86; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_608 = _out_wofireMux_T_607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_611 = _out_wofireMux_T_262 & out_backSel_87; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_612 = _out_wofireMux_T_611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_615 = _out_wofireMux_T_262 & out_backSel_88; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_616 = _out_wofireMux_T_615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_619 = _out_wofireMux_T_262 & out_backSel_89; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_620 = _out_wofireMux_T_619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_623 = _out_wofireMux_T_262 & out_backSel_90; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_624 = _out_wofireMux_T_623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_627 = _out_wofireMux_T_262 & out_backSel_91; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_628 = _out_wofireMux_T_627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_631 = _out_wofireMux_T_262 & out_backSel_92; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_632 = _out_wofireMux_T_631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_635 = _out_wofireMux_T_262 & out_backSel_93; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_636 = _out_wofireMux_T_635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_639 = _out_wofireMux_T_262 & out_backSel_94; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_640 = _out_wofireMux_T_639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_643 = _out_wofireMux_T_262 & out_backSel_95; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_644 = _out_wofireMux_T_643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_647 = _out_wofireMux_T_262 & out_backSel_96; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_648 = _out_wofireMux_T_647 & _out_T_1713; // @[RegisterRouter.scala:87:24] assign out_woready_1_442 = _out_wofireMux_T_648; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_649 = ~_out_T_1713; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_651 = _out_wofireMux_T_262 & out_backSel_97; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_652 = _out_wofireMux_T_651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_655 = _out_wofireMux_T_262 & out_backSel_98; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_656 = _out_wofireMux_T_655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_659 = _out_wofireMux_T_262 & out_backSel_99; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_660 = _out_wofireMux_T_659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_663 = _out_wofireMux_T_262 & out_backSel_100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_664 = _out_wofireMux_T_663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_667 = _out_wofireMux_T_262 & out_backSel_101; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_668 = _out_wofireMux_T_667; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_671 = _out_wofireMux_T_262 & out_backSel_102; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_672 = _out_wofireMux_T_671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_675 = _out_wofireMux_T_262 & out_backSel_103; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_676 = _out_wofireMux_T_675 & _out_T_1781; // @[RegisterRouter.scala:87:24] assign out_woready_1_697 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] assign out_woready_1_698 = _out_wofireMux_T_676; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_677 = ~_out_T_1781; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_679 = _out_wofireMux_T_262 & out_backSel_104; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_680 = _out_wofireMux_T_679 & _out_T_1841; // @[RegisterRouter.scala:87:24] assign out_woready_1_931 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_932 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_933 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_934 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_935 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_936 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_937 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] assign out_woready_1_938 = _out_wofireMux_T_680; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_681 = ~_out_T_1841; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_683 = _out_wofireMux_T_262 & out_backSel_105; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_684 = _out_wofireMux_T_683 & _out_T_1733; // @[RegisterRouter.scala:87:24] assign out_woready_1_511 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_512 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_513 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_514 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_515 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_516 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_517 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] assign out_woready_1_518 = _out_wofireMux_T_684; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_685 = ~_out_T_1733; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_687 = _out_wofireMux_T_262 & out_backSel_106; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_688 = _out_wofireMux_T_687 & _out_T_1649; // @[RegisterRouter.scala:87:24] assign out_woready_1_192 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_193 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_194 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_195 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_196 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_197 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_198 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] assign out_woready_1_199 = _out_wofireMux_T_688; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_689 = ~_out_T_1649; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_691 = _out_wofireMux_T_262 & out_backSel_107; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_692 = _out_wofireMux_T_691 & _out_T_1881; // @[RegisterRouter.scala:87:24] assign out_woready_1_1091 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1092 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1093 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1094 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1095 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1096 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1097 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] assign out_woready_1_1098 = _out_wofireMux_T_692; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_693 = ~_out_T_1881; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_695 = _out_wofireMux_T_262 & out_backSel_108; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_696 = _out_wofireMux_T_695 & _out_T_1791; // @[RegisterRouter.scala:87:24] assign out_woready_1_731 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_732 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_733 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_734 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_735 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_736 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_737 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] assign out_woready_1_738 = _out_wofireMux_T_696; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_697 = ~_out_T_1791; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_699 = _out_wofireMux_T_262 & out_backSel_109; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_700 = _out_wofireMux_T_699 & _out_T_1715; // @[RegisterRouter.scala:87:24] assign out_woready_1_443 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_444 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_445 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_446 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_447 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_448 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_449 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] assign out_woready_1_450 = _out_wofireMux_T_700; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_701 = ~_out_T_1715; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_703 = _out_wofireMux_T_262 & out_backSel_110; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_704 = _out_wofireMux_T_703 & _out_T_1629; // @[RegisterRouter.scala:87:24] assign out_woready_1_112 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_113 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_114 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_115 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_116 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_117 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_118 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] assign out_woready_1_119 = _out_wofireMux_T_704; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_705 = ~_out_T_1629; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_707 = _out_wofireMux_T_262 & out_backSel_111; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_708 = _out_wofireMux_T_707 & _out_T_1899; // @[RegisterRouter.scala:87:24] assign out_woready_1_1163 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1164 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1165 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1166 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1167 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1168 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1169 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] assign out_woready_1_1170 = _out_wofireMux_T_708; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_709 = ~_out_T_1899; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_711 = _out_wofireMux_T_262 & out_backSel_112; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_712 = _out_wofireMux_T_711 & _out_T_1815; // @[RegisterRouter.scala:87:24] assign out_woready_1_827 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_828 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_829 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_830 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_831 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_832 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_833 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] assign out_woready_1_834 = _out_wofireMux_T_712; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_713 = ~_out_T_1815; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_715 = _out_wofireMux_T_262 & out_backSel_113; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_716 = _out_wofireMux_T_715 & _out_T_1771; // @[RegisterRouter.scala:87:24] assign out_woready_1_657 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_658 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_659 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_660 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_661 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_662 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_663 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] assign out_woready_1_664 = _out_wofireMux_T_716; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_717 = ~_out_T_1771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_719 = _out_wofireMux_T_262 & out_backSel_114; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_720 = _out_wofireMux_T_719 & _out_T_1853; // @[RegisterRouter.scala:87:24] assign out_woready_1_979 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_980 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_981 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_982 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_983 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_984 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_985 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] assign out_woready_1_986 = _out_wofireMux_T_720; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_721 = ~_out_T_1853; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_723 = _out_wofireMux_T_262 & out_backSel_115; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_724 = _out_wofireMux_T_723 & _out_T_1609; // @[RegisterRouter.scala:87:24] assign out_woready_1_32 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_33 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_34 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_35 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_36 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_37 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_38 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] assign out_woready_1_39 = _out_wofireMux_T_724; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_725 = ~_out_T_1609; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_727 = _out_wofireMux_T_262 & out_backSel_116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_728 = _out_wofireMux_T_727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_731 = _out_wofireMux_T_262 & out_backSel_117; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_732 = _out_wofireMux_T_731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_735 = _out_wofireMux_T_262 & out_backSel_118; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_736 = _out_wofireMux_T_735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_739 = _out_wofireMux_T_262 & out_backSel_119; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_740 = _out_wofireMux_T_739; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_743 = _out_wofireMux_T_262 & out_backSel_120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_744 = _out_wofireMux_T_743; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_747 = _out_wofireMux_T_262 & out_backSel_121; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_748 = _out_wofireMux_T_747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_751 = _out_wofireMux_T_262 & out_backSel_122; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_752 = _out_wofireMux_T_751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_755 = _out_wofireMux_T_262 & out_backSel_123; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_756 = _out_wofireMux_T_755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_759 = _out_wofireMux_T_262 & out_backSel_124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_760 = _out_wofireMux_T_759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_763 = _out_wofireMux_T_262 & out_backSel_125; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_764 = _out_wofireMux_T_763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_767 = _out_wofireMux_T_262 & out_backSel_126; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_768 = _out_wofireMux_T_767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_771 = _out_wofireMux_T_262 & out_backSel_127; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_772 = _out_wofireMux_T_771; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_775 = _out_wofireMux_T_262 & out_backSel_128; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_776 = _out_wofireMux_T_775 & _out_T_1729; // @[RegisterRouter.scala:87:24] assign out_woready_1_495 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_496 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_497 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_498 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_499 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_500 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_501 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] assign out_woready_1_502 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_777 = ~_out_T_1729; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_779 = _out_wofireMux_T_262 & out_backSel_129; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_780 = _out_wofireMux_T_779 & _out_T_1721; // @[RegisterRouter.scala:87:24] assign out_woready_1_467 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_468 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_469 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_470 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_471 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_472 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_473 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] assign out_woready_1_474 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_781 = ~_out_T_1721; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_783 = _out_wofireMux_T_262 & out_backSel_130; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_784 = _out_wofireMux_T_783 & _out_T_1797; // @[RegisterRouter.scala:87:24] assign out_woready_1_755 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_756 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_757 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_758 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_759 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_760 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_761 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] assign out_woready_1_762 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_785 = ~_out_T_1797; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_787 = _out_wofireMux_T_262 & out_backSel_131; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_788 = _out_wofireMux_T_787 & _out_T_1891; // @[RegisterRouter.scala:87:24] assign out_woready_1_1131 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1132 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1133 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1134 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1135 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1136 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1137 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] assign out_woready_1_1138 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_789 = ~_out_T_1891; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_791 = _out_wofireMux_T_262 & out_backSel_132; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_792 = _out_wofireMux_T_791 & _out_T_1661; // @[RegisterRouter.scala:87:24] assign out_woready_1_240 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_241 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_242 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_243 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_244 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_245 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_246 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] assign out_woready_1_247 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_793 = ~_out_T_1661; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_795 = _out_wofireMux_T_262 & out_backSel_133; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_796 = _out_wofireMux_T_795 & _out_T_1663; // @[RegisterRouter.scala:87:24] assign out_woready_1_248 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_249 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_250 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_251 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_252 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_253 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_254 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] assign out_woready_1_255 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_797 = ~_out_T_1663; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_799 = _out_wofireMux_T_262 & out_backSel_134; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_800 = _out_wofireMux_T_799 & _out_T_1723; // @[RegisterRouter.scala:87:24] assign out_woready_1_475 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_476 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_477 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_478 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_479 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_480 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_481 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] assign out_woready_1_482 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_801 = ~_out_T_1723; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_803 = _out_wofireMux_T_262 & out_backSel_135; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_804 = _out_wofireMux_T_803 & _out_T_1801; // @[RegisterRouter.scala:87:24] assign out_woready_1_771 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_772 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_773 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_774 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_775 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_776 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_777 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] assign out_woready_1_778 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_805 = ~_out_T_1801; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_807 = _out_wofireMux_T_262 & out_backSel_136; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_808 = _out_wofireMux_T_807 & _out_T_1883; // @[RegisterRouter.scala:87:24] assign out_woready_1_1099 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1100 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1101 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1102 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1103 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1104 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1105 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] assign out_woready_1_1106 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_809 = ~_out_T_1883; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_811 = _out_wofireMux_T_262 & out_backSel_137; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_812 = _out_wofireMux_T_811 & _out_T_1685; // @[RegisterRouter.scala:87:24] assign out_woready_1_336 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_337 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_338 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_339 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_340 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_341 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_342 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] assign out_woready_1_343 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_813 = ~_out_T_1685; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_815 = _out_wofireMux_T_262 & out_backSel_138; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_816 = _out_wofireMux_T_815 & _out_T_1601; // @[RegisterRouter.scala:87:24] assign out_woready_1_0 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_1 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_2 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_3 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_4 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_5 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_6 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] assign out_woready_1_7 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_817 = ~_out_T_1601; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_819 = _out_wofireMux_T_262 & out_backSel_139; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_820 = _out_wofireMux_T_819 & _out_T_1857; // @[RegisterRouter.scala:87:24] assign out_woready_1_995 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_996 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_997 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_998 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_999 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1000 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1001 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] assign out_woready_1_1002 = _out_wofireMux_T_820; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_821 = ~_out_T_1857; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_823 = _out_wofireMux_T_262 & out_backSel_140; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_824 = _out_wofireMux_T_823 & _out_T_1783; // @[RegisterRouter.scala:87:24] assign out_woready_1_699 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_700 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_701 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_702 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_703 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_704 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_705 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] assign out_woready_1_706 = _out_wofireMux_T_824; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_825 = ~_out_T_1783; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_827 = _out_wofireMux_T_262 & out_backSel_141; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_828 = _out_wofireMux_T_827 & _out_T_1705; // @[RegisterRouter.scala:87:24] assign out_woready_1_410 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_411 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_412 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_413 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_414 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_415 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_416 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] assign out_woready_1_417 = _out_wofireMux_T_828; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_829 = ~_out_T_1705; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_831 = _out_wofireMux_T_262 & out_backSel_142; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_832 = _out_wofireMux_T_831 & _out_T_1617; // @[RegisterRouter.scala:87:24] assign out_woready_1_64 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_65 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_66 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_67 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_68 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_69 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_70 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] assign out_woready_1_71 = _out_wofireMux_T_832; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_833 = ~_out_T_1617; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_835 = _out_wofireMux_T_262 & out_backSel_143; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_836 = _out_wofireMux_T_835 & _out_T_1835; // @[RegisterRouter.scala:87:24] assign out_woready_1_907 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_908 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_909 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_910 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_911 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_912 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_913 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] assign out_woready_1_914 = _out_wofireMux_T_836; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_837 = ~_out_T_1835; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_839 = _out_wofireMux_T_262 & out_backSel_144; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_840 = _out_wofireMux_T_839 & _out_T_1759; // @[RegisterRouter.scala:87:24] assign out_woready_1_609 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_610 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_611 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_612 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_613 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_614 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_615 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] assign out_woready_1_616 = _out_wofireMux_T_840; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_841 = ~_out_T_1759; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_843 = _out_wofireMux_T_262 & out_backSel_145; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_844 = _out_wofireMux_T_843 & _out_T_1819; // @[RegisterRouter.scala:87:24] assign out_woready_1_843 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_844 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_845 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_846 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_847 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_848 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_849 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] assign out_woready_1_850 = _out_wofireMux_T_844; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_845 = ~_out_T_1819; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_847 = _out_wofireMux_T_262 & out_backSel_146; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_848 = _out_wofireMux_T_847 & _out_T_1869; // @[RegisterRouter.scala:87:24] assign out_woready_1_1043 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1044 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1045 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1046 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1047 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1048 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1049 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] assign out_woready_1_1050 = _out_wofireMux_T_848; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_849 = ~_out_T_1869; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_851 = _out_wofireMux_T_262 & out_backSel_147; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_852 = _out_wofireMux_T_851 & _out_T_1657; // @[RegisterRouter.scala:87:24] assign out_woready_1_224 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_225 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_226 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_227 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_228 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_229 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_230 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] assign out_woready_1_231 = _out_wofireMux_T_852; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_853 = ~_out_T_1657; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_855 = _out_wofireMux_T_262 & out_backSel_148; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_856 = _out_wofireMux_T_855 & _out_T_1741; // @[RegisterRouter.scala:87:24] assign out_woready_1_537 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_538 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_539 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_540 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_541 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_542 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_543 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] assign out_woready_1_544 = _out_wofireMux_T_856; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_857 = ~_out_T_1741; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_859 = _out_wofireMux_T_262 & out_backSel_149; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_860 = _out_wofireMux_T_859 & _out_T_1749; // @[RegisterRouter.scala:87:24] assign out_woready_1_569 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_570 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_571 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_572 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_573 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_574 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_575 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] assign out_woready_1_576 = _out_wofireMux_T_860; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_861 = ~_out_T_1749; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_863 = _out_wofireMux_T_262 & out_backSel_150; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_864 = _out_wofireMux_T_863 & _out_T_1821; // @[RegisterRouter.scala:87:24] assign out_woready_1_851 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_852 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_853 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_854 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_855 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_856 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_857 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] assign out_woready_1_858 = _out_wofireMux_T_864; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_865 = ~_out_T_1821; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_867 = _out_wofireMux_T_262 & out_backSel_151; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_868 = _out_wofireMux_T_867 & _out_T_1867; // @[RegisterRouter.scala:87:24] assign out_woready_1_1035 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1036 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1037 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1038 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1039 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1040 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1041 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] assign out_woready_1_1042 = _out_wofireMux_T_868; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_869 = ~_out_T_1867; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_871 = _out_wofireMux_T_262 & out_backSel_152; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_872 = _out_wofireMux_T_871 & _out_T_1637; // @[RegisterRouter.scala:87:24] assign out_woready_1_144 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_145 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_146 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_147 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_148 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_149 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_150 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] assign out_woready_1_151 = _out_wofireMux_T_872; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_873 = ~_out_T_1637; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_875 = _out_wofireMux_T_262 & out_backSel_153; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_876 = _out_wofireMux_T_875 & _out_T_1619; // @[RegisterRouter.scala:87:24] assign out_woready_1_72 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_73 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_74 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_75 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_76 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_77 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_78 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] assign out_woready_1_79 = _out_wofireMux_T_876; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_877 = ~_out_T_1619; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_879 = _out_wofireMux_T_262 & out_backSel_154; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_880 = _out_wofireMux_T_879 & _out_T_1831; // @[RegisterRouter.scala:87:24] assign out_woready_1_891 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_892 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_893 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_894 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_895 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_896 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_897 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] assign out_woready_1_898 = _out_wofireMux_T_880; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_881 = ~_out_T_1831; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_883 = _out_wofireMux_T_262 & out_backSel_155; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_884 = _out_wofireMux_T_883 & _out_T_1787; // @[RegisterRouter.scala:87:24] assign out_woready_1_715 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_716 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_717 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_718 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_719 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_720 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_721 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] assign out_woready_1_722 = _out_wofireMux_T_884; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_885 = ~_out_T_1787; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_887 = _out_wofireMux_T_262 & out_backSel_156; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_888 = _out_wofireMux_T_887 & _out_T_1699; // @[RegisterRouter.scala:87:24] assign out_woready_1_386 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_387 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_388 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_389 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_390 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_391 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_392 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] assign out_woready_1_393 = _out_wofireMux_T_888; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_889 = ~_out_T_1699; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_891 = _out_wofireMux_T_262 & out_backSel_157; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_892 = _out_wofireMux_T_891 & _out_T_1633; // @[RegisterRouter.scala:87:24] assign out_woready_1_128 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_129 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_130 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_131 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_132 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_133 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_134 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] assign out_woready_1_135 = _out_wofireMux_T_892; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_893 = ~_out_T_1633; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_895 = _out_wofireMux_T_262 & out_backSel_158; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_896 = _out_wofireMux_T_895 & _out_T_1849; // @[RegisterRouter.scala:87:24] assign out_woready_1_963 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_964 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_965 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_966 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_967 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_968 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_969 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] assign out_woready_1_970 = _out_wofireMux_T_896; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_897 = ~_out_T_1849; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_899 = _out_wofireMux_T_262 & out_backSel_159; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_900 = _out_wofireMux_T_899 & _out_T_1765; // @[RegisterRouter.scala:87:24] assign out_woready_1_633 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_634 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_635 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_636 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_637 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_638 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_639 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] assign out_woready_1_640 = _out_wofireMux_T_900; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_901 = ~_out_T_1765; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_903 = _out_wofireMux_T_262 & out_backSel_160; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_904 = _out_wofireMux_T_903 & _out_T_1681; // @[RegisterRouter.scala:87:24] assign out_woready_1_320 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_321 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_322 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_323 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_324 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_325 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_326 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] assign out_woready_1_327 = _out_wofireMux_T_904; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_905 = ~_out_T_1681; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_907 = _out_wofireMux_T_262 & out_backSel_161; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_908 = _out_wofireMux_T_907 & _out_T_1745; // @[RegisterRouter.scala:87:24] assign out_woready_1_553 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_554 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_555 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_556 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_557 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_558 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_559 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] assign out_woready_1_560 = _out_wofireMux_T_908; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_909 = ~_out_T_1745; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_911 = _out_wofireMux_T_262 & out_backSel_162; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_912 = _out_wofireMux_T_911 & _out_T_1809; // @[RegisterRouter.scala:87:24] assign out_woready_1_803 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_804 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_805 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_806 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_807 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_808 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_809 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] assign out_woready_1_810 = _out_wofireMux_T_912; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_913 = ~_out_T_1809; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_915 = _out_wofireMux_T_262 & out_backSel_163; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_916 = _out_wofireMux_T_915 & _out_T_1895; // @[RegisterRouter.scala:87:24] assign out_woready_1_1147 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1148 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1149 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1150 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1151 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1152 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1153 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] assign out_woready_1_1154 = _out_wofireMux_T_916; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_917 = ~_out_T_1895; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_919 = _out_wofireMux_T_262 & out_backSel_164; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_920 = _out_wofireMux_T_919 & _out_T_1645; // @[RegisterRouter.scala:87:24] assign out_woready_1_176 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_177 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_178 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_179 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_180 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_181 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_182 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] assign out_woready_1_183 = _out_wofireMux_T_920; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_921 = ~_out_T_1645; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_923 = _out_wofireMux_T_262 & out_backSel_165; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_924 = _out_wofireMux_T_923 & _out_T_1687; // @[RegisterRouter.scala:87:24] assign out_woready_1_344 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_345 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_346 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_347 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_348 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_349 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_350 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] assign out_woready_1_351 = _out_wofireMux_T_924; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_925 = ~_out_T_1687; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_927 = _out_wofireMux_T_262 & out_backSel_166; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_928 = _out_wofireMux_T_927 & _out_T_1737; // @[RegisterRouter.scala:87:24] assign out_woready_1_527 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_528 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_529 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_530 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_531 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_532 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_533 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] assign out_woready_1_534 = _out_wofireMux_T_928; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_929 = ~_out_T_1737; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_931 = _out_wofireMux_T_262 & out_backSel_167; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_932 = _out_wofireMux_T_931 & _out_T_1807; // @[RegisterRouter.scala:87:24] assign out_woready_1_795 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_796 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_797 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_798 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_799 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_800 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_801 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] assign out_woready_1_802 = _out_wofireMux_T_932; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_933 = ~_out_T_1807; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_935 = _out_wofireMux_T_262 & out_backSel_168; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_936 = _out_wofireMux_T_935 & _out_T_1875; // @[RegisterRouter.scala:87:24] assign out_woready_1_1067 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1068 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1069 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1070 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1071 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1072 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1073 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] assign out_woready_1_1074 = _out_wofireMux_T_936; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_937 = ~_out_T_1875; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_939 = _out_wofireMux_T_262 & out_backSel_169; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_940 = _out_wofireMux_T_939 & _out_T_1703; // @[RegisterRouter.scala:87:24] assign out_woready_1_402 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_403 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_404 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_405 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_406 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_407 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_408 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] assign out_woready_1_409 = _out_wofireMux_T_940; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_941 = ~_out_T_1703; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_943 = _out_wofireMux_T_262 & out_backSel_170; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_944 = _out_wofireMux_T_943 & _out_T_1607; // @[RegisterRouter.scala:87:24] assign out_woready_1_24 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_25 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_26 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_27 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_28 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_29 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_30 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] assign out_woready_1_31 = _out_wofireMux_T_944; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_945 = ~_out_T_1607; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_947 = _out_wofireMux_T_262 & out_backSel_171; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_948 = _out_wofireMux_T_947 & _out_T_1855; // @[RegisterRouter.scala:87:24] assign out_woready_1_987 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_988 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_989 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_990 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_991 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_992 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_993 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] assign out_woready_1_994 = _out_wofireMux_T_948; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_949 = ~_out_T_1855; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_951 = _out_wofireMux_T_262 & out_backSel_172; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_952 = _out_wofireMux_T_951 & _out_T_1769; // @[RegisterRouter.scala:87:24] assign out_woready_1_649 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_650 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_651 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_652 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_653 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_654 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_655 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] assign out_woready_1_656 = _out_wofireMux_T_952; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_953 = ~_out_T_1769; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_955 = _out_wofireMux_T_262 & out_backSel_173; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_956 = _out_wofireMux_T_955 & _out_T_1719; // @[RegisterRouter.scala:87:24] assign out_woready_1_459 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_460 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_461 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_462 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_463 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_464 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_465 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] assign out_woready_1_466 = _out_wofireMux_T_956; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_957 = ~_out_T_1719; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_959 = _out_wofireMux_T_262 & out_backSel_174; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_960 = _out_wofireMux_T_959 & _out_T_1621; // @[RegisterRouter.scala:87:24] assign out_woready_1_80 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_81 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_82 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_83 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_84 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_85 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_86 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] assign out_woready_1_87 = _out_wofireMux_T_960; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_961 = ~_out_T_1621; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_963 = _out_wofireMux_T_262 & out_backSel_175; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_964 = _out_wofireMux_T_963 & _out_T_1833; // @[RegisterRouter.scala:87:24] assign out_woready_1_899 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_900 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_901 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_902 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_903 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_904 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_905 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] assign out_woready_1_906 = _out_wofireMux_T_964; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_965 = ~_out_T_1833; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_967 = _out_wofireMux_T_262 & out_backSel_176; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_968 = _out_wofireMux_T_967 & _out_T_1751; // @[RegisterRouter.scala:87:24] assign out_woready_1_577 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_578 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_579 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_580 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_581 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_582 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_583 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] assign out_woready_1_584 = _out_wofireMux_T_968; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_969 = ~_out_T_1751; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_971 = _out_wofireMux_T_262 & out_backSel_177; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_972 = _out_wofireMux_T_971 & _out_T_1827; // @[RegisterRouter.scala:87:24] assign out_woready_1_875 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_876 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_877 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_878 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_879 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_880 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_881 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] assign out_woready_1_882 = _out_wofireMux_T_972; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_973 = ~_out_T_1827; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_975 = _out_wofireMux_T_262 & out_backSel_178; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_976 = _out_wofireMux_T_975 & _out_T_1893; // @[RegisterRouter.scala:87:24] assign out_woready_1_1139 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1140 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1141 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1142 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1143 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1144 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1145 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] assign out_woready_1_1146 = _out_wofireMux_T_976; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_977 = ~_out_T_1893; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_979 = _out_wofireMux_T_262 & out_backSel_179; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_980 = _out_wofireMux_T_979 & _out_T_1647; // @[RegisterRouter.scala:87:24] assign out_woready_1_184 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_185 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_186 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_187 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_188 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_189 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_190 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] assign out_woready_1_191 = _out_wofireMux_T_980; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_981 = ~_out_T_1647; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_983 = _out_wofireMux_T_262 & out_backSel_180; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_984 = _out_wofireMux_T_983 & _out_T_1747; // @[RegisterRouter.scala:87:24] assign out_woready_1_561 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_562 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_563 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_564 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_565 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_566 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_567 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] assign out_woready_1_568 = _out_wofireMux_T_984; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_985 = ~_out_T_1747; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_987 = _out_wofireMux_T_262 & out_backSel_181; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_988 = _out_wofireMux_T_987 & _out_T_1763; // @[RegisterRouter.scala:87:24] assign out_woready_1_625 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_626 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_627 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_628 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_629 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_630 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_631 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] assign out_woready_1_632 = _out_wofireMux_T_988; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_989 = ~_out_T_1763; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_991 = _out_wofireMux_T_262 & out_backSel_182; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_992 = _out_wofireMux_T_991 & _out_T_1829; // @[RegisterRouter.scala:87:24] assign out_woready_1_883 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_884 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_885 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_886 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_887 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_888 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_889 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] assign out_woready_1_890 = _out_wofireMux_T_992; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_993 = ~_out_T_1829; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_995 = _out_wofireMux_T_262 & out_backSel_183; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_996 = _out_wofireMux_T_995 & _out_T_1873; // @[RegisterRouter.scala:87:24] assign out_woready_1_1059 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1060 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1061 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1062 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1063 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1064 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1065 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] assign out_woready_1_1066 = _out_wofireMux_T_996; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_997 = ~_out_T_1873; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_999 = _out_wofireMux_T_262 & out_backSel_184; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1000 = _out_wofireMux_T_999 & _out_T_1627; // @[RegisterRouter.scala:87:24] assign out_woready_1_104 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_105 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_106 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_107 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_108 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_109 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_110 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] assign out_woready_1_111 = _out_wofireMux_T_1000; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1001 = ~_out_T_1627; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1003 = _out_wofireMux_T_262 & out_backSel_185; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1004 = _out_wofireMux_T_1003 & _out_T_1623; // @[RegisterRouter.scala:87:24] assign out_woready_1_88 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_89 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_90 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_91 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_92 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_93 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_94 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] assign out_woready_1_95 = _out_wofireMux_T_1004; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1005 = ~_out_T_1623; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1007 = _out_wofireMux_T_262 & out_backSel_186; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1008 = _out_wofireMux_T_1007 & _out_T_1851; // @[RegisterRouter.scala:87:24] assign out_woready_1_971 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_972 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_973 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_974 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_975 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_976 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_977 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] assign out_woready_1_978 = _out_wofireMux_T_1008; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1009 = ~_out_T_1851; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1011 = _out_wofireMux_T_262 & out_backSel_187; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1012 = _out_wofireMux_T_1011 & _out_T_1767; // @[RegisterRouter.scala:87:24] assign out_woready_1_641 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_642 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_643 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_644 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_645 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_646 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_647 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] assign out_woready_1_648 = _out_wofireMux_T_1012; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1013 = ~_out_T_1767; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1015 = _out_wofireMux_T_262 & out_backSel_188; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1016 = _out_wofireMux_T_1015 & _out_T_1701; // @[RegisterRouter.scala:87:24] assign out_woready_1_394 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_395 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_396 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_397 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_398 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_399 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_400 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] assign out_woready_1_401 = _out_wofireMux_T_1016; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1017 = ~_out_T_1701; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1019 = _out_wofireMux_T_262 & out_backSel_189; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1020 = _out_wofireMux_T_1019 & _out_T_1635; // @[RegisterRouter.scala:87:24] assign out_woready_1_136 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_137 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_138 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_139 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_140 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_141 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_142 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] assign out_woready_1_143 = _out_wofireMux_T_1020; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1021 = ~_out_T_1635; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1023 = _out_wofireMux_T_262 & out_backSel_190; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1024 = _out_wofireMux_T_1023 & _out_T_1871; // @[RegisterRouter.scala:87:24] assign out_woready_1_1051 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1052 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1053 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1054 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1055 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1056 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1057 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] assign out_woready_1_1058 = _out_wofireMux_T_1024; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1025 = ~_out_T_1871; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1027 = _out_wofireMux_T_262 & out_backSel_191; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1028 = _out_wofireMux_T_1027 & _out_T_1753; // @[RegisterRouter.scala:87:24] assign out_woready_1_585 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_586 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_587 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_588 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_589 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_590 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_591 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] assign out_woready_1_592 = _out_wofireMux_T_1028; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1029 = ~_out_T_1753; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1031 = _out_wofireMux_T_262 & out_backSel_192; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1032 = _out_wofireMux_T_1031 & _out_T_1683; // @[RegisterRouter.scala:87:24] assign out_woready_1_328 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_329 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_330 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_331 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_332 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_333 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_334 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] assign out_woready_1_335 = _out_wofireMux_T_1032; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1033 = ~_out_T_1683; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1035 = _out_wofireMux_T_262 & out_backSel_193; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1036 = _out_wofireMux_T_1035 & _out_T_1709; // @[RegisterRouter.scala:87:24] assign out_woready_1_426 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_427 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_428 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_429 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_430 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_431 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_432 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] assign out_woready_1_433 = _out_wofireMux_T_1036; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1037 = ~_out_T_1709; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1039 = _out_wofireMux_T_262 & out_backSel_194; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1040 = _out_wofireMux_T_1039 & _out_T_1817; // @[RegisterRouter.scala:87:24] assign out_woready_1_835 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_836 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_837 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_838 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_839 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_840 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_841 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] assign out_woready_1_842 = _out_wofireMux_T_1040; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1041 = ~_out_T_1817; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1043 = _out_wofireMux_T_262 & out_backSel_195; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1044 = _out_wofireMux_T_1043 & _out_T_1885; // @[RegisterRouter.scala:87:24] assign out_woready_1_1107 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1108 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1109 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1110 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1111 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1112 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1113 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] assign out_woready_1_1114 = _out_wofireMux_T_1044; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1045 = ~_out_T_1885; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1047 = _out_wofireMux_T_262 & out_backSel_196; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1048 = _out_wofireMux_T_1047 & _out_T_1631; // @[RegisterRouter.scala:87:24] assign out_woready_1_120 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_121 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_122 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_123 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_124 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_125 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_126 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] assign out_woready_1_127 = _out_wofireMux_T_1048; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1049 = ~_out_T_1631; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1051 = _out_wofireMux_T_262 & out_backSel_197; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1052 = _out_wofireMux_T_1051 & _out_T_1695; // @[RegisterRouter.scala:87:24] assign out_woready_1_370 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_371 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_372 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_373 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_374 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_375 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_376 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] assign out_woready_1_377 = _out_wofireMux_T_1052; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1053 = ~_out_T_1695; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1055 = _out_wofireMux_T_262 & out_backSel_198; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1056 = _out_wofireMux_T_1055 & _out_T_1789; // @[RegisterRouter.scala:87:24] assign out_woready_1_723 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_724 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_725 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_726 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_727 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_728 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_729 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] assign out_woready_1_730 = _out_wofireMux_T_1056; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1057 = ~_out_T_1789; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1059 = _out_wofireMux_T_262 & out_backSel_199; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1060 = _out_wofireMux_T_1059 & _out_T_1825; // @[RegisterRouter.scala:87:24] assign out_woready_1_867 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_868 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_869 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_870 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_871 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_872 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_873 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] assign out_woready_1_874 = _out_wofireMux_T_1060; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1061 = ~_out_T_1825; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1063 = _out_wofireMux_T_262 & out_backSel_200; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1064 = _out_wofireMux_T_1063 & _out_T_1897; // @[RegisterRouter.scala:87:24] assign out_woready_1_1155 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1156 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1157 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1158 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1159 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1160 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1161 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] assign out_woready_1_1162 = _out_wofireMux_T_1064; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1065 = ~_out_T_1897; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1067 = _out_wofireMux_T_262 & out_backSel_201; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1068 = _out_wofireMux_T_1067 & _out_T_1675; // @[RegisterRouter.scala:87:24] assign out_woready_1_296 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_297 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_298 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_299 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_300 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_301 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_302 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] assign out_woready_1_303 = _out_wofireMux_T_1068; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1069 = ~_out_T_1675; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1071 = _out_wofireMux_T_262 & out_backSel_202; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1072 = _out_wofireMux_T_1071 & _out_T_1615; // @[RegisterRouter.scala:87:24] assign out_woready_1_56 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_57 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_58 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_59 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_60 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_61 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_62 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] assign out_woready_1_63 = _out_wofireMux_T_1072; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1073 = ~_out_T_1615; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1075 = _out_wofireMux_T_262 & out_backSel_203; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1076 = _out_wofireMux_T_1075 & _out_T_1837; // @[RegisterRouter.scala:87:24] assign out_woready_1_915 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_916 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_917 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_918 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_919 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_920 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_921 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] assign out_woready_1_922 = _out_wofireMux_T_1076; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1077 = ~_out_T_1837; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1079 = _out_wofireMux_T_262 & out_backSel_204; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1080 = _out_wofireMux_T_1079 & _out_T_1755; // @[RegisterRouter.scala:87:24] assign out_woready_1_593 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_594 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_595 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_596 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_597 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_598 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_599 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] assign out_woready_1_600 = _out_wofireMux_T_1080; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1081 = ~_out_T_1755; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1083 = _out_wofireMux_T_262 & out_backSel_205; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1084 = _out_wofireMux_T_1083 & _out_T_1727; // @[RegisterRouter.scala:87:24] assign out_woready_1_487 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_488 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_489 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_490 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_491 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_492 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_493 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] assign out_woready_1_494 = _out_wofireMux_T_1084; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1085 = ~_out_T_1727; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1087 = _out_wofireMux_T_262 & out_backSel_206; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1088 = _out_wofireMux_T_1087 & _out_T_1669; // @[RegisterRouter.scala:87:24] assign out_woready_1_272 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_273 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_274 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_275 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_276 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_277 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_278 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] assign out_woready_1_279 = _out_wofireMux_T_1088; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1089 = ~_out_T_1669; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1091 = _out_wofireMux_T_262 & out_backSel_207; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1092 = _out_wofireMux_T_1091 & _out_T_1859; // @[RegisterRouter.scala:87:24] assign out_woready_1_1003 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1004 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1005 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1006 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1007 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1008 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1009 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] assign out_woready_1_1010 = _out_wofireMux_T_1092; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1093 = ~_out_T_1859; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1095 = _out_wofireMux_T_262 & out_backSel_208; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1096 = _out_wofireMux_T_1095 & _out_T_1779; // @[RegisterRouter.scala:87:24] assign out_woready_1_689 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_690 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_691 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_692 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_693 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_694 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_695 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] assign out_woready_1_696 = _out_wofireMux_T_1096; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1097 = ~_out_T_1779; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1099 = _out_wofireMux_T_262 & out_backSel_209; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1100 = _out_wofireMux_T_1099 & _out_T_1813; // @[RegisterRouter.scala:87:24] assign out_woready_1_819 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_820 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_821 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_822 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_823 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_824 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_825 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] assign out_woready_1_826 = _out_wofireMux_T_1100; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1101 = ~_out_T_1813; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1103 = _out_wofireMux_T_262 & out_backSel_210; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1104 = _out_wofireMux_T_1103 & _out_T_1879; // @[RegisterRouter.scala:87:24] assign out_woready_1_1083 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1084 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1085 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1086 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1087 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1088 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1089 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] assign out_woready_1_1090 = _out_wofireMux_T_1104; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1105 = ~_out_T_1879; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1107 = _out_wofireMux_T_262 & out_backSel_211; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1108 = _out_wofireMux_T_1107 & _out_T_1653; // @[RegisterRouter.scala:87:24] assign out_woready_1_208 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_209 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_210 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_211 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_212 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_213 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_214 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] assign out_woready_1_215 = _out_wofireMux_T_1108; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1109 = ~_out_T_1653; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1111 = _out_wofireMux_T_262 & out_backSel_212; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1112 = _out_wofireMux_T_1111 & _out_T_1711; // @[RegisterRouter.scala:87:24] assign out_woready_1_434 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_435 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_436 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_437 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_438 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_439 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_440 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] assign out_woready_1_441 = _out_wofireMux_T_1112; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1113 = ~_out_T_1711; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1115 = _out_wofireMux_T_262 & out_backSel_213; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1116 = _out_wofireMux_T_1115 & _out_T_1785; // @[RegisterRouter.scala:87:24] assign out_woready_1_707 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_708 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_709 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_710 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_711 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_712 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_713 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] assign out_woready_1_714 = _out_wofireMux_T_1116; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1117 = ~_out_T_1785; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1119 = _out_wofireMux_T_262 & out_backSel_214; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1120 = _out_wofireMux_T_1119 & _out_T_1861; // @[RegisterRouter.scala:87:24] assign out_woready_1_1011 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1012 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1013 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1014 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1015 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1016 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1017 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] assign out_woready_1_1018 = _out_wofireMux_T_1120; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1121 = ~_out_T_1861; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1123 = _out_wofireMux_T_262 & out_backSel_215; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1124 = _out_wofireMux_T_1123 & _out_T_1901; // @[RegisterRouter.scala:87:24] assign out_woready_1_1171 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1172 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1173 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1174 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1175 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1176 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1177 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] assign out_woready_1_1178 = _out_wofireMux_T_1124; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1125 = ~_out_T_1901; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1127 = _out_wofireMux_T_262 & out_backSel_216; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1128 = _out_wofireMux_T_1127 & _out_T_1643; // @[RegisterRouter.scala:87:24] assign out_woready_1_168 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_169 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_170 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_171 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_172 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_173 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_174 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] assign out_woready_1_175 = _out_wofireMux_T_1128; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1129 = ~_out_T_1643; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1131 = _out_wofireMux_T_262 & out_backSel_217; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1132 = _out_wofireMux_T_1131 & _out_T_1611; // @[RegisterRouter.scala:87:24] assign out_woready_1_40 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_41 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_42 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_43 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_44 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_45 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_46 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] assign out_woready_1_47 = _out_wofireMux_T_1132; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1133 = ~_out_T_1611; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1135 = _out_wofireMux_T_262 & out_backSel_218; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1136 = _out_wofireMux_T_1135 & _out_T_1839; // @[RegisterRouter.scala:87:24] assign out_woready_1_923 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_924 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_925 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_926 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_927 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_928 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_929 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] assign out_woready_1_930 = _out_wofireMux_T_1136; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1137 = ~_out_T_1839; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1139 = _out_wofireMux_T_262 & out_backSel_219; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1140 = _out_wofireMux_T_1139 & _out_T_1773; // @[RegisterRouter.scala:87:24] assign out_woready_1_665 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_666 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_667 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_668 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_669 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_670 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_671 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] assign out_woready_1_672 = _out_wofireMux_T_1140; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1141 = ~_out_T_1773; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1143 = _out_wofireMux_T_262 & out_backSel_220; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1144 = _out_wofireMux_T_1143 & _out_T_1677; // @[RegisterRouter.scala:87:24] assign out_woready_1_304 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_305 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_306 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_307 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_308 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_309 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_310 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] assign out_woready_1_311 = _out_wofireMux_T_1144; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1145 = ~_out_T_1677; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1147 = _out_wofireMux_T_262 & out_backSel_221; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1148 = _out_wofireMux_T_1147 & _out_T_1659; // @[RegisterRouter.scala:87:24] assign out_woready_1_232 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_233 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_234 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_235 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_236 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_237 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_238 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] assign out_woready_1_239 = _out_wofireMux_T_1148; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1149 = ~_out_T_1659; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1151 = _out_wofireMux_T_262 & out_backSel_222; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1152 = _out_wofireMux_T_1151 & _out_T_1903; // @[RegisterRouter.scala:87:24] assign out_woready_1_1179 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1180 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1181 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1182 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1183 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1184 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1185 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] assign out_woready_1_1186 = _out_wofireMux_T_1152; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1153 = ~_out_T_1903; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1155 = _out_wofireMux_T_262 & out_backSel_223; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1156 = _out_wofireMux_T_1155 & _out_T_1799; // @[RegisterRouter.scala:87:24] assign out_woready_1_763 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_764 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_765 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_766 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_767 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_768 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_769 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] assign out_woready_1_770 = _out_wofireMux_T_1156; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1157 = ~_out_T_1799; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1159 = _out_wofireMux_T_262 & out_backSel_224; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1160 = _out_wofireMux_T_1159 & _out_T_1697; // @[RegisterRouter.scala:87:24] assign out_woready_1_378 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_379 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_380 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_381 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_382 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_383 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_384 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] assign out_woready_1_385 = _out_wofireMux_T_1160; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1161 = ~_out_T_1697; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1163 = _out_wofireMux_T_262 & out_backSel_225; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1164 = _out_wofireMux_T_1163 & _out_T_1707; // @[RegisterRouter.scala:87:24] assign out_woready_1_418 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_419 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_420 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_421 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_422 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_423 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_424 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] assign out_woready_1_425 = _out_wofireMux_T_1164; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1165 = ~_out_T_1707; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1167 = _out_wofireMux_T_262 & out_backSel_226; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1168 = _out_wofireMux_T_1167 & _out_T_1803; // @[RegisterRouter.scala:87:24] assign out_woready_1_779 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_780 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_781 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_782 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_783 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_784 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_785 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] assign out_woready_1_786 = _out_wofireMux_T_1168; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1169 = ~_out_T_1803; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1171 = _out_wofireMux_T_262 & out_backSel_227; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1172 = _out_wofireMux_T_1171 & _out_T_1909; // @[RegisterRouter.scala:87:24] assign out_woready_1_1203 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1204 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1205 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1206 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1207 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1208 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1209 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] assign out_woready_1_1210 = _out_wofireMux_T_1172; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1173 = ~_out_T_1909; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1175 = _out_wofireMux_T_262 & out_backSel_228; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1176 = _out_wofireMux_T_1175 & _out_T_1639; // @[RegisterRouter.scala:87:24] assign out_woready_1_152 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_153 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_154 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_155 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_156 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_157 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_158 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] assign out_woready_1_159 = _out_wofireMux_T_1176; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1177 = ~_out_T_1639; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1179 = _out_wofireMux_T_262 & out_backSel_229; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1180 = _out_wofireMux_T_1179 & _out_T_1691; // @[RegisterRouter.scala:87:24] assign out_woready_1_354 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_355 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_356 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_357 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_358 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_359 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_360 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] assign out_woready_1_361 = _out_wofireMux_T_1180; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1181 = ~_out_T_1691; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1183 = _out_wofireMux_T_262 & out_backSel_230; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1184 = _out_wofireMux_T_1183 & _out_T_1775; // @[RegisterRouter.scala:87:24] assign out_woready_1_673 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_674 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_675 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_676 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_677 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_678 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_679 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] assign out_woready_1_680 = _out_wofireMux_T_1184; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1185 = ~_out_T_1775; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1187 = _out_wofireMux_T_262 & out_backSel_231; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1188 = _out_wofireMux_T_1187 & _out_T_1845; // @[RegisterRouter.scala:87:24] assign out_woready_1_947 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_948 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_949 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_950 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_951 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_952 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_953 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] assign out_woready_1_954 = _out_wofireMux_T_1188; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1189 = ~_out_T_1845; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1191 = _out_wofireMux_T_262 & out_backSel_232; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1192 = _out_wofireMux_T_1191 & _out_T_1905; // @[RegisterRouter.scala:87:24] assign out_woready_1_1187 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1188 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1189 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1190 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1191 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1192 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1193 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] assign out_woready_1_1194 = _out_wofireMux_T_1192; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1193 = ~_out_T_1905; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1195 = _out_wofireMux_T_262 & out_backSel_233; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1196 = _out_wofireMux_T_1195 & _out_T_1671; // @[RegisterRouter.scala:87:24] assign out_woready_1_280 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_281 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_282 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_283 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_284 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_285 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_286 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] assign out_woready_1_287 = _out_wofireMux_T_1196; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1197 = ~_out_T_1671; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1199 = _out_wofireMux_T_262 & out_backSel_234; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1200 = _out_wofireMux_T_1199 & _out_T_1605; // @[RegisterRouter.scala:87:24] assign out_woready_1_16 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_17 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_18 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_19 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_20 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_21 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_22 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] assign out_woready_1_23 = _out_wofireMux_T_1200; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1201 = ~_out_T_1605; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1203 = _out_wofireMux_T_262 & out_backSel_235; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1204 = _out_wofireMux_T_1203 & _out_T_1863; // @[RegisterRouter.scala:87:24] assign out_woready_1_1019 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1020 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1021 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1022 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1023 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1024 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1025 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] assign out_woready_1_1026 = _out_wofireMux_T_1204; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1205 = ~_out_T_1863; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1207 = _out_wofireMux_T_262 & out_backSel_236; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1208 = _out_wofireMux_T_1207 & _out_T_1761; // @[RegisterRouter.scala:87:24] assign out_woready_1_617 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_618 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_619 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_620 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_621 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_622 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_623 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] assign out_woready_1_624 = _out_wofireMux_T_1208; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1209 = ~_out_T_1761; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1211 = _out_wofireMux_T_262 & out_backSel_237; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1212 = _out_wofireMux_T_1211 & _out_T_1731; // @[RegisterRouter.scala:87:24] assign out_woready_1_503 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_504 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_505 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_506 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_507 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_508 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_509 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] assign out_woready_1_510 = _out_wofireMux_T_1212; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1213 = ~_out_T_1731; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1215 = _out_wofireMux_T_262 & out_backSel_238; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1216 = _out_wofireMux_T_1215 & _out_T_1651; // @[RegisterRouter.scala:87:24] assign out_woready_1_200 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_201 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_202 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_203 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_204 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_205 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_206 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] assign out_woready_1_207 = _out_wofireMux_T_1216; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1217 = ~_out_T_1651; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1219 = _out_wofireMux_T_262 & out_backSel_239; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1220 = _out_wofireMux_T_1219 & _out_T_1887; // @[RegisterRouter.scala:87:24] assign out_woready_1_1115 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1116 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1117 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1118 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1119 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1120 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1121 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] assign out_woready_1_1122 = _out_wofireMux_T_1220; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1221 = ~_out_T_1887; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1223 = _out_wofireMux_T_262 & out_backSel_240; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1224 = _out_wofireMux_T_1223 & _out_T_1793; // @[RegisterRouter.scala:87:24] assign out_woready_1_739 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_740 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_741 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_742 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_743 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_744 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_745 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] assign out_woready_1_746 = _out_wofireMux_T_1224; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1225 = ~_out_T_1793; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1227 = _out_wofireMux_T_262 & out_backSel_241; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1228 = _out_wofireMux_T_1227 & _out_T_1805; // @[RegisterRouter.scala:87:24] assign out_woready_1_787 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_788 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_789 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_790 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_791 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_792 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_793 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] assign out_woready_1_794 = _out_wofireMux_T_1228; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1229 = ~_out_T_1805; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1231 = _out_wofireMux_T_262 & out_backSel_242; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1232 = _out_wofireMux_T_1231 & _out_T_1889; // @[RegisterRouter.scala:87:24] assign out_woready_1_1123 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1124 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1125 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1126 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1127 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1128 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1129 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] assign out_woready_1_1130 = _out_wofireMux_T_1232; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1233 = ~_out_T_1889; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1235 = _out_wofireMux_T_262 & out_backSel_243; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1236 = _out_wofireMux_T_1235 & _out_T_1665; // @[RegisterRouter.scala:87:24] assign out_woready_1_256 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_257 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_258 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_259 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_260 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_261 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_262 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] assign out_woready_1_263 = _out_wofireMux_T_1236; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1237 = ~_out_T_1665; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1239 = _out_wofireMux_T_262 & out_backSel_244; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1240 = _out_wofireMux_T_1239 & _out_T_1735; // @[RegisterRouter.scala:87:24] assign out_woready_1_519 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_520 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_521 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_522 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_523 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_524 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_525 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] assign out_woready_1_526 = _out_wofireMux_T_1240; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1241 = ~_out_T_1735; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1243 = _out_wofireMux_T_262 & out_backSel_245; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1244 = _out_wofireMux_T_1243 & _out_T_1777; // @[RegisterRouter.scala:87:24] assign out_woready_1_681 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_682 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_683 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_684 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_685 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_686 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_687 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] assign out_woready_1_688 = _out_wofireMux_T_1244; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1245 = ~_out_T_1777; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1247 = _out_wofireMux_T_262 & out_backSel_246; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1248 = _out_wofireMux_T_1247 & _out_T_1865; // @[RegisterRouter.scala:87:24] assign out_woready_1_1027 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1028 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1029 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1030 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1031 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1032 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1033 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] assign out_woready_1_1034 = _out_wofireMux_T_1248; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1249 = ~_out_T_1865; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1251 = _out_wofireMux_T_262 & out_backSel_247; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1252 = _out_wofireMux_T_1251 & _out_T_1613; // @[RegisterRouter.scala:87:24] assign out_woready_1_48 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_49 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_50 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_51 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_52 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_53 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_54 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] assign out_woready_1_55 = _out_wofireMux_T_1252; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1253 = ~_out_T_1613; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1255 = _out_wofireMux_T_262 & out_backSel_248; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1256 = _out_wofireMux_T_1255 & _out_T_1673; // @[RegisterRouter.scala:87:24] assign out_woready_1_288 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_289 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_290 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_291 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_292 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_293 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_294 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] assign out_woready_1_295 = _out_wofireMux_T_1256; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1257 = ~_out_T_1673; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1259 = _out_wofireMux_T_262 & out_backSel_249; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1260 = _out_wofireMux_T_1259 & _out_T_1603; // @[RegisterRouter.scala:87:24] assign out_woready_1_8 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_9 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_10 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_11 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_12 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_13 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_14 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] assign out_woready_1_15 = _out_wofireMux_T_1260; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1261 = ~_out_T_1603; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1263 = _out_wofireMux_T_262 & out_backSel_250; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1264 = _out_wofireMux_T_1263 & _out_T_1843; // @[RegisterRouter.scala:87:24] assign out_woready_1_939 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_940 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_941 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_942 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_943 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_944 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_945 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] assign out_woready_1_946 = _out_wofireMux_T_1264; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1265 = ~_out_T_1843; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1267 = _out_wofireMux_T_262 & out_backSel_251; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1268 = _out_wofireMux_T_1267 & _out_T_1795; // @[RegisterRouter.scala:87:24] assign out_woready_1_747 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_748 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_749 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_750 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_751 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_752 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_753 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] assign out_woready_1_754 = _out_wofireMux_T_1268; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1269 = ~_out_T_1795; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1271 = _out_wofireMux_T_262 & out_backSel_252; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1272 = _out_wofireMux_T_1271 & _out_T_1693; // @[RegisterRouter.scala:87:24] assign out_woready_1_362 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_363 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_364 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_365 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_366 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_367 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_368 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] assign out_woready_1_369 = _out_wofireMux_T_1272; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1273 = ~_out_T_1693; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1275 = _out_wofireMux_T_262 & out_backSel_253; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1276 = _out_wofireMux_T_1275 & _out_T_1655; // @[RegisterRouter.scala:87:24] assign out_woready_1_216 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_217 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_218 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_219 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_220 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_221 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_222 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] assign out_woready_1_223 = _out_wofireMux_T_1276; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1277 = ~_out_T_1655; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1279 = _out_wofireMux_T_262 & out_backSel_254; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1280 = _out_wofireMux_T_1279 & _out_T_1907; // @[RegisterRouter.scala:87:24] assign out_woready_1_1195 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1196 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1197 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1198 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1199 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1200 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1201 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] assign out_woready_1_1202 = _out_wofireMux_T_1280; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1281 = ~_out_T_1907; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1283 = _out_wofireMux_T_262 & out_backSel_255; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_1284 = _out_wofireMux_T_1283 & _out_T_1811; // @[RegisterRouter.scala:87:24] assign out_woready_1_811 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_812 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_813 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_814 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_815 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_816 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_817 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] assign out_woready_1_818 = _out_wofireMux_T_1284; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1285 = ~_out_T_1811; // @[RegisterRouter.scala:87:24] assign in_1_ready = _out_in_ready_T_1; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_1_valid = _out_front_valid_T_1; // @[RegisterRouter.scala:87:24] assign out_front_1_ready = _out_front_ready_T_1; // @[RegisterRouter.scala:87:24] assign out_1_valid = _out_out_valid_T_1; // @[RegisterRouter.scala:87:24] wire [255:0] _GEN_24 = {{_out_out_bits_data_WIRE_2_255}, {_out_out_bits_data_WIRE_2_254}, {_out_out_bits_data_WIRE_2_253}, {_out_out_bits_data_WIRE_2_252}, {_out_out_bits_data_WIRE_2_251}, {_out_out_bits_data_WIRE_2_250}, {_out_out_bits_data_WIRE_2_249}, {_out_out_bits_data_WIRE_2_248}, {_out_out_bits_data_WIRE_2_247}, {_out_out_bits_data_WIRE_2_246}, {_out_out_bits_data_WIRE_2_245}, {_out_out_bits_data_WIRE_2_244}, {_out_out_bits_data_WIRE_2_243}, {_out_out_bits_data_WIRE_2_242}, {_out_out_bits_data_WIRE_2_241}, {_out_out_bits_data_WIRE_2_240}, {_out_out_bits_data_WIRE_2_239}, {_out_out_bits_data_WIRE_2_238}, {_out_out_bits_data_WIRE_2_237}, {_out_out_bits_data_WIRE_2_236}, {_out_out_bits_data_WIRE_2_235}, {_out_out_bits_data_WIRE_2_234}, {_out_out_bits_data_WIRE_2_233}, {_out_out_bits_data_WIRE_2_232}, {_out_out_bits_data_WIRE_2_231}, {_out_out_bits_data_WIRE_2_230}, {_out_out_bits_data_WIRE_2_229}, {_out_out_bits_data_WIRE_2_228}, {_out_out_bits_data_WIRE_2_227}, {_out_out_bits_data_WIRE_2_226}, {_out_out_bits_data_WIRE_2_225}, {_out_out_bits_data_WIRE_2_224}, {_out_out_bits_data_WIRE_2_223}, {_out_out_bits_data_WIRE_2_222}, {_out_out_bits_data_WIRE_2_221}, {_out_out_bits_data_WIRE_2_220}, {_out_out_bits_data_WIRE_2_219}, {_out_out_bits_data_WIRE_2_218}, {_out_out_bits_data_WIRE_2_217}, {_out_out_bits_data_WIRE_2_216}, {_out_out_bits_data_WIRE_2_215}, {_out_out_bits_data_WIRE_2_214}, {_out_out_bits_data_WIRE_2_213}, {_out_out_bits_data_WIRE_2_212}, {_out_out_bits_data_WIRE_2_211}, {_out_out_bits_data_WIRE_2_210}, {_out_out_bits_data_WIRE_2_209}, {_out_out_bits_data_WIRE_2_208}, {_out_out_bits_data_WIRE_2_207}, {_out_out_bits_data_WIRE_2_206}, {_out_out_bits_data_WIRE_2_205}, {_out_out_bits_data_WIRE_2_204}, {_out_out_bits_data_WIRE_2_203}, {_out_out_bits_data_WIRE_2_202}, {_out_out_bits_data_WIRE_2_201}, {_out_out_bits_data_WIRE_2_200}, {_out_out_bits_data_WIRE_2_199}, {_out_out_bits_data_WIRE_2_198}, {_out_out_bits_data_WIRE_2_197}, {_out_out_bits_data_WIRE_2_196}, {_out_out_bits_data_WIRE_2_195}, {_out_out_bits_data_WIRE_2_194}, {_out_out_bits_data_WIRE_2_193}, {_out_out_bits_data_WIRE_2_192}, {_out_out_bits_data_WIRE_2_191}, {_out_out_bits_data_WIRE_2_190}, {_out_out_bits_data_WIRE_2_189}, {_out_out_bits_data_WIRE_2_188}, {_out_out_bits_data_WIRE_2_187}, {_out_out_bits_data_WIRE_2_186}, {_out_out_bits_data_WIRE_2_185}, {_out_out_bits_data_WIRE_2_184}, {_out_out_bits_data_WIRE_2_183}, {_out_out_bits_data_WIRE_2_182}, {_out_out_bits_data_WIRE_2_181}, {_out_out_bits_data_WIRE_2_180}, {_out_out_bits_data_WIRE_2_179}, {_out_out_bits_data_WIRE_2_178}, {_out_out_bits_data_WIRE_2_177}, {_out_out_bits_data_WIRE_2_176}, {_out_out_bits_data_WIRE_2_175}, {_out_out_bits_data_WIRE_2_174}, {_out_out_bits_data_WIRE_2_173}, {_out_out_bits_data_WIRE_2_172}, {_out_out_bits_data_WIRE_2_171}, {_out_out_bits_data_WIRE_2_170}, {_out_out_bits_data_WIRE_2_169}, {_out_out_bits_data_WIRE_2_168}, {_out_out_bits_data_WIRE_2_167}, {_out_out_bits_data_WIRE_2_166}, {_out_out_bits_data_WIRE_2_165}, {_out_out_bits_data_WIRE_2_164}, {_out_out_bits_data_WIRE_2_163}, {_out_out_bits_data_WIRE_2_162}, {_out_out_bits_data_WIRE_2_161}, {_out_out_bits_data_WIRE_2_160}, {_out_out_bits_data_WIRE_2_159}, {_out_out_bits_data_WIRE_2_158}, {_out_out_bits_data_WIRE_2_157}, {_out_out_bits_data_WIRE_2_156}, {_out_out_bits_data_WIRE_2_155}, {_out_out_bits_data_WIRE_2_154}, {_out_out_bits_data_WIRE_2_153}, {_out_out_bits_data_WIRE_2_152}, {_out_out_bits_data_WIRE_2_151}, {_out_out_bits_data_WIRE_2_150}, {_out_out_bits_data_WIRE_2_149}, {_out_out_bits_data_WIRE_2_148}, {_out_out_bits_data_WIRE_2_147}, {_out_out_bits_data_WIRE_2_146}, {_out_out_bits_data_WIRE_2_145}, {_out_out_bits_data_WIRE_2_144}, {_out_out_bits_data_WIRE_2_143}, {_out_out_bits_data_WIRE_2_142}, {_out_out_bits_data_WIRE_2_141}, {_out_out_bits_data_WIRE_2_140}, {_out_out_bits_data_WIRE_2_139}, {_out_out_bits_data_WIRE_2_138}, {_out_out_bits_data_WIRE_2_137}, {_out_out_bits_data_WIRE_2_136}, {_out_out_bits_data_WIRE_2_135}, {_out_out_bits_data_WIRE_2_134}, {_out_out_bits_data_WIRE_2_133}, {_out_out_bits_data_WIRE_2_132}, {_out_out_bits_data_WIRE_2_131}, {_out_out_bits_data_WIRE_2_130}, {_out_out_bits_data_WIRE_2_129}, {_out_out_bits_data_WIRE_2_128}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_115}, {_out_out_bits_data_WIRE_2_114}, {_out_out_bits_data_WIRE_2_113}, {_out_out_bits_data_WIRE_2_112}, {_out_out_bits_data_WIRE_2_111}, {_out_out_bits_data_WIRE_2_110}, {_out_out_bits_data_WIRE_2_109}, {_out_out_bits_data_WIRE_2_108}, {_out_out_bits_data_WIRE_2_107}, {_out_out_bits_data_WIRE_2_106}, {_out_out_bits_data_WIRE_2_105}, {_out_out_bits_data_WIRE_2_104}, {_out_out_bits_data_WIRE_2_103}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_96}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_33}, {_out_out_bits_data_WIRE_2_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_2_10}, {_out_out_bits_data_WIRE_2_9}, {_out_out_bits_data_WIRE_2_8}, {_out_out_bits_data_WIRE_2_7}, {_out_out_bits_data_WIRE_2_6}, {_out_out_bits_data_WIRE_2_5}, {_out_out_bits_data_WIRE_2_4}, {_out_out_bits_data_WIRE_2_3}, {_out_out_bits_data_WIRE_2_2}, {_out_out_bits_data_WIRE_2_1}, {_out_out_bits_data_WIRE_2_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_6 = _GEN_24[out_oindex_1]; // @[MuxLiteral.scala:49:10] wire [255:0][63:0] _GEN_25 = {{_out_out_bits_data_WIRE_3_255}, {_out_out_bits_data_WIRE_3_254}, {_out_out_bits_data_WIRE_3_253}, {_out_out_bits_data_WIRE_3_252}, {_out_out_bits_data_WIRE_3_251}, {_out_out_bits_data_WIRE_3_250}, {_out_out_bits_data_WIRE_3_249}, {_out_out_bits_data_WIRE_3_248}, {_out_out_bits_data_WIRE_3_247}, {_out_out_bits_data_WIRE_3_246}, {_out_out_bits_data_WIRE_3_245}, {_out_out_bits_data_WIRE_3_244}, {_out_out_bits_data_WIRE_3_243}, {_out_out_bits_data_WIRE_3_242}, {_out_out_bits_data_WIRE_3_241}, {_out_out_bits_data_WIRE_3_240}, {_out_out_bits_data_WIRE_3_239}, {_out_out_bits_data_WIRE_3_238}, {_out_out_bits_data_WIRE_3_237}, {_out_out_bits_data_WIRE_3_236}, {_out_out_bits_data_WIRE_3_235}, {_out_out_bits_data_WIRE_3_234}, {_out_out_bits_data_WIRE_3_233}, {_out_out_bits_data_WIRE_3_232}, {_out_out_bits_data_WIRE_3_231}, {_out_out_bits_data_WIRE_3_230}, {_out_out_bits_data_WIRE_3_229}, {_out_out_bits_data_WIRE_3_228}, {_out_out_bits_data_WIRE_3_227}, {_out_out_bits_data_WIRE_3_226}, {_out_out_bits_data_WIRE_3_225}, {_out_out_bits_data_WIRE_3_224}, {_out_out_bits_data_WIRE_3_223}, {_out_out_bits_data_WIRE_3_222}, {_out_out_bits_data_WIRE_3_221}, {_out_out_bits_data_WIRE_3_220}, {_out_out_bits_data_WIRE_3_219}, {_out_out_bits_data_WIRE_3_218}, {_out_out_bits_data_WIRE_3_217}, {_out_out_bits_data_WIRE_3_216}, {_out_out_bits_data_WIRE_3_215}, {_out_out_bits_data_WIRE_3_214}, {_out_out_bits_data_WIRE_3_213}, {_out_out_bits_data_WIRE_3_212}, {_out_out_bits_data_WIRE_3_211}, {_out_out_bits_data_WIRE_3_210}, {_out_out_bits_data_WIRE_3_209}, {_out_out_bits_data_WIRE_3_208}, {_out_out_bits_data_WIRE_3_207}, {_out_out_bits_data_WIRE_3_206}, {_out_out_bits_data_WIRE_3_205}, {_out_out_bits_data_WIRE_3_204}, {_out_out_bits_data_WIRE_3_203}, {_out_out_bits_data_WIRE_3_202}, {_out_out_bits_data_WIRE_3_201}, {_out_out_bits_data_WIRE_3_200}, {_out_out_bits_data_WIRE_3_199}, {_out_out_bits_data_WIRE_3_198}, {_out_out_bits_data_WIRE_3_197}, {_out_out_bits_data_WIRE_3_196}, {_out_out_bits_data_WIRE_3_195}, {_out_out_bits_data_WIRE_3_194}, {_out_out_bits_data_WIRE_3_193}, {_out_out_bits_data_WIRE_3_192}, {_out_out_bits_data_WIRE_3_191}, {_out_out_bits_data_WIRE_3_190}, {_out_out_bits_data_WIRE_3_189}, {_out_out_bits_data_WIRE_3_188}, {_out_out_bits_data_WIRE_3_187}, {_out_out_bits_data_WIRE_3_186}, {_out_out_bits_data_WIRE_3_185}, {_out_out_bits_data_WIRE_3_184}, {_out_out_bits_data_WIRE_3_183}, {_out_out_bits_data_WIRE_3_182}, {_out_out_bits_data_WIRE_3_181}, {_out_out_bits_data_WIRE_3_180}, {_out_out_bits_data_WIRE_3_179}, {_out_out_bits_data_WIRE_3_178}, {_out_out_bits_data_WIRE_3_177}, {_out_out_bits_data_WIRE_3_176}, {_out_out_bits_data_WIRE_3_175}, {_out_out_bits_data_WIRE_3_174}, {_out_out_bits_data_WIRE_3_173}, {_out_out_bits_data_WIRE_3_172}, {_out_out_bits_data_WIRE_3_171}, {_out_out_bits_data_WIRE_3_170}, {_out_out_bits_data_WIRE_3_169}, {_out_out_bits_data_WIRE_3_168}, {_out_out_bits_data_WIRE_3_167}, {_out_out_bits_data_WIRE_3_166}, {_out_out_bits_data_WIRE_3_165}, {_out_out_bits_data_WIRE_3_164}, {_out_out_bits_data_WIRE_3_163}, {_out_out_bits_data_WIRE_3_162}, {_out_out_bits_data_WIRE_3_161}, {_out_out_bits_data_WIRE_3_160}, {_out_out_bits_data_WIRE_3_159}, {_out_out_bits_data_WIRE_3_158}, {_out_out_bits_data_WIRE_3_157}, {_out_out_bits_data_WIRE_3_156}, {_out_out_bits_data_WIRE_3_155}, {_out_out_bits_data_WIRE_3_154}, {_out_out_bits_data_WIRE_3_153}, {_out_out_bits_data_WIRE_3_152}, {_out_out_bits_data_WIRE_3_151}, {_out_out_bits_data_WIRE_3_150}, {_out_out_bits_data_WIRE_3_149}, {_out_out_bits_data_WIRE_3_148}, {_out_out_bits_data_WIRE_3_147}, {_out_out_bits_data_WIRE_3_146}, {_out_out_bits_data_WIRE_3_145}, {_out_out_bits_data_WIRE_3_144}, {_out_out_bits_data_WIRE_3_143}, {_out_out_bits_data_WIRE_3_142}, {_out_out_bits_data_WIRE_3_141}, {_out_out_bits_data_WIRE_3_140}, {_out_out_bits_data_WIRE_3_139}, {_out_out_bits_data_WIRE_3_138}, {_out_out_bits_data_WIRE_3_137}, {_out_out_bits_data_WIRE_3_136}, {_out_out_bits_data_WIRE_3_135}, {_out_out_bits_data_WIRE_3_134}, {_out_out_bits_data_WIRE_3_133}, {_out_out_bits_data_WIRE_3_132}, {_out_out_bits_data_WIRE_3_131}, {_out_out_bits_data_WIRE_3_130}, {_out_out_bits_data_WIRE_3_129}, {_out_out_bits_data_WIRE_3_128}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {_out_out_bits_data_WIRE_3_115}, {_out_out_bits_data_WIRE_3_114}, {_out_out_bits_data_WIRE_3_113}, {_out_out_bits_data_WIRE_3_112}, {_out_out_bits_data_WIRE_3_111}, {_out_out_bits_data_WIRE_3_110}, {_out_out_bits_data_WIRE_3_109}, {_out_out_bits_data_WIRE_3_108}, {_out_out_bits_data_WIRE_3_107}, {_out_out_bits_data_WIRE_3_106}, {_out_out_bits_data_WIRE_3_105}, {_out_out_bits_data_WIRE_3_104}, {_out_out_bits_data_WIRE_3_103}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h380006F}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h0}, {64'h100073}, {64'h100026237B200073}, {64'h7B20247310802423}, {64'hF140247330000067}, {64'h100022237B202473}, {64'h4086300147413}, {64'hFE0408E300347413}, {64'h4004440310802023}, {64'hF14024737B241073}, {64'hFF0000F0440006F}, {64'h380006F00C0006F}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_8 = _GEN_25[out_oindex_1]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_9 = _out_out_bits_data_T_6 ? _out_out_bits_data_T_8 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_1_bits_data = _out_out_bits_data_T_9; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27] wire hartHalted = _hartHalted_T; // @[Debug.scala:1734:37] wire [1:0] ctrlStateNxt; // @[Debug.scala:1735:32] assign _abstractCommandBusy_T = |ctrlStateReg; // @[Debug.scala:1732:27, :1740:42] assign abstractCommandBusy = _abstractCommandBusy_T; // @[Debug.scala:1220:39, :1740:42] assign _ABSTRACTCSWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44] assign ABSTRACTCSWrEnLegal = _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1190:39, :1742:44] assign _COMMANDWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1743:44] assign COMMANDWrEnLegal = _COMMANDWrEnLegal_T; // @[Debug.scala:1282:39, :1743:44] assign _ABSTRACTAUTOWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1744:44] assign ABSTRACTAUTOWrEnLegal = _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1243:41, :1744:44] assign _dmiAbstractDataAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1745:50] assign dmiAbstractDataAccessLegal = _dmiAbstractDataAccessLegal_T; // @[Debug.scala:892:46, :1745:50] assign _dmiProgramBufferAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1746:50] assign dmiProgramBufferAccessLegal = _dmiProgramBufferAccessLegal_T; // @[Debug.scala:888:47, :1746:50] wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39, :1748:45] wire _errorBusy_T_1 = ABSTRACTCSWrEnMaybe & _errorBusy_T; // @[Debug.scala:1188:39, :1748:{42,45}] wire _errorBusy_T_2 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45] wire _errorBusy_T_3 = autoexecdataWrEnMaybe & _errorBusy_T_2; // @[Debug.scala:1240:41, :1749:{42,45}] wire _errorBusy_T_4 = _errorBusy_T_1 | _errorBusy_T_3; // @[Debug.scala:1748:{42,74}, :1749:42] wire _errorBusy_T_5 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45, :1750:47] wire _errorBusy_T_6 = autoexecprogbufWrEnMaybe & _errorBusy_T_5; // @[Debug.scala:1241:44, :1750:{44,47}] wire _errorBusy_T_7 = _errorBusy_T_4 | _errorBusy_T_6; // @[Debug.scala:1748:74, :1749:74, :1750:44] wire _errorBusy_T_8 = ~COMMANDWrEnLegal; // @[Debug.scala:1282:39, :1751:45] wire _errorBusy_T_9 = COMMANDWrEnMaybe & _errorBusy_T_8; // @[Debug.scala:1281:39, :1751:{42,45}] wire _errorBusy_T_10 = _errorBusy_T_7 | _errorBusy_T_9; // @[Debug.scala:1749:74, :1750:74, :1751:42] wire _errorBusy_T_11 = ~dmiAbstractDataAccessLegal; // @[Debug.scala:892:46, :1752:45] wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T_11; // @[Debug.scala:1263:68, :1752:{42,45}] wire _errorBusy_T_13 = _errorBusy_T_10 | _errorBusy_T_12; // @[Debug.scala:1750:74, :1751:74, :1752:42] wire _errorBusy_T_14 = ~dmiProgramBufferAccessLegal; // @[Debug.scala:888:47, :1753:45] wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T_14; // @[Debug.scala:1264:69, :1753:{42,45}] assign _errorBusy_T_16 = _errorBusy_T_13 | _errorBusy_T_15; // @[Debug.scala:1751:74, :1752:74, :1753:42] assign errorBusy = _errorBusy_T_16; // @[Debug.scala:1195:36, :1752:74] wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala:1280:39, :1756:60] wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58] wire _commandWrIsUnsupported_T = ~commandWrIsAccessRegister; // @[Debug.scala:1756:60, :1759:49] wire commandWrIsUnsupported = COMMANDWrEn & _commandWrIsUnsupported_T; // @[Debug.scala:1285:40, :1759:{46,49}] wire commandRegIsUnsupported; // @[Debug.scala:1761:43] wire commandRegBadHaltResume; // @[Debug.scala:1762:43] wire _accessRegIsLegalSize_T = accessRegisterCommandReg_size == 3'h2; // @[Debug.scala:1533:44, :1765:63] wire _accessRegIsLegalSize_T_1 = accessRegisterCommandReg_size == 3'h3; // @[Debug.scala:1533:44, :1765:106] wire accessRegIsLegalSize = _accessRegIsLegalSize_T | _accessRegIsLegalSize_T_1; // @[Debug.scala:1765:{63,72,106}] wire _accessRegIsGPR_T = |(accessRegisterCommandReg_regno[15:12]); // @[Debug.scala:1533:44, :1766:58] wire _accessRegIsGPR_T_1 = accessRegisterCommandReg_regno < 16'h1020; // @[Debug.scala:1533:44, :1766:104] wire _accessRegIsGPR_T_2 = _accessRegIsGPR_T & _accessRegIsGPR_T_1; // @[Debug.scala:1766:{58,70,104}] wire accessRegIsGPR = _accessRegIsGPR_T_2 & accessRegIsLegalSize; // @[Debug.scala:1765:72, :1766:{70,117}] wire _T_1567 = ~accessRegisterCommandReg_transfer | accessRegIsGPR; // @[Debug.scala:1533:44, :1766:117, :1776:{19,54}] assign commandRegIsUnsupported = ~commandRegIsAccessRegister | ~_T_1567; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33] wire _commandRegBadHaltResume_T = ~hartHalted; // @[Debug.scala:1734:37, :1778:36] assign commandRegBadHaltResume = commandRegIsAccessRegister & _T_1567 & _commandRegBadHaltResume_T; // @[Debug.scala:1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}] wire _wrAccessRegisterCommand_T = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala:1285:40, :1756:60, :1782:48] wire _GEN_26 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103] wire _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:103] assign _wrAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103] wire _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:103] assign _regAccessRegisterCommand_T_1 = _GEN_26; // @[Debug.scala:1782:103, :1783:103] wire wrAccessRegisterCommand = _wrAccessRegisterCommand_T & _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:{48,78,103}] wire _regAccessRegisterCommand_T = autoexec & commandRegIsAccessRegister; // @[Debug.scala:1272:48, :1757:58, :1783:48] wire regAccessRegisterCommand = _regAccessRegisterCommand_T & _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:{48,78,103}] wire _T_1569 = wrAccessRegisterCommand | regAccessRegisterCommand; // @[Debug.scala:1782:78, :1783:78, :1790:37] wire _T_1571 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30] assign errorUnsupported = (|ctrlStateReg) ? _T_1571 & commandRegIsUnsupported : ~_T_1569 & (commandWrIsUnsupported | autoexec & commandRegIsUnsupported); // @[Debug.scala:1197:36, :1272:48, :1732:27, :1740:42, :1759:46, :1761:43, :1789:47, :1790:{37,66}, :1792:43, :1793:26, :1794:{28,56}, :1797:{30,59}, :1804:38] assign errorHaltResume = (|ctrlStateReg) & _T_1571 & ~commandRegIsUnsupported & commandRegBadHaltResume; // @[Debug.scala:1198:36, :1732:27, :1740:42, :1761:43, :1762:43, :1789:47, :1797:{30,59}, :1804:38, :1807:43] wire _GEN_27 = commandRegIsUnsupported | commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] assign goAbstract = (|ctrlStateReg) & _T_1571 & ~_GEN_27; // @[Debug.scala:1495:32, :1732:27, :1740:42, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33] wire _T_1572 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30] wire _GEN_28 = ~(|ctrlStateReg) | _T_1571; // @[Debug.scala:1196:36, :1732:27, :1740:42, :1742:44, :1789:47, :1797:{30,59}, :1818:51] assign errorException = ~_GEN_28 & _T_1572 & hartExceptionWrEn; // @[Debug.scala:881:36, :1196:36, :1789:47, :1797:59, :1818:{30,51}, :1826:31] assign goCustom = ~(_GEN_28 | _T_1572) & (&ctrlStateReg); // @[Debug.scala:1196:36, :1496:32, :1732:27, :1789:47, :1797:59, :1818:{30,51}, :1831:{30,53}] assign ctrlStateNxt = (|ctrlStateReg) ? (_T_1571 ? {~_GEN_27, 1'h0} : _T_1572 & (hartExceptionWrEn | ~goReg & hartHaltedWrEn) ? 2'h0 : ctrlStateReg) : _T_1569 ? 2'h1 : ctrlStateReg; // @[Debug.scala:875:36, :881:36, :1494:27, :1732:27, :1735:32, :1740:42, :1789:47, :1790:{37,66}, :1791:22, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33, :1818:{30,51}, :1823:{18,30,116}, :1824:22, :1826:31, :1828:24, :1831:53]

Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module AsyncResetRegVec_w1_i0_4( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLInterconnectCoupler_cbus_to_debug( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34] wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [11:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] TLFragmenter_Debug fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0), .auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7] ); // @[Fragmenter.scala:345:34] assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_73( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a32d128s4k4z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_source = 4'h0; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_source = 4'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_45 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s4k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s4k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s4k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s4k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s4k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLBuffer_a32d64s4k5z4u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (auto_buffer_in_a_ready), .auto_in_a_valid (auto_buffer_in_a_valid), .auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode), .auto_in_a_bits_param (auto_buffer_in_a_bits_param), .auto_in_a_bits_size (auto_buffer_in_a_bits_size), .auto_in_a_bits_source (auto_buffer_in_a_bits_source), .auto_in_a_bits_address (auto_buffer_in_a_bits_address), .auto_in_a_bits_mask (auto_buffer_in_a_bits_mask), .auto_in_a_bits_data (auto_buffer_in_a_bits_data), .auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt), .auto_in_d_ready (auto_buffer_in_d_ready), .auto_in_d_valid (auto_buffer_in_d_valid), .auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode), .auto_in_d_bits_param (auto_buffer_in_d_bits_param), .auto_in_d_bits_size (auto_buffer_in_d_bits_size), .auto_in_d_bits_source (auto_buffer_in_d_bits_source), .auto_in_d_bits_sink (auto_buffer_in_d_bits_sink), .auto_in_d_bits_denied (auto_buffer_in_d_bits_denied), .auto_in_d_bits_data (auto_buffer_in_d_bits_data), .auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt), .auto_out_a_ready (auto_tl_out_a_ready), .auto_out_a_valid (auto_tl_out_a_valid), .auto_out_a_bits_opcode (auto_tl_out_a_bits_opcode), .auto_out_a_bits_param (auto_tl_out_a_bits_param), .auto_out_a_bits_size (auto_tl_out_a_bits_size), .auto_out_a_bits_source (auto_tl_out_a_bits_source), .auto_out_a_bits_address (auto_tl_out_a_bits_address), .auto_out_a_bits_mask (auto_tl_out_a_bits_mask), .auto_out_a_bits_data (auto_tl_out_a_bits_data), .auto_out_a_bits_corrupt (auto_tl_out_a_bits_corrupt), .auto_out_d_ready (auto_tl_out_d_ready), .auto_out_d_valid (auto_tl_out_d_valid), .auto_out_d_bits_opcode (auto_tl_out_d_bits_opcode), .auto_out_d_bits_param (auto_tl_out_d_bits_param), .auto_out_d_bits_size (auto_tl_out_d_bits_size), .auto_out_d_bits_source (auto_tl_out_d_bits_source), .auto_out_d_bits_sink (auto_tl_out_d_bits_sink), .auto_out_d_bits_denied (auto_tl_out_d_bits_denied), .auto_out_d_bits_data (auto_tl_out_d_bits_data), .auto_out_d_bits_corrupt (auto_tl_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLBuffer_a29d64s7k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_9 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s7k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s7k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }

module L1MetadataArray_1( // @[HellaCache.scala:322:7] input clock, // @[HellaCache.scala:322:7] input reset, // @[HellaCache.scala:322:7] output io_read_ready, // @[HellaCache.scala:324:14] input io_read_valid, // @[HellaCache.scala:324:14] input [3:0] io_read_bits_idx, // @[HellaCache.scala:324:14] input [1:0] io_read_bits_way_en, // @[HellaCache.scala:324:14] input [21:0] io_read_bits_tag, // @[HellaCache.scala:324:14] output io_write_ready, // @[HellaCache.scala:324:14] input io_write_valid, // @[HellaCache.scala:324:14] input [3:0] io_write_bits_idx, // @[HellaCache.scala:324:14] input [1:0] io_write_bits_way_en, // @[HellaCache.scala:324:14] input [21:0] io_write_bits_tag, // @[HellaCache.scala:324:14] input [1:0] io_write_bits_data_coh_state, // @[HellaCache.scala:324:14] input [21:0] io_write_bits_data_tag, // @[HellaCache.scala:324:14] output [1:0] io_resp_0_coh_state, // @[HellaCache.scala:324:14] output [21:0] io_resp_0_tag, // @[HellaCache.scala:324:14] output [1:0] io_resp_1_coh_state, // @[HellaCache.scala:324:14] output [21:0] io_resp_1_tag // @[HellaCache.scala:324:14] ); wire tag_array_MPORT_1_en; // @[Decoupled.scala:51:35] wire [3:0] tag_array_MPORT_addr; // @[HellaCache.scala:342:20] wire [47:0] _tag_array_RW0_rdata; // @[HellaCache.scala:339:30] wire io_read_valid_0 = io_read_valid; // @[HellaCache.scala:322:7] wire [3:0] io_read_bits_idx_0 = io_read_bits_idx; // @[HellaCache.scala:322:7] wire [1:0] io_read_bits_way_en_0 = io_read_bits_way_en; // @[HellaCache.scala:322:7] wire [21:0] io_read_bits_tag_0 = io_read_bits_tag; // @[HellaCache.scala:322:7] wire io_write_valid_0 = io_write_valid; // @[HellaCache.scala:322:7] wire [3:0] io_write_bits_idx_0 = io_write_bits_idx; // @[HellaCache.scala:322:7] wire [1:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[HellaCache.scala:322:7] wire [21:0] io_write_bits_tag_0 = io_write_bits_tag; // @[HellaCache.scala:322:7] wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[HellaCache.scala:322:7] wire [21:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[HellaCache.scala:322:7] wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [21:0] rstVal_tag = 22'h0; // @[HellaCache.scala:305:20] wire _io_read_ready_T; // @[HellaCache.scala:346:20] wire [1:0] _rmask_T_1 = io_read_bits_way_en_0; // @[HellaCache.scala:322:7, :335:70] wire _io_write_ready_T; // @[HellaCache.scala:347:21] wire [1:0] _wmask_T_1 = io_write_bits_way_en_0; // @[HellaCache.scala:322:7, :334:71] wire io_read_ready_0; // @[HellaCache.scala:322:7] wire io_write_ready_0; // @[HellaCache.scala:322:7] wire [1:0] io_resp_0_coh_state_0; // @[HellaCache.scala:322:7] wire [21:0] io_resp_0_tag_0; // @[HellaCache.scala:322:7] wire [1:0] io_resp_1_coh_state_0; // @[HellaCache.scala:322:7] wire [21:0] io_resp_1_tag_0; // @[HellaCache.scala:322:7] reg [4:0] rst_cnt; // @[HellaCache.scala:330:24] wire rst = ~(rst_cnt[4]); // @[HellaCache.scala:330:24, :331:21] wire _wmask_T = rst; // @[HellaCache.scala:331:21, :334:23] wire _rmask_T = rst; // @[HellaCache.scala:331:21, :335:23] wire [4:0] waddr = rst ? rst_cnt : {1'h0, io_write_bits_idx_0}; // @[HellaCache.scala:322:7, :330:24, :331:21, :332:18] wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[HellaCache.scala:322:7, :331:21, :333:18] wire [21:0] _wdata_T_tag = rst ? 22'h0 : io_write_bits_data_tag_0; // @[HellaCache.scala:322:7, :331:21, :333:18] wire [23:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[HellaCache.scala:333:{18,52}] wire [1:0] _wmask_T_2 = _wmask_T ? 2'h3 : _wmask_T_1; // @[HellaCache.scala:334:{18,23,71}] wire wmask_0 = _wmask_T_2[0]; // @[HellaCache.scala:334:{18,79}] wire wmask_1 = _wmask_T_2[1]; // @[HellaCache.scala:334:{18,79}] wire [1:0] _rmask_T_2 = _rmask_T ? 2'h3 : _rmask_T_1; // @[HellaCache.scala:335:{18,23,70}] wire rmask_0 = _rmask_T_2[0]; // @[HellaCache.scala:335:{18,78}] wire rmask_1 = _rmask_T_2[1]; // @[HellaCache.scala:335:{18,78}] wire [5:0] _rst_cnt_T = {1'h0, rst_cnt} + 6'h1; // @[HellaCache.scala:330:24, :332:18, :336:34] wire [4:0] _rst_cnt_T_1 = _rst_cnt_T[4:0]; // @[HellaCache.scala:336:34] wire wen; // @[HellaCache.scala:340:17] assign wen = rst | io_write_valid_0; // @[HellaCache.scala:322:7, :331:21, :340:17] assign tag_array_MPORT_addr = waddr[3:0]; // @[HellaCache.scala:332:18, :342:20] assign tag_array_MPORT_1_en = io_read_ready_0 & io_read_valid_0; // @[Decoupled.scala:51:35] assign io_resp_0_tag_0 = _tag_array_RW0_rdata[21:0]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_0_coh_state_0 = _tag_array_RW0_rdata[23:22]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_1_tag_0 = _tag_array_RW0_rdata[45:24]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign io_resp_1_coh_state_0 = _tag_array_RW0_rdata[47:46]; // @[HellaCache.scala:322:7, :339:30, :344:75] assign _io_read_ready_T = ~wen; // @[HellaCache.scala:340:17, :346:20] assign io_read_ready_0 = _io_read_ready_T; // @[HellaCache.scala:322:7, :346:20] assign _io_write_ready_T = ~rst; // @[HellaCache.scala:331:21, :347:21] assign io_write_ready_0 = _io_write_ready_T; // @[HellaCache.scala:322:7, :347:21] always @(posedge clock) begin // @[HellaCache.scala:322:7] if (reset) // @[HellaCache.scala:322:7] rst_cnt <= 5'h0; // @[HellaCache.scala:330:24] else if (rst) // @[HellaCache.scala:331:21] rst_cnt <= _rst_cnt_T_1; // @[HellaCache.scala:330:24, :336:34] always @(posedge) tag_array_0 tag_array ( // @[HellaCache.scala:339:30] .RW0_addr (wen ? tag_array_MPORT_addr : io_read_bits_idx_0), // @[HellaCache.scala:322:7, :339:30, :340:17, :342:20] .RW0_en (tag_array_MPORT_1_en | wen), // @[Decoupled.scala:51:35] .RW0_clk (clock), .RW0_wmode (wen), // @[HellaCache.scala:340:17] .RW0_wdata ({2{wdata}}), // @[HellaCache.scala:333:52, :339:30] .RW0_rdata (_tag_array_RW0_rdata), .RW0_wmask ({wmask_1, wmask_0}) // @[HellaCache.scala:334:79, :339:30] ); // @[HellaCache.scala:339:30] assign io_read_ready = io_read_ready_0; // @[HellaCache.scala:322:7] assign io_write_ready = io_write_ready_0; // @[HellaCache.scala:322:7] assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[HellaCache.scala:322:7] assign io_resp_0_tag = io_resp_0_tag_0; // @[HellaCache.scala:322:7] assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[HellaCache.scala:322:7] assign io_resp_1_tag = io_resp_1_tag_0; // @[HellaCache.scala:322:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module AsyncResetRegVec_w1_i0_49( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File SourceE.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceERequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val sink = UInt(params.outer.bundle.sinkBits.W) } class SourceE(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceERequest(params))) val e = Decoupled(new TLBundleE(params.outer.bundle)) }) // ready must be a register, because we derive valid from ready require (!params.micro.outerBuf.e.pipe && params.micro.outerBuf.e.isDefined) val e = Wire(chiselTypeOf(io.e)) io.e <> params.micro.outerBuf.e(e) io.req.ready := e.ready e.valid := io.req.valid e.bits.sink := io.req.bits.sink // we can't cover valid+!ready, because no backpressure on E is common }

module SourceE_6( // @[SourceE.scala:29:7] input clock, // @[SourceE.scala:29:7] input reset, // @[SourceE.scala:29:7] output io_req_ready, // @[SourceE.scala:31:14] input io_req_valid, // @[SourceE.scala:31:14] input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14] output io_e_valid, // @[SourceE.scala:31:14] output [2:0] io_e_bits_sink // @[SourceE.scala:31:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceE.scala:29:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceE.scala:29:7] wire io_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire e_ready; // @[SourceE.scala:39:15] wire e_valid = io_req_valid_0; // @[SourceE.scala:29:7, :39:15] wire [2:0] e_bits_sink = io_req_bits_sink_0; // @[SourceE.scala:29:7, :39:15] wire io_req_ready_0; // @[SourceE.scala:29:7] wire [2:0] io_e_bits_sink_0; // @[SourceE.scala:29:7] wire io_e_valid_0; // @[SourceE.scala:29:7] assign io_req_ready_0 = e_ready; // @[SourceE.scala:29:7, :39:15] Queue2_TLBundleE_a32d64s4k3z3c_6 io_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (e_ready), .io_enq_valid (e_valid), // @[SourceE.scala:39:15] .io_enq_bits_sink (e_bits_sink), // @[SourceE.scala:39:15] .io_deq_valid (io_e_valid_0), .io_deq_bits_sink (io_e_bits_sink_0) ); // @[Decoupled.scala:362:21] assign io_req_ready = io_req_ready_0; // @[SourceE.scala:29:7] assign io_e_valid = io_e_valid_0; // @[SourceE.scala:29:7] assign io_e_bits_sink = io_e_bits_sink_0; // @[SourceE.scala:29:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module PE_369( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_113 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_11( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [3:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [3:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [31:0] io_out_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_27 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7] .io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7] .io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7] .io_out_a_bits (io_out_a_0_bits), .io_out_b_bits (io_out_b_0_bits_0), .io_out_c_bits (io_out_c_0_bits_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7] assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File JtagShifter.scala: // See LICENSE.jtag for license details. package freechips.rocketchip.jtag import chisel3._ import chisel3.reflect.DataMirror import chisel3.internal.firrtl.KnownWidth import chisel3.util.{Cat, Valid} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.property /** Base JTAG shifter IO, viewed from input to shift register chain. * Can be chained together. */ class ShifterIO extends Bundle { val shift = Bool() // advance the scan chain on clock high val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB val capture = Bool() // high in the CaptureIR/DR state when this chain is selected val update = Bool() // high in the UpdateIR/DR state when this chain is selected /** Sets a output shifter IO's control signals from a input shifter IO's control signals. */ def chainControlFrom(in: ShifterIO): Unit = { shift := in.shift capture := in.capture update := in.update } } trait ChainIO extends Bundle { val chainIn = Input(new ShifterIO) val chainOut = Output(new ShifterIO) } class Capture[+T <: Data](gen: T) extends Bundle { val bits = Input(gen) // data to capture, should be always valid val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge } object Capture { def apply[T <: Data](gen: T): Capture[T] = new Capture(gen) } /** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain * IO. */ trait Chain extends Module { val io: ChainIO } /** One-element shift register, data register for bypass mode. * * Implements Clause 10. */ class JtagBypassChain(implicit val p: Parameters) extends Chain { class ModIO extends ChainIO val io = IO(new ModIO) io.chainOut chainControlFrom io.chainIn val reg = Reg(Bool()) // 10.1.1a single shift register stage io.chainOut.data := reg property.cover(io.chainIn.capture, "bypass_chain_capture", "JTAG; bypass_chain_capture; This Bypass Chain captured data") when (io.chainIn.capture) { reg := false.B // 10.1.1b capture logic 0 on TCK rising } .elsewhen (io.chainIn.shift) { reg := io.chainIn.data } assert(!(io.chainIn.capture && io.chainIn.update) && !(io.chainIn.capture && io.chainIn.shift) && !(io.chainIn.update && io.chainIn.shift)) } object JtagBypassChain { def apply()(implicit p: Parameters) = new JtagBypassChain } /** Simple shift register with parallel capture only, for read-only data registers. * * Number of stages is the number of bits in gen, which must have a known width. * * Useful notes: * 7.2.1c shifter shifts on TCK rising edge * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge */ class CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain { override def desiredName = s"CaptureChain_${gen.typeName}" class ModIO extends ChainIO { val capture = Capture(gen) } val io = IO(new ModIO) io.chainOut chainControlFrom io.chainIn val n = DataMirror.widthOf(gen) match { case KnownWidth(x) => x case _ => require(false, s"can't generate chain for unknown width data type $gen"); -1 // TODO: remove -1 type hack } val regs = (0 until n) map (x => Reg(Bool())) io.chainOut.data := regs(0) property.cover(io.chainIn.capture, "chain_capture", "JTAG; chain_capture; This Chain captured data") when (io.chainIn.capture) { (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x)) io.capture.capture := true.B } .elsewhen (io.chainIn.shift) { regs(n-1) := io.chainIn.data (0 until n-1) map (x => regs(x) := regs(x+1)) io.capture.capture := false.B } .otherwise { io.capture.capture := false.B } assert(!(io.chainIn.capture && io.chainIn.update) && !(io.chainIn.capture && io.chainIn.shift) && !(io.chainIn.update && io.chainIn.shift)) } object CaptureChain { def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen) } /** Simple shift register with parallel capture and update. Useful for general instruction and data * scan registers. * * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have * known widths. If there is a width mismatch, the unused most significant bits will be zero. * * Useful notes: * 7.2.1c shifter shifts on TCK rising edge * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge */ class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain { override def desiredName = s"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}" class ModIO extends ChainIO { val capture = Capture(genCapture) val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after } val io = IO(new ModIO) io.chainOut chainControlFrom io.chainIn val captureWidth = DataMirror.widthOf(genCapture) match { case KnownWidth(x) => x case _ => require(false, s"can't generate chain for unknown width data type $genCapture"); -1 // TODO: remove -1 type hack } val updateWidth = DataMirror.widthOf(genUpdate) match { case KnownWidth(x) => x case _ => require(false, s"can't generate chain for unknown width data type $genUpdate"); -1 // TODO: remove -1 type hack } val n = math.max(captureWidth, updateWidth) val regs = (0 until n) map (x => Reg(Bool())) io.chainOut.data := regs(0) val updateBits = Cat(regs.reverse)(updateWidth-1, 0) io.update.bits := updateBits.asTypeOf(io.update.bits) val captureBits = io.capture.bits.asUInt property.cover(io.chainIn.capture, "chain_capture", "JTAG;chain_capture; This Chain captured data") property.cover(io.chainIn.capture, "chain_update", "JTAG;chain_update; This Chain updated data") when (io.chainIn.capture) { (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x)) (captureWidth until n) map (x => regs(x) := 0.U) io.capture.capture := true.B io.update.valid := false.B } .elsewhen (io.chainIn.update) { io.capture.capture := false.B io.update.valid := true.B } .elsewhen (io.chainIn.shift) { regs(n-1) := io.chainIn.data (0 until n-1) map (x => regs(x) := regs(x+1)) io.capture.capture := false.B io.update.valid := false.B } .otherwise { io.capture.capture := false.B io.update.valid := false.B } assert(!(io.chainIn.capture && io.chainIn.update) && !(io.chainIn.capture && io.chainIn.shift) && !(io.chainIn.update && io.chainIn.shift)) } object CaptureUpdateChain { /** Capture-update chain with matching capture and update types. */ def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen) def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) = new CaptureUpdateChain(genCapture, genUpdate) }

module JtagBypassChain( // @[JtagShifter.scala:56:7] input clock, // @[JtagShifter.scala:56:7] input reset, // @[JtagShifter.scala:56:7] input io_chainIn_shift, // @[JtagShifter.scala:58:14] input io_chainIn_data, // @[JtagShifter.scala:58:14] input io_chainIn_capture, // @[JtagShifter.scala:58:14] input io_chainIn_update, // @[JtagShifter.scala:58:14] output io_chainOut_data // @[JtagShifter.scala:58:14] ); reg reg_0; // @[JtagShifter.scala:61:16]

Generate the Verilog code corresponding to the following Chisel files. File Mesh.scala: package gemmini import chisel3._ import chisel3.util._ import chisel3.experimental._ /** * A Grid is a 2D array of Tile modules with registers in between each tile and * registers from the bottom row and rightmost column of tiles to the Grid outputs. * @param width * @param tileRows * @param tileColumns * @param meshRows * @param meshColumns */ class Mesh[T <: Data : Arithmetic](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, tile_latency: Int, max_simultaneous_matmuls: Int, output_delay: Int, val tileRows: Int, val tileColumns: Int, val meshRows: Int, val meshColumns: Int) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(meshRows, Vec(tileRows, inputType))) val in_b = Input(Vec(meshColumns, Vec(tileColumns, inputType))) val in_d = Input(Vec(meshColumns, Vec(tileColumns, inputType))) val in_control = Input(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) val in_id = Input(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) // The unique id of this particular matmul val in_last = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) val out_b = Output(Vec(meshColumns, Vec(tileColumns, outputType))) val out_c = Output(Vec(meshColumns, Vec(tileColumns, outputType))) val in_valid = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) val out_valid = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) val out_control = Output(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) val out_id = Output(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) val out_last = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) }) // mesh(r)(c) => Tile at row r, column c val mesh: Seq[Seq[Tile[T]]] = Seq.fill(meshRows, meshColumns)(Module(new Tile(inputType, outputType, accType, df, tree_reduction, max_simultaneous_matmuls, tileRows, tileColumns))) val meshT = mesh.transpose def pipe[T <: Data](valid: Bool, t: T, latency: Int): T = { // The default "Pipe" function apparently resets the valid signals to false.B. We would like to avoid using global // signals in the Mesh, so over here, we make it clear that the reset signal will never be asserted chisel3.withReset(false.B) { Pipe(valid, t, latency).bits } } // Chain tile_a_out -> tile_a_in (pipeline a across each row) // TODO clock-gate A signals with in_garbage for (r <- 0 until meshRows) { mesh(r).foldLeft(io.in_a(r)) { case (in_a, tile) => tile.io.in_a := ShiftRegister(in_a, tile_latency+1) tile.io.out_a } } // Chain tile_out_b -> tile_b_in (pipeline b across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft((io.in_b(c), io.in_valid(c))) { case ((in_b, valid), tile) => tile.io.in_b := pipe(valid.head, in_b, tile_latency+1) (tile.io.out_b, tile.io.out_valid) } } // Chain tile_out -> tile_propag (pipeline output across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft((io.in_d(c), io.in_valid(c))) { case ((in_propag, valid), tile) => tile.io.in_d := pipe(valid.head, in_propag, tile_latency+1) (tile.io.out_c, tile.io.out_valid) } } // Chain control signals (pipeline across each column) assert(!(mesh.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_))) for (c <- 0 until meshColumns) { meshT(c).foldLeft((io.in_control(c), io.in_valid(c))) { case ((in_ctrl, valid), tile) => (tile.io.in_control, in_ctrl, valid).zipped.foreach { case (tile_ctrl, ctrl, v) => tile_ctrl.shift := pipe(v, ctrl.shift, tile_latency+1) tile_ctrl.dataflow := pipe(v, ctrl.dataflow, tile_latency+1) tile_ctrl.propagate := pipe(v, ctrl.propagate, tile_latency+1) } (tile.io.out_control, tile.io.out_valid) } } // Chain in_valid (pipeline across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft(io.in_valid(c)) { case (in_v, tile) => tile.io.in_valid := ShiftRegister(in_v, tile_latency+1) tile.io.out_valid } } // Chain in_id (pipeline across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft(io.in_id(c)) { case (in_id, tile) => tile.io.in_id := ShiftRegister(in_id, tile_latency+1) tile.io.out_id } } // Chain in_last (pipeline across each column) for (c <- 0 until meshColumns) { meshT(c).foldLeft(io.in_last(c)) { case (in_last, tile) => tile.io.in_last := ShiftRegister(in_last, tile_latency+1) tile.io.out_last } } // Capture out_vec and out_control_vec (connect IO to bottom row of mesh) // (The only reason we have so many zips is because Scala doesn't provide a zipped function for Tuple4) for (((((((b, c), v), ctrl), id), last), tile) <- io.out_b zip io.out_c zip io.out_valid zip io.out_control zip io.out_id zip io.out_last zip mesh.last) { // TODO we pipelined this to make physical design easier. Consider removing these if possible // TODO shouldn't we clock-gate these signals with "garbage" as well? b := ShiftRegister(tile.io.out_b, output_delay) c := ShiftRegister(tile.io.out_c, output_delay) v := ShiftRegister(tile.io.out_valid, output_delay) ctrl := ShiftRegister(tile.io.out_control, output_delay) id := ShiftRegister(tile.io.out_id, output_delay) last := ShiftRegister(tile.io.out_last, output_delay) } }

module Mesh( // @[Mesh.scala:17:7] input clock, // @[Mesh.scala:17:7] input reset, // @[Mesh.scala:17:7] input [7:0] io_in_a_0_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_1_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_2_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_3_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_4_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_5_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_6_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_7_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_8_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_9_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_10_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_11_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_12_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_13_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_14_0, // @[Mesh.scala:22:14] input [7:0] io_in_a_15_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_0_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_1_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_2_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_3_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_4_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_5_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_6_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_7_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_8_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_9_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_10_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_11_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_12_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_13_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_14_0, // @[Mesh.scala:22:14] input [7:0] io_in_b_15_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_0_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_1_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_2_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_3_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_4_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_5_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_6_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_7_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_8_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_9_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_10_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_11_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_12_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_13_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_14_0, // @[Mesh.scala:22:14] input [7:0] io_in_d_15_0, // @[Mesh.scala:22:14] input io_in_control_0_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_0_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_0_0_shift, // @[Mesh.scala:22:14] input io_in_control_1_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_1_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_1_0_shift, // @[Mesh.scala:22:14] input io_in_control_2_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_2_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_2_0_shift, // @[Mesh.scala:22:14] input io_in_control_3_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_3_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_3_0_shift, // @[Mesh.scala:22:14] input io_in_control_4_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_4_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_4_0_shift, // @[Mesh.scala:22:14] input io_in_control_5_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_5_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_5_0_shift, // @[Mesh.scala:22:14] input io_in_control_6_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_6_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_6_0_shift, // @[Mesh.scala:22:14] input io_in_control_7_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_7_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_7_0_shift, // @[Mesh.scala:22:14] input io_in_control_8_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_8_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_8_0_shift, // @[Mesh.scala:22:14] input io_in_control_9_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_9_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_9_0_shift, // @[Mesh.scala:22:14] input io_in_control_10_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_10_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_10_0_shift, // @[Mesh.scala:22:14] input io_in_control_11_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_11_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_11_0_shift, // @[Mesh.scala:22:14] input io_in_control_12_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_12_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_12_0_shift, // @[Mesh.scala:22:14] input io_in_control_13_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_13_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_13_0_shift, // @[Mesh.scala:22:14] input io_in_control_14_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_14_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_14_0_shift, // @[Mesh.scala:22:14] input io_in_control_15_0_dataflow, // @[Mesh.scala:22:14] input io_in_control_15_0_propagate, // @[Mesh.scala:22:14] input [4:0] io_in_control_15_0_shift, // @[Mesh.scala:22:14] input [2:0] io_in_id_0_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_1_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_2_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_3_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_4_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_5_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_6_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_7_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_8_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_9_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_10_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_11_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_12_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_13_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_14_0, // @[Mesh.scala:22:14] input [2:0] io_in_id_15_0, // @[Mesh.scala:22:14] input io_in_last_0_0, // @[Mesh.scala:22:14] input io_in_last_1_0, // @[Mesh.scala:22:14] input io_in_last_2_0, // @[Mesh.scala:22:14] input io_in_last_3_0, // @[Mesh.scala:22:14] input io_in_last_4_0, // @[Mesh.scala:22:14] input io_in_last_5_0, // @[Mesh.scala:22:14] input io_in_last_6_0, // @[Mesh.scala:22:14] input io_in_last_7_0, // @[Mesh.scala:22:14] input io_in_last_8_0, // @[Mesh.scala:22:14] input io_in_last_9_0, // @[Mesh.scala:22:14] input io_in_last_10_0, // @[Mesh.scala:22:14] input io_in_last_11_0, // @[Mesh.scala:22:14] input io_in_last_12_0, // @[Mesh.scala:22:14] input io_in_last_13_0, // @[Mesh.scala:22:14] input io_in_last_14_0, // @[Mesh.scala:22:14] input io_in_last_15_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_0_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_1_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_2_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_3_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_4_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_5_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_6_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_7_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_8_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_9_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_10_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_11_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_12_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_13_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_14_0, // @[Mesh.scala:22:14] output [19:0] io_out_b_15_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_0_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_1_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_2_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_3_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_4_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_5_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_6_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_7_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_8_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_9_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_10_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_11_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_12_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_13_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_14_0, // @[Mesh.scala:22:14] output [19:0] io_out_c_15_0, // @[Mesh.scala:22:14] input io_in_valid_0_0, // @[Mesh.scala:22:14] input io_in_valid_1_0, // @[Mesh.scala:22:14] input io_in_valid_2_0, // @[Mesh.scala:22:14] input io_in_valid_3_0, // @[Mesh.scala:22:14] input io_in_valid_4_0, // @[Mesh.scala:22:14] input io_in_valid_5_0, // @[Mesh.scala:22:14] input io_in_valid_6_0, // @[Mesh.scala:22:14] input io_in_valid_7_0, // @[Mesh.scala:22:14] input io_in_valid_8_0, // @[Mesh.scala:22:14] input io_in_valid_9_0, // @[Mesh.scala:22:14] input io_in_valid_10_0, // @[Mesh.scala:22:14] input io_in_valid_11_0, // @[Mesh.scala:22:14] input io_in_valid_12_0, // @[Mesh.scala:22:14] input io_in_valid_13_0, // @[Mesh.scala:22:14] input io_in_valid_14_0, // @[Mesh.scala:22:14] input io_in_valid_15_0, // @[Mesh.scala:22:14] output io_out_valid_0_0, // @[Mesh.scala:22:14] output io_out_valid_1_0, // @[Mesh.scala:22:14] output io_out_valid_2_0, // @[Mesh.scala:22:14] output io_out_valid_3_0, // @[Mesh.scala:22:14] output io_out_valid_4_0, // @[Mesh.scala:22:14] output io_out_valid_5_0, // @[Mesh.scala:22:14] output io_out_valid_6_0, // @[Mesh.scala:22:14] output io_out_valid_7_0, // @[Mesh.scala:22:14] output io_out_valid_8_0, // @[Mesh.scala:22:14] output io_out_valid_9_0, // @[Mesh.scala:22:14] output io_out_valid_10_0, // @[Mesh.scala:22:14] output io_out_valid_11_0, // @[Mesh.scala:22:14] output io_out_valid_12_0, // @[Mesh.scala:22:14] output io_out_valid_13_0, // @[Mesh.scala:22:14] output io_out_valid_14_0, // @[Mesh.scala:22:14] output io_out_valid_15_0, // @[Mesh.scala:22:14] output io_out_control_0_0_dataflow, // @[Mesh.scala:22:14] output [2:0] io_out_id_0_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_1_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_2_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_3_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_4_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_5_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_6_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_7_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_8_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_9_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_10_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_11_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_12_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_13_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_14_0, // @[Mesh.scala:22:14] output [2:0] io_out_id_15_0, // @[Mesh.scala:22:14] output io_out_last_0_0, // @[Mesh.scala:22:14] output io_out_last_1_0, // @[Mesh.scala:22:14] output io_out_last_2_0, // @[Mesh.scala:22:14] output io_out_last_3_0, // @[Mesh.scala:22:14] output io_out_last_4_0, // @[Mesh.scala:22:14] output io_out_last_5_0, // @[Mesh.scala:22:14] output io_out_last_6_0, // @[Mesh.scala:22:14] output io_out_last_7_0, // @[Mesh.scala:22:14] output io_out_last_8_0, // @[Mesh.scala:22:14] output io_out_last_9_0, // @[Mesh.scala:22:14] output io_out_last_10_0, // @[Mesh.scala:22:14] output io_out_last_11_0, // @[Mesh.scala:22:14] output io_out_last_12_0, // @[Mesh.scala:22:14] output io_out_last_13_0, // @[Mesh.scala:22:14] output io_out_last_14_0, // @[Mesh.scala:22:14] output io_out_last_15_0 // @[Mesh.scala:22:14] ); wire [19:0] _mesh_15_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_15_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_15_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_15_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_15_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_15_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_14_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_14_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_14_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_14_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_14_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_13_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_13_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_13_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_13_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_13_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_12_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_12_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_12_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_12_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_12_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_11_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_11_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_11_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_11_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_11_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_10_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_10_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_10_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_10_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_10_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_9_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_9_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_9_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_9_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_9_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_8_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_8_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_8_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_8_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_8_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_7_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_7_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_7_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_7_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_7_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_6_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_6_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_6_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_6_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_6_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_5_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_5_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_5_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_5_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_5_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_4_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_4_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_4_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_4_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_4_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_3_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_3_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_3_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_3_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_3_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_2_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_2_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_2_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_2_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_2_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_1_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_1_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_1_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_1_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_1_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_15_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_15_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_15_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_15_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_15_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_14_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_14_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_14_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_14_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_14_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_14_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_13_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_13_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_13_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_13_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_13_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_13_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_12_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_12_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_12_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_12_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_12_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_12_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_11_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_11_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_11_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_11_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_11_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_11_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_10_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_10_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_10_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_10_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_10_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_10_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_9_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_9_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_9_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_9_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_9_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_9_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_8_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_8_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_8_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_8_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_8_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_8_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_7_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_7_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_7_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_7_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_7_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_7_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_6_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_6_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_6_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_6_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_6_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_6_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_5_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_5_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_5_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_5_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_5_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_5_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_4_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_4_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_4_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_4_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_4_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_4_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_3_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_3_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_3_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_3_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_3_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_3_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_2_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_2_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_2_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_2_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_2_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_2_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_1_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_1_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_1_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_1_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_1_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_1_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] _mesh_0_0_io_out_a_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_0_io_out_c_0; // @[Mesh.scala:39:71] wire [19:0] _mesh_0_0_io_out_b_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_control_0_dataflow; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_control_0_propagate; // @[Mesh.scala:39:71] wire [4:0] _mesh_0_0_io_out_control_0_shift; // @[Mesh.scala:39:71] wire [2:0] _mesh_0_0_io_out_id_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_last_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_out_valid_0; // @[Mesh.scala:39:71] wire _mesh_0_0_io_bad_dataflow; // @[Mesh.scala:39:71] wire [7:0] io_in_a_0_0_0 = io_in_a_0_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_1_0_0 = io_in_a_1_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_2_0_0 = io_in_a_2_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_3_0_0 = io_in_a_3_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_4_0_0 = io_in_a_4_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_5_0_0 = io_in_a_5_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_6_0_0 = io_in_a_6_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_7_0_0 = io_in_a_7_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_8_0_0 = io_in_a_8_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_9_0_0 = io_in_a_9_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_10_0_0 = io_in_a_10_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_11_0_0 = io_in_a_11_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_12_0_0 = io_in_a_12_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_13_0_0 = io_in_a_13_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_14_0_0 = io_in_a_14_0; // @[Mesh.scala:17:7] wire [7:0] io_in_a_15_0_0 = io_in_a_15_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_0_0_0 = io_in_b_0_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_1_0_0 = io_in_b_1_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_2_0_0 = io_in_b_2_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_3_0_0 = io_in_b_3_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_4_0_0 = io_in_b_4_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_5_0_0 = io_in_b_5_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_6_0_0 = io_in_b_6_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_7_0_0 = io_in_b_7_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_8_0_0 = io_in_b_8_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_9_0_0 = io_in_b_9_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_10_0_0 = io_in_b_10_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_11_0_0 = io_in_b_11_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_12_0_0 = io_in_b_12_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_13_0_0 = io_in_b_13_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_14_0_0 = io_in_b_14_0; // @[Mesh.scala:17:7] wire [7:0] io_in_b_15_0_0 = io_in_b_15_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_0_0_0 = io_in_d_0_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_1_0_0 = io_in_d_1_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_2_0_0 = io_in_d_2_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_3_0_0 = io_in_d_3_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_4_0_0 = io_in_d_4_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_5_0_0 = io_in_d_5_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_6_0_0 = io_in_d_6_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_7_0_0 = io_in_d_7_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_8_0_0 = io_in_d_8_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_9_0_0 = io_in_d_9_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_10_0_0 = io_in_d_10_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_11_0_0 = io_in_d_11_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_12_0_0 = io_in_d_12_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_13_0_0 = io_in_d_13_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_14_0_0 = io_in_d_14_0; // @[Mesh.scala:17:7] wire [7:0] io_in_d_15_0_0 = io_in_d_15_0; // @[Mesh.scala:17:7] wire io_in_control_0_0_dataflow_0 = io_in_control_0_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_0_0_propagate_0 = io_in_control_0_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_0_0_shift_0 = io_in_control_0_0_shift; // @[Mesh.scala:17:7] wire io_in_control_1_0_dataflow_0 = io_in_control_1_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_1_0_propagate_0 = io_in_control_1_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_1_0_shift_0 = io_in_control_1_0_shift; // @[Mesh.scala:17:7] wire io_in_control_2_0_dataflow_0 = io_in_control_2_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_2_0_propagate_0 = io_in_control_2_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_2_0_shift_0 = io_in_control_2_0_shift; // @[Mesh.scala:17:7] wire io_in_control_3_0_dataflow_0 = io_in_control_3_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_3_0_propagate_0 = io_in_control_3_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_3_0_shift_0 = io_in_control_3_0_shift; // @[Mesh.scala:17:7] wire io_in_control_4_0_dataflow_0 = io_in_control_4_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_4_0_propagate_0 = io_in_control_4_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_4_0_shift_0 = io_in_control_4_0_shift; // @[Mesh.scala:17:7] wire io_in_control_5_0_dataflow_0 = io_in_control_5_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_5_0_propagate_0 = io_in_control_5_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_5_0_shift_0 = io_in_control_5_0_shift; // @[Mesh.scala:17:7] wire io_in_control_6_0_dataflow_0 = io_in_control_6_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_6_0_propagate_0 = io_in_control_6_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_6_0_shift_0 = io_in_control_6_0_shift; // @[Mesh.scala:17:7] wire io_in_control_7_0_dataflow_0 = io_in_control_7_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_7_0_propagate_0 = io_in_control_7_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_7_0_shift_0 = io_in_control_7_0_shift; // @[Mesh.scala:17:7] wire io_in_control_8_0_dataflow_0 = io_in_control_8_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_8_0_propagate_0 = io_in_control_8_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_8_0_shift_0 = io_in_control_8_0_shift; // @[Mesh.scala:17:7] wire io_in_control_9_0_dataflow_0 = io_in_control_9_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_9_0_propagate_0 = io_in_control_9_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_9_0_shift_0 = io_in_control_9_0_shift; // @[Mesh.scala:17:7] wire io_in_control_10_0_dataflow_0 = io_in_control_10_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_10_0_propagate_0 = io_in_control_10_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_10_0_shift_0 = io_in_control_10_0_shift; // @[Mesh.scala:17:7] wire io_in_control_11_0_dataflow_0 = io_in_control_11_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_11_0_propagate_0 = io_in_control_11_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_11_0_shift_0 = io_in_control_11_0_shift; // @[Mesh.scala:17:7] wire io_in_control_12_0_dataflow_0 = io_in_control_12_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_12_0_propagate_0 = io_in_control_12_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_12_0_shift_0 = io_in_control_12_0_shift; // @[Mesh.scala:17:7] wire io_in_control_13_0_dataflow_0 = io_in_control_13_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_13_0_propagate_0 = io_in_control_13_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_13_0_shift_0 = io_in_control_13_0_shift; // @[Mesh.scala:17:7] wire io_in_control_14_0_dataflow_0 = io_in_control_14_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_14_0_propagate_0 = io_in_control_14_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_14_0_shift_0 = io_in_control_14_0_shift; // @[Mesh.scala:17:7] wire io_in_control_15_0_dataflow_0 = io_in_control_15_0_dataflow; // @[Mesh.scala:17:7] wire io_in_control_15_0_propagate_0 = io_in_control_15_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_in_control_15_0_shift_0 = io_in_control_15_0_shift; // @[Mesh.scala:17:7] wire [2:0] io_in_id_0_0_0 = io_in_id_0_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_1_0_0 = io_in_id_1_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_2_0_0 = io_in_id_2_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_3_0_0 = io_in_id_3_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_4_0_0 = io_in_id_4_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_5_0_0 = io_in_id_5_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_6_0_0 = io_in_id_6_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_7_0_0 = io_in_id_7_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_8_0_0 = io_in_id_8_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_9_0_0 = io_in_id_9_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_10_0_0 = io_in_id_10_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_11_0_0 = io_in_id_11_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_12_0_0 = io_in_id_12_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_13_0_0 = io_in_id_13_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_14_0_0 = io_in_id_14_0; // @[Mesh.scala:17:7] wire [2:0] io_in_id_15_0_0 = io_in_id_15_0; // @[Mesh.scala:17:7] wire io_in_last_0_0_0 = io_in_last_0_0; // @[Mesh.scala:17:7] wire io_in_last_1_0_0 = io_in_last_1_0; // @[Mesh.scala:17:7] wire io_in_last_2_0_0 = io_in_last_2_0; // @[Mesh.scala:17:7] wire io_in_last_3_0_0 = io_in_last_3_0; // @[Mesh.scala:17:7] wire io_in_last_4_0_0 = io_in_last_4_0; // @[Mesh.scala:17:7] wire io_in_last_5_0_0 = io_in_last_5_0; // @[Mesh.scala:17:7] wire io_in_last_6_0_0 = io_in_last_6_0; // @[Mesh.scala:17:7] wire io_in_last_7_0_0 = io_in_last_7_0; // @[Mesh.scala:17:7] wire io_in_last_8_0_0 = io_in_last_8_0; // @[Mesh.scala:17:7] wire io_in_last_9_0_0 = io_in_last_9_0; // @[Mesh.scala:17:7] wire io_in_last_10_0_0 = io_in_last_10_0; // @[Mesh.scala:17:7] wire io_in_last_11_0_0 = io_in_last_11_0; // @[Mesh.scala:17:7] wire io_in_last_12_0_0 = io_in_last_12_0; // @[Mesh.scala:17:7] wire io_in_last_13_0_0 = io_in_last_13_0; // @[Mesh.scala:17:7] wire io_in_last_14_0_0 = io_in_last_14_0; // @[Mesh.scala:17:7] wire io_in_last_15_0_0 = io_in_last_15_0; // @[Mesh.scala:17:7] wire io_in_valid_0_0_0 = io_in_valid_0_0; // @[Mesh.scala:17:7] wire io_in_valid_1_0_0 = io_in_valid_1_0; // @[Mesh.scala:17:7] wire io_in_valid_2_0_0 = io_in_valid_2_0; // @[Mesh.scala:17:7] wire io_in_valid_3_0_0 = io_in_valid_3_0; // @[Mesh.scala:17:7] wire io_in_valid_4_0_0 = io_in_valid_4_0; // @[Mesh.scala:17:7] wire io_in_valid_5_0_0 = io_in_valid_5_0; // @[Mesh.scala:17:7] wire io_in_valid_6_0_0 = io_in_valid_6_0; // @[Mesh.scala:17:7] wire io_in_valid_7_0_0 = io_in_valid_7_0; // @[Mesh.scala:17:7] wire io_in_valid_8_0_0 = io_in_valid_8_0; // @[Mesh.scala:17:7] wire io_in_valid_9_0_0 = io_in_valid_9_0; // @[Mesh.scala:17:7] wire io_in_valid_10_0_0 = io_in_valid_10_0; // @[Mesh.scala:17:7] wire io_in_valid_11_0_0 = io_in_valid_11_0; // @[Mesh.scala:17:7] wire io_in_valid_12_0_0 = io_in_valid_12_0; // @[Mesh.scala:17:7] wire io_in_valid_13_0_0 = io_in_valid_13_0; // @[Mesh.scala:17:7] wire io_in_valid_14_0_0 = io_in_valid_14_0; // @[Mesh.scala:17:7] wire io_in_valid_15_0_0 = io_in_valid_15_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_0_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_1_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_2_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_3_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_4_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_5_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_6_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_7_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_8_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_9_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_10_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_11_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_12_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_13_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_14_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_b_15_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_0_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_1_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_2_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_3_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_4_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_5_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_6_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_7_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_8_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_9_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_10_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_11_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_12_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_13_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_14_0_0; // @[Mesh.scala:17:7] wire [19:0] io_out_c_15_0_0; // @[Mesh.scala:17:7] wire io_out_valid_0_0_0; // @[Mesh.scala:17:7] wire io_out_valid_1_0_0; // @[Mesh.scala:17:7] wire io_out_valid_2_0_0; // @[Mesh.scala:17:7] wire io_out_valid_3_0_0; // @[Mesh.scala:17:7] wire io_out_valid_4_0_0; // @[Mesh.scala:17:7] wire io_out_valid_5_0_0; // @[Mesh.scala:17:7] wire io_out_valid_6_0_0; // @[Mesh.scala:17:7] wire io_out_valid_7_0_0; // @[Mesh.scala:17:7] wire io_out_valid_8_0_0; // @[Mesh.scala:17:7] wire io_out_valid_9_0_0; // @[Mesh.scala:17:7] wire io_out_valid_10_0_0; // @[Mesh.scala:17:7] wire io_out_valid_11_0_0; // @[Mesh.scala:17:7] wire io_out_valid_12_0_0; // @[Mesh.scala:17:7] wire io_out_valid_13_0_0; // @[Mesh.scala:17:7] wire io_out_valid_14_0_0; // @[Mesh.scala:17:7] wire io_out_valid_15_0_0; // @[Mesh.scala:17:7] wire io_out_control_0_0_dataflow_0; // @[Mesh.scala:17:7] wire io_out_control_0_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_0_0_shift; // @[Mesh.scala:17:7] wire io_out_control_1_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_1_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_1_0_shift; // @[Mesh.scala:17:7] wire io_out_control_2_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_2_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_2_0_shift; // @[Mesh.scala:17:7] wire io_out_control_3_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_3_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_3_0_shift; // @[Mesh.scala:17:7] wire io_out_control_4_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_4_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_4_0_shift; // @[Mesh.scala:17:7] wire io_out_control_5_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_5_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_5_0_shift; // @[Mesh.scala:17:7] wire io_out_control_6_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_6_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_6_0_shift; // @[Mesh.scala:17:7] wire io_out_control_7_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_7_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_7_0_shift; // @[Mesh.scala:17:7] wire io_out_control_8_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_8_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_8_0_shift; // @[Mesh.scala:17:7] wire io_out_control_9_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_9_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_9_0_shift; // @[Mesh.scala:17:7] wire io_out_control_10_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_10_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_10_0_shift; // @[Mesh.scala:17:7] wire io_out_control_11_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_11_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_11_0_shift; // @[Mesh.scala:17:7] wire io_out_control_12_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_12_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_12_0_shift; // @[Mesh.scala:17:7] wire io_out_control_13_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_13_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_13_0_shift; // @[Mesh.scala:17:7] wire io_out_control_14_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_14_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_14_0_shift; // @[Mesh.scala:17:7] wire io_out_control_15_0_dataflow; // @[Mesh.scala:17:7] wire io_out_control_15_0_propagate; // @[Mesh.scala:17:7] wire [4:0] io_out_control_15_0_shift; // @[Mesh.scala:17:7] wire [2:0] io_out_id_0_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_1_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_2_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_3_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_4_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_5_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_6_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_7_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_8_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_9_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_10_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_11_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_12_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_13_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_14_0_0; // @[Mesh.scala:17:7] wire [2:0] io_out_id_15_0_0; // @[Mesh.scala:17:7] wire io_out_last_0_0_0; // @[Mesh.scala:17:7] wire io_out_last_1_0_0; // @[Mesh.scala:17:7] wire io_out_last_2_0_0; // @[Mesh.scala:17:7] wire io_out_last_3_0_0; // @[Mesh.scala:17:7] wire io_out_last_4_0_0; // @[Mesh.scala:17:7] wire io_out_last_5_0_0; // @[Mesh.scala:17:7] wire io_out_last_6_0_0; // @[Mesh.scala:17:7] wire io_out_last_7_0_0; // @[Mesh.scala:17:7] wire io_out_last_8_0_0; // @[Mesh.scala:17:7] wire io_out_last_9_0_0; // @[Mesh.scala:17:7] wire io_out_last_10_0_0; // @[Mesh.scala:17:7] wire io_out_last_11_0_0; // @[Mesh.scala:17:7] wire io_out_last_12_0_0; // @[Mesh.scala:17:7] wire io_out_last_13_0_0; // @[Mesh.scala:17:7] wire io_out_last_14_0_0; // @[Mesh.scala:17:7] wire io_out_last_15_0_0; // @[Mesh.scala:17:7] reg [7:0] r_0; // @[Mesh.scala:53:38] reg [7:0] r_1_0; // @[Mesh.scala:53:38] reg [7:0] r_2_0; // @[Mesh.scala:53:38] reg [7:0] r_3_0; // @[Mesh.scala:53:38] reg [7:0] r_4_0; // @[Mesh.scala:53:38] reg [7:0] r_5_0; // @[Mesh.scala:53:38] reg [7:0] r_6_0; // @[Mesh.scala:53:38] reg [7:0] r_7_0; // @[Mesh.scala:53:38] reg [7:0] r_8_0; // @[Mesh.scala:53:38] reg [7:0] r_9_0; // @[Mesh.scala:53:38] reg [7:0] r_10_0; // @[Mesh.scala:53:38] reg [7:0] r_11_0; // @[Mesh.scala:53:38] reg [7:0] r_12_0; // @[Mesh.scala:53:38] reg [7:0] r_13_0; // @[Mesh.scala:53:38] reg [7:0] r_14_0; // @[Mesh.scala:53:38] reg [7:0] r_15_0; // @[Mesh.scala:53:38] reg [7:0] r_16_0; // @[Mesh.scala:53:38] reg [7:0] r_17_0; // @[Mesh.scala:53:38] reg [7:0] r_18_0; // @[Mesh.scala:53:38] reg [7:0] r_19_0; // @[Mesh.scala:53:38] reg [7:0] r_20_0; // @[Mesh.scala:53:38] reg [7:0] r_21_0; // @[Mesh.scala:53:38] reg [7:0] r_22_0; // @[Mesh.scala:53:38] reg [7:0] r_23_0; // @[Mesh.scala:53:38] reg [7:0] r_24_0; // @[Mesh.scala:53:38] reg [7:0] r_25_0; // @[Mesh.scala:53:38] reg [7:0] r_26_0; // @[Mesh.scala:53:38] reg [7:0] r_27_0; // @[Mesh.scala:53:38] reg [7:0] r_28_0; // @[Mesh.scala:53:38] reg [7:0] r_29_0; // @[Mesh.scala:53:38] reg [7:0] r_30_0; // @[Mesh.scala:53:38] reg [7:0] r_31_0; // @[Mesh.scala:53:38] reg [7:0] r_32_0; // @[Mesh.scala:53:38] reg [7:0] r_33_0; // @[Mesh.scala:53:38] reg [7:0] r_34_0; // @[Mesh.scala:53:38] reg [7:0] r_35_0; // @[Mesh.scala:53:38] reg [7:0] r_36_0; // @[Mesh.scala:53:38] reg [7:0] r_37_0; // @[Mesh.scala:53:38] reg [7:0] r_38_0; // @[Mesh.scala:53:38] reg [7:0] r_39_0; // @[Mesh.scala:53:38] reg [7:0] r_40_0; // @[Mesh.scala:53:38] reg [7:0] r_41_0; // @[Mesh.scala:53:38] reg [7:0] r_42_0; // @[Mesh.scala:53:38] reg [7:0] r_43_0; // @[Mesh.scala:53:38] reg [7:0] r_44_0; // @[Mesh.scala:53:38] reg [7:0] r_45_0; // @[Mesh.scala:53:38] reg [7:0] r_46_0; // @[Mesh.scala:53:38] reg [7:0] r_47_0; // @[Mesh.scala:53:38] reg [7:0] r_48_0; // @[Mesh.scala:53:38] reg [7:0] r_49_0; // @[Mesh.scala:53:38] reg [7:0] r_50_0; // @[Mesh.scala:53:38] reg [7:0] r_51_0; // @[Mesh.scala:53:38] reg [7:0] r_52_0; // @[Mesh.scala:53:38] reg [7:0] r_53_0; // @[Mesh.scala:53:38] reg [7:0] r_54_0; // @[Mesh.scala:53:38] reg [7:0] r_55_0; // @[Mesh.scala:53:38] reg [7:0] r_56_0; // @[Mesh.scala:53:38] reg [7:0] r_57_0; // @[Mesh.scala:53:38] reg [7:0] r_58_0; // @[Mesh.scala:53:38] reg [7:0] r_59_0; // @[Mesh.scala:53:38] reg [7:0] r_60_0; // @[Mesh.scala:53:38] reg [7:0] r_61_0; // @[Mesh.scala:53:38] reg [7:0] r_62_0; // @[Mesh.scala:53:38] reg [7:0] r_63_0; // @[Mesh.scala:53:38] reg [7:0] r_64_0; // @[Mesh.scala:53:38] reg [7:0] r_65_0; // @[Mesh.scala:53:38] reg [7:0] r_66_0; // @[Mesh.scala:53:38] reg [7:0] r_67_0; // @[Mesh.scala:53:38] reg [7:0] r_68_0; // @[Mesh.scala:53:38] reg [7:0] r_69_0; // @[Mesh.scala:53:38] reg [7:0] r_70_0; // @[Mesh.scala:53:38] reg [7:0] r_71_0; // @[Mesh.scala:53:38] reg [7:0] r_72_0; // @[Mesh.scala:53:38] reg [7:0] r_73_0; // @[Mesh.scala:53:38] reg [7:0] r_74_0; // @[Mesh.scala:53:38] reg [7:0] r_75_0; // @[Mesh.scala:53:38] reg [7:0] r_76_0; // @[Mesh.scala:53:38] reg [7:0] r_77_0; // @[Mesh.scala:53:38] reg [7:0] r_78_0; // @[Mesh.scala:53:38] reg [7:0] r_79_0; // @[Mesh.scala:53:38] reg [7:0] r_80_0; // @[Mesh.scala:53:38] reg [7:0] r_81_0; // @[Mesh.scala:53:38] reg [7:0] r_82_0; // @[Mesh.scala:53:38] reg [7:0] r_83_0; // @[Mesh.scala:53:38] reg [7:0] r_84_0; // @[Mesh.scala:53:38] reg [7:0] r_85_0; // @[Mesh.scala:53:38] reg [7:0] r_86_0; // @[Mesh.scala:53:38] reg [7:0] r_87_0; // @[Mesh.scala:53:38] reg [7:0] r_88_0; // @[Mesh.scala:53:38] reg [7:0] r_89_0; // @[Mesh.scala:53:38] reg [7:0] r_90_0; // @[Mesh.scala:53:38] reg [7:0] r_91_0; // @[Mesh.scala:53:38] reg [7:0] r_92_0; // @[Mesh.scala:53:38] reg [7:0] r_93_0; // @[Mesh.scala:53:38] reg [7:0] r_94_0; // @[Mesh.scala:53:38] reg [7:0] r_95_0; // @[Mesh.scala:53:38] reg [7:0] r_96_0; // @[Mesh.scala:53:38] reg [7:0] r_97_0; // @[Mesh.scala:53:38] reg [7:0] r_98_0; // @[Mesh.scala:53:38] reg [7:0] r_99_0; // @[Mesh.scala:53:38] reg [7:0] r_100_0; // @[Mesh.scala:53:38] reg [7:0] r_101_0; // @[Mesh.scala:53:38] reg [7:0] r_102_0; // @[Mesh.scala:53:38] reg [7:0] r_103_0; // @[Mesh.scala:53:38] reg [7:0] r_104_0; // @[Mesh.scala:53:38] reg [7:0] r_105_0; // @[Mesh.scala:53:38] reg [7:0] r_106_0; // @[Mesh.scala:53:38] reg [7:0] r_107_0; // @[Mesh.scala:53:38] reg [7:0] r_108_0; // @[Mesh.scala:53:38] reg [7:0] r_109_0; // @[Mesh.scala:53:38] reg [7:0] r_110_0; // @[Mesh.scala:53:38] reg [7:0] r_111_0; // @[Mesh.scala:53:38] reg [7:0] r_112_0; // @[Mesh.scala:53:38] reg [7:0] r_113_0; // @[Mesh.scala:53:38] reg [7:0] r_114_0; // @[Mesh.scala:53:38] reg [7:0] r_115_0; // @[Mesh.scala:53:38] reg [7:0] r_116_0; // @[Mesh.scala:53:38] reg [7:0] r_117_0; // @[Mesh.scala:53:38] reg [7:0] r_118_0; // @[Mesh.scala:53:38] reg [7:0] r_119_0; // @[Mesh.scala:53:38] reg [7:0] r_120_0; // @[Mesh.scala:53:38] reg [7:0] r_121_0; // @[Mesh.scala:53:38] reg [7:0] r_122_0; // @[Mesh.scala:53:38] reg [7:0] r_123_0; // @[Mesh.scala:53:38] reg [7:0] r_124_0; // @[Mesh.scala:53:38] reg [7:0] r_125_0; // @[Mesh.scala:53:38] reg [7:0] r_126_0; // @[Mesh.scala:53:38] reg [7:0] r_127_0; // @[Mesh.scala:53:38] reg [7:0] r_128_0; // @[Mesh.scala:53:38] reg [7:0] r_129_0; // @[Mesh.scala:53:38] reg [7:0] r_130_0; // @[Mesh.scala:53:38] reg [7:0] r_131_0; // @[Mesh.scala:53:38] reg [7:0] r_132_0; // @[Mesh.scala:53:38] reg [7:0] r_133_0; // @[Mesh.scala:53:38] reg [7:0] r_134_0; // @[Mesh.scala:53:38] reg [7:0] r_135_0; // @[Mesh.scala:53:38] reg [7:0] r_136_0; // @[Mesh.scala:53:38] reg [7:0] r_137_0; // @[Mesh.scala:53:38] reg [7:0] r_138_0; // @[Mesh.scala:53:38] reg [7:0] r_139_0; // @[Mesh.scala:53:38] reg [7:0] r_140_0; // @[Mesh.scala:53:38] reg [7:0] r_141_0; // @[Mesh.scala:53:38] reg [7:0] r_142_0; // @[Mesh.scala:53:38] reg [7:0] r_143_0; // @[Mesh.scala:53:38] reg [7:0] r_144_0; // @[Mesh.scala:53:38] reg [7:0] r_145_0; // @[Mesh.scala:53:38] reg [7:0] r_146_0; // @[Mesh.scala:53:38] reg [7:0] r_147_0; // @[Mesh.scala:53:38] reg [7:0] r_148_0; // @[Mesh.scala:53:38] reg [7:0] r_149_0; // @[Mesh.scala:53:38] reg [7:0] r_150_0; // @[Mesh.scala:53:38] reg [7:0] r_151_0; // @[Mesh.scala:53:38] reg [7:0] r_152_0; // @[Mesh.scala:53:38] reg [7:0] r_153_0; // @[Mesh.scala:53:38] reg [7:0] r_154_0; // @[Mesh.scala:53:38] reg [7:0] r_155_0; // @[Mesh.scala:53:38] reg [7:0] r_156_0; // @[Mesh.scala:53:38] reg [7:0] r_157_0; // @[Mesh.scala:53:38] reg [7:0] r_158_0; // @[Mesh.scala:53:38] reg [7:0] r_159_0; // @[Mesh.scala:53:38] reg [7:0] r_160_0; // @[Mesh.scala:53:38] reg [7:0] r_161_0; // @[Mesh.scala:53:38] reg [7:0] r_162_0; // @[Mesh.scala:53:38] reg [7:0] r_163_0; // @[Mesh.scala:53:38] reg [7:0] r_164_0; // @[Mesh.scala:53:38] reg [7:0] r_165_0; // @[Mesh.scala:53:38] reg [7:0] r_166_0; // @[Mesh.scala:53:38] reg [7:0] r_167_0; // @[Mesh.scala:53:38] reg [7:0] r_168_0; // @[Mesh.scala:53:38] reg [7:0] r_169_0; // @[Mesh.scala:53:38] reg [7:0] r_170_0; // @[Mesh.scala:53:38] reg [7:0] r_171_0; // @[Mesh.scala:53:38] reg [7:0] r_172_0; // @[Mesh.scala:53:38] reg [7:0] r_173_0; // @[Mesh.scala:53:38] reg [7:0] r_174_0; // @[Mesh.scala:53:38] reg [7:0] r_175_0; // @[Mesh.scala:53:38] reg [7:0] r_176_0; // @[Mesh.scala:53:38] reg [7:0] r_177_0; // @[Mesh.scala:53:38] reg [7:0] r_178_0; // @[Mesh.scala:53:38] reg [7:0] r_179_0; // @[Mesh.scala:53:38] reg [7:0] r_180_0; // @[Mesh.scala:53:38] reg [7:0] r_181_0; // @[Mesh.scala:53:38] reg [7:0] r_182_0; // @[Mesh.scala:53:38] reg [7:0] r_183_0; // @[Mesh.scala:53:38] reg [7:0] r_184_0; // @[Mesh.scala:53:38] reg [7:0] r_185_0; // @[Mesh.scala:53:38] reg [7:0] r_186_0; // @[Mesh.scala:53:38] reg [7:0] r_187_0; // @[Mesh.scala:53:38] reg [7:0] r_188_0; // @[Mesh.scala:53:38] reg [7:0] r_189_0; // @[Mesh.scala:53:38] reg [7:0] r_190_0; // @[Mesh.scala:53:38] reg [7:0] r_191_0; // @[Mesh.scala:53:38] reg [7:0] r_192_0; // @[Mesh.scala:53:38] reg [7:0] r_193_0; // @[Mesh.scala:53:38] reg [7:0] r_194_0; // @[Mesh.scala:53:38] reg [7:0] r_195_0; // @[Mesh.scala:53:38] reg [7:0] r_196_0; // @[Mesh.scala:53:38] reg [7:0] r_197_0; // @[Mesh.scala:53:38] reg [7:0] r_198_0; // @[Mesh.scala:53:38] reg [7:0] r_199_0; // @[Mesh.scala:53:38] reg [7:0] r_200_0; // @[Mesh.scala:53:38] reg [7:0] r_201_0; // @[Mesh.scala:53:38] reg [7:0] r_202_0; // @[Mesh.scala:53:38] reg [7:0] r_203_0; // @[Mesh.scala:53:38] reg [7:0] r_204_0; // @[Mesh.scala:53:38] reg [7:0] r_205_0; // @[Mesh.scala:53:38] reg [7:0] r_206_0; // @[Mesh.scala:53:38] reg [7:0] r_207_0; // @[Mesh.scala:53:38] reg [7:0] r_208_0; // @[Mesh.scala:53:38] reg [7:0] r_209_0; // @[Mesh.scala:53:38] reg [7:0] r_210_0; // @[Mesh.scala:53:38] reg [7:0] r_211_0; // @[Mesh.scala:53:38] reg [7:0] r_212_0; // @[Mesh.scala:53:38] reg [7:0] r_213_0; // @[Mesh.scala:53:38] reg [7:0] r_214_0; // @[Mesh.scala:53:38] reg [7:0] r_215_0; // @[Mesh.scala:53:38] reg [7:0] r_216_0; // @[Mesh.scala:53:38] reg [7:0] r_217_0; // @[Mesh.scala:53:38] reg [7:0] r_218_0; // @[Mesh.scala:53:38] reg [7:0] r_219_0; // @[Mesh.scala:53:38] reg [7:0] r_220_0; // @[Mesh.scala:53:38] reg [7:0] r_221_0; // @[Mesh.scala:53:38] reg [7:0] r_222_0; // @[Mesh.scala:53:38] reg [7:0] r_223_0; // @[Mesh.scala:53:38] reg [7:0] r_224_0; // @[Mesh.scala:53:38] reg [7:0] r_225_0; // @[Mesh.scala:53:38] reg [7:0] r_226_0; // @[Mesh.scala:53:38] reg [7:0] r_227_0; // @[Mesh.scala:53:38] reg [7:0] r_228_0; // @[Mesh.scala:53:38] reg [7:0] r_229_0; // @[Mesh.scala:53:38] reg [7:0] r_230_0; // @[Mesh.scala:53:38] reg [7:0] r_231_0; // @[Mesh.scala:53:38] reg [7:0] r_232_0; // @[Mesh.scala:53:38] reg [7:0] r_233_0; // @[Mesh.scala:53:38] reg [7:0] r_234_0; // @[Mesh.scala:53:38] reg [7:0] r_235_0; // @[Mesh.scala:53:38] reg [7:0] r_236_0; // @[Mesh.scala:53:38] reg [7:0] r_237_0; // @[Mesh.scala:53:38] reg [7:0] r_238_0; // @[Mesh.scala:53:38] reg [7:0] r_239_0; // @[Mesh.scala:53:38] reg [7:0] r_240_0; // @[Mesh.scala:53:38] reg [7:0] r_241_0; // @[Mesh.scala:53:38] reg [7:0] r_242_0; // @[Mesh.scala:53:38] reg [7:0] r_243_0; // @[Mesh.scala:53:38] reg [7:0] r_244_0; // @[Mesh.scala:53:38] reg [7:0] r_245_0; // @[Mesh.scala:53:38] reg [7:0] r_246_0; // @[Mesh.scala:53:38] reg [7:0] r_247_0; // @[Mesh.scala:53:38] reg [7:0] r_248_0; // @[Mesh.scala:53:38] reg [7:0] r_249_0; // @[Mesh.scala:53:38] reg [7:0] r_250_0; // @[Mesh.scala:53:38] reg [7:0] r_251_0; // @[Mesh.scala:53:38] reg [7:0] r_252_0; // @[Mesh.scala:53:38] reg [7:0] r_253_0; // @[Mesh.scala:53:38] reg [7:0] r_254_0; // @[Mesh.scala:53:38] reg [7:0] r_255_0; // @[Mesh.scala:53:38] reg pipe_v; // @[Valid.scala:141:24] wire pipe_out_valid = pipe_v; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_bits_0 = pipe_b_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_1; // @[Valid.scala:141:24] wire pipe_out_1_valid = pipe_v_1; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_1_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_1_bits_0 = pipe_b_1_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_2; // @[Valid.scala:141:24] wire pipe_out_2_valid = pipe_v_2; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_2_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_2_bits_0 = pipe_b_2_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_3; // @[Valid.scala:141:24] wire pipe_out_3_valid = pipe_v_3; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_3_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_3_bits_0 = pipe_b_3_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_4; // @[Valid.scala:141:24] wire pipe_out_4_valid = pipe_v_4; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_4_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_4_bits_0 = pipe_b_4_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_5; // @[Valid.scala:141:24] wire pipe_out_5_valid = pipe_v_5; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_5_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_5_bits_0 = pipe_b_5_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_6; // @[Valid.scala:141:24] wire pipe_out_6_valid = pipe_v_6; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_6_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_6_bits_0 = pipe_b_6_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_7; // @[Valid.scala:141:24] wire pipe_out_7_valid = pipe_v_7; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_7_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_7_bits_0 = pipe_b_7_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_8; // @[Valid.scala:141:24] wire pipe_out_8_valid = pipe_v_8; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_8_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_8_bits_0 = pipe_b_8_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_9; // @[Valid.scala:141:24] wire pipe_out_9_valid = pipe_v_9; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_9_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_9_bits_0 = pipe_b_9_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_10; // @[Valid.scala:141:24] wire pipe_out_10_valid = pipe_v_10; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_10_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_10_bits_0 = pipe_b_10_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_11; // @[Valid.scala:141:24] wire pipe_out_11_valid = pipe_v_11; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_11_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_11_bits_0 = pipe_b_11_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_12; // @[Valid.scala:141:24] wire pipe_out_12_valid = pipe_v_12; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_12_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_12_bits_0 = pipe_b_12_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_13; // @[Valid.scala:141:24] wire pipe_out_13_valid = pipe_v_13; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_13_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_13_bits_0 = pipe_b_13_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_14; // @[Valid.scala:141:24] wire pipe_out_14_valid = pipe_v_14; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_14_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_14_bits_0 = pipe_b_14_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_15; // @[Valid.scala:141:24] wire pipe_out_15_valid = pipe_v_15; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_15_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_15_bits_0 = pipe_b_15_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_16; // @[Valid.scala:141:24] wire pipe_out_16_valid = pipe_v_16; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_16_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_16_bits_0 = pipe_b_16_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_17; // @[Valid.scala:141:24] wire pipe_out_17_valid = pipe_v_17; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_17_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_17_bits_0 = pipe_b_17_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_18; // @[Valid.scala:141:24] wire pipe_out_18_valid = pipe_v_18; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_18_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_18_bits_0 = pipe_b_18_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_19; // @[Valid.scala:141:24] wire pipe_out_19_valid = pipe_v_19; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_19_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_19_bits_0 = pipe_b_19_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_20; // @[Valid.scala:141:24] wire pipe_out_20_valid = pipe_v_20; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_20_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_20_bits_0 = pipe_b_20_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_21; // @[Valid.scala:141:24] wire pipe_out_21_valid = pipe_v_21; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_21_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_21_bits_0 = pipe_b_21_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_22; // @[Valid.scala:141:24] wire pipe_out_22_valid = pipe_v_22; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_22_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_22_bits_0 = pipe_b_22_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_23; // @[Valid.scala:141:24] wire pipe_out_23_valid = pipe_v_23; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_23_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_23_bits_0 = pipe_b_23_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_24; // @[Valid.scala:141:24] wire pipe_out_24_valid = pipe_v_24; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_24_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_24_bits_0 = pipe_b_24_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_25; // @[Valid.scala:141:24] wire pipe_out_25_valid = pipe_v_25; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_25_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_25_bits_0 = pipe_b_25_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_26; // @[Valid.scala:141:24] wire pipe_out_26_valid = pipe_v_26; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_26_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_26_bits_0 = pipe_b_26_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_27; // @[Valid.scala:141:24] wire pipe_out_27_valid = pipe_v_27; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_27_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_27_bits_0 = pipe_b_27_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_28; // @[Valid.scala:141:24] wire pipe_out_28_valid = pipe_v_28; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_28_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_28_bits_0 = pipe_b_28_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_29; // @[Valid.scala:141:24] wire pipe_out_29_valid = pipe_v_29; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_29_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_29_bits_0 = pipe_b_29_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_30; // @[Valid.scala:141:24] wire pipe_out_30_valid = pipe_v_30; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_30_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_30_bits_0 = pipe_b_30_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_31; // @[Valid.scala:141:24] wire pipe_out_31_valid = pipe_v_31; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_31_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_31_bits_0 = pipe_b_31_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_32; // @[Valid.scala:141:24] wire pipe_out_32_valid = pipe_v_32; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_32_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_32_bits_0 = pipe_b_32_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_33; // @[Valid.scala:141:24] wire pipe_out_33_valid = pipe_v_33; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_33_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_33_bits_0 = pipe_b_33_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_34; // @[Valid.scala:141:24] wire pipe_out_34_valid = pipe_v_34; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_34_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_34_bits_0 = pipe_b_34_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_35; // @[Valid.scala:141:24] wire pipe_out_35_valid = pipe_v_35; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_35_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_35_bits_0 = pipe_b_35_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_36; // @[Valid.scala:141:24] wire pipe_out_36_valid = pipe_v_36; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_36_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_36_bits_0 = pipe_b_36_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_37; // @[Valid.scala:141:24] wire pipe_out_37_valid = pipe_v_37; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_37_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_37_bits_0 = pipe_b_37_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_38; // @[Valid.scala:141:24] wire pipe_out_38_valid = pipe_v_38; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_38_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_38_bits_0 = pipe_b_38_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_39; // @[Valid.scala:141:24] wire pipe_out_39_valid = pipe_v_39; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_39_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_39_bits_0 = pipe_b_39_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_40; // @[Valid.scala:141:24] wire pipe_out_40_valid = pipe_v_40; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_40_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_40_bits_0 = pipe_b_40_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_41; // @[Valid.scala:141:24] wire pipe_out_41_valid = pipe_v_41; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_41_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_41_bits_0 = pipe_b_41_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_42; // @[Valid.scala:141:24] wire pipe_out_42_valid = pipe_v_42; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_42_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_42_bits_0 = pipe_b_42_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_43; // @[Valid.scala:141:24] wire pipe_out_43_valid = pipe_v_43; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_43_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_43_bits_0 = pipe_b_43_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_44; // @[Valid.scala:141:24] wire pipe_out_44_valid = pipe_v_44; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_44_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_44_bits_0 = pipe_b_44_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_45; // @[Valid.scala:141:24] wire pipe_out_45_valid = pipe_v_45; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_45_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_45_bits_0 = pipe_b_45_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_46; // @[Valid.scala:141:24] wire pipe_out_46_valid = pipe_v_46; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_46_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_46_bits_0 = pipe_b_46_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_47; // @[Valid.scala:141:24] wire pipe_out_47_valid = pipe_v_47; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_47_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_47_bits_0 = pipe_b_47_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_48; // @[Valid.scala:141:24] wire pipe_out_48_valid = pipe_v_48; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_48_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_48_bits_0 = pipe_b_48_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_49; // @[Valid.scala:141:24] wire pipe_out_49_valid = pipe_v_49; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_49_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_49_bits_0 = pipe_b_49_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_50; // @[Valid.scala:141:24] wire pipe_out_50_valid = pipe_v_50; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_50_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_50_bits_0 = pipe_b_50_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_51; // @[Valid.scala:141:24] wire pipe_out_51_valid = pipe_v_51; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_51_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_51_bits_0 = pipe_b_51_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_52; // @[Valid.scala:141:24] wire pipe_out_52_valid = pipe_v_52; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_52_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_52_bits_0 = pipe_b_52_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_53; // @[Valid.scala:141:24] wire pipe_out_53_valid = pipe_v_53; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_53_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_53_bits_0 = pipe_b_53_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_54; // @[Valid.scala:141:24] wire pipe_out_54_valid = pipe_v_54; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_54_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_54_bits_0 = pipe_b_54_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_55; // @[Valid.scala:141:24] wire pipe_out_55_valid = pipe_v_55; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_55_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_55_bits_0 = pipe_b_55_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_56; // @[Valid.scala:141:24] wire pipe_out_56_valid = pipe_v_56; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_56_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_56_bits_0 = pipe_b_56_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_57; // @[Valid.scala:141:24] wire pipe_out_57_valid = pipe_v_57; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_57_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_57_bits_0 = pipe_b_57_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_58; // @[Valid.scala:141:24] wire pipe_out_58_valid = pipe_v_58; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_58_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_58_bits_0 = pipe_b_58_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_59; // @[Valid.scala:141:24] wire pipe_out_59_valid = pipe_v_59; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_59_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_59_bits_0 = pipe_b_59_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_60; // @[Valid.scala:141:24] wire pipe_out_60_valid = pipe_v_60; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_60_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_60_bits_0 = pipe_b_60_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_61; // @[Valid.scala:141:24] wire pipe_out_61_valid = pipe_v_61; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_61_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_61_bits_0 = pipe_b_61_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_62; // @[Valid.scala:141:24] wire pipe_out_62_valid = pipe_v_62; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_62_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_62_bits_0 = pipe_b_62_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_63; // @[Valid.scala:141:24] wire pipe_out_63_valid = pipe_v_63; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_63_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_63_bits_0 = pipe_b_63_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_64; // @[Valid.scala:141:24] wire pipe_out_64_valid = pipe_v_64; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_64_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_64_bits_0 = pipe_b_64_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_65; // @[Valid.scala:141:24] wire pipe_out_65_valid = pipe_v_65; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_65_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_65_bits_0 = pipe_b_65_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_66; // @[Valid.scala:141:24] wire pipe_out_66_valid = pipe_v_66; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_66_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_66_bits_0 = pipe_b_66_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_67; // @[Valid.scala:141:24] wire pipe_out_67_valid = pipe_v_67; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_67_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_67_bits_0 = pipe_b_67_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_68; // @[Valid.scala:141:24] wire pipe_out_68_valid = pipe_v_68; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_68_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_68_bits_0 = pipe_b_68_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_69; // @[Valid.scala:141:24] wire pipe_out_69_valid = pipe_v_69; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_69_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_69_bits_0 = pipe_b_69_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_70; // @[Valid.scala:141:24] wire pipe_out_70_valid = pipe_v_70; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_70_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_70_bits_0 = pipe_b_70_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_71; // @[Valid.scala:141:24] wire pipe_out_71_valid = pipe_v_71; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_71_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_71_bits_0 = pipe_b_71_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_72; // @[Valid.scala:141:24] wire pipe_out_72_valid = pipe_v_72; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_72_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_72_bits_0 = pipe_b_72_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_73; // @[Valid.scala:141:24] wire pipe_out_73_valid = pipe_v_73; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_73_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_73_bits_0 = pipe_b_73_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_74; // @[Valid.scala:141:24] wire pipe_out_74_valid = pipe_v_74; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_74_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_74_bits_0 = pipe_b_74_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_75; // @[Valid.scala:141:24] wire pipe_out_75_valid = pipe_v_75; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_75_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_75_bits_0 = pipe_b_75_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_76; // @[Valid.scala:141:24] wire pipe_out_76_valid = pipe_v_76; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_76_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_76_bits_0 = pipe_b_76_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_77; // @[Valid.scala:141:24] wire pipe_out_77_valid = pipe_v_77; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_77_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_77_bits_0 = pipe_b_77_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_78; // @[Valid.scala:141:24] wire pipe_out_78_valid = pipe_v_78; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_78_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_78_bits_0 = pipe_b_78_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_79; // @[Valid.scala:141:24] wire pipe_out_79_valid = pipe_v_79; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_79_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_79_bits_0 = pipe_b_79_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_80; // @[Valid.scala:141:24] wire pipe_out_80_valid = pipe_v_80; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_80_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_80_bits_0 = pipe_b_80_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_81; // @[Valid.scala:141:24] wire pipe_out_81_valid = pipe_v_81; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_81_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_81_bits_0 = pipe_b_81_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_82; // @[Valid.scala:141:24] wire pipe_out_82_valid = pipe_v_82; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_82_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_82_bits_0 = pipe_b_82_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_83; // @[Valid.scala:141:24] wire pipe_out_83_valid = pipe_v_83; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_83_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_83_bits_0 = pipe_b_83_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_84; // @[Valid.scala:141:24] wire pipe_out_84_valid = pipe_v_84; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_84_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_84_bits_0 = pipe_b_84_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_85; // @[Valid.scala:141:24] wire pipe_out_85_valid = pipe_v_85; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_85_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_85_bits_0 = pipe_b_85_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_86; // @[Valid.scala:141:24] wire pipe_out_86_valid = pipe_v_86; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_86_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_86_bits_0 = pipe_b_86_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_87; // @[Valid.scala:141:24] wire pipe_out_87_valid = pipe_v_87; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_87_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_87_bits_0 = pipe_b_87_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_88; // @[Valid.scala:141:24] wire pipe_out_88_valid = pipe_v_88; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_88_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_88_bits_0 = pipe_b_88_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_89; // @[Valid.scala:141:24] wire pipe_out_89_valid = pipe_v_89; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_89_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_89_bits_0 = pipe_b_89_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_90; // @[Valid.scala:141:24] wire pipe_out_90_valid = pipe_v_90; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_90_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_90_bits_0 = pipe_b_90_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_91; // @[Valid.scala:141:24] wire pipe_out_91_valid = pipe_v_91; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_91_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_91_bits_0 = pipe_b_91_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_92; // @[Valid.scala:141:24] wire pipe_out_92_valid = pipe_v_92; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_92_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_92_bits_0 = pipe_b_92_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_93; // @[Valid.scala:141:24] wire pipe_out_93_valid = pipe_v_93; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_93_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_93_bits_0 = pipe_b_93_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_94; // @[Valid.scala:141:24] wire pipe_out_94_valid = pipe_v_94; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_94_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_94_bits_0 = pipe_b_94_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_95; // @[Valid.scala:141:24] wire pipe_out_95_valid = pipe_v_95; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_95_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_95_bits_0 = pipe_b_95_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_96; // @[Valid.scala:141:24] wire pipe_out_96_valid = pipe_v_96; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_96_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_96_bits_0 = pipe_b_96_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_97; // @[Valid.scala:141:24] wire pipe_out_97_valid = pipe_v_97; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_97_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_97_bits_0 = pipe_b_97_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_98; // @[Valid.scala:141:24] wire pipe_out_98_valid = pipe_v_98; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_98_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_98_bits_0 = pipe_b_98_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_99; // @[Valid.scala:141:24] wire pipe_out_99_valid = pipe_v_99; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_99_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_99_bits_0 = pipe_b_99_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_100; // @[Valid.scala:141:24] wire pipe_out_100_valid = pipe_v_100; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_100_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_100_bits_0 = pipe_b_100_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_101; // @[Valid.scala:141:24] wire pipe_out_101_valid = pipe_v_101; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_101_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_101_bits_0 = pipe_b_101_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_102; // @[Valid.scala:141:24] wire pipe_out_102_valid = pipe_v_102; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_102_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_102_bits_0 = pipe_b_102_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_103; // @[Valid.scala:141:24] wire pipe_out_103_valid = pipe_v_103; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_103_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_103_bits_0 = pipe_b_103_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_104; // @[Valid.scala:141:24] wire pipe_out_104_valid = pipe_v_104; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_104_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_104_bits_0 = pipe_b_104_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_105; // @[Valid.scala:141:24] wire pipe_out_105_valid = pipe_v_105; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_105_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_105_bits_0 = pipe_b_105_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_106; // @[Valid.scala:141:24] wire pipe_out_106_valid = pipe_v_106; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_106_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_106_bits_0 = pipe_b_106_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_107; // @[Valid.scala:141:24] wire pipe_out_107_valid = pipe_v_107; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_107_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_107_bits_0 = pipe_b_107_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_108; // @[Valid.scala:141:24] wire pipe_out_108_valid = pipe_v_108; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_108_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_108_bits_0 = pipe_b_108_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_109; // @[Valid.scala:141:24] wire pipe_out_109_valid = pipe_v_109; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_109_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_109_bits_0 = pipe_b_109_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_110; // @[Valid.scala:141:24] wire pipe_out_110_valid = pipe_v_110; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_110_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_110_bits_0 = pipe_b_110_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_111; // @[Valid.scala:141:24] wire pipe_out_111_valid = pipe_v_111; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_111_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_111_bits_0 = pipe_b_111_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_112; // @[Valid.scala:141:24] wire pipe_out_112_valid = pipe_v_112; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_112_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_112_bits_0 = pipe_b_112_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_113; // @[Valid.scala:141:24] wire pipe_out_113_valid = pipe_v_113; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_113_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_113_bits_0 = pipe_b_113_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_114; // @[Valid.scala:141:24] wire pipe_out_114_valid = pipe_v_114; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_114_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_114_bits_0 = pipe_b_114_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_115; // @[Valid.scala:141:24] wire pipe_out_115_valid = pipe_v_115; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_115_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_115_bits_0 = pipe_b_115_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_116; // @[Valid.scala:141:24] wire pipe_out_116_valid = pipe_v_116; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_116_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_116_bits_0 = pipe_b_116_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_117; // @[Valid.scala:141:24] wire pipe_out_117_valid = pipe_v_117; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_117_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_117_bits_0 = pipe_b_117_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_118; // @[Valid.scala:141:24] wire pipe_out_118_valid = pipe_v_118; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_118_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_118_bits_0 = pipe_b_118_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_119; // @[Valid.scala:141:24] wire pipe_out_119_valid = pipe_v_119; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_119_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_119_bits_0 = pipe_b_119_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_120; // @[Valid.scala:141:24] wire pipe_out_120_valid = pipe_v_120; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_120_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_120_bits_0 = pipe_b_120_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_121; // @[Valid.scala:141:24] wire pipe_out_121_valid = pipe_v_121; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_121_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_121_bits_0 = pipe_b_121_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_122; // @[Valid.scala:141:24] wire pipe_out_122_valid = pipe_v_122; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_122_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_122_bits_0 = pipe_b_122_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_123; // @[Valid.scala:141:24] wire pipe_out_123_valid = pipe_v_123; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_123_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_123_bits_0 = pipe_b_123_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_124; // @[Valid.scala:141:24] wire pipe_out_124_valid = pipe_v_124; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_124_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_124_bits_0 = pipe_b_124_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_125; // @[Valid.scala:141:24] wire pipe_out_125_valid = pipe_v_125; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_125_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_125_bits_0 = pipe_b_125_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_126; // @[Valid.scala:141:24] wire pipe_out_126_valid = pipe_v_126; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_126_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_126_bits_0 = pipe_b_126_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_127; // @[Valid.scala:141:24] wire pipe_out_127_valid = pipe_v_127; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_127_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_127_bits_0 = pipe_b_127_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_128; // @[Valid.scala:141:24] wire pipe_out_128_valid = pipe_v_128; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_128_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_128_bits_0 = pipe_b_128_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_129; // @[Valid.scala:141:24] wire pipe_out_129_valid = pipe_v_129; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_129_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_129_bits_0 = pipe_b_129_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_130; // @[Valid.scala:141:24] wire pipe_out_130_valid = pipe_v_130; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_130_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_130_bits_0 = pipe_b_130_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_131; // @[Valid.scala:141:24] wire pipe_out_131_valid = pipe_v_131; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_131_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_131_bits_0 = pipe_b_131_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_132; // @[Valid.scala:141:24] wire pipe_out_132_valid = pipe_v_132; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_132_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_132_bits_0 = pipe_b_132_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_133; // @[Valid.scala:141:24] wire pipe_out_133_valid = pipe_v_133; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_133_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_133_bits_0 = pipe_b_133_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_134; // @[Valid.scala:141:24] wire pipe_out_134_valid = pipe_v_134; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_134_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_134_bits_0 = pipe_b_134_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_135; // @[Valid.scala:141:24] wire pipe_out_135_valid = pipe_v_135; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_135_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_135_bits_0 = pipe_b_135_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_136; // @[Valid.scala:141:24] wire pipe_out_136_valid = pipe_v_136; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_136_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_136_bits_0 = pipe_b_136_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_137; // @[Valid.scala:141:24] wire pipe_out_137_valid = pipe_v_137; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_137_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_137_bits_0 = pipe_b_137_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_138; // @[Valid.scala:141:24] wire pipe_out_138_valid = pipe_v_138; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_138_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_138_bits_0 = pipe_b_138_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_139; // @[Valid.scala:141:24] wire pipe_out_139_valid = pipe_v_139; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_139_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_139_bits_0 = pipe_b_139_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_140; // @[Valid.scala:141:24] wire pipe_out_140_valid = pipe_v_140; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_140_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_140_bits_0 = pipe_b_140_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_141; // @[Valid.scala:141:24] wire pipe_out_141_valid = pipe_v_141; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_141_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_141_bits_0 = pipe_b_141_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_142; // @[Valid.scala:141:24] wire pipe_out_142_valid = pipe_v_142; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_142_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_142_bits_0 = pipe_b_142_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_143; // @[Valid.scala:141:24] wire pipe_out_143_valid = pipe_v_143; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_143_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_143_bits_0 = pipe_b_143_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_144; // @[Valid.scala:141:24] wire pipe_out_144_valid = pipe_v_144; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_144_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_144_bits_0 = pipe_b_144_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_145; // @[Valid.scala:141:24] wire pipe_out_145_valid = pipe_v_145; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_145_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_145_bits_0 = pipe_b_145_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_146; // @[Valid.scala:141:24] wire pipe_out_146_valid = pipe_v_146; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_146_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_146_bits_0 = pipe_b_146_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_147; // @[Valid.scala:141:24] wire pipe_out_147_valid = pipe_v_147; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_147_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_147_bits_0 = pipe_b_147_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_148; // @[Valid.scala:141:24] wire pipe_out_148_valid = pipe_v_148; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_148_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_148_bits_0 = pipe_b_148_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_149; // @[Valid.scala:141:24] wire pipe_out_149_valid = pipe_v_149; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_149_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_149_bits_0 = pipe_b_149_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_150; // @[Valid.scala:141:24] wire pipe_out_150_valid = pipe_v_150; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_150_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_150_bits_0 = pipe_b_150_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_151; // @[Valid.scala:141:24] wire pipe_out_151_valid = pipe_v_151; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_151_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_151_bits_0 = pipe_b_151_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_152; // @[Valid.scala:141:24] wire pipe_out_152_valid = pipe_v_152; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_152_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_152_bits_0 = pipe_b_152_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_153; // @[Valid.scala:141:24] wire pipe_out_153_valid = pipe_v_153; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_153_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_153_bits_0 = pipe_b_153_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_154; // @[Valid.scala:141:24] wire pipe_out_154_valid = pipe_v_154; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_154_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_154_bits_0 = pipe_b_154_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_155; // @[Valid.scala:141:24] wire pipe_out_155_valid = pipe_v_155; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_155_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_155_bits_0 = pipe_b_155_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_156; // @[Valid.scala:141:24] wire pipe_out_156_valid = pipe_v_156; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_156_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_156_bits_0 = pipe_b_156_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_157; // @[Valid.scala:141:24] wire pipe_out_157_valid = pipe_v_157; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_157_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_157_bits_0 = pipe_b_157_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_158; // @[Valid.scala:141:24] wire pipe_out_158_valid = pipe_v_158; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_158_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_158_bits_0 = pipe_b_158_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_159; // @[Valid.scala:141:24] wire pipe_out_159_valid = pipe_v_159; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_159_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_159_bits_0 = pipe_b_159_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_160; // @[Valid.scala:141:24] wire pipe_out_160_valid = pipe_v_160; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_160_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_160_bits_0 = pipe_b_160_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_161; // @[Valid.scala:141:24] wire pipe_out_161_valid = pipe_v_161; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_161_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_161_bits_0 = pipe_b_161_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_162; // @[Valid.scala:141:24] wire pipe_out_162_valid = pipe_v_162; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_162_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_162_bits_0 = pipe_b_162_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_163; // @[Valid.scala:141:24] wire pipe_out_163_valid = pipe_v_163; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_163_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_163_bits_0 = pipe_b_163_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_164; // @[Valid.scala:141:24] wire pipe_out_164_valid = pipe_v_164; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_164_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_164_bits_0 = pipe_b_164_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_165; // @[Valid.scala:141:24] wire pipe_out_165_valid = pipe_v_165; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_165_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_165_bits_0 = pipe_b_165_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_166; // @[Valid.scala:141:24] wire pipe_out_166_valid = pipe_v_166; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_166_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_166_bits_0 = pipe_b_166_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_167; // @[Valid.scala:141:24] wire pipe_out_167_valid = pipe_v_167; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_167_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_167_bits_0 = pipe_b_167_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_168; // @[Valid.scala:141:24] wire pipe_out_168_valid = pipe_v_168; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_168_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_168_bits_0 = pipe_b_168_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_169; // @[Valid.scala:141:24] wire pipe_out_169_valid = pipe_v_169; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_169_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_169_bits_0 = pipe_b_169_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_170; // @[Valid.scala:141:24] wire pipe_out_170_valid = pipe_v_170; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_170_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_170_bits_0 = pipe_b_170_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_171; // @[Valid.scala:141:24] wire pipe_out_171_valid = pipe_v_171; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_171_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_171_bits_0 = pipe_b_171_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_172; // @[Valid.scala:141:24] wire pipe_out_172_valid = pipe_v_172; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_172_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_172_bits_0 = pipe_b_172_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_173; // @[Valid.scala:141:24] wire pipe_out_173_valid = pipe_v_173; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_173_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_173_bits_0 = pipe_b_173_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_174; // @[Valid.scala:141:24] wire pipe_out_174_valid = pipe_v_174; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_174_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_174_bits_0 = pipe_b_174_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_175; // @[Valid.scala:141:24] wire pipe_out_175_valid = pipe_v_175; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_175_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_175_bits_0 = pipe_b_175_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_176; // @[Valid.scala:141:24] wire pipe_out_176_valid = pipe_v_176; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_176_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_176_bits_0 = pipe_b_176_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_177; // @[Valid.scala:141:24] wire pipe_out_177_valid = pipe_v_177; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_177_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_177_bits_0 = pipe_b_177_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_178; // @[Valid.scala:141:24] wire pipe_out_178_valid = pipe_v_178; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_178_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_178_bits_0 = pipe_b_178_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_179; // @[Valid.scala:141:24] wire pipe_out_179_valid = pipe_v_179; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_179_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_179_bits_0 = pipe_b_179_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_180; // @[Valid.scala:141:24] wire pipe_out_180_valid = pipe_v_180; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_180_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_180_bits_0 = pipe_b_180_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_181; // @[Valid.scala:141:24] wire pipe_out_181_valid = pipe_v_181; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_181_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_181_bits_0 = pipe_b_181_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_182; // @[Valid.scala:141:24] wire pipe_out_182_valid = pipe_v_182; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_182_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_182_bits_0 = pipe_b_182_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_183; // @[Valid.scala:141:24] wire pipe_out_183_valid = pipe_v_183; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_183_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_183_bits_0 = pipe_b_183_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_184; // @[Valid.scala:141:24] wire pipe_out_184_valid = pipe_v_184; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_184_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_184_bits_0 = pipe_b_184_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_185; // @[Valid.scala:141:24] wire pipe_out_185_valid = pipe_v_185; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_185_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_185_bits_0 = pipe_b_185_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_186; // @[Valid.scala:141:24] wire pipe_out_186_valid = pipe_v_186; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_186_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_186_bits_0 = pipe_b_186_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_187; // @[Valid.scala:141:24] wire pipe_out_187_valid = pipe_v_187; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_187_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_187_bits_0 = pipe_b_187_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_188; // @[Valid.scala:141:24] wire pipe_out_188_valid = pipe_v_188; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_188_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_188_bits_0 = pipe_b_188_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_189; // @[Valid.scala:141:24] wire pipe_out_189_valid = pipe_v_189; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_189_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_189_bits_0 = pipe_b_189_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_190; // @[Valid.scala:141:24] wire pipe_out_190_valid = pipe_v_190; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_190_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_190_bits_0 = pipe_b_190_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_191; // @[Valid.scala:141:24] wire pipe_out_191_valid = pipe_v_191; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_191_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_191_bits_0 = pipe_b_191_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_192; // @[Valid.scala:141:24] wire pipe_out_192_valid = pipe_v_192; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_192_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_192_bits_0 = pipe_b_192_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_193; // @[Valid.scala:141:24] wire pipe_out_193_valid = pipe_v_193; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_193_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_193_bits_0 = pipe_b_193_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_194; // @[Valid.scala:141:24] wire pipe_out_194_valid = pipe_v_194; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_194_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_194_bits_0 = pipe_b_194_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_195; // @[Valid.scala:141:24] wire pipe_out_195_valid = pipe_v_195; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_195_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_195_bits_0 = pipe_b_195_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_196; // @[Valid.scala:141:24] wire pipe_out_196_valid = pipe_v_196; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_196_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_196_bits_0 = pipe_b_196_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_197; // @[Valid.scala:141:24] wire pipe_out_197_valid = pipe_v_197; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_197_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_197_bits_0 = pipe_b_197_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_198; // @[Valid.scala:141:24] wire pipe_out_198_valid = pipe_v_198; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_198_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_198_bits_0 = pipe_b_198_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_199; // @[Valid.scala:141:24] wire pipe_out_199_valid = pipe_v_199; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_199_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_199_bits_0 = pipe_b_199_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_200; // @[Valid.scala:141:24] wire pipe_out_200_valid = pipe_v_200; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_200_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_200_bits_0 = pipe_b_200_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_201; // @[Valid.scala:141:24] wire pipe_out_201_valid = pipe_v_201; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_201_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_201_bits_0 = pipe_b_201_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_202; // @[Valid.scala:141:24] wire pipe_out_202_valid = pipe_v_202; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_202_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_202_bits_0 = pipe_b_202_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_203; // @[Valid.scala:141:24] wire pipe_out_203_valid = pipe_v_203; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_203_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_203_bits_0 = pipe_b_203_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_204; // @[Valid.scala:141:24] wire pipe_out_204_valid = pipe_v_204; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_204_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_204_bits_0 = pipe_b_204_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_205; // @[Valid.scala:141:24] wire pipe_out_205_valid = pipe_v_205; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_205_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_205_bits_0 = pipe_b_205_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_206; // @[Valid.scala:141:24] wire pipe_out_206_valid = pipe_v_206; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_206_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_206_bits_0 = pipe_b_206_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_207; // @[Valid.scala:141:24] wire pipe_out_207_valid = pipe_v_207; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_207_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_207_bits_0 = pipe_b_207_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_208; // @[Valid.scala:141:24] wire pipe_out_208_valid = pipe_v_208; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_208_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_208_bits_0 = pipe_b_208_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_209; // @[Valid.scala:141:24] wire pipe_out_209_valid = pipe_v_209; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_209_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_209_bits_0 = pipe_b_209_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_210; // @[Valid.scala:141:24] wire pipe_out_210_valid = pipe_v_210; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_210_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_210_bits_0 = pipe_b_210_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_211; // @[Valid.scala:141:24] wire pipe_out_211_valid = pipe_v_211; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_211_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_211_bits_0 = pipe_b_211_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_212; // @[Valid.scala:141:24] wire pipe_out_212_valid = pipe_v_212; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_212_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_212_bits_0 = pipe_b_212_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_213; // @[Valid.scala:141:24] wire pipe_out_213_valid = pipe_v_213; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_213_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_213_bits_0 = pipe_b_213_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_214; // @[Valid.scala:141:24] wire pipe_out_214_valid = pipe_v_214; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_214_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_214_bits_0 = pipe_b_214_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_215; // @[Valid.scala:141:24] wire pipe_out_215_valid = pipe_v_215; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_215_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_215_bits_0 = pipe_b_215_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_216; // @[Valid.scala:141:24] wire pipe_out_216_valid = pipe_v_216; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_216_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_216_bits_0 = pipe_b_216_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_217; // @[Valid.scala:141:24] wire pipe_out_217_valid = pipe_v_217; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_217_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_217_bits_0 = pipe_b_217_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_218; // @[Valid.scala:141:24] wire pipe_out_218_valid = pipe_v_218; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_218_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_218_bits_0 = pipe_b_218_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_219; // @[Valid.scala:141:24] wire pipe_out_219_valid = pipe_v_219; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_219_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_219_bits_0 = pipe_b_219_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_220; // @[Valid.scala:141:24] wire pipe_out_220_valid = pipe_v_220; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_220_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_220_bits_0 = pipe_b_220_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_221; // @[Valid.scala:141:24] wire pipe_out_221_valid = pipe_v_221; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_221_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_221_bits_0 = pipe_b_221_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_222; // @[Valid.scala:141:24] wire pipe_out_222_valid = pipe_v_222; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_222_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_222_bits_0 = pipe_b_222_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_223; // @[Valid.scala:141:24] wire pipe_out_223_valid = pipe_v_223; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_223_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_223_bits_0 = pipe_b_223_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_224; // @[Valid.scala:141:24] wire pipe_out_224_valid = pipe_v_224; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_224_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_224_bits_0 = pipe_b_224_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_225; // @[Valid.scala:141:24] wire pipe_out_225_valid = pipe_v_225; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_225_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_225_bits_0 = pipe_b_225_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_226; // @[Valid.scala:141:24] wire pipe_out_226_valid = pipe_v_226; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_226_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_226_bits_0 = pipe_b_226_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_227; // @[Valid.scala:141:24] wire pipe_out_227_valid = pipe_v_227; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_227_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_227_bits_0 = pipe_b_227_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_228; // @[Valid.scala:141:24] wire pipe_out_228_valid = pipe_v_228; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_228_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_228_bits_0 = pipe_b_228_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_229; // @[Valid.scala:141:24] wire pipe_out_229_valid = pipe_v_229; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_229_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_229_bits_0 = pipe_b_229_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_230; // @[Valid.scala:141:24] wire pipe_out_230_valid = pipe_v_230; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_230_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_230_bits_0 = pipe_b_230_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_231; // @[Valid.scala:141:24] wire pipe_out_231_valid = pipe_v_231; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_231_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_231_bits_0 = pipe_b_231_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_232; // @[Valid.scala:141:24] wire pipe_out_232_valid = pipe_v_232; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_232_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_232_bits_0 = pipe_b_232_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_233; // @[Valid.scala:141:24] wire pipe_out_233_valid = pipe_v_233; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_233_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_233_bits_0 = pipe_b_233_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_234; // @[Valid.scala:141:24] wire pipe_out_234_valid = pipe_v_234; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_234_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_234_bits_0 = pipe_b_234_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_235; // @[Valid.scala:141:24] wire pipe_out_235_valid = pipe_v_235; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_235_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_235_bits_0 = pipe_b_235_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_236; // @[Valid.scala:141:24] wire pipe_out_236_valid = pipe_v_236; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_236_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_236_bits_0 = pipe_b_236_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_237; // @[Valid.scala:141:24] wire pipe_out_237_valid = pipe_v_237; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_237_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_237_bits_0 = pipe_b_237_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_238; // @[Valid.scala:141:24] wire pipe_out_238_valid = pipe_v_238; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_238_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_238_bits_0 = pipe_b_238_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_239; // @[Valid.scala:141:24] wire pipe_out_239_valid = pipe_v_239; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_239_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_239_bits_0 = pipe_b_239_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_240; // @[Valid.scala:141:24] wire pipe_out_240_valid = pipe_v_240; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_240_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_240_bits_0 = pipe_b_240_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_241; // @[Valid.scala:141:24] wire pipe_out_241_valid = pipe_v_241; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_241_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_241_bits_0 = pipe_b_241_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_242; // @[Valid.scala:141:24] wire pipe_out_242_valid = pipe_v_242; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_242_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_242_bits_0 = pipe_b_242_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_243; // @[Valid.scala:141:24] wire pipe_out_243_valid = pipe_v_243; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_243_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_243_bits_0 = pipe_b_243_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_244; // @[Valid.scala:141:24] wire pipe_out_244_valid = pipe_v_244; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_244_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_244_bits_0 = pipe_b_244_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_245; // @[Valid.scala:141:24] wire pipe_out_245_valid = pipe_v_245; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_245_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_245_bits_0 = pipe_b_245_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_246; // @[Valid.scala:141:24] wire pipe_out_246_valid = pipe_v_246; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_246_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_246_bits_0 = pipe_b_246_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_247; // @[Valid.scala:141:24] wire pipe_out_247_valid = pipe_v_247; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_247_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_247_bits_0 = pipe_b_247_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_248; // @[Valid.scala:141:24] wire pipe_out_248_valid = pipe_v_248; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_248_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_248_bits_0 = pipe_b_248_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_249; // @[Valid.scala:141:24] wire pipe_out_249_valid = pipe_v_249; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_249_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_249_bits_0 = pipe_b_249_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_250; // @[Valid.scala:141:24] wire pipe_out_250_valid = pipe_v_250; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_250_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_250_bits_0 = pipe_b_250_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_251; // @[Valid.scala:141:24] wire pipe_out_251_valid = pipe_v_251; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_251_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_251_bits_0 = pipe_b_251_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_252; // @[Valid.scala:141:24] wire pipe_out_252_valid = pipe_v_252; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_252_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_252_bits_0 = pipe_b_252_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_253; // @[Valid.scala:141:24] wire pipe_out_253_valid = pipe_v_253; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_253_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_253_bits_0 = pipe_b_253_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_254; // @[Valid.scala:141:24] wire pipe_out_254_valid = pipe_v_254; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_254_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_254_bits_0 = pipe_b_254_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_255; // @[Valid.scala:141:24] wire pipe_out_255_valid = pipe_v_255; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_255_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_255_bits_0 = pipe_b_255_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_256; // @[Valid.scala:141:24] wire pipe_out_256_valid = pipe_v_256; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_256_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_256_bits_0 = pipe_b_256_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_257; // @[Valid.scala:141:24] wire pipe_out_257_valid = pipe_v_257; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_257_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_257_bits_0 = pipe_b_257_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_258; // @[Valid.scala:141:24] wire pipe_out_258_valid = pipe_v_258; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_258_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_258_bits_0 = pipe_b_258_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_259; // @[Valid.scala:141:24] wire pipe_out_259_valid = pipe_v_259; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_259_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_259_bits_0 = pipe_b_259_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_260; // @[Valid.scala:141:24] wire pipe_out_260_valid = pipe_v_260; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_260_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_260_bits_0 = pipe_b_260_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_261; // @[Valid.scala:141:24] wire pipe_out_261_valid = pipe_v_261; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_261_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_261_bits_0 = pipe_b_261_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_262; // @[Valid.scala:141:24] wire pipe_out_262_valid = pipe_v_262; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_262_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_262_bits_0 = pipe_b_262_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_263; // @[Valid.scala:141:24] wire pipe_out_263_valid = pipe_v_263; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_263_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_263_bits_0 = pipe_b_263_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_264; // @[Valid.scala:141:24] wire pipe_out_264_valid = pipe_v_264; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_264_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_264_bits_0 = pipe_b_264_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_265; // @[Valid.scala:141:24] wire pipe_out_265_valid = pipe_v_265; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_265_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_265_bits_0 = pipe_b_265_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_266; // @[Valid.scala:141:24] wire pipe_out_266_valid = pipe_v_266; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_266_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_266_bits_0 = pipe_b_266_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_267; // @[Valid.scala:141:24] wire pipe_out_267_valid = pipe_v_267; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_267_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_267_bits_0 = pipe_b_267_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_268; // @[Valid.scala:141:24] wire pipe_out_268_valid = pipe_v_268; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_268_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_268_bits_0 = pipe_b_268_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_269; // @[Valid.scala:141:24] wire pipe_out_269_valid = pipe_v_269; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_269_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_269_bits_0 = pipe_b_269_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_270; // @[Valid.scala:141:24] wire pipe_out_270_valid = pipe_v_270; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_270_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_270_bits_0 = pipe_b_270_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_271; // @[Valid.scala:141:24] wire pipe_out_271_valid = pipe_v_271; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_271_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_271_bits_0 = pipe_b_271_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_272; // @[Valid.scala:141:24] wire pipe_out_272_valid = pipe_v_272; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_272_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_272_bits_0 = pipe_b_272_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_273; // @[Valid.scala:141:24] wire pipe_out_273_valid = pipe_v_273; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_273_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_273_bits_0 = pipe_b_273_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_274; // @[Valid.scala:141:24] wire pipe_out_274_valid = pipe_v_274; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_274_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_274_bits_0 = pipe_b_274_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_275; // @[Valid.scala:141:24] wire pipe_out_275_valid = pipe_v_275; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_275_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_275_bits_0 = pipe_b_275_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_276; // @[Valid.scala:141:24] wire pipe_out_276_valid = pipe_v_276; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_276_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_276_bits_0 = pipe_b_276_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_277; // @[Valid.scala:141:24] wire pipe_out_277_valid = pipe_v_277; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_277_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_277_bits_0 = pipe_b_277_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_278; // @[Valid.scala:141:24] wire pipe_out_278_valid = pipe_v_278; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_278_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_278_bits_0 = pipe_b_278_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_279; // @[Valid.scala:141:24] wire pipe_out_279_valid = pipe_v_279; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_279_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_279_bits_0 = pipe_b_279_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_280; // @[Valid.scala:141:24] wire pipe_out_280_valid = pipe_v_280; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_280_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_280_bits_0 = pipe_b_280_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_281; // @[Valid.scala:141:24] wire pipe_out_281_valid = pipe_v_281; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_281_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_281_bits_0 = pipe_b_281_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_282; // @[Valid.scala:141:24] wire pipe_out_282_valid = pipe_v_282; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_282_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_282_bits_0 = pipe_b_282_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_283; // @[Valid.scala:141:24] wire pipe_out_283_valid = pipe_v_283; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_283_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_283_bits_0 = pipe_b_283_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_284; // @[Valid.scala:141:24] wire pipe_out_284_valid = pipe_v_284; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_284_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_284_bits_0 = pipe_b_284_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_285; // @[Valid.scala:141:24] wire pipe_out_285_valid = pipe_v_285; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_285_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_285_bits_0 = pipe_b_285_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_286; // @[Valid.scala:141:24] wire pipe_out_286_valid = pipe_v_286; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_286_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_286_bits_0 = pipe_b_286_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_287; // @[Valid.scala:141:24] wire pipe_out_287_valid = pipe_v_287; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_287_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_287_bits_0 = pipe_b_287_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_288; // @[Valid.scala:141:24] wire pipe_out_288_valid = pipe_v_288; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_288_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_288_bits_0 = pipe_b_288_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_289; // @[Valid.scala:141:24] wire pipe_out_289_valid = pipe_v_289; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_289_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_289_bits_0 = pipe_b_289_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_290; // @[Valid.scala:141:24] wire pipe_out_290_valid = pipe_v_290; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_290_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_290_bits_0 = pipe_b_290_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_291; // @[Valid.scala:141:24] wire pipe_out_291_valid = pipe_v_291; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_291_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_291_bits_0 = pipe_b_291_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_292; // @[Valid.scala:141:24] wire pipe_out_292_valid = pipe_v_292; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_292_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_292_bits_0 = pipe_b_292_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_293; // @[Valid.scala:141:24] wire pipe_out_293_valid = pipe_v_293; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_293_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_293_bits_0 = pipe_b_293_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_294; // @[Valid.scala:141:24] wire pipe_out_294_valid = pipe_v_294; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_294_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_294_bits_0 = pipe_b_294_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_295; // @[Valid.scala:141:24] wire pipe_out_295_valid = pipe_v_295; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_295_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_295_bits_0 = pipe_b_295_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_296; // @[Valid.scala:141:24] wire pipe_out_296_valid = pipe_v_296; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_296_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_296_bits_0 = pipe_b_296_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_297; // @[Valid.scala:141:24] wire pipe_out_297_valid = pipe_v_297; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_297_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_297_bits_0 = pipe_b_297_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_298; // @[Valid.scala:141:24] wire pipe_out_298_valid = pipe_v_298; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_298_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_298_bits_0 = pipe_b_298_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_299; // @[Valid.scala:141:24] wire pipe_out_299_valid = pipe_v_299; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_299_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_299_bits_0 = pipe_b_299_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_300; // @[Valid.scala:141:24] wire pipe_out_300_valid = pipe_v_300; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_300_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_300_bits_0 = pipe_b_300_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_301; // @[Valid.scala:141:24] wire pipe_out_301_valid = pipe_v_301; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_301_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_301_bits_0 = pipe_b_301_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_302; // @[Valid.scala:141:24] wire pipe_out_302_valid = pipe_v_302; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_302_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_302_bits_0 = pipe_b_302_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_303; // @[Valid.scala:141:24] wire pipe_out_303_valid = pipe_v_303; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_303_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_303_bits_0 = pipe_b_303_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_304; // @[Valid.scala:141:24] wire pipe_out_304_valid = pipe_v_304; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_304_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_304_bits_0 = pipe_b_304_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_305; // @[Valid.scala:141:24] wire pipe_out_305_valid = pipe_v_305; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_305_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_305_bits_0 = pipe_b_305_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_306; // @[Valid.scala:141:24] wire pipe_out_306_valid = pipe_v_306; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_306_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_306_bits_0 = pipe_b_306_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_307; // @[Valid.scala:141:24] wire pipe_out_307_valid = pipe_v_307; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_307_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_307_bits_0 = pipe_b_307_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_308; // @[Valid.scala:141:24] wire pipe_out_308_valid = pipe_v_308; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_308_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_308_bits_0 = pipe_b_308_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_309; // @[Valid.scala:141:24] wire pipe_out_309_valid = pipe_v_309; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_309_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_309_bits_0 = pipe_b_309_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_310; // @[Valid.scala:141:24] wire pipe_out_310_valid = pipe_v_310; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_310_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_310_bits_0 = pipe_b_310_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_311; // @[Valid.scala:141:24] wire pipe_out_311_valid = pipe_v_311; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_311_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_311_bits_0 = pipe_b_311_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_312; // @[Valid.scala:141:24] wire pipe_out_312_valid = pipe_v_312; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_312_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_312_bits_0 = pipe_b_312_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_313; // @[Valid.scala:141:24] wire pipe_out_313_valid = pipe_v_313; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_313_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_313_bits_0 = pipe_b_313_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_314; // @[Valid.scala:141:24] wire pipe_out_314_valid = pipe_v_314; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_314_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_314_bits_0 = pipe_b_314_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_315; // @[Valid.scala:141:24] wire pipe_out_315_valid = pipe_v_315; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_315_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_315_bits_0 = pipe_b_315_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_316; // @[Valid.scala:141:24] wire pipe_out_316_valid = pipe_v_316; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_316_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_316_bits_0 = pipe_b_316_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_317; // @[Valid.scala:141:24] wire pipe_out_317_valid = pipe_v_317; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_317_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_317_bits_0 = pipe_b_317_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_318; // @[Valid.scala:141:24] wire pipe_out_318_valid = pipe_v_318; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_318_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_318_bits_0 = pipe_b_318_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_319; // @[Valid.scala:141:24] wire pipe_out_319_valid = pipe_v_319; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_319_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_319_bits_0 = pipe_b_319_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_320; // @[Valid.scala:141:24] wire pipe_out_320_valid = pipe_v_320; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_320_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_320_bits_0 = pipe_b_320_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_321; // @[Valid.scala:141:24] wire pipe_out_321_valid = pipe_v_321; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_321_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_321_bits_0 = pipe_b_321_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_322; // @[Valid.scala:141:24] wire pipe_out_322_valid = pipe_v_322; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_322_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_322_bits_0 = pipe_b_322_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_323; // @[Valid.scala:141:24] wire pipe_out_323_valid = pipe_v_323; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_323_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_323_bits_0 = pipe_b_323_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_324; // @[Valid.scala:141:24] wire pipe_out_324_valid = pipe_v_324; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_324_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_324_bits_0 = pipe_b_324_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_325; // @[Valid.scala:141:24] wire pipe_out_325_valid = pipe_v_325; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_325_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_325_bits_0 = pipe_b_325_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_326; // @[Valid.scala:141:24] wire pipe_out_326_valid = pipe_v_326; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_326_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_326_bits_0 = pipe_b_326_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_327; // @[Valid.scala:141:24] wire pipe_out_327_valid = pipe_v_327; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_327_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_327_bits_0 = pipe_b_327_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_328; // @[Valid.scala:141:24] wire pipe_out_328_valid = pipe_v_328; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_328_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_328_bits_0 = pipe_b_328_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_329; // @[Valid.scala:141:24] wire pipe_out_329_valid = pipe_v_329; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_329_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_329_bits_0 = pipe_b_329_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_330; // @[Valid.scala:141:24] wire pipe_out_330_valid = pipe_v_330; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_330_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_330_bits_0 = pipe_b_330_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_331; // @[Valid.scala:141:24] wire pipe_out_331_valid = pipe_v_331; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_331_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_331_bits_0 = pipe_b_331_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_332; // @[Valid.scala:141:24] wire pipe_out_332_valid = pipe_v_332; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_332_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_332_bits_0 = pipe_b_332_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_333; // @[Valid.scala:141:24] wire pipe_out_333_valid = pipe_v_333; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_333_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_333_bits_0 = pipe_b_333_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_334; // @[Valid.scala:141:24] wire pipe_out_334_valid = pipe_v_334; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_334_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_334_bits_0 = pipe_b_334_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_335; // @[Valid.scala:141:24] wire pipe_out_335_valid = pipe_v_335; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_335_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_335_bits_0 = pipe_b_335_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_336; // @[Valid.scala:141:24] wire pipe_out_336_valid = pipe_v_336; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_336_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_336_bits_0 = pipe_b_336_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_337; // @[Valid.scala:141:24] wire pipe_out_337_valid = pipe_v_337; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_337_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_337_bits_0 = pipe_b_337_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_338; // @[Valid.scala:141:24] wire pipe_out_338_valid = pipe_v_338; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_338_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_338_bits_0 = pipe_b_338_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_339; // @[Valid.scala:141:24] wire pipe_out_339_valid = pipe_v_339; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_339_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_339_bits_0 = pipe_b_339_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_340; // @[Valid.scala:141:24] wire pipe_out_340_valid = pipe_v_340; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_340_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_340_bits_0 = pipe_b_340_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_341; // @[Valid.scala:141:24] wire pipe_out_341_valid = pipe_v_341; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_341_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_341_bits_0 = pipe_b_341_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_342; // @[Valid.scala:141:24] wire pipe_out_342_valid = pipe_v_342; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_342_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_342_bits_0 = pipe_b_342_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_343; // @[Valid.scala:141:24] wire pipe_out_343_valid = pipe_v_343; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_343_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_343_bits_0 = pipe_b_343_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_344; // @[Valid.scala:141:24] wire pipe_out_344_valid = pipe_v_344; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_344_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_344_bits_0 = pipe_b_344_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_345; // @[Valid.scala:141:24] wire pipe_out_345_valid = pipe_v_345; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_345_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_345_bits_0 = pipe_b_345_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_346; // @[Valid.scala:141:24] wire pipe_out_346_valid = pipe_v_346; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_346_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_346_bits_0 = pipe_b_346_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_347; // @[Valid.scala:141:24] wire pipe_out_347_valid = pipe_v_347; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_347_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_347_bits_0 = pipe_b_347_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_348; // @[Valid.scala:141:24] wire pipe_out_348_valid = pipe_v_348; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_348_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_348_bits_0 = pipe_b_348_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_349; // @[Valid.scala:141:24] wire pipe_out_349_valid = pipe_v_349; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_349_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_349_bits_0 = pipe_b_349_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_350; // @[Valid.scala:141:24] wire pipe_out_350_valid = pipe_v_350; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_350_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_350_bits_0 = pipe_b_350_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_351; // @[Valid.scala:141:24] wire pipe_out_351_valid = pipe_v_351; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_351_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_351_bits_0 = pipe_b_351_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_352; // @[Valid.scala:141:24] wire pipe_out_352_valid = pipe_v_352; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_352_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_352_bits_0 = pipe_b_352_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_353; // @[Valid.scala:141:24] wire pipe_out_353_valid = pipe_v_353; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_353_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_353_bits_0 = pipe_b_353_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_354; // @[Valid.scala:141:24] wire pipe_out_354_valid = pipe_v_354; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_354_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_354_bits_0 = pipe_b_354_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_355; // @[Valid.scala:141:24] wire pipe_out_355_valid = pipe_v_355; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_355_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_355_bits_0 = pipe_b_355_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_356; // @[Valid.scala:141:24] wire pipe_out_356_valid = pipe_v_356; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_356_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_356_bits_0 = pipe_b_356_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_357; // @[Valid.scala:141:24] wire pipe_out_357_valid = pipe_v_357; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_357_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_357_bits_0 = pipe_b_357_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_358; // @[Valid.scala:141:24] wire pipe_out_358_valid = pipe_v_358; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_358_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_358_bits_0 = pipe_b_358_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_359; // @[Valid.scala:141:24] wire pipe_out_359_valid = pipe_v_359; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_359_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_359_bits_0 = pipe_b_359_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_360; // @[Valid.scala:141:24] wire pipe_out_360_valid = pipe_v_360; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_360_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_360_bits_0 = pipe_b_360_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_361; // @[Valid.scala:141:24] wire pipe_out_361_valid = pipe_v_361; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_361_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_361_bits_0 = pipe_b_361_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_362; // @[Valid.scala:141:24] wire pipe_out_362_valid = pipe_v_362; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_362_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_362_bits_0 = pipe_b_362_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_363; // @[Valid.scala:141:24] wire pipe_out_363_valid = pipe_v_363; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_363_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_363_bits_0 = pipe_b_363_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_364; // @[Valid.scala:141:24] wire pipe_out_364_valid = pipe_v_364; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_364_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_364_bits_0 = pipe_b_364_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_365; // @[Valid.scala:141:24] wire pipe_out_365_valid = pipe_v_365; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_365_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_365_bits_0 = pipe_b_365_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_366; // @[Valid.scala:141:24] wire pipe_out_366_valid = pipe_v_366; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_366_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_366_bits_0 = pipe_b_366_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_367; // @[Valid.scala:141:24] wire pipe_out_367_valid = pipe_v_367; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_367_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_367_bits_0 = pipe_b_367_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_368; // @[Valid.scala:141:24] wire pipe_out_368_valid = pipe_v_368; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_368_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_368_bits_0 = pipe_b_368_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_369; // @[Valid.scala:141:24] wire pipe_out_369_valid = pipe_v_369; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_369_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_369_bits_0 = pipe_b_369_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_370; // @[Valid.scala:141:24] wire pipe_out_370_valid = pipe_v_370; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_370_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_370_bits_0 = pipe_b_370_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_371; // @[Valid.scala:141:24] wire pipe_out_371_valid = pipe_v_371; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_371_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_371_bits_0 = pipe_b_371_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_372; // @[Valid.scala:141:24] wire pipe_out_372_valid = pipe_v_372; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_372_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_372_bits_0 = pipe_b_372_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_373; // @[Valid.scala:141:24] wire pipe_out_373_valid = pipe_v_373; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_373_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_373_bits_0 = pipe_b_373_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_374; // @[Valid.scala:141:24] wire pipe_out_374_valid = pipe_v_374; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_374_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_374_bits_0 = pipe_b_374_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_375; // @[Valid.scala:141:24] wire pipe_out_375_valid = pipe_v_375; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_375_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_375_bits_0 = pipe_b_375_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_376; // @[Valid.scala:141:24] wire pipe_out_376_valid = pipe_v_376; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_376_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_376_bits_0 = pipe_b_376_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_377; // @[Valid.scala:141:24] wire pipe_out_377_valid = pipe_v_377; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_377_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_377_bits_0 = pipe_b_377_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_378; // @[Valid.scala:141:24] wire pipe_out_378_valid = pipe_v_378; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_378_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_378_bits_0 = pipe_b_378_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_379; // @[Valid.scala:141:24] wire pipe_out_379_valid = pipe_v_379; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_379_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_379_bits_0 = pipe_b_379_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_380; // @[Valid.scala:141:24] wire pipe_out_380_valid = pipe_v_380; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_380_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_380_bits_0 = pipe_b_380_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_381; // @[Valid.scala:141:24] wire pipe_out_381_valid = pipe_v_381; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_381_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_381_bits_0 = pipe_b_381_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_382; // @[Valid.scala:141:24] wire pipe_out_382_valid = pipe_v_382; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_382_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_382_bits_0 = pipe_b_382_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_383; // @[Valid.scala:141:24] wire pipe_out_383_valid = pipe_v_383; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_383_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_383_bits_0 = pipe_b_383_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_384; // @[Valid.scala:141:24] wire pipe_out_384_valid = pipe_v_384; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_384_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_384_bits_0 = pipe_b_384_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_385; // @[Valid.scala:141:24] wire pipe_out_385_valid = pipe_v_385; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_385_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_385_bits_0 = pipe_b_385_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_386; // @[Valid.scala:141:24] wire pipe_out_386_valid = pipe_v_386; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_386_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_386_bits_0 = pipe_b_386_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_387; // @[Valid.scala:141:24] wire pipe_out_387_valid = pipe_v_387; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_387_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_387_bits_0 = pipe_b_387_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_388; // @[Valid.scala:141:24] wire pipe_out_388_valid = pipe_v_388; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_388_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_388_bits_0 = pipe_b_388_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_389; // @[Valid.scala:141:24] wire pipe_out_389_valid = pipe_v_389; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_389_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_389_bits_0 = pipe_b_389_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_390; // @[Valid.scala:141:24] wire pipe_out_390_valid = pipe_v_390; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_390_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_390_bits_0 = pipe_b_390_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_391; // @[Valid.scala:141:24] wire pipe_out_391_valid = pipe_v_391; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_391_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_391_bits_0 = pipe_b_391_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_392; // @[Valid.scala:141:24] wire pipe_out_392_valid = pipe_v_392; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_392_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_392_bits_0 = pipe_b_392_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_393; // @[Valid.scala:141:24] wire pipe_out_393_valid = pipe_v_393; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_393_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_393_bits_0 = pipe_b_393_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_394; // @[Valid.scala:141:24] wire pipe_out_394_valid = pipe_v_394; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_394_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_394_bits_0 = pipe_b_394_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_395; // @[Valid.scala:141:24] wire pipe_out_395_valid = pipe_v_395; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_395_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_395_bits_0 = pipe_b_395_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_396; // @[Valid.scala:141:24] wire pipe_out_396_valid = pipe_v_396; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_396_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_396_bits_0 = pipe_b_396_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_397; // @[Valid.scala:141:24] wire pipe_out_397_valid = pipe_v_397; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_397_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_397_bits_0 = pipe_b_397_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_398; // @[Valid.scala:141:24] wire pipe_out_398_valid = pipe_v_398; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_398_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_398_bits_0 = pipe_b_398_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_399; // @[Valid.scala:141:24] wire pipe_out_399_valid = pipe_v_399; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_399_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_399_bits_0 = pipe_b_399_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_400; // @[Valid.scala:141:24] wire pipe_out_400_valid = pipe_v_400; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_400_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_400_bits_0 = pipe_b_400_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_401; // @[Valid.scala:141:24] wire pipe_out_401_valid = pipe_v_401; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_401_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_401_bits_0 = pipe_b_401_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_402; // @[Valid.scala:141:24] wire pipe_out_402_valid = pipe_v_402; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_402_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_402_bits_0 = pipe_b_402_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_403; // @[Valid.scala:141:24] wire pipe_out_403_valid = pipe_v_403; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_403_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_403_bits_0 = pipe_b_403_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_404; // @[Valid.scala:141:24] wire pipe_out_404_valid = pipe_v_404; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_404_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_404_bits_0 = pipe_b_404_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_405; // @[Valid.scala:141:24] wire pipe_out_405_valid = pipe_v_405; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_405_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_405_bits_0 = pipe_b_405_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_406; // @[Valid.scala:141:24] wire pipe_out_406_valid = pipe_v_406; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_406_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_406_bits_0 = pipe_b_406_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_407; // @[Valid.scala:141:24] wire pipe_out_407_valid = pipe_v_407; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_407_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_407_bits_0 = pipe_b_407_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_408; // @[Valid.scala:141:24] wire pipe_out_408_valid = pipe_v_408; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_408_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_408_bits_0 = pipe_b_408_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_409; // @[Valid.scala:141:24] wire pipe_out_409_valid = pipe_v_409; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_409_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_409_bits_0 = pipe_b_409_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_410; // @[Valid.scala:141:24] wire pipe_out_410_valid = pipe_v_410; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_410_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_410_bits_0 = pipe_b_410_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_411; // @[Valid.scala:141:24] wire pipe_out_411_valid = pipe_v_411; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_411_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_411_bits_0 = pipe_b_411_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_412; // @[Valid.scala:141:24] wire pipe_out_412_valid = pipe_v_412; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_412_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_412_bits_0 = pipe_b_412_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_413; // @[Valid.scala:141:24] wire pipe_out_413_valid = pipe_v_413; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_413_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_413_bits_0 = pipe_b_413_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_414; // @[Valid.scala:141:24] wire pipe_out_414_valid = pipe_v_414; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_414_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_414_bits_0 = pipe_b_414_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_415; // @[Valid.scala:141:24] wire pipe_out_415_valid = pipe_v_415; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_415_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_415_bits_0 = pipe_b_415_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_416; // @[Valid.scala:141:24] wire pipe_out_416_valid = pipe_v_416; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_416_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_416_bits_0 = pipe_b_416_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_417; // @[Valid.scala:141:24] wire pipe_out_417_valid = pipe_v_417; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_417_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_417_bits_0 = pipe_b_417_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_418; // @[Valid.scala:141:24] wire pipe_out_418_valid = pipe_v_418; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_418_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_418_bits_0 = pipe_b_418_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_419; // @[Valid.scala:141:24] wire pipe_out_419_valid = pipe_v_419; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_419_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_419_bits_0 = pipe_b_419_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_420; // @[Valid.scala:141:24] wire pipe_out_420_valid = pipe_v_420; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_420_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_420_bits_0 = pipe_b_420_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_421; // @[Valid.scala:141:24] wire pipe_out_421_valid = pipe_v_421; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_421_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_421_bits_0 = pipe_b_421_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_422; // @[Valid.scala:141:24] wire pipe_out_422_valid = pipe_v_422; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_422_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_422_bits_0 = pipe_b_422_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_423; // @[Valid.scala:141:24] wire pipe_out_423_valid = pipe_v_423; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_423_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_423_bits_0 = pipe_b_423_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_424; // @[Valid.scala:141:24] wire pipe_out_424_valid = pipe_v_424; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_424_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_424_bits_0 = pipe_b_424_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_425; // @[Valid.scala:141:24] wire pipe_out_425_valid = pipe_v_425; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_425_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_425_bits_0 = pipe_b_425_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_426; // @[Valid.scala:141:24] wire pipe_out_426_valid = pipe_v_426; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_426_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_426_bits_0 = pipe_b_426_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_427; // @[Valid.scala:141:24] wire pipe_out_427_valid = pipe_v_427; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_427_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_427_bits_0 = pipe_b_427_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_428; // @[Valid.scala:141:24] wire pipe_out_428_valid = pipe_v_428; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_428_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_428_bits_0 = pipe_b_428_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_429; // @[Valid.scala:141:24] wire pipe_out_429_valid = pipe_v_429; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_429_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_429_bits_0 = pipe_b_429_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_430; // @[Valid.scala:141:24] wire pipe_out_430_valid = pipe_v_430; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_430_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_430_bits_0 = pipe_b_430_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_431; // @[Valid.scala:141:24] wire pipe_out_431_valid = pipe_v_431; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_431_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_431_bits_0 = pipe_b_431_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_432; // @[Valid.scala:141:24] wire pipe_out_432_valid = pipe_v_432; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_432_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_432_bits_0 = pipe_b_432_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_433; // @[Valid.scala:141:24] wire pipe_out_433_valid = pipe_v_433; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_433_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_433_bits_0 = pipe_b_433_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_434; // @[Valid.scala:141:24] wire pipe_out_434_valid = pipe_v_434; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_434_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_434_bits_0 = pipe_b_434_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_435; // @[Valid.scala:141:24] wire pipe_out_435_valid = pipe_v_435; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_435_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_435_bits_0 = pipe_b_435_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_436; // @[Valid.scala:141:24] wire pipe_out_436_valid = pipe_v_436; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_436_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_436_bits_0 = pipe_b_436_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_437; // @[Valid.scala:141:24] wire pipe_out_437_valid = pipe_v_437; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_437_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_437_bits_0 = pipe_b_437_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_438; // @[Valid.scala:141:24] wire pipe_out_438_valid = pipe_v_438; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_438_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_438_bits_0 = pipe_b_438_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_439; // @[Valid.scala:141:24] wire pipe_out_439_valid = pipe_v_439; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_439_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_439_bits_0 = pipe_b_439_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_440; // @[Valid.scala:141:24] wire pipe_out_440_valid = pipe_v_440; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_440_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_440_bits_0 = pipe_b_440_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_441; // @[Valid.scala:141:24] wire pipe_out_441_valid = pipe_v_441; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_441_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_441_bits_0 = pipe_b_441_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_442; // @[Valid.scala:141:24] wire pipe_out_442_valid = pipe_v_442; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_442_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_442_bits_0 = pipe_b_442_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_443; // @[Valid.scala:141:24] wire pipe_out_443_valid = pipe_v_443; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_443_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_443_bits_0 = pipe_b_443_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_444; // @[Valid.scala:141:24] wire pipe_out_444_valid = pipe_v_444; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_444_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_444_bits_0 = pipe_b_444_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_445; // @[Valid.scala:141:24] wire pipe_out_445_valid = pipe_v_445; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_445_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_445_bits_0 = pipe_b_445_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_446; // @[Valid.scala:141:24] wire pipe_out_446_valid = pipe_v_446; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_446_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_446_bits_0 = pipe_b_446_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_447; // @[Valid.scala:141:24] wire pipe_out_447_valid = pipe_v_447; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_447_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_447_bits_0 = pipe_b_447_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_448; // @[Valid.scala:141:24] wire pipe_out_448_valid = pipe_v_448; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_448_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_448_bits_0 = pipe_b_448_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_449; // @[Valid.scala:141:24] wire pipe_out_449_valid = pipe_v_449; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_449_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_449_bits_0 = pipe_b_449_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_450; // @[Valid.scala:141:24] wire pipe_out_450_valid = pipe_v_450; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_450_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_450_bits_0 = pipe_b_450_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_451; // @[Valid.scala:141:24] wire pipe_out_451_valid = pipe_v_451; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_451_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_451_bits_0 = pipe_b_451_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_452; // @[Valid.scala:141:24] wire pipe_out_452_valid = pipe_v_452; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_452_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_452_bits_0 = pipe_b_452_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_453; // @[Valid.scala:141:24] wire pipe_out_453_valid = pipe_v_453; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_453_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_453_bits_0 = pipe_b_453_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_454; // @[Valid.scala:141:24] wire pipe_out_454_valid = pipe_v_454; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_454_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_454_bits_0 = pipe_b_454_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_455; // @[Valid.scala:141:24] wire pipe_out_455_valid = pipe_v_455; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_455_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_455_bits_0 = pipe_b_455_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_456; // @[Valid.scala:141:24] wire pipe_out_456_valid = pipe_v_456; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_456_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_456_bits_0 = pipe_b_456_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_457; // @[Valid.scala:141:24] wire pipe_out_457_valid = pipe_v_457; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_457_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_457_bits_0 = pipe_b_457_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_458; // @[Valid.scala:141:24] wire pipe_out_458_valid = pipe_v_458; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_458_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_458_bits_0 = pipe_b_458_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_459; // @[Valid.scala:141:24] wire pipe_out_459_valid = pipe_v_459; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_459_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_459_bits_0 = pipe_b_459_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_460; // @[Valid.scala:141:24] wire pipe_out_460_valid = pipe_v_460; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_460_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_460_bits_0 = pipe_b_460_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_461; // @[Valid.scala:141:24] wire pipe_out_461_valid = pipe_v_461; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_461_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_461_bits_0 = pipe_b_461_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_462; // @[Valid.scala:141:24] wire pipe_out_462_valid = pipe_v_462; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_462_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_462_bits_0 = pipe_b_462_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_463; // @[Valid.scala:141:24] wire pipe_out_463_valid = pipe_v_463; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_463_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_463_bits_0 = pipe_b_463_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_464; // @[Valid.scala:141:24] wire pipe_out_464_valid = pipe_v_464; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_464_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_464_bits_0 = pipe_b_464_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_465; // @[Valid.scala:141:24] wire pipe_out_465_valid = pipe_v_465; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_465_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_465_bits_0 = pipe_b_465_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_466; // @[Valid.scala:141:24] wire pipe_out_466_valid = pipe_v_466; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_466_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_466_bits_0 = pipe_b_466_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_467; // @[Valid.scala:141:24] wire pipe_out_467_valid = pipe_v_467; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_467_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_467_bits_0 = pipe_b_467_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_468; // @[Valid.scala:141:24] wire pipe_out_468_valid = pipe_v_468; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_468_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_468_bits_0 = pipe_b_468_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_469; // @[Valid.scala:141:24] wire pipe_out_469_valid = pipe_v_469; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_469_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_469_bits_0 = pipe_b_469_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_470; // @[Valid.scala:141:24] wire pipe_out_470_valid = pipe_v_470; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_470_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_470_bits_0 = pipe_b_470_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_471; // @[Valid.scala:141:24] wire pipe_out_471_valid = pipe_v_471; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_471_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_471_bits_0 = pipe_b_471_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_472; // @[Valid.scala:141:24] wire pipe_out_472_valid = pipe_v_472; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_472_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_472_bits_0 = pipe_b_472_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_473; // @[Valid.scala:141:24] wire pipe_out_473_valid = pipe_v_473; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_473_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_473_bits_0 = pipe_b_473_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_474; // @[Valid.scala:141:24] wire pipe_out_474_valid = pipe_v_474; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_474_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_474_bits_0 = pipe_b_474_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_475; // @[Valid.scala:141:24] wire pipe_out_475_valid = pipe_v_475; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_475_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_475_bits_0 = pipe_b_475_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_476; // @[Valid.scala:141:24] wire pipe_out_476_valid = pipe_v_476; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_476_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_476_bits_0 = pipe_b_476_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_477; // @[Valid.scala:141:24] wire pipe_out_477_valid = pipe_v_477; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_477_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_477_bits_0 = pipe_b_477_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_478; // @[Valid.scala:141:24] wire pipe_out_478_valid = pipe_v_478; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_478_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_478_bits_0 = pipe_b_478_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_479; // @[Valid.scala:141:24] wire pipe_out_479_valid = pipe_v_479; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_479_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_479_bits_0 = pipe_b_479_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_480; // @[Valid.scala:141:24] wire pipe_out_480_valid = pipe_v_480; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_480_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_480_bits_0 = pipe_b_480_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_481; // @[Valid.scala:141:24] wire pipe_out_481_valid = pipe_v_481; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_481_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_481_bits_0 = pipe_b_481_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_482; // @[Valid.scala:141:24] wire pipe_out_482_valid = pipe_v_482; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_482_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_482_bits_0 = pipe_b_482_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_483; // @[Valid.scala:141:24] wire pipe_out_483_valid = pipe_v_483; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_483_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_483_bits_0 = pipe_b_483_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_484; // @[Valid.scala:141:24] wire pipe_out_484_valid = pipe_v_484; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_484_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_484_bits_0 = pipe_b_484_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_485; // @[Valid.scala:141:24] wire pipe_out_485_valid = pipe_v_485; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_485_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_485_bits_0 = pipe_b_485_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_486; // @[Valid.scala:141:24] wire pipe_out_486_valid = pipe_v_486; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_486_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_486_bits_0 = pipe_b_486_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_487; // @[Valid.scala:141:24] wire pipe_out_487_valid = pipe_v_487; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_487_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_487_bits_0 = pipe_b_487_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_488; // @[Valid.scala:141:24] wire pipe_out_488_valid = pipe_v_488; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_488_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_488_bits_0 = pipe_b_488_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_489; // @[Valid.scala:141:24] wire pipe_out_489_valid = pipe_v_489; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_489_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_489_bits_0 = pipe_b_489_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_490; // @[Valid.scala:141:24] wire pipe_out_490_valid = pipe_v_490; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_490_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_490_bits_0 = pipe_b_490_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_491; // @[Valid.scala:141:24] wire pipe_out_491_valid = pipe_v_491; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_491_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_491_bits_0 = pipe_b_491_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_492; // @[Valid.scala:141:24] wire pipe_out_492_valid = pipe_v_492; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_492_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_492_bits_0 = pipe_b_492_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_493; // @[Valid.scala:141:24] wire pipe_out_493_valid = pipe_v_493; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_493_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_493_bits_0 = pipe_b_493_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_494; // @[Valid.scala:141:24] wire pipe_out_494_valid = pipe_v_494; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_494_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_494_bits_0 = pipe_b_494_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_495; // @[Valid.scala:141:24] wire pipe_out_495_valid = pipe_v_495; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_495_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_495_bits_0 = pipe_b_495_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_496; // @[Valid.scala:141:24] wire pipe_out_496_valid = pipe_v_496; // @[Valid.scala:135:21, :141:24] reg [7:0] pipe_b_496_0; // @[Valid.scala:142:26] wire [7:0] pipe_out_496_bits_0 = pipe_b_496_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_497; // @[Valid.scala:141:24] wire pipe_out_497_valid = pipe_v_497; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_497_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_497_bits_0 = pipe_b_497_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_498; // @[Valid.scala:141:24] wire pipe_out_498_valid = pipe_v_498; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_498_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_498_bits_0 = pipe_b_498_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_499; // @[Valid.scala:141:24] wire pipe_out_499_valid = pipe_v_499; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_499_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_499_bits_0 = pipe_b_499_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_500; // @[Valid.scala:141:24] wire pipe_out_500_valid = pipe_v_500; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_500_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_500_bits_0 = pipe_b_500_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_501; // @[Valid.scala:141:24] wire pipe_out_501_valid = pipe_v_501; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_501_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_501_bits_0 = pipe_b_501_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_502; // @[Valid.scala:141:24] wire pipe_out_502_valid = pipe_v_502; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_502_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_502_bits_0 = pipe_b_502_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_503; // @[Valid.scala:141:24] wire pipe_out_503_valid = pipe_v_503; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_503_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_503_bits_0 = pipe_b_503_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_504; // @[Valid.scala:141:24] wire pipe_out_504_valid = pipe_v_504; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_504_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_504_bits_0 = pipe_b_504_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_505; // @[Valid.scala:141:24] wire pipe_out_505_valid = pipe_v_505; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_505_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_505_bits_0 = pipe_b_505_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_506; // @[Valid.scala:141:24] wire pipe_out_506_valid = pipe_v_506; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_506_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_506_bits_0 = pipe_b_506_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_507; // @[Valid.scala:141:24] wire pipe_out_507_valid = pipe_v_507; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_507_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_507_bits_0 = pipe_b_507_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_508; // @[Valid.scala:141:24] wire pipe_out_508_valid = pipe_v_508; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_508_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_508_bits_0 = pipe_b_508_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_509; // @[Valid.scala:141:24] wire pipe_out_509_valid = pipe_v_509; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_509_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_509_bits_0 = pipe_b_509_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_510; // @[Valid.scala:141:24] wire pipe_out_510_valid = pipe_v_510; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_510_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_510_bits_0 = pipe_b_510_0; // @[Valid.scala:135:21, :142:26] reg pipe_v_511; // @[Valid.scala:141:24] wire pipe_out_511_valid = pipe_v_511; // @[Valid.scala:135:21, :141:24] reg [19:0] pipe_b_511_0; // @[Valid.scala:142:26] wire [19:0] pipe_out_511_bits_0 = pipe_b_511_0; // @[Valid.scala:135:21, :142:26]

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Debug.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBFanout, APBToTL} import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule} import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError} import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode} import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.rocket.{CSRs, Instructions} import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar} import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle} import freechips.rocketchip.util.SeqBoolBitwiseOps import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.BooleanToAugmentedBoolean object DsbBusConsts { def sbAddrWidth = 12 def sbIdWidth = 10 } object DsbRegAddrs{ // These are used by the ROM. def HALTED = 0x100 def GOING = 0x104 def RESUMING = 0x108 def EXCEPTION = 0x10C def WHERETO = 0x300 // This needs to be aligned for up to lq/sq // This shows up in HartInfo, and needs to be aligned // to enable up to LQ/SQ instructions. def DATA = 0x380 // We want DATA to immediately follow PROGBUF so that we can // use them interchangeably. Leave another slot if there is an // implicit ebreak. def PROGBUF(cfg:DebugModuleParams) = { val tmp = DATA - (cfg.nProgramBufferWords * 4) if (cfg.hasImplicitEbreak) (tmp - 4) else tmp } // This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF. def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 } // We want abstract to be immediately before PROGBUF // because we auto-generate 2 (or 5) instructions. def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4) def FLAGS = 0x400 def ROMBASE = 0x800 } /** Enumerations used both in the hardware * and in the configuration specification. */ object DebugModuleAccessType extends scala.Enumeration { type DebugModuleAccessType = Value val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value } object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } object DebugAbstractCommandType extends scala.Enumeration { type DebugAbstractCommandType = Value val AccessRegister, QuickAccess = Value } /** Parameters exposed to the top-level design, set based on * external requirements, etc. * * This object checks that the parameters conform to the * full specification. The implementation which receives this * object can perform more checks on what that implementation * actually supports. * @param nComponents Number of components to support debugging. * @param baseAddress Base offest for debugEntry and debugException * @param nDMIAddrSize Size of the Debug Bus Address * @param nAbstractDataWords Number of 32-bit words for Abstract Commands * @param nProgamBufferWords Number of 32-bit words for Program Buffer * @param hasBusMaster Whether or not a bus master should be included * @param clockGate Whether or not to use dmactive as the clockgate for debug module * @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic. * @param supportQuickAccess Whether or not to support the quick access command. * @param supportHartArray Whether or not to implement the hart array register (if >1 hart). * @param nHaltGroups Number of halt groups * @param nExtTriggers Number of external triggers * @param hasHartResets Feature to reset all the currently selected harts * @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak * @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset. */ case class DebugModuleParams ( baseAddress : BigInt = BigInt(0), nDMIAddrSize : Int = 7, nProgramBufferWords: Int = 16, nAbstractDataWords : Int = 4, nScratch : Int = 1, hasBusMaster : Boolean = false, clockGate : Boolean = true, maxSupportedSBAccess : Int = 32, supportQuickAccess : Boolean = false, supportHartArray : Boolean = true, nHaltGroups : Int = 1, nExtTriggers : Int = 0, hasHartResets : Boolean = false, hasImplicitEbreak : Boolean = false, hasAuthentication : Boolean = false, crossingHasSafeReset : Boolean = true ) { require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}") require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}") require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}") require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}") require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}") if (supportQuickAccess) { // TODO: Check that quick access requirements are met. } def address = AddressSet(baseAddress, 0xFFF) /** the base address of DM */ def atzero = (baseAddress == 0) /** The number of generated instructions * * When the base address is not zero, we need more instruction also, * more dscratch registers) to load/store memory mapped data register * because they may no longer be directly addressible with x0 + 12-bit imm */ def nAbstractInstructions = if (atzero) 2 else 5 def debugEntry: BigInt = baseAddress + 0x800 def debugException: BigInt = baseAddress + 0x808 def nDscratch: Int = if (atzero) 1 else 2 } object DefaultDebugModuleParams { def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = { new DebugModuleParams().copy( nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4), maxSupportedSBAccess = xlen ) } } case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams())) /** Functional parameters exposed to the design configuration. * * hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping. * hartSelToHartId: Provide inverse mapping of the above */ case class DebugModuleHartSelFuncs ( hartIdToHartSel : (UInt) => UInt = (x:UInt) => x, hartSelToHartId : (UInt) => UInt = (x:UInt) => x ) case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs()) class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle { val req = Output(UInt(nExtTriggers.W)) val ack = Input(UInt(nExtTriggers.W)) } class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle { val req = Input(UInt(nExtTriggers.W)) val ack = Output(UInt(nExtTriggers.W)) } class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers) val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers) } class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) { val dmactive = Output(Bool()) val dmAuthWrite = Output(Bool()) val dmAuthRead = Output(Bool()) val dmAuthWdata = Output(UInt(32.W)) val dmAuthBusy = Input(Bool()) val dmAuthRdata = Input(UInt(32.W)) val dmAuthenticated = Input(Bool()) } // ***************************************** // Module Interfaces // // ***************************************** /** Control signals for Inner, generated in Outer * {{{ * run control: resumreq, ackhavereset, halt-on-reset mask * hart select: hasel, hartsel and the hart array mask * }}} */ class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** resume request */ val resumereq = Bool() /** hart select */ val hartsel = UInt(10.W) /** reset acknowledge */ val ackhavereset = Bool() /** hart array enable */ val hasel = Bool() /** hart array mask */ val hamask = Vec(nComponents, Bool()) /** halt-on-reset mask */ val hrmask = Vec(nComponents, Bool()) } /** structure for top-level Debug Module signals which aren't the bus interfaces. */ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) { /** debug availability status for all harts */ val debugUnavail = Input(Vec(nComponents, Bool())) /** reset signal * * for every part of the hardware platform, * including every hart, except for the DM and any * logic required to access the DM */ val ndreset = Output(Bool()) /** reset signal for the DM itself */ val dmactive = Output(Bool()) /** dmactive acknowlege */ val dmactiveAck = Input(Bool()) } // ***************************************** // Debug Module // // ***************************************** /** Parameterized version of the Debug Module defined in the * RISC-V Debug Specification * * DebugModule is a slave to two asynchronous masters: * The Debug Bus (DMI) -- This is driven by an external debugger * * The System Bus -- This services requests from the cores. Generally * this interface should only be active at the request * of the debugger, but the Debug Module may also * provide the default MTVEC since it is mapped * to address 0x0. * * DebugModule is responsible for control registers and RAM, and * Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and * the TL clock. Therefore, it is divided into "Outer" portion (running * off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset). * This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive, * and ndreset to be modified even while the Core is in reset or not being clocked. * Not all reads from the Debugger to the Debug Module will actually complete * in these scenarios either, they will just block until tl_clock and tl_reset * allow them to complete. This is not strictly necessary for * proper debugger functionality. */ // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, 0.U, RegWriteFn((valid, data) => { set := valid value := data true.B }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.W))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}), RegWriteFn((valid, data) => { wNotify := valid when (valid) {wVal := data} true.B } ), desc) } } // Local reg mapper function : Notify with value when written, take read input as presented. // This allows checking or correcting the write value before storing it in the register field. object WNotifyVal { def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = { RegField(n, rVal, RegWriteFn((valid, data) => { wNotify := valid wVal := data true.B } ), desc) } } class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get val intnode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false) val dmiNode = TLRegisterNode ( address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++ AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++ AddressSet.misaligned(DMI_HAWINDOW << 2, 4), device = device, beatBytes = 4, executable = false ) lazy val module = new Impl class Impl extends LazyModuleImp(this) { require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts") val nComponents = intnode.out.size def getNComponents = () => nComponents val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart val io = IO(new Bundle { /** structure for top-level Debug Module signals which aren't the bus interfaces. */ val ctrl = (new DebugCtrlBundle(nComponents)) /** control signals for Inner, generated in Outer */ val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents)) /** debug interruption from Inner to Outer * * contains 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** authentication support */ val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool())) }) val omRegMap = withReset(reset.asAsyncReset) { // FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available) val dmAuthenticated = io.dmAuthenticated.map( dma => ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B) //----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it // can be written even if 'Inner' is not being clocked or is in reset. This allows halting // harts while the rest of the system is in reset. It doesn't really allow any other // register accesses, which will keep returning 'busy' to the debugger interface. val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg") val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields())) val dmactiveWrEn = WireInit(false.B) val ndmresetWrEn = WireInit(false.B) val clrresethaltreqWrEn = WireInit(false.B) val setresethaltreqWrEn = WireInit(false.B) val hartselloWrEn = WireInit(false.B) val haselWrEn = WireInit(false.B) val ackhaveresetWrEn = WireInit(false.B) val hartresetWrEn = WireInit(false.B) val resumereqWrEn = WireInit(false.B) val haltreqWrEn = WireInit(false.B) val dmactive = DMCONTROLReg.dmactive DMCONTROLNxt := DMCONTROLReg when (~dmactive) { DMCONTROLNxt := DMCONTROLReset } .otherwise { when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset } when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask} when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel } when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset } when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq } } // Put this last to override its own effects. when (dmactiveWrEn) { DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive } //----HARTINFO // DATA registers are mapped to memory. The dataaddr field of HARTINFO has only // 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0 // (implying nonexistence according to the Debug Spec). val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields())) if (cfg.atzero) when (dmAuthenticated) { HARTINFORdData.dataaccess := true.B HARTINFORdData.datasize := cfg.nAbstractDataWords.U HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U HARTINFORdData.nscratch := cfg.nScratch.U } //-------------------------------------------------------------- // Hart array mask and window // hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello // HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW //-------------------------------------------------------------- val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) def haWindowSize = 32 // The following need to be declared even if supportHartArray is false due to reference // at compile time by dmiNode.regmap val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELWrEn = WireInit(false.B) val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAWINDOWWrEn = WireInit(false.B) /** whether the hart is selected */ def hartSelected(hart: Int): Bool = { ((io.innerCtrl.bits.hartsel === hart.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B)) } val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt)) if (supportHartArray) { val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields())) HAWINDOWSELNxt := HAWINDOWSELReg when (~dmactive || ~dmAuthenticated) { HAWINDOWSELNxt := HAWINDOWSELReset } .otherwise { when (HAWINDOWSELWrEn) { // Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window if (nComponents > haWindowSize) { HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U } else { HAWINDOWSELNxt.hawindowsel := 0.U } } } val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1 HAWINDOWRdData.maskdata := 0.U // default, overridden below // for each slice,use a hamaskReg to store the selection info for (ii <- 0 until numHAMASKSlices) { val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields())) val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt)) when (ii.U === HAWINDOWSELReg.hawindowsel) { HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U } HAMASKNxt.maskdata := HAMASKReg.asUInt when (~dmactive || ~dmAuthenticated) { HAMASKNxt := HAMASKRst }.otherwise { when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { HAMASKNxt.maskdata := HAWINDOWWrData.maskdata } } // drive each slice of hamask with stored HAMASKReg or with new value being written for (jj <- 0 until haWindowSize) { if (((ii*haWindowSize) + jj) < nComponents) { val tempWrData = HAWINDOWWrData.maskdata.asBools val tempMaskReg = HAMASKReg.asUInt.asBools when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) { hamask(ii*haWindowSize + jj) := tempWrData(jj) }.otherwise { hamask(ii*haWindowSize + jj) := tempMaskReg(jj) } } } } } //-------------------------------------------------------------- // Halt-on-reset // hrmaskReg is current set of harts that should halt-on-reset // Reset state (dmactive=0) is all zeroes // Bits are set by writing 1 to DMCONTROL.setresethaltreq // Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq // Spec says if both are 1, then clrresethaltreq is executed // hrmask is the halt-on-reset mask which will be sent to inner //-------------------------------------------------------------- val hrmask = Wire(Vec(nComponents, Bool())) val hrmaskNxt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg") hrmaskNxt := hrmaskReg for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { hrmaskNxt(component) := false.B }.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) { hrmaskNxt(component) := false.B }.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) { hrmaskNxt(component) := true.B } } hrmask := hrmaskNxt val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq( WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn, RegFieldDesc("dmactive", "debug module active", reset=Some(0))), WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn, RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))), WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn, RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn, RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)), RegField(12), if (nComponents > 1) WNotifyVal(p(MaxHartIdBits), DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn, RegFieldDesc("hartsello", "hart select low", reset=Some(0))) else RegField(1), if (nComponents > 1) RegField(10-p(MaxHartIdBits)) else RegField(9), if (supportHartArray) WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn, RegFieldDesc("hasel", "hart array select", reset=Some(0))) else RegField(1), RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn, RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)), if (cfg.hasHartResets) WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn, RegFieldDesc("hartreset", "hart reset request", reset=Some(0))) else RegField(1), WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn, RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)), WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior RegFieldDesc("haltreq", "halt request", reset=Some(0))) )) val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq( RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))), RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))), RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))), RegField(3), RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0))) )) //-------------------------------------------------------------- // DMI register decoder for Outer //-------------------------------------------------------------- // regmap addresses are byte offsets from lowest address def DMI_DMCONTROL_OFFSET = 0 def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2) def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2) def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2) val omRegMap = dmiNode.regmap( DMI_DMCONTROL_OFFSET -> dmControlRegFields, DMI_HARTINFO_OFFSET -> hartinfoRegFields, DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq( WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn, RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil), DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq( WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn, RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil) ) //-------------------------------------------------------------- // Interrupt Registers //-------------------------------------------------------------- val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs") debugIntNxt := debugIntRegs val (intnode_out, _) = intnode.out.unzip for (component <- 0 until nComponents) { intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component) } // sends debug interruption to Core when dmcs.haltreq is set, for (component <- 0 until nComponents) { when (~dmactive || ~dmAuthenticated) { debugIntNxt(component) := false.B }. otherwise { when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U) || (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) { debugIntNxt(component) := DMCONTROLWrData.haltreq } } } // Halt request registers are set & cleared by writes to DMCONTROL.haltreq // resumereq also causes the core to execute a 'dret', // so resumereq is passed through to Inner. // hartsel/hasel/hamask must also be used by the DebugModule state machine, // so it is passed to Inner. // These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together. // If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received. // Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent. // Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received. val innerCtrlValid = Wire(Bool()) val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg") val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg") val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg") innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn | (HAWINDOWWrEn & supportHartArray.B) innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg io.innerCtrl.bits.hrmask := hrmask if (supportHartArray) { io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel) io.innerCtrl.bits.hamask := hamask } else { io.innerCtrl.bits.hasel := DontCare io.innerCtrl.bits.hamask := DontCare } io.ctrl.ndreset := DMCONTROLReg.ndmreset io.ctrl.dmactive := DMCONTROLReg.dmactive // hart reset mechanism implementation if (cfg.hasHartResets) { val hartResetNxt = Wire(Vec(nComponents, Bool())) val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt)) for (component <- 0 until nComponents) { hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component) io.hartResetReq.get(component) := hartResetReg(component) } } omRegMap // FIXME: Remove this when withReset is removed }} } // wrap a Outer with a DMIToTL, derived by dmi clock & reset class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule { val cfg = p(DebugModuleKey).get val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar"))) val dmi2tlOpt = (!p(ExportDebug).apb).option({ val dmi2tl = LazyModule(new DMIToTL()) dmiXbar.node := dmi2tl.node dmi2tl }) val apbNodeOpt = p(ExportDebug).apb.option({ val apb2tl = LazyModule(new APBToTL()) val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe)) val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4) val tlError = LazyModule(new TLError(tlErrorParams, buffer=false)) val apbXbar = LazyModule(new APBFanout()) val apbRegs = LazyModule(new APBDebugRegisters()) apbRegs.node := apbXbar.node apb2tl.node := apbXbar.node apb2tlBuffer.node := apb2tl.node dmiXbar.node := apb2tlBuffer.node tlError.node := dmiXbar.node apbXbar.node }) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val intnode = IntSyncIdentityNode() intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4)) val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node dmOuter.dmiNode := dmiXbar.node lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.intnode.edges.out.size val io = IO(new Bundle { val dmi_clock = Input(Clock()) val dmi_reset = Input(Reset()) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p))) // Optional APB Interface is fully diplomatic so is not listed here. val ctrl = new DebugCtrlBundle(nComponents) /** conrol signals for Inner, generated in Outer */ val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) /** debug interruption generated in Inner */ val hgDebugInt = Input(Vec(nComponents, Bool())) /** hart reset request to core */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Authentication signal from core */ val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool())) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.dmi_clock childReset := io.dmi_reset override def provideImplicitClockToLazyChildren = true withClockAndReset(childClock, childReset) { dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get } val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync")) dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck io.ctrl <> dmOuter.module.io.ctrl dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)) dmOuter.module.io.hgDebugInt := io.hgDebugInt io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}} } } } class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // For Shorter Register Names import DMI_RegAddrs._ val cfg = p(DebugModuleKey).get def getCfg = () => cfg val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2 /** dmiNode address set */ val dmiNode = TLRegisterNode( // Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++ AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++ AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++ AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))), device = device, beatBytes = 4, executable = false ) val tlNode = TLRegisterNode( address=Seq(cfg.address), device=device, beatBytes=beatBytes, executable=true ) val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL())) // If we want to support custom registers read through Abstract Commands, // provide a place to bring them into the debug module. What this connects // to is up to the implementation. val customNode = new DebugCustomSink() lazy val module = new Impl class Impl extends LazyModuleImp(this){ val nComponents = getNComponents() Annotated.params(this, cfg) val supportHartArray = cfg.supportHartArray & (nComponents > 1) val nExtTriggers = cfg.nExtTriggers val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups else 0 // no halt groups possible if single hart with no external triggers val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs( hartIdToHartSel = (x) => 0.U, hartSelToHartId = (x) => x ) val io = IO(new Bundle { /** dm reset signal passed in from Outer */ val dmactive = Input(Bool()) /** conrol signals for Inner * * it's generated by Outer and comes in */ val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents))) /** debug unavail signal passed in from Outer*/ val debugUnavail = Input(Vec(nComponents, Bool())) /** debug interruption from Inner to Outer * * contain 2 type of debug interruption causes: * - halt group * - halt-on-reset */ val hgDebugInt = Output(Vec(nComponents, Bool())) /** interface for trigger */ val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug Authentication signals from core */ val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO()) }) sb2tlOpt.map { sb => sb.module.clock := io.tl_clock sb.module.reset := io.tl_reset sb.module.rf_reset := io.tl_reset } //-------------------------------------------------------------- // Import constants for shorter variable names //-------------------------------------------------------------- import DMI_RegAddrs._ import DsbRegAddrs._ import DsbBusConsts._ //-------------------------------------------------------------- // Sanity Check Configuration For this implementation. //-------------------------------------------------------------- require (cfg.supportQuickAccess == false, "No Quick Access support yet") require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group") //-------------------------------------------------------------- // Register & Wire Declarations (which need to be pre-declared) //-------------------------------------------------------------- // run control regs: tracking all the harts // implements: see implementation-specific bits part /** all harts halted status */ val haltedBitRegs = Reg(UInt(nComponents.W)) /** all harts resume request status */ val resumeReqRegs = Reg(UInt(nComponents.W)) /** all harts have reset status */ val haveResetBitRegs = Reg(UInt(nComponents.W)) // default is 1,after resume, resumeAcks get 0 /** all harts resume ack status */ val resumeAcks = Wire(UInt(nComponents.W)) // --- regmapper outputs // hart state Id and En // in Hart Bus Access ROM val hartHaltedWrEn = Wire(Bool()) val hartHaltedId = Wire(UInt(sbIdWidth.W)) val hartGoingWrEn = Wire(Bool()) val hartGoingId = Wire(UInt(sbIdWidth.W)) val hartResumingWrEn = Wire(Bool()) val hartResumingId = Wire(UInt(sbIdWidth.W)) val hartExceptionWrEn = Wire(Bool()) val hartExceptionId = Wire(UInt(sbIdWidth.W)) // progbuf and abstract data: byte-addressable control logic // AccessLegal is set only when state = waiting // RdEn and WrEnMaybe : contrl signal drived by DMI bus val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiProgramBufferAccessLegal = WireInit(false.B) val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) val dmiAbstractDataAccessLegal = WireInit(false.B) val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) //-------------------------------------------------------------- // Registers coming from 'CONTROL' in Outer //-------------------------------------------------------------- val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B) val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W)) // hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nComponents > 1) { when (~io.dmactive) { selectedHartReg := 0.U }.elsewhen (io.innerCtrl.fire){ selectedHartReg := io.innerCtrl.bits.hartsel } } if (supportHartArray) { val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) val hamaskReg = Reg(Vec(nComponents, Bool())) when (~io.dmactive || ~dmAuthenticated) { hamaskReg := hamaskZero }.elsewhen (io.innerCtrl.fire){ hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero) } hamaskFull := hamaskReg } // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello, // so append it here when (selectedHartReg < nComponents.U) { hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B } io.innerCtrl.ready := true.B // Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write // A hart may be selected by hartsel field or by hart array val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) for (component <- 0 until nComponents ) { hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) || (if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B)) } //------------------------------------- // Halt-on-reset logic // hrmask is set in dmOuter and passed in // Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set // Debug interrupt is maintained until the hart enters halted state //------------------------------------- val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } )) val hrDebugInt = Wire(Vec(nComponents, Bool())) val hrmaskReg = RegInit(hrReset) val hartIsInResetSync = Wire(Vec(nComponents, Bool())) for (component <- 0 until nComponents) { hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component")) } when (~io.dmactive || ~dmAuthenticated) { hrmaskReg := hrReset }.elsewhen (io.innerCtrl.fire){ hrmaskReg := io.innerCtrl.bits.hrmask } withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } )) when (~io.dmactive || ~dmAuthenticated) { hrDebugIntReg := hrReset }.otherwise { hrDebugIntReg := hrmaskReg & (hartIsInResetSync | // set debugInt during reset (hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts } hrDebugInt := hrDebugIntReg } //-------------------------------------------------------------- // DMI Registers //-------------------------------------------------------------- //----DMSTATUS val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields())) DMSTATUSRdData.authenticated := dmAuthenticated DMSTATUSRdData.version := 2.U // Version 0.13 io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy) val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq when (dmAuthenticated) { DMSTATUSRdData.hasresethaltreq := true.B DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent // all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _)) when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _) DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _) when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _) DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _) } } //TODO DMSTATUSRdData.confstrptrvalid := false.B DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B } when(~io.dmactive || ~dmAuthenticated) { haveResetBitRegs := 0.U }.otherwise { when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) { haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt }.otherwise { haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt } } //----DMCS2 (Halt Groups) val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields())) val hgselectWrEn = WireInit(false.B) val hgwriteWrEn = WireInit(false.B) val haltgroupWrEn = WireInit(false.B) val exttriggerWrEn = WireInit(false.B) val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} )) if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup val hgBits = log2Up(nHaltGroups) // hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned. val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W)))) val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil // assign group index to current seledcted harts for (component <- 0 until nComponents) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateHart(component) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect & hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateHart(component) := DMCS2WrData.haltgroup } } } DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg) if (nExtTriggers > 0) { val hgSelect = Reg(Bool()) when (~io.dmactive || ~dmAuthenticated) { hgSelect := false.B }.otherwise { when (hgselectWrEn) { hgSelect := DMCS2WrData.hgselect } } // assign group index to trigger for (trigger <- 0 until nExtTriggers) { when (~io.dmactive || ~dmAuthenticated) { hgParticipateTrig(trigger) := 0.U }.otherwise { when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect & (DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) { hgParticipateTrig(trigger) := DMCS2WrData.haltgroup } } } DMCS2RdData.hgselect := hgSelect when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(0) } // If there is only 1 ext trigger, then the exttrigger field is fixed at 0 // Otherwise, instantiate a register with only the number of bits required if (nExtTriggers > 1) { val trigBits = log2Up(nExtTriggers-1) val hgExtTrigger = Reg(UInt(trigBits.W)) when (~io.dmactive || ~dmAuthenticated) { hgExtTrigger := 0.U }.otherwise { when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) { hgExtTrigger := DMCS2WrData.exttrigger } } DMCS2RdData.exttrigger := hgExtTrigger when (hgSelect) { DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger) } } } // Halt group state machine // IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0 // or when any trigin assigned to this hg occurs // FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs // and all trig out in this hg have been acknowledged val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} )) val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked io.extTrigger.foreach {extTrigger => val extTriggerInReq = Wire(Vec(nExtTriggers, Bool())) val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool())) extTriggerInReq := extTrigger.in.req.asBools extTriggerOutAck := extTrigger.out.ack.asBools val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync")) val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync")) for (hg <- 1 to nHaltGroups) { hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _) hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _) } extTrigger.in.ack := trigInReq.asUInt } for (hg <- 1 to nHaltGroups) { hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U) hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _) when (~io.dmactive || ~dmAuthenticated) { hgFired(hg) := false.B }.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) { hgFired(hg) := true.B }.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) { hgFired(hg) := false.B } } // For each hg that has fired, assert debug interrupt to each hart in that hg for (component <- 0 until nComponents) { hgDebugInt(component) := hgFired(hgParticipateHart(component)) } // For each hg that has fired, assert trigger out for all external triggers in that hg io.extTrigger.foreach {extTrigger => val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} )) for (trig <- 0 until nExtTriggers) { extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig)) } extTrigger.out.req := extTriggerOutReq.asUInt } } io.hgDebugInt := hgDebugInt | hrDebugInt //----HALTSUM* val numHaltedStatus = ((nComponents - 1) / 32) + 1 val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W))) for (ii <- 0 until numHaltedStatus) { when (dmAuthenticated) { haltedStatus(ii) := haltedBitRegs >> (ii*32) }.otherwise { haltedStatus(ii) := 0.U } } val haltedSummary = Cat(haltedStatus.map(_.orR).reverse) val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields()) val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5)) val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields()) // Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3 //----ABSTRACTCS val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U val ABSTRACTCSReg = Reg(new ABSTRACTCSFields()) val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields())) val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg) val ABSTRACTCSRdEn = WireInit(false.B) val ABSTRACTCSWrEnMaybe = WireInit(false.B) val ABSTRACTCSWrEnLegal = WireInit(false.B) val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal // multiple error types // find implement in the state machine part val errorBusy = WireInit(false.B) val errorException = WireInit(false.B) val errorUnsupported = WireInit(false.B) val errorHaltResume = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTCSReg := ABSTRACTCSReset }.otherwise { when (errorBusy){ ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U }.elsewhen (errorException) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U }.elsewhen (errorUnsupported) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U }.elsewhen (errorHaltResume) { ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U }.otherwise { //W1C when (ABSTRACTCSWrEn){ ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr); } } } // For busy, see below state machine. val abstractCommandBusy = WireInit(true.B) ABSTRACTCSRdData.busy := abstractCommandBusy when (~dmAuthenticated) { // read value must be 0 when not authenticated ABSTRACTCSRdData.datacount := 0.U ABSTRACTCSRdData.progbufsize := 0.U } //---- ABSTRACTAUTO // It is a mask indicating whether datai/probufi have the autoexcution permisson // this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec // first two specify which reg supports autoexec // autoexec is a control signal, meaning there is at least one enabled autoexec reg // when autoexec is set, generate instructions using COMMAND register val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields()) val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields())) val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg) val ABSTRACTAUTORdEn = WireInit(false.B) val autoexecdataWrEnMaybe = WireInit(false.B) val autoexecprogbufWrEnMaybe = WireInit(false.B) val ABSTRACTAUTOWrEnLegal = WireInit(false.B) when (~io.dmactive || ~dmAuthenticated) { ABSTRACTAUTOReg := ABSTRACTAUTOReset }.otherwise { when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U } when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) { ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U } } // Abstract Data access vector(byte-addressable) val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} )) dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w} // Program Buffer access vector(byte-addressable) val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} )) dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w} // at least one word access val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ ) val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _) // This will take the shorter of the lists, which is what we want. val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} )) val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} )) (autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 } (autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2} val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _) //---- COMMAND val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields())) val COMMANDReg = Reg(new COMMANDFields()) val COMMANDWrDataVal = WireInit(0.U(32.W)) val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields())) val COMMANDWrEnMaybe = WireInit(false.B) val COMMANDWrEnLegal = WireInit(false.B) val COMMANDRdEn = WireInit(false.B) val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal val COMMANDRdData = COMMANDReg when (~io.dmactive || ~dmAuthenticated) { COMMANDReg := COMMANDReset }.otherwise { when (COMMANDWrEn) { COMMANDReg := COMMANDWrData } } // --- Abstract Data // These are byte addressible, s.t. the Processor can use // byte-addressible instructions to store to them. val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W))) val abstractDataNxt = WireInit(abstractDataMem) // --- Program Buffer // byte-addressible mem val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W))) val programBufferNxt = WireInit(programBufferMem) //-------------------------------------------------------------- // These bits are implementation-specific bits set // by harts executing code. //-------------------------------------------------------------- // Run control logic when (~io.dmactive || ~dmAuthenticated) { haltedBitRegs := 0.U resumeReqRegs := 0.U }.otherwise { //remove those harts in reset resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt) val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId)) val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId)) val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel) when (hartHaltedWrEn) { // add those harts halting and remove those in reset haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt) }.elsewhen (hartResumingWrEn) { // remove those harts in reset and those in resume haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) }.otherwise { // remove those harts in reset haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt) } when (hartResumingWrEn) { // remove those harts in resume and those in reset resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt) } when (resumereq) { // set all sleceted harts to resumeReq, remove those in reset resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt) } } when (resumereq) { // next cycle resumeAcls will be the negation of next cycle resumeReqRegs resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt)) }.otherwise { resumeAcks := ~resumeReqRegs } //---- AUTHDATA val authRdEnMaybe = WireInit(false.B) val authWrEnMaybe = WireInit(false.B) io.auth.map { a => a.dmactive := io.dmactive a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy } val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq( RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))), RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))), RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))), RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))), RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))), RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))), RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))), RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))), RegField(2), RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0))) )) val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq( WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn, RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)), WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn, RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)), WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn, RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)), if (nExtTriggers > 1) WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn, RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true)) else RegField(4) )) val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq( RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))), RegField(4), WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe, RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))), RegField(1), RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))), RegField(11), RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords))) )) val (sbcsFields, sbAddrFields, sbDataFields): (Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl => SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p) }.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]))) //-------------------------------------------------------------- // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- val omRegMap = dmiNode.regmap( (DMI_DMSTATUS << 2) -> dmstatusRegFields, //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, (DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil), (DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"), Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))), (DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"), Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))), (DMI_ABSTRACTCS << 2) -> abstractcsRegFields, (DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq( WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe, RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))), RegField(16-cfg.nAbstractDataWords), WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe, RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))), (DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"), Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))), (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i), dmiAbstractDataRdEn(i), dmiAbstractDataWrEnMaybe(i), Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false), (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i), dmiProgramBufferRdEn(i), dmiProgramBufferWrEnMaybe(i), Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false), (DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"), Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe, Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil), (DMI_SBCS << 2) -> sbcsFields, (DMI_SBDATA0 << 2) -> sbDataFields(0), (DMI_SBDATA1 << 2) -> sbDataFields(1), (DMI_SBDATA2 << 2) -> sbDataFields(2), (DMI_SBDATA3 << 2) -> sbDataFields(3), (DMI_SBADDRESS0 << 2) -> sbAddrFields(0), (DMI_SBADDRESS1 << 2) -> sbAddrFields(1), (DMI_SBADDRESS2 << 2) -> sbAddrFields(2), (DMI_SBADDRESS3 << 2) -> sbAddrFields(3) ) // Abstract data mem is written by both the tile link interface and DMI... abstractDataMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) { x := abstractDataNxt(i) } } // ... and also by custom register read (if implemented) val (customs, customParams) = customNode.in.unzip val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0) def getNeedCustom = () => needCustom if (needCustom) { val (custom, customP) = customNode.in.head require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}") val custom_data = custom.data.asBools val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt} when (custom.ready && custom.valid) { (abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) => a := b } } } programBufferMem.zipWithIndex.foreach { case (x, i) => when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) { x := programBufferNxt(i) } } //-------------------------------------------------------------- // "Variable" ROM Generation //-------------------------------------------------------------- val goReg = Reg(Bool()) val goAbstract = WireInit(false.B) val goCustom = WireInit(false.B) val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ())) jalAbstract.setImm(ABSTRACT(cfg) - WHERETO) when (~io.dmactive){ goReg := false.B }.otherwise { when (goAbstract) { goReg := true.B }.elsewhen (hartGoingWrEn){ assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U) goReg := false.B } } class flagBundle extends Bundle { val reserved = UInt(6.W) val resume = Bool() val go = Bool() } val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} )) assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U), s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.") flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg for (component <- 0 until nComponents) { val componentSel = WireInit(component.U) flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component) } //---------------------------- // Abstract Command Decoding & Generation //---------------------------- val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields())) /** real COMMAND*/ val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields())) // TODO: Quick Access class GeneratedI extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedS extends Bundle { val immhi = UInt(7.W) val rs2 = UInt(5.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val immlo = UInt(5.W) val opcode = UInt(7.W) } class GeneratedCSR extends Bundle { val imm = UInt(12.W) val rs1 = UInt(5.W) val funct3 = UInt(3.W) val rd = UInt(5.W) val opcode = UInt(7.W) } class GeneratedUJ extends Bundle { val imm3 = UInt(1.W) val imm0 = UInt(10.W) val imm1 = UInt(1.W) val imm2 = UInt(8.W) val rd = UInt(5.W) val opcode = UInt(7.W) def setImm(imm: Int) : Unit = { // TODO: Check bounds of imm. require(imm % 2 == 0, "Immediate must be even for UJ encoding.") val immWire = WireInit(imm.S(21.W)) val immBits = WireInit(VecInit(immWire.asBools)) imm0 := immBits.slice(1, 1 + 10).asUInt imm1 := immBits.slice(11, 11 + 11).asUInt imm2 := immBits.slice(12, 12 + 8).asUInt imm3 := immBits.slice(20, 20 + 1).asUInt } } require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5), "Mismatch between DebugModuleParams atzero and nAbstractInstructions") val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W)))) def abstractGeneratedI(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedI()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode inst.rd := (accessRegisterCommandReg.regno & 0x1F.U) inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.imm := offset.U inst.asUInt } def abstractGeneratedS(cfg: DebugModuleParams): UInt = { val inst = Wire(new GeneratedS()) val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode inst.immlo := (offset & 0x1F).U inst.funct3 := accessRegisterCommandReg.size inst.rs1 := base inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U) inst.immhi := (offset >> 5).U inst.asUInt } def abstractGeneratedCSR: UInt = { val inst = Wire(new GeneratedCSR()) val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR())) inst.imm := CSRs.dscratch1.U inst.rs1 := base inst.rd := base inst.asUInt } val nop = Wire(new GeneratedI()) nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI()) nop.rd := 0.U nop.rs1 := 0.U nop.imm := 0.U val isa = Wire(new GeneratedI()) isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI()) isa.rd := 0.U isa.rs1 := 0.U isa.imm := 0.U when (goAbstract) { if (cfg.nAbstractInstructions == 2) { // ABSTRACT(0): Transfer: LW or SW, else NOP // ABSTRACT(1): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } else { // Entry: All regs in GPRs, dscratch1=offset 0x800 in DM // ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64) // ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP // ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0 // ABSTRACT(4): Postexec: NOP else EBREAK abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt) abstractGeneratedMem(1) := abstractGeneratedCSR abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer, Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)), nop.asUInt ) abstractGeneratedMem(3) := abstractGeneratedCSR abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec, nop.asUInt, Instructions.EBREAK.value.U) } } //-------------------------------------------------------------- // Drive Custom Access //-------------------------------------------------------------- if (needCustom) { val (custom, customP) = customNode.in.head custom.addr := accessRegisterCommandReg.regno custom.valid := goCustom } //-------------------------------------------------------------- // Hart Bus Access //-------------------------------------------------------------- tlNode.regmap( // This memory is writable. HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, "debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil}, WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))), ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}), FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), if (nComponents == 1) { Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) } } else { flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))} }), ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset. when (~io.dmactive){ abstractDataMem.foreach {x => x := 0.U} programBufferMem.foreach {x => x := 0.U} } //-------------------------------------------------------------- // Abstract Command State Machine //-------------------------------------------------------------- object CtrlState extends scala.Enumeration { type CtrlState = Value val Waiting, CheckGenerate, Exec, Custom = Value def apply( t : Value) : UInt = { t.id.U(log2Up(values.size).W) } } import CtrlState._ // This is not an initialization! val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting))) val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg) val ctrlStateNxt = WireInit(ctrlStateReg) //------------------------ // DMI Register Control and Status abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting)) ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting)) dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting)) dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting)) errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) || (autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) || (COMMANDWrEnMaybe && ~COMMANDWrEnLegal) || (dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) || (dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal) // TODO: Maybe Quick Access val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister val commandRegIsUnsupported = WireInit(true.B) val commandRegBadHaltResume = WireInit(false.B) // We only support abstract commands for GPRs and any custom registers, if specified. val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U) val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize val accessRegIsCustom = if (needCustom) { val (custom, customP) = customNode.in.head customP.addrs.foldLeft(false.B){ (result, current) => result || (current.U === accessRegisterCommandReg.regno)} } else false.B when (commandRegIsAccessRegister) { when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) { commandRegIsUnsupported := false.B }.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) { commandRegIsUnsupported := false.B commandRegBadHaltResume := ~hartHalted } } val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U) //------------------------ // Variable ROM STATE MACHINE // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ when (wrAccessRegisterCommand || regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. errorUnsupported := true.B }.elsewhen (autoexec && commandRegIsUnsupported) { errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. // This 'commandRegIsUnsupported' is really just checking the // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) }.elsewhen (commandRegBadHaltResume){ errorHaltResume := true.B ctrlStateNxt := CtrlState(Waiting) }.otherwise { when(accessRegIsCustom) { ctrlStateNxt := CtrlState(Custom) }.otherwise { ctrlStateNxt := CtrlState(Exec) goAbstract := true.B } } }.elsewhen (ctrlStateReg === CtrlState(Exec)) { // We can't just look at 'hartHalted' here, because // hartHaltedWrEn is overloaded to mean 'got an ebreak' // which may have happened when we were already halted. when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){ ctrlStateNxt := CtrlState(Waiting) } when(hartExceptionWrEn) { assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U) ctrlStateNxt := CtrlState(Waiting) errorException := true.B } }.elsewhen (ctrlStateReg === CtrlState(Custom)) { assert(needCustom.B, "Should not be in custom state unless we need it.") goCustom := true.B val (custom, customP) = customNode.in.head when (custom.ready && custom.valid) { ctrlStateNxt := CtrlState(Waiting) } } when (~io.dmactive || ~dmAuthenticated) { ctrlStateReg := CtrlState(Waiting) }.otherwise { ctrlStateReg := ctrlStateNxt } assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)), "Unexpected EXCEPTION write: should only get it in Debug Module EXEC state") } } // Wrapper around TL Debug Module Inner and an Async DMI Sink interface. // Handles the synchronization of dmactive, which is used as a synchronous reset // inside the Inner block. // Also is the Sink side of hartsel & resumereq fields of DMCONTROL. class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{ val cfg = p(DebugModuleKey).get val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes)) val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node // Require that there are no registers in TL interface, so that spurious // processor accesses to the DM don't need to enable the clock. We don't // require this property of the SBA, because the debugger is responsible for // raising dmactive (hence enabling the clock) during these transactions. require(dmInner.tlNode.concurrency == 0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { // Clock/reset domains: // debug_clock / debug_reset = Debug inner domain // tl_clock / tl_reset = tilelink domain (External: clock / reset) // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) // These are all asynchronous and come from Outer /** reset signal for DM */ val dmactive = Input(Bool()) /** conrol signals for Inner * * generated in Outer */ val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))) // This comes from tlClk domain. /** debug available status */ val debugUnavail = Input(Vec(getNComponents(), Bool())) /** debug interruption*/ val hgDebugInt = Output(Vec(getNComponents(), Bool())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(getNComponents(), Bool())) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) val rf_reset = IO(Input(Reset())) // RF transform childClock := io.debug_clock childReset := io.debug_reset override def provideImplicitClockToLazyChildren = true val dmactive_synced = withClockAndReset(childClock, childReset) { val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync")) dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.dmactive := dmactive_synced dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl) dmInner.module.io.debugUnavail := io.debugUnavail io.hgDebugInt := dmInner.module.io.hgDebugInt io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} dmactive_synced } } } /** Create a version of the TLDebugModule which includes a synchronization interface * internally for the DMI. This is no longer optional outside of this module * because the Clock must run when tl_clock isn't running or tl_reset is asserted. */ class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule { val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){ override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val attach = Map( "debug-attach" -> ( (if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++ (if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++ (if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++ (if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq()))) Description(name, mapping ++ attach) } } val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p)) val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p)) val node = dmInner.tlNode val intnode = dmOuter.intnode val apbNodeOpt = dmOuter.apbNodeOpt dmInner.dmiNode := dmOuter.dmiInnerNode lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val nComponents = dmOuter.dmOuter.intnode.edges.out.size // Clock/reset domains: // tl_clock / tl_reset = tilelink domain // debug_clock / debug_reset = Inner debug (synchronous to tl_clock) // apb_clock / apb_reset = Outer debug with APB // dmiClock / dmiReset = Outer debug without APB // val io = IO(new Bundle { val debug_clock = Input(Clock()) val debug_reset = Input(Reset()) val tl_clock = Input(Clock()) val tl_reset = Input(Reset()) /** Debug control signals generated in Outer */ val ctrl = new DebugCtrlBundle(nComponents) /** Debug Module Interface bewteen DM and DTM * * The DTM provides access to one or more Debug Modules (DMs) using DMI */ val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO())) val apb_clock = p(ExportDebug).apb.option(Input(Clock())) val apb_reset = p(ExportDebug).apb.option(Input(Reset())) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) /** vector to indicate which hart is in reset * * dm receives it from core and sends it to Inner */ val hartIsInReset = Input(Vec(nComponents, Bool())) /** hart reset request generated by hartreset-logic in Outer */ val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool()))) /** Debug Authentication signals from core */ val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO()) }) childClock := io.tl_clock childReset := io.tl_reset override def provideImplicitClockToLazyChildren = true dmOuter.module.io.dmi.foreach { dmOuterDMI => dmOuterDMI <> io.dmi.get.dmi dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock dmOuter.module.rf_reset := io.dmi.get.dmiReset } (io.apb_clock zip io.apb_reset) foreach { case (c, r) => dmOuter.module.io.dmi_reset := r dmOuter.module.io.dmi_clock := c dmOuter.module.rf_reset := r } dmInner.module.rf_reset := io.debug_reset dmInner.module.io.debug_clock := io.debug_clock dmInner.module.io.debug_reset := io.debug_reset dmInner.module.io.tl_clock := io.tl_clock dmInner.module.io.tl_reset := io.tl_reset dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt io.ctrl <> dmOuter.module.io.ctrl io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}} dmInner.module.io.hartIsInReset := io.hartIsInReset io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}} io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated } io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}} } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLDebugModuleOuterAsync( // @[Debug.scala:709:9] output [2:0] auto_asource_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_asource_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_asource_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_asource_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_asource_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_asource_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_asource_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_asource_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_asource_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_asource_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_asource_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_asource_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_asource_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_asource_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_asource_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_asource_out_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] output auto_int_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input io_dmi_clock, // @[Debug.scala:713:16] input io_dmi_reset, // @[Debug.scala:713:16] output io_dmi_req_ready, // @[Debug.scala:713:16] input io_dmi_req_valid, // @[Debug.scala:713:16] input [6:0] io_dmi_req_bits_addr, // @[Debug.scala:713:16] input [31:0] io_dmi_req_bits_data, // @[Debug.scala:713:16] input [1:0] io_dmi_req_bits_op, // @[Debug.scala:713:16] input io_dmi_resp_ready, // @[Debug.scala:713:16] output io_dmi_resp_valid, // @[Debug.scala:713:16] output [31:0] io_dmi_resp_bits_data, // @[Debug.scala:713:16] output [1:0] io_dmi_resp_bits_resp, // @[Debug.scala:713:16] output io_ctrl_ndreset, // @[Debug.scala:713:16] output io_ctrl_dmactive, // @[Debug.scala:713:16] input io_ctrl_dmactiveAck, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_resumereq, // @[Debug.scala:713:16] output [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hasel, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_0, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_1, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_2, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hamask_3, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_1, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_2, // @[Debug.scala:713:16] output io_innerCtrl_mem_0_hrmask_3, // @[Debug.scala:713:16] input io_innerCtrl_ridx, // @[Debug.scala:713:16] output io_innerCtrl_widx, // @[Debug.scala:713:16] input io_innerCtrl_safe_ridx_valid, // @[Debug.scala:713:16] output io_innerCtrl_safe_widx_valid, // @[Debug.scala:713:16] output io_innerCtrl_safe_source_reset_n, // @[Debug.scala:713:16] input io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:713:16] input io_hgDebugInt_0, // @[Debug.scala:713:16] input io_hgDebugInt_1, // @[Debug.scala:713:16] input io_hgDebugInt_2, // @[Debug.scala:713:16] input io_hgDebugInt_3, // @[Debug.scala:713:16] input rf_reset // @[Debug.scala:732:22] ); wire _io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala:220:24] wire _asource_auto_in_a_ready; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_valid; // @[AsyncCrossing.scala:94:29] wire [2:0] _asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala:94:29] wire [1:0] _asource_auto_in_d_bits_param; // @[AsyncCrossing.scala:94:29] wire [1:0] _asource_auto_in_d_bits_size; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_source; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala:94:29] wire [31:0] _asource_auto_in_d_bits_data; // @[AsyncCrossing.scala:94:29] wire _asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala:94:29] wire _dmiBypass_auto_node_out_out_a_valid; // @[Debug.scala:704:29] wire [2:0] _dmiBypass_auto_node_out_out_a_bits_opcode; // @[Debug.scala:704:29] wire [8:0] _dmiBypass_auto_node_out_out_a_bits_address; // @[Debug.scala:704:29] wire [31:0] _dmiBypass_auto_node_out_out_a_bits_data; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_out_out_d_ready; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_a_ready; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_valid; // @[Debug.scala:704:29] wire [2:0] _dmiBypass_auto_node_in_in_d_bits_opcode; // @[Debug.scala:704:29] wire [1:0] _dmiBypass_auto_node_in_in_d_bits_param; // @[Debug.scala:704:29] wire [1:0] _dmiBypass_auto_node_in_in_d_bits_size; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_source; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_sink; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_denied; // @[Debug.scala:704:29] wire [31:0] _dmiBypass_auto_node_in_in_d_bits_data; // @[Debug.scala:704:29] wire _dmiBypass_auto_node_in_in_d_bits_corrupt; // @[Debug.scala:704:29] wire _dmOuter_auto_dmi_in_a_ready; // @[Debug.scala:700:27] wire _dmOuter_auto_dmi_in_d_valid; // @[Debug.scala:700:27] wire [2:0] _dmOuter_auto_dmi_in_d_bits_opcode; // @[Debug.scala:700:27] wire [31:0] _dmOuter_auto_dmi_in_d_bits_data; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_3_0; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_2_0; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_1_0; // @[Debug.scala:700:27] wire _dmOuter_auto_int_out_0_0; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_valid; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_resumereq; // @[Debug.scala:700:27] wire [9:0] _dmOuter_io_innerCtrl_bits_hartsel; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_ackhavereset; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hasel; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_0; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_1; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_2; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hamask_3; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_0; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_1; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_2; // @[Debug.scala:700:27] wire _dmOuter_io_innerCtrl_bits_hrmask_3; // @[Debug.scala:700:27] wire _dmi2tl_auto_out_a_valid; // @[Debug.scala:678:28] wire [2:0] _dmi2tl_auto_out_a_bits_opcode; // @[Debug.scala:678:28] wire [8:0] _dmi2tl_auto_out_a_bits_address; // @[Debug.scala:678:28] wire [31:0] _dmi2tl_auto_out_a_bits_data; // @[Debug.scala:678:28] wire _dmi2tl_auto_out_d_ready; // @[Debug.scala:678:28] wire _dmiXbar_auto_anon_in_a_ready; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_valid; // @[Debug.scala:675:28] wire [2:0] _dmiXbar_auto_anon_in_d_bits_opcode; // @[Debug.scala:675:28] wire [1:0] _dmiXbar_auto_anon_in_d_bits_param; // @[Debug.scala:675:28] wire [1:0] _dmiXbar_auto_anon_in_d_bits_size; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_bits_sink; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_bits_denied; // @[Debug.scala:675:28] wire [31:0] _dmiXbar_auto_anon_in_d_bits_data; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_in_d_bits_corrupt; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_1_a_valid; // @[Debug.scala:675:28] wire [2:0] _dmiXbar_auto_anon_out_1_a_bits_opcode; // @[Debug.scala:675:28] wire [6:0] _dmiXbar_auto_anon_out_1_a_bits_address; // @[Debug.scala:675:28] wire [31:0] _dmiXbar_auto_anon_out_1_a_bits_data; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_1_d_ready; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_0_a_valid; // @[Debug.scala:675:28] wire [2:0] _dmiXbar_auto_anon_out_0_a_bits_opcode; // @[Debug.scala:675:28] wire [8:0] _dmiXbar_auto_anon_out_0_a_bits_address; // @[Debug.scala:675:28] wire [31:0] _dmiXbar_auto_anon_out_0_a_bits_data; // @[Debug.scala:675:28] wire _dmiXbar_auto_anon_out_0_d_ready; // @[Debug.scala:675:28] wire auto_asource_out_a_ridx_0 = auto_asource_out_a_ridx; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_ridx_valid_0 = auto_asource_out_a_safe_ridx_valid; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_sink_reset_n_0 = auto_asource_out_a_safe_sink_reset_n; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_d_mem_0_opcode_0 = auto_asource_out_d_mem_0_opcode; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_d_mem_0_size_0 = auto_asource_out_d_mem_0_size; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_source_0 = auto_asource_out_d_mem_0_source; // @[Debug.scala:709:9] wire [31:0] auto_asource_out_d_mem_0_data_0 = auto_asource_out_d_mem_0_data; // @[Debug.scala:709:9] wire auto_asource_out_d_widx_0 = auto_asource_out_d_widx; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_widx_valid_0 = auto_asource_out_d_safe_widx_valid; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_source_reset_n_0 = auto_asource_out_d_safe_source_reset_n; // @[Debug.scala:709:9] wire io_dmi_clock_0 = io_dmi_clock; // @[Debug.scala:709:9] wire io_dmi_reset_0 = io_dmi_reset; // @[Debug.scala:709:9] wire io_dmi_req_valid_0 = io_dmi_req_valid; // @[Debug.scala:709:9] wire [6:0] io_dmi_req_bits_addr_0 = io_dmi_req_bits_addr; // @[Debug.scala:709:9] wire [31:0] io_dmi_req_bits_data_0 = io_dmi_req_bits_data; // @[Debug.scala:709:9] wire [1:0] io_dmi_req_bits_op_0 = io_dmi_req_bits_op; // @[Debug.scala:709:9] wire io_dmi_resp_ready_0 = io_dmi_resp_ready; // @[Debug.scala:709:9] wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck; // @[Debug.scala:709:9] wire io_innerCtrl_ridx_0 = io_innerCtrl_ridx; // @[Debug.scala:709:9] wire io_innerCtrl_safe_ridx_valid_0 = io_innerCtrl_safe_ridx_valid; // @[Debug.scala:709:9] wire io_innerCtrl_safe_sink_reset_n_0 = io_innerCtrl_safe_sink_reset_n; // @[Debug.scala:709:9] wire io_hgDebugInt_0_0 = io_hgDebugInt_0; // @[Debug.scala:709:9] wire io_hgDebugInt_1_0 = io_hgDebugInt_1; // @[Debug.scala:709:9] wire io_hgDebugInt_2_0 = io_hgDebugInt_2; // @[Debug.scala:709:9] wire io_hgDebugInt_3_0 = io_hgDebugInt_3; // @[Debug.scala:709:9] wire auto_asource_out_a_mem_0_source = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_a_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_mem_0_source = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_ridx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_widx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_widx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_mem_0_source = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_ridx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_widx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_widx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_sink = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_denied = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_d_mem_0_corrupt = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_mem_0_sink = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_ridx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_widx = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_ridx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_widx_valid = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_source_reset_n = 1'h0; // @[Debug.scala:709:9] wire auto_asource_out_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_0 = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_1 = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_2 = 1'h0; // @[Debug.scala:709:9] wire io_ctrl_debugUnavail_3 = 1'h0; // @[Debug.scala:709:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire [31:0] auto_asource_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:94:29] wire [31:0] auto_asource_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:94:29] wire [3:0] auto_asource_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:94:29] wire [8:0] auto_asource_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:94:29] wire [8:0] auto_asource_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:94:29] wire [1:0] auto_asource_out_b_mem_0_param = 2'h0; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_b_mem_0_size = 2'h0; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_c_mem_0_size = 2'h0; // @[Debug.scala:709:9] wire [1:0] auto_asource_out_d_mem_0_param = 2'h0; // @[Debug.scala:709:9] wire [3:0] auto_asource_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:94:29] wire [1:0] auto_asource_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:94:29] wire [2:0] auto_asource_out_a_mem_0_param = 3'h0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_b_mem_0_opcode = 3'h0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_c_mem_0_opcode = 3'h0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_c_mem_0_param = 3'h0; // @[Debug.scala:709:9] wire x1_intnodeOut_2_sync_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_1_sync_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_sync_0; // @[MixedNode.scala:542:17] wire intnodeOut_sync_0; // @[MixedNode.scala:542:17] wire childClock = io_dmi_clock_0; // @[Debug.scala:709:9] wire childReset = io_dmi_reset_0; // @[Debug.scala:709:9] wire [2:0] auto_asource_out_a_mem_0_opcode_0; // @[Debug.scala:709:9] wire [8:0] auto_asource_out_a_mem_0_address_0; // @[Debug.scala:709:9] wire [31:0] auto_asource_out_a_mem_0_data_0; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_widx_valid_0; // @[Debug.scala:709:9] wire auto_asource_out_a_safe_source_reset_n_0; // @[Debug.scala:709:9] wire auto_asource_out_a_widx_0; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_ridx_valid_0; // @[Debug.scala:709:9] wire auto_asource_out_d_safe_sink_reset_n_0; // @[Debug.scala:709:9] wire auto_asource_out_d_ridx_0; // @[Debug.scala:709:9] wire auto_int_out_3_sync_0_0; // @[Debug.scala:709:9] wire auto_int_out_2_sync_0_0; // @[Debug.scala:709:9] wire auto_int_out_1_sync_0_0; // @[Debug.scala:709:9] wire auto_int_out_0_sync_0_0; // @[Debug.scala:709:9] wire io_dmi_req_ready_0; // @[Debug.scala:709:9] wire [31:0] io_dmi_resp_bits_data_0; // @[Debug.scala:709:9] wire [1:0] io_dmi_resp_bits_resp_0; // @[Debug.scala:709:9] wire io_dmi_resp_valid_0; // @[Debug.scala:709:9] wire io_ctrl_ndreset_0; // @[Debug.scala:709:9] wire io_ctrl_dmactive_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_0_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_1_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_2_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hamask_3_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_0_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_1_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_2_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hrmask_3_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_resumereq_0; // @[Debug.scala:709:9] wire [9:0] io_innerCtrl_mem_0_hartsel_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_ackhavereset_0; // @[Debug.scala:709:9] wire io_innerCtrl_mem_0_hasel_0; // @[Debug.scala:709:9] wire io_innerCtrl_safe_widx_valid_0; // @[Debug.scala:709:9] wire io_innerCtrl_safe_source_reset_n_0; // @[Debug.scala:709:9] wire io_innerCtrl_widx_0; // @[Debug.scala:709:9] wire intnodeIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_0_sync_0_0 = intnodeOut_sync_0; // @[Debug.scala:709:9] wire x1_intnodeIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_1_sync_0_0 = x1_intnodeOut_sync_0; // @[Debug.scala:709:9] wire x1_intnodeIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_2_sync_0_0 = x1_intnodeOut_1_sync_0; // @[Debug.scala:709:9] wire x1_intnodeIn_2_sync_0; // @[MixedNode.scala:551:17] assign auto_int_out_3_sync_0_0 = x1_intnodeOut_2_sync_0; // @[Debug.scala:709:9] assign intnodeOut_sync_0 = intnodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign x1_intnodeOut_sync_0 = x1_intnodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign x1_intnodeOut_1_sync_0 = x1_intnodeIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign x1_intnodeOut_2_sync_0 = x1_intnodeIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17] wire dmactiveAck; // @[ShiftReg.scala:48:24] wire _dmiBypass_io_bypass_T = ~io_ctrl_dmactive_0; // @[Debug.scala:709:9, :742:37] wire _dmiBypass_io_bypass_T_1 = ~dmactiveAck; // @[ShiftReg.scala:48:24] wire _dmiBypass_io_bypass_T_2 = _dmiBypass_io_bypass_T | _dmiBypass_io_bypass_T_1; // @[Debug.scala:742:{37,55,57}] TLXbar_dmixbar_i1_o2_a9d32s1k1z2u dmiXbar ( // @[Debug.scala:675:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_dmiXbar_auto_anon_in_a_ready), .auto_anon_in_a_valid (_dmi2tl_auto_out_a_valid), // @[Debug.scala:678:28] .auto_anon_in_a_bits_opcode (_dmi2tl_auto_out_a_bits_opcode), // @[Debug.scala:678:28] .auto_anon_in_a_bits_address (_dmi2tl_auto_out_a_bits_address), // @[Debug.scala:678:28] .auto_anon_in_a_bits_data (_dmi2tl_auto_out_a_bits_data), // @[Debug.scala:678:28] .auto_anon_in_d_ready (_dmi2tl_auto_out_d_ready), // @[Debug.scala:678:28] .auto_anon_in_d_valid (_dmiXbar_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_dmiXbar_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (_dmiXbar_auto_anon_in_d_bits_param), .auto_anon_in_d_bits_size (_dmiXbar_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_sink (_dmiXbar_auto_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (_dmiXbar_auto_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (_dmiXbar_auto_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (_dmiXbar_auto_anon_in_d_bits_corrupt), .auto_anon_out_1_a_ready (_dmOuter_auto_dmi_in_a_ready), // @[Debug.scala:700:27] .auto_anon_out_1_a_valid (_dmiXbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_dmiXbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_address (_dmiXbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_data (_dmiXbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_d_ready (_dmiXbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_dmOuter_auto_dmi_in_d_valid), // @[Debug.scala:700:27] .auto_anon_out_1_d_bits_opcode (_dmOuter_auto_dmi_in_d_bits_opcode), // @[Debug.scala:700:27] .auto_anon_out_1_d_bits_data (_dmOuter_auto_dmi_in_d_bits_data), // @[Debug.scala:700:27] .auto_anon_out_0_a_ready (_dmiBypass_auto_node_in_in_a_ready), // @[Debug.scala:704:29] .auto_anon_out_0_a_valid (_dmiXbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_dmiXbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_address (_dmiXbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_data (_dmiXbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_d_ready (_dmiXbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_dmiBypass_auto_node_in_in_d_valid), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_opcode (_dmiBypass_auto_node_in_in_d_bits_opcode), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_param (_dmiBypass_auto_node_in_in_d_bits_param), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_size (_dmiBypass_auto_node_in_in_d_bits_size), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_source (_dmiBypass_auto_node_in_in_d_bits_source), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_sink (_dmiBypass_auto_node_in_in_d_bits_sink), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_denied (_dmiBypass_auto_node_in_in_d_bits_denied), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_data (_dmiBypass_auto_node_in_in_d_bits_data), // @[Debug.scala:704:29] .auto_anon_out_0_d_bits_corrupt (_dmiBypass_auto_node_in_in_d_bits_corrupt) // @[Debug.scala:704:29] ); // @[Debug.scala:675:28] DMIToTL dmi2tl ( // @[Debug.scala:678:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_out_a_ready (_dmiXbar_auto_anon_in_a_ready), // @[Debug.scala:675:28] .auto_out_a_valid (_dmi2tl_auto_out_a_valid), .auto_out_a_bits_opcode (_dmi2tl_auto_out_a_bits_opcode), .auto_out_a_bits_address (_dmi2tl_auto_out_a_bits_address), .auto_out_a_bits_data (_dmi2tl_auto_out_a_bits_data), .auto_out_d_ready (_dmi2tl_auto_out_d_ready), .auto_out_d_valid (_dmiXbar_auto_anon_in_d_valid), // @[Debug.scala:675:28] .auto_out_d_bits_opcode (_dmiXbar_auto_anon_in_d_bits_opcode), // @[Debug.scala:675:28] .auto_out_d_bits_param (_dmiXbar_auto_anon_in_d_bits_param), // @[Debug.scala:675:28] .auto_out_d_bits_size (_dmiXbar_auto_anon_in_d_bits_size), // @[Debug.scala:675:28] .auto_out_d_bits_sink (_dmiXbar_auto_anon_in_d_bits_sink), // @[Debug.scala:675:28] .auto_out_d_bits_denied (_dmiXbar_auto_anon_in_d_bits_denied), // @[Debug.scala:675:28] .auto_out_d_bits_data (_dmiXbar_auto_anon_in_d_bits_data), // @[Debug.scala:675:28] .auto_out_d_bits_corrupt (_dmiXbar_auto_anon_in_d_bits_corrupt), // @[Debug.scala:675:28] .io_dmi_req_ready (io_dmi_req_ready_0), .io_dmi_req_valid (io_dmi_req_valid_0), // @[Debug.scala:709:9] .io_dmi_req_bits_addr (io_dmi_req_bits_addr_0), // @[Debug.scala:709:9] .io_dmi_req_bits_data (io_dmi_req_bits_data_0), // @[Debug.scala:709:9] .io_dmi_req_bits_op (io_dmi_req_bits_op_0), // @[Debug.scala:709:9] .io_dmi_resp_ready (io_dmi_resp_ready_0), // @[Debug.scala:709:9] .io_dmi_resp_valid (io_dmi_resp_valid_0), .io_dmi_resp_bits_data (io_dmi_resp_bits_data_0), .io_dmi_resp_bits_resp (io_dmi_resp_bits_resp_0) ); // @[Debug.scala:678:28] TLDebugModuleOuter dmOuter ( // @[Debug.scala:700:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_dmi_in_a_ready (_dmOuter_auto_dmi_in_a_ready), .auto_dmi_in_a_valid (_dmiXbar_auto_anon_out_1_a_valid), // @[Debug.scala:675:28] .auto_dmi_in_a_bits_opcode (_dmiXbar_auto_anon_out_1_a_bits_opcode), // @[Debug.scala:675:28] .auto_dmi_in_a_bits_address (_dmiXbar_auto_anon_out_1_a_bits_address), // @[Debug.scala:675:28] .auto_dmi_in_a_bits_data (_dmiXbar_auto_anon_out_1_a_bits_data), // @[Debug.scala:675:28] .auto_dmi_in_d_ready (_dmiXbar_auto_anon_out_1_d_ready), // @[Debug.scala:675:28] .auto_dmi_in_d_valid (_dmOuter_auto_dmi_in_d_valid), .auto_dmi_in_d_bits_opcode (_dmOuter_auto_dmi_in_d_bits_opcode), .auto_dmi_in_d_bits_data (_dmOuter_auto_dmi_in_d_bits_data), .auto_int_out_3_0 (_dmOuter_auto_int_out_3_0), .auto_int_out_2_0 (_dmOuter_auto_int_out_2_0), .auto_int_out_1_0 (_dmOuter_auto_int_out_1_0), .auto_int_out_0_0 (_dmOuter_auto_int_out_0_0), .io_ctrl_ndreset (io_ctrl_ndreset_0), .io_ctrl_dmactive (io_ctrl_dmactive_0), .io_ctrl_dmactiveAck (dmactiveAck), // @[ShiftReg.scala:48:24] .io_innerCtrl_ready (_io_innerCtrl_source_io_enq_ready), // @[AsyncQueue.scala:220:24] .io_innerCtrl_valid (_dmOuter_io_innerCtrl_valid), .io_innerCtrl_bits_resumereq (_dmOuter_io_innerCtrl_bits_resumereq), .io_innerCtrl_bits_hartsel (_dmOuter_io_innerCtrl_bits_hartsel), .io_innerCtrl_bits_ackhavereset (_dmOuter_io_innerCtrl_bits_ackhavereset), .io_innerCtrl_bits_hasel (_dmOuter_io_innerCtrl_bits_hasel), .io_innerCtrl_bits_hamask_0 (_dmOuter_io_innerCtrl_bits_hamask_0), .io_innerCtrl_bits_hamask_1 (_dmOuter_io_innerCtrl_bits_hamask_1), .io_innerCtrl_bits_hamask_2 (_dmOuter_io_innerCtrl_bits_hamask_2), .io_innerCtrl_bits_hamask_3 (_dmOuter_io_innerCtrl_bits_hamask_3), .io_innerCtrl_bits_hrmask_0 (_dmOuter_io_innerCtrl_bits_hrmask_0), .io_innerCtrl_bits_hrmask_1 (_dmOuter_io_innerCtrl_bits_hrmask_1), .io_innerCtrl_bits_hrmask_2 (_dmOuter_io_innerCtrl_bits_hrmask_2), .io_innerCtrl_bits_hrmask_3 (_dmOuter_io_innerCtrl_bits_hrmask_3), .io_hgDebugInt_0 (io_hgDebugInt_0_0), // @[Debug.scala:709:9] .io_hgDebugInt_1 (io_hgDebugInt_1_0), // @[Debug.scala:709:9] .io_hgDebugInt_2 (io_hgDebugInt_2_0), // @[Debug.scala:709:9] .io_hgDebugInt_3 (io_hgDebugInt_3_0) // @[Debug.scala:709:9] ); // @[Debug.scala:700:27] IntSyncCrossingSource_n4x1_Registered intsource ( // @[Crossing.scala:29:31] .auto_in_3_0 (_dmOuter_auto_int_out_3_0), // @[Debug.scala:700:27] .auto_in_2_0 (_dmOuter_auto_int_out_2_0), // @[Debug.scala:700:27] .auto_in_1_0 (_dmOuter_auto_int_out_1_0), // @[Debug.scala:700:27] .auto_in_0_0 (_dmOuter_auto_int_out_0_0), // @[Debug.scala:700:27] .auto_out_3_sync_0 (x1_intnodeIn_2_sync_0), .auto_out_2_sync_0 (x1_intnodeIn_1_sync_0), .auto_out_1_sync_0 (x1_intnodeIn_sync_0), .auto_out_0_sync_0 (intnodeIn_sync_0) ); // @[Crossing.scala:29:31] TLBusBypass dmiBypass ( // @[Debug.scala:704:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_node_out_out_a_ready (_asource_auto_in_a_ready), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_a_valid (_dmiBypass_auto_node_out_out_a_valid), .auto_node_out_out_a_bits_opcode (_dmiBypass_auto_node_out_out_a_bits_opcode), .auto_node_out_out_a_bits_address (_dmiBypass_auto_node_out_out_a_bits_address), .auto_node_out_out_a_bits_data (_dmiBypass_auto_node_out_out_a_bits_data), .auto_node_out_out_d_ready (_dmiBypass_auto_node_out_out_d_ready), .auto_node_out_out_d_valid (_asource_auto_in_d_valid), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_opcode (_asource_auto_in_d_bits_opcode), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_param (_asource_auto_in_d_bits_param), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_size (_asource_auto_in_d_bits_size), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_source (_asource_auto_in_d_bits_source), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_sink (_asource_auto_in_d_bits_sink), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_denied (_asource_auto_in_d_bits_denied), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_data (_asource_auto_in_d_bits_data), // @[AsyncCrossing.scala:94:29] .auto_node_out_out_d_bits_corrupt (_asource_auto_in_d_bits_corrupt), // @[AsyncCrossing.scala:94:29] .auto_node_in_in_a_ready (_dmiBypass_auto_node_in_in_a_ready), .auto_node_in_in_a_valid (_dmiXbar_auto_anon_out_0_a_valid), // @[Debug.scala:675:28] .auto_node_in_in_a_bits_opcode (_dmiXbar_auto_anon_out_0_a_bits_opcode), // @[Debug.scala:675:28] .auto_node_in_in_a_bits_address (_dmiXbar_auto_anon_out_0_a_bits_address), // @[Debug.scala:675:28] .auto_node_in_in_a_bits_data (_dmiXbar_auto_anon_out_0_a_bits_data), // @[Debug.scala:675:28] .auto_node_in_in_d_ready (_dmiXbar_auto_anon_out_0_d_ready), // @[Debug.scala:675:28] .auto_node_in_in_d_valid (_dmiBypass_auto_node_in_in_d_valid), .auto_node_in_in_d_bits_opcode (_dmiBypass_auto_node_in_in_d_bits_opcode), .auto_node_in_in_d_bits_param (_dmiBypass_auto_node_in_in_d_bits_param), .auto_node_in_in_d_bits_size (_dmiBypass_auto_node_in_in_d_bits_size), .auto_node_in_in_d_bits_source (_dmiBypass_auto_node_in_in_d_bits_source), .auto_node_in_in_d_bits_sink (_dmiBypass_auto_node_in_in_d_bits_sink), .auto_node_in_in_d_bits_denied (_dmiBypass_auto_node_in_in_d_bits_denied), .auto_node_in_in_d_bits_data (_dmiBypass_auto_node_in_in_d_bits_data), .auto_node_in_in_d_bits_corrupt (_dmiBypass_auto_node_in_in_d_bits_corrupt), .io_bypass (_dmiBypass_io_bypass_T_2) // @[Debug.scala:742:55] ); // @[Debug.scala:704:29] TLAsyncCrossingSource_a9d32s1k1z2u asource ( // @[AsyncCrossing.scala:94:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_asource_auto_in_a_ready), .auto_in_a_valid (_dmiBypass_auto_node_out_out_a_valid), // @[Debug.scala:704:29] .auto_in_a_bits_opcode (_dmiBypass_auto_node_out_out_a_bits_opcode), // @[Debug.scala:704:29] .auto_in_a_bits_address (_dmiBypass_auto_node_out_out_a_bits_address), // @[Debug.scala:704:29] .auto_in_a_bits_data (_dmiBypass_auto_node_out_out_a_bits_data), // @[Debug.scala:704:29] .auto_in_d_ready (_dmiBypass_auto_node_out_out_d_ready), // @[Debug.scala:704:29] .auto_in_d_valid (_asource_auto_in_d_valid), .auto_in_d_bits_opcode (_asource_auto_in_d_bits_opcode), .auto_in_d_bits_param (_asource_auto_in_d_bits_param), .auto_in_d_bits_size (_asource_auto_in_d_bits_size), .auto_in_d_bits_source (_asource_auto_in_d_bits_source), .auto_in_d_bits_sink (_asource_auto_in_d_bits_sink), .auto_in_d_bits_denied (_asource_auto_in_d_bits_denied), .auto_in_d_bits_data (_asource_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_asource_auto_in_d_bits_corrupt), .auto_out_a_mem_0_opcode (auto_asource_out_a_mem_0_opcode_0), .auto_out_a_mem_0_address (auto_asource_out_a_mem_0_address_0), .auto_out_a_mem_0_data (auto_asource_out_a_mem_0_data_0), .auto_out_a_ridx (auto_asource_out_a_ridx_0), // @[Debug.scala:709:9] .auto_out_a_widx (auto_asource_out_a_widx_0), .auto_out_a_safe_ridx_valid (auto_asource_out_a_safe_ridx_valid_0), // @[Debug.scala:709:9] .auto_out_a_safe_widx_valid (auto_asource_out_a_safe_widx_valid_0), .auto_out_a_safe_source_reset_n (auto_asource_out_a_safe_source_reset_n_0), .auto_out_a_safe_sink_reset_n (auto_asource_out_a_safe_sink_reset_n_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_opcode (auto_asource_out_d_mem_0_opcode_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_size (auto_asource_out_d_mem_0_size_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_source (auto_asource_out_d_mem_0_source_0), // @[Debug.scala:709:9] .auto_out_d_mem_0_data (auto_asource_out_d_mem_0_data_0), // @[Debug.scala:709:9] .auto_out_d_ridx (auto_asource_out_d_ridx_0), .auto_out_d_widx (auto_asource_out_d_widx_0), // @[Debug.scala:709:9] .auto_out_d_safe_ridx_valid (auto_asource_out_d_safe_ridx_valid_0), .auto_out_d_safe_widx_valid (auto_asource_out_d_safe_widx_valid_0), // @[Debug.scala:709:9] .auto_out_d_safe_source_reset_n (auto_asource_out_d_safe_source_reset_n_0), // @[Debug.scala:709:9] .auto_out_d_safe_sink_reset_n (auto_asource_out_d_safe_sink_reset_n_0) ); // @[AsyncCrossing.scala:94:29] AsyncResetSynchronizerShiftReg_w1_d3_i0_10 dmactiveAck_dmactiveAckSync ( // @[ShiftReg.scala:45:23] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_d (io_ctrl_dmactiveAck_0), // @[Debug.scala:709:9] .io_q (dmactiveAck) ); // @[ShiftReg.scala:45:23] AsyncQueueSource_DebugInternalBundle io_innerCtrl_source ( // @[AsyncQueue.scala:220:24] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .io_enq_ready (_io_innerCtrl_source_io_enq_ready), .io_enq_valid (_dmOuter_io_innerCtrl_valid), // @[Debug.scala:700:27] .io_enq_bits_resumereq (_dmOuter_io_innerCtrl_bits_resumereq), // @[Debug.scala:700:27] .io_enq_bits_hartsel (_dmOuter_io_innerCtrl_bits_hartsel), // @[Debug.scala:700:27] .io_enq_bits_ackhavereset (_dmOuter_io_innerCtrl_bits_ackhavereset), // @[Debug.scala:700:27] .io_enq_bits_hasel (_dmOuter_io_innerCtrl_bits_hasel), // @[Debug.scala:700:27] .io_enq_bits_hamask_0 (_dmOuter_io_innerCtrl_bits_hamask_0), // @[Debug.scala:700:27] .io_enq_bits_hamask_1 (_dmOuter_io_innerCtrl_bits_hamask_1), // @[Debug.scala:700:27] .io_enq_bits_hamask_2 (_dmOuter_io_innerCtrl_bits_hamask_2), // @[Debug.scala:700:27] .io_enq_bits_hamask_3 (_dmOuter_io_innerCtrl_bits_hamask_3), // @[Debug.scala:700:27] .io_enq_bits_hrmask_0 (_dmOuter_io_innerCtrl_bits_hrmask_0), // @[Debug.scala:700:27] .io_enq_bits_hrmask_1 (_dmOuter_io_innerCtrl_bits_hrmask_1), // @[Debug.scala:700:27] .io_enq_bits_hrmask_2 (_dmOuter_io_innerCtrl_bits_hrmask_2), // @[Debug.scala:700:27] .io_enq_bits_hrmask_3 (_dmOuter_io_innerCtrl_bits_hrmask_3), // @[Debug.scala:700:27] .io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), .io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), .io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), .io_async_mem_0_hasel (io_innerCtrl_mem_0_hasel_0), .io_async_mem_0_hamask_0 (io_innerCtrl_mem_0_hamask_0_0), .io_async_mem_0_hamask_1 (io_innerCtrl_mem_0_hamask_1_0), .io_async_mem_0_hamask_2 (io_innerCtrl_mem_0_hamask_2_0), .io_async_mem_0_hamask_3 (io_innerCtrl_mem_0_hamask_3_0), .io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), .io_async_mem_0_hrmask_1 (io_innerCtrl_mem_0_hrmask_1_0), .io_async_mem_0_hrmask_2 (io_innerCtrl_mem_0_hrmask_2_0), .io_async_mem_0_hrmask_3 (io_innerCtrl_mem_0_hrmask_3_0), .io_async_ridx (io_innerCtrl_ridx_0), // @[Debug.scala:709:9] .io_async_widx (io_innerCtrl_widx_0), .io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0), // @[Debug.scala:709:9] .io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), .io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), .io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0) // @[Debug.scala:709:9] ); // @[AsyncQueue.scala:220:24] assign auto_asource_out_a_mem_0_opcode = auto_asource_out_a_mem_0_opcode_0; // @[Debug.scala:709:9] assign auto_asource_out_a_mem_0_address = auto_asource_out_a_mem_0_address_0; // @[Debug.scala:709:9] assign auto_asource_out_a_mem_0_data = auto_asource_out_a_mem_0_data_0; // @[Debug.scala:709:9] assign auto_asource_out_a_widx = auto_asource_out_a_widx_0; // @[Debug.scala:709:9] assign auto_asource_out_a_safe_widx_valid = auto_asource_out_a_safe_widx_valid_0; // @[Debug.scala:709:9] assign auto_asource_out_a_safe_source_reset_n = auto_asource_out_a_safe_source_reset_n_0; // @[Debug.scala:709:9] assign auto_asource_out_d_ridx = auto_asource_out_d_ridx_0; // @[Debug.scala:709:9] assign auto_asource_out_d_safe_ridx_valid = auto_asource_out_d_safe_ridx_valid_0; // @[Debug.scala:709:9] assign auto_asource_out_d_safe_sink_reset_n = auto_asource_out_d_safe_sink_reset_n_0; // @[Debug.scala:709:9] assign auto_int_out_3_sync_0 = auto_int_out_3_sync_0_0; // @[Debug.scala:709:9] assign auto_int_out_2_sync_0 = auto_int_out_2_sync_0_0; // @[Debug.scala:709:9] assign auto_int_out_1_sync_0 = auto_int_out_1_sync_0_0; // @[Debug.scala:709:9] assign auto_int_out_0_sync_0 = auto_int_out_0_sync_0_0; // @[Debug.scala:709:9] assign io_dmi_req_ready = io_dmi_req_ready_0; // @[Debug.scala:709:9] assign io_dmi_resp_valid = io_dmi_resp_valid_0; // @[Debug.scala:709:9] assign io_dmi_resp_bits_data = io_dmi_resp_bits_data_0; // @[Debug.scala:709:9] assign io_dmi_resp_bits_resp = io_dmi_resp_bits_resp_0; // @[Debug.scala:709:9] assign io_ctrl_ndreset = io_ctrl_ndreset_0; // @[Debug.scala:709:9] assign io_ctrl_dmactive = io_ctrl_dmactive_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_resumereq = io_innerCtrl_mem_0_resumereq_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hartsel = io_innerCtrl_mem_0_hartsel_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_ackhavereset = io_innerCtrl_mem_0_ackhavereset_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hasel = io_innerCtrl_mem_0_hasel_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_0 = io_innerCtrl_mem_0_hamask_0_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_1 = io_innerCtrl_mem_0_hamask_1_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_2 = io_innerCtrl_mem_0_hamask_2_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hamask_3 = io_innerCtrl_mem_0_hamask_3_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_0 = io_innerCtrl_mem_0_hrmask_0_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_1 = io_innerCtrl_mem_0_hrmask_1_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_2 = io_innerCtrl_mem_0_hrmask_2_0; // @[Debug.scala:709:9] assign io_innerCtrl_mem_0_hrmask_3 = io_innerCtrl_mem_0_hrmask_3_0; // @[Debug.scala:709:9] assign io_innerCtrl_widx = io_innerCtrl_widx_0; // @[Debug.scala:709:9] assign io_innerCtrl_safe_widx_valid = io_innerCtrl_safe_widx_valid_0; // @[Debug.scala:709:9] assign io_innerCtrl_safe_source_reset_n = io_innerCtrl_safe_source_reset_n_0; // @[Debug.scala:709:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLSerdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ object TLSerdesser { // This should be the standard bundle type for TLSerdesser val STANDARD_TLBUNDLE_PARAMS = TLBundleParameters( addressBits=64, dataBits=64, sourceBits=8, sinkBits=8, sizeBits=8, echoFields=Nil, requestFields=Nil, responseFields=Nil, hasBCE=true) } class SerdesDebugIO extends Bundle { val ser_busy = Output(Bool()) val des_busy = Output(Bool()) } class TLSerdesser( val flitWidth: Int, clientPortParams: Option[TLMasterPortParameters], managerPortParams: Option[TLSlavePortParameters], val bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS, nameSuffix: Option[String] = None ) (implicit p: Parameters) extends LazyModule { require (clientPortParams.isDefined || managerPortParams.isDefined) val clientNode = clientPortParams.map { c => TLClientNode(Seq(c)) } val managerNode = managerPortParams.map { m => TLManagerNode(Seq(m)) } override lazy val desiredName = (Seq("TLSerdesser") ++ nameSuffix).mkString("_") lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val ser = Vec(5, new DecoupledFlitIO(flitWidth)) val debug = new SerdesDebugIO }) val client_tl = clientNode.map(_.out(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val client_edge = clientNode.map(_.out(0)._2) val manager_tl = managerNode.map(_.in(0)._1).getOrElse(0.U.asTypeOf(new TLBundle(bundleParams))) val manager_edge = managerNode.map(_.in(0)._2) val clientParams = client_edge.map(_.bundle).getOrElse(bundleParams) val managerParams = manager_edge.map(_.bundle).getOrElse(bundleParams) val mergedParams = clientParams.union(managerParams).union(bundleParams) require(mergedParams.echoFields.isEmpty, "TLSerdesser does not support TileLink with echo fields") require(mergedParams.requestFields.isEmpty, "TLSerdesser does not support TileLink with request fields") require(mergedParams.responseFields.isEmpty, "TLSerdesser does not support TileLink with response fields") require(mergedParams == bundleParams, s"TLSerdesser is misconfigured, the combined inwards/outwards parameters cannot be serialized using the provided bundle params\n$mergedParams > $bundleParams") val out_channels = Seq( (manager_tl.e, manager_edge.map(e => Module(new TLEToBeat(e, mergedParams, nameSuffix)))), (client_tl.d, client_edge.map (e => Module(new TLDToBeat(e, mergedParams, nameSuffix)))), (manager_tl.c, manager_edge.map(e => Module(new TLCToBeat(e, mergedParams, nameSuffix)))), (client_tl.b, client_edge.map (e => Module(new TLBToBeat(e, mergedParams, nameSuffix)))), (manager_tl.a, manager_edge.map(e => Module(new TLAToBeat(e, mergedParams, nameSuffix)))) ) io.ser.map(_.out.valid := false.B) io.ser.map(_.out.bits := DontCare) val out_sers = out_channels.zipWithIndex.map { case ((c,b),i) => b.map { b => b.io.protocol <> c val ser = Module(new GenericSerializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"ser_$i") ser.io.in <> b.io.beat io.ser(i).out <> ser.io.out ser }}.flatten io.debug.ser_busy := out_sers.map(_.io.busy).orR val in_channels = Seq( (client_tl.e, Module(new TLEFromBeat(mergedParams, nameSuffix))), (manager_tl.d, Module(new TLDFromBeat(mergedParams, nameSuffix))), (client_tl.c, Module(new TLCFromBeat(mergedParams, nameSuffix))), (manager_tl.b, Module(new TLBFromBeat(mergedParams, nameSuffix))), (client_tl.a, Module(new TLAFromBeat(mergedParams, nameSuffix))) ) val in_desers = in_channels.zipWithIndex.map { case ((c,b),i) => c <> b.io.protocol val des = Module(new GenericDeserializer(b.io.beat.bits.cloneType, flitWidth)).suggestName(s"des_$i") des.io.in <> io.ser(i).in b.io.beat <> des.io.out des } io.debug.des_busy := in_desers.map(_.io.busy).orR } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_0_out_ready, // @[TLSerdes.scala:40:16] output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_2_out_ready, // @[TLSerdes.scala:40:16] output io_ser_2_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_4_out_ready, // @[TLSerdes.scala:40:16] output io_ser_4_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28] wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_4_io_busy; // @[TLSerdes.scala:69:23] wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50] wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50] wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50] wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50] wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50] wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9] wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9] wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9] wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71] wire [2:0] _out_channels_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74] wire [2:0] out_channels_0_1_bits_sink = 3'h0; // @[Bundles.scala:267:61] wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71] wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71] wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71] wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17] wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71] wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61] wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9] wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire _io_debug_ser_busy_T_1; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy; // @[TLSerdes.scala:39:9] wire io_debug_des_busy; // @[TLSerdes.scala:39:9] assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_a_valid; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71] wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71] wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71] wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71] wire client_tl_c_valid; // @[TLSerdes.scala:45:71] wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71] wire client_tl_e_valid; // @[TLSerdes.scala:45:71] wire _io_debug_ser_busy_T; // @[package.scala:81:59] assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9] wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61] wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61] wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61] wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61] wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61] wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61] wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61] wire in_channels_3_1_valid; // @[Bundles.scala:264:61] assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9] assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[2:0]; // @[TLSerdes.scala:79:28, :85:9] assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9] assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLMonitor_87 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_0_2_io_beat_bits_head) ); // @[TLSerdes.scala:59:50] TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_2_2_io_beat_bits_head) ); // @[TLSerdes.scala:61:50] TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_a_ready), .io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21] .io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_4_2_io_beat_valid), .io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_4_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail) ); // @[TLSerdes.scala:63:50] GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_0_io_in_ready), .io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50] .io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_bits_flit (io_ser_0_out_bits_flit_0) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_2_io_in_ready), .io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50] .io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_2_out_valid_0), .io_out_bits_flit (io_ser_2_out_bits_flit_0), .io_busy (_io_debug_ser_busy_T) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_4_io_in_ready), .io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50] .io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50] .io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50] .io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50] .io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_4_out_valid_0), .io_out_bits_flit (io_ser_4_out_bits_flit_0), .io_busy (_ser_4_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_e_valid), .io_protocol_bits_sink (client_tl_e_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_protocol_valid (managerNodeIn_d_valid), .io_protocol_bits_opcode (managerNodeIn_d_bits_opcode), .io_protocol_bits_param (managerNodeIn_d_bits_param), .io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source), .io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink), .io_protocol_bits_denied (managerNodeIn_d_bits_denied), .io_protocol_bits_data (managerNodeIn_d_bits_data), .io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_c_valid), .io_protocol_bits_opcode (client_tl_c_bits_opcode), .io_protocol_bits_param (client_tl_c_bits_param), .io_protocol_bits_size (client_tl_c_bits_size), .io_protocol_bits_source (client_tl_c_bits_source), .io_protocol_bits_address (client_tl_c_bits_address), .io_protocol_bits_data (client_tl_c_bits_data), .io_protocol_bits_corrupt (client_tl_c_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_3_1_valid), .io_protocol_bits_opcode (in_channels_3_1_bits_opcode), .io_protocol_bits_param (in_channels_3_1_bits_param), .io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address), .io_protocol_bits_mask (in_channels_3_1_bits_mask), .io_protocol_bits_data (in_channels_3_1_bits_data), .io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_valid (client_tl_a_valid), .io_protocol_bits_opcode (client_tl_a_bits_opcode), .io_protocol_bits_param (client_tl_a_bits_param), .io_protocol_bits_size (client_tl_a_bits_size), .io_protocol_bits_source (client_tl_a_bits_source), .io_protocol_bits_address (client_tl_a_bits_address), .io_protocol_bits_mask (client_tl_a_bits_mask), .io_protocol_bits_data (client_tl_a_bits_data), .io_protocol_bits_corrupt (client_tl_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }

module IssueSlot_56( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to the following Chisel files. File IngressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class IngressUnit( ingressNodeId: Int, cParam: IngressChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean, ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits))) } val io = IO(new IngressUnitIO) val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2, flow=combineRCVA)) assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR)) route_buffer.io.enq.bits.head := io.in.bits.head route_buffer.io.enq.bits.tail := io.in.bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { route_buffer.io.enq.bits.flow := DontCare } else { route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U route_buffer.io.enq.bits.flow.egress_node := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNode.U) ) route_buffer.io.enq.bits.flow.egress_node_id := Mux1H( flows.map(_.egressId.U === io.in.bits.egress_id), flows.map(_.egressNodeId.U) ) } route_buffer.io.enq.bits.payload := io.in.bits.payload route_buffer.io.enq.bits.virt_channel_id := DontCare io.router_req.bits.src_virt_id := 0.U io.router_req.bits.flow := route_buffer.io.enq.bits.flow val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U route_buffer.io.enq.valid := io.in.valid && ( io.router_req.ready || !io.in.bits.head || at_dest) io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest io.in.ready := route_buffer.io.enq.ready && ( io.router_req.ready || !io.in.bits.head || at_dest) route_q.io.enq.valid := io.router_req.fire route_q.io.enq.bits := io.router_resp when (io.in.fire && io.in.bits.head && at_dest) { route_q.io.enq.valid := true.B route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (egressParams(o).egressId.U === io.in.bits.egress_id) { route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B } } } assert(!(route_q.io.enq.valid && !route_q.io.enq.ready)) val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2)) val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams), 1, pipe=true)) vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow io.vcalloc_req.bits.in_vc := 0.U val head = route_buffer.io.deq.bits.head val tail = route_buffer.io.deq.bits.tail vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) ) io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid && head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready) route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready && (route_q.io.deq.valid || !head) && (io.vcalloc_req.ready || !head) && (vcalloc_q.io.enq.ready || !head)) route_q.io.deq.ready := (route_buffer.io.deq.fire && tail) vcalloc_q.io.enq.valid := io.vcalloc_req.fire vcalloc_q.io.enq.bits := io.vcalloc_resp assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready)) io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire val out_bundle = if (combineSAST) { Wire(Valid(new SwitchBundle(outParams, egressParams))) } else { Reg(Valid(new SwitchBundle(outParams, egressParams))) } io.out(0) := out_bundle out_bundle.valid := vcalloc_buffer.io.deq.fire out_bundle.bits.flit := vcalloc_buffer.io.deq.bits out_bundle.bits.flit.virt_channel_id := 0.U val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq) io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready // TODO: We should not generate input/ingress/output/egress units for untraversable channels if (!cParam.traversable) { io.in.ready := false.B io.router_req.valid := false.B io.router_req.bits := DontCare io.vcalloc_req.valid := false.B io.vcalloc_req.bits := DontCare io.salloc_req.foreach(_.valid := false.B) io.salloc_req.foreach(_.bits := DontCare) io.out.foreach(_.valid := false.B) io.out.foreach(_.bits := DontCare) } }

module IngressUnit_54( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_10, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_11, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_14, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_15, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_18, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_19, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h28; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h2B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h2E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h31; // @[IngressUnit.scala:30:72] wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFN_e8_s24_16( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_16 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_16 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_16 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_71( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }

module TLXbar_cbus_out_i1_o8_a29d64s7k1z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire requestAIO_0_0 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], ~(auto_anon_in_a_bits_address[13:12])} == 7'h0; // @[Xbar.scala:222:41] wire [9:0] _GEN = auto_anon_in_a_bits_address[25:16] ^ 10'h201; // @[Xbar.scala:222:41] wire requestAIO_0_1 = {auto_anon_in_a_bits_address[28:27], _GEN[9], auto_anon_in_a_bits_address[20], _GEN[0], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41] wire requestAIO_0_2 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13], ~(auto_anon_in_a_bits_address[12])} == 7'h0 | {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12] ^ 2'h2} == 7'h0 | {auto_anon_in_a_bits_address[28:27] ^ 2'h2, auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41, :291:92] wire requestAIO_0_3 = {auto_anon_in_a_bits_address[28:27], ~(auto_anon_in_a_bits_address[25]), auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16]} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}] wire requestAIO_0_4 = {auto_anon_in_a_bits_address[28], ~(auto_anon_in_a_bits_address[27])} == 2'h0; // @[Xbar.scala:222:41] wire requestAIO_0_5 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41] wire requestAIO_0_6 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], ~(auto_anon_in_a_bits_address[16])} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}] wire requestAIO_0_7 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], ~(auto_anon_in_a_bits_address[20]), auto_anon_in_a_bits_address[13:12]} == 6'h0; // @[Xbar.scala:222:41] wire _portsAOI_in_0_a_ready_T_14 = requestAIO_0_0 & auto_anon_out_0_a_ready | requestAIO_0_1 & auto_anon_out_1_a_ready | requestAIO_0_2 & auto_anon_out_2_a_ready | requestAIO_0_3 & auto_anon_out_3_a_ready | requestAIO_0_4 & auto_anon_out_4_a_ready | requestAIO_0_5 & auto_anon_out_5_a_ready | requestAIO_0_6 & auto_anon_out_6_a_ready | requestAIO_0_7 & auto_anon_out_7_a_ready; // @[Mux.scala:30:73] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [7:0] readys_valid = {auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [7:0] readys_mask; // @[Arbiter.scala:23:23] wire [7:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [13:0] _GEN_0 = {_readys_filter_T_1[6:0], auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid} | {_readys_filter_T_1, auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid}; // @[package.scala:262:{43,48}] wire [12:0] _GEN_1 = _GEN_0[12:0] | {_readys_filter_T_1[7], _GEN_0[13:2]}; // @[package.scala:262:{43,48}] wire [10:0] _GEN_2 = _GEN_1[10:0] | {_readys_filter_T_1[7], _GEN_0[13], _GEN_1[12:4]}; // @[package.scala:262:{43,48}] wire [7:0] readys_readys = ~({readys_mask[7], _readys_filter_T_1[7] | readys_mask[6], _GEN_0[13] | readys_mask[5], _GEN_1[12:11] | readys_mask[4:3], _GEN_2[10:8] | readys_mask[2:0]} & _GEN_2[7:0]); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_2 = readys_readys[2] & auto_anon_out_2_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_3 = readys_readys[3] & auto_anon_out_3_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_4 = readys_readys[4] & auto_anon_out_4_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_5 = readys_readys[5] & auto_anon_out_5_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_6 = readys_readys[6] & auto_anon_out_6_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_7 = readys_readys[7] & auto_anon_out_7_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }

module MacUnit_117( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }

module dataMems_359( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule

Generate the Verilog code corresponding to the following Chisel files. File memory.scala: //************************************************************************** // Scratchpad Memory (asynchronous) //-------------------------------------------------------------------------- // // Christopher Celio // 2013 Jun 12 // // Provides a variable number of ports to the core, and one port to the HTIF // (host-target interface). // // Assumes that if the port is ready, it will be performed immediately. // For now, don't detect write collisions. // // Optionally uses synchronous read (default is async). For example, a 1-stage // processor can only ever work using asynchronous memory! package sodor.common import chisel3._ import chisel3.util._ import chisel3.experimental._ import Constants._ import sodor.common.Util._ trait MemoryOpConstants { val MT_X = 0.asUInt(3.W) val MT_B = 1.asUInt(3.W) val MT_H = 2.asUInt(3.W) val MT_W = 3.asUInt(3.W) val MT_D = 4.asUInt(3.W) val MT_BU = 5.asUInt(3.W) val MT_HU = 6.asUInt(3.W) val MT_WU = 7.asUInt(3.W) val M_X = "b0".asUInt(1.W) val M_XRD = "b0".asUInt(1.W) // int load val M_XWR = "b1".asUInt(1.W) // int store val DPORT = 0 val IPORT = 1 } // from the pov of the datapath class MemPortIo(data_width: Int)(implicit val conf: SodorCoreParams) extends Bundle { val req = new DecoupledIO(new MemReq(data_width)) val resp = Flipped(new ValidIO(new MemResp(data_width))) } class MemReq(data_width: Int)(implicit val conf: SodorCoreParams) extends Bundle { val addr = Output(UInt(conf.xprlen.W)) val data = Output(UInt(data_width.W)) val fcn = Output(UInt(M_X.getWidth.W)) // memory function code val typ = Output(UInt(MT_X.getWidth.W)) // memory type // To convert MemPortIO type to sign and size in TileLink format: subtract 1 from type, then take inversed MSB as signedness // and the remaining two bits as TileLink size def getTLSize = (typ - 1.U)(1, 0) def getTLSigned = ~(typ - 1.U)(2) def setType(tlSigned: Bool, tlSize: UInt) = { typ := Cat(~tlSigned, tlSize + 1.U) } } class MemResp(data_width: Int) extends Bundle { val data = Output(UInt(data_width.W)) } // Note: All `size` field in this class are base 2 logarithm class MemoryModule(numBytes: Int, useAsync: Boolean) { val addrWidth = log2Ceil(numBytes) val mem = if (useAsync) Mem(numBytes / 4, Vec(4, UInt(8.W))) else SyncReadMem(numBytes / 4, Vec(4, UInt(8.W))) // Convert size exponent to actual number of bytes - 1 private def sizeToBytes(size: UInt) = MuxLookup(size, 3.U)(List(0.U -> 0.U, 1.U -> 1.U, 2.U -> 3.U)) private def getMask(bytes: UInt, storeOffset: UInt = 0.U) = { val mask = ("b00011111".U(8.W) << bytes).apply(7, 4) val maskWithOffset = (mask << storeOffset).apply(3, 0) maskWithOffset.asBools.reverse } private def splitWord(data: UInt) = VecInit(((data(31, 0).asBools.reverse grouped 8) map (bools => Cat(bools))).toSeq) // Read function def read(addr: UInt, size: UInt, signed: Bool) = { // Create a module to show signal inside class MemReader extends Module { val io = IO(new Bundle { val addr = Input(UInt(addrWidth.W)) val size = Input(UInt(2.W)) val signed = Input(Bool()) val data = Output(UInt(32.W)) val mem_addr = Output(UInt((addrWidth - 2).W)) val mem_data = Input(Vec(4, UInt(8.W))) }) // Sync argument if needed val s_offset = if (useAsync) io.addr(1, 0) else RegNext(io.addr(1, 0)) val s_size = if (useAsync) io.size else RegNext(io.size) val s_signed = if (useAsync) io.signed else RegNext(io.signed) // Read data from the banks and align io.mem_addr := io.addr(addrWidth - 1, 2) val readVec = io.mem_data val shiftedVec = splitWord(Cat(readVec) >> (s_offset << 3)) // Mask data according to the size val bytes = sizeToBytes(s_size) val sign = shiftedVec(3.U - bytes).apply(7) val masks = getMask(bytes) val maskedVec = (shiftedVec zip masks) map ({ case (byte, mask) => Mux(sign && s_signed, byte | ~Fill(8, mask), byte & Fill(8, mask)) }) io.data := Cat(maskedVec) } val memreader = Module(new MemReader) memreader.io.addr := addr memreader.io.size := size memreader.io.signed := signed memreader.io.mem_data := mem.read(memreader.io.mem_addr) memreader.io.data } def apply(addr: UInt, size: UInt, signed: Bool) = read(addr, size, signed) // Write function def write(addr: UInt, data: UInt, size: UInt, en: Bool) = { // Create a module to show signal inside class MemWriter extends Module { val io = IO(new Bundle { val addr = Input(UInt(addrWidth.W)) val data = Input(UInt(32.W)) val size = Input(UInt(2.W)) val en = Input(Bool()) val mem_addr = Output(UInt((addrWidth - 2).W)) val mem_data = Output(Vec(4, UInt(8.W))) val mem_masks = Output(Vec(4, Bool())) }) // Align data and mask val offset = io.addr(1, 0) val shiftedVec = splitWord(io.data << (offset << 3)) val masks = getMask(sizeToBytes(io.size), offset) // Write io.mem_addr := io.addr(addrWidth - 1, 2) io.mem_data := shiftedVec io.mem_masks := VecInit(masks map (mask => mask && io.en)) } val memwriter = Module(new MemWriter) memwriter.io.addr := addr memwriter.io.data := data memwriter.io.size := size memwriter.io.en := en when (en) { mem.write(memwriter.io.mem_addr, memwriter.io.mem_data, memwriter.io.mem_masks) } } } // NOTE: the default is enormous (and may crash your computer), but is bound by // what the fesvr expects the smallest memory size to be. A proper fix would // be to modify the fesvr to expect smaller sizes. //for 1,2 and 5 stage need for combinational reads class ScratchPadMemoryBase(num_core_ports: Int, num_bytes: Int = (1 << 21), useAsync: Boolean = true)(implicit val conf: SodorCoreParams) extends Module { val io = IO(new Bundle { val core_ports = Vec(num_core_ports, Flipped(new MemPortIo(data_width = conf.xprlen)) ) val debug_port = Flipped(new MemPortIo(data_width = 32)) }) val num_bytes_per_line = 8 val num_lines = num_bytes / num_bytes_per_line println("\n Sodor Tile: creating Asynchronous Scratchpad Memory of size " + num_lines*num_bytes_per_line/1024 + " kB\n") val async_data = new MemoryModule(num_bytes, useAsync) for (i <- 0 until num_core_ports) { io.core_ports(i).resp.valid := (if (useAsync) io.core_ports(i).req.valid else RegNext(io.core_ports(i).req.valid, false.B)) io.core_ports(i).req.ready := true.B // for now, no back pressure } /////////// DPORT val req_addri = io.core_ports(DPORT).req.bits.addr val dport_req = io.core_ports(DPORT).req.bits val dport_wen = io.core_ports(DPORT).req.valid && dport_req.fcn === M_XWR io.core_ports(DPORT).resp.bits.data := async_data.read(dport_req.addr, dport_req.getTLSize, dport_req.getTLSigned) async_data.write(dport_req.addr, dport_req.data, dport_req.getTLSize, dport_wen) ///////////////// ///////////// IPORT if (num_core_ports == 2){ val iport_req = io.core_ports(IPORT).req.bits io.core_ports(IPORT).resp.bits.data := async_data.read(iport_req.addr, iport_req.getTLSize, iport_req.getTLSigned) } //////////// // DEBUG PORT------- io.debug_port.req.ready := true.B // for now, no back pressure io.debug_port.resp.valid := (if (useAsync) io.debug_port.req.valid else RegNext(io.debug_port.req.valid, false.B)) // asynchronous read val debug_port_req = io.debug_port.req.bits val debug_port_wen = io.debug_port.req.valid && debug_port_req.fcn === M_XWR io.debug_port.resp.bits.data := async_data.read(debug_port_req.addr, debug_port_req.getTLSize, debug_port_req.getTLSigned) async_data.write(debug_port_req.addr, debug_port_req.data, debug_port_req.getTLSize, debug_port_wen) } class AsyncScratchPadMemory(num_core_ports: Int, num_bytes: Int = (1 << 21))(implicit conf: SodorCoreParams) extends ScratchPadMemoryBase(num_core_ports, num_bytes, true)(conf) class SyncScratchPadMemory(num_core_ports: Int, num_bytes: Int = (1 << 21))(implicit conf: SodorCoreParams) extends ScratchPadMemoryBase(num_core_ports, num_bytes, false)(conf)

module MemWriter_1( // @[memory.scala:133:13] input clock, // @[memory.scala:133:13] input reset, // @[memory.scala:133:13] input [20:0] io_addr, // @[memory.scala:134:21] input [31:0] io_data, // @[memory.scala:134:21] input [1:0] io_size, // @[memory.scala:134:21] input io_en, // @[memory.scala:134:21] output [18:0] io_mem_addr, // @[memory.scala:134:21] output [7:0] io_mem_data_0, // @[memory.scala:134:21] output [7:0] io_mem_data_1, // @[memory.scala:134:21] output [7:0] io_mem_data_2, // @[memory.scala:134:21] output [7:0] io_mem_data_3, // @[memory.scala:134:21] output io_mem_masks_0, // @[memory.scala:134:21] output io_mem_masks_1, // @[memory.scala:134:21] output io_mem_masks_2, // @[memory.scala:134:21] output io_mem_masks_3 // @[memory.scala:134:21] ); wire [20:0] io_addr_0 = io_addr; // @[memory.scala:133:13] wire [31:0] io_data_0 = io_data; // @[memory.scala:133:13] wire [1:0] io_size_0 = io_size; // @[memory.scala:133:13] wire io_en_0 = io_en; // @[memory.scala:133:13] wire [18:0] _io_mem_addr_T; // @[memory.scala:151:32] wire [7:0] shiftedVec_0; // @[memory.scala:84:47] wire [7:0] shiftedVec_1; // @[memory.scala:84:47] wire [7:0] shiftedVec_2; // @[memory.scala:84:47] wire [7:0] shiftedVec_3; // @[memory.scala:84:47] wire [7:0] io_mem_data_0_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_1_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_2_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_3_0; // @[memory.scala:133:13] wire io_mem_masks_0_0; // @[memory.scala:133:13] wire io_mem_masks_1_0; // @[memory.scala:133:13] wire io_mem_masks_2_0; // @[memory.scala:133:13] wire io_mem_masks_3_0; // @[memory.scala:133:13] wire [18:0] io_mem_addr_0; // @[memory.scala:133:13] wire [1:0] offset = io_addr_0[1:0]; // @[memory.scala:133:13, :146:30] wire [4:0] _shiftedVec_T = {offset, 3'h0}; // @[memory.scala:146:30, :147:56] wire [62:0] _shiftedVec_T_1 = {31'h0, io_data_0} << _shiftedVec_T; // @[memory.scala:133:13, :147:{45,56}] wire [31:0] _shiftedVec_T_2 = _shiftedVec_T_1[31:0]; // @[memory.scala:84:54, :147:45] wire _shiftedVec_T_3 = _shiftedVec_T_2[0]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_4 = _shiftedVec_T_2[1]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_5 = _shiftedVec_T_2[2]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_6 = _shiftedVec_T_2[3]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_7 = _shiftedVec_T_2[4]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_8 = _shiftedVec_T_2[5]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_9 = _shiftedVec_T_2[6]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_10 = _shiftedVec_T_2[7]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_11 = _shiftedVec_T_2[8]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_12 = _shiftedVec_T_2[9]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_13 = _shiftedVec_T_2[10]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_14 = _shiftedVec_T_2[11]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_15 = _shiftedVec_T_2[12]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_16 = _shiftedVec_T_2[13]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_17 = _shiftedVec_T_2[14]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_18 = _shiftedVec_T_2[15]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_19 = _shiftedVec_T_2[16]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_20 = _shiftedVec_T_2[17]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_21 = _shiftedVec_T_2[18]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_22 = _shiftedVec_T_2[19]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_23 = _shiftedVec_T_2[20]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_24 = _shiftedVec_T_2[21]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_25 = _shiftedVec_T_2[22]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_26 = _shiftedVec_T_2[23]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_27 = _shiftedVec_T_2[24]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_28 = _shiftedVec_T_2[25]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_29 = _shiftedVec_T_2[26]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_30 = _shiftedVec_T_2[27]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_31 = _shiftedVec_T_2[28]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_32 = _shiftedVec_T_2[29]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_33 = _shiftedVec_T_2[30]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_34 = _shiftedVec_T_2[31]; // @[memory.scala:84:{54,62}] wire [1:0] shiftedVec_lo_lo = {_shiftedVec_T_28, _shiftedVec_T_27}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi = {_shiftedVec_T_30, _shiftedVec_T_29}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo = {shiftedVec_lo_hi, shiftedVec_lo_lo}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo = {_shiftedVec_T_32, _shiftedVec_T_31}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi = {_shiftedVec_T_34, _shiftedVec_T_33}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi = {shiftedVec_hi_hi, shiftedVec_hi_lo}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_35 = {shiftedVec_hi, shiftedVec_lo}; // @[memory.scala:84:106] assign shiftedVec_0 = _shiftedVec_T_35; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_1 = {_shiftedVec_T_20, _shiftedVec_T_19}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_1 = {_shiftedVec_T_22, _shiftedVec_T_21}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_1 = {shiftedVec_lo_hi_1, shiftedVec_lo_lo_1}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_1 = {_shiftedVec_T_24, _shiftedVec_T_23}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_1 = {_shiftedVec_T_26, _shiftedVec_T_25}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_1 = {shiftedVec_hi_hi_1, shiftedVec_hi_lo_1}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_36 = {shiftedVec_hi_1, shiftedVec_lo_1}; // @[memory.scala:84:106] assign shiftedVec_1 = _shiftedVec_T_36; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_2 = {_shiftedVec_T_12, _shiftedVec_T_11}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_2 = {_shiftedVec_T_14, _shiftedVec_T_13}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_2 = {shiftedVec_lo_hi_2, shiftedVec_lo_lo_2}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_2 = {_shiftedVec_T_16, _shiftedVec_T_15}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_2 = {_shiftedVec_T_18, _shiftedVec_T_17}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_2 = {shiftedVec_hi_hi_2, shiftedVec_hi_lo_2}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_37 = {shiftedVec_hi_2, shiftedVec_lo_2}; // @[memory.scala:84:106] assign shiftedVec_2 = _shiftedVec_T_37; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_3 = {_shiftedVec_T_4, _shiftedVec_T_3}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_3 = {_shiftedVec_T_6, _shiftedVec_T_5}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_3 = {shiftedVec_lo_hi_3, shiftedVec_lo_lo_3}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_3 = {_shiftedVec_T_8, _shiftedVec_T_7}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_3 = {_shiftedVec_T_10, _shiftedVec_T_9}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_3 = {shiftedVec_hi_hi_3, shiftedVec_hi_lo_3}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_38 = {shiftedVec_hi_3, shiftedVec_lo_3}; // @[memory.scala:84:106] assign shiftedVec_3 = _shiftedVec_T_38; // @[memory.scala:84:{47,106}] assign io_mem_data_0_0 = shiftedVec_0; // @[memory.scala:84:47, :133:13] assign io_mem_data_1_0 = shiftedVec_1; // @[memory.scala:84:47, :133:13] assign io_mem_data_2_0 = shiftedVec_2; // @[memory.scala:84:47, :133:13] assign io_mem_data_3_0 = shiftedVec_3; // @[memory.scala:84:47, :133:13] wire _masks_T = io_size_0 == 2'h0; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_1 = _masks_T ? 2'h0 : 2'h3; // @[memory.scala:76:62] wire _masks_T_2 = io_size_0 == 2'h1; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_3 = _masks_T_2 ? 2'h1 : _masks_T_1; // @[memory.scala:76:62] wire _masks_T_4 = io_size_0 == 2'h2; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_5 = _masks_T_4 ? 2'h3 : _masks_T_3; // @[memory.scala:76:62] wire [10:0] _masks_mask_T = 11'h1F << _masks_T_5; // @[memory.scala:76:62, :79:38] wire [3:0] masks_mask = _masks_mask_T[7:4]; // @[memory.scala:79:{38,53}] wire [6:0] _masks_maskWithOffset_T = {3'h0, masks_mask} << offset; // @[memory.scala:79:53, :80:34, :146:30, :147:56] wire [3:0] masks_maskWithOffset = _masks_maskWithOffset_T[3:0]; // @[memory.scala:80:{34,55}] wire masks_3 = masks_maskWithOffset[0]; // @[memory.scala:80:55, :81:22] wire masks_2 = masks_maskWithOffset[1]; // @[memory.scala:80:55, :81:22] wire masks_1 = masks_maskWithOffset[2]; // @[memory.scala:80:55, :81:22] wire masks_0 = masks_maskWithOffset[3]; // @[memory.scala:80:55, :81:22] assign _io_mem_addr_T = io_addr_0[20:2]; // @[memory.scala:133:13, :151:32] assign io_mem_addr_0 = _io_mem_addr_T; // @[memory.scala:133:13, :151:32] assign io_mem_masks_0_0 = masks_0 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_1_0 = masks_1 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_2_0 = masks_2 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_3_0 = masks_3 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_addr = io_mem_addr_0; // @[memory.scala:133:13] assign io_mem_data_0 = io_mem_data_0_0; // @[memory.scala:133:13] assign io_mem_data_1 = io_mem_data_1_0; // @[memory.scala:133:13] assign io_mem_data_2 = io_mem_data_2_0; // @[memory.scala:133:13] assign io_mem_data_3 = io_mem_data_3_0; // @[memory.scala:133:13] assign io_mem_masks_0 = io_mem_masks_0_0; // @[memory.scala:133:13] assign io_mem_masks_1 = io_mem_masks_1_0; // @[memory.scala:133:13] assign io_mem_masks_2 = io_mem_masks_2_0; // @[memory.scala:133:13] assign io_mem_masks_3 = io_mem_masks_3_0; // @[memory.scala:133:13] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }

module Tile_22( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_278 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_25( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _T_1505 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1505; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1505; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1578 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1578; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1578; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1578; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1431 = _T_1505 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1431 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1431 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1431 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1431 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1431 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1477 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1477 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1446 = _T_1578 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1446 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1446 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1446 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1549 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1549 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1531 = _T_1578 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1531 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1531 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1531 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_8(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule

Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }

module AsyncResetSynchronizerShiftReg_w1_d3_i0_75( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_151 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }

module Router_20( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_8_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_8_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_8_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_8_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_8_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_8_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_8_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_8_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_6_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_6_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_8_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }

module IntSyncSyncCrossingSink_n1x5_2( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] input auto_in_sync_1, // @[LazyModuleImp.scala:107:25] input auto_in_sync_2, // @[LazyModuleImp.scala:107:25] input auto_in_sync_3, // @[LazyModuleImp.scala:107:25] input auto_in_sync_4, // @[LazyModuleImp.scala:107:25] output auto_out_0, // @[LazyModuleImp.scala:107:25] output auto_out_1, // @[LazyModuleImp.scala:107:25] output auto_out_2, // @[LazyModuleImp.scala:107:25] output auto_out_3, // @[LazyModuleImp.scala:107:25] output auto_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire auto_in_sync_1_0 = auto_in_sync_1; // @[Crossing.scala:96:9] wire auto_in_sync_2_0 = auto_in_sync_2; // @[Crossing.scala:96:9] wire auto_in_sync_3_0 = auto_in_sync_3; // @[Crossing.scala:96:9] wire auto_in_sync_4_0 = auto_in_sync_4; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeIn_sync_1 = auto_in_sync_1_0; // @[Crossing.scala:96:9] wire nodeIn_sync_2 = auto_in_sync_2_0; // @[Crossing.scala:96:9] wire nodeIn_sync_3 = auto_in_sync_3_0; // @[Crossing.scala:96:9] wire nodeIn_sync_4 = auto_in_sync_4_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire nodeOut_1; // @[MixedNode.scala:542:17] wire nodeOut_2; // @[MixedNode.scala:542:17] wire nodeOut_3; // @[MixedNode.scala:542:17] wire nodeOut_4; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] wire auto_out_1_0; // @[Crossing.scala:96:9] wire auto_out_2_0; // @[Crossing.scala:96:9] wire auto_out_3_0; // @[Crossing.scala:96:9] wire auto_out_4_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_1 = nodeIn_sync_1; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_2 = nodeIn_sync_2; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_3 = nodeIn_sync_3; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_4 = nodeIn_sync_4; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_1_0 = nodeOut_1; // @[Crossing.scala:96:9] assign auto_out_2_0 = nodeOut_2; // @[Crossing.scala:96:9] assign auto_out_3_0 = nodeOut_3; // @[Crossing.scala:96:9] assign auto_out_4_0 = nodeOut_4; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] assign auto_out_1 = auto_out_1_0; // @[Crossing.scala:96:9] assign auto_out_2 = auto_out_2_0; // @[Crossing.scala:96:9] assign auto_out_3 = auto_out_3_0; // @[Crossing.scala:96:9] assign auto_out_4 = auto_out_4_0; // @[Crossing.scala:96:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }

module AsyncResetRegVec_w1_i0_43( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_1( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_1 = 1'h1; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = 1'h1; // @[Mux.scala:30:73] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [1:0] io_in_b_bits_source = 2'h1; // @[Monitor.scala:36:7] wire [1:0] _legal_source_T_6 = 2'h1; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = 2'h1; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = 2'h1; // @[Mux.scala:30:73] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_5 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] _legal_source_T_3 = 2'h0; // @[Mux.scala:30:73] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_20 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_22 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_23 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLMonitor_6( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }

module MulAddRecFN_e8_s24( // @[MulAddRecFN.scala:300:7] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = 48'h0; // @[MulAddRecFN.scala:327:45] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [48:0] mulAddResult = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_8 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule

Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet || m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) || (arithmetic && !m.supportsArithmetic.contains(ourSupport)) || !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ || _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ || _) val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask | (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) | signext_a val a_d_ext = (a_d & wide_mask) | signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8*beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready || d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied in.d.bits.denied := d_cam_denied || out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData val doesR = a.opcode === Get || doesA val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) || (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }

module TLAtomicAutomata_pbus( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _a_canLogical_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_canArithmetic_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83] wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60] wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85] wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _source_c_bits_legal_T_8 = 1'h1; // @[Parameters.scala:137:59] wire _a_canLogical_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canLogical_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canLogical_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canLogical = 1'h0; // @[AtomicAutomata.scala:94:45] wire _a_canArithmetic_T = 1'h0; // @[Parameters.scala:684:29] wire _a_canArithmetic_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _a_canArithmetic_T_7 = 1'h0; // @[Parameters.scala:686:26] wire a_canArithmetic = 1'h0; // @[AtomicAutomata.scala:95:45] wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [29:0] _a_canLogical_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canLogical_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_canArithmetic_T_4 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_6 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _source_c_bits_legal_T_7 = 30'h0; // @[Parameters.scala:137:46] wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27] wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9] wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9] wire [2:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28] wire [28:0] _a_canLogical_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_1 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28] wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28] wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28] wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] wire [2:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17] wire [2:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34] reg [7:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] wire [7:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] _source_c_bits_legal_T_4 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44] wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58] wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82] wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire cam_amo_0; // @[AtomicAutomata.scala:87:44] assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44] wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68] assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68] wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56] wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80] wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28] wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49] wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}] wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96] wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49] wire [29:0] _a_canLogical_T_2 = {1'h0, _a_canLogical_T_1}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_2 = {1'h0, _a_canArithmetic_T_1}; // @[Parameters.scala:137:{31,41}] wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47] wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47] wire _a_isSupported_T = ~a_isArithmetic; // @[AtomicAutomata.scala:97:47, :98:63] wire a_isSupported = ~a_isLogical & _a_isSupported_T; // @[AtomicAutomata.scala:96:47, :98:{32,63}] wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}] wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}] wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57] wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28] wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42] wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42] wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39] wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25] wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39] wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}] wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}] wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29] wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29] wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38] wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}] wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}] wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38] wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}] wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}] wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17] wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17] wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17] wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17] wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17] wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17] wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17] wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17] wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40] wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40] wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17] wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17] wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17] wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17] wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17] wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17] wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17] wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17] wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40] wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40] wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40] wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28] wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}] wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28] wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}] wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43] wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}] wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33] wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33] wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49] wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35] wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}] wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50] wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}] wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65] wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}] wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}] wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31] wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50] wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}] wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34] wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}] wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17] wire _source_i_ready_T; // @[Arbiter.scala:94:31] wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38] wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28] wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28] wire source_i_ready; // @[AtomicAutomata.scala:154:28] wire source_i_valid; // @[AtomicAutomata.scala:154:28] wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23] wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53] wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}] assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38] assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32] assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32] wire _source_c_ready_T; // @[Arbiter.scala:94:31] wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17] wire source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [2:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28] wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28] wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28] wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28] wire source_c_ready; // @[AtomicAutomata.scala:165:28] wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45] assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17] wire _source_c_bits_legal_T_1 = cam_a_0_bits_size != 3'h7; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29] wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3; // @[Parameters.scala:684:{29,54}] wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire source_c_bits_legal = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17] assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17] assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10] assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17] assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17] assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 3'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10] assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10] wire [12:0] _decode_T = 13'h3F << nodeIn_a_bits_size; // @[package.scala:243:71] wire [5:0] _decode_T_1 = _decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] decode = _decode_T_2[5:3]; // @[package.scala:243:46] wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28]

Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }

module RoundRawFNToRecFN_e8_s24_121( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_121 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule

Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := 0.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt }

module LoopBranchPredictorColumn( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [36:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [36:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [36:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [36:0] f4_idx_REG; // @[loop.scala:92:35] reg [36:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule

Generate the Verilog code corresponding to the following Chisel files. File RegMapFIFO.scala: package sifive.blocks.util import chisel3._ import chisel3.util._ import freechips.rocketchip.regmapper._ // MSB indicates full status object NonBlockingEnqueue { def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val enqWidth = enq.bits.getWidth val quash = Wire(Bool()) require(enqWidth > 0) require(regWidth > enqWidth) Seq( RegField(enqWidth, RegReadFn(0.U), RegWriteFn((valid, data) => { enq.valid := valid && !quash enq.bits := data true.B }), RegFieldDesc("data", "Transmit data", access=RegFieldAccessType.W)), RegField(regWidth - enqWidth - 1), RegField(1, !enq.ready, RegWriteFn((valid, data) => { quash := valid && data(0) true.B }), RegFieldDesc("full", "Transmit FIFO full", access=RegFieldAccessType.R, volatile=true))) } } // MSB indicates empty status object NonBlockingDequeue { def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { val deqWidth = deq.bits.getWidth require(deqWidth > 0) require(regWidth > deqWidth) Seq( RegField.r(deqWidth, RegReadFn(ready => { deq.ready := ready (true.B, deq.bits) }), RegFieldDesc("data", "Receive data", volatile=true)), RegField(regWidth - deqWidth - 1), RegField.r(1, !deq.valid, RegFieldDesc("empty", "Receive FIFO empty", volatile=true))) } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * */ case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) || (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit */ class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get || !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get || errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. */ case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map*) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_*) } def genRegDescsJson(mapping: RegField.Map*): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_*) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_*) } } /** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. */ trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag /* MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. */ object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct */ cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) /* Filter out any cases identical to the default */ val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2*simple.size) { /* The dense encoding case uses a Vec */ val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { /* The sparse encoding case uses switch */ val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }

module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] wire _txm_io_tx_busy; // @[UART.scala:129:19] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25] wire [11:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25] wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25] wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32] wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25] wire [11:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire ioNodeOut_txd; // @[MixedNode.scala:542:17] wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25] wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] wire [11:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] wire auto_io_out_txd_0; // @[UART.scala:127:25] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [11:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [11:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25] wire _intnodeOut_0_T_2; // @[UART.scala:191:41] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] reg [15:0] div; // @[UART.scala:135:20] wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24] reg txen; // @[UART.scala:141:21] wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49] wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}] wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24] wire _ip_rxwm_T; // @[UART.scala:190:28] wire _ip_txwm_T; // @[UART.scala:189:28] wire ip_rxwm; // @[UART.scala:187:16] wire ip_txwm; // @[UART.scala:187:16] assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28] assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28] wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29] wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53] assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}] assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41] wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26] wire quash; // @[RegMapFIFO.scala:11:21] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33] wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24] wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24] assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26] wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24] wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:141:21] rxen <= 1'h0; // @[UART.scala:142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:151:22] ie_rxwm <= 1'h0; // @[UART.scala:186:19] ie_txwm <= 1'h0; // @[UART.scala:186:19] end else begin // @[UART.scala:127:25] if (out_f_woready_15) // @[RegisterRouter.scala:87:24] div <= _out_T_157; // @[RegisterRouter.scala:87:24] if (out_f_woready_6) // @[RegisterRouter.scala:87:24] txen <= _out_T_62; // @[RegisterRouter.scala:87:24] if (out_f_woready_9) // @[RegisterRouter.scala:87:24] rxen <= _out_T_95; // @[RegisterRouter.scala:87:24] if (out_f_woready_8) // @[RegisterRouter.scala:87:24] txwm <= _out_T_84; // @[RegisterRouter.scala:87:24] if (out_f_woready_10) // @[RegisterRouter.scala:87:24] rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24] if (out_f_woready_7) // @[RegisterRouter.scala:87:24] nstop <= _out_T_73; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24] if (out_f_woready_11) // @[RegisterRouter.scala:87:24] ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x1_20 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0) ); // @[Crossing.scala:29:31] TLMonitor_68 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] UARTTx txm ( // @[UART.scala:129:19] .clock (clock), .reset (reset), .io_en (txen), // @[UART.scala:141:21] .io_in_ready (_txm_io_in_ready), .io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19] .io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19] .io_out (ioNodeOut_txd), .io_div (div), // @[UART.scala:135:20] .io_nstop (nstop), // @[UART.scala:151:22] .io_tx_busy (_txm_io_tx_busy) ); // @[UART.scala:129:19] Queue8_UInt8 txq ( // @[UART.scala:130:19] .clock (clock), .reset (reset), .io_enq_ready (_txq_io_enq_ready), .io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30] .io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24] .io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19] .io_deq_valid (_txq_io_deq_valid), .io_deq_bits (_txq_io_deq_bits), .io_count (_txq_io_count) ); // @[UART.scala:130:19] UARTRx rxm ( // @[UART.scala:132:19] .clock (clock), .reset (reset), .io_en (rxen), // @[UART.scala:142:21] .io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17] .io_out_valid (_rxm_io_out_valid), .io_out_bits (_rxm_io_out_bits), .io_div (div) // @[UART.scala:135:20] ); // @[UART.scala:132:19] Queue8_UInt8_1 rxq ( // @[UART.scala:133:19] .clock (clock), .reset (reset), .io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19] .io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxq_io_deq_valid), .io_deq_bits (_rxq_io_deq_bits), .io_count (_rxq_io_count) ); // @[UART.scala:133:19] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25] endmodule

Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }

module InputBuffer_3( // @[InputUnit.scala:49:7] input clock, // @[InputUnit.scala:49:7] input reset, // @[InputUnit.scala:49:7] input io_enq_0_valid, // @[InputUnit.scala:51:14] input io_enq_0_bits_head, // @[InputUnit.scala:51:14] input io_enq_0_bits_tail, // @[InputUnit.scala:51:14] input [72:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14] input [4:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14] output io_deq_0_bits_head, // @[InputUnit.scala:51:14] output io_deq_0_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14] output io_deq_1_bits_head, // @[InputUnit.scala:51:14] output io_deq_1_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14] output io_deq_2_bits_head, // @[InputUnit.scala:51:14] output io_deq_2_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14] output io_deq_3_bits_head, // @[InputUnit.scala:51:14] output io_deq_3_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_3_bits_payload, // @[InputUnit.scala:51:14] output io_deq_4_bits_head, // @[InputUnit.scala:51:14] output io_deq_4_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_4_bits_payload, // @[InputUnit.scala:51:14] output io_deq_5_bits_head, // @[InputUnit.scala:51:14] output io_deq_5_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_5_bits_payload, // @[InputUnit.scala:51:14] output io_deq_6_bits_head, // @[InputUnit.scala:51:14] output io_deq_6_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_6_bits_payload, // @[InputUnit.scala:51:14] output io_deq_7_bits_head, // @[InputUnit.scala:51:14] output io_deq_7_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_7_bits_payload, // @[InputUnit.scala:51:14] output io_deq_8_bits_head, // @[InputUnit.scala:51:14] output io_deq_8_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_8_bits_payload, // @[InputUnit.scala:51:14] output io_deq_9_bits_head, // @[InputUnit.scala:51:14] output io_deq_9_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_9_bits_payload, // @[InputUnit.scala:51:14] output io_deq_10_bits_head, // @[InputUnit.scala:51:14] output io_deq_10_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_10_bits_payload, // @[InputUnit.scala:51:14] output io_deq_11_bits_head, // @[InputUnit.scala:51:14] output io_deq_11_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_11_bits_payload, // @[InputUnit.scala:51:14] output io_deq_12_bits_head, // @[InputUnit.scala:51:14] output io_deq_12_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_12_bits_payload, // @[InputUnit.scala:51:14] output io_deq_13_bits_head, // @[InputUnit.scala:51:14] output io_deq_13_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_13_bits_payload, // @[InputUnit.scala:51:14] output io_deq_14_bits_head, // @[InputUnit.scala:51:14] output io_deq_14_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_14_bits_payload, // @[InputUnit.scala:51:14] output io_deq_15_bits_head, // @[InputUnit.scala:51:14] output io_deq_15_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_15_bits_payload, // @[InputUnit.scala:51:14] output io_deq_16_bits_head, // @[InputUnit.scala:51:14] output io_deq_16_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_16_bits_payload, // @[InputUnit.scala:51:14] output io_deq_17_bits_head, // @[InputUnit.scala:51:14] output io_deq_17_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_17_bits_payload, // @[InputUnit.scala:51:14] input io_deq_18_ready, // @[InputUnit.scala:51:14] output io_deq_18_valid, // @[InputUnit.scala:51:14] output io_deq_18_bits_head, // @[InputUnit.scala:51:14] output io_deq_18_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_18_bits_payload, // @[InputUnit.scala:51:14] input io_deq_19_ready, // @[InputUnit.scala:51:14] output io_deq_19_valid, // @[InputUnit.scala:51:14] output io_deq_19_bits_head, // @[InputUnit.scala:51:14] output io_deq_19_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_19_bits_payload, // @[InputUnit.scala:51:14] input io_deq_20_ready, // @[InputUnit.scala:51:14] output io_deq_20_valid, // @[InputUnit.scala:51:14] output io_deq_20_bits_head, // @[InputUnit.scala:51:14] output io_deq_20_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_20_bits_payload, // @[InputUnit.scala:51:14] input io_deq_21_ready, // @[InputUnit.scala:51:14] output io_deq_21_valid, // @[InputUnit.scala:51:14] output io_deq_21_bits_head, // @[InputUnit.scala:51:14] output io_deq_21_bits_tail, // @[InputUnit.scala:51:14] output [72:0] io_deq_21_bits_payload // @[InputUnit.scala:51:14] ); wire _qs_21_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_20_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_19_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_18_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_17_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_16_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_15_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_14_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_13_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_12_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_11_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_10_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_9_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_8_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_7_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_6_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_5_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_4_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49] wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49] wire [74:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R4_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R5_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R6_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R7_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R8_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R9_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R10_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R11_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R12_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R13_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R14_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R15_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R16_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R17_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R18_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R19_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R20_data; // @[InputUnit.scala:85:18] wire [74:0] _mem_ext_R21_data; // @[InputUnit.scala:85:18] reg [3:0] heads_0; // @[InputUnit.scala:86:24] reg [3:0] heads_1; // @[InputUnit.scala:86:24] reg [3:0] heads_2; // @[InputUnit.scala:86:24] reg [3:0] heads_3; // @[InputUnit.scala:86:24] reg [3:0] heads_4; // @[InputUnit.scala:86:24] reg [3:0] heads_5; // @[InputUnit.scala:86:24] reg [3:0] heads_6; // @[InputUnit.scala:86:24] reg [3:0] heads_7; // @[InputUnit.scala:86:24] reg [3:0] heads_8; // @[InputUnit.scala:86:24] reg [3:0] heads_9; // @[InputUnit.scala:86:24] reg [3:0] heads_10; // @[InputUnit.scala:86:24] reg [3:0] heads_11; // @[InputUnit.scala:86:24] reg [3:0] heads_12; // @[InputUnit.scala:86:24] reg [3:0] heads_13; // @[InputUnit.scala:86:24] reg [3:0] heads_14; // @[InputUnit.scala:86:24] reg [3:0] heads_15; // @[InputUnit.scala:86:24] reg [3:0] heads_16; // @[InputUnit.scala:86:24] reg [3:0] heads_17; // @[InputUnit.scala:86:24] reg [3:0] heads_18; // @[InputUnit.scala:86:24] reg [3:0] heads_19; // @[InputUnit.scala:86:24] reg [3:0] heads_20; // @[InputUnit.scala:86:24] reg [3:0] heads_21; // @[InputUnit.scala:86:24] reg [3:0] tails_0; // @[InputUnit.scala:87:24] reg [3:0] tails_1; // @[InputUnit.scala:87:24] reg [3:0] tails_2; // @[InputUnit.scala:87:24] reg [3:0] tails_3; // @[InputUnit.scala:87:24] reg [3:0] tails_4; // @[InputUnit.scala:87:24] reg [3:0] tails_5; // @[InputUnit.scala:87:24] reg [3:0] tails_6; // @[InputUnit.scala:87:24] reg [3:0] tails_7; // @[InputUnit.scala:87:24] reg [3:0] tails_8; // @[InputUnit.scala:87:24] reg [3:0] tails_9; // @[InputUnit.scala:87:24] reg [3:0] tails_10; // @[InputUnit.scala:87:24] reg [3:0] tails_11; // @[InputUnit.scala:87:24] reg [3:0] tails_12; // @[InputUnit.scala:87:24] reg [3:0] tails_13; // @[InputUnit.scala:87:24] reg [3:0] tails_14; // @[InputUnit.scala:87:24] reg [3:0] tails_15; // @[InputUnit.scala:87:24] reg [3:0] tails_16; // @[InputUnit.scala:87:24] reg [3:0] tails_17; // @[InputUnit.scala:87:24] reg [3:0] tails_18; // @[InputUnit.scala:87:24] reg [3:0] tails_19; // @[InputUnit.scala:87:24] reg [3:0] tails_20; // @[InputUnit.scala:87:24] reg [3:0] tails_21; // @[InputUnit.scala:87:24] wire _tails_T_66 = io_enq_0_bits_virt_channel_id == 5'h0; // @[Mux.scala:32:36] wire _tails_T_67 = io_enq_0_bits_virt_channel_id == 5'h1; // @[Mux.scala:32:36] wire _tails_T_68 = io_enq_0_bits_virt_channel_id == 5'h2; // @[Mux.scala:32:36] wire _tails_T_69 = io_enq_0_bits_virt_channel_id == 5'h3; // @[Mux.scala:32:36] wire _tails_T_70 = io_enq_0_bits_virt_channel_id == 5'h4; // @[Mux.scala:32:36] wire _tails_T_71 = io_enq_0_bits_virt_channel_id == 5'h5; // @[Mux.scala:32:36] wire _tails_T_72 = io_enq_0_bits_virt_channel_id == 5'h6; // @[Mux.scala:32:36] wire _tails_T_73 = io_enq_0_bits_virt_channel_id == 5'h7; // @[Mux.scala:32:36] wire _tails_T_74 = io_enq_0_bits_virt_channel_id == 5'h8; // @[Mux.scala:32:36] wire _tails_T_75 = io_enq_0_bits_virt_channel_id == 5'h9; // @[Mux.scala:32:36] wire _tails_T_76 = io_enq_0_bits_virt_channel_id == 5'hA; // @[Mux.scala:32:36] wire _tails_T_77 = io_enq_0_bits_virt_channel_id == 5'hB; // @[Mux.scala:32:36] wire _tails_T_78 = io_enq_0_bits_virt_channel_id == 5'hC; // @[Mux.scala:32:36] wire _tails_T_79 = io_enq_0_bits_virt_channel_id == 5'hD; // @[Mux.scala:32:36] wire _tails_T_80 = io_enq_0_bits_virt_channel_id == 5'hE; // @[Mux.scala:32:36] wire _tails_T_81 = io_enq_0_bits_virt_channel_id == 5'hF; // @[Mux.scala:32:36] wire _tails_T_82 = io_enq_0_bits_virt_channel_id == 5'h10; // @[Mux.scala:32:36] wire _tails_T_83 = io_enq_0_bits_virt_channel_id == 5'h11; // @[Mux.scala:32:36] wire _tails_T_84 = io_enq_0_bits_virt_channel_id == 5'h12; // @[Mux.scala:32:36] wire _tails_T_85 = io_enq_0_bits_virt_channel_id == 5'h13; // @[Mux.scala:32:36] wire _tails_T_86 = io_enq_0_bits_virt_channel_id == 5'h14; // @[Mux.scala:32:36] wire _tails_T_87 = io_enq_0_bits_virt_channel_id == 5'h15; // @[Mux.scala:32:36] wire direct_to_q = (_tails_T_66 & _qs_0_io_enq_ready | _tails_T_67 & _qs_1_io_enq_ready | _tails_T_68 & _qs_2_io_enq_ready | _tails_T_69 & _qs_3_io_enq_ready | _tails_T_70 & _qs_4_io_enq_ready | _tails_T_71 & _qs_5_io_enq_ready | _tails_T_72 & _qs_6_io_enq_ready | _tails_T_73 & _qs_7_io_enq_ready | _tails_T_74 & _qs_8_io_enq_ready | _tails_T_75 & _qs_9_io_enq_ready | _tails_T_76 & _qs_10_io_enq_ready | _tails_T_77 & _qs_11_io_enq_ready | _tails_T_78 & _qs_12_io_enq_ready | _tails_T_79 & _qs_13_io_enq_ready | _tails_T_80 & _qs_14_io_enq_ready | _tails_T_81 & _qs_15_io_enq_ready | _tails_T_82 & _qs_16_io_enq_ready | _tails_T_83 & _qs_17_io_enq_ready | _tails_T_84 & _qs_18_io_enq_ready | _tails_T_85 & _qs_19_io_enq_ready | _tails_T_86 & _qs_20_io_enq_ready | _tails_T_87 & _qs_21_io_enq_ready) & (_tails_T_66 & heads_0 == tails_0 | _tails_T_67 & heads_1 == tails_1 | _tails_T_68 & heads_2 == tails_2 | _tails_T_69 & heads_3 == tails_3 | _tails_T_70 & heads_4 == tails_4 | _tails_T_71 & heads_5 == tails_5 | _tails_T_72 & heads_6 == tails_6 | _tails_T_73 & heads_7 == tails_7 | _tails_T_74 & heads_8 == tails_8 | _tails_T_75 & heads_9 == tails_9 | _tails_T_76 & heads_10 == tails_10 | _tails_T_77 & heads_11 == tails_11 | _tails_T_78 & heads_12 == tails_12 | _tails_T_79 & heads_13 == tails_13 | _tails_T_80 & heads_14 == tails_14 | _tails_T_81 & heads_15 == tails_15 | _tails_T_82 & heads_16 == tails_16 | _tails_T_83 & heads_17 == tails_17 | _tails_T_84 & heads_18 == tails_18 | _tails_T_85 & heads_19 == tails_19 | _tails_T_86 & heads_20 == tails_20 | _tails_T_87 & heads_21 == tails_21); // @[Mux.scala:30:73, :32:36] wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}] wire [31:0][3:0] _GEN = {{tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_0}, {tails_21}, {tails_20}, {tails_19}, {tails_18}, {tails_17}, {tails_16}, {tails_15}, {tails_14}, {tails_13}, {tails_12}, {tails_11}, {tails_10}, {tails_9}, {tails_8}, {tails_7}, {tails_6}, {tails_5}, {tails_4}, {tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16] wire _GEN_0 = io_enq_0_bits_virt_channel_id == 5'h0; // @[InputUnit.scala:103:45] wire _GEN_1 = io_enq_0_bits_virt_channel_id == 5'h1; // @[InputUnit.scala:103:45] wire _GEN_2 = io_enq_0_bits_virt_channel_id == 5'h2; // @[InputUnit.scala:103:45] wire _GEN_3 = io_enq_0_bits_virt_channel_id == 5'h3; // @[InputUnit.scala:103:45] wire _GEN_4 = io_enq_0_bits_virt_channel_id == 5'h4; // @[InputUnit.scala:103:45] wire _GEN_5 = io_enq_0_bits_virt_channel_id == 5'h5; // @[InputUnit.scala:103:45] wire _GEN_6 = io_enq_0_bits_virt_channel_id == 5'h6; // @[InputUnit.scala:103:45] wire _GEN_7 = io_enq_0_bits_virt_channel_id == 5'h7; // @[InputUnit.scala:103:45] wire _GEN_8 = io_enq_0_bits_virt_channel_id == 5'h8; // @[InputUnit.scala:103:45] wire _GEN_9 = io_enq_0_bits_virt_channel_id == 5'h9; // @[InputUnit.scala:103:45] wire _GEN_10 = io_enq_0_bits_virt_channel_id == 5'hA; // @[InputUnit.scala:103:45] wire _GEN_11 = io_enq_0_bits_virt_channel_id == 5'hB; // @[InputUnit.scala:103:45] wire _GEN_12 = io_enq_0_bits_virt_channel_id == 5'hC; // @[InputUnit.scala:103:45] wire _GEN_13 = io_enq_0_bits_virt_channel_id == 5'hD; // @[InputUnit.scala:103:45] wire _GEN_14 = io_enq_0_bits_virt_channel_id == 5'hE; // @[InputUnit.scala:103:45] wire _GEN_15 = io_enq_0_bits_virt_channel_id == 5'hF; // @[InputUnit.scala:103:45] wire _GEN_16 = io_enq_0_bits_virt_channel_id == 5'h10; // @[InputUnit.scala:103:45] wire _GEN_17 = io_enq_0_bits_virt_channel_id == 5'h11; // @[InputUnit.scala:103:45] wire _GEN_18 = io_enq_0_bits_virt_channel_id == 5'h12; // @[InputUnit.scala:103:45] wire _GEN_19 = io_enq_0_bits_virt_channel_id == 5'h13; // @[InputUnit.scala:103:45] wire _GEN_20 = io_enq_0_bits_virt_channel_id == 5'h14; // @[InputUnit.scala:103:45] wire _GEN_21 = io_enq_0_bits_virt_channel_id == 5'h15; // @[InputUnit.scala:103:45] wire _GEN_22 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34] wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_4 = heads_4 != tails_4 & _qs_4_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_5 = heads_5 != tails_5 & _qs_5_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_6 = heads_6 != tails_6 & _qs_6_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_7 = heads_7 != tails_7 & _qs_7_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_8 = heads_8 != tails_8 & _qs_8_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_9 = heads_9 != tails_9 & _qs_9_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_10 = heads_10 != tails_10 & _qs_10_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_11 = heads_11 != tails_11 & _qs_11_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_12 = heads_12 != tails_12 & _qs_12_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_13 = heads_13 != tails_13 & _qs_13_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_14 = heads_14 != tails_14 & _qs_14_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_15 = heads_15 != tails_15 & _qs_15_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_16 = heads_16 != tails_16 & _qs_16_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_17 = heads_17 != tails_17 & _qs_17_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_18 = heads_18 != tails_18 & _qs_18_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_19 = heads_19 != tails_19 & _qs_19_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_20 = heads_20 != tails_20 & _qs_20_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire can_to_q_21 = heads_21 != tails_21 & _qs_21_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}] wire [21:0] to_q_oh_enc = can_to_q_0 ? 22'h1 : can_to_q_1 ? 22'h2 : can_to_q_2 ? 22'h4 : can_to_q_3 ? 22'h8 : can_to_q_4 ? 22'h10 : can_to_q_5 ? 22'h20 : can_to_q_6 ? 22'h40 : can_to_q_7 ? 22'h80 : can_to_q_8 ? 22'h100 : can_to_q_9 ? 22'h200 : can_to_q_10 ? 22'h400 : can_to_q_11 ? 22'h800 : can_to_q_12 ? 22'h1000 : can_to_q_13 ? 22'h2000 : can_to_q_14 ? 22'h4000 : can_to_q_15 ? 22'h8000 : can_to_q_16 ? 22'h10000 : can_to_q_17 ? 22'h20000 : can_to_q_18 ? 22'h40000 : can_to_q_19 ? 22'h80000 : can_to_q_20 ? 22'h100000 : {can_to_q_21, 21'h0}; // @[Mux.scala:50:70] wire _GEN_23 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3 | can_to_q_4 | can_to_q_5 | can_to_q_6 | can_to_q_7 | can_to_q_8 | can_to_q_9 | can_to_q_10 | can_to_q_11 | can_to_q_12 | can_to_q_13 | can_to_q_14 | can_to_q_15 | can_to_q_16 | can_to_q_17 | can_to_q_18 | can_to_q_19 | can_to_q_20 | can_to_q_21; // @[package.scala:81:59] wire [3:0] head = (to_q_oh_enc[0] ? heads_0 : 4'h0) | (to_q_oh_enc[1] ? heads_1 : 4'h0) | (to_q_oh_enc[2] ? heads_2 : 4'h0) | (to_q_oh_enc[3] ? heads_3 : 4'h0) | (to_q_oh_enc[4] ? heads_4 : 4'h0) | (to_q_oh_enc[5] ? heads_5 : 4'h0) | (to_q_oh_enc[6] ? heads_6 : 4'h0) | (to_q_oh_enc[7] ? heads_7 : 4'h0) | (to_q_oh_enc[8] ? heads_8 : 4'h0) | (to_q_oh_enc[9] ? heads_9 : 4'h0) | (to_q_oh_enc[10] ? heads_10 : 4'h0) | (to_q_oh_enc[11] ? heads_11 : 4'h0) | (to_q_oh_enc[12] ? heads_12 : 4'h0) | (to_q_oh_enc[13] ? heads_13 : 4'h0) | (to_q_oh_enc[14] ? heads_14 : 4'h0) | (to_q_oh_enc[15] ? heads_15 : 4'h0) | (to_q_oh_enc[16] ? heads_16 : 4'h0) | (to_q_oh_enc[17] ? heads_17 : 4'h0) | (to_q_oh_enc[18] ? heads_18 : 4'h0) | (to_q_oh_enc[19] ? heads_19 : 4'h0) | (to_q_oh_enc[20] ? heads_20 : 4'h0) | (to_q_oh_enc[21] ? heads_21 : 4'h0); // @[OneHot.scala:83:30] wire _GEN_24 = _GEN_23 & to_q_oh_enc[0]; // @[OneHot.scala:83:30] wire _GEN_25 = _GEN_23 & to_q_oh_enc[1]; // @[OneHot.scala:83:30] wire _GEN_26 = _GEN_23 & to_q_oh_enc[2]; // @[OneHot.scala:83:30] wire _GEN_27 = _GEN_23 & to_q_oh_enc[3]; // @[OneHot.scala:83:30] wire _GEN_28 = _GEN_23 & to_q_oh_enc[4]; // @[OneHot.scala:83:30] wire _GEN_29 = _GEN_23 & to_q_oh_enc[5]; // @[OneHot.scala:83:30] wire _GEN_30 = _GEN_23 & to_q_oh_enc[6]; // @[OneHot.scala:83:30] wire _GEN_31 = _GEN_23 & to_q_oh_enc[7]; // @[OneHot.scala:83:30] wire _GEN_32 = _GEN_23 & to_q_oh_enc[8]; // @[OneHot.scala:83:30] wire _GEN_33 = _GEN_23 & to_q_oh_enc[9]; // @[OneHot.scala:83:30] wire _GEN_34 = _GEN_23 & to_q_oh_enc[10]; // @[OneHot.scala:83:30] wire _GEN_35 = _GEN_23 & to_q_oh_enc[11]; // @[OneHot.scala:83:30] wire _GEN_36 = _GEN_23 & to_q_oh_enc[12]; // @[OneHot.scala:83:30] wire _GEN_37 = _GEN_23 & to_q_oh_enc[13]; // @[OneHot.scala:83:30] wire _GEN_38 = _GEN_23 & to_q_oh_enc[14]; // @[OneHot.scala:83:30] wire _GEN_39 = _GEN_23 & to_q_oh_enc[15]; // @[OneHot.scala:83:30] wire _GEN_40 = _GEN_23 & to_q_oh_enc[16]; // @[OneHot.scala:83:30] wire _GEN_41 = _GEN_23 & to_q_oh_enc[17]; // @[OneHot.scala:83:30] wire _GEN_42 = _GEN_23 & to_q_oh_enc[18]; // @[OneHot.scala:83:30] wire _GEN_43 = _GEN_23 & to_q_oh_enc[19]; // @[OneHot.scala:83:30] wire _GEN_44 = _GEN_23 & to_q_oh_enc[20]; // @[OneHot.scala:83:30] wire _GEN_45 = _GEN_23 & to_q_oh_enc[21]; // @[OneHot.scala:83:30] wire [3:0] _tails_T_133 = _GEN[io_enq_0_bits_virt_channel_id] == ({1'h0, {1'h0, {2{_tails_T_84}}} | {3{_tails_T_85}}} | (_tails_T_86 ? 4'hB : 4'h0) | {4{_tails_T_87}}) ? {_tails_T_86, _tails_T_85, 2'h0} | (_tails_T_87 ? 4'hC : 4'h0) : _GEN[io_enq_0_bits_virt_channel_id] + 4'h1; // @[Mux.scala:30:73, :32:36] wire [14:0] _to_q_T_2 = {10'h0, to_q_oh_enc[21:17]} | to_q_oh_enc[15:1]; // @[OneHot.scala:31:18, :32:28] wire [6:0] _to_q_T_4 = _to_q_T_2[14:8] | _to_q_T_2[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _to_q_T_6 = _to_q_T_4[6:4] | _to_q_T_4[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire _to_q_T_8 = _to_q_T_6[2] | _to_q_T_6[0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [4:0] to_q = {|(to_q_oh_enc[21:16]), |(_to_q_T_2[14:7]), |(_to_q_T_4[6:3]), |(_to_q_T_6[2:1]), _to_q_T_8}; // @[OneHot.scala:30:18, :32:{10,14,28}] wire [3:0] _heads_T_89 = head == ({1'h0, {1'h0, {2{to_q_oh_enc[18]}}} | {3{to_q_oh_enc[19]}}} | (to_q_oh_enc[20] ? 4'hB : 4'h0) | {4{to_q_oh_enc[21]}}) ? {to_q_oh_enc[20:19], 2'h0} | (to_q_oh_enc[21] ? 4'hC : 4'h0) : head + 4'h1; // @[OneHot.scala:83:30] always @(posedge clock) begin // @[InputUnit.scala:49:7] if (reset) begin // @[InputUnit.scala:49:7] heads_0 <= 4'h0; // @[InputUnit.scala:86:24] heads_1 <= 4'h0; // @[InputUnit.scala:86:24] heads_2 <= 4'h0; // @[InputUnit.scala:86:24] heads_3 <= 4'h0; // @[InputUnit.scala:86:24] heads_4 <= 4'h0; // @[InputUnit.scala:86:24] heads_5 <= 4'h0; // @[InputUnit.scala:86:24] heads_6 <= 4'h0; // @[InputUnit.scala:86:24] heads_7 <= 4'h0; // @[InputUnit.scala:86:24] heads_8 <= 4'h0; // @[InputUnit.scala:86:24] heads_9 <= 4'h0; // @[InputUnit.scala:86:24] heads_10 <= 4'h0; // @[InputUnit.scala:86:24] heads_11 <= 4'h0; // @[InputUnit.scala:86:24] heads_12 <= 4'h0; // @[InputUnit.scala:86:24] heads_13 <= 4'h0; // @[InputUnit.scala:86:24] heads_14 <= 4'h0; // @[InputUnit.scala:86:24] heads_15 <= 4'h0; // @[InputUnit.scala:86:24] heads_16 <= 4'h0; // @[InputUnit.scala:86:24] heads_17 <= 4'h0; // @[InputUnit.scala:86:24] heads_18 <= 4'h0; // @[InputUnit.scala:86:24] heads_19 <= 4'h4; // @[InputUnit.scala:86:24] heads_20 <= 4'h8; // @[InputUnit.scala:86:24] heads_21 <= 4'hC; // @[InputUnit.scala:86:24] tails_0 <= 4'h0; // @[InputUnit.scala:87:24] tails_1 <= 4'h0; // @[InputUnit.scala:87:24] tails_2 <= 4'h0; // @[InputUnit.scala:87:24] tails_3 <= 4'h0; // @[InputUnit.scala:87:24] tails_4 <= 4'h0; // @[InputUnit.scala:87:24] tails_5 <= 4'h0; // @[InputUnit.scala:87:24] tails_6 <= 4'h0; // @[InputUnit.scala:87:24] tails_7 <= 4'h0; // @[InputUnit.scala:87:24] tails_8 <= 4'h0; // @[InputUnit.scala:87:24] tails_9 <= 4'h0; // @[InputUnit.scala:87:24] tails_10 <= 4'h0; // @[InputUnit.scala:87:24] tails_11 <= 4'h0; // @[InputUnit.scala:87:24] tails_12 <= 4'h0; // @[InputUnit.scala:87:24] tails_13 <= 4'h0; // @[InputUnit.scala:87:24] tails_14 <= 4'h0; // @[InputUnit.scala:87:24] tails_15 <= 4'h0; // @[InputUnit.scala:87:24] tails_16 <= 4'h0; // @[InputUnit.scala:87:24] tails_17 <= 4'h0; // @[InputUnit.scala:87:24] tails_18 <= 4'h0; // @[InputUnit.scala:87:24] tails_19 <= 4'h4; // @[InputUnit.scala:87:24] tails_20 <= 4'h8; // @[InputUnit.scala:87:24] tails_21 <= 4'hC; // @[InputUnit.scala:87:24] end else begin // @[InputUnit.scala:49:7] if (_GEN_23 & {to_q_oh_enc[21:16], |(_to_q_T_2[14:7]), |(_to_q_T_4[6:3]), |(_to_q_T_6[2:1]), _to_q_T_8} == 10'h0) // @[OneHot.scala:30:18, :32:{10,14,28}] heads_0 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h1) // @[OneHot.scala:32:10] heads_1 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h2) // @[OneHot.scala:32:10] heads_2 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h3) // @[OneHot.scala:32:10] heads_3 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h4) // @[OneHot.scala:32:10] heads_4 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h5) // @[OneHot.scala:32:10] heads_5 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h6) // @[OneHot.scala:32:10] heads_6 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h7) // @[OneHot.scala:32:10] heads_7 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h8) // @[OneHot.scala:32:10] heads_8 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h9) // @[OneHot.scala:32:10] heads_9 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hA) // @[OneHot.scala:32:10] heads_10 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hB) // @[OneHot.scala:32:10] heads_11 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hC) // @[OneHot.scala:32:10] heads_12 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hD) // @[OneHot.scala:32:10] heads_13 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hE) // @[OneHot.scala:32:10] heads_14 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'hF) // @[OneHot.scala:32:10] heads_15 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h10) // @[OneHot.scala:32:10] heads_16 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h11) // @[OneHot.scala:32:10] heads_17 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h12) // @[OneHot.scala:32:10] heads_18 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h13) // @[OneHot.scala:32:10] heads_19 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h14) // @[OneHot.scala:32:10] heads_20 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (_GEN_23 & to_q == 5'h15) // @[OneHot.scala:32:10] heads_21 <= _heads_T_89; // @[InputUnit.scala:86:24, :122:27] if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_0 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_1 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_2 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_3) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_3 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_4) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_4 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_5) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_5 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_6) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_6 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_7) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_7 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_8) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_8 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_9) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_9 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_10) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_10 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_11) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_11 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_12) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_12 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_13) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_13 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_14) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_14 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_15) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_15 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_16) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_16 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_17) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_17 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_18) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_18 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_19) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_19 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_20) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_20 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] if (mem_MPORT_en & _GEN_21) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45] tails_21 <= _tails_T_133; // @[InputUnit.scala:87:24, :103:51] end always @(posedge)